d06aa2e4365b20de2baece7fe6ad02f77cc6194d
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
, Elaboratable
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOpIn
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 from singlepipe
import (ControlBase
, StageChain
, SimpleHandshake
,
13 PassThroughStage
, PrevControl
)
14 from multipipe
import CombMuxOutPipe
15 from multipipe
import PriorityCombMuxInPipe
17 from fpbase
import FPState
20 class FPGetOpMod(Elaboratable
):
21 def __init__(self
, width
):
22 self
.in_op
= FPOpIn(width
)
23 self
.out_op
= Signal(width
)
24 self
.out_decode
= Signal(reset_less
=True)
26 def elaborate(self
, platform
):
28 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ready_o
) & \
29 (self
.in_op
.i_valid_test
))
30 m
.submodules
.get_op_in
= self
.in_op
31 #m.submodules.get_op_out = self.out_op
32 with m
.If(self
.out_decode
):
34 self
.out_op
.eq(self
.in_op
.v
),
39 class FPGetOp(FPState
):
43 def __init__(self
, in_state
, out_state
, in_op
, width
):
44 FPState
.__init
__(self
, in_state
)
45 self
.out_state
= out_state
46 self
.mod
= FPGetOpMod(width
)
48 self
.out_op
= Signal(width
)
49 self
.out_decode
= Signal(reset_less
=True)
51 def setup(self
, m
, in_op
):
52 """ links module to inputs and outputs
54 setattr(m
.submodules
, self
.state_from
, self
.mod
)
55 m
.d
.comb
+= self
.mod
.in_op
.eq(in_op
)
56 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
59 with m
.If(self
.out_decode
):
60 m
.next
= self
.out_state
62 self
.in_op
.ready_o
.eq(0),
63 self
.out_op
.eq(self
.mod
.out_op
)
66 m
.d
.sync
+= self
.in_op
.ready_o
.eq(1)
71 def __init__(self
, width
, id_wid
, m_extra
=True):
72 self
.a
= FPNumBase(width
, m_extra
)
73 self
.b
= FPNumBase(width
, m_extra
)
74 self
.mid
= Signal(id_wid
, reset_less
=True)
77 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
80 return [self
.a
, self
.b
, self
.mid
]
85 def __init__(self
, width
, id_wid
):
88 self
.a
= Signal(width
)
89 self
.b
= Signal(width
)
90 self
.mid
= Signal(id_wid
, reset_less
=True)
93 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
), self
.mid
.eq(i
.mid
)]
96 return [self
.a
, self
.b
, self
.mid
]
99 class FPGet2OpMod(PrevControl
):
100 def __init__(self
, width
, id_wid
):
101 PrevControl
.__init
__(self
)
104 self
.i_data
= self
.ispec()
106 self
.o
= self
.ospec()
109 return FPADDBaseData(self
.width
, self
.id_wid
)
112 return FPADDBaseData(self
.width
, self
.id_wid
)
114 def process(self
, i
):
117 def elaborate(self
, platform
):
118 m
= PrevControl
.elaborate(self
, platform
)
119 with m
.If(self
.trigger
):
121 self
.o
.eq(self
.i_data
),
126 class FPGet2Op(FPState
):
130 def __init__(self
, in_state
, out_state
, width
, id_wid
):
131 FPState
.__init
__(self
, in_state
)
132 self
.out_state
= out_state
133 self
.mod
= FPGet2OpMod(width
, id_wid
)
134 self
.o
= self
.ospec()
135 self
.in_stb
= Signal(reset_less
=True)
136 self
.out_ack
= Signal(reset_less
=True)
137 self
.out_decode
= Signal(reset_less
=True)
140 return self
.mod
.ispec()
143 return self
.mod
.ospec()
145 def trigger_setup(self
, m
, in_stb
, in_ack
):
148 m
.d
.comb
+= self
.mod
.i_valid
.eq(in_stb
)
149 m
.d
.comb
+= in_ack
.eq(self
.mod
.ready_o
)
151 def setup(self
, m
, i
):
152 """ links module to inputs and outputs
154 m
.submodules
.get_ops
= self
.mod
155 m
.d
.comb
+= self
.mod
.i
.eq(i
)
156 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ready_o
)
157 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
159 def process(self
, i
):
163 with m
.If(self
.out_decode
):
164 m
.next
= self
.out_state
166 self
.mod
.ready_o
.eq(0),
167 self
.o
.eq(self
.mod
.o
),
170 m
.d
.sync
+= self
.mod
.ready_o
.eq(1)