0d2f9ae05bd261954b01cece41623cb30a9a8b65
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 #from fpbase import FPNumShiftMultiRight
15 class FPState(FPBase
):
16 def __init__(self
, state_from
):
17 self
.state_from
= state_from
19 def set_inputs(self
, inputs
):
21 for k
,v
in inputs
.items():
24 def set_outputs(self
, outputs
):
25 self
.outputs
= outputs
26 for k
,v
in outputs
.items():
30 class FPGetSyncOpsMod
:
31 def __init__(self
, width
, num_ops
=2):
33 self
.num_ops
= num_ops
36 for i
in range(num_ops
):
37 inops
.append(Signal(width
, reset_less
=True))
38 outops
.append(Signal(width
, reset_less
=True))
41 self
.stb
= Signal(num_ops
)
43 self
.ready
= Signal(reset_less
=True)
44 self
.out_decode
= Signal(reset_less
=True)
46 def elaborate(self
, platform
):
48 m
.d
.comb
+= self
.ready
.eq(self
.stb
== Const(-1, (self
.num_ops
, False)))
49 m
.d
.comb
+= self
.out_decode
.eq(self
.ack
& self
.ready
)
50 with m
.If(self
.out_decode
):
51 for i
in range(self
.num_ops
):
53 self
.out_op
[i
].eq(self
.in_op
[i
]),
58 return self
.in_op
+ self
.out_op
+ [self
.stb
, self
.ack
]
62 def __init__(self
, width
, num_ops
):
63 Trigger
.__init
__(self
)
65 self
.num_ops
= num_ops
68 for i
in range(num_ops
):
69 res
.append(Signal(width
))
74 for i
in range(self
.num_ops
):
82 def __init__(self
, width
, num_ops
=2, num_rows
=4):
84 self
.num_ops
= num_ops
85 self
.num_rows
= num_rows
86 self
.mmax
= int(log(self
.num_rows
) / log(2))
88 self
.mid
= Signal(self
.mmax
, reset_less
=True) # multiplex id
89 for i
in range(num_rows
):
90 self
.rs
.append(FPGetSyncOpsMod(width
, num_ops
))
91 self
.rs
= Array(self
.rs
)
93 self
.out_op
= FPOps(width
, num_ops
)
95 def elaborate(self
, platform
):
98 pe
= PriorityEncoder(self
.num_rows
)
99 m
.submodules
.selector
= pe
100 m
.submodules
.out_op
= self
.out_op
101 m
.submodules
+= self
.rs
103 # connect priority encoder
105 for i
in range(self
.num_rows
):
106 in_ready
.append(self
.rs
[i
].ready
)
107 m
.d
.comb
+= pe
.i
.eq(Cat(*in_ready
))
109 active
= Signal(reset_less
=True)
110 out_en
= Signal(reset_less
=True)
111 m
.d
.comb
+= active
.eq(~pe
.n
) # encoder active
112 m
.d
.comb
+= out_en
.eq(active
& self
.out_op
.trigger
)
114 # encoder active: ack relevant input, record MID, pass output
117 m
.d
.sync
+= self
.mid
.eq(pe
.o
)
118 m
.d
.sync
+= rs
.ack
.eq(0)
119 m
.d
.sync
+= self
.out_op
.stb
.eq(0)
120 for j
in range(self
.num_ops
):
121 m
.d
.sync
+= self
.out_op
.v
[j
].eq(rs
.out_op
[j
])
123 m
.d
.sync
+= self
.out_op
.stb
.eq(1)
124 # acks all default to zero
125 for i
in range(self
.num_rows
):
126 m
.d
.sync
+= self
.rs
[i
].ack
.eq(1)
132 for i
in range(self
.num_rows
):
134 res
+= inop
.in_op
+ [inop
.stb
]
135 return self
.out_op
.ports() + res
+ [self
.mid
]
139 def __init__(self
, width
):
140 self
.in_op
= FPOp(width
)
141 self
.out_op
= Signal(width
)
142 self
.out_decode
= Signal(reset_less
=True)
144 def elaborate(self
, platform
):
146 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
147 m
.submodules
.get_op_in
= self
.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m
.If(self
.out_decode
):
151 self
.out_op
.eq(self
.in_op
.v
),
156 class FPGetOp(FPState
):
160 def __init__(self
, in_state
, out_state
, in_op
, width
):
161 FPState
.__init
__(self
, in_state
)
162 self
.out_state
= out_state
163 self
.mod
= FPGetOpMod(width
)
165 self
.out_op
= Signal(width
)
166 self
.out_decode
= Signal(reset_less
=True)
168 def setup(self
, m
, in_op
):
169 """ links module to inputs and outputs
171 setattr(m
.submodules
, self
.state_from
, self
.mod
)
172 m
.d
.comb
+= self
.mod
.in_op
.eq(in_op
)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.out_decode
)
177 with m
.If(self
.out_decode
):
178 m
.next
= self
.out_state
180 self
.in_op
.ack
.eq(0),
181 self
.out_op
.eq(self
.mod
.out_op
)
184 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
187 class FPGet2OpMod(Trigger
):
188 def __init__(self
, width
):
189 Trigger
.__init
__(self
)
190 self
.in_op1
= Signal(width
, reset_less
=True)
191 self
.in_op2
= Signal(width
, reset_less
=True)
192 self
.out_op1
= FPNumIn(None, width
)
193 self
.out_op2
= FPNumIn(None, width
)
195 def elaborate(self
, platform
):
196 m
= Trigger
.elaborate(self
, platform
)
197 #m.submodules.get_op_in = self.in_op
198 m
.submodules
.get_op1_out
= self
.out_op1
199 m
.submodules
.get_op2_out
= self
.out_op2
200 with m
.If(self
.trigger
):
202 self
.out_op1
.decode(self
.in_op1
),
203 self
.out_op2
.decode(self
.in_op2
),
208 class FPGet2Op(FPState
):
212 def __init__(self
, in_state
, out_state
, in_op1
, in_op2
, width
):
213 FPState
.__init
__(self
, in_state
)
214 self
.out_state
= out_state
215 self
.mod
= FPGet2OpMod(width
)
218 self
.out_op1
= FPNumIn(None, width
)
219 self
.out_op2
= FPNumIn(None, width
)
220 self
.in_stb
= Signal(reset_less
=True)
221 self
.out_ack
= Signal(reset_less
=True)
222 self
.out_decode
= Signal(reset_less
=True)
224 def setup(self
, m
, in_op1
, in_op2
, in_stb
, in_ack
):
225 """ links module to inputs and outputs
227 m
.submodules
.get_ops
= self
.mod
228 m
.d
.comb
+= self
.mod
.in_op1
.eq(in_op1
)
229 m
.d
.comb
+= self
.mod
.in_op2
.eq(in_op2
)
230 m
.d
.comb
+= self
.mod
.stb
.eq(in_stb
)
231 m
.d
.comb
+= self
.out_ack
.eq(self
.mod
.ack
)
232 m
.d
.comb
+= self
.out_decode
.eq(self
.mod
.trigger
)
233 m
.d
.comb
+= in_ack
.eq(self
.mod
.ack
)
236 with m
.If(self
.out_decode
):
237 m
.next
= self
.out_state
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self
.out_op1
.eq(self
.mod
.out_op1
),
243 self
.out_op2
.eq(self
.mod
.out_op2
)
246 m
.d
.sync
+= self
.mod
.ack
.eq(1)
250 def __init__(self
, width
, m_extra
=True):
251 self
.a
= FPNumBase(width
, m_extra
)
252 self
.b
= FPNumBase(width
, m_extra
)
255 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
)]
258 class FPAddSpecialCasesMod
:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
264 def __init__(self
, width
):
266 self
.i
= self
.ispec()
267 self
.out_z
= self
.ospec()
268 self
.out_do_z
= Signal(reset_less
=True)
271 return FPNumBase2Ops(self
.width
)
274 return FPNumOut(self
.width
, False)
276 def setup(self
, m
, in_a
, in_b
, out_do_z
):
277 """ links module to inputs and outputs
279 m
.submodules
.specialcases
= self
280 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
281 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
282 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
284 def elaborate(self
, platform
):
287 m
.submodules
.sc_in_a
= self
.i
.a
288 m
.submodules
.sc_in_b
= self
.i
.b
289 m
.submodules
.sc_out_z
= self
.out_z
292 m
.d
.comb
+= s_nomatch
.eq(self
.i
.a
.s
!= self
.i
.b
.s
)
295 m
.d
.comb
+= m_match
.eq(self
.i
.a
.m
== self
.i
.b
.m
)
297 # if a is NaN or b is NaN return NaN
298 with m
.If(self
.i
.a
.is_nan | self
.i
.b
.is_nan
):
299 m
.d
.comb
+= self
.out_do_z
.eq(1)
300 m
.d
.comb
+= self
.out_z
.nan(0)
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
325 # if a is inf return inf (or NaN)
326 with m
.Elif(self
.i
.a
.is_inf
):
327 m
.d
.comb
+= self
.out_do_z
.eq(1)
328 m
.d
.comb
+= self
.out_z
.inf(self
.i
.a
.s
)
329 # if a is inf and signs don't match return NaN
330 with m
.If(self
.i
.b
.exp_128
& s_nomatch
):
331 m
.d
.comb
+= self
.out_z
.nan(0)
333 # if b is inf return inf
334 with m
.Elif(self
.i
.b
.is_inf
):
335 m
.d
.comb
+= self
.out_do_z
.eq(1)
336 m
.d
.comb
+= self
.out_z
.inf(self
.i
.b
.s
)
338 # if a is zero and b zero return signed-a/b
339 with m
.Elif(self
.i
.a
.is_zero
& self
.i
.b
.is_zero
):
340 m
.d
.comb
+= self
.out_do_z
.eq(1)
341 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
& self
.i
.b
.s
,
345 # if a is zero return b
346 with m
.Elif(self
.i
.a
.is_zero
):
347 m
.d
.comb
+= self
.out_do_z
.eq(1)
348 m
.d
.comb
+= self
.out_z
.create(self
.i
.b
.s
, self
.i
.b
.e
,
351 # if b is zero return a
352 with m
.Elif(self
.i
.b
.is_zero
):
353 m
.d
.comb
+= self
.out_do_z
.eq(1)
354 m
.d
.comb
+= self
.out_z
.create(self
.i
.a
.s
, self
.i
.a
.e
,
357 # if a equal to -b return zero (+ve zero)
358 with m
.Elif(s_nomatch
& m_match
& (self
.i
.a
.e
== self
.i
.b
.e
)):
359 m
.d
.comb
+= self
.out_do_z
.eq(1)
360 m
.d
.comb
+= self
.out_z
.zero(0)
362 # Denormalised Number checks
364 m
.d
.comb
+= self
.out_do_z
.eq(0)
370 def __init__(self
, id_wid
):
373 self
.in_mid
= Signal(id_wid
, reset_less
=True)
374 self
.out_mid
= Signal(id_wid
, reset_less
=True)
380 if self
.id_wid
is not None:
381 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
384 class FPAddSpecialCases(FPState
, FPID
):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
390 def __init__(self
, width
, id_wid
):
391 FPState
.__init
__(self
, "special_cases")
392 FPID
.__init
__(self
, id_wid
)
393 self
.mod
= FPAddSpecialCasesMod(width
)
394 self
.out_z
= self
.mod
.ospec()
395 self
.out_do_z
= Signal(reset_less
=True)
397 def setup(self
, m
, in_a
, in_b
, in_mid
):
398 """ links module to inputs and outputs
400 self
.mod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
401 if self
.in_mid
is not None:
402 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
406 with m
.If(self
.out_do_z
):
407 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
410 m
.next
= "denormalise"
413 class FPAddSpecialCasesDeNorm(FPState
, FPID
):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
419 def __init__(self
, width
, id_wid
):
420 FPState
.__init
__(self
, "special_cases")
421 FPID
.__init
__(self
, id_wid
)
422 self
.smod
= FPAddSpecialCasesMod(width
)
423 self
.out_z
= self
.smod
.ospec()
424 self
.out_do_z
= Signal(reset_less
=True)
426 self
.dmod
= FPAddDeNormMod(width
)
427 self
.o
= self
.dmod
.ospec()
429 def setup(self
, m
, in_a
, in_b
, in_mid
):
430 """ links module to inputs and outputs
432 self
.smod
.setup(m
, in_a
, in_b
, self
.out_do_z
)
433 self
.dmod
.setup(m
, in_a
, in_b
)
434 if self
.in_mid
is not None:
435 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
439 with m
.If(self
.out_do_z
):
440 m
.d
.sync
+= self
.out_z
.v
.eq(self
.smod
.out_z
.v
) # only take output
444 m
.d
.sync
+= self
.o
.a
.eq(self
.dmod
.o
.a
)
445 m
.d
.sync
+= self
.o
.b
.eq(self
.dmod
.o
.b
)
448 class FPAddDeNormMod(FPState
):
450 def __init__(self
, width
):
452 self
.i
= self
.ispec()
453 self
.o
= self
.ospec()
456 return FPNumBase2Ops(self
.width
)
459 return FPNumBase2Ops(self
.width
)
461 def setup(self
, m
, in_a
, in_b
):
462 """ links module to inputs and outputs
464 m
.submodules
.denormalise
= self
465 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
466 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
468 def elaborate(self
, platform
):
470 m
.submodules
.denorm_in_a
= self
.i
.a
471 m
.submodules
.denorm_in_b
= self
.i
.b
472 m
.submodules
.denorm_out_a
= self
.o
.a
473 m
.submodules
.denorm_out_b
= self
.o
.b
474 # hmmm, don't like repeating identical code
475 m
.d
.comb
+= self
.o
.a
.eq(self
.i
.a
)
476 with m
.If(self
.i
.a
.exp_n127
):
477 m
.d
.comb
+= self
.o
.a
.e
.eq(self
.i
.a
.N126
) # limit a exponent
479 m
.d
.comb
+= self
.o
.a
.m
[-1].eq(1) # set top mantissa bit
481 m
.d
.comb
+= self
.o
.b
.eq(self
.i
.b
)
482 with m
.If(self
.i
.b
.exp_n127
):
483 m
.d
.comb
+= self
.o
.b
.e
.eq(self
.i
.b
.N126
) # limit a exponent
485 m
.d
.comb
+= self
.o
.b
.m
[-1].eq(1) # set top mantissa bit
490 class FPAddDeNorm(FPState
, FPID
):
492 def __init__(self
, width
, id_wid
):
493 FPState
.__init
__(self
, "denormalise")
494 FPID
.__init
__(self
, id_wid
)
495 self
.mod
= FPAddDeNormMod(width
)
496 self
.out_a
= FPNumBase(width
)
497 self
.out_b
= FPNumBase(width
)
499 def setup(self
, m
, in_a
, in_b
, in_mid
):
500 """ links module to inputs and outputs
502 self
.mod
.setup(m
, in_a
, in_b
)
503 if self
.in_mid
is not None:
504 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
508 # Denormalised Number checks
510 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
511 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
514 class FPAddAlignMultiMod(FPState
):
516 def __init__(self
, width
):
517 self
.in_a
= FPNumBase(width
)
518 self
.in_b
= FPNumBase(width
)
519 self
.out_a
= FPNumIn(None, width
)
520 self
.out_b
= FPNumIn(None, width
)
521 self
.exp_eq
= Signal(reset_less
=True)
523 def elaborate(self
, platform
):
524 # This one however (single-cycle) will do the shift
529 m
.submodules
.align_in_a
= self
.in_a
530 m
.submodules
.align_in_b
= self
.in_b
531 m
.submodules
.align_out_a
= self
.out_a
532 m
.submodules
.align_out_b
= self
.out_b
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
537 # exponent of a greater than b: shift b down
538 m
.d
.comb
+= self
.exp_eq
.eq(0)
539 m
.d
.comb
+= self
.out_a
.eq(self
.in_a
)
540 m
.d
.comb
+= self
.out_b
.eq(self
.in_b
)
541 agtb
= Signal(reset_less
=True)
542 altb
= Signal(reset_less
=True)
543 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
544 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
546 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
547 # exponent of b greater than a: shift a down
549 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
550 # exponents equal: move to next stage.
552 m
.d
.comb
+= self
.exp_eq
.eq(1)
556 class FPAddAlignMulti(FPState
, FPID
):
558 def __init__(self
, width
, id_wid
):
559 FPID
.__init
__(self
, id_wid
)
560 FPState
.__init
__(self
, "align")
561 self
.mod
= FPAddAlignMultiMod(width
)
562 self
.out_a
= FPNumIn(None, width
)
563 self
.out_b
= FPNumIn(None, width
)
564 self
.exp_eq
= Signal(reset_less
=True)
566 def setup(self
, m
, in_a
, in_b
, in_mid
):
567 """ links module to inputs and outputs
569 m
.submodules
.align
= self
.mod
570 m
.d
.comb
+= self
.mod
.in_a
.eq(in_a
)
571 m
.d
.comb
+= self
.mod
.in_b
.eq(in_b
)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m
.d
.comb
+= self
.exp_eq
.eq(self
.mod
.exp_eq
)
575 if self
.in_mid
is not None:
576 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
580 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
581 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
582 with m
.If(self
.exp_eq
):
588 def __init__(self
, width
):
589 self
.a
= FPNumIn(None, width
)
590 self
.b
= FPNumIn(None, width
)
593 return [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
)]
596 class FPAddAlignSingleMod
:
598 def __init__(self
, width
):
600 self
.i
= self
.ispec()
601 self
.o
= self
.ospec()
604 return FPNumBase2Ops(self
.width
)
607 return FPNumIn2Ops(self
.width
)
609 def setup(self
, m
, in_a
, in_b
):
610 """ links module to inputs and outputs
612 m
.submodules
.align
= self
613 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
614 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
616 def elaborate(self
, platform
):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
627 m
.submodules
.align_in_a
= self
.i
.a
628 m
.submodules
.align_in_b
= self
.i
.b
629 m
.submodules
.align_out_a
= self
.o
.a
630 m
.submodules
.align_out_b
= self
.o
.b
632 # temporary (muxed) input and output to be shifted
633 t_inp
= FPNumBase(self
.width
)
634 t_out
= FPNumIn(None, self
.width
)
635 espec
= (len(self
.i
.a
.e
), True)
636 msr
= MultiShiftRMerge(self
.i
.a
.m_width
, espec
)
637 m
.submodules
.align_t_in
= t_inp
638 m
.submodules
.align_t_out
= t_out
639 m
.submodules
.multishift_r
= msr
641 ediff
= Signal(espec
, reset_less
=True)
642 ediffr
= Signal(espec
, reset_less
=True)
643 tdiff
= Signal(espec
, reset_less
=True)
644 elz
= Signal(reset_less
=True)
645 egz
= Signal(reset_less
=True)
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m
.d
.comb
+= msr
.inp
.eq(t_inp
.m
)
649 m
.d
.comb
+= msr
.diff
.eq(tdiff
)
650 m
.d
.comb
+= t_out
.m
.eq(msr
.m
)
651 m
.d
.comb
+= t_out
.e
.eq(t_inp
.e
+ tdiff
)
652 m
.d
.comb
+= t_out
.s
.eq(t_inp
.s
)
654 m
.d
.comb
+= ediff
.eq(self
.i
.a
.e
- self
.i
.b
.e
)
655 m
.d
.comb
+= ediffr
.eq(self
.i
.b
.e
- self
.i
.a
.e
)
656 m
.d
.comb
+= elz
.eq(self
.i
.a
.e
< self
.i
.b
.e
)
657 m
.d
.comb
+= egz
.eq(self
.i
.a
.e
> self
.i
.b
.e
)
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m
.d
.comb
+= self
.o
.a
.eq(self
.i
.a
)
661 m
.d
.comb
+= self
.o
.b
.eq(self
.i
.b
)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
666 m
.d
.comb
+= [t_inp
.eq(self
.i
.b
),
669 self
.o
.b
.s
.eq(self
.i
.b
.s
), # whoops forgot sign
671 # exponent of b greater than a: shift a down
673 m
.d
.comb
+= [t_inp
.eq(self
.i
.a
),
676 self
.o
.a
.s
.eq(self
.i
.a
.s
), # whoops forgot sign
681 class FPAddAlignSingle(FPState
, FPID
):
683 def __init__(self
, width
, id_wid
):
684 FPState
.__init
__(self
, "align")
685 FPID
.__init
__(self
, id_wid
)
686 self
.mod
= FPAddAlignSingleMod(width
)
687 self
.out_a
= FPNumIn(None, width
)
688 self
.out_b
= FPNumIn(None, width
)
690 def setup(self
, m
, in_a
, in_b
, in_mid
):
691 """ links module to inputs and outputs
693 self
.mod
.setup(m
, in_a
, in_b
)
694 if self
.in_mid
is not None:
695 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
699 # NOTE: could be done as comb
700 m
.d
.sync
+= self
.out_a
.eq(self
.mod
.out_a
)
701 m
.d
.sync
+= self
.out_b
.eq(self
.mod
.out_b
)
705 class FPAddAlignSingleAdd(FPState
, FPID
):
707 def __init__(self
, width
, id_wid
):
708 FPState
.__init
__(self
, "align")
709 FPID
.__init
__(self
, id_wid
)
710 self
.mod
= FPAddAlignSingleMod(width
)
711 self
.o
= self
.mod
.ospec()
713 self
.a0mod
= FPAddStage0Mod(width
)
714 self
.a0_out_z
= FPNumBase(width
, False)
715 self
.out_tot
= Signal(self
.a0_out_z
.m_width
+ 4, reset_less
=True)
716 self
.a0_out_z
= FPNumBase(width
, False)
718 self
.a1mod
= FPAddStage1Mod(width
)
719 self
.out_z
= FPNumBase(width
, False)
720 self
.out_of
= Overflow()
722 def setup(self
, m
, in_a
, in_b
, in_mid
):
723 """ links module to inputs and outputs
725 self
.mod
.setup(m
, in_a
, in_b
)
726 m
.d
.comb
+= self
.o
.eq(self
.mod
.o
)
728 self
.a0mod
.setup(m
, self
.o
.a
, self
.o
.b
)
729 m
.d
.comb
+= self
.a0_out_z
.eq(self
.a0mod
.o
.z
)
730 m
.d
.comb
+= self
.out_tot
.eq(self
.a0mod
.o
.tot
)
732 self
.a1mod
.setup(m
, self
.out_tot
, self
.a0_out_z
)
734 if self
.in_mid
is not None:
735 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
739 m
.d
.sync
+= self
.out_of
.eq(self
.a1mod
.o
.of
)
740 m
.d
.sync
+= self
.out_z
.eq(self
.a1mod
.o
.z
)
741 m
.next
= "normalise_1"
744 class FPAddStage0Data
:
746 def __init__(self
, width
):
747 self
.z
= FPNumBase(width
, False)
748 self
.tot
= Signal(self
.z
.m_width
+ 4, reset_less
=True)
751 return [self
.z
.eq(i
.z
), self
.tot
.eq(i
.tot
)]
754 class FPAddStage0Mod
:
756 def __init__(self
, width
):
758 self
.i
= self
.ispec()
759 self
.o
= self
.ospec()
762 return FPNumBase2Ops(self
.width
)
765 return FPAddStage0Data(self
.width
)
767 def setup(self
, m
, in_a
, in_b
):
768 """ links module to inputs and outputs
770 m
.submodules
.add0
= self
771 m
.d
.comb
+= self
.i
.a
.eq(in_a
)
772 m
.d
.comb
+= self
.i
.b
.eq(in_b
)
774 def elaborate(self
, platform
):
776 m
.submodules
.add0_in_a
= self
.i
.a
777 m
.submodules
.add0_in_b
= self
.i
.b
778 m
.submodules
.add0_out_z
= self
.o
.z
780 m
.d
.comb
+= self
.o
.z
.e
.eq(self
.i
.a
.e
)
782 # store intermediate tests (and zero-extended mantissas)
783 seq
= Signal(reset_less
=True)
784 mge
= Signal(reset_less
=True)
785 am0
= Signal(len(self
.i
.a
.m
)+1, reset_less
=True)
786 bm0
= Signal(len(self
.i
.b
.m
)+1, reset_less
=True)
787 m
.d
.comb
+= [seq
.eq(self
.i
.a
.s
== self
.i
.b
.s
),
788 mge
.eq(self
.i
.a
.m
>= self
.i
.b
.m
),
789 am0
.eq(Cat(self
.i
.a
.m
, 0)),
790 bm0
.eq(Cat(self
.i
.b
.m
, 0))
792 # same-sign (both negative or both positive) add mantissas
795 self
.o
.tot
.eq(am0
+ bm0
),
796 self
.o
.z
.s
.eq(self
.i
.a
.s
)
798 # a mantissa greater than b, use a
801 self
.o
.tot
.eq(am0
- bm0
),
802 self
.o
.z
.s
.eq(self
.i
.a
.s
)
804 # b mantissa greater than a, use b
807 self
.o
.tot
.eq(bm0
- am0
),
808 self
.o
.z
.s
.eq(self
.i
.b
.s
)
813 class FPAddStage0(FPState
, FPID
):
814 """ First stage of add. covers same-sign (add) and subtract
815 special-casing when mantissas are greater or equal, to
816 give greatest accuracy.
819 def __init__(self
, width
, id_wid
):
820 FPState
.__init
__(self
, "add_0")
821 FPID
.__init
__(self
, id_wid
)
822 self
.mod
= FPAddStage0Mod(width
)
823 self
.o
= self
.mod
.ospec()
825 def setup(self
, m
, in_a
, in_b
, in_mid
):
826 """ links module to inputs and outputs
828 self
.mod
.setup(m
, in_a
, in_b
)
829 if self
.in_mid
is not None:
830 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
834 # NOTE: these could be done as combinatorial (merge add0+add1)
835 m
.d
.sync
+= self
.o
.eq(self
.mod
.o
)
839 class FPAddStage1Data
:
841 def __init__(self
, width
):
842 self
.z
= FPNumBase(width
, False)
846 return [self
.z
.eq(i
.z
), self
.of
.eq(i
.of
)]
850 class FPAddStage1Mod(FPState
):
851 """ Second stage of add: preparation for normalisation.
852 detects when tot sum is too big (tot[27] is kinda a carry bit)
855 def __init__(self
, width
):
857 self
.i
= self
.ispec()
858 self
.o
= self
.ospec()
861 return FPAddStage0Data(self
.width
)
864 return FPAddStage1Data(self
.width
)
866 def setup(self
, m
, in_tot
, in_z
):
867 """ links module to inputs and outputs
869 m
.submodules
.add1
= self
870 m
.submodules
.add1_out_overflow
= self
.o
.of
872 m
.d
.comb
+= self
.i
.z
.eq(in_z
)
873 m
.d
.comb
+= self
.i
.tot
.eq(in_tot
)
875 def elaborate(self
, platform
):
877 #m.submodules.norm1_in_overflow = self.in_of
878 #m.submodules.norm1_out_overflow = self.out_of
879 #m.submodules.norm1_in_z = self.in_z
880 #m.submodules.norm1_out_z = self.out_z
881 m
.d
.comb
+= self
.o
.z
.eq(self
.i
.z
)
882 # tot[-1] (MSB) gets set when the sum overflows. shift result down
883 with m
.If(self
.i
.tot
[-1]):
885 self
.o
.z
.m
.eq(self
.i
.tot
[4:]),
886 self
.o
.of
.m0
.eq(self
.i
.tot
[4]),
887 self
.o
.of
.guard
.eq(self
.i
.tot
[3]),
888 self
.o
.of
.round_bit
.eq(self
.i
.tot
[2]),
889 self
.o
.of
.sticky
.eq(self
.i
.tot
[1] | self
.i
.tot
[0]),
890 self
.o
.z
.e
.eq(self
.i
.z
.e
+ 1)
892 # tot[-1] (MSB) zero case
895 self
.o
.z
.m
.eq(self
.i
.tot
[3:]),
896 self
.o
.of
.m0
.eq(self
.i
.tot
[3]),
897 self
.o
.of
.guard
.eq(self
.i
.tot
[2]),
898 self
.o
.of
.round_bit
.eq(self
.i
.tot
[1]),
899 self
.o
.of
.sticky
.eq(self
.i
.tot
[0])
904 class FPAddStage1(FPState
, FPID
):
906 def __init__(self
, width
, id_wid
):
907 FPState
.__init
__(self
, "add_1")
908 FPID
.__init
__(self
, id_wid
)
909 self
.mod
= FPAddStage1Mod(width
)
910 self
.out_z
= FPNumBase(width
, False)
911 self
.out_of
= Overflow()
912 self
.norm_stb
= Signal()
914 def setup(self
, m
, in_tot
, in_z
, in_mid
):
915 """ links module to inputs and outputs
917 self
.mod
.setup(m
, in_tot
, in_z
)
919 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
921 if self
.in_mid
is not None:
922 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
926 m
.d
.sync
+= self
.out_of
.eq(self
.mod
.out_of
)
927 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
928 m
.d
.sync
+= self
.norm_stb
.eq(1)
929 m
.next
= "normalise_1"
932 class FPNormaliseModSingle
:
934 def __init__(self
, width
):
936 self
.in_z
= FPNumBase(width
, False)
937 self
.out_z
= FPNumBase(width
, False)
939 def setup(self
, m
, in_z
, out_z
, modname
):
940 """ links module to inputs and outputs
942 m
.submodules
.normalise
= self
943 m
.d
.comb
+= self
.in_z
.eq(in_z
)
944 m
.d
.comb
+= out_z
.eq(self
.out_z
)
946 def elaborate(self
, platform
):
949 mwid
= self
.out_z
.m_width
+2
950 pe
= PriorityEncoder(mwid
)
951 m
.submodules
.norm_pe
= pe
953 m
.submodules
.norm1_out_z
= self
.out_z
954 m
.submodules
.norm1_in_z
= self
.in_z
956 in_z
= FPNumBase(self
.width
, False)
958 m
.submodules
.norm1_insel_z
= in_z
959 m
.submodules
.norm1_insel_overflow
= in_of
961 espec
= (len(in_z
.e
), True)
962 ediff_n126
= Signal(espec
, reset_less
=True)
963 msr
= MultiShiftRMerge(mwid
, espec
)
964 m
.submodules
.multishift_r
= msr
966 m
.d
.comb
+= in_z
.eq(self
.in_z
)
967 m
.d
.comb
+= in_of
.eq(self
.in_of
)
968 # initialise out from in (overridden below)
969 m
.d
.comb
+= self
.out_z
.eq(in_z
)
970 m
.d
.comb
+= self
.out_of
.eq(in_of
)
971 # normalisation increase/decrease conditions
972 decrease
= Signal(reset_less
=True)
973 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
)
976 # *sigh* not entirely obvious: count leading zeros (clz)
977 # with a PriorityEncoder: to find from the MSB
978 # we reverse the order of the bits.
979 temp_m
= Signal(mwid
, reset_less
=True)
980 temp_s
= Signal(mwid
+1, reset_less
=True)
981 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
983 # cat round and guard bits back into the mantissa
984 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
985 pe
.i
.eq(temp_m
[::-1]), # inverted
986 clz
.eq(pe
.o
), # count zeros from MSB down
987 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
988 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
989 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
995 class FPNorm1ModSingle
:
997 def __init__(self
, width
):
999 self
.out_norm
= Signal(reset_less
=True)
1000 self
.in_z
= FPNumBase(width
, False)
1001 self
.in_of
= Overflow()
1002 self
.out_z
= FPNumBase(width
, False)
1003 self
.out_of
= Overflow()
1005 def setup(self
, m
, in_z
, in_of
, out_z
):
1006 """ links module to inputs and outputs
1008 m
.submodules
.normalise_1
= self
1010 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1011 m
.d
.comb
+= self
.in_of
.eq(in_of
)
1013 m
.d
.comb
+= out_z
.eq(self
.out_z
)
1015 def elaborate(self
, platform
):
1018 mwid
= self
.out_z
.m_width
+2
1019 pe
= PriorityEncoder(mwid
)
1020 m
.submodules
.norm_pe
= pe
1022 m
.submodules
.norm1_out_z
= self
.out_z
1023 m
.submodules
.norm1_out_overflow
= self
.out_of
1024 m
.submodules
.norm1_in_z
= self
.in_z
1025 m
.submodules
.norm1_in_overflow
= self
.in_of
1027 in_z
= FPNumBase(self
.width
, False)
1029 m
.submodules
.norm1_insel_z
= in_z
1030 m
.submodules
.norm1_insel_overflow
= in_of
1032 espec
= (len(in_z
.e
), True)
1033 ediff_n126
= Signal(espec
, reset_less
=True)
1034 msr
= MultiShiftRMerge(mwid
, espec
)
1035 m
.submodules
.multishift_r
= msr
1037 m
.d
.comb
+= in_z
.eq(self
.in_z
)
1038 m
.d
.comb
+= in_of
.eq(self
.in_of
)
1039 # initialise out from in (overridden below)
1040 m
.d
.comb
+= self
.out_z
.eq(in_z
)
1041 m
.d
.comb
+= self
.out_of
.eq(in_of
)
1042 # normalisation increase/decrease conditions
1043 decrease
= Signal(reset_less
=True)
1044 increase
= Signal(reset_less
=True)
1045 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
1046 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
1048 with m
.If(decrease
):
1049 # *sigh* not entirely obvious: count leading zeros (clz)
1050 # with a PriorityEncoder: to find from the MSB
1051 # we reverse the order of the bits.
1052 temp_m
= Signal(mwid
, reset_less
=True)
1053 temp_s
= Signal(mwid
+1, reset_less
=True)
1054 clz
= Signal((len(in_z
.e
), True), reset_less
=True)
1055 # make sure that the amount to decrease by does NOT
1056 # go below the minimum non-INF/NaN exponent
1057 limclz
= Mux(in_z
.exp_sub_n126
> pe
.o
, pe
.o
,
1060 # cat round and guard bits back into the mantissa
1061 temp_m
.eq(Cat(in_of
.round_bit
, in_of
.guard
, in_z
.m
)),
1062 pe
.i
.eq(temp_m
[::-1]), # inverted
1063 clz
.eq(limclz
), # count zeros from MSB down
1064 temp_s
.eq(temp_m
<< clz
), # shift mantissa UP
1065 self
.out_z
.e
.eq(in_z
.e
- clz
), # DECREASE exponent
1066 self
.out_z
.m
.eq(temp_s
[2:]), # exclude bits 0&1
1067 self
.out_of
.m0
.eq(temp_s
[2]), # copy of mantissa[0]
1068 # overflow in bits 0..1: got shifted too (leave sticky)
1069 self
.out_of
.guard
.eq(temp_s
[1]), # guard
1070 self
.out_of
.round_bit
.eq(temp_s
[0]), # round
1073 with m
.Elif(increase
):
1074 temp_m
= Signal(mwid
+1, reset_less
=True)
1076 temp_m
.eq(Cat(in_of
.sticky
, in_of
.round_bit
, in_of
.guard
,
1078 ediff_n126
.eq(in_z
.N126
- in_z
.e
),
1079 # connect multi-shifter to inp/out mantissa (and ediff)
1081 msr
.diff
.eq(ediff_n126
),
1082 self
.out_z
.m
.eq(msr
.m
[3:]),
1083 self
.out_of
.m0
.eq(temp_s
[3]), # copy of mantissa[0]
1084 # overflow in bits 0..1: got shifted too (leave sticky)
1085 self
.out_of
.guard
.eq(temp_s
[2]), # guard
1086 self
.out_of
.round_bit
.eq(temp_s
[1]), # round
1087 self
.out_of
.sticky
.eq(temp_s
[0]), # sticky
1088 self
.out_z
.e
.eq(in_z
.e
+ ediff_n126
),
1094 class FPNorm1ModMulti
:
1096 def __init__(self
, width
, single_cycle
=True):
1098 self
.in_select
= Signal(reset_less
=True)
1099 self
.out_norm
= Signal(reset_less
=True)
1100 self
.in_z
= FPNumBase(width
, False)
1101 self
.in_of
= Overflow()
1102 self
.temp_z
= FPNumBase(width
, False)
1103 self
.temp_of
= Overflow()
1104 self
.out_z
= FPNumBase(width
, False)
1105 self
.out_of
= Overflow()
1107 def elaborate(self
, platform
):
1110 m
.submodules
.norm1_out_z
= self
.out_z
1111 m
.submodules
.norm1_out_overflow
= self
.out_of
1112 m
.submodules
.norm1_temp_z
= self
.temp_z
1113 m
.submodules
.norm1_temp_of
= self
.temp_of
1114 m
.submodules
.norm1_in_z
= self
.in_z
1115 m
.submodules
.norm1_in_overflow
= self
.in_of
1117 in_z
= FPNumBase(self
.width
, False)
1119 m
.submodules
.norm1_insel_z
= in_z
1120 m
.submodules
.norm1_insel_overflow
= in_of
1122 # select which of temp or in z/of to use
1123 with m
.If(self
.in_select
):
1124 m
.d
.comb
+= in_z
.eq(self
.in_z
)
1125 m
.d
.comb
+= in_of
.eq(self
.in_of
)
1127 m
.d
.comb
+= in_z
.eq(self
.temp_z
)
1128 m
.d
.comb
+= in_of
.eq(self
.temp_of
)
1129 # initialise out from in (overridden below)
1130 m
.d
.comb
+= self
.out_z
.eq(in_z
)
1131 m
.d
.comb
+= self
.out_of
.eq(in_of
)
1132 # normalisation increase/decrease conditions
1133 decrease
= Signal(reset_less
=True)
1134 increase
= Signal(reset_less
=True)
1135 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
1136 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
1137 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end
1139 with m
.If(decrease
):
1141 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
1142 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
1143 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
1144 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
1145 self
.out_of
.round_bit
.eq(0), # reset round bit
1146 self
.out_of
.m0
.eq(in_of
.guard
),
1149 with m
.Elif(increase
):
1151 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
1152 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
1153 self
.out_of
.guard
.eq(in_z
.m
[0]),
1154 self
.out_of
.m0
.eq(in_z
.m
[1]),
1155 self
.out_of
.round_bit
.eq(in_of
.guard
),
1156 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
1162 class FPNorm1Single(FPState
, FPID
):
1164 def __init__(self
, width
, id_wid
, single_cycle
=True):
1165 FPID
.__init
__(self
, id_wid
)
1166 FPState
.__init
__(self
, "normalise_1")
1167 self
.mod
= FPNorm1ModSingle(width
)
1168 self
.out_norm
= Signal(reset_less
=True)
1169 self
.out_z
= FPNumBase(width
)
1170 self
.out_roundz
= Signal(reset_less
=True)
1172 def setup(self
, m
, in_z
, in_of
, in_mid
):
1173 """ links module to inputs and outputs
1175 self
.mod
.setup(m
, in_z
, in_of
, self
.out_z
)
1177 if self
.in_mid
is not None:
1178 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1180 def action(self
, m
):
1182 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1186 class FPNorm1Multi(FPState
, FPID
):
1188 def __init__(self
, width
, id_wid
):
1189 FPID
.__init
__(self
, id_wid
)
1190 FPState
.__init
__(self
, "normalise_1")
1191 self
.mod
= FPNorm1ModMulti(width
)
1192 self
.stb
= Signal(reset_less
=True)
1193 self
.ack
= Signal(reset
=0, reset_less
=True)
1194 self
.out_norm
= Signal(reset_less
=True)
1195 self
.in_accept
= Signal(reset_less
=True)
1196 self
.temp_z
= FPNumBase(width
)
1197 self
.temp_of
= Overflow()
1198 self
.out_z
= FPNumBase(width
)
1199 self
.out_roundz
= Signal(reset_less
=True)
1201 def setup(self
, m
, in_z
, in_of
, norm_stb
, in_mid
):
1202 """ links module to inputs and outputs
1204 self
.mod
.setup(m
, in_z
, in_of
, norm_stb
,
1205 self
.in_accept
, self
.temp_z
, self
.temp_of
,
1206 self
.out_z
, self
.out_norm
)
1208 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
1209 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
1211 if self
.in_mid
is not None:
1212 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1214 def action(self
, m
):
1216 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
1217 m
.d
.sync
+= self
.temp_of
.eq(self
.mod
.out_of
)
1218 m
.d
.sync
+= self
.temp_z
.eq(self
.out_z
)
1219 with m
.If(self
.out_norm
):
1220 with m
.If(self
.in_accept
):
1225 m
.d
.sync
+= self
.ack
.eq(0)
1227 # normalisation not required (or done).
1229 m
.d
.sync
+= self
.ack
.eq(1)
1230 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
1233 class FPNormToPack(FPState
, FPID
):
1235 def __init__(self
, width
, id_wid
):
1236 FPID
.__init
__(self
, id_wid
)
1237 FPState
.__init
__(self
, "normalise_1")
1240 def setup(self
, m
, in_z
, in_of
, in_mid
):
1241 """ links module to inputs and outputs
1244 # Normalisation (chained to input in_z+in_of)
1245 nmod
= FPNorm1ModSingle(self
.width
)
1246 n_out_z
= FPNumBase(self
.width
)
1247 n_out_roundz
= Signal(reset_less
=True)
1248 nmod
.setup(m
, in_z
, in_of
, n_out_z
)
1250 # Rounding (chained to normalisation)
1251 rmod
= FPRoundMod(self
.width
)
1252 r_out_z
= FPNumBase(self
.width
)
1253 rmod
.setup(m
, n_out_z
, n_out_roundz
)
1254 m
.d
.comb
+= n_out_roundz
.eq(nmod
.out_of
.roundz
)
1255 m
.d
.comb
+= r_out_z
.eq(rmod
.out_z
)
1257 # Corrections (chained to rounding)
1258 cmod
= FPCorrectionsMod(self
.width
)
1259 c_out_z
= FPNumBase(self
.width
)
1260 cmod
.setup(m
, r_out_z
)
1261 m
.d
.comb
+= c_out_z
.eq(cmod
.out_z
)
1263 # Pack (chained to corrections)
1264 self
.pmod
= FPPackMod(self
.width
)
1265 self
.out_z
= FPNumBase(self
.width
)
1266 self
.pmod
.setup(m
, c_out_z
)
1269 if self
.in_mid
is not None:
1270 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1272 def action(self
, m
):
1273 self
.idsync(m
) # copies incoming ID to outgoing
1274 m
.d
.sync
+= self
.out_z
.v
.eq(self
.pmod
.out_z
.v
) # outputs packed result
1275 m
.next
= "pack_put_z"
1280 def __init__(self
, width
):
1281 self
.in_roundz
= Signal(reset_less
=True)
1282 self
.in_z
= FPNumBase(width
, False)
1283 self
.out_z
= FPNumBase(width
, False)
1285 def setup(self
, m
, in_z
, roundz
):
1286 m
.submodules
.roundz
= self
1288 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1289 m
.d
.comb
+= self
.in_roundz
.eq(roundz
)
1291 def elaborate(self
, platform
):
1293 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
1294 with m
.If(self
.in_roundz
):
1295 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
1296 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
1297 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
1301 class FPRound(FPState
, FPID
):
1303 def __init__(self
, width
, id_wid
):
1304 FPState
.__init
__(self
, "round")
1305 FPID
.__init
__(self
, id_wid
)
1306 self
.mod
= FPRoundMod(width
)
1307 self
.out_z
= FPNumBase(width
)
1309 def setup(self
, m
, in_z
, roundz
, in_mid
):
1310 """ links module to inputs and outputs
1312 self
.mod
.setup(m
, in_z
, roundz
)
1314 if self
.in_mid
is not None:
1315 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1317 def action(self
, m
):
1319 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1320 m
.next
= "corrections"
1323 class FPCorrectionsMod
:
1325 def __init__(self
, width
):
1326 self
.in_z
= FPNumOut(width
, False)
1327 self
.out_z
= FPNumOut(width
, False)
1329 def setup(self
, m
, in_z
):
1330 """ links module to inputs and outputs
1332 m
.submodules
.corrections
= self
1333 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1335 def elaborate(self
, platform
):
1337 m
.submodules
.corr_in_z
= self
.in_z
1338 m
.submodules
.corr_out_z
= self
.out_z
1339 m
.d
.comb
+= self
.out_z
.eq(self
.in_z
)
1340 with m
.If(self
.in_z
.is_denormalised
):
1341 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
1345 class FPCorrections(FPState
, FPID
):
1347 def __init__(self
, width
, id_wid
):
1348 FPState
.__init
__(self
, "corrections")
1349 FPID
.__init
__(self
, id_wid
)
1350 self
.mod
= FPCorrectionsMod(width
)
1351 self
.out_z
= FPNumBase(width
)
1353 def setup(self
, m
, in_z
, in_mid
):
1354 """ links module to inputs and outputs
1356 self
.mod
.setup(m
, in_z
)
1357 if self
.in_mid
is not None:
1358 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1360 def action(self
, m
):
1362 m
.d
.sync
+= self
.out_z
.eq(self
.mod
.out_z
)
1368 def __init__(self
, width
):
1369 self
.in_z
= FPNumOut(width
, False)
1370 self
.out_z
= FPNumOut(width
, False)
1372 def setup(self
, m
, in_z
):
1373 """ links module to inputs and outputs
1375 m
.submodules
.pack
= self
1376 m
.d
.comb
+= self
.in_z
.eq(in_z
)
1378 def elaborate(self
, platform
):
1380 m
.submodules
.pack_in_z
= self
.in_z
1381 with m
.If(self
.in_z
.is_overflowed
):
1382 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
1384 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
1388 class FPPack(FPState
, FPID
):
1390 def __init__(self
, width
, id_wid
):
1391 FPState
.__init
__(self
, "pack")
1392 FPID
.__init
__(self
, id_wid
)
1393 self
.mod
= FPPackMod(width
)
1394 self
.out_z
= FPNumOut(width
, False)
1396 def setup(self
, m
, in_z
, in_mid
):
1397 """ links module to inputs and outputs
1399 self
.mod
.setup(m
, in_z
)
1400 if self
.in_mid
is not None:
1401 m
.d
.comb
+= self
.in_mid
.eq(in_mid
)
1403 def action(self
, m
):
1405 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1406 m
.next
= "pack_put_z"
1409 class FPPutZ(FPState
):
1411 def __init__(self
, state
, in_z
, out_z
, in_mid
, out_mid
, to_state
=None):
1412 FPState
.__init
__(self
, state
)
1413 if to_state
is None:
1414 to_state
= "get_ops"
1415 self
.to_state
= to_state
1418 self
.in_mid
= in_mid
1419 self
.out_mid
= out_mid
1421 def action(self
, m
):
1422 if self
.in_mid
is not None:
1423 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
1425 self
.out_z
.v
.eq(self
.in_z
.v
)
1427 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
1428 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1429 m
.next
= self
.to_state
1431 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1434 class FPPutZIdx(FPState
):
1436 def __init__(self
, state
, in_z
, out_zs
, in_mid
, to_state
=None):
1437 FPState
.__init
__(self
, state
)
1438 if to_state
is None:
1439 to_state
= "get_ops"
1440 self
.to_state
= to_state
1442 self
.out_zs
= out_zs
1443 self
.in_mid
= in_mid
1445 def action(self
, m
):
1446 outz_stb
= Signal(reset_less
=True)
1447 outz_ack
= Signal(reset_less
=True)
1448 m
.d
.comb
+= [outz_stb
.eq(self
.out_zs
[self
.in_mid
].stb
),
1449 outz_ack
.eq(self
.out_zs
[self
.in_mid
].ack
),
1452 self
.out_zs
[self
.in_mid
].v
.eq(self
.in_z
.v
)
1454 with m
.If(outz_stb
& outz_ack
):
1455 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(0)
1456 m
.next
= self
.to_state
1458 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(1)
1461 class FPADDBaseMod(FPID
):
1463 def __init__(self
, width
, id_wid
=None, single_cycle
=False, compact
=True):
1466 * width: bit-width of IEEE754. supported: 16, 32, 64
1467 * id_wid: an identifier that is sync-connected to the input
1468 * single_cycle: True indicates each stage to complete in 1 clock
1469 * compact: True indicates a reduced number of stages
1471 FPID
.__init
__(self
, id_wid
)
1473 self
.single_cycle
= single_cycle
1474 self
.compact
= compact
1476 self
.in_t
= Trigger()
1477 self
.in_a
= Signal(width
)
1478 self
.in_b
= Signal(width
)
1479 self
.out_z
= FPOp(width
)
1483 def add_state(self
, state
):
1484 self
.states
.append(state
)
1487 def get_fragment(self
, platform
=None):
1488 """ creates the HDL code-fragment for FPAdd
1491 m
.submodules
.out_z
= self
.out_z
1492 m
.submodules
.in_t
= self
.in_t
1494 self
.get_compact_fragment(m
, platform
)
1496 self
.get_longer_fragment(m
, platform
)
1498 with m
.FSM() as fsm
:
1500 for state
in self
.states
:
1501 with m
.State(state
.state_from
):
1506 def get_longer_fragment(self
, m
, platform
=None):
1508 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1509 self
.in_a
, self
.in_b
, self
.width
))
1510 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1514 sc
= self
.add_state(FPAddSpecialCases(self
.width
, self
.id_wid
))
1515 sc
.setup(m
, a
, b
, self
.in_mid
)
1517 dn
= self
.add_state(FPAddDeNorm(self
.width
, self
.id_wid
))
1518 dn
.setup(m
, a
, b
, sc
.in_mid
)
1520 if self
.single_cycle
:
1521 alm
= self
.add_state(FPAddAlignSingle(self
.width
, self
.id_wid
))
1522 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1524 alm
= self
.add_state(FPAddAlignMulti(self
.width
, self
.id_wid
))
1525 alm
.setup(m
, dn
.out_a
, dn
.out_b
, dn
.in_mid
)
1527 add0
= self
.add_state(FPAddStage0(self
.width
, self
.id_wid
))
1528 add0
.setup(m
, alm
.out_a
, alm
.out_b
, alm
.in_mid
)
1530 add1
= self
.add_state(FPAddStage1(self
.width
, self
.id_wid
))
1531 add1
.setup(m
, add0
.out_tot
, add0
.out_z
, add0
.in_mid
)
1533 if self
.single_cycle
:
1534 n1
= self
.add_state(FPNorm1Single(self
.width
, self
.id_wid
))
1535 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add0
.in_mid
)
1537 n1
= self
.add_state(FPNorm1Multi(self
.width
, self
.id_wid
))
1538 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
, add0
.in_mid
)
1540 rn
= self
.add_state(FPRound(self
.width
, self
.id_wid
))
1541 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
, n1
.in_mid
)
1543 cor
= self
.add_state(FPCorrections(self
.width
, self
.id_wid
))
1544 cor
.setup(m
, rn
.out_z
, rn
.in_mid
)
1546 pa
= self
.add_state(FPPack(self
.width
, self
.id_wid
))
1547 pa
.setup(m
, cor
.out_z
, rn
.in_mid
)
1549 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
,
1550 pa
.in_mid
, self
.out_mid
))
1552 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1553 pa
.in_mid
, self
.out_mid
))
1555 def get_compact_fragment(self
, m
, platform
=None):
1557 get
= self
.add_state(FPGet2Op("get_ops", "special_cases",
1558 self
.in_a
, self
.in_b
, self
.width
))
1559 get
.setup(m
, self
.in_a
, self
.in_b
, self
.in_t
.stb
, self
.in_t
.ack
)
1563 sc
= self
.add_state(FPAddSpecialCasesDeNorm(self
.width
, self
.id_wid
))
1564 sc
.setup(m
, a
, b
, self
.in_mid
)
1566 alm
= self
.add_state(FPAddAlignSingleAdd(self
.width
, self
.id_wid
))
1567 alm
.setup(m
, sc
.o
.a
, sc
.o
.b
, sc
.in_mid
)
1569 n1
= self
.add_state(FPNormToPack(self
.width
, self
.id_wid
))
1570 n1
.setup(m
, alm
.out_z
, alm
.out_of
, alm
.in_mid
)
1572 ppz
= self
.add_state(FPPutZ("pack_put_z", n1
.out_z
, self
.out_z
,
1573 n1
.in_mid
, self
.out_mid
))
1575 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
,
1576 sc
.in_mid
, self
.out_mid
))
1579 class FPADDBase(FPState
, FPID
):
1581 def __init__(self
, width
, id_wid
=None, single_cycle
=False):
1584 * width: bit-width of IEEE754. supported: 16, 32, 64
1585 * id_wid: an identifier that is sync-connected to the input
1586 * single_cycle: True indicates each stage to complete in 1 clock
1588 FPID
.__init
__(self
, id_wid
)
1589 FPState
.__init
__(self
, "fpadd")
1591 self
.single_cycle
= single_cycle
1592 self
.mod
= FPADDBaseMod(width
, id_wid
, single_cycle
)
1594 self
.in_t
= Trigger()
1595 self
.in_a
= Signal(width
)
1596 self
.in_b
= Signal(width
)
1597 #self.out_z = FPOp(width)
1599 self
.z_done
= Signal(reset_less
=True) # connects to out_z Strobe
1600 self
.in_accept
= Signal(reset_less
=True)
1601 self
.add_stb
= Signal(reset_less
=True)
1602 self
.add_ack
= Signal(reset
=0, reset_less
=True)
1604 def setup(self
, m
, a
, b
, add_stb
, in_mid
, out_z
, out_mid
):
1606 self
.out_mid
= out_mid
1607 m
.d
.comb
+= [self
.in_a
.eq(a
),
1609 self
.mod
.in_a
.eq(self
.in_a
),
1610 self
.mod
.in_b
.eq(self
.in_b
),
1611 self
.in_mid
.eq(in_mid
),
1612 self
.mod
.in_mid
.eq(self
.in_mid
),
1613 self
.z_done
.eq(self
.mod
.out_z
.trigger
),
1614 #self.add_stb.eq(add_stb),
1615 self
.mod
.in_t
.stb
.eq(self
.in_t
.stb
),
1616 self
.in_t
.ack
.eq(self
.mod
.in_t
.ack
),
1617 self
.out_mid
.eq(self
.mod
.out_mid
),
1618 self
.out_z
.v
.eq(self
.mod
.out_z
.v
),
1619 self
.out_z
.stb
.eq(self
.mod
.out_z
.stb
),
1620 self
.mod
.out_z
.ack
.eq(self
.out_z
.ack
),
1623 m
.d
.sync
+= self
.add_stb
.eq(add_stb
)
1624 m
.d
.sync
+= self
.add_ack
.eq(0) # sets to zero when not in active state
1625 m
.d
.sync
+= self
.out_z
.ack
.eq(0) # likewise
1626 #m.d.sync += self.in_t.stb.eq(0)
1628 m
.submodules
.fpadd
= self
.mod
1630 def action(self
, m
):
1632 # in_accept is set on incoming strobe HIGH and ack LOW.
1633 m
.d
.comb
+= self
.in_accept
.eq((~self
.add_ack
) & (self
.add_stb
))
1635 #with m.If(self.in_t.ack):
1636 # m.d.sync += self.in_t.stb.eq(0)
1637 with m
.If(~self
.z_done
):
1638 # not done: test for accepting an incoming operand pair
1639 with m
.If(self
.in_accept
):
1641 self
.add_ack
.eq(1), # acknowledge receipt...
1642 self
.in_t
.stb
.eq(1), # initiate add
1645 m
.d
.sync
+= [self
.add_ack
.eq(0),
1646 self
.in_t
.stb
.eq(0),
1647 self
.out_z
.ack
.eq(1),
1650 # done: acknowledge, and write out id and value
1651 m
.d
.sync
+= [self
.add_ack
.eq(1),
1658 if self
.in_mid
is not None:
1659 m
.d
.sync
+= self
.out_mid
.eq(self
.mod
.out_mid
)
1662 self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
1664 # move to output state on detecting z ack
1665 with m
.If(self
.out_z
.trigger
):
1666 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
1669 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
1672 def __init__(self
, width
, id_wid
):
1674 self
.id_wid
= id_wid
1676 for i
in range(rs_sz
):
1678 out_z
.name
= "out_z_%d" % i
1680 self
.res
= Array(res
)
1681 self
.in_z
= FPOp(width
)
1682 self
.in_mid
= Signal(self
.id_wid
, reset_less
=True)
1684 def setup(self
, m
, in_z
, in_mid
):
1685 m
.d
.comb
+= [self
.in_z
.eq(in_z
),
1686 self
.in_mid
.eq(in_mid
)]
1688 def get_fragment(self
, platform
=None):
1689 """ creates the HDL code-fragment for FPAdd
1692 m
.submodules
.res_in_z
= self
.in_z
1693 m
.submodules
+= self
.res
1705 """ FPADD: stages as follows:
1711 FPAddBase---> FPAddBaseMod
1713 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1715 FPAddBase is tricky: it is both a stage and *has* stages.
1716 Connection to FPAddBaseMod therefore requires an in stb/ack
1717 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1718 needs to be the thing that raises the incoming stb.
1721 def __init__(self
, width
, id_wid
=None, single_cycle
=False, rs_sz
=2):
1724 * width: bit-width of IEEE754. supported: 16, 32, 64
1725 * id_wid: an identifier that is sync-connected to the input
1726 * single_cycle: True indicates each stage to complete in 1 clock
1729 self
.id_wid
= id_wid
1730 self
.single_cycle
= single_cycle
1732 #self.out_z = FPOp(width)
1733 self
.ids
= FPID(id_wid
)
1736 for i
in range(rs_sz
):
1739 in_a
.name
= "in_a_%d" % i
1740 in_b
.name
= "in_b_%d" % i
1741 rs
.append((in_a
, in_b
))
1745 for i
in range(rs_sz
):
1747 out_z
.name
= "out_z_%d" % i
1749 self
.res
= Array(res
)
1753 def add_state(self
, state
):
1754 self
.states
.append(state
)
1757 def get_fragment(self
, platform
=None):
1758 """ creates the HDL code-fragment for FPAdd
1761 m
.submodules
+= self
.rs
1763 in_a
= self
.rs
[0][0]
1764 in_b
= self
.rs
[0][1]
1766 out_z
= FPOp(self
.width
)
1767 out_mid
= Signal(self
.id_wid
, reset_less
=True)
1768 m
.submodules
.out_z
= out_z
1770 geta
= self
.add_state(FPGetOp("get_a", "get_b",
1775 getb
= self
.add_state(FPGetOp("get_b", "fpadd",
1780 ab
= FPADDBase(self
.width
, self
.id_wid
, self
.single_cycle
)
1781 ab
= self
.add_state(ab
)
1782 ab
.setup(m
, a
, b
, getb
.out_decode
, self
.ids
.in_mid
,
1785 pz
= self
.add_state(FPPutZIdx("put_z", ab
.out_z
, self
.res
,
1788 with m
.FSM() as fsm
:
1790 for state
in self
.states
:
1791 with m
.State(state
.state_from
):
1797 if __name__
== "__main__":
1799 alu
= FPADD(width
=32, id_wid
=5, single_cycle
=True)
1800 main(alu
, ports
=alu
.rs
[0][0].ports() + \
1801 alu
.rs
[0][1].ports() + \
1802 alu
.res
[0].ports() + \
1803 [alu
.ids
.in_mid
, alu
.ids
.out_mid
])
1805 alu
= FPADDBase(width
=32, id_wid
=5, single_cycle
=True)
1806 main(alu
, ports
=[alu
.in_a
, alu
.in_b
] + \
1807 alu
.in_t
.ports() + \
1808 alu
.out_z
.ports() + \
1809 [alu
.in_mid
, alu
.out_mid
])
1812 # works... but don't use, just do "python fname.py convert -t v"
1813 #print (verilog.convert(alu, ports=[
1814 # ports=alu.in_a.ports() + \
1815 # alu.in_b.ports() + \
1816 # alu.out_z.ports())