360e29393aad8842d5d82be0655676153274a41c
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
26 class FPGetOpA(FPState
):
30 def __init__(self
, in_a
, width
):
31 FPState
.__init
__(self
, "get_a")
33 self
.a
= FPNumIn(in_a
, width
)
36 self
.get_op(m
, self
.in_a
, self
.a
, "get_b")
39 class FPGetOpB(FPState
):
44 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
47 class FPAddSpecialCasesMod
:
48 """ special cases: NaNs, infs, zeros, denormalised
49 NOTE: some of these are unique to add. see "Special Operations"
50 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
53 def __init__(self
, width
):
54 self
.in_a
= FPNumBase(width
)
55 self
.in_b
= FPNumBase(width
)
56 self
.out_z
= FPNumOut(width
, False)
57 self
.out_do_z
= Signal(reset_less
=True)
59 def setup(self
, m
, in_a
, in_b
, out_z
, out_do_z
):
60 """ links module to inputs and outputs
62 m
.d
.comb
+= self
.in_a
.copy(in_a
)
63 m
.d
.comb
+= self
.in_b
.copy(in_b
)
64 m
.d
.comb
+= out_z
.v
.eq(self
.out_z
.v
)
65 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
67 def elaborate(self
, platform
):
70 m
.submodules
.sc_in_a
= self
.in_a
71 m
.submodules
.sc_in_b
= self
.in_b
72 m
.submodules
.sc_out_z
= self
.out_z
75 m
.d
.comb
+= s_nomatch
.eq(self
.in_a
.s
!= self
.in_b
.s
)
78 m
.d
.comb
+= m_match
.eq(self
.in_a
.m
== self
.in_b
.m
)
80 # if a is NaN or b is NaN return NaN
81 with m
.If(self
.in_a
.is_nan | self
.in_b
.is_nan
):
82 m
.d
.comb
+= self
.out_do_z
.eq(1)
83 m
.d
.comb
+= self
.out_z
.nan(1)
85 # XXX WEIRDNESS for FP16 non-canonical NaN handling
88 ## if a is zero and b is NaN return -b
89 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
90 # m.d.comb += self.out_do_z.eq(1)
91 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
93 ## if b is zero and a is NaN return -a
94 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
95 # m.d.comb += self.out_do_z.eq(1)
96 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
98 ## if a is -zero and b is NaN return -b
99 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
100 # m.d.comb += self.out_do_z.eq(1)
101 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
103 ## if b is -zero and a is NaN return -a
104 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
105 # m.d.comb += self.out_do_z.eq(1)
106 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
108 # if a is inf return inf (or NaN)
109 with m
.Elif(self
.in_a
.is_inf
):
110 m
.d
.comb
+= self
.out_do_z
.eq(1)
111 m
.d
.comb
+= self
.out_z
.inf(self
.in_a
.s
)
112 # if a is inf and signs don't match return NaN
113 with m
.If(self
.in_b
.exp_128
& s_nomatch
):
114 m
.d
.comb
+= self
.out_z
.nan(1)
116 # if b is inf return inf
117 with m
.Elif(self
.in_b
.is_inf
):
118 m
.d
.comb
+= self
.out_do_z
.eq(1)
119 m
.d
.comb
+= self
.out_z
.inf(self
.in_b
.s
)
121 # if a is zero and b zero return signed-a/b
122 with m
.Elif(self
.in_a
.is_zero
& self
.in_b
.is_zero
):
123 m
.d
.comb
+= self
.out_do_z
.eq(1)
124 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
& self
.in_b
.s
,
128 # if a is zero return b
129 with m
.Elif(self
.in_a
.is_zero
):
130 m
.d
.comb
+= self
.out_do_z
.eq(1)
131 m
.d
.comb
+= self
.out_z
.create(self
.in_b
.s
, self
.in_b
.e
,
134 # if b is zero return a
135 with m
.Elif(self
.in_b
.is_zero
):
136 m
.d
.comb
+= self
.out_do_z
.eq(1)
137 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
, self
.in_a
.e
,
140 # if a equal to -b return zero (+ve zero)
141 with m
.Elif(s_nomatch
& m_match
& (self
.in_a
.e
== self
.in_b
.e
)):
142 m
.d
.comb
+= self
.out_do_z
.eq(1)
143 m
.d
.comb
+= self
.out_z
.zero(0)
145 # Denormalised Number checks
147 m
.d
.comb
+= self
.out_do_z
.eq(0)
152 class FPAddSpecialCases(FPState
):
153 """ special cases: NaNs, infs, zeros, denormalised
154 NOTE: some of these are unique to add. see "Special Operations"
155 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
158 def __init__(self
, width
):
159 FPState
.__init
__(self
, "special_cases")
160 self
.mod
= FPAddSpecialCasesMod(width
)
161 self
.out_z
= FPNumOut(width
, False)
162 self
.out_do_z
= Signal(reset_less
=True)
165 with m
.If(self
.out_do_z
):
166 m
.d
.sync
+= self
.z
.v
.eq(self
.out_z
.v
) # only take the output
169 m
.next
= "denormalise"
172 class FPAddDeNorm(FPState
):
175 # Denormalised Number checks
177 self
.denormalise(m
, self
.a
)
178 self
.denormalise(m
, self
.b
)
181 class FPAddAlignMulti(FPState
):
184 # NOTE: this does *not* do single-cycle multi-shifting,
185 # it *STAYS* in the align state until exponents match
187 # exponent of a greater than b: shift b down
188 with m
.If(self
.a
.e
> self
.b
.e
):
189 m
.d
.sync
+= self
.b
.shift_down()
190 # exponent of b greater than a: shift a down
191 with m
.Elif(self
.a
.e
< self
.b
.e
):
192 m
.d
.sync
+= self
.a
.shift_down()
193 # exponents equal: move to next stage.
198 class FPAddAlignSingle(FPState
):
201 # This one however (single-cycle) will do the shift
204 # XXX TODO: the shifter used here is quite expensive
205 # having only one would be better
207 ediff
= Signal((len(self
.a
.e
), True), reset_less
=True)
208 ediffr
= Signal((len(self
.a
.e
), True), reset_less
=True)
209 m
.d
.comb
+= ediff
.eq(self
.a
.e
- self
.b
.e
)
210 m
.d
.comb
+= ediffr
.eq(self
.b
.e
- self
.a
.e
)
211 with m
.If(ediff
> 0):
212 m
.d
.sync
+= self
.b
.shift_down_multi(ediff
)
213 # exponent of b greater than a: shift a down
214 with m
.Elif(ediff
< 0):
215 m
.d
.sync
+= self
.a
.shift_down_multi(ediffr
)
220 class FPAddStage0(FPState
):
221 """ First stage of add. covers same-sign (add) and subtract
222 special-casing when mantissas are greater or equal, to
223 give greatest accuracy.
228 m
.d
.sync
+= self
.z
.e
.eq(self
.a
.e
)
229 # same-sign (both negative or both positive) add mantissas
230 with m
.If(self
.a
.s
== self
.b
.s
):
232 self
.tot
.eq(Cat(self
.a
.m
, 0) + Cat(self
.b
.m
, 0)),
233 self
.z
.s
.eq(self
.a
.s
)
235 # a mantissa greater than b, use a
236 with m
.Elif(self
.a
.m
>= self
.b
.m
):
238 self
.tot
.eq(Cat(self
.a
.m
, 0) - Cat(self
.b
.m
, 0)),
239 self
.z
.s
.eq(self
.a
.s
)
241 # b mantissa greater than a, use b
244 self
.tot
.eq(Cat(self
.b
.m
, 0) - Cat(self
.a
.m
, 0)),
245 self
.z
.s
.eq(self
.b
.s
)
249 class FPAddStage1(FPState
):
250 """ Second stage of add: preparation for normalisation.
251 detects when tot sum is too big (tot[27] is kinda a carry bit)
255 m
.next
= "normalise_1"
256 # tot[27] gets set when the sum overflows. shift result down
257 with m
.If(self
.tot
[-1]):
259 self
.z
.m
.eq(self
.tot
[4:]),
260 self
.of
.m0
.eq(self
.tot
[4]),
261 self
.of
.guard
.eq(self
.tot
[3]),
262 self
.of
.round_bit
.eq(self
.tot
[2]),
263 self
.of
.sticky
.eq(self
.tot
[1] | self
.tot
[0]),
264 self
.z
.e
.eq(self
.z
.e
+ 1)
269 self
.z
.m
.eq(self
.tot
[3:]),
270 self
.of
.m0
.eq(self
.tot
[3]),
271 self
.of
.guard
.eq(self
.tot
[2]),
272 self
.of
.round_bit
.eq(self
.tot
[1]),
273 self
.of
.sticky
.eq(self
.tot
[0])
279 def __init__(self
, width
):
280 self
.out_norm
= Signal(reset_less
=True)
281 self
.in_z
= FPNumBase(width
, False)
282 self
.out_z
= FPNumBase(width
, False)
283 self
.in_of
= Overflow()
284 self
.out_of
= Overflow()
286 def setup(self
, m
, in_z
, out_z
, in_of
, out_of
, out_norm
):
287 """ links module to inputs and outputs
289 m
.d
.comb
+= self
.in_z
.copy(in_z
)
290 m
.d
.comb
+= out_z
.copy(self
.out_z
)
291 m
.d
.comb
+= self
.in_of
.copy(in_of
)
292 m
.d
.comb
+= out_of
.copy(self
.out_of
)
293 m
.d
.comb
+= out_norm
.eq(self
.out_norm
)
295 def elaborate(self
, platform
):
297 m
.submodules
.norm1_in_overflow
= self
.in_of
298 m
.submodules
.norm1_out_overflow
= self
.out_of
299 m
.submodules
.norm1_in_z
= self
.in_z
300 m
.submodules
.norm1_out_z
= self
.out_z
301 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
302 m
.d
.comb
+= self
.out_of
.copy(self
.in_of
)
303 m
.d
.comb
+= self
.out_norm
.eq((self
.in_z
.m
[-1] == 0) & \
304 (self
.in_z
.e
> self
.in_z
.N126
))
305 with m
.If(self
.out_norm
):
307 self
.out_z
.e
.eq(self
.in_z
.e
- 1), # DECREASE exponent
308 self
.out_z
.m
.eq(self
.in_z
.m
<< 1), # shift mantissa UP
309 self
.out_z
.m
[0].eq(self
.in_of
.guard
), # steal guard (was tot[2])
310 self
.out_of
.guard
.eq(self
.in_of
.round_bit
), # round (was tot[1])
311 self
.out_of
.round_bit
.eq(0), # reset round bit
312 self
.out_of
.m0
.eq(self
.in_of
.guard
),
318 class FPNorm1(FPState
):
320 def __init__(self
, width
):
321 FPState
.__init
__(self
, "normalise_1")
322 self
.mod
= FPNorm1Mod(width
)
323 self
.out_norm
= Signal(reset_less
=True)
324 self
.out_z
= FPNumBase(width
)
325 self
.out_of
= Overflow()
328 m
.d
.sync
+= self
.of
.copy(self
.out_of
)
329 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
330 with m
.If(~self
.out_norm
):
331 m
.next
= "normalise_2"
334 class FPNorm2(FPState
):
337 self
.normalise_2(m
, self
.z
, self
.of
, "round")
342 def __init__(self
, width
):
343 self
.in_roundz
= Signal(reset_less
=True)
344 self
.in_z
= FPNumBase(width
, False)
345 self
.out_z
= FPNumBase(width
, False)
347 def setup(self
, m
, in_z
, out_z
, in_of
):
348 """ links module to inputs and outputs
350 m
.d
.comb
+= self
.in_z
.copy(in_z
)
351 m
.d
.comb
+= out_z
.copy(self
.out_z
)
352 m
.d
.comb
+= self
.in_roundz
.eq(in_of
.roundz
)
354 def elaborate(self
, platform
):
356 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
357 with m
.If(self
.in_roundz
):
358 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
359 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
360 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
364 class FPRound(FPState
):
366 def __init__(self
, width
):
367 FPState
.__init
__(self
, "round")
368 self
.mod
= FPRoundMod(width
)
369 self
.out_z
= FPNumBase(width
)
372 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
373 m
.next
= "corrections"
376 class FPCorrectionsMod
:
378 def __init__(self
, width
):
379 self
.in_z
= FPNumOut(width
, False)
380 self
.out_z
= FPNumOut(width
, False)
382 def setup(self
, m
, in_z
, out_z
):
383 """ links module to inputs and outputs
385 m
.d
.comb
+= self
.in_z
.copy(in_z
)
386 m
.d
.comb
+= out_z
.copy(self
.out_z
)
388 def elaborate(self
, platform
):
390 m
.submodules
.corr_in_z
= self
.in_z
391 m
.submodules
.corr_out_z
= self
.out_z
392 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
393 with m
.If(self
.in_z
.is_denormalised
):
394 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
396 # with m.If(self.in_z.is_overflowed):
397 # m.d.comb += self.out_z.inf(self.in_z.s)
399 # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
403 class FPCorrections(FPState
):
405 def __init__(self
, width
):
406 FPState
.__init
__(self
, "corrections")
407 self
.mod
= FPCorrectionsMod(width
)
408 self
.out_z
= FPNumBase(width
)
411 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
417 def __init__(self
, width
):
418 self
.in_z
= FPNumOut(width
, False)
419 self
.out_z
= FPNumOut(width
, False)
421 def setup(self
, m
, in_z
, out_z
):
422 """ links module to inputs and outputs
424 m
.d
.comb
+= self
.in_z
.copy(in_z
)
425 m
.d
.comb
+= out_z
.v
.eq(self
.out_z
.v
)
427 def elaborate(self
, platform
):
429 m
.submodules
.pack_in_z
= self
.in_z
430 with m
.If(self
.in_z
.is_overflowed
):
431 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
433 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
437 class FPPack(FPState
):
439 def __init__(self
, width
):
440 FPState
.__init
__(self
, "pack")
441 self
.mod
= FPPackMod(width
)
442 self
.out_z
= FPNumOut(width
, False)
445 m
.d
.sync
+= self
.z
.v
.eq(self
.out_z
.v
)
449 class FPPutZ(FPState
):
452 self
.put_z(m
, self
.z
, self
.out_z
, "get_a")
457 def __init__(self
, width
, single_cycle
=False):
459 self
.single_cycle
= single_cycle
461 self
.in_a
= FPOp(width
)
462 self
.in_b
= FPOp(width
)
463 self
.out_z
= FPOp(width
)
467 def add_state(self
, state
):
468 self
.states
.append(state
)
471 def get_fragment(self
, platform
=None):
472 """ creates the HDL code-fragment for FPAdd
477 #a = FPNumIn(self.in_a, self.width)
478 b
= FPNumIn(self
.in_b
, self
.width
)
479 z
= FPNumOut(self
.width
, False)
481 m
.submodules
.fpnum_b
= b
482 m
.submodules
.fpnum_z
= z
485 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
488 m
.submodules
.overflow
= of
490 geta
= self
.add_state(FPGetOpA(self
.in_a
, self
.width
))
491 #geta.set_inputs({"in_a": self.in_a})
492 #geta.set_outputs({"a": a})
494 # XXX m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
495 m
.submodules
.fpnum_a
= a
497 getb
= self
.add_state(FPGetOpB("get_b"))
498 getb
.set_inputs({"in_b": self
.in_b
})
499 getb
.set_outputs({"b": b
})
500 # XXX m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
502 sc
= self
.add_state(FPAddSpecialCases(self
.width
))
503 sc
.set_inputs({"a": a
, "b": b
})
504 sc
.set_outputs({"z": z
})
505 sc
.mod
.setup(m
, a
, b
, sc
.out_z
, sc
.out_do_z
)
506 m
.submodules
.specialcases
= sc
.mod
508 dn
= self
.add_state(FPAddDeNorm("denormalise"))
509 dn
.set_inputs({"a": a
, "b": b
})
510 dn
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
512 if self
.single_cycle
:
513 alm
= self
.add_state(FPAddAlignSingle("align"))
515 alm
= self
.add_state(FPAddAlignMulti("align"))
516 alm
.set_inputs({"a": a
, "b": b
})
517 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
519 add0
= self
.add_state(FPAddStage0("add_0"))
520 add0
.set_inputs({"a": a
, "b": b
})
521 add0
.set_outputs({"z": z
, "tot": tot
})
523 add1
= self
.add_state(FPAddStage1("add_1"))
524 add1
.set_inputs({"tot": tot
, "z": z
}) # Z input passes through
525 add1
.set_outputs({"z": z
, "of": of
}) # XXX Z as output
527 n1
= self
.add_state(FPNorm1(self
.width
))
528 n1
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
529 n1
.set_outputs({"z": z
}) # XXX Z as output
530 n1
.mod
.setup(m
, z
, n1
.out_z
, of
, n1
.out_of
, n1
.out_norm
)
531 m
.submodules
.normalise_1
= n1
.mod
533 n2
= self
.add_state(FPNorm2("normalise_2"))
534 n2
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
535 n2
.set_outputs({"z": z
}) # XXX Z as output
537 rn
= self
.add_state(FPRound(self
.width
))
538 rn
.set_inputs({"z": z
, "of": of
}) # XXX Z as output
539 rn
.set_outputs({"z": z
}) # XXX Z as output
540 rn
.mod
.setup(m
, z
, rn
.out_z
, of
)
541 m
.submodules
.roundz
= rn
.mod
543 cor
= self
.add_state(FPCorrections(self
.width
))
544 cor
.set_inputs({"z": z
}) # XXX Z as output
545 cor
.set_outputs({"z": z
}) # XXX Z as output
546 cor
.mod
.setup(m
, z
, cor
.out_z
)
547 m
.submodules
.corrections
= cor
.mod
549 pa
= self
.add_state(FPPack(self
.width
))
550 pa
.set_inputs({"z": z
}) # XXX Z as output
551 pa
.set_outputs({"z": z
}) # XXX Z as output
552 pa
.mod
.setup(m
, z
, pa
.out_z
)
553 m
.submodules
.pack
= pa
.mod
555 pz
= self
.add_state(FPPutZ("put_z"))
556 pz
.set_inputs({"z": z
})
557 pz
.set_outputs({"out_z": self
.out_z
})
561 for state
in self
.states
:
562 with m
.State(state
.state_from
):
568 if __name__
== "__main__":
569 alu
= FPADD(width
=32)
570 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
573 # works... but don't use, just do "python fname.py convert -t v"
574 #print (verilog.convert(alu, ports=[
575 # ports=alu.in_a.ports() + \
576 # alu.in_b.ports() + \