2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
30 #include "util/macros.h"
31 #include "util/u_math.h"
36 #include "drm-uapi/amdgpu_drm.h"
40 #define CIK_TILE_MODE_COLOR_2D 14
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
60 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
82 fprintf(stderr
, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
88 static bool has_syncobj(int fd
)
91 if (drmGetCap(fd
, DRM_CAP_SYNCOBJ
, &value
))
93 return value
? true : false;
96 static uint64_t fix_vram_size(uint64_t size
)
98 /* The VRAM size is underreported, so we need to fix it, because
99 * it's used to compute the number of memory modules for harvesting.
101 return align64(size
, 256*1024*1024);
105 get_l2_cache_size(enum radeon_family family
)
138 bool ac_query_gpu_info(int fd
, void *dev_p
,
139 struct radeon_info
*info
,
140 struct amdgpu_gpu_info
*amdinfo
)
142 struct drm_amdgpu_info_device device_info
= {};
143 struct amdgpu_buffer_size_alignments alignment_info
= {};
144 struct drm_amdgpu_info_hw_ip dma
= {}, compute
= {}, uvd
= {};
145 struct drm_amdgpu_info_hw_ip uvd_enc
= {}, vce
= {}, vcn_dec
= {}, vcn_jpeg
= {};
146 struct drm_amdgpu_info_hw_ip vcn_enc
= {}, gfx
= {};
147 struct amdgpu_gds_resource_info gds
= {};
148 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
150 amdgpu_device_handle dev
= dev_p
;
151 drmDevicePtr devinfo
;
154 r
= drmGetDevice2(fd
, 0, &devinfo
);
156 fprintf(stderr
, "amdgpu: drmGetDevice2 failed.\n");
159 info
->pci_domain
= devinfo
->businfo
.pci
->domain
;
160 info
->pci_bus
= devinfo
->businfo
.pci
->bus
;
161 info
->pci_dev
= devinfo
->businfo
.pci
->dev
;
162 info
->pci_func
= devinfo
->businfo
.pci
->func
;
163 drmFreeDevice(&devinfo
);
165 assert(info
->drm_major
== 3);
166 info
->is_amdgpu
= true;
168 /* Query hardware and driver information. */
169 r
= amdgpu_query_gpu_info(dev
, amdinfo
);
171 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
175 r
= amdgpu_query_info(dev
, AMDGPU_INFO_DEV_INFO
, sizeof(device_info
),
178 fprintf(stderr
, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
182 r
= amdgpu_query_buffer_size_alignment(dev
, &alignment_info
);
184 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
188 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
190 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
194 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_GFX
, 0, &gfx
);
196 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
200 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_COMPUTE
, 0, &compute
);
202 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
206 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
208 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
212 if (info
->drm_minor
>= 17) {
213 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD_ENC
, 0, &uvd_enc
);
215 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
220 if (info
->drm_minor
>= 17) {
221 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_DEC
, 0, &vcn_dec
);
223 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
228 if (info
->drm_minor
>= 17) {
229 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_ENC
, 0, &vcn_enc
);
231 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
236 if (info
->drm_minor
>= 27) {
237 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_JPEG
, 0, &vcn_jpeg
);
239 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
244 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
245 &info
->me_fw_version
,
246 &info
->me_fw_feature
);
248 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
252 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
253 &info
->pfp_fw_version
,
254 &info
->pfp_fw_feature
);
256 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
260 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
261 &info
->ce_fw_version
,
262 &info
->ce_fw_feature
);
264 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
268 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
269 &uvd_version
, &uvd_feature
);
271 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
275 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
277 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
281 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
282 &vce_version
, &vce_feature
);
284 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
288 r
= amdgpu_query_sw_info(dev
, amdgpu_sw_info_address32_hi
, &info
->address32_hi
);
290 fprintf(stderr
, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
294 r
= amdgpu_query_gds_info(dev
, &gds
);
296 fprintf(stderr
, "amdgpu: amdgpu_query_gds_info failed.\n");
300 if (info
->drm_minor
>= 9) {
301 struct drm_amdgpu_memory_info meminfo
= {};
303 r
= amdgpu_query_info(dev
, AMDGPU_INFO_MEMORY
, sizeof(meminfo
), &meminfo
);
305 fprintf(stderr
, "amdgpu: amdgpu_query_info(memory) failed.\n");
309 /* Note: usable_heap_size values can be random and can't be relied on. */
310 info
->gart_size
= meminfo
.gtt
.total_heap_size
;
311 info
->vram_size
= fix_vram_size(meminfo
.vram
.total_heap_size
);
312 info
->vram_vis_size
= meminfo
.cpu_accessible_vram
.total_heap_size
;
314 /* This is a deprecated interface, which reports usable sizes
315 * (total minus pinned), but the pinned size computation is
316 * buggy, so the values returned from these functions can be
319 struct amdgpu_heap_info vram
, vram_vis
, gtt
;
321 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
323 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
327 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
,
328 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
331 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
335 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
337 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
341 info
->gart_size
= gtt
.heap_size
;
342 info
->vram_size
= fix_vram_size(vram
.heap_size
);
343 info
->vram_vis_size
= vram_vis
.heap_size
;
346 /* Set chip identification. */
347 info
->pci_id
= amdinfo
->asic_id
; /* TODO: is this correct? */
348 info
->pci_rev_id
= amdinfo
->pci_rev_id
;
349 info
->vce_harvest_config
= amdinfo
->vce_harvest_config
;
351 #define identify_chip2(asic, chipname) \
352 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
353 info->family = CHIP_##chipname; \
354 info->name = #chipname; \
356 #define identify_chip(chipname) identify_chip2(chipname, chipname)
358 switch (amdinfo
->family_id
) {
360 identify_chip(TAHITI
);
361 identify_chip(PITCAIRN
);
362 identify_chip2(CAPEVERDE
, VERDE
);
363 identify_chip(OLAND
);
364 identify_chip(HAINAN
);
367 identify_chip(BONAIRE
);
368 identify_chip(HAWAII
);
371 identify_chip2(SPECTRE
, KAVERI
);
372 identify_chip2(SPOOKY
, KAVERI
);
373 identify_chip2(KALINDI
, KABINI
);
374 identify_chip2(GODAVARI
, KABINI
);
377 identify_chip(ICELAND
);
378 identify_chip(TONGA
);
380 identify_chip(POLARIS10
);
381 identify_chip(POLARIS11
);
382 identify_chip(POLARIS12
);
383 identify_chip(VEGAM
);
386 identify_chip(CARRIZO
);
387 identify_chip(STONEY
);
390 identify_chip(VEGA10
);
391 identify_chip(VEGA12
);
392 identify_chip(VEGA20
);
393 identify_chip(ARCTURUS
);
396 identify_chip(RAVEN
);
397 identify_chip(RAVEN2
);
398 identify_chip(RENOIR
);
401 identify_chip(NAVI10
);
402 identify_chip(NAVI12
);
403 identify_chip(NAVI14
);
404 identify_chip(SIENNA
);
409 fprintf(stderr
, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
410 amdinfo
->family_id
, amdinfo
->chip_external_rev
);
414 if (info
->family
>= CHIP_SIENNA
)
415 info
->chip_class
= GFX10_3
;
416 else if (info
->family
>= CHIP_NAVI10
)
417 info
->chip_class
= GFX10
;
418 else if (info
->family
>= CHIP_VEGA10
)
419 info
->chip_class
= GFX9
;
420 else if (info
->family
>= CHIP_TONGA
)
421 info
->chip_class
= GFX8
;
422 else if (info
->family
>= CHIP_BONAIRE
)
423 info
->chip_class
= GFX7
;
424 else if (info
->family
>= CHIP_TAHITI
)
425 info
->chip_class
= GFX6
;
427 fprintf(stderr
, "amdgpu: Unknown family.\n");
431 info
->family_id
= amdinfo
->family_id
;
432 info
->chip_external_rev
= amdinfo
->chip_external_rev
;
433 info
->marketing_name
= amdgpu_get_marketing_name(dev
);
434 info
->is_pro_graphics
= info
->marketing_name
&&
435 (!strcmp(info
->marketing_name
, "Pro") ||
436 !strcmp(info
->marketing_name
, "PRO") ||
437 !strcmp(info
->marketing_name
, "Frontier"));
439 /* Set which chips have dedicated VRAM. */
440 info
->has_dedicated_vram
=
441 !(amdinfo
->ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
443 /* The kernel can split large buffers in VRAM but not in GTT, so large
444 * allocations can fail or cause buffer movement failures in the kernel.
446 if (info
->has_dedicated_vram
)
447 info
->max_alloc_size
= info
->vram_size
* 0.8;
449 info
->max_alloc_size
= info
->gart_size
* 0.7;
451 info
->vram_type
= amdinfo
->vram_type
;
452 info
->vram_bit_width
= amdinfo
->vram_bit_width
;
453 info
->ce_ram_size
= amdinfo
->ce_ram_size
;
455 info
->l2_cache_size
= get_l2_cache_size(info
->family
);
456 info
->l1_cache_size
= 16384;
458 /* Set which chips have uncached device memory. */
459 info
->has_l2_uncached
= info
->chip_class
>= GFX9
;
461 /* Set hardware information. */
462 info
->gds_size
= gds
.gds_total_size
;
463 info
->gds_gfx_partition_size
= gds
.gds_gfx_partition_size
;
464 /* convert the shader/memory clocks from KHz to MHz */
465 info
->max_shader_clock
= amdinfo
->max_engine_clk
/ 1000;
466 info
->max_memory_clock
= amdinfo
->max_memory_clk
/ 1000;
467 info
->num_tcc_blocks
= device_info
.num_tcc_blocks
;
468 info
->max_se
= amdinfo
->num_shader_engines
;
469 info
->max_sh_per_se
= amdinfo
->num_shader_arrays_per_engine
;
470 info
->has_hw_decode
=
471 (uvd
.available_rings
!= 0) || (vcn_dec
.available_rings
!= 0) ||
472 (vcn_jpeg
.available_rings
!= 0);
473 info
->uvd_fw_version
=
474 uvd
.available_rings
? uvd_version
: 0;
475 info
->vce_fw_version
=
476 vce
.available_rings
? vce_version
: 0;
477 info
->uvd_enc_supported
=
478 uvd_enc
.available_rings
? true : false;
479 info
->has_userptr
= true;
480 info
->has_syncobj
= has_syncobj(fd
);
481 info
->has_syncobj_wait_for_submit
= info
->has_syncobj
&& info
->drm_minor
>= 20;
482 info
->has_fence_to_handle
= info
->has_syncobj
&& info
->drm_minor
>= 21;
483 info
->has_ctx_priority
= info
->drm_minor
>= 22;
484 info
->has_local_buffers
= info
->drm_minor
>= 20;
485 info
->kernel_flushes_hdp_before_ib
= true;
486 info
->htile_cmask_support_1d_tiling
= true;
487 info
->si_TA_CS_BC_BASE_ADDR_allowed
= true;
488 info
->has_bo_metadata
= true;
489 info
->has_gpu_reset_status_query
= true;
490 info
->has_eqaa_surface_allocator
= true;
491 info
->has_format_bc1_through_bc7
= true;
492 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
493 info
->kernel_flushes_tc_l2_after_ib
= info
->chip_class
!= GFX8
||
494 info
->drm_minor
>= 2;
495 info
->has_indirect_compute_dispatch
= true;
496 /* GFX6 doesn't support unaligned loads. */
497 info
->has_unaligned_shader_loads
= info
->chip_class
!= GFX6
;
498 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
499 * these faults are mitigated in software.
501 info
->has_sparse_vm_mappings
= info
->chip_class
>= GFX7
&& info
->drm_minor
>= 13;
502 info
->has_2d_tiling
= true;
503 info
->has_read_registers_query
= true;
504 info
->has_scheduled_fence_dependency
= info
->drm_minor
>= 28;
506 info
->pa_sc_tile_steering_override
= device_info
.pa_sc_tile_steering_override
;
507 info
->num_render_backends
= amdinfo
->rb_pipes
;
508 /* The value returned by the kernel driver was wrong. */
509 if (info
->family
== CHIP_KAVERI
)
510 info
->num_render_backends
= 2;
512 info
->clock_crystal_freq
= amdinfo
->gpu_counter_freq
;
513 if (!info
->clock_crystal_freq
) {
514 fprintf(stderr
, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
515 info
->clock_crystal_freq
= 1;
517 if (info
->chip_class
>= GFX10
) {
518 info
->tcc_cache_line_size
= 128;
520 if (info
->drm_minor
>= 35) {
521 info
->tcc_harvested
= device_info
.tcc_disabled_mask
!= 0;
523 /* This is a hack, but it's all we can do without a kernel upgrade. */
524 info
->tcc_harvested
=
525 (info
->vram_size
/ info
->num_tcc_blocks
) != 512*1024*1024;
528 info
->tcc_cache_line_size
= 64;
530 info
->gb_addr_config
= amdinfo
->gb_addr_cfg
;
531 if (info
->chip_class
== GFX9
) {
532 info
->num_tile_pipes
= 1 << G_0098F8_NUM_PIPES(amdinfo
->gb_addr_cfg
);
533 info
->pipe_interleave_bytes
=
534 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo
->gb_addr_cfg
);
536 info
->num_tile_pipes
= cik_get_num_tile_pipes(amdinfo
);
537 info
->pipe_interleave_bytes
=
538 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo
->gb_addr_cfg
);
540 info
->r600_has_virtual_memory
= true;
542 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
543 * 16KB makes some SIMDs unoccupied).
545 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
547 info
->lds_size_per_workgroup
= info
->chip_class
>= GFX10
? 128 * 1024 : 64 * 1024;
548 info
->lds_granularity
= info
->chip_class
>= GFX7
? 128 * 4 : 64 * 4;
550 assert(util_is_power_of_two_or_zero(dma
.available_rings
+ 1));
551 assert(util_is_power_of_two_or_zero(compute
.available_rings
+ 1));
553 info
->has_graphics
= gfx
.available_rings
> 0;
554 info
->num_rings
[RING_GFX
] = util_bitcount(gfx
.available_rings
);
555 info
->num_rings
[RING_COMPUTE
] = util_bitcount(compute
.available_rings
);
556 info
->num_rings
[RING_DMA
] = util_bitcount(dma
.available_rings
);
557 info
->num_rings
[RING_UVD
] = util_bitcount(uvd
.available_rings
);
558 info
->num_rings
[RING_VCE
] = util_bitcount(vce
.available_rings
);
559 info
->num_rings
[RING_UVD_ENC
] = util_bitcount(uvd_enc
.available_rings
);
560 info
->num_rings
[RING_VCN_DEC
] = util_bitcount(vcn_dec
.available_rings
);
561 info
->num_rings
[RING_VCN_ENC
] = util_bitcount(vcn_enc
.available_rings
);
562 info
->num_rings
[RING_VCN_JPEG
] = util_bitcount(vcn_jpeg
.available_rings
);
564 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
565 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
566 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
568 info
->has_clear_state
= info
->chip_class
>= GFX7
;
570 info
->has_distributed_tess
= info
->chip_class
>= GFX10
||
571 (info
->chip_class
>= GFX8
&& info
->max_se
>= 2);
573 info
->has_dcc_constant_encode
= info
->family
== CHIP_RAVEN2
||
574 info
->family
== CHIP_RENOIR
||
575 info
->chip_class
>= GFX10
;
577 info
->has_rbplus
= info
->family
== CHIP_STONEY
||
578 info
->chip_class
>= GFX9
;
580 /* Some chips have RB+ registers, but don't support RB+. Those must
583 info
->rbplus_allowed
= info
->has_rbplus
&&
584 (info
->family
== CHIP_STONEY
||
585 info
->family
== CHIP_VEGA12
||
586 info
->family
== CHIP_RAVEN
||
587 info
->family
== CHIP_RAVEN2
||
588 info
->family
== CHIP_RENOIR
||
589 info
->chip_class
>= GFX10_3
);
591 info
->has_out_of_order_rast
= info
->chip_class
>= GFX8
&&
592 info
->chip_class
<= GFX9
&&
595 /* Whether chips support double rate packed math instructions. */
596 info
->has_packed_math_16bit
= info
->chip_class
>= GFX9
;
598 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
599 info
->has_load_ctx_reg_pkt
= info
->chip_class
>= GFX9
||
600 (info
->chip_class
>= GFX8
&&
601 info
->me_fw_feature
>= 41);
603 info
->cpdma_prefetch_writes_memory
= info
->chip_class
<= GFX8
;
605 info
->has_gfx9_scissor_bug
= info
->family
== CHIP_VEGA10
||
606 info
->family
== CHIP_RAVEN
;
608 info
->has_tc_compat_zrange_bug
= info
->chip_class
>= GFX8
&&
609 info
->chip_class
<= GFX9
;
611 info
->has_msaa_sample_loc_bug
= (info
->family
>= CHIP_POLARIS10
&&
612 info
->family
<= CHIP_POLARIS12
) ||
613 info
->family
== CHIP_VEGA10
||
614 info
->family
== CHIP_RAVEN
;
616 info
->has_ls_vgpr_init_bug
= info
->family
== CHIP_VEGA10
||
617 info
->family
== CHIP_RAVEN
;
619 /* Get the number of good compute units. */
620 info
->num_good_compute_units
= 0;
621 for (i
= 0; i
< info
->max_se
; i
++) {
622 for (j
= 0; j
< info
->max_sh_per_se
; j
++) {
624 * The cu bitmap in amd gpu info structure is
625 * 4x4 size array, and it's usually suitable for Vega
626 * ASICs which has 4*2 SE/SH layout.
627 * But for Arcturus, SE/SH layout is changed to 8*1.
628 * To mostly reduce the impact, we make it compatible
629 * with current bitmap array as below:
630 * SE4,SH0 --> cu_bitmap[0][1]
631 * SE5,SH0 --> cu_bitmap[1][1]
632 * SE6,SH0 --> cu_bitmap[2][1]
633 * SE7,SH0 --> cu_bitmap[3][1]
635 info
->cu_mask
[i
%4][j
+i
/4] = amdinfo
->cu_bitmap
[i
%4][j
+i
/4];
636 info
->num_good_compute_units
+=
637 util_bitcount(info
->cu_mask
[i
][j
]);
641 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
642 * and max - min <= 2.
644 unsigned cu_group
= info
->chip_class
>= GFX10
? 2 : 1;
645 info
->max_good_cu_per_sa
= DIV_ROUND_UP(info
->num_good_compute_units
,
646 (info
->max_se
* info
->max_sh_per_se
* cu_group
)) * cu_group
;
647 info
->min_good_cu_per_sa
= (info
->num_good_compute_units
/
648 (info
->max_se
* info
->max_sh_per_se
* cu_group
)) * cu_group
;
650 memcpy(info
->si_tile_mode_array
, amdinfo
->gb_tile_mode
,
651 sizeof(amdinfo
->gb_tile_mode
));
652 info
->enabled_rb_mask
= amdinfo
->enabled_rb_pipes_mask
;
654 memcpy(info
->cik_macrotile_mode_array
, amdinfo
->gb_macro_tile_mode
,
655 sizeof(amdinfo
->gb_macro_tile_mode
));
657 info
->pte_fragment_size
= alignment_info
.size_local
;
658 info
->gart_page_size
= alignment_info
.size_remote
;
660 if (info
->chip_class
== GFX6
)
661 info
->gfx_ib_pad_with_type2
= true;
663 unsigned ib_align
= 0;
664 ib_align
= MAX2(ib_align
, gfx
.ib_start_alignment
);
665 ib_align
= MAX2(ib_align
, gfx
.ib_size_alignment
);
666 ib_align
= MAX2(ib_align
, compute
.ib_start_alignment
);
667 ib_align
= MAX2(ib_align
, compute
.ib_size_alignment
);
668 ib_align
= MAX2(ib_align
, dma
.ib_start_alignment
);
669 ib_align
= MAX2(ib_align
, dma
.ib_size_alignment
);
670 ib_align
= MAX2(ib_align
, uvd
.ib_start_alignment
);
671 ib_align
= MAX2(ib_align
, uvd
.ib_size_alignment
);
672 ib_align
= MAX2(ib_align
, uvd_enc
.ib_start_alignment
);
673 ib_align
= MAX2(ib_align
, uvd_enc
.ib_size_alignment
);
674 ib_align
= MAX2(ib_align
, vce
.ib_start_alignment
);
675 ib_align
= MAX2(ib_align
, vce
.ib_size_alignment
);
676 ib_align
= MAX2(ib_align
, vcn_dec
.ib_start_alignment
);
677 ib_align
= MAX2(ib_align
, vcn_dec
.ib_size_alignment
);
678 ib_align
= MAX2(ib_align
, vcn_enc
.ib_start_alignment
);
679 ib_align
= MAX2(ib_align
, vcn_enc
.ib_size_alignment
);
680 ib_align
= MAX2(ib_align
, vcn_jpeg
.ib_start_alignment
);
681 ib_align
= MAX2(ib_align
, vcn_jpeg
.ib_size_alignment
);
682 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
683 if (info
->chip_class
>= GFX9
)
684 ib_align
= MAX2(ib_align
, info
->tcc_cache_line_size
);
686 info
->ib_alignment
= ib_align
;
688 if ((info
->drm_minor
>= 31 &&
689 (info
->family
== CHIP_RAVEN
||
690 info
->family
== CHIP_RAVEN2
||
691 info
->family
== CHIP_RENOIR
)) ||
692 (info
->drm_minor
>= 34 &&
693 (info
->family
== CHIP_NAVI12
||
694 info
->family
== CHIP_NAVI14
))) {
695 if (info
->num_render_backends
== 1)
696 info
->use_display_dcc_unaligned
= true;
698 info
->use_display_dcc_with_retile_blit
= true;
701 info
->has_gds_ordered_append
= info
->chip_class
>= GFX7
&&
702 info
->drm_minor
>= 29;
704 if (info
->chip_class
>= GFX9
) {
705 unsigned pc_lines
= 0;
707 switch (info
->family
) {
730 info
->pc_lines
= pc_lines
;
732 if (info
->chip_class
>= GFX10
) {
733 info
->pbb_max_alloc_count
= pc_lines
/ 3;
735 info
->pbb_max_alloc_count
=
736 MIN2(128, pc_lines
/ (4 * info
->max_se
));
740 /* The number of SDPs is the same as the number of TCCs for now. */
741 if (info
->chip_class
>= GFX10
)
742 info
->num_sdp_interfaces
= device_info
.num_tcc_blocks
;
744 if (info
->chip_class
>= GFX10_3
)
745 info
->max_wave64_per_simd
= 16;
746 else if (info
->chip_class
== GFX10
)
747 info
->max_wave64_per_simd
= 20;
748 else if (info
->family
>= CHIP_POLARIS10
&& info
->family
<= CHIP_VEGAM
)
749 info
->max_wave64_per_simd
= 8;
751 info
->max_wave64_per_simd
= 10;
753 /* The number is per SIMD. There is enough SGPRs for the maximum number
754 * of Wave32, which is double the number for Wave64.
756 if (info
->chip_class
>= GFX10
) {
757 info
->num_physical_sgprs_per_simd
= 128 * info
->max_wave64_per_simd
* 2;
758 info
->min_sgpr_alloc
= 128;
759 info
->sgpr_alloc_granularity
= 128;
760 /* Don't use late alloc on small chips. */
761 info
->use_late_alloc
= info
->num_render_backends
> 4;
762 } else if (info
->chip_class
>= GFX8
) {
763 info
->num_physical_sgprs_per_simd
= 800;
764 info
->min_sgpr_alloc
= 16;
765 info
->sgpr_alloc_granularity
= 16;
766 info
->use_late_alloc
= true;
768 info
->num_physical_sgprs_per_simd
= 512;
769 info
->min_sgpr_alloc
= 8;
770 info
->sgpr_alloc_granularity
= 8;
771 /* Potential hang on Kabini: */
772 info
->use_late_alloc
= info
->family
!= CHIP_KABINI
;
775 info
->max_sgpr_alloc
= info
->family
== CHIP_TONGA
||
776 info
->family
== CHIP_ICELAND
? 96 : 104;
778 info
->min_wave64_vgpr_alloc
= 4;
779 info
->max_vgpr_alloc
= 256;
780 info
->wave64_vgpr_alloc_granularity
= 4;
782 info
->num_physical_wave64_vgprs_per_simd
= info
->chip_class
>= GFX10
? 512 : 256;
783 info
->num_simd_per_compute_unit
= info
->chip_class
>= GFX10
? 2 : 4;
788 void ac_compute_driver_uuid(char *uuid
, size_t size
)
790 char amd_uuid
[] = "AMD-MESA-DRV";
792 assert(size
>= sizeof(amd_uuid
));
794 memset(uuid
, 0, size
);
795 strncpy(uuid
, amd_uuid
, size
);
798 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
)
800 uint32_t *uint_uuid
= (uint32_t*)uuid
;
802 assert(size
>= sizeof(uint32_t)*4);
805 * Use the device info directly instead of using a sha1. GL/VK UUIDs
806 * are 16 byte vs 20 byte for sha1, and the truncation that would be
807 * required would get rid of part of the little entropy we have.
809 memset(uuid
, 0, size
);
810 uint_uuid
[0] = info
->pci_domain
;
811 uint_uuid
[1] = info
->pci_bus
;
812 uint_uuid
[2] = info
->pci_dev
;
813 uint_uuid
[3] = info
->pci_func
;
816 void ac_print_gpu_info(struct radeon_info
*info
)
818 printf("Device info:\n");
819 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
820 info
->pci_domain
, info
->pci_bus
,
821 info
->pci_dev
, info
->pci_func
);
823 printf(" name = %s\n", info
->name
);
824 printf(" marketing_name = %s\n", info
->marketing_name
);
825 printf(" is_pro_graphics = %u\n", info
->is_pro_graphics
);
826 printf(" pci_id = 0x%x\n", info
->pci_id
);
827 printf(" pci_rev_id = 0x%x\n", info
->pci_rev_id
);
828 printf(" family = %i\n", info
->family
);
829 printf(" chip_class = %i\n", info
->chip_class
);
830 printf(" family_id = %i\n", info
->family_id
);
831 printf(" chip_external_rev = %i\n", info
->chip_external_rev
);
832 printf(" clock_crystal_freq = %i\n", info
->clock_crystal_freq
);
834 printf("Features:\n");
835 printf(" has_graphics = %i\n", info
->has_graphics
);
836 printf(" num_rings[RING_GFX] = %i\n", info
->num_rings
[RING_GFX
]);
837 printf(" num_rings[RING_DMA] = %i\n", info
->num_rings
[RING_DMA
]);
838 printf(" num_rings[RING_COMPUTE] = %u\n", info
->num_rings
[RING_COMPUTE
]);
839 printf(" num_rings[RING_UVD] = %i\n", info
->num_rings
[RING_UVD
]);
840 printf(" num_rings[RING_VCE] = %i\n", info
->num_rings
[RING_VCE
]);
841 printf(" num_rings[RING_UVD_ENC] = %i\n", info
->num_rings
[RING_UVD_ENC
]);
842 printf(" num_rings[RING_VCN_DEC] = %i\n", info
->num_rings
[RING_VCN_DEC
]);
843 printf(" num_rings[RING_VCN_ENC] = %i\n", info
->num_rings
[RING_VCN_ENC
]);
844 printf(" num_rings[RING_VCN_JPEG] = %i\n", info
->num_rings
[RING_VCN_JPEG
]);
845 printf(" has_clear_state = %u\n", info
->has_clear_state
);
846 printf(" has_distributed_tess = %u\n", info
->has_distributed_tess
);
847 printf(" has_dcc_constant_encode = %u\n", info
->has_dcc_constant_encode
);
848 printf(" has_rbplus = %u\n", info
->has_rbplus
);
849 printf(" rbplus_allowed = %u\n", info
->rbplus_allowed
);
850 printf(" has_load_ctx_reg_pkt = %u\n", info
->has_load_ctx_reg_pkt
);
851 printf(" has_out_of_order_rast = %u\n", info
->has_out_of_order_rast
);
852 printf(" cpdma_prefetch_writes_memory = %u\n", info
->cpdma_prefetch_writes_memory
);
853 printf(" has_gfx9_scissor_bug = %i\n", info
->has_gfx9_scissor_bug
);
854 printf(" has_tc_compat_zrange_bug = %i\n", info
->has_tc_compat_zrange_bug
);
855 printf(" has_msaa_sample_loc_bug = %i\n", info
->has_msaa_sample_loc_bug
);
856 printf(" has_ls_vgpr_init_bug = %i\n", info
->has_ls_vgpr_init_bug
);
858 printf("Display features:\n");
859 printf(" use_display_dcc_unaligned = %u\n", info
->use_display_dcc_unaligned
);
860 printf(" use_display_dcc_with_retile_blit = %u\n", info
->use_display_dcc_with_retile_blit
);
862 printf("Memory info:\n");
863 printf(" pte_fragment_size = %u\n", info
->pte_fragment_size
);
864 printf(" gart_page_size = %u\n", info
->gart_page_size
);
865 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info
->gart_size
, 1024*1024));
866 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_size
, 1024*1024));
867 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_vis_size
, 1024*1024));
868 printf(" vram_type = %i\n", info
->vram_type
);
869 printf(" vram_bit_width = %i\n", info
->vram_bit_width
);
870 printf(" gds_size = %u kB\n", info
->gds_size
/ 1024);
871 printf(" gds_gfx_partition_size = %u kB\n", info
->gds_gfx_partition_size
/ 1024);
872 printf(" max_alloc_size = %i MB\n",
873 (int)DIV_ROUND_UP(info
->max_alloc_size
, 1024*1024));
874 printf(" min_alloc_size = %u\n", info
->min_alloc_size
);
875 printf(" address32_hi = %u\n", info
->address32_hi
);
876 printf(" has_dedicated_vram = %u\n", info
->has_dedicated_vram
);
877 printf(" num_sdp_interfaces = %u\n", info
->num_sdp_interfaces
);
878 printf(" num_tcc_blocks = %i\n", info
->num_tcc_blocks
);
879 printf(" tcc_cache_line_size = %u\n", info
->tcc_cache_line_size
);
880 printf(" tcc_harvested = %u\n", info
->tcc_harvested
);
881 printf(" pc_lines = %u\n", info
->pc_lines
);
882 printf(" lds_size_per_workgroup = %u\n", info
->lds_size_per_workgroup
);
883 printf(" lds_granularity = %i\n", info
->lds_granularity
);
884 printf(" max_memory_clock = %i\n", info
->max_memory_clock
);
885 printf(" ce_ram_size = %i\n", info
->ce_ram_size
);
886 printf(" l1_cache_size = %i\n", info
->l1_cache_size
);
887 printf(" l2_cache_size = %i\n", info
->l2_cache_size
);
889 printf("CP info:\n");
890 printf(" gfx_ib_pad_with_type2 = %i\n", info
->gfx_ib_pad_with_type2
);
891 printf(" ib_alignment = %u\n", info
->ib_alignment
);
892 printf(" me_fw_version = %i\n", info
->me_fw_version
);
893 printf(" me_fw_feature = %i\n", info
->me_fw_feature
);
894 printf(" pfp_fw_version = %i\n", info
->pfp_fw_version
);
895 printf(" pfp_fw_feature = %i\n", info
->pfp_fw_feature
);
896 printf(" ce_fw_version = %i\n", info
->ce_fw_version
);
897 printf(" ce_fw_feature = %i\n", info
->ce_fw_feature
);
899 printf("Multimedia info:\n");
900 printf(" has_hw_decode = %u\n", info
->has_hw_decode
);
901 printf(" uvd_enc_supported = %u\n", info
->uvd_enc_supported
);
902 printf(" uvd_fw_version = %u\n", info
->uvd_fw_version
);
903 printf(" vce_fw_version = %u\n", info
->vce_fw_version
);
904 printf(" vce_harvest_config = %i\n", info
->vce_harvest_config
);
906 printf("Kernel & winsys capabilities:\n");
907 printf(" drm = %i.%i.%i\n", info
->drm_major
,
908 info
->drm_minor
, info
->drm_patchlevel
);
909 printf(" has_userptr = %i\n", info
->has_userptr
);
910 printf(" has_syncobj = %u\n", info
->has_syncobj
);
911 printf(" has_syncobj_wait_for_submit = %u\n", info
->has_syncobj_wait_for_submit
);
912 printf(" has_fence_to_handle = %u\n", info
->has_fence_to_handle
);
913 printf(" has_ctx_priority = %u\n", info
->has_ctx_priority
);
914 printf(" has_local_buffers = %u\n", info
->has_local_buffers
);
915 printf(" kernel_flushes_hdp_before_ib = %u\n", info
->kernel_flushes_hdp_before_ib
);
916 printf(" htile_cmask_support_1d_tiling = %u\n", info
->htile_cmask_support_1d_tiling
);
917 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info
->si_TA_CS_BC_BASE_ADDR_allowed
);
918 printf(" has_bo_metadata = %u\n", info
->has_bo_metadata
);
919 printf(" has_gpu_reset_status_query = %u\n", info
->has_gpu_reset_status_query
);
920 printf(" has_eqaa_surface_allocator = %u\n", info
->has_eqaa_surface_allocator
);
921 printf(" has_format_bc1_through_bc7 = %u\n", info
->has_format_bc1_through_bc7
);
922 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info
->kernel_flushes_tc_l2_after_ib
);
923 printf(" has_indirect_compute_dispatch = %u\n", info
->has_indirect_compute_dispatch
);
924 printf(" has_unaligned_shader_loads = %u\n", info
->has_unaligned_shader_loads
);
925 printf(" has_sparse_vm_mappings = %u\n", info
->has_sparse_vm_mappings
);
926 printf(" has_2d_tiling = %u\n", info
->has_2d_tiling
);
927 printf(" has_read_registers_query = %u\n", info
->has_read_registers_query
);
928 printf(" has_gds_ordered_append = %u\n", info
->has_gds_ordered_append
);
929 printf(" has_scheduled_fence_dependency = %u\n", info
->has_scheduled_fence_dependency
);
931 printf("Shader core info:\n");
932 printf(" max_shader_clock = %i\n", info
->max_shader_clock
);
933 printf(" num_good_compute_units = %i\n", info
->num_good_compute_units
);
934 printf(" max_good_cu_per_sa = %i\n", info
->max_good_cu_per_sa
);
935 printf(" min_good_cu_per_sa = %i\n", info
->min_good_cu_per_sa
);
936 printf(" max_se = %i\n", info
->max_se
);
937 printf(" max_sh_per_se = %i\n", info
->max_sh_per_se
);
938 printf(" max_wave64_per_simd = %i\n", info
->max_wave64_per_simd
);
939 printf(" num_physical_sgprs_per_simd = %i\n", info
->num_physical_sgprs_per_simd
);
940 printf(" num_physical_wave64_vgprs_per_simd = %i\n", info
->num_physical_wave64_vgprs_per_simd
);
941 printf(" num_simd_per_compute_unit = %i\n", info
->num_simd_per_compute_unit
);
942 printf(" min_sgpr_alloc = %i\n", info
->min_sgpr_alloc
);
943 printf(" max_sgpr_alloc = %i\n", info
->max_sgpr_alloc
);
944 printf(" sgpr_alloc_granularity = %i\n", info
->sgpr_alloc_granularity
);
945 printf(" min_wave64_vgpr_alloc = %i\n", info
->min_wave64_vgpr_alloc
);
946 printf(" max_vgpr_alloc = %i\n", info
->max_vgpr_alloc
);
947 printf(" wave64_vgpr_alloc_granularity = %i\n", info
->wave64_vgpr_alloc_granularity
);
949 printf("Render backend info:\n");
950 printf(" pa_sc_tile_steering_override = 0x%x\n", info
->pa_sc_tile_steering_override
);
951 printf(" num_render_backends = %i\n", info
->num_render_backends
);
952 printf(" num_tile_pipes = %i\n", info
->num_tile_pipes
);
953 printf(" pipe_interleave_bytes = %i\n", info
->pipe_interleave_bytes
);
954 printf(" enabled_rb_mask = 0x%x\n", info
->enabled_rb_mask
);
955 printf(" max_alignment = %u\n", (unsigned)info
->max_alignment
);
956 printf(" pbb_max_alloc_count = %u\n", info
->pbb_max_alloc_count
);
958 printf("GB_ADDR_CONFIG: 0x%08x\n", info
->gb_addr_config
);
959 if (info
->chip_class
>= GFX10
) {
960 printf(" num_pipes = %u\n",
961 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
962 printf(" pipe_interleave_size = %u\n",
963 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info
->gb_addr_config
));
964 printf(" max_compressed_frags = %u\n",
965 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info
->gb_addr_config
));
966 } else if (info
->chip_class
== GFX9
) {
967 printf(" num_pipes = %u\n",
968 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
969 printf(" pipe_interleave_size = %u\n",
970 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info
->gb_addr_config
));
971 printf(" max_compressed_frags = %u\n",
972 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info
->gb_addr_config
));
973 printf(" bank_interleave_size = %u\n",
974 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
975 printf(" num_banks = %u\n",
976 1 << G_0098F8_NUM_BANKS(info
->gb_addr_config
));
977 printf(" shader_engine_tile_size = %u\n",
978 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
979 printf(" num_shader_engines = %u\n",
980 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info
->gb_addr_config
));
981 printf(" num_gpus = %u (raw)\n",
982 G_0098F8_NUM_GPUS_GFX9(info
->gb_addr_config
));
983 printf(" multi_gpu_tile_size = %u (raw)\n",
984 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
985 printf(" num_rb_per_se = %u\n",
986 1 << G_0098F8_NUM_RB_PER_SE(info
->gb_addr_config
));
987 printf(" row_size = %u\n",
988 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
989 printf(" num_lower_pipes = %u (raw)\n",
990 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
991 printf(" se_enable = %u (raw)\n",
992 G_0098F8_SE_ENABLE(info
->gb_addr_config
));
994 printf(" num_pipes = %u\n",
995 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
996 printf(" pipe_interleave_size = %u\n",
997 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info
->gb_addr_config
));
998 printf(" bank_interleave_size = %u\n",
999 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
1000 printf(" num_shader_engines = %u\n",
1001 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info
->gb_addr_config
));
1002 printf(" shader_engine_tile_size = %u\n",
1003 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
1004 printf(" num_gpus = %u (raw)\n",
1005 G_0098F8_NUM_GPUS_GFX6(info
->gb_addr_config
));
1006 printf(" multi_gpu_tile_size = %u (raw)\n",
1007 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
1008 printf(" row_size = %u\n",
1009 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
1010 printf(" num_lower_pipes = %u (raw)\n",
1011 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
1016 ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
)
1018 if (chip_class
>= GFX9
)
1037 case CHIP_POLARIS10
:
1038 case CHIP_POLARIS11
:
1039 case CHIP_POLARIS12
:
1043 unreachable("Unknown GPU");
1048 ac_get_raster_config(struct radeon_info
*info
,
1049 uint32_t *raster_config_p
,
1050 uint32_t *raster_config_1_p
,
1051 uint32_t *se_tile_repeat_p
)
1053 unsigned raster_config
, raster_config_1
, se_tile_repeat
;
1055 switch (info
->family
) {
1060 raster_config
= 0x00000000;
1061 raster_config_1
= 0x00000000;
1065 raster_config
= 0x0000124a;
1066 raster_config_1
= 0x00000000;
1068 /* 1 SE / 2 RBs (Oland is special) */
1070 raster_config
= 0x00000082;
1071 raster_config_1
= 0x00000000;
1077 raster_config
= 0x00000002;
1078 raster_config_1
= 0x00000000;
1082 case CHIP_POLARIS11
:
1083 case CHIP_POLARIS12
:
1084 raster_config
= 0x16000012;
1085 raster_config_1
= 0x00000000;
1090 raster_config
= 0x2a00126a;
1091 raster_config_1
= 0x00000000;
1095 case CHIP_POLARIS10
:
1096 raster_config
= 0x16000012;
1097 raster_config_1
= 0x0000002a;
1099 /* 4 SEs / 16 RBs */
1103 raster_config
= 0x3a00161a;
1104 raster_config_1
= 0x0000002e;
1108 "ac: Unknown GPU, using 0 for raster_config\n");
1109 raster_config
= 0x00000000;
1110 raster_config_1
= 0x00000000;
1114 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1115 * This decreases performance by up to 50% when the RB is the bottleneck.
1117 if (info
->family
== CHIP_KAVERI
&& !info
->is_amdgpu
)
1118 raster_config
= 0x00000000;
1120 /* Fiji: Old kernels have incorrect tiling config. This decreases
1121 * RB performance by 25%. (it disables 1 RB in the second packer)
1123 if (info
->family
== CHIP_FIJI
&&
1124 info
->cik_macrotile_mode_array
[0] == 0x000000e8) {
1125 raster_config
= 0x16000012;
1126 raster_config_1
= 0x0000002a;
1129 unsigned se_width
= 8 << G_028350_SE_XSEL_GFX6(raster_config
);
1130 unsigned se_height
= 8 << G_028350_SE_YSEL_GFX6(raster_config
);
1132 /* I don't know how to calculate this, though this is probably a good guess. */
1133 se_tile_repeat
= MAX2(se_width
, se_height
) * info
->max_se
;
1135 *raster_config_p
= raster_config
;
1136 *raster_config_1_p
= raster_config_1
;
1137 if (se_tile_repeat_p
)
1138 *se_tile_repeat_p
= se_tile_repeat
;
1142 ac_get_harvested_configs(struct radeon_info
*info
,
1143 unsigned raster_config
,
1144 unsigned *cik_raster_config_1_p
,
1145 unsigned *raster_config_se
)
1147 unsigned sh_per_se
= MAX2(info
->max_sh_per_se
, 1);
1148 unsigned num_se
= MAX2(info
->max_se
, 1);
1149 unsigned rb_mask
= info
->enabled_rb_mask
;
1150 unsigned num_rb
= MIN2(info
->num_render_backends
, 16);
1151 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
1152 unsigned rb_per_se
= num_rb
/ num_se
;
1153 unsigned se_mask
[4];
1156 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
1157 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
1158 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
1159 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
1161 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
1162 assert(sh_per_se
== 1 || sh_per_se
== 2);
1163 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
1166 if (info
->chip_class
>= GFX7
) {
1167 unsigned raster_config_1
= *cik_raster_config_1_p
;
1168 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
1169 (!se_mask
[2] && !se_mask
[3]))) {
1170 raster_config_1
&= C_028354_SE_PAIR_MAP
;
1172 if (!se_mask
[0] && !se_mask
[1]) {
1174 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
1177 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
1179 *cik_raster_config_1_p
= raster_config_1
;
1183 for (se
= 0; se
< num_se
; se
++) {
1184 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
1185 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
1186 int idx
= (se
/ 2) * 2;
1188 raster_config_se
[se
] = raster_config
;
1189 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
1190 raster_config_se
[se
] &= C_028350_SE_MAP
;
1192 if (!se_mask
[idx
]) {
1193 raster_config_se
[se
] |=
1194 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
1196 raster_config_se
[se
] |=
1197 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
1201 pkr0_mask
&= rb_mask
;
1202 pkr1_mask
&= rb_mask
;
1203 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
1204 raster_config_se
[se
] &= C_028350_PKR_MAP
;
1207 raster_config_se
[se
] |=
1208 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
1210 raster_config_se
[se
] |=
1211 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
1215 if (rb_per_se
>= 2) {
1216 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
1217 unsigned rb1_mask
= rb0_mask
<< 1;
1219 rb0_mask
&= rb_mask
;
1220 rb1_mask
&= rb_mask
;
1221 if (!rb0_mask
|| !rb1_mask
) {
1222 raster_config_se
[se
] &= C_028350_RB_MAP_PKR0
;
1225 raster_config_se
[se
] |=
1226 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
1228 raster_config_se
[se
] |=
1229 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
1233 if (rb_per_se
> 2) {
1234 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
1235 rb1_mask
= rb0_mask
<< 1;
1236 rb0_mask
&= rb_mask
;
1237 rb1_mask
&= rb_mask
;
1238 if (!rb0_mask
|| !rb1_mask
) {
1239 raster_config_se
[se
] &= C_028350_RB_MAP_PKR1
;
1242 raster_config_se
[se
] |=
1243 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
1245 raster_config_se
[se
] |=
1246 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
1254 unsigned ac_get_compute_resource_limits(struct radeon_info
*info
,
1255 unsigned waves_per_threadgroup
,
1256 unsigned max_waves_per_sh
,
1257 unsigned threadgroups_per_cu
)
1259 unsigned compute_resource_limits
=
1260 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
1262 if (info
->chip_class
>= GFX7
) {
1263 unsigned num_cu_per_se
= info
->num_good_compute_units
/
1266 /* Force even distribution on all SIMDs in CU if the workgroup
1267 * size is 64. This has shown some good improvements if # of CUs
1268 * per SE is not a multiple of 4.
1270 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
1271 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
1273 assert(threadgroups_per_cu
>= 1 && threadgroups_per_cu
<= 8);
1274 compute_resource_limits
|= S_00B854_WAVES_PER_SH(max_waves_per_sh
) |
1275 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu
- 1);
1278 if (max_waves_per_sh
) {
1279 unsigned limit_div16
= DIV_ROUND_UP(max_waves_per_sh
, 16);
1280 compute_resource_limits
|= S_00B854_WAVES_PER_SH_SI(limit_div16
);
1283 return compute_resource_limits
;