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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 if (dst
.size() == 1) {
1530 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1531 } else if (dst
.size() == 2) {
1532 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1533 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1536 nir_print_instr(&instr
->instr
, stderr
);
1537 fprintf(stderr
, "\n");
1542 if (dst
.size() == 1) {
1543 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1544 } else if (dst
.size() == 2) {
1545 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1546 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.size() == 1) {
1558 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1559 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1561 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1562 } else if (dst
.size() == 2) {
1563 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]),
1565 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1570 nir_print_instr(&instr
->instr
, stderr
);
1571 fprintf(stderr
, "\n");
1576 if (dst
.size() == 1) {
1577 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1578 } else if (dst
.size() == 2) {
1579 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1581 get_alu_src(ctx
, instr
->src
[0]),
1582 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1583 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1585 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1586 get_alu_src(ctx
, instr
->src
[0]),
1587 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 if (dst
.size() == 1) {
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1599 } else if (dst
.size() == 2) {
1600 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1601 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1602 get_alu_src(ctx
, instr
->src
[0]),
1603 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1606 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1607 get_alu_src(ctx
, instr
->src
[0]),
1608 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1611 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1612 nir_print_instr(&instr
->instr
, stderr
);
1613 fprintf(stderr
, "\n");
1617 case nir_op_fmax3
: {
1618 if (dst
.size() == 1) {
1619 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_fmin3
: {
1628 if (dst
.size() == 1) {
1629 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_fmed3
: {
1638 if (dst
.size() == 1) {
1639 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1647 case nir_op_umax3
: {
1648 if (dst
.size() == 1) {
1649 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1652 nir_print_instr(&instr
->instr
, stderr
);
1653 fprintf(stderr
, "\n");
1657 case nir_op_umin3
: {
1658 if (dst
.size() == 1) {
1659 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1661 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1662 nir_print_instr(&instr
->instr
, stderr
);
1663 fprintf(stderr
, "\n");
1667 case nir_op_umed3
: {
1668 if (dst
.size() == 1) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_imax3
: {
1678 if (dst
.size() == 1) {
1679 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1687 case nir_op_imin3
: {
1688 if (dst
.size() == 1) {
1689 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1697 case nir_op_imed3
: {
1698 if (dst
.size() == 1) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_cube_face_coord
: {
1708 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1709 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1710 emit_extract_vector(ctx
, in
, 1, v1
),
1711 emit_extract_vector(ctx
, in
, 2, v1
) };
1712 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1713 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1714 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1715 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1716 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1717 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1718 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1721 case nir_op_cube_face_index
: {
1722 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1723 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1724 emit_extract_vector(ctx
, in
, 1, v1
),
1725 emit_extract_vector(ctx
, in
, 2, v1
) };
1726 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1729 case nir_op_bcsel
: {
1730 emit_bcsel(ctx
, instr
, dst
);
1734 if (dst
.size() == 1) {
1735 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1736 } else if (dst
.size() == 2) {
1737 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1746 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1747 if (dst
.size() == 1) {
1748 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1749 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1750 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1751 } else if (dst
.size() == 2) {
1752 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1753 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1754 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1756 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1766 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1767 if (dst
.size() == 1) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1769 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1770 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1771 } else if (dst
.size() == 2) {
1772 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1773 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1774 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1776 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1777 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1779 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1780 nir_print_instr(&instr
->instr
, stderr
);
1781 fprintf(stderr
, "\n");
1786 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1787 if (dst
.size() == 1) {
1788 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1789 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1790 // TODO: confirm that this holds under any circumstances
1791 } else if (dst
.size() == 2) {
1792 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1793 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1797 nir_print_instr(&instr
->instr
, stderr
);
1798 fprintf(stderr
, "\n");
1802 case nir_op_flog2
: {
1803 if (dst
.size() == 1) {
1804 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1807 nir_print_instr(&instr
->instr
, stderr
);
1808 fprintf(stderr
, "\n");
1813 if (dst
.size() == 1) {
1814 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1815 } else if (dst
.size() == 2) {
1816 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1818 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1819 nir_print_instr(&instr
->instr
, stderr
);
1820 fprintf(stderr
, "\n");
1824 case nir_op_fexp2
: {
1825 if (dst
.size() == 1) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1834 case nir_op_fsqrt
: {
1835 if (dst
.size() == 1) {
1836 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1837 } else if (dst
.size() == 2) {
1838 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1841 nir_print_instr(&instr
->instr
, stderr
);
1842 fprintf(stderr
, "\n");
1846 case nir_op_ffract
: {
1847 if (dst
.size() == 1) {
1848 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1849 } else if (dst
.size() == 2) {
1850 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1858 case nir_op_ffloor
: {
1859 if (dst
.size() == 1) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1861 } else if (dst
.size() == 2) {
1862 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1864 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1865 nir_print_instr(&instr
->instr
, stderr
);
1866 fprintf(stderr
, "\n");
1870 case nir_op_fceil
: {
1871 if (dst
.size() == 1) {
1872 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1873 } else if (dst
.size() == 2) {
1874 if (ctx
->options
->chip_class
>= GFX7
) {
1875 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1877 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1878 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1880 /* trunc = trunc(src0)
1881 * if (src0 > 0.0 && src0 != trunc)
1884 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1885 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1886 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1887 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1888 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1889 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1890 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1893 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1894 nir_print_instr(&instr
->instr
, stderr
);
1895 fprintf(stderr
, "\n");
1899 case nir_op_ftrunc
: {
1900 if (dst
.size() == 1) {
1901 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1902 } else if (dst
.size() == 2) {
1903 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_fround_even
: {
1912 if (dst
.size() == 1) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1914 } else if (dst
.size() == 2) {
1915 if (ctx
->options
->chip_class
>= GFX7
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1918 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1919 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1921 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1924 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1925 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1926 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1927 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1928 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1929 tmp
= sub
->definitions
[0].getTemp();
1931 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1932 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1933 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1934 Temp cond
= vop3
->definitions
[0].getTemp();
1936 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1938 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1939 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1941 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1944 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1945 nir_print_instr(&instr
->instr
, stderr
);
1946 fprintf(stderr
, "\n");
1952 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1953 aco_ptr
<Instruction
> norm
;
1954 if (dst
.size() == 1) {
1955 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1956 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1958 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1959 if (ctx
->options
->chip_class
< GFX9
)
1960 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1962 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1963 bld
.vop1(opcode
, Definition(dst
), tmp
);
1965 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1966 nir_print_instr(&instr
->instr
, stderr
);
1967 fprintf(stderr
, "\n");
1971 case nir_op_ldexp
: {
1972 if (dst
.size() == 1) {
1973 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1974 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1975 get_alu_src(ctx
, instr
->src
[1]));
1976 } else if (dst
.size() == 2) {
1977 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1978 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1979 get_alu_src(ctx
, instr
->src
[1]));
1981 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1982 nir_print_instr(&instr
->instr
, stderr
);
1983 fprintf(stderr
, "\n");
1987 case nir_op_frexp_sig
: {
1988 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1989 if (dst
.regClass() == v2b
) {
1990 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
1991 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1992 } else if (dst
.regClass() == v1
) {
1993 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
1994 } else if (dst
.regClass() == v2
) {
1995 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
1997 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1998 nir_print_instr(&instr
->instr
, stderr
);
1999 fprintf(stderr
, "\n");
2003 case nir_op_frexp_exp
: {
2004 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2005 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2006 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2007 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2008 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2009 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2010 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2011 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2013 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2014 nir_print_instr(&instr
->instr
, stderr
);
2015 fprintf(stderr
, "\n");
2019 case nir_op_fsign
: {
2020 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2021 if (dst
.size() == 1) {
2022 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2023 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2024 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2025 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2026 } else if (dst
.size() == 2) {
2027 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2028 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2029 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2031 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2032 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2033 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2037 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2038 nir_print_instr(&instr
->instr
, stderr
);
2039 fprintf(stderr
, "\n");
2044 case nir_op_f2f16_rtne
: {
2045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2046 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2047 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2048 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2049 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2052 case nir_op_f2f16_rtz
: {
2053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2054 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2055 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2056 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2057 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2060 case nir_op_f2f32
: {
2061 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2062 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2063 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2064 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2066 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2067 nir_print_instr(&instr
->instr
, stderr
);
2068 fprintf(stderr
, "\n");
2072 case nir_op_f2f64
: {
2073 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2074 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2075 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2076 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2079 case nir_op_i2f32
: {
2080 assert(dst
.size() == 1);
2081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2084 case nir_op_i2f64
: {
2085 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2086 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2087 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2088 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2089 RegClass rc
= RegClass(src
.type(), 1);
2090 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2091 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2092 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2093 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2094 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2095 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2098 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2099 nir_print_instr(&instr
->instr
, stderr
);
2100 fprintf(stderr
, "\n");
2104 case nir_op_u2f32
: {
2105 assert(dst
.size() == 1);
2106 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2109 case nir_op_u2f64
: {
2110 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2111 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2112 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2113 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2114 RegClass rc
= RegClass(src
.type(), 1);
2115 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2116 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2117 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2118 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2119 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2120 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2122 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2123 nir_print_instr(&instr
->instr
, stderr
);
2124 fprintf(stderr
, "\n");
2128 case nir_op_f2i16
: {
2129 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2130 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2131 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2132 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2133 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2135 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2137 if (dst
.type() == RegType::vgpr
)
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2140 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2143 case nir_op_f2u16
: {
2144 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2145 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2146 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2147 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2148 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2150 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2152 if (dst
.type() == RegType::vgpr
)
2153 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2155 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2158 case nir_op_f2i32
: {
2159 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2160 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2161 if (dst
.type() == RegType::vgpr
)
2162 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2164 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2165 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2167 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2168 if (dst
.type() == RegType::vgpr
)
2169 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2171 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2172 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2175 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2176 nir_print_instr(&instr
->instr
, stderr
);
2177 fprintf(stderr
, "\n");
2181 case nir_op_f2u32
: {
2182 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2184 if (dst
.type() == RegType::vgpr
)
2185 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2187 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2188 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2190 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2191 if (dst
.type() == RegType::vgpr
)
2192 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2194 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2195 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2198 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2199 nir_print_instr(&instr
->instr
, stderr
);
2200 fprintf(stderr
, "\n");
2204 case nir_op_f2i64
: {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2207 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2208 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2209 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2210 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2211 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2212 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2213 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2214 Temp new_exponent
= bld
.tmp(v1
);
2215 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2216 if (ctx
->program
->chip_class
>= GFX8
)
2217 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2219 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2220 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2221 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2222 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2223 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2224 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2225 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2226 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2227 Temp new_lower
= bld
.tmp(v1
);
2228 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2229 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2230 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2232 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2233 if (src
.type() == RegType::vgpr
)
2234 src
= bld
.as_uniform(src
);
2235 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2236 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2237 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2238 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2239 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2240 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2241 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2242 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2243 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2244 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2245 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2246 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2247 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2248 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2249 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2250 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2251 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2252 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2253 Temp borrow
= bld
.tmp(s1
);
2254 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2255 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2256 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2258 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2259 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2260 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2261 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2262 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2263 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2264 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2265 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2266 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2267 if (dst
.type() == RegType::sgpr
) {
2268 lower
= bld
.as_uniform(lower
);
2269 upper
= bld
.as_uniform(upper
);
2271 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2274 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2275 nir_print_instr(&instr
->instr
, stderr
);
2276 fprintf(stderr
, "\n");
2280 case nir_op_f2u64
: {
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2283 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2284 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2285 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2286 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2287 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2288 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2289 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2290 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2291 Temp new_exponent
= bld
.tmp(v1
);
2292 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2293 if (ctx
->program
->chip_class
>= GFX8
)
2294 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2296 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2297 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2298 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2299 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2300 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2301 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2302 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2303 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2305 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2306 if (src
.type() == RegType::vgpr
)
2307 src
= bld
.as_uniform(src
);
2308 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2309 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2310 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2311 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2312 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2313 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2314 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2315 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2316 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2317 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2318 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2319 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2320 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2322 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2323 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2324 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2325 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2327 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2328 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2329 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2330 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2331 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2332 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2333 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2334 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2335 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2336 if (dst
.type() == RegType::sgpr
) {
2337 lower
= bld
.as_uniform(lower
);
2338 upper
= bld
.as_uniform(upper
);
2340 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2343 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2344 nir_print_instr(&instr
->instr
, stderr
);
2345 fprintf(stderr
, "\n");
2349 case nir_op_b2f32
: {
2350 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2351 assert(src
.regClass() == bld
.lm
);
2353 if (dst
.regClass() == s1
) {
2354 src
= bool_to_scalar_condition(ctx
, src
);
2355 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2356 } else if (dst
.regClass() == v1
) {
2357 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2359 unreachable("Wrong destination register class for nir_op_b2f32.");
2363 case nir_op_b2f64
: {
2364 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2365 assert(src
.regClass() == bld
.lm
);
2367 if (dst
.regClass() == s2
) {
2368 src
= bool_to_scalar_condition(ctx
, src
);
2369 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2370 } else if (dst
.regClass() == v2
) {
2371 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2372 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2373 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2375 unreachable("Wrong destination register class for nir_op_b2f64.");
2381 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2382 /* we can actually just say dst = src */
2383 if (src
.regClass() == s1
)
2384 bld
.copy(Definition(dst
), src
);
2386 emit_extract_vector(ctx
, src
, 0, dst
);
2389 case nir_op_i2i16
: {
2390 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2391 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2392 if (dst
.regClass() == s1
) {
2393 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2395 assert(src
.regClass() == v1b
);
2396 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2397 sdwa
->operands
[0] = Operand(src
);
2398 sdwa
->definitions
[0] = Definition(dst
);
2399 sdwa
->sel
[0] = sdwa_sbyte
;
2400 sdwa
->dst_sel
= sdwa_sword
;
2401 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2405 /* we can actually just say dst = src */
2406 if (src
.regClass() == s1
)
2407 bld
.copy(Definition(dst
), src
);
2409 emit_extract_vector(ctx
, src
, 0, dst
);
2413 case nir_op_u2u16
: {
2414 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2415 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2416 if (dst
.regClass() == s1
)
2417 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2419 assert(src
.regClass() == v1b
);
2420 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2421 sdwa
->operands
[0] = Operand(src
);
2422 sdwa
->definitions
[0] = Definition(dst
);
2423 sdwa
->sel
[0] = sdwa_ubyte
;
2424 sdwa
->dst_sel
= sdwa_uword
;
2425 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2428 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2429 /* we can actually just say dst = src */
2430 if (src
.regClass() == s1
)
2431 bld
.copy(Definition(dst
), src
);
2433 emit_extract_vector(ctx
, src
, 0, dst
);
2437 case nir_op_i2i32
: {
2438 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2439 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2440 if (dst
.regClass() == s1
) {
2441 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2443 assert(src
.regClass() == v1b
);
2444 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2445 sdwa
->operands
[0] = Operand(src
);
2446 sdwa
->definitions
[0] = Definition(dst
);
2447 sdwa
->sel
[0] = sdwa_sbyte
;
2448 sdwa
->dst_sel
= sdwa_sdword
;
2449 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2451 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2452 if (dst
.regClass() == s1
) {
2453 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2455 assert(src
.regClass() == v2b
);
2456 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2457 sdwa
->operands
[0] = Operand(src
);
2458 sdwa
->definitions
[0] = Definition(dst
);
2459 sdwa
->sel
[0] = sdwa_sword
;
2460 sdwa
->dst_sel
= sdwa_udword
;
2461 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2463 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2464 /* we can actually just say dst = src, as it would map the lower register */
2465 emit_extract_vector(ctx
, src
, 0, dst
);
2467 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2468 nir_print_instr(&instr
->instr
, stderr
);
2469 fprintf(stderr
, "\n");
2473 case nir_op_u2u32
: {
2474 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2475 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2476 if (dst
.regClass() == s1
)
2477 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2479 assert(src
.regClass() == v1b
);
2480 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2481 sdwa
->operands
[0] = Operand(src
);
2482 sdwa
->definitions
[0] = Definition(dst
);
2483 sdwa
->sel
[0] = sdwa_ubyte
;
2484 sdwa
->dst_sel
= sdwa_udword
;
2485 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2487 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2488 if (dst
.regClass() == s1
) {
2489 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2491 assert(src
.regClass() == v2b
);
2492 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2493 sdwa
->operands
[0] = Operand(src
);
2494 sdwa
->definitions
[0] = Definition(dst
);
2495 sdwa
->sel
[0] = sdwa_uword
;
2496 sdwa
->dst_sel
= sdwa_udword
;
2497 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2499 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2500 /* we can actually just say dst = src, as it would map the lower register */
2501 emit_extract_vector(ctx
, src
, 0, dst
);
2503 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2504 nir_print_instr(&instr
->instr
, stderr
);
2505 fprintf(stderr
, "\n");
2509 case nir_op_i2i64
: {
2510 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2511 if (src
.regClass() == s1
) {
2512 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2514 } else if (src
.regClass() == v1
) {
2515 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2516 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2518 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2519 nir_print_instr(&instr
->instr
, stderr
);
2520 fprintf(stderr
, "\n");
2524 case nir_op_u2u64
: {
2525 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2526 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2527 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2529 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2530 nir_print_instr(&instr
->instr
, stderr
);
2531 fprintf(stderr
, "\n");
2536 case nir_op_b2i32
: {
2537 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2538 assert(src
.regClass() == bld
.lm
);
2540 if (dst
.regClass() == s1
) {
2541 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2542 bool_to_scalar_condition(ctx
, src
, dst
);
2543 } else if (dst
.regClass() == v1
) {
2544 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2546 unreachable("Invalid register class for b2i32");
2552 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2553 assert(dst
.regClass() == bld
.lm
);
2555 if (src
.type() == RegType::vgpr
) {
2556 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2557 assert(dst
.regClass() == bld
.lm
);
2558 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2559 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2561 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2563 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2564 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2566 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2567 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2569 bool_to_vector_condition(ctx
, tmp
, dst
);
2573 case nir_op_pack_64_2x32_split
: {
2574 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2575 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2577 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2580 case nir_op_unpack_64_2x32_split_x
:
2581 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2583 case nir_op_unpack_64_2x32_split_y
:
2584 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2586 case nir_op_unpack_32_2x16_split_x
:
2587 if (dst
.type() == RegType::vgpr
) {
2588 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2590 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2593 case nir_op_unpack_32_2x16_split_y
:
2594 if (dst
.type() == RegType::vgpr
) {
2595 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2597 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2600 case nir_op_pack_32_2x16_split
: {
2601 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2602 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2603 if (dst
.regClass() == v1
) {
2604 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2606 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2607 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2608 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2612 case nir_op_pack_half_2x16
: {
2613 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2615 if (dst
.regClass() == v1
) {
2616 Temp src0
= bld
.tmp(v1
);
2617 Temp src1
= bld
.tmp(v1
);
2618 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2619 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2620 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2622 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2623 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2624 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2626 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2627 nir_print_instr(&instr
->instr
, stderr
);
2628 fprintf(stderr
, "\n");
2632 case nir_op_unpack_half_2x16_split_x
: {
2633 if (dst
.regClass() == v1
) {
2634 Builder
bld(ctx
->program
, ctx
->block
);
2635 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2637 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2638 nir_print_instr(&instr
->instr
, stderr
);
2639 fprintf(stderr
, "\n");
2643 case nir_op_unpack_half_2x16_split_y
: {
2644 if (dst
.regClass() == v1
) {
2645 Builder
bld(ctx
->program
, ctx
->block
);
2646 /* TODO: use SDWA here */
2647 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2648 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2651 nir_print_instr(&instr
->instr
, stderr
);
2652 fprintf(stderr
, "\n");
2656 case nir_op_fquantize2f16
: {
2657 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2658 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2661 if (ctx
->program
->chip_class
>= GFX8
) {
2662 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2663 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2664 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2666 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2667 * so compare the result and flush to 0 if it's smaller.
2669 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2670 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2671 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2672 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2673 cmp_res
= vop3
->definitions
[0].getTemp();
2676 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2677 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2678 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2680 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2685 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2686 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2688 if (dst
.regClass() == s1
) {
2689 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2690 } else if (dst
.regClass() == v1
) {
2691 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2694 nir_print_instr(&instr
->instr
, stderr
);
2695 fprintf(stderr
, "\n");
2699 case nir_op_bitfield_select
: {
2700 /* (mask & insert) | (~mask & base) */
2701 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2702 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2703 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2705 /* dst = (insert & bitmask) | (base & ~bitmask) */
2706 if (dst
.regClass() == s1
) {
2707 aco_ptr
<Instruction
> sop2
;
2708 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2709 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2711 if (const_insert
&& const_bitmask
) {
2712 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2714 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2715 lhs
= Operand(insert
);
2719 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2720 if (const_base
&& const_bitmask
) {
2721 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2723 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2724 rhs
= Operand(base
);
2727 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2729 } else if (dst
.regClass() == v1
) {
2730 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2731 base
= as_vgpr(ctx
, base
);
2732 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2733 insert
= as_vgpr(ctx
, insert
);
2735 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2739 nir_print_instr(&instr
->instr
, stderr
);
2740 fprintf(stderr
, "\n");
2746 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2747 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2748 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2750 if (dst
.type() == RegType::sgpr
) {
2752 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2753 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2754 if (const_offset
&& const_bits
) {
2755 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2756 extract
= Operand(const_extract
);
2760 width
= Operand(const_bits
->u32
<< 16);
2762 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2764 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2768 if (dst
.regClass() == s1
) {
2769 if (instr
->op
== nir_op_ubfe
)
2770 opcode
= aco_opcode::s_bfe_u32
;
2772 opcode
= aco_opcode::s_bfe_i32
;
2773 } else if (dst
.regClass() == s2
) {
2774 if (instr
->op
== nir_op_ubfe
)
2775 opcode
= aco_opcode::s_bfe_u64
;
2777 opcode
= aco_opcode::s_bfe_i64
;
2779 unreachable("Unsupported BFE bit size");
2782 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2786 if (dst
.regClass() == v1
) {
2787 if (instr
->op
== nir_op_ubfe
)
2788 opcode
= aco_opcode::v_bfe_u32
;
2790 opcode
= aco_opcode::v_bfe_i32
;
2792 unreachable("Unsupported BFE bit size");
2795 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2799 case nir_op_bit_count
: {
2800 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2801 if (src
.regClass() == s1
) {
2802 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2803 } else if (src
.regClass() == v1
) {
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2805 } else if (src
.regClass() == v2
) {
2806 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2807 emit_extract_vector(ctx
, src
, 1, v1
),
2808 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2809 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2810 } else if (src
.regClass() == s2
) {
2811 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2813 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2814 nir_print_instr(&instr
->instr
, stderr
);
2815 fprintf(stderr
, "\n");
2820 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2824 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2828 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2840 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2844 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2845 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2847 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2848 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2852 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2853 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2855 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2856 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2864 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2869 case nir_op_fddx_fine
:
2870 case nir_op_fddy_fine
:
2871 case nir_op_fddx_coarse
:
2872 case nir_op_fddy_coarse
: {
2873 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2874 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2875 if (instr
->op
== nir_op_fddx_fine
) {
2876 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2877 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2878 } else if (instr
->op
== nir_op_fddy_fine
) {
2879 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2880 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2882 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2883 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2884 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2886 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2890 if (ctx
->program
->chip_class
>= GFX8
) {
2891 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2892 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2894 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2895 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2896 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2898 emit_wqm(ctx
, tmp
, dst
, true);
2902 fprintf(stderr
, "Unknown NIR ALU instr: ");
2903 nir_print_instr(&instr
->instr
, stderr
);
2904 fprintf(stderr
, "\n");
2908 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2910 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2912 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2913 // which get truncated the lsb if double and msb if int
2914 // for now, we only use s_mov_b64 with 64bit inline constants
2915 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2916 assert(dst
.type() == RegType::sgpr
);
2918 Builder
bld(ctx
->program
, ctx
->block
);
2920 if (instr
->def
.bit_size
== 1) {
2921 assert(dst
.regClass() == bld
.lm
);
2922 int val
= instr
->value
[0].b
? -1 : 0;
2923 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2924 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2925 } else if (dst
.size() == 1) {
2926 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2928 assert(dst
.size() != 1);
2929 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2930 if (instr
->def
.bit_size
== 64)
2931 for (unsigned i
= 0; i
< dst
.size(); i
++)
2932 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2934 for (unsigned i
= 0; i
< dst
.size(); i
++)
2935 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2937 vec
->definitions
[0] = Definition(dst
);
2938 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2942 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2944 uint32_t new_mask
= 0;
2945 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2946 if (mask
& (1u << i
))
2947 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2951 Operand
load_lds_size_m0(isel_context
*ctx
)
2953 /* TODO: m0 does not need to be initialized on GFX9+ */
2954 Builder
bld(ctx
->program
, ctx
->block
);
2955 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2958 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2959 Temp address
, unsigned base_offset
, unsigned align
)
2961 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2963 Builder
bld(ctx
->program
, ctx
->block
);
2965 Operand m
= load_lds_size_m0(ctx
);
2967 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2968 unsigned bytes_read
= 0;
2969 unsigned result_size
= 0;
2970 unsigned total_bytes
= num_components
* elem_size_bytes
;
2971 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2972 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2973 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2975 while (bytes_read
< total_bytes
) {
2976 unsigned todo
= total_bytes
- bytes_read
;
2977 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2978 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2980 aco_opcode op
= aco_opcode::last_opcode
;
2982 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2983 op
= aco_opcode::ds_read_b128
;
2985 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2986 op
= aco_opcode::ds_read2_b64
;
2989 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2990 op
= aco_opcode::ds_read_b96
;
2992 } else if (todo
>= 8 && aligned8
) {
2993 op
= aco_opcode::ds_read_b64
;
2995 } else if (todo
>= 8 && usable_read2
) {
2996 op
= aco_opcode::ds_read2_b32
;
2999 } else if (todo
>= 4) {
3000 op
= aco_opcode::ds_read_b32
;
3005 assert(todo
% elem_size_bytes
== 0);
3006 unsigned num_elements
= todo
/ elem_size_bytes
;
3007 unsigned offset
= base_offset
+ bytes_read
;
3008 unsigned max_offset
= read2
? 1019 : 65535;
3010 Temp address_offset
= address
;
3011 if (offset
> max_offset
) {
3012 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3013 offset
= bytes_read
;
3015 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3018 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3021 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3024 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3026 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3028 if (num_components
== 1) {
3029 assert(todo
== total_bytes
);
3030 if (dst
.type() == RegType::sgpr
)
3031 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3035 if (dst
.type() == RegType::sgpr
) {
3036 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3037 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3041 if (num_elements
== 1) {
3042 result
[result_size
++] = res
;
3044 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3045 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3046 split
->operands
[0] = Operand(res
);
3047 for (unsigned i
= 0; i
< num_elements
; i
++)
3048 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3049 ctx
->block
->instructions
.emplace_back(std::move(split
));
3055 assert(result_size
== num_components
&& result_size
> 1);
3056 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3057 for (unsigned i
= 0; i
< result_size
; i
++)
3058 vec
->operands
[i
] = Operand(result
[i
]);
3059 vec
->definitions
[0] = Definition(dst
);
3060 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3061 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3066 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3068 if (start
== 0 && size
== data
.size())
3069 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3071 unsigned size_hint
= 1;
3072 auto it
= ctx
->allocated_vec
.find(data
.id());
3073 if (it
!= ctx
->allocated_vec
.end())
3074 size_hint
= it
->second
[0].size();
3075 if (size
% size_hint
|| start
% size_hint
)
3082 for (unsigned i
= 0; i
< size
; i
++)
3083 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3086 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3088 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3089 for (unsigned i
= 0; i
< size
; i
++)
3090 vec
->operands
[i
] = Operand(elems
[i
]);
3091 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3092 vec
->definitions
[0] = Definition(res
);
3093 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3097 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3099 Builder
bld(ctx
->program
, ctx
->block
);
3100 unsigned bytes_written
= 0;
3101 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3102 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3104 while (bytes_written
< total_size
* 4) {
3105 unsigned todo
= total_size
* 4 - bytes_written
;
3106 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3107 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3109 aco_opcode op
= aco_opcode::last_opcode
;
3110 bool write2
= false;
3112 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3113 op
= aco_opcode::ds_write_b128
;
3115 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3116 op
= aco_opcode::ds_write2_b64
;
3119 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3120 op
= aco_opcode::ds_write_b96
;
3122 } else if (todo
>= 8 && aligned8
) {
3123 op
= aco_opcode::ds_write_b64
;
3125 } else if (todo
>= 8 && usable_write2
) {
3126 op
= aco_opcode::ds_write2_b32
;
3129 } else if (todo
>= 4) {
3130 op
= aco_opcode::ds_write_b32
;
3136 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3137 unsigned max_offset
= write2
? 1020 : 65535;
3138 Temp address_offset
= address
;
3139 if (offset
> max_offset
) {
3140 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3141 offset
= offset1
+ bytes_written
;
3143 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3146 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3147 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3148 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3150 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3151 bld
.ds(op
, address_offset
, val
, m
, offset
);
3154 bytes_written
+= size
* 4;
3158 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3159 Temp address
, unsigned base_offset
, unsigned align
)
3161 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3162 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3164 Operand m
= load_lds_size_m0(ctx
);
3166 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3167 assert(wrmask
<= 0x0f);
3168 int start
[2], count
[2];
3169 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3170 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3171 assert(wrmask
== 0);
3173 /* one combined store is sufficient */
3174 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3175 Builder
bld(ctx
->program
, ctx
->block
);
3177 Temp address_offset
= address
;
3178 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3179 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3183 assert(count
[0] == 1);
3184 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3186 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3187 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3188 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3189 base_offset
= base_offset
/ elem_size_bytes
;
3190 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3191 base_offset
+ start
[0], base_offset
+ start
[1]);
3195 for (unsigned i
= 0; i
< 2; i
++) {
3199 unsigned elem_size_words
= elem_size_bytes
/ 4;
3200 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3201 base_offset
, start
[i
] * elem_size_bytes
, align
);
3206 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3208 unsigned align
= 16;
3210 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3216 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3217 unsigned split_cnt
= 0u, Temp dst
= Temp())
3219 Builder
bld(ctx
->program
, ctx
->block
);
3220 unsigned dword_size
= elem_size_bytes
/ 4;
3223 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3225 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3226 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3227 instr
->definitions
[0] = Definition(dst
);
3229 for (unsigned i
= 0; i
< cnt
; ++i
) {
3231 assert(arr
[i
].size() == dword_size
);
3232 allocated_vec
[i
] = arr
[i
];
3233 instr
->operands
[i
] = Operand(arr
[i
]);
3235 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3236 allocated_vec
[i
] = zero
;
3237 instr
->operands
[i
] = Operand(zero
);
3241 bld
.insert(std::move(instr
));
3244 emit_split_vector(ctx
, dst
, split_cnt
);
3246 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3251 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3253 if (const_offset
>= 4096) {
3254 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3255 const_offset
%= 4096u;
3258 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3259 else if (unlikely(voffset
.regClass() == s1
))
3260 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3261 else if (likely(voffset
.regClass() == v1
))
3262 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3264 unreachable("Unsupported register class of voffset");
3267 return const_offset
;
3270 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3271 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3274 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3275 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3277 Builder
bld(ctx
->program
, ctx
->block
);
3278 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3279 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3281 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3282 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3283 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3284 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3285 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3287 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3290 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3291 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3292 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3294 Builder
bld(ctx
->program
, ctx
->block
);
3295 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3298 if (elem_size_bytes
== 8) {
3299 elem_size_bytes
= 4;
3300 write_mask
= widen_mask(write_mask
, 2);
3303 while (write_mask
) {
3306 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3311 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3312 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3314 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3315 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3318 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3319 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3329 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3330 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3332 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3333 assert(size_dwords
>= 1 && size_dwords
<= 4);
3335 Builder
bld(ctx
->program
, ctx
->block
);
3336 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3337 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3338 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3340 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3341 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3342 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3343 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3344 /* disable_wqm */ false, /* glc */ true,
3345 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3347 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3352 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3353 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3354 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3356 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3357 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3358 assert(!!stride
!= allow_combining
);
3360 Builder
bld(ctx
->program
, ctx
->block
);
3361 unsigned split_cnt
= num_components
;
3363 if (elem_size_bytes
== 8) {
3364 elem_size_bytes
= 4;
3365 num_components
*= 2;
3369 stride
= elem_size_bytes
;
3371 unsigned load_size
= 1;
3372 if (allow_combining
) {
3373 if ((num_components
% 4) == 0)
3375 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3377 else if ((num_components
% 2) == 0)
3381 unsigned num_loads
= num_components
/ load_size
;
3382 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3384 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3385 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3386 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3389 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3392 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3394 Builder
bld(ctx
->program
, ctx
->block
);
3395 Temp offset
= base_offset
.first
;
3396 unsigned const_offset
= base_offset
.second
;
3398 if (!nir_src_is_const(*off_src
)) {
3399 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3402 /* Calculate indirect offset with stride */
3403 if (likely(indirect_offset_arg
.regClass() == v1
))
3404 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3405 else if (indirect_offset_arg
.regClass() == s1
)
3406 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3408 unreachable("Unsupported register class of indirect offset");
3410 /* Add to the supplied base offset */
3411 if (offset
.id() == 0)
3412 offset
= with_stride
;
3413 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3414 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3415 else if (offset
.size() == 1 && with_stride
.size() == 1)
3416 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3418 unreachable("Unsupported register class of indirect offset");
3420 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3421 const_offset
+= const_offset_arg
* stride
;
3424 return std::make_pair(offset
, const_offset
);
3427 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3429 Builder
bld(ctx
->program
, ctx
->block
);
3432 if (off1
.first
.id() && off2
.first
.id()) {
3433 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3434 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3435 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3436 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3438 unreachable("Unsupported register class of indirect offset");
3440 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3443 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3446 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3448 Builder
bld(ctx
->program
, ctx
->block
);
3449 unsigned const_offset
= offs
.second
* multiplier
;
3451 if (!offs
.first
.id())
3452 return std::make_pair(offs
.first
, const_offset
);
3454 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3455 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3456 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3458 return std::make_pair(offset
, const_offset
);
3461 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3463 Builder
bld(ctx
->program
, ctx
->block
);
3465 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3466 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3467 /* component is in bytes */
3468 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3470 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3471 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3472 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3475 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3477 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3480 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3482 Builder
bld(ctx
->program
, ctx
->block
);
3484 switch (ctx
->shader
->info
.stage
) {
3485 case MESA_SHADER_TESS_CTRL
:
3486 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3487 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3488 case MESA_SHADER_TESS_EVAL
:
3489 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3491 unreachable("Unsupported stage in get_tess_rel_patch_id");
3495 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3497 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3498 Builder
bld(ctx
->program
, ctx
->block
);
3500 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3501 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3503 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3505 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3506 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3508 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3509 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3510 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3512 return offset_mul(ctx
, offs
, 4u);
3515 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3517 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3518 Builder
bld(ctx
->program
, ctx
->block
);
3520 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3521 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3522 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3523 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3524 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3525 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3527 std::pair
<Temp
, unsigned> offs
= instr
3528 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3529 : std::make_pair(Temp(), 0u);
3531 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3532 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3537 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3538 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3540 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3541 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3543 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3544 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3550 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3552 Builder
bld(ctx
->program
, ctx
->block
);
3554 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3555 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3557 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3559 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3560 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3561 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3563 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3564 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3569 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3571 Builder
bld(ctx
->program
, ctx
->block
);
3573 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3574 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3575 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3577 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3578 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3579 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3580 unsigned attr_stride
= ctx
->tcs_num_patches
;
3582 std::pair
<Temp
, unsigned> offs
= instr
3583 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3584 : std::make_pair(Temp(), 0u);
3586 if (const_base_offset
)
3587 offs
.second
+= const_base_offset
* attr_stride
;
3589 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3590 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3591 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3596 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3598 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3599 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3601 if (!nir_src_is_const(*off_src
)) {
3607 off
+= nir_src_as_uint(*off_src
) * 16u;
3610 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3611 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3618 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3620 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3621 unsigned component
= nir_intrinsic_component(instr
);
3622 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3624 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3625 if (off_instr
->type
!= nir_instr_type_load_const
)
3628 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3629 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3631 if (instr
->src
[0].ssa
->bit_size
== 64)
3632 write_mask
= widen_mask(write_mask
, 2);
3634 for (unsigned i
= 0; i
< 8; ++i
) {
3635 if (write_mask
& (1 << i
)) {
3636 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3637 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3645 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3647 /* Only TCS per-vertex inputs are supported by this function.
3648 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3650 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3653 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3654 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3655 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3656 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3657 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3658 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3663 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3664 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3665 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3666 assert(vec
.size() == dst
.size());
3668 Builder
bld(ctx
->program
, ctx
->block
);
3669 bld
.copy(Definition(dst
), vec
);
3673 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3675 Builder
bld(ctx
->program
, ctx
->block
);
3677 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3678 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3679 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3680 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3682 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3683 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3684 bool indirect_write
;
3685 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3686 if (temp_only_input
&& !indirect_write
)
3690 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3691 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3692 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3693 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3694 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3698 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3699 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3700 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3701 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3702 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3703 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3704 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3705 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3706 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3707 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3708 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3709 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3710 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3712 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3713 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3714 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3716 unreachable("Invalid LS or ES stage");
3719 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3720 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3721 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3725 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3727 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3728 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3729 off
!= ctx
->tcs_tess_lvl_in_loc
;
3732 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3734 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3735 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3738 uint64_t mask
= per_vertex
3739 ? ctx
->shader
->info
.outputs_read
3740 : ctx
->shader
->info
.patch_outputs_read
;
3741 bool indirect_write
;
3742 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3743 return indirect_write
|| output_read
;
3746 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3748 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3749 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3751 Builder
bld(ctx
->program
, ctx
->block
);
3753 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3754 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3755 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3757 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3758 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3759 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3760 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3762 if (write_to_vmem
) {
3763 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3764 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3765 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3767 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3768 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3769 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3773 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3774 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3775 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3779 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3781 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3782 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3784 Builder
bld(ctx
->program
, ctx
->block
);
3786 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3787 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3788 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3789 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3791 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3794 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3796 if (ctx
->stage
== vertex_vs
||
3797 ctx
->stage
== tess_eval_vs
||
3798 ctx
->stage
== fragment_fs
||
3799 ctx
->stage
== ngg_vertex_gs
||
3800 ctx
->stage
== ngg_tess_eval_gs
||
3801 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3802 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3803 if (!stored_to_temps
) {
3804 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3805 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3806 fprintf(stderr
, "\n");
3809 } else if (ctx
->stage
== vertex_es
||
3810 ctx
->stage
== vertex_ls
||
3811 ctx
->stage
== tess_eval_es
||
3812 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3813 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3814 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3815 visit_store_ls_or_es_output(ctx
, instr
);
3816 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3817 visit_store_tcs_output(ctx
, instr
, false);
3819 unreachable("Shader stage not implemented");
3823 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3825 visit_load_tcs_output(ctx
, instr
, false);
3828 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3830 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3831 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3833 Builder
bld(ctx
->program
, ctx
->block
);
3834 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3835 if (ctx
->program
->has_16bank_lds
)
3836 interp_p1
.instr
->operands
[0].setLateKill(true);
3837 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3840 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3842 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3843 for (unsigned i
= 0; i
< num_components
; i
++)
3844 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3845 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3846 assert(num_components
== 4);
3847 Builder
bld(ctx
->program
, ctx
->block
);
3848 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3851 for (Operand
& op
: vec
->operands
)
3852 op
= op
.isUndefined() ? Operand(0u) : op
;
3854 vec
->definitions
[0] = Definition(dst
);
3855 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3856 emit_split_vector(ctx
, dst
, num_components
);
3860 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3862 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3863 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3864 unsigned idx
= nir_intrinsic_base(instr
);
3865 unsigned component
= nir_intrinsic_component(instr
);
3866 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3868 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3870 assert(offset
->u32
== 0);
3872 /* the lower 15bit of the prim_mask contain the offset into LDS
3873 * while the upper bits contain the number of prims */
3874 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3875 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3876 Builder
bld(ctx
->program
, ctx
->block
);
3877 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3878 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3879 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3880 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3881 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3884 if (instr
->dest
.ssa
.num_components
== 1) {
3885 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3887 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3888 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3890 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3891 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3892 vec
->operands
[i
] = Operand(tmp
);
3894 vec
->definitions
[0] = Definition(dst
);
3895 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3899 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3900 unsigned offset
, unsigned stride
, unsigned channels
)
3902 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3903 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3905 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3906 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3909 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3910 unsigned offset
, unsigned stride
, unsigned *channels
)
3912 if (!vtx_info
->chan_byte_size
) {
3913 *channels
= vtx_info
->num_channels
;
3914 return vtx_info
->chan_format
;
3917 unsigned num_channels
= *channels
;
3918 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3919 unsigned new_channels
= num_channels
+ 1;
3920 /* first, assume more loads is worse and try using a larger data format */
3921 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3923 /* don't make the attribute potentially out-of-bounds */
3924 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3928 if (new_channels
== 5) {
3929 /* then try decreasing load size (at the cost of more loads) */
3930 new_channels
= *channels
;
3931 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3935 if (new_channels
< *channels
)
3936 *channels
= new_channels
;
3937 num_channels
= new_channels
;
3940 switch (vtx_info
->chan_format
) {
3941 case V_008F0C_BUF_DATA_FORMAT_8
:
3942 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3943 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3944 case V_008F0C_BUF_DATA_FORMAT_16
:
3945 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3946 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3947 case V_008F0C_BUF_DATA_FORMAT_32
:
3948 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3949 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3951 unreachable("shouldn't reach here");
3952 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3955 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3956 * so we may need to fix it up. */
3957 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3959 Builder
bld(ctx
->program
, ctx
->block
);
3961 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3962 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3964 /* For the integer-like cases, do a natural sign extension.
3966 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3967 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3970 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3971 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3973 /* Convert back to the right type. */
3974 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3975 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3976 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3977 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3978 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3979 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3985 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3987 Builder
bld(ctx
->program
, ctx
->block
);
3988 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3989 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3991 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3992 if (off_instr
->type
!= nir_instr_type_load_const
) {
3993 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3994 nir_print_instr(off_instr
, stderr
);
3995 fprintf(stderr
, "\n");
3997 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3999 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4001 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4002 unsigned component
= nir_intrinsic_component(instr
);
4003 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4004 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4005 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4006 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4008 unsigned dfmt
= attrib_format
& 0xf;
4009 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4010 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4012 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4013 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4014 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4015 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4017 num_channels
= MAX2(num_channels
, 3);
4019 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4020 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4023 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4024 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4025 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4027 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4029 Temp divided
= bld
.tmp(v1
);
4030 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4031 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4033 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4036 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4039 index
= bld
.vadd32(bld
.def(v1
),
4040 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4041 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4044 Temp channels
[num_channels
];
4045 unsigned channel_start
= 0;
4046 bool direct_fetch
= false;
4048 /* skip unused channels at the start */
4049 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4050 channel_start
= ffs(mask
) - 1;
4051 for (unsigned i
= 0; i
< channel_start
; i
++)
4052 channels
[i
] = Temp(0, s1
);
4053 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4054 num_channels
= 3 - (ffs(mask
) - 1);
4058 while (channel_start
< num_channels
) {
4059 unsigned fetch_size
= num_channels
- channel_start
;
4060 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4061 bool expanded
= false;
4063 /* use MUBUF when possible to avoid possible alignment issues */
4064 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4065 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4066 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4067 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4068 vtx_info
->chan_byte_size
== 4;
4069 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4071 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4073 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4074 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4080 Temp fetch_index
= index
;
4081 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4082 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4083 fetch_offset
= fetch_offset
% attrib_stride
;
4086 Operand
soffset(0u);
4087 if (fetch_offset
>= 4096) {
4088 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4089 fetch_offset
%= 4096;
4093 switch (fetch_size
) {
4095 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4098 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4101 assert(ctx
->options
->chip_class
>= GFX7
||
4102 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4103 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4106 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4109 unreachable("Unimplemented load_input vector size");
4113 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4114 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4115 num_channels
<= 3)) {
4116 direct_fetch
= true;
4119 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4123 Instruction
*mubuf
= bld
.mubuf(opcode
,
4124 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4125 fetch_offset
, false, true).instr
;
4126 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4128 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4129 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4130 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4131 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4134 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4136 if (fetch_size
== 1) {
4137 channels
[channel_start
] = fetch_dst
;
4139 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4140 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4143 channel_start
+= fetch_size
;
4146 if (!direct_fetch
) {
4147 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4148 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4150 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4151 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4152 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4154 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4155 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4156 unsigned num_temp
= 0;
4157 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4158 unsigned idx
= i
+ component
;
4159 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4160 Temp channel
= channels
[swizzle
[idx
]];
4161 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4162 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4163 vec
->operands
[i
] = Operand(channel
);
4167 } else if (is_float
&& idx
== 3) {
4168 vec
->operands
[i
] = Operand(0x3f800000u
);
4169 } else if (!is_float
&& idx
== 3) {
4170 vec
->operands
[i
] = Operand(1u);
4172 vec
->operands
[i
] = Operand(0u);
4175 vec
->definitions
[0] = Definition(dst
);
4176 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4177 emit_split_vector(ctx
, dst
, dst
.size());
4179 if (num_temp
== dst
.size())
4180 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4182 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4183 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4184 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4185 if (off_instr
->type
!= nir_instr_type_load_const
||
4186 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4187 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4188 nir_print_instr(off_instr
, stderr
);
4189 fprintf(stderr
, "\n");
4192 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4193 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4195 assert(offset
->u32
== 0);
4197 /* the lower 15bit of the prim_mask contain the offset into LDS
4198 * while the upper bits contain the number of prims */
4199 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4200 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4201 Builder
bld(ctx
->program
, ctx
->block
);
4202 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4203 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4204 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4205 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4206 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4209 unsigned idx
= nir_intrinsic_base(instr
);
4210 unsigned component
= nir_intrinsic_component(instr
);
4211 unsigned vertex_id
= 2; /* P0 */
4213 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4214 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4215 switch (src0
->u32
) {
4217 vertex_id
= 2; /* P0 */
4220 vertex_id
= 0; /* P10 */
4223 vertex_id
= 1; /* P20 */
4226 unreachable("invalid vertex index");
4230 if (dst
.size() == 1) {
4231 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4233 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4234 for (unsigned i
= 0; i
< dst
.size(); i
++)
4235 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4236 vec
->definitions
[0] = Definition(dst
);
4237 bld
.insert(std::move(vec
));
4240 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4241 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4242 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4243 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4244 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4246 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4248 unreachable("Shader stage not implemented");
4252 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4254 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4256 Builder
bld(ctx
->program
, ctx
->block
);
4257 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4260 if (!nir_src_is_const(*vertex_src
)) {
4261 /* better code could be created, but this case probably doesn't happen
4262 * much in practice */
4263 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4264 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4267 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4268 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4270 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4272 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4275 if (vertex_offset
.id()) {
4276 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4277 Operand(i
), indirect_vertex
);
4278 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4280 vertex_offset
= elem
;
4284 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4285 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4287 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4288 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4289 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4290 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4291 Operand((vertex
% 2u) * 16u), Operand(16u));
4293 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4296 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4297 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4298 return offset_mul(ctx
, offs
, 4u);
4301 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4303 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4305 Builder
bld(ctx
->program
, ctx
->block
);
4306 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4307 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4309 if (ctx
->stage
== geometry_gs
) {
4310 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4311 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4312 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4313 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4314 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4315 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4316 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4318 unreachable("Unsupported GS stage.");
4322 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4324 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4326 Builder
bld(ctx
->program
, ctx
->block
);
4327 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4329 if (load_input_from_temps(ctx
, instr
, dst
))
4332 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4333 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4334 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4336 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4339 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4341 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4343 Builder
bld(ctx
->program
, ctx
->block
);
4345 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4346 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4347 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4349 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4350 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4352 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4355 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4357 switch (ctx
->shader
->info
.stage
) {
4358 case MESA_SHADER_GEOMETRY
:
4359 visit_load_gs_per_vertex_input(ctx
, instr
);
4361 case MESA_SHADER_TESS_CTRL
:
4362 visit_load_tcs_per_vertex_input(ctx
, instr
);
4364 case MESA_SHADER_TESS_EVAL
:
4365 visit_load_tes_per_vertex_input(ctx
, instr
);
4368 unreachable("Unimplemented shader stage");
4372 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4374 visit_load_tcs_output(ctx
, instr
, true);
4377 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4379 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4380 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4382 visit_store_tcs_output(ctx
, instr
, true);
4385 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4387 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4389 Builder
bld(ctx
->program
, ctx
->block
);
4390 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4392 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4393 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4396 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4397 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4398 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4399 tes_w
= Operand(tmp
);
4402 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4403 emit_split_vector(ctx
, tess_coord
, 3);
4406 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4408 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4409 Builder
bld(ctx
->program
, ctx
->block
);
4410 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4411 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4412 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4415 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4419 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4421 Builder
bld(ctx
->program
, ctx
->block
);
4422 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4423 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4424 index
= bld
.as_uniform(index
);
4425 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4426 unsigned binding
= nir_intrinsic_binding(instr
);
4429 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4430 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4431 unsigned offset
= layout
->binding
[binding
].offset
;
4433 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4434 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4435 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4436 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4437 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4440 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4441 stride
= layout
->binding
[binding
].size
;
4444 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4445 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4447 if (nir_const_index
) {
4448 const_index
= const_index
* stride
;
4449 } else if (index
.type() == RegType::vgpr
) {
4450 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4451 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4453 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4457 if (nir_const_index
) {
4458 const_index
= const_index
+ offset
;
4459 } else if (index
.type() == RegType::vgpr
) {
4460 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4462 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4466 if (nir_const_index
&& const_index
== 0) {
4468 } else if (index
.type() == RegType::vgpr
) {
4469 index
= bld
.vadd32(bld
.def(v1
),
4470 nir_const_index
? Operand(const_index
) : Operand(index
),
4473 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4474 nir_const_index
? Operand(const_index
) : Operand(index
),
4478 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4481 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4482 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4483 bool glc
=false, bool readonly
=true)
4485 Builder
bld(ctx
->program
, ctx
->block
);
4486 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4487 unsigned num_bytes
= num_components
* component_size
;
4490 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4491 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4492 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4493 unsigned const_offset
= 0;
4495 /* for small bit sizes add buffer for unaligned loads */
4498 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4503 Temp lower
= Temp();
4504 if (num_bytes
> 16) {
4505 assert(num_components
== 3 || num_components
== 4);
4506 op
= aco_opcode::buffer_load_dwordx4
;
4507 lower
= bld
.tmp(v4
);
4508 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4509 mubuf
->definitions
[0] = Definition(lower
);
4510 mubuf
->operands
[0] = Operand(rsrc
);
4511 mubuf
->operands
[1] = vaddr
;
4512 mubuf
->operands
[2] = soffset
;
4513 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4516 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4517 mubuf
->can_reorder
= readonly
;
4518 bld
.insert(std::move(mubuf
));
4519 emit_split_vector(ctx
, lower
, 2);
4522 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4523 /* GFX6 doesn't support loading vec3, expand to vec4. */
4527 switch (num_bytes
) {
4529 op
= aco_opcode::buffer_load_ubyte
;
4532 op
= aco_opcode::buffer_load_ushort
;
4536 op
= aco_opcode::buffer_load_dword
;
4542 op
= aco_opcode::buffer_load_dwordx2
;
4546 assert(ctx
->options
->chip_class
> GFX6
);
4547 op
= aco_opcode::buffer_load_dwordx3
;
4550 op
= aco_opcode::buffer_load_dwordx4
;
4553 unreachable("Load SSBO not implemented for this size.");
4555 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4556 mubuf
->operands
[0] = Operand(rsrc
);
4557 mubuf
->operands
[1] = vaddr
;
4558 mubuf
->operands
[2] = soffset
;
4559 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4562 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4563 mubuf
->can_reorder
= readonly
;
4564 mubuf
->offset
= const_offset
;
4565 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4567 if (component_size
< 4) {
4568 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4569 instr
->definitions
[0] = Definition(vec
);
4570 bld
.insert(std::move(instr
));
4572 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4573 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4574 Temp tmp
[3] = {vec
, vec
, vec
};
4576 if (vec
.size() == 3) {
4577 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4579 } else if (vec
.size() == 2) {
4580 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4581 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4583 for (unsigned i
= 0; i
< dst
.size(); i
++)
4584 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4587 if (dst
.size() == 2)
4588 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4593 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4594 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4596 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4601 } else if (dst
.size() > 4) {
4602 assert(lower
!= Temp());
4603 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4604 instr
->definitions
[0] = Definition(upper
);
4605 bld
.insert(std::move(instr
));
4606 if (dst
.size() == 8)
4607 emit_split_vector(ctx
, upper
, 2);
4608 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4609 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4610 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4611 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4612 if (dst
.size() == 8)
4613 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4614 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4615 Temp vec
= bld
.tmp(v4
);
4616 instr
->definitions
[0] = Definition(vec
);
4617 bld
.insert(std::move(instr
));
4618 emit_split_vector(ctx
, vec
, 4);
4620 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4621 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4622 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4623 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4626 if (dst
.type() == RegType::sgpr
) {
4627 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4628 instr
->definitions
[0] = Definition(vec
);
4629 bld
.insert(std::move(instr
));
4630 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4632 instr
->definitions
[0] = Definition(dst
);
4633 bld
.insert(std::move(instr
));
4634 emit_split_vector(ctx
, dst
, num_components
);
4637 /* for small bit sizes add buffer for unaligned loads */
4639 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4641 switch (num_bytes
) {
4646 op
= aco_opcode::s_buffer_load_dword
;
4652 op
= aco_opcode::s_buffer_load_dwordx2
;
4657 op
= aco_opcode::s_buffer_load_dwordx4
;
4661 op
= aco_opcode::s_buffer_load_dwordx8
;
4664 unreachable("Load SSBO not implemented for this size.");
4666 offset
= bld
.as_uniform(offset
);
4667 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4668 load
->operands
[0] = Operand(rsrc
);
4669 load
->operands
[1] = Operand(offset
);
4670 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4671 load
->definitions
[0] = Definition(dst
);
4674 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4675 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4676 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4678 /* adjust misaligned small bit size loads */
4680 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4681 load
->definitions
[0] = Definition(vec
);
4682 bld
.insert(std::move(load
));
4683 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4684 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4687 } else if (dst
.size() == 3) {
4688 Temp vec
= bld
.tmp(s4
);
4689 load
->definitions
[0] = Definition(vec
);
4690 bld
.insert(std::move(load
));
4691 emit_split_vector(ctx
, vec
, 4);
4693 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4694 emit_extract_vector(ctx
, vec
, 0, s1
),
4695 emit_extract_vector(ctx
, vec
, 1, s1
),
4696 emit_extract_vector(ctx
, vec
, 2, s1
));
4697 } else if (dst
.size() == 6) {
4698 Temp vec
= bld
.tmp(s8
);
4699 load
->definitions
[0] = Definition(vec
);
4700 bld
.insert(std::move(load
));
4701 emit_split_vector(ctx
, vec
, 4);
4703 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4704 emit_extract_vector(ctx
, vec
, 0, s2
),
4705 emit_extract_vector(ctx
, vec
, 1, s2
),
4706 emit_extract_vector(ctx
, vec
, 2, s2
));
4708 bld
.insert(std::move(load
));
4710 emit_split_vector(ctx
, dst
, num_components
);
4714 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4716 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4717 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4719 Builder
bld(ctx
->program
, ctx
->block
);
4721 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4722 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4723 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4724 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4726 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4727 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4728 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4729 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4730 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4731 if (ctx
->options
->chip_class
>= GFX10
) {
4732 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4733 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4734 S_008F0C_RESOURCE_LEVEL(1);
4736 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4737 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4739 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4740 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4741 Operand(0xFFFFFFFFu
),
4742 Operand(desc_type
));
4743 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4744 rsrc
, upper_dwords
);
4746 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4747 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4749 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4752 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4753 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4754 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4756 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4759 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4761 Builder
bld(ctx
->program
, ctx
->block
);
4762 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4763 unsigned offset
= nir_intrinsic_base(instr
);
4764 unsigned count
= instr
->dest
.ssa
.num_components
;
4765 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4767 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4768 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4769 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4770 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4771 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4772 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4773 for (unsigned i
= 0; i
< count
; ++i
) {
4774 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4775 vec
->operands
[i
] = Operand
{elems
[i
]};
4777 vec
->definitions
[0] = Definition(dst
);
4778 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4779 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4784 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4785 if (offset
!= 0) // TODO check if index != 0 as well
4786 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4787 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4790 bool aligned
= true;
4792 if (instr
->dest
.ssa
.bit_size
== 8) {
4793 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4794 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4796 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4797 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4798 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4800 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4805 switch (vec
.size()) {
4807 op
= aco_opcode::s_load_dword
;
4810 op
= aco_opcode::s_load_dwordx2
;
4816 op
= aco_opcode::s_load_dwordx4
;
4822 op
= aco_opcode::s_load_dwordx8
;
4825 unreachable("unimplemented or forbidden load_push_constant.");
4828 bld
.smem(op
, Definition(vec
), ptr
, index
);
4831 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4832 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4837 emit_split_vector(ctx
, vec
, 4);
4838 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4839 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4840 emit_extract_vector(ctx
, vec
, 0, rc
),
4841 emit_extract_vector(ctx
, vec
, 1, rc
),
4842 emit_extract_vector(ctx
, vec
, 2, rc
));
4845 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4848 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4850 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4852 Builder
bld(ctx
->program
, ctx
->block
);
4854 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4855 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4856 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4857 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4858 if (ctx
->options
->chip_class
>= GFX10
) {
4859 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4860 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4861 S_008F0C_RESOURCE_LEVEL(1);
4863 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4864 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4867 unsigned base
= nir_intrinsic_base(instr
);
4868 unsigned range
= nir_intrinsic_range(instr
);
4870 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4871 if (base
&& offset
.type() == RegType::sgpr
)
4872 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4873 else if (base
&& offset
.type() == RegType::vgpr
)
4874 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4876 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4877 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4878 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4879 Operand(desc_type
));
4880 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4881 // TODO: get alignment information for subdword constants
4882 unsigned byte_align
= size
< 4 ? -1 : 0;
4883 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
4886 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4888 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4889 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4891 ctx
->program
->needs_exact
= true;
4893 // TODO: optimize uniform conditions
4894 Builder
bld(ctx
->program
, ctx
->block
);
4895 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4896 assert(src
.regClass() == bld
.lm
);
4897 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4898 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4899 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4903 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4905 Builder
bld(ctx
->program
, ctx
->block
);
4907 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4908 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4910 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4911 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4913 if (ctx
->block
->loop_nest_depth
&&
4914 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4915 /* we handle discards the same way as jump instructions */
4916 append_logical_end(ctx
->block
);
4918 /* in loops, discard behaves like break */
4919 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4920 ctx
->block
->kind
|= block_kind_discard
;
4923 /* uniform discard - loop ends here */
4924 assert(nir_instr_is_last(&instr
->instr
));
4925 ctx
->block
->kind
|= block_kind_uniform
;
4926 ctx
->cf_info
.has_branch
= true;
4927 bld
.branch(aco_opcode::p_branch
);
4928 add_linear_edge(ctx
->block
->index
, linear_target
);
4932 /* we add a break right behind the discard() instructions */
4933 ctx
->block
->kind
|= block_kind_break
;
4934 unsigned idx
= ctx
->block
->index
;
4936 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4937 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4939 /* remove critical edges from linear CFG */
4940 bld
.branch(aco_opcode::p_branch
);
4941 Block
* break_block
= ctx
->program
->create_and_insert_block();
4942 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4943 break_block
->kind
|= block_kind_uniform
;
4944 add_linear_edge(idx
, break_block
);
4945 add_linear_edge(break_block
->index
, linear_target
);
4946 bld
.reset(break_block
);
4947 bld
.branch(aco_opcode::p_branch
);
4949 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4950 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4951 add_linear_edge(idx
, continue_block
);
4952 append_logical_start(continue_block
);
4953 ctx
->block
= continue_block
;
4958 /* it can currently happen that NIR doesn't remove the unreachable code */
4959 if (!nir_instr_is_last(&instr
->instr
)) {
4960 ctx
->program
->needs_exact
= true;
4961 /* save exec somewhere temporarily so that it doesn't get
4962 * overwritten before the discard from outer exec masks */
4963 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4964 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4965 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4969 /* This condition is incorrect for uniformly branched discards in a loop
4970 * predicated by a divergent condition, but the above code catches that case
4971 * and the discard would end up turning into a discard_if.
4981 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4982 /* program just ends here */
4983 ctx
->block
->kind
|= block_kind_uniform
;
4984 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4985 0 /* enabled mask */, 9 /* dest */,
4986 false /* compressed */, true/* done */, true /* valid mask */);
4987 bld
.sopp(aco_opcode::s_endpgm
);
4988 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4990 ctx
->block
->kind
|= block_kind_discard
;
4991 /* branch and linear edge is added by visit_if() */
4995 enum aco_descriptor_type
{
5006 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5007 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5009 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5010 return dim
== ac_image_cube
||
5011 dim
== ac_image_1darray
||
5012 dim
== ac_image_2darray
||
5013 dim
== ac_image_2darraymsaa
;
5016 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5017 enum aco_descriptor_type desc_type
,
5018 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5020 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5021 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5022 if (it != ctx->tex_desc.end())
5025 Temp index
= Temp();
5026 bool index_set
= false;
5027 unsigned constant_index
= 0;
5028 unsigned descriptor_set
;
5029 unsigned base_index
;
5030 Builder
bld(ctx
->program
, ctx
->block
);
5033 assert(tex_instr
&& !image
);
5035 base_index
= tex_instr
->sampler_index
;
5037 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5038 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5042 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5043 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5045 constant_index
+= array_size
* const_value
->u32
;
5047 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5048 if (indirect
.type() == RegType::vgpr
)
5049 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5051 if (array_size
!= 1)
5052 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5058 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5062 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5064 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5065 base_index
= deref_instr
->var
->data
.binding
;
5068 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5069 list
= convert_pointer_to_64_bit(ctx
, list
);
5071 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5072 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5073 unsigned offset
= binding
->offset
;
5074 unsigned stride
= binding
->size
;
5078 assert(base_index
< layout
->binding_count
);
5080 switch (desc_type
) {
5081 case ACO_DESC_IMAGE
:
5083 opcode
= aco_opcode::s_load_dwordx8
;
5085 case ACO_DESC_FMASK
:
5087 opcode
= aco_opcode::s_load_dwordx8
;
5090 case ACO_DESC_SAMPLER
:
5092 opcode
= aco_opcode::s_load_dwordx4
;
5093 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5094 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5096 case ACO_DESC_BUFFER
:
5098 opcode
= aco_opcode::s_load_dwordx4
;
5100 case ACO_DESC_PLANE_0
:
5101 case ACO_DESC_PLANE_1
:
5103 opcode
= aco_opcode::s_load_dwordx8
;
5104 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5106 case ACO_DESC_PLANE_2
:
5108 opcode
= aco_opcode::s_load_dwordx4
;
5112 unreachable("invalid desc_type\n");
5115 offset
+= constant_index
* stride
;
5117 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5118 (!index_set
|| binding
->immutable_samplers_equal
)) {
5119 if (binding
->immutable_samplers_equal
)
5122 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5123 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5124 Operand(samplers
[constant_index
* 4 + 0]),
5125 Operand(samplers
[constant_index
* 4 + 1]),
5126 Operand(samplers
[constant_index
* 4 + 2]),
5127 Operand(samplers
[constant_index
* 4 + 3]));
5132 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5134 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5135 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5138 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5140 if (desc_type
== ACO_DESC_PLANE_2
) {
5142 for (unsigned i
= 0; i
< 8; i
++)
5143 components
[i
] = bld
.tmp(s1
);
5144 bld
.pseudo(aco_opcode::p_split_vector
,
5145 Definition(components
[0]),
5146 Definition(components
[1]),
5147 Definition(components
[2]),
5148 Definition(components
[3]),
5151 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5152 bld
.pseudo(aco_opcode::p_split_vector
,
5153 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5154 Definition(components
[4]),
5155 Definition(components
[5]),
5156 Definition(components
[6]),
5157 Definition(components
[7]),
5160 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5161 components
[0], components
[1], components
[2], components
[3],
5162 components
[4], components
[5], components
[6], components
[7]);
5168 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5171 case GLSL_SAMPLER_DIM_BUF
:
5173 case GLSL_SAMPLER_DIM_1D
:
5174 return array
? 2 : 1;
5175 case GLSL_SAMPLER_DIM_2D
:
5176 return array
? 3 : 2;
5177 case GLSL_SAMPLER_DIM_MS
:
5178 return array
? 4 : 3;
5179 case GLSL_SAMPLER_DIM_3D
:
5180 case GLSL_SAMPLER_DIM_CUBE
:
5182 case GLSL_SAMPLER_DIM_RECT
:
5183 case GLSL_SAMPLER_DIM_SUBPASS
:
5185 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5194 /* Adjust the sample index according to FMASK.
5196 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5197 * which is the identity mapping. Each nibble says which physical sample
5198 * should be fetched to get that sample.
5200 * For example, 0x11111100 means there are only 2 samples stored and
5201 * the second sample covers 3/4 of the pixel. When reading samples 0
5202 * and 1, return physical sample 0 (determined by the first two 0s
5203 * in FMASK), otherwise return physical sample 1.
5205 * The sample index should be adjusted as follows:
5206 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5208 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5210 Builder
bld(ctx
->program
, ctx
->block
);
5211 Temp fmask
= bld
.tmp(v1
);
5212 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5213 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5216 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5217 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5218 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5219 load
->operands
[0] = Operand(fmask_desc_ptr
);
5220 load
->operands
[1] = Operand(s4
); /* no sampler */
5221 load
->operands
[2] = Operand(coord
);
5222 load
->definitions
[0] = Definition(fmask
);
5229 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5230 ctx
->block
->instructions
.emplace_back(std::move(load
));
5232 Operand sample_index4
;
5233 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5234 sample_index4
= Operand(sample_index
.constantValue() << 2);
5235 } else if (sample_index
.regClass() == s1
) {
5236 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5238 assert(sample_index
.regClass() == v1
);
5239 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5243 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5244 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5245 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5246 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5248 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5250 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5251 * resource descriptor is 0 (invalid),
5253 Temp compare
= bld
.tmp(bld
.lm
);
5254 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5255 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5257 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5259 /* Replace the MSAA sample index. */
5260 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5263 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5266 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5267 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5268 bool is_array
= glsl_sampler_type_is_array(type
);
5269 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5270 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5271 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5272 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5273 int count
= image_type_to_components_count(dim
, is_array
);
5274 std::vector
<Temp
> coords(count
);
5275 Builder
bld(ctx
->program
, ctx
->block
);
5279 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5280 /* get sample index */
5281 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5282 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5283 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5284 std::vector
<Temp
> fmask_load_address
;
5285 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5286 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5288 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5289 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5291 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5296 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5297 coords
.resize(coords
.size() + 1);
5298 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5300 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5302 for (int i
= 0; i
< count
; i
++)
5303 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5306 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5307 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5308 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5309 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5312 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5315 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5316 for (unsigned i
= 0; i
< coords
.size(); i
++)
5317 vec
->operands
[i
] = Operand(coords
[i
]);
5318 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5319 vec
->definitions
[0] = Definition(res
);
5320 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5325 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5327 Builder
bld(ctx
->program
, ctx
->block
);
5328 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5329 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5330 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5331 bool is_array
= glsl_sampler_type_is_array(type
);
5332 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5334 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5335 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5336 unsigned num_channels
= util_last_bit(mask
);
5337 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5338 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5341 switch (num_channels
) {
5343 opcode
= aco_opcode::buffer_load_format_x
;
5346 opcode
= aco_opcode::buffer_load_format_xy
;
5349 opcode
= aco_opcode::buffer_load_format_xyz
;
5352 opcode
= aco_opcode::buffer_load_format_xyzw
;
5355 unreachable(">4 channel buffer image load");
5357 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5358 load
->operands
[0] = Operand(rsrc
);
5359 load
->operands
[1] = Operand(vindex
);
5360 load
->operands
[2] = Operand((uint32_t) 0);
5362 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5365 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5366 load
->definitions
[0] = Definition(tmp
);
5368 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5369 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5370 load
->barrier
= barrier_image
;
5371 ctx
->block
->instructions
.emplace_back(std::move(load
));
5373 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5377 Temp coords
= get_image_coords(ctx
, instr
, type
);
5378 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5380 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5381 unsigned num_components
= util_bitcount(dmask
);
5383 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5386 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5388 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5389 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5391 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5392 load
->operands
[0] = Operand(resource
);
5393 load
->operands
[1] = Operand(s4
); /* no sampler */
5394 load
->operands
[2] = Operand(coords
);
5395 load
->definitions
[0] = Definition(tmp
);
5396 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5397 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5398 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5399 load
->dmask
= dmask
;
5401 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5402 load
->barrier
= barrier_image
;
5403 ctx
->block
->instructions
.emplace_back(std::move(load
));
5405 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5409 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5411 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5412 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5413 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5414 bool is_array
= glsl_sampler_type_is_array(type
);
5415 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5417 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5419 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5420 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5421 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5423 switch (data
.size()) {
5425 opcode
= aco_opcode::buffer_store_format_x
;
5428 opcode
= aco_opcode::buffer_store_format_xy
;
5431 opcode
= aco_opcode::buffer_store_format_xyz
;
5434 opcode
= aco_opcode::buffer_store_format_xyzw
;
5437 unreachable(">4 channel buffer image store");
5439 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5440 store
->operands
[0] = Operand(rsrc
);
5441 store
->operands
[1] = Operand(vindex
);
5442 store
->operands
[2] = Operand((uint32_t) 0);
5443 store
->operands
[3] = Operand(data
);
5444 store
->idxen
= true;
5447 store
->disable_wqm
= true;
5448 store
->barrier
= barrier_image
;
5449 ctx
->program
->needs_exact
= true;
5450 ctx
->block
->instructions
.emplace_back(std::move(store
));
5454 assert(data
.type() == RegType::vgpr
);
5455 Temp coords
= get_image_coords(ctx
, instr
, type
);
5456 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5458 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5459 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5461 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5462 store
->operands
[0] = Operand(resource
);
5463 store
->operands
[1] = Operand(data
);
5464 store
->operands
[2] = Operand(coords
);
5467 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5468 store
->dmask
= (1 << data
.size()) - 1;
5470 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5471 store
->disable_wqm
= true;
5472 store
->barrier
= barrier_image
;
5473 ctx
->program
->needs_exact
= true;
5474 ctx
->block
->instructions
.emplace_back(std::move(store
));
5478 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5480 /* return the previous value if dest is ever used */
5481 bool return_previous
= false;
5482 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5483 return_previous
= true;
5486 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5487 return_previous
= true;
5491 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5492 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5493 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5494 bool is_array
= glsl_sampler_type_is_array(type
);
5495 Builder
bld(ctx
->program
, ctx
->block
);
5497 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5498 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5500 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5501 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5503 aco_opcode buf_op
, image_op
;
5504 switch (instr
->intrinsic
) {
5505 case nir_intrinsic_image_deref_atomic_add
:
5506 buf_op
= aco_opcode::buffer_atomic_add
;
5507 image_op
= aco_opcode::image_atomic_add
;
5509 case nir_intrinsic_image_deref_atomic_umin
:
5510 buf_op
= aco_opcode::buffer_atomic_umin
;
5511 image_op
= aco_opcode::image_atomic_umin
;
5513 case nir_intrinsic_image_deref_atomic_imin
:
5514 buf_op
= aco_opcode::buffer_atomic_smin
;
5515 image_op
= aco_opcode::image_atomic_smin
;
5517 case nir_intrinsic_image_deref_atomic_umax
:
5518 buf_op
= aco_opcode::buffer_atomic_umax
;
5519 image_op
= aco_opcode::image_atomic_umax
;
5521 case nir_intrinsic_image_deref_atomic_imax
:
5522 buf_op
= aco_opcode::buffer_atomic_smax
;
5523 image_op
= aco_opcode::image_atomic_smax
;
5525 case nir_intrinsic_image_deref_atomic_and
:
5526 buf_op
= aco_opcode::buffer_atomic_and
;
5527 image_op
= aco_opcode::image_atomic_and
;
5529 case nir_intrinsic_image_deref_atomic_or
:
5530 buf_op
= aco_opcode::buffer_atomic_or
;
5531 image_op
= aco_opcode::image_atomic_or
;
5533 case nir_intrinsic_image_deref_atomic_xor
:
5534 buf_op
= aco_opcode::buffer_atomic_xor
;
5535 image_op
= aco_opcode::image_atomic_xor
;
5537 case nir_intrinsic_image_deref_atomic_exchange
:
5538 buf_op
= aco_opcode::buffer_atomic_swap
;
5539 image_op
= aco_opcode::image_atomic_swap
;
5541 case nir_intrinsic_image_deref_atomic_comp_swap
:
5542 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5543 image_op
= aco_opcode::image_atomic_cmpswap
;
5546 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5549 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5551 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5552 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5553 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5554 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5555 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5556 mubuf
->operands
[0] = Operand(resource
);
5557 mubuf
->operands
[1] = Operand(vindex
);
5558 mubuf
->operands
[2] = Operand((uint32_t)0);
5559 mubuf
->operands
[3] = Operand(data
);
5560 if (return_previous
)
5561 mubuf
->definitions
[0] = Definition(dst
);
5563 mubuf
->idxen
= true;
5564 mubuf
->glc
= return_previous
;
5565 mubuf
->dlc
= false; /* Not needed for atomics */
5566 mubuf
->disable_wqm
= true;
5567 mubuf
->barrier
= barrier_image
;
5568 ctx
->program
->needs_exact
= true;
5569 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5573 Temp coords
= get_image_coords(ctx
, instr
, type
);
5574 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5575 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5576 mimg
->operands
[0] = Operand(resource
);
5577 mimg
->operands
[1] = Operand(data
);
5578 mimg
->operands
[2] = Operand(coords
);
5579 if (return_previous
)
5580 mimg
->definitions
[0] = Definition(dst
);
5581 mimg
->glc
= return_previous
;
5582 mimg
->dlc
= false; /* Not needed for atomics */
5583 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5584 mimg
->dmask
= (1 << data
.size()) - 1;
5586 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5587 mimg
->disable_wqm
= true;
5588 mimg
->barrier
= barrier_image
;
5589 ctx
->program
->needs_exact
= true;
5590 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5594 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5596 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5597 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5598 Builder
bld(ctx
->program
, ctx
->block
);
5600 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5602 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5603 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5605 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5606 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5608 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5609 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5611 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5612 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5613 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5614 if (dst
.type() == RegType::vgpr
)
5615 bld
.copy(Definition(dst
), shr_dst
);
5617 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5619 emit_extract_vector(ctx
, desc
, 2, dst
);
5623 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5625 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5626 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5627 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5628 bool is_array
= glsl_sampler_type_is_array(type
);
5629 Builder
bld(ctx
->program
, ctx
->block
);
5631 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5632 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5633 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5637 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5640 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5642 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5644 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5645 mimg
->operands
[0] = Operand(resource
);
5646 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5647 mimg
->operands
[2] = Operand(lod
);
5648 uint8_t& dmask
= mimg
->dmask
;
5649 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5650 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5651 mimg
->da
= glsl_sampler_type_is_array(type
);
5652 mimg
->can_reorder
= true;
5653 Definition
& def
= mimg
->definitions
[0];
5654 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5656 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5657 glsl_sampler_type_is_array(type
)) {
5659 assert(instr
->dest
.ssa
.num_components
== 3);
5660 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5661 def
= Definition(tmp
);
5662 emit_split_vector(ctx
, tmp
, 3);
5664 /* divide 3rd value by 6 by multiplying with magic number */
5665 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5666 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5668 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5669 emit_extract_vector(ctx
, tmp
, 0, v1
),
5670 emit_extract_vector(ctx
, tmp
, 1, v1
),
5673 } else if (ctx
->options
->chip_class
== GFX9
&&
5674 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5675 glsl_sampler_type_is_array(type
)) {
5676 assert(instr
->dest
.ssa
.num_components
== 2);
5677 def
= Definition(dst
);
5680 def
= Definition(dst
);
5683 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5686 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5688 Builder
bld(ctx
->program
, ctx
->block
);
5689 unsigned num_components
= instr
->num_components
;
5691 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5692 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5693 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5695 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5696 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5699 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5700 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5701 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5703 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5706 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5708 Builder
bld(ctx
->program
, ctx
->block
);
5709 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5710 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5711 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5712 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5714 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5715 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5717 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5718 ctx
->options
->chip_class
>= GFX8
&&
5719 elem_size_bytes
>= 4;
5721 offset
= bld
.as_uniform(offset
);
5722 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5726 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5727 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5728 /* GFX6 doesn't support storing vec3, split it. */
5729 writemask
|= 1u << (start
+ 2);
5732 int num_bytes
= count
* elem_size_bytes
;
5734 /* dword or larger stores have to be dword-aligned */
5735 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5736 // TODO: improve alignment check of sub-dword stores
5737 unsigned count_new
= 2 / elem_size_bytes
;
5738 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5743 if (num_bytes
> 16) {
5744 assert(elem_size_bytes
== 8);
5745 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5751 if (elem_size_bytes
< 4) {
5752 if (data
.type() == RegType::sgpr
) {
5753 data
= as_vgpr(ctx
, data
);
5754 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5756 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5757 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5758 for (int i
= 0; i
< count
; i
++)
5759 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5760 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5761 vec
->definitions
[0] = Definition(write_data
);
5762 bld
.insert(std::move(vec
));
5763 } else if (count
!= instr
->num_components
) {
5764 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5765 for (int i
= 0; i
< count
; i
++) {
5766 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5767 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5769 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5770 vec
->definitions
[0] = Definition(write_data
);
5771 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5772 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5773 assert(num_bytes
% 4 == 0);
5774 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5775 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5776 assert(num_bytes
% 4 == 0);
5777 write_data
= bld
.as_uniform(data
);
5782 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5783 switch (num_bytes
) {
5785 vmem_op
= aco_opcode::buffer_store_byte
;
5788 vmem_op
= aco_opcode::buffer_store_short
;
5791 vmem_op
= aco_opcode::buffer_store_dword
;
5792 smem_op
= aco_opcode::s_buffer_store_dword
;
5795 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5796 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5799 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5800 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5803 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5804 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5807 unreachable("Store SSBO not implemented for this size.");
5809 if (ctx
->stage
== fragment_fs
)
5810 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5813 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5814 store
->operands
[0] = Operand(rsrc
);
5816 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5817 offset
, Operand(start
* elem_size_bytes
));
5818 store
->operands
[1] = Operand(off
);
5820 store
->operands
[1] = Operand(offset
);
5822 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5823 store
->operands
[1].setFixed(m0
);
5824 store
->operands
[2] = Operand(write_data
);
5825 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5827 store
->disable_wqm
= true;
5828 store
->barrier
= barrier_buffer
;
5829 ctx
->block
->instructions
.emplace_back(std::move(store
));
5830 ctx
->program
->wb_smem_l1_on_end
= true;
5831 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5832 ctx
->block
->kind
|= block_kind_needs_lowering
;
5833 ctx
->program
->needs_exact
= true;
5836 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5837 store
->operands
[0] = Operand(rsrc
);
5838 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5839 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5840 store
->operands
[3] = Operand(write_data
);
5841 store
->offset
= start
* elem_size_bytes
;
5842 store
->offen
= (offset
.type() == RegType::vgpr
);
5843 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5845 store
->disable_wqm
= true;
5846 store
->barrier
= barrier_buffer
;
5847 ctx
->program
->needs_exact
= true;
5848 ctx
->block
->instructions
.emplace_back(std::move(store
));
5853 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5855 /* return the previous value if dest is ever used */
5856 bool return_previous
= false;
5857 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5858 return_previous
= true;
5861 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5862 return_previous
= true;
5866 Builder
bld(ctx
->program
, ctx
->block
);
5867 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5869 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5870 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5871 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5873 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5874 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5875 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5877 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5879 aco_opcode op32
, op64
;
5880 switch (instr
->intrinsic
) {
5881 case nir_intrinsic_ssbo_atomic_add
:
5882 op32
= aco_opcode::buffer_atomic_add
;
5883 op64
= aco_opcode::buffer_atomic_add_x2
;
5885 case nir_intrinsic_ssbo_atomic_imin
:
5886 op32
= aco_opcode::buffer_atomic_smin
;
5887 op64
= aco_opcode::buffer_atomic_smin_x2
;
5889 case nir_intrinsic_ssbo_atomic_umin
:
5890 op32
= aco_opcode::buffer_atomic_umin
;
5891 op64
= aco_opcode::buffer_atomic_umin_x2
;
5893 case nir_intrinsic_ssbo_atomic_imax
:
5894 op32
= aco_opcode::buffer_atomic_smax
;
5895 op64
= aco_opcode::buffer_atomic_smax_x2
;
5897 case nir_intrinsic_ssbo_atomic_umax
:
5898 op32
= aco_opcode::buffer_atomic_umax
;
5899 op64
= aco_opcode::buffer_atomic_umax_x2
;
5901 case nir_intrinsic_ssbo_atomic_and
:
5902 op32
= aco_opcode::buffer_atomic_and
;
5903 op64
= aco_opcode::buffer_atomic_and_x2
;
5905 case nir_intrinsic_ssbo_atomic_or
:
5906 op32
= aco_opcode::buffer_atomic_or
;
5907 op64
= aco_opcode::buffer_atomic_or_x2
;
5909 case nir_intrinsic_ssbo_atomic_xor
:
5910 op32
= aco_opcode::buffer_atomic_xor
;
5911 op64
= aco_opcode::buffer_atomic_xor_x2
;
5913 case nir_intrinsic_ssbo_atomic_exchange
:
5914 op32
= aco_opcode::buffer_atomic_swap
;
5915 op64
= aco_opcode::buffer_atomic_swap_x2
;
5917 case nir_intrinsic_ssbo_atomic_comp_swap
:
5918 op32
= aco_opcode::buffer_atomic_cmpswap
;
5919 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5922 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5924 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5925 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5926 mubuf
->operands
[0] = Operand(rsrc
);
5927 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5928 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5929 mubuf
->operands
[3] = Operand(data
);
5930 if (return_previous
)
5931 mubuf
->definitions
[0] = Definition(dst
);
5933 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5934 mubuf
->glc
= return_previous
;
5935 mubuf
->dlc
= false; /* Not needed for atomics */
5936 mubuf
->disable_wqm
= true;
5937 mubuf
->barrier
= barrier_buffer
;
5938 ctx
->program
->needs_exact
= true;
5939 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5942 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5944 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5945 Builder
bld(ctx
->program
, ctx
->block
);
5946 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5947 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5950 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5952 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5953 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5955 if (addr
.type() == RegType::vgpr
)
5956 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5957 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5960 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5962 Builder
bld(ctx
->program
, ctx
->block
);
5963 unsigned num_components
= instr
->num_components
;
5964 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5967 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5969 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5970 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5972 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5973 bool global
= ctx
->options
->chip_class
>= GFX9
;
5975 if (ctx
->options
->chip_class
>= GFX7
) {
5977 switch (num_bytes
) {
5979 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5982 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5985 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5988 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5991 unreachable("load_global not implemented for this size.");
5994 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5995 flat
->operands
[0] = Operand(addr
);
5996 flat
->operands
[1] = Operand(s1
);
5999 flat
->barrier
= barrier_buffer
;
6001 if (dst
.type() == RegType::sgpr
) {
6002 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6003 flat
->definitions
[0] = Definition(vec
);
6004 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6005 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6007 flat
->definitions
[0] = Definition(dst
);
6008 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6010 emit_split_vector(ctx
, dst
, num_components
);
6012 assert(ctx
->options
->chip_class
== GFX6
);
6014 /* GFX6 doesn't support loading vec3, expand to vec4. */
6015 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6018 switch (num_bytes
) {
6020 op
= aco_opcode::buffer_load_dword
;
6023 op
= aco_opcode::buffer_load_dwordx2
;
6026 op
= aco_opcode::buffer_load_dwordx4
;
6029 unreachable("load_global not implemented for this size.");
6032 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6034 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6035 mubuf
->operands
[0] = Operand(rsrc
);
6036 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6037 mubuf
->operands
[2] = Operand(0u);
6041 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6042 mubuf
->disable_wqm
= false;
6043 mubuf
->barrier
= barrier_buffer
;
6044 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6047 if (dst
.size() == 3) {
6048 Temp vec
= bld
.tmp(v4
);
6049 instr
->definitions
[0] = Definition(vec
);
6050 bld
.insert(std::move(instr
));
6051 emit_split_vector(ctx
, vec
, 4);
6053 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6054 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6055 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6056 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6059 if (dst
.type() == RegType::sgpr
) {
6060 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6061 instr
->definitions
[0] = Definition(vec
);
6062 bld
.insert(std::move(instr
));
6063 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6064 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6066 instr
->definitions
[0] = Definition(dst
);
6067 bld
.insert(std::move(instr
));
6068 emit_split_vector(ctx
, dst
, num_components
);
6072 switch (num_bytes
) {
6074 op
= aco_opcode::s_load_dword
;
6077 op
= aco_opcode::s_load_dwordx2
;
6081 op
= aco_opcode::s_load_dwordx4
;
6084 unreachable("load_global not implemented for this size.");
6086 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6087 load
->operands
[0] = Operand(addr
);
6088 load
->operands
[1] = Operand(0u);
6089 load
->definitions
[0] = Definition(dst
);
6092 load
->barrier
= barrier_buffer
;
6093 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6095 if (dst
.size() == 3) {
6097 Temp vec
= bld
.tmp(s4
);
6098 load
->definitions
[0] = Definition(vec
);
6099 ctx
->block
->instructions
.emplace_back(std::move(load
));
6100 emit_split_vector(ctx
, vec
, 4);
6102 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6103 emit_extract_vector(ctx
, vec
, 0, s1
),
6104 emit_extract_vector(ctx
, vec
, 1, s1
),
6105 emit_extract_vector(ctx
, vec
, 2, s1
));
6107 ctx
->block
->instructions
.emplace_back(std::move(load
));
6112 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6114 Builder
bld(ctx
->program
, ctx
->block
);
6115 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6117 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6118 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6120 if (ctx
->options
->chip_class
>= GFX7
)
6121 addr
= as_vgpr(ctx
, addr
);
6123 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6126 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6127 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6128 /* GFX6 doesn't support storing vec3, split it. */
6129 writemask
|= 1u << (start
+ 2);
6132 unsigned num_bytes
= count
* elem_size_bytes
;
6134 Temp write_data
= data
;
6135 if (count
!= instr
->num_components
) {
6136 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6137 for (int i
= 0; i
< count
; i
++)
6138 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6139 write_data
= bld
.tmp(RegType::vgpr
, count
);
6140 vec
->definitions
[0] = Definition(write_data
);
6141 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6144 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6145 unsigned offset
= start
* elem_size_bytes
;
6147 if (ctx
->options
->chip_class
>= GFX7
) {
6148 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6149 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6150 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6151 Temp carry
= bld
.tmp(bld
.lm
);
6152 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6154 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6155 Operand(offset
), addr0
);
6156 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6158 carry
).def(1).setHint(vcc
);
6160 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6165 bool global
= ctx
->options
->chip_class
>= GFX9
;
6167 switch (num_bytes
) {
6169 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6172 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6175 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6178 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6181 unreachable("store_global not implemented for this size.");
6184 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6185 flat
->operands
[0] = Operand(addr
);
6186 flat
->operands
[1] = Operand(s1
);
6187 flat
->operands
[2] = Operand(data
);
6190 flat
->offset
= offset
;
6191 flat
->disable_wqm
= true;
6192 flat
->barrier
= barrier_buffer
;
6193 ctx
->program
->needs_exact
= true;
6194 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6196 assert(ctx
->options
->chip_class
== GFX6
);
6199 switch (num_bytes
) {
6201 op
= aco_opcode::buffer_store_dword
;
6204 op
= aco_opcode::buffer_store_dwordx2
;
6207 op
= aco_opcode::buffer_store_dwordx4
;
6210 unreachable("store_global not implemented for this size.");
6213 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6215 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6216 mubuf
->operands
[0] = Operand(rsrc
);
6217 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6218 mubuf
->operands
[2] = Operand(0u);
6219 mubuf
->operands
[3] = Operand(write_data
);
6222 mubuf
->offset
= offset
;
6223 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6224 mubuf
->disable_wqm
= true;
6225 mubuf
->barrier
= barrier_buffer
;
6226 ctx
->program
->needs_exact
= true;
6227 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6232 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6234 /* return the previous value if dest is ever used */
6235 bool return_previous
= false;
6236 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6237 return_previous
= true;
6240 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6241 return_previous
= true;
6245 Builder
bld(ctx
->program
, ctx
->block
);
6246 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6247 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6249 if (ctx
->options
->chip_class
>= GFX7
)
6250 addr
= as_vgpr(ctx
, addr
);
6252 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6253 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6254 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6256 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6258 aco_opcode op32
, op64
;
6260 if (ctx
->options
->chip_class
>= GFX7
) {
6261 bool global
= ctx
->options
->chip_class
>= GFX9
;
6262 switch (instr
->intrinsic
) {
6263 case nir_intrinsic_global_atomic_add
:
6264 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6265 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6267 case nir_intrinsic_global_atomic_imin
:
6268 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6269 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6271 case nir_intrinsic_global_atomic_umin
:
6272 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6273 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6275 case nir_intrinsic_global_atomic_imax
:
6276 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6277 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6279 case nir_intrinsic_global_atomic_umax
:
6280 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6281 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6283 case nir_intrinsic_global_atomic_and
:
6284 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6285 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6287 case nir_intrinsic_global_atomic_or
:
6288 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6289 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6291 case nir_intrinsic_global_atomic_xor
:
6292 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6293 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6295 case nir_intrinsic_global_atomic_exchange
:
6296 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6297 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6299 case nir_intrinsic_global_atomic_comp_swap
:
6300 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6301 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6304 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6307 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6308 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6309 flat
->operands
[0] = Operand(addr
);
6310 flat
->operands
[1] = Operand(s1
);
6311 flat
->operands
[2] = Operand(data
);
6312 if (return_previous
)
6313 flat
->definitions
[0] = Definition(dst
);
6314 flat
->glc
= return_previous
;
6315 flat
->dlc
= false; /* Not needed for atomics */
6317 flat
->disable_wqm
= true;
6318 flat
->barrier
= barrier_buffer
;
6319 ctx
->program
->needs_exact
= true;
6320 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6322 assert(ctx
->options
->chip_class
== GFX6
);
6324 switch (instr
->intrinsic
) {
6325 case nir_intrinsic_global_atomic_add
:
6326 op32
= aco_opcode::buffer_atomic_add
;
6327 op64
= aco_opcode::buffer_atomic_add_x2
;
6329 case nir_intrinsic_global_atomic_imin
:
6330 op32
= aco_opcode::buffer_atomic_smin
;
6331 op64
= aco_opcode::buffer_atomic_smin_x2
;
6333 case nir_intrinsic_global_atomic_umin
:
6334 op32
= aco_opcode::buffer_atomic_umin
;
6335 op64
= aco_opcode::buffer_atomic_umin_x2
;
6337 case nir_intrinsic_global_atomic_imax
:
6338 op32
= aco_opcode::buffer_atomic_smax
;
6339 op64
= aco_opcode::buffer_atomic_smax_x2
;
6341 case nir_intrinsic_global_atomic_umax
:
6342 op32
= aco_opcode::buffer_atomic_umax
;
6343 op64
= aco_opcode::buffer_atomic_umax_x2
;
6345 case nir_intrinsic_global_atomic_and
:
6346 op32
= aco_opcode::buffer_atomic_and
;
6347 op64
= aco_opcode::buffer_atomic_and_x2
;
6349 case nir_intrinsic_global_atomic_or
:
6350 op32
= aco_opcode::buffer_atomic_or
;
6351 op64
= aco_opcode::buffer_atomic_or_x2
;
6353 case nir_intrinsic_global_atomic_xor
:
6354 op32
= aco_opcode::buffer_atomic_xor
;
6355 op64
= aco_opcode::buffer_atomic_xor_x2
;
6357 case nir_intrinsic_global_atomic_exchange
:
6358 op32
= aco_opcode::buffer_atomic_swap
;
6359 op64
= aco_opcode::buffer_atomic_swap_x2
;
6361 case nir_intrinsic_global_atomic_comp_swap
:
6362 op32
= aco_opcode::buffer_atomic_cmpswap
;
6363 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6366 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6369 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6371 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6373 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6374 mubuf
->operands
[0] = Operand(rsrc
);
6375 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6376 mubuf
->operands
[2] = Operand(0u);
6377 mubuf
->operands
[3] = Operand(data
);
6378 if (return_previous
)
6379 mubuf
->definitions
[0] = Definition(dst
);
6380 mubuf
->glc
= return_previous
;
6383 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6384 mubuf
->disable_wqm
= true;
6385 mubuf
->barrier
= barrier_buffer
;
6386 ctx
->program
->needs_exact
= true;
6387 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6391 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6392 Builder
bld(ctx
->program
, ctx
->block
);
6393 switch(instr
->intrinsic
) {
6394 case nir_intrinsic_group_memory_barrier
:
6395 case nir_intrinsic_memory_barrier
:
6396 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6398 case nir_intrinsic_memory_barrier_buffer
:
6399 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6401 case nir_intrinsic_memory_barrier_image
:
6402 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6404 case nir_intrinsic_memory_barrier_tcs_patch
:
6405 case nir_intrinsic_memory_barrier_shared
:
6406 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6409 unreachable("Unimplemented memory barrier intrinsic");
6414 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6416 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6417 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6418 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6419 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6420 Builder
bld(ctx
->program
, ctx
->block
);
6422 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6423 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6424 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6427 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6429 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6430 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6431 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6432 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6433 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6435 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6436 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6439 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6441 unsigned offset
= nir_intrinsic_base(instr
);
6442 Operand m
= load_lds_size_m0(ctx
);
6443 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6444 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6446 unsigned num_operands
= 3;
6447 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6448 switch(instr
->intrinsic
) {
6449 case nir_intrinsic_shared_atomic_add
:
6450 op32
= aco_opcode::ds_add_u32
;
6451 op64
= aco_opcode::ds_add_u64
;
6452 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6453 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6455 case nir_intrinsic_shared_atomic_imin
:
6456 op32
= aco_opcode::ds_min_i32
;
6457 op64
= aco_opcode::ds_min_i64
;
6458 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6459 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6461 case nir_intrinsic_shared_atomic_umin
:
6462 op32
= aco_opcode::ds_min_u32
;
6463 op64
= aco_opcode::ds_min_u64
;
6464 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6465 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6467 case nir_intrinsic_shared_atomic_imax
:
6468 op32
= aco_opcode::ds_max_i32
;
6469 op64
= aco_opcode::ds_max_i64
;
6470 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6471 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6473 case nir_intrinsic_shared_atomic_umax
:
6474 op32
= aco_opcode::ds_max_u32
;
6475 op64
= aco_opcode::ds_max_u64
;
6476 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6477 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6479 case nir_intrinsic_shared_atomic_and
:
6480 op32
= aco_opcode::ds_and_b32
;
6481 op64
= aco_opcode::ds_and_b64
;
6482 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6483 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6485 case nir_intrinsic_shared_atomic_or
:
6486 op32
= aco_opcode::ds_or_b32
;
6487 op64
= aco_opcode::ds_or_b64
;
6488 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6489 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6491 case nir_intrinsic_shared_atomic_xor
:
6492 op32
= aco_opcode::ds_xor_b32
;
6493 op64
= aco_opcode::ds_xor_b64
;
6494 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6495 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6497 case nir_intrinsic_shared_atomic_exchange
:
6498 op32
= aco_opcode::ds_write_b32
;
6499 op64
= aco_opcode::ds_write_b64
;
6500 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6501 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6503 case nir_intrinsic_shared_atomic_comp_swap
:
6504 op32
= aco_opcode::ds_cmpst_b32
;
6505 op64
= aco_opcode::ds_cmpst_b64
;
6506 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6507 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6511 unreachable("Unhandled shared atomic intrinsic");
6514 /* return the previous value if dest is ever used */
6515 bool return_previous
= false;
6516 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6517 return_previous
= true;
6520 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6521 return_previous
= true;
6526 if (data
.size() == 1) {
6527 assert(instr
->dest
.ssa
.bit_size
== 32);
6528 op
= return_previous
? op32_rtn
: op32
;
6530 assert(instr
->dest
.ssa
.bit_size
== 64);
6531 op
= return_previous
? op64_rtn
: op64
;
6534 if (offset
> 65535) {
6535 Builder
bld(ctx
->program
, ctx
->block
);
6536 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6540 aco_ptr
<DS_instruction
> ds
;
6541 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6542 ds
->operands
[0] = Operand(address
);
6543 ds
->operands
[1] = Operand(data
);
6544 if (num_operands
== 4)
6545 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6546 ds
->operands
[num_operands
- 1] = m
;
6547 ds
->offset0
= offset
;
6548 if (return_previous
)
6549 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6550 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6553 Temp
get_scratch_resource(isel_context
*ctx
)
6555 Builder
bld(ctx
->program
, ctx
->block
);
6556 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6557 if (ctx
->stage
!= compute_cs
)
6558 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6560 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6561 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6563 if (ctx
->program
->chip_class
>= GFX10
) {
6564 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6565 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6566 S_008F0C_RESOURCE_LEVEL(1);
6567 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6568 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6569 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6572 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6573 if (ctx
->program
->chip_class
<= GFX8
)
6574 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6576 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6579 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6580 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6581 Builder
bld(ctx
->program
, ctx
->block
);
6582 Temp rsrc
= get_scratch_resource(ctx
);
6583 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6584 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6587 switch (dst
.size()) {
6589 op
= aco_opcode::buffer_load_dword
;
6592 op
= aco_opcode::buffer_load_dwordx2
;
6595 op
= aco_opcode::buffer_load_dwordx3
;
6598 op
= aco_opcode::buffer_load_dwordx4
;
6602 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6603 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6604 bld
.def(v4
), rsrc
, offset
,
6605 ctx
->program
->scratch_offset
, 0, true);
6606 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6607 aco_opcode::buffer_load_dwordx4
,
6608 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6609 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6610 emit_split_vector(ctx
, lower
, 2);
6611 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6612 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6613 if (dst
.size() == 8) {
6614 emit_split_vector(ctx
, upper
, 2);
6615 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6616 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6621 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6622 Format::PSEUDO
, dst
.size() / 2, 1)};
6623 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6624 vec
->operands
[i
] = Operand(elems
[i
]);
6625 vec
->definitions
[0] = Definition(dst
);
6626 bld
.insert(std::move(vec
));
6627 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6631 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6634 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6635 emit_split_vector(ctx
, dst
, instr
->num_components
);
6638 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6639 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6640 Builder
bld(ctx
->program
, ctx
->block
);
6641 Temp rsrc
= get_scratch_resource(ctx
);
6642 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6643 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6645 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6646 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6650 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6651 int num_bytes
= count
* elem_size_bytes
;
6653 if (num_bytes
> 16) {
6654 assert(elem_size_bytes
== 8);
6655 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6660 // TODO: check alignment of sub-dword stores
6661 // TODO: split 3 bytes. there is no store instruction for that
6664 if (count
!= instr
->num_components
) {
6665 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6666 for (int i
= 0; i
< count
; i
++) {
6667 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6668 vec
->operands
[i
] = Operand(elem
);
6670 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6671 vec
->definitions
[0] = Definition(write_data
);
6672 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6678 switch (num_bytes
) {
6680 op
= aco_opcode::buffer_store_dword
;
6683 op
= aco_opcode::buffer_store_dwordx2
;
6686 op
= aco_opcode::buffer_store_dwordx3
;
6689 op
= aco_opcode::buffer_store_dwordx4
;
6692 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6695 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6699 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6700 uint8_t log2_ps_iter_samples
;
6701 if (ctx
->program
->info
->ps
.force_persample
) {
6702 log2_ps_iter_samples
=
6703 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6705 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6708 /* The bit pattern matches that used by fixed function fragment
6710 static const unsigned ps_iter_masks
[] = {
6711 0xffff, /* not used */
6717 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6719 Builder
bld(ctx
->program
, ctx
->block
);
6721 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6722 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6723 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6724 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6725 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6726 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6729 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6730 Builder
bld(ctx
->program
, ctx
->block
);
6732 unsigned stream
= nir_intrinsic_stream_id(instr
);
6733 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6734 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6735 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6738 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6740 unsigned num_components
=
6741 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6742 assert(num_components
);
6744 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6745 unsigned stream_offset
= 0;
6746 for (unsigned i
= 0; i
< stream
; i
++) {
6747 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6748 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6751 /* Limit on the stride field for <= GFX7. */
6752 assert(stride
< (1 << 14));
6754 Temp gsvs_dwords
[4];
6755 for (unsigned i
= 0; i
< 4; i
++)
6756 gsvs_dwords
[i
] = bld
.tmp(s1
);
6757 bld
.pseudo(aco_opcode::p_split_vector
,
6758 Definition(gsvs_dwords
[0]),
6759 Definition(gsvs_dwords
[1]),
6760 Definition(gsvs_dwords
[2]),
6761 Definition(gsvs_dwords
[3]),
6764 if (stream_offset
) {
6765 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6767 Temp carry
= bld
.tmp(s1
);
6768 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6769 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6772 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6773 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6775 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6776 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6778 unsigned offset
= 0;
6779 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6780 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6783 for (unsigned j
= 0; j
< 4; j
++) {
6784 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6787 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6788 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6789 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6790 if (const_offset
>= 4096u) {
6791 if (vaddr_offset
.isUndefined())
6792 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6794 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6795 const_offset
%= 4096u;
6798 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6799 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6800 mtbuf
->operands
[1] = vaddr_offset
;
6801 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6802 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6803 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6804 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6805 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6806 mtbuf
->offset
= const_offset
;
6809 mtbuf
->barrier
= barrier_gs_data
;
6810 mtbuf
->can_reorder
= true;
6811 bld
.insert(std::move(mtbuf
));
6814 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6817 /* outputs for the next vertex are undefined and keeping them around can
6818 * create invalid IR with control flow */
6819 ctx
->outputs
.mask
[i
] = 0;
6822 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6825 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6827 Builder
bld(ctx
->program
, ctx
->block
);
6829 if (cluster_size
== 1) {
6831 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6832 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6833 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6834 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6835 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6836 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6837 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6838 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6839 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6840 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6841 //subgroupAnd(val) -> (exec & ~val) == 0
6842 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6843 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6844 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6845 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6846 //subgroupOr(val) -> (val & exec) != 0
6847 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6848 return bool_to_vector_condition(ctx
, tmp
);
6849 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6850 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6851 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6852 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6853 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6854 return bool_to_vector_condition(ctx
, tmp
);
6856 //subgroupClustered{And,Or,Xor}(val, n) ->
6857 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6858 //cluster_offset = ~(n - 1) & lane_id
6859 //cluster_mask = ((1 << n) - 1)
6860 //subgroupClusteredAnd():
6861 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6862 //subgroupClusteredOr():
6863 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6864 //subgroupClusteredXor():
6865 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6866 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6867 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6870 if (op
== nir_op_iand
)
6871 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6873 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6875 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6877 if (ctx
->program
->chip_class
<= GFX7
)
6878 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6879 else if (ctx
->program
->wave_size
== 64)
6880 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6882 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6883 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6884 if (cluster_mask
!= 0xffffffff)
6885 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6887 Definition cmp_def
= Definition();
6888 if (op
== nir_op_iand
) {
6889 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6890 } else if (op
== nir_op_ior
) {
6891 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6892 } else if (op
== nir_op_ixor
) {
6893 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6894 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6895 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6897 cmp_def
.setHint(vcc
);
6898 return cmp_def
.getTemp();
6902 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6904 Builder
bld(ctx
->program
, ctx
->block
);
6906 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6907 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6908 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6910 if (op
== nir_op_iand
)
6911 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6913 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6915 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6916 Temp lo
= lohi
.def(0).getTemp();
6917 Temp hi
= lohi
.def(1).getTemp();
6918 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6920 Definition cmp_def
= Definition();
6921 if (op
== nir_op_iand
)
6922 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6923 else if (op
== nir_op_ior
)
6924 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6925 else if (op
== nir_op_ixor
)
6926 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6927 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6928 cmp_def
.setHint(vcc
);
6929 return cmp_def
.getTemp();
6932 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6934 Builder
bld(ctx
->program
, ctx
->block
);
6936 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6937 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6938 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6939 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6940 if (op
== nir_op_iand
)
6941 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6942 else if (op
== nir_op_ior
)
6943 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6944 else if (op
== nir_op_ixor
)
6945 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6951 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6953 Builder
bld(ctx
->program
, ctx
->block
);
6954 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6955 if (src
.regClass().type() == RegType::vgpr
) {
6956 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6957 } else if (src
.regClass() == s1
) {
6958 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6959 } else if (src
.regClass() == s2
) {
6960 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6962 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6963 nir_print_instr(&instr
->instr
, stderr
);
6964 fprintf(stderr
, "\n");
6968 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6970 Builder
bld(ctx
->program
, ctx
->block
);
6971 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6972 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6973 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6975 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6976 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6977 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6978 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6981 if (ctx
->program
->chip_class
>= GFX8
) {
6982 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6983 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6984 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6985 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6986 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6987 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6989 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6990 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6991 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6992 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6993 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6994 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6995 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6996 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6997 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6998 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7001 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7002 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7003 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7004 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7005 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7006 Temp wqm1
= bld
.tmp(v1
);
7007 emit_wqm(ctx
, tmp1
, wqm1
, true);
7008 Temp wqm2
= bld
.tmp(v1
);
7009 emit_wqm(ctx
, tmp2
, wqm2
, true);
7010 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7014 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7016 Builder
bld(ctx
->program
, ctx
->block
);
7017 switch(instr
->intrinsic
) {
7018 case nir_intrinsic_load_barycentric_sample
:
7019 case nir_intrinsic_load_barycentric_pixel
:
7020 case nir_intrinsic_load_barycentric_centroid
: {
7021 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7022 Temp bary
= Temp(0, s2
);
7024 case INTERP_MODE_SMOOTH
:
7025 case INTERP_MODE_NONE
:
7026 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7027 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7028 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7029 bary
= ctx
->persp_centroid
;
7030 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7031 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7033 case INTERP_MODE_NOPERSPECTIVE
:
7034 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7035 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7036 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7037 bary
= ctx
->linear_centroid
;
7038 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7039 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7044 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7045 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7046 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7047 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7048 Operand(p1
), Operand(p2
));
7049 emit_split_vector(ctx
, dst
, 2);
7052 case nir_intrinsic_load_barycentric_model
: {
7053 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7055 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7056 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7057 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7058 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7060 Operand(p1
), Operand(p2
), Operand(p3
));
7061 emit_split_vector(ctx
, dst
, 3);
7064 case nir_intrinsic_load_barycentric_at_sample
: {
7065 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7066 switch (ctx
->options
->key
.fs
.num_samples
) {
7067 case 2: sample_pos_offset
+= 1 << 3; break;
7068 case 4: sample_pos_offset
+= 3 << 3; break;
7069 case 8: sample_pos_offset
+= 7 << 3; break;
7073 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7074 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7075 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7076 if (addr
.type() == RegType::sgpr
) {
7079 sample_pos_offset
+= const_addr
->u32
<< 3;
7080 offset
= Operand(sample_pos_offset
);
7081 } else if (ctx
->options
->chip_class
>= GFX9
) {
7082 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7084 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7085 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7088 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7089 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7091 } else if (ctx
->options
->chip_class
>= GFX9
) {
7092 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7093 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7094 } else if (ctx
->options
->chip_class
>= GFX7
) {
7095 /* addr += private_segment_buffer + sample_pos_offset */
7096 Temp tmp0
= bld
.tmp(s1
);
7097 Temp tmp1
= bld
.tmp(s1
);
7098 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7099 Definition scc_tmp
= bld
.def(s1
, scc
);
7100 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7101 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7102 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7103 Temp pck0
= bld
.tmp(v1
);
7104 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7105 tmp1
= as_vgpr(ctx
, tmp1
);
7106 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7107 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7109 /* sample_pos = flat_load_dwordx2 addr */
7110 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7112 assert(ctx
->options
->chip_class
== GFX6
);
7114 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7115 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7116 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7118 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7119 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7121 sample_pos
= bld
.tmp(v2
);
7123 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7124 load
->definitions
[0] = Definition(sample_pos
);
7125 load
->operands
[0] = Operand(rsrc
);
7126 load
->operands
[1] = Operand(addr
);
7127 load
->operands
[2] = Operand(0u);
7128 load
->offset
= sample_pos_offset
;
7130 load
->addr64
= true;
7133 load
->disable_wqm
= false;
7134 load
->barrier
= barrier_none
;
7135 load
->can_reorder
= true;
7136 ctx
->block
->instructions
.emplace_back(std::move(load
));
7139 /* sample_pos -= 0.5 */
7140 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7141 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7143 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7144 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7146 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7149 case nir_intrinsic_load_barycentric_at_offset
: {
7150 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7151 RegClass rc
= RegClass(offset
.type(), 1);
7152 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7153 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7154 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7157 case nir_intrinsic_load_front_face
: {
7158 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7159 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7162 case nir_intrinsic_load_view_index
: {
7163 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7164 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7165 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7171 case nir_intrinsic_load_layer_id
: {
7172 unsigned idx
= nir_intrinsic_base(instr
);
7173 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7174 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7177 case nir_intrinsic_load_frag_coord
: {
7178 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7181 case nir_intrinsic_load_sample_pos
: {
7182 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7183 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7184 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7185 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7186 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7189 case nir_intrinsic_load_tess_coord
:
7190 visit_load_tess_coord(ctx
, instr
);
7192 case nir_intrinsic_load_interpolated_input
:
7193 visit_load_interpolated_input(ctx
, instr
);
7195 case nir_intrinsic_store_output
:
7196 visit_store_output(ctx
, instr
);
7198 case nir_intrinsic_load_input
:
7199 case nir_intrinsic_load_input_vertex
:
7200 visit_load_input(ctx
, instr
);
7202 case nir_intrinsic_load_output
:
7203 visit_load_output(ctx
, instr
);
7205 case nir_intrinsic_load_per_vertex_input
:
7206 visit_load_per_vertex_input(ctx
, instr
);
7208 case nir_intrinsic_load_per_vertex_output
:
7209 visit_load_per_vertex_output(ctx
, instr
);
7211 case nir_intrinsic_store_per_vertex_output
:
7212 visit_store_per_vertex_output(ctx
, instr
);
7214 case nir_intrinsic_load_ubo
:
7215 visit_load_ubo(ctx
, instr
);
7217 case nir_intrinsic_load_push_constant
:
7218 visit_load_push_constant(ctx
, instr
);
7220 case nir_intrinsic_load_constant
:
7221 visit_load_constant(ctx
, instr
);
7223 case nir_intrinsic_vulkan_resource_index
:
7224 visit_load_resource(ctx
, instr
);
7226 case nir_intrinsic_discard
:
7227 visit_discard(ctx
, instr
);
7229 case nir_intrinsic_discard_if
:
7230 visit_discard_if(ctx
, instr
);
7232 case nir_intrinsic_load_shared
:
7233 visit_load_shared(ctx
, instr
);
7235 case nir_intrinsic_store_shared
:
7236 visit_store_shared(ctx
, instr
);
7238 case nir_intrinsic_shared_atomic_add
:
7239 case nir_intrinsic_shared_atomic_imin
:
7240 case nir_intrinsic_shared_atomic_umin
:
7241 case nir_intrinsic_shared_atomic_imax
:
7242 case nir_intrinsic_shared_atomic_umax
:
7243 case nir_intrinsic_shared_atomic_and
:
7244 case nir_intrinsic_shared_atomic_or
:
7245 case nir_intrinsic_shared_atomic_xor
:
7246 case nir_intrinsic_shared_atomic_exchange
:
7247 case nir_intrinsic_shared_atomic_comp_swap
:
7248 visit_shared_atomic(ctx
, instr
);
7250 case nir_intrinsic_image_deref_load
:
7251 visit_image_load(ctx
, instr
);
7253 case nir_intrinsic_image_deref_store
:
7254 visit_image_store(ctx
, instr
);
7256 case nir_intrinsic_image_deref_atomic_add
:
7257 case nir_intrinsic_image_deref_atomic_umin
:
7258 case nir_intrinsic_image_deref_atomic_imin
:
7259 case nir_intrinsic_image_deref_atomic_umax
:
7260 case nir_intrinsic_image_deref_atomic_imax
:
7261 case nir_intrinsic_image_deref_atomic_and
:
7262 case nir_intrinsic_image_deref_atomic_or
:
7263 case nir_intrinsic_image_deref_atomic_xor
:
7264 case nir_intrinsic_image_deref_atomic_exchange
:
7265 case nir_intrinsic_image_deref_atomic_comp_swap
:
7266 visit_image_atomic(ctx
, instr
);
7268 case nir_intrinsic_image_deref_size
:
7269 visit_image_size(ctx
, instr
);
7271 case nir_intrinsic_load_ssbo
:
7272 visit_load_ssbo(ctx
, instr
);
7274 case nir_intrinsic_store_ssbo
:
7275 visit_store_ssbo(ctx
, instr
);
7277 case nir_intrinsic_load_global
:
7278 visit_load_global(ctx
, instr
);
7280 case nir_intrinsic_store_global
:
7281 visit_store_global(ctx
, instr
);
7283 case nir_intrinsic_global_atomic_add
:
7284 case nir_intrinsic_global_atomic_imin
:
7285 case nir_intrinsic_global_atomic_umin
:
7286 case nir_intrinsic_global_atomic_imax
:
7287 case nir_intrinsic_global_atomic_umax
:
7288 case nir_intrinsic_global_atomic_and
:
7289 case nir_intrinsic_global_atomic_or
:
7290 case nir_intrinsic_global_atomic_xor
:
7291 case nir_intrinsic_global_atomic_exchange
:
7292 case nir_intrinsic_global_atomic_comp_swap
:
7293 visit_global_atomic(ctx
, instr
);
7295 case nir_intrinsic_ssbo_atomic_add
:
7296 case nir_intrinsic_ssbo_atomic_imin
:
7297 case nir_intrinsic_ssbo_atomic_umin
:
7298 case nir_intrinsic_ssbo_atomic_imax
:
7299 case nir_intrinsic_ssbo_atomic_umax
:
7300 case nir_intrinsic_ssbo_atomic_and
:
7301 case nir_intrinsic_ssbo_atomic_or
:
7302 case nir_intrinsic_ssbo_atomic_xor
:
7303 case nir_intrinsic_ssbo_atomic_exchange
:
7304 case nir_intrinsic_ssbo_atomic_comp_swap
:
7305 visit_atomic_ssbo(ctx
, instr
);
7307 case nir_intrinsic_load_scratch
:
7308 visit_load_scratch(ctx
, instr
);
7310 case nir_intrinsic_store_scratch
:
7311 visit_store_scratch(ctx
, instr
);
7313 case nir_intrinsic_get_buffer_size
:
7314 visit_get_buffer_size(ctx
, instr
);
7316 case nir_intrinsic_control_barrier
: {
7317 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7318 /* GFX6 only (thanks to a hw bug workaround):
7319 * The real barrier instruction isn’t needed, because an entire patch
7320 * always fits into a single wave.
7325 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7326 bld
.sopp(aco_opcode::s_barrier
);
7330 case nir_intrinsic_memory_barrier_tcs_patch
:
7331 case nir_intrinsic_group_memory_barrier
:
7332 case nir_intrinsic_memory_barrier
:
7333 case nir_intrinsic_memory_barrier_buffer
:
7334 case nir_intrinsic_memory_barrier_image
:
7335 case nir_intrinsic_memory_barrier_shared
:
7336 emit_memory_barrier(ctx
, instr
);
7338 case nir_intrinsic_load_num_work_groups
: {
7339 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7340 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7341 emit_split_vector(ctx
, dst
, 3);
7344 case nir_intrinsic_load_local_invocation_id
: {
7345 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7346 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7347 emit_split_vector(ctx
, dst
, 3);
7350 case nir_intrinsic_load_work_group_id
: {
7351 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7352 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7353 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7354 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7355 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7356 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7357 emit_split_vector(ctx
, dst
, 3);
7360 case nir_intrinsic_load_local_invocation_index
: {
7361 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7363 /* The tg_size bits [6:11] contain the subgroup id,
7364 * we need this multiplied by the wave size, and then OR the thread id to it.
7366 if (ctx
->program
->wave_size
== 64) {
7367 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7368 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7369 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7370 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7372 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7373 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7374 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7375 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7379 case nir_intrinsic_load_subgroup_id
: {
7380 if (ctx
->stage
== compute_cs
) {
7381 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7382 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7384 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7388 case nir_intrinsic_load_subgroup_invocation
: {
7389 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7392 case nir_intrinsic_load_num_subgroups
: {
7393 if (ctx
->stage
== compute_cs
)
7394 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7395 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7397 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7400 case nir_intrinsic_ballot
: {
7401 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7402 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7403 Definition tmp
= bld
.def(dst
.regClass());
7404 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7405 if (instr
->src
[0].ssa
->bit_size
== 1) {
7406 assert(src
.regClass() == bld
.lm
);
7407 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7408 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7409 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7410 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7411 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7413 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7414 nir_print_instr(&instr
->instr
, stderr
);
7415 fprintf(stderr
, "\n");
7417 if (dst
.size() != bld
.lm
.size()) {
7418 /* Wave32 with ballot size set to 64 */
7419 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7421 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7424 case nir_intrinsic_shuffle
:
7425 case nir_intrinsic_read_invocation
: {
7426 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7427 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7428 emit_uniform_subgroup(ctx
, instr
, src
);
7430 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7431 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7432 tid
= bld
.as_uniform(tid
);
7433 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7434 if (src
.regClass() == v1
) {
7435 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7436 } else if (src
.regClass() == v2
) {
7437 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7439 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7440 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7441 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7442 emit_split_vector(ctx
, dst
, 2);
7443 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7444 assert(src
.regClass() == bld
.lm
);
7445 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7446 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7447 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7448 assert(src
.regClass() == bld
.lm
);
7450 if (ctx
->program
->chip_class
<= GFX7
)
7451 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7452 else if (ctx
->program
->wave_size
== 64)
7453 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7455 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7456 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7457 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7458 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7460 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7461 nir_print_instr(&instr
->instr
, stderr
);
7462 fprintf(stderr
, "\n");
7467 case nir_intrinsic_load_sample_id
: {
7468 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7469 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7472 case nir_intrinsic_load_sample_mask_in
: {
7473 visit_load_sample_mask_in(ctx
, instr
);
7476 case nir_intrinsic_read_first_invocation
: {
7477 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7478 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7479 if (src
.regClass() == v1
) {
7481 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7483 } else if (src
.regClass() == v2
) {
7484 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7485 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7486 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7487 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7489 emit_split_vector(ctx
, dst
, 2);
7490 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7491 assert(src
.regClass() == bld
.lm
);
7492 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7493 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7494 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7495 } else if (src
.regClass() == s1
) {
7496 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7497 } else if (src
.regClass() == s2
) {
7498 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7500 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7501 nir_print_instr(&instr
->instr
, stderr
);
7502 fprintf(stderr
, "\n");
7506 case nir_intrinsic_vote_all
: {
7507 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7508 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7509 assert(src
.regClass() == bld
.lm
);
7510 assert(dst
.regClass() == bld
.lm
);
7512 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7513 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7514 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7517 case nir_intrinsic_vote_any
: {
7518 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7519 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7520 assert(src
.regClass() == bld
.lm
);
7521 assert(dst
.regClass() == bld
.lm
);
7523 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7524 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7527 case nir_intrinsic_reduce
:
7528 case nir_intrinsic_inclusive_scan
:
7529 case nir_intrinsic_exclusive_scan
: {
7530 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7531 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7532 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7533 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7534 nir_intrinsic_cluster_size(instr
) : 0;
7535 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7537 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7538 emit_uniform_subgroup(ctx
, instr
, src
);
7539 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7540 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7542 else if (op
== nir_op_iadd
)
7544 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7546 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7548 switch (instr
->intrinsic
) {
7549 case nir_intrinsic_reduce
:
7550 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7552 case nir_intrinsic_exclusive_scan
:
7553 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7555 case nir_intrinsic_inclusive_scan
:
7556 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7561 } else if (cluster_size
== 1) {
7562 bld
.copy(Definition(dst
), src
);
7564 src
= as_vgpr(ctx
, src
);
7568 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7583 unreachable("unknown reduction op");
7588 switch (instr
->intrinsic
) {
7589 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7590 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7591 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7593 unreachable("unknown reduce intrinsic");
7596 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7597 reduce
->operands
[0] = Operand(src
);
7598 // filled in by aco_reduce_assign.cpp, used internally as part of the
7600 assert(dst
.size() == 1 || dst
.size() == 2);
7601 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7602 reduce
->operands
[2] = Operand(v1
.as_linear());
7604 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7605 reduce
->definitions
[0] = Definition(tmp_dst
);
7606 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7607 reduce
->definitions
[2] = Definition();
7608 reduce
->definitions
[3] = Definition(scc
, s1
);
7609 reduce
->definitions
[4] = Definition();
7610 reduce
->reduce_op
= reduce_op
;
7611 reduce
->cluster_size
= cluster_size
;
7612 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7614 emit_wqm(ctx
, tmp_dst
, dst
);
7618 case nir_intrinsic_quad_broadcast
: {
7619 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7620 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7621 emit_uniform_subgroup(ctx
, instr
, src
);
7623 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7624 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7625 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7627 if (instr
->dest
.ssa
.bit_size
== 1) {
7628 assert(src
.regClass() == bld
.lm
);
7629 assert(dst
.regClass() == bld
.lm
);
7630 uint32_t half_mask
= 0x11111111u
<< lane
;
7631 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7632 Temp tmp
= bld
.tmp(bld
.lm
);
7633 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7634 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7635 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7636 emit_wqm(ctx
, tmp
, dst
);
7637 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7638 if (ctx
->program
->chip_class
>= GFX8
)
7639 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7641 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7642 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7643 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7644 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7645 if (ctx
->program
->chip_class
>= GFX8
) {
7646 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7647 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7649 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7650 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7652 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7653 emit_split_vector(ctx
, dst
, 2);
7655 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7656 nir_print_instr(&instr
->instr
, stderr
);
7657 fprintf(stderr
, "\n");
7662 case nir_intrinsic_quad_swap_horizontal
:
7663 case nir_intrinsic_quad_swap_vertical
:
7664 case nir_intrinsic_quad_swap_diagonal
:
7665 case nir_intrinsic_quad_swizzle_amd
: {
7666 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7667 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7668 emit_uniform_subgroup(ctx
, instr
, src
);
7671 uint16_t dpp_ctrl
= 0;
7672 switch (instr
->intrinsic
) {
7673 case nir_intrinsic_quad_swap_horizontal
:
7674 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7676 case nir_intrinsic_quad_swap_vertical
:
7677 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7679 case nir_intrinsic_quad_swap_diagonal
:
7680 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7682 case nir_intrinsic_quad_swizzle_amd
:
7683 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7688 if (ctx
->program
->chip_class
< GFX8
)
7689 dpp_ctrl
|= (1 << 15);
7691 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7692 if (instr
->dest
.ssa
.bit_size
== 1) {
7693 assert(src
.regClass() == bld
.lm
);
7694 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7695 if (ctx
->program
->chip_class
>= GFX8
)
7696 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7698 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7699 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7700 emit_wqm(ctx
, tmp
, dst
);
7701 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7703 if (ctx
->program
->chip_class
>= GFX8
)
7704 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7706 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7707 emit_wqm(ctx
, tmp
, dst
);
7708 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7709 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7710 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7711 if (ctx
->program
->chip_class
>= GFX8
) {
7712 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7713 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7715 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7716 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7718 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7719 emit_split_vector(ctx
, dst
, 2);
7721 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7722 nir_print_instr(&instr
->instr
, stderr
);
7723 fprintf(stderr
, "\n");
7727 case nir_intrinsic_masked_swizzle_amd
: {
7728 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7729 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7730 emit_uniform_subgroup(ctx
, instr
, src
);
7733 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7734 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7735 if (dst
.regClass() == v1
) {
7737 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7739 } else if (dst
.regClass() == v2
) {
7740 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7741 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7742 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7743 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7744 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7745 emit_split_vector(ctx
, dst
, 2);
7747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7748 nir_print_instr(&instr
->instr
, stderr
);
7749 fprintf(stderr
, "\n");
7753 case nir_intrinsic_write_invocation_amd
: {
7754 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7755 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7756 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7757 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7758 if (dst
.regClass() == v1
) {
7759 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7760 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7761 } else if (dst
.regClass() == v2
) {
7762 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7763 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7766 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7767 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7768 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7769 emit_split_vector(ctx
, dst
, 2);
7771 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7772 nir_print_instr(&instr
->instr
, stderr
);
7773 fprintf(stderr
, "\n");
7777 case nir_intrinsic_mbcnt_amd
: {
7778 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7779 RegClass rc
= RegClass(src
.type(), 1);
7780 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7781 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7783 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7784 emit_wqm(ctx
, wqm_tmp
, dst
);
7787 case nir_intrinsic_load_helper_invocation
: {
7788 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7789 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7790 ctx
->block
->kind
|= block_kind_needs_lowering
;
7791 ctx
->program
->needs_exact
= true;
7794 case nir_intrinsic_is_helper_invocation
: {
7795 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7796 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7797 ctx
->block
->kind
|= block_kind_needs_lowering
;
7798 ctx
->program
->needs_exact
= true;
7801 case nir_intrinsic_demote
:
7802 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7804 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7805 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7806 ctx
->block
->kind
|= block_kind_uses_demote
;
7807 ctx
->program
->needs_exact
= true;
7809 case nir_intrinsic_demote_if
: {
7810 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7811 assert(src
.regClass() == bld
.lm
);
7812 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7813 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7815 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7816 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7817 ctx
->block
->kind
|= block_kind_uses_demote
;
7818 ctx
->program
->needs_exact
= true;
7821 case nir_intrinsic_first_invocation
: {
7822 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7823 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7826 case nir_intrinsic_shader_clock
:
7827 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7828 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7830 case nir_intrinsic_load_vertex_id_zero_base
: {
7831 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7832 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7835 case nir_intrinsic_load_first_vertex
: {
7836 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7837 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7840 case nir_intrinsic_load_base_instance
: {
7841 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7842 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7845 case nir_intrinsic_load_instance_id
: {
7846 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7847 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7850 case nir_intrinsic_load_draw_id
: {
7851 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7852 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7855 case nir_intrinsic_load_invocation_id
: {
7856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7858 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7859 if (ctx
->options
->chip_class
>= GFX10
)
7860 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7862 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7863 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7864 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7865 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7867 unreachable("Unsupported stage for load_invocation_id");
7872 case nir_intrinsic_load_primitive_id
: {
7873 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7875 switch (ctx
->shader
->info
.stage
) {
7876 case MESA_SHADER_GEOMETRY
:
7877 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7879 case MESA_SHADER_TESS_CTRL
:
7880 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7882 case MESA_SHADER_TESS_EVAL
:
7883 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7886 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7891 case nir_intrinsic_load_patch_vertices_in
: {
7892 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7893 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7895 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7896 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7899 case nir_intrinsic_emit_vertex_with_counter
: {
7900 visit_emit_vertex_with_counter(ctx
, instr
);
7903 case nir_intrinsic_end_primitive_with_counter
: {
7904 unsigned stream
= nir_intrinsic_stream_id(instr
);
7905 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7908 case nir_intrinsic_set_vertex_count
: {
7909 /* unused, the HW keeps track of this for us */
7913 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7914 nir_print_instr(&instr
->instr
, stderr
);
7915 fprintf(stderr
, "\n");
7923 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7924 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7925 enum glsl_base_type
*stype
)
7927 nir_deref_instr
*texture_deref_instr
= NULL
;
7928 nir_deref_instr
*sampler_deref_instr
= NULL
;
7931 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7932 switch (instr
->src
[i
].src_type
) {
7933 case nir_tex_src_texture_deref
:
7934 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7936 case nir_tex_src_sampler_deref
:
7937 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7939 case nir_tex_src_plane
:
7940 plane
= nir_src_as_int(instr
->src
[i
].src
);
7947 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7949 if (!sampler_deref_instr
)
7950 sampler_deref_instr
= texture_deref_instr
;
7953 assert(instr
->op
!= nir_texop_txf_ms
&&
7954 instr
->op
!= nir_texop_samples_identical
);
7955 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7956 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7957 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7958 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7959 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7960 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7962 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7965 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7967 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7968 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7969 Builder
bld(ctx
->program
, ctx
->block
);
7971 /* to avoid unnecessary moves, we split and recombine sampler and image */
7972 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7973 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7974 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7975 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7976 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7977 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7979 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7981 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7982 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7983 img
[0], img
[1], img
[2], img
[3],
7984 img
[4], img
[5], img
[6], img
[7]);
7985 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7986 samp
[0], samp
[1], samp
[2], samp
[3]);
7989 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7990 instr
->op
== nir_texop_samples_identical
))
7991 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7994 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7995 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7997 Builder
bld(ctx
->program
, ctx
->block
);
7999 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8000 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8001 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8003 Operand
neg_one(0xbf800000u
);
8004 Operand
one(0x3f800000u
);
8005 Operand
two(0x40000000u
);
8006 Operand
four(0x40800000u
);
8008 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8009 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8010 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8012 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8013 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8014 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8015 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8018 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8019 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8020 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8022 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8025 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8026 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8027 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8030 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8031 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8033 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8034 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8037 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8039 Builder
bld(ctx
->program
, ctx
->block
);
8040 Temp ma
, tc
, sc
, id
;
8043 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8045 // see comment in ac_prepare_cube_coords()
8046 if (ctx
->options
->chip_class
<= GFX8
)
8047 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8050 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8052 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8053 vop3a
->operands
[0] = Operand(ma
);
8054 vop3a
->abs
[0] = true;
8055 Temp invma
= bld
.tmp(v1
);
8056 vop3a
->definitions
[0] = Definition(invma
);
8057 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8059 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8061 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8063 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8065 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8067 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8070 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8071 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8073 for (unsigned i
= 0; i
< 2; i
++) {
8074 // see comment in ac_prepare_cube_coords()
8076 Temp deriv_sc
, deriv_tc
;
8077 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8078 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8080 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8082 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8083 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8084 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8085 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8086 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8087 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8088 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8091 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8092 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8096 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8103 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8105 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8107 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8108 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8111 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8112 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8113 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8117 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8119 Builder
bld(ctx
->program
, ctx
->block
);
8120 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8121 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8122 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8123 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8124 std::vector
<Temp
> coords
;
8125 std::vector
<Temp
> derivs
;
8126 nir_const_value
*sample_index_cv
= NULL
;
8127 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8128 enum glsl_base_type stype
;
8129 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8131 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8132 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8133 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8134 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8136 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8137 switch (instr
->src
[i
].src_type
) {
8138 case nir_tex_src_coord
: {
8139 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8140 for (unsigned i
= 0; i
< coord
.size(); i
++)
8141 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8144 case nir_tex_src_bias
:
8145 if (instr
->op
== nir_texop_txb
) {
8146 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8150 case nir_tex_src_lod
: {
8151 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8153 if (val
&& val
->f32
<= 0.0) {
8156 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8161 case nir_tex_src_comparator
:
8162 if (instr
->is_shadow
) {
8163 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8167 case nir_tex_src_offset
:
8168 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8169 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8172 case nir_tex_src_ddx
:
8173 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8176 case nir_tex_src_ddy
:
8177 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8180 case nir_tex_src_ms_index
:
8181 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8182 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8183 has_sample_index
= true;
8185 case nir_tex_src_texture_offset
:
8186 case nir_tex_src_sampler_offset
:
8192 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8193 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8195 if (instr
->op
== nir_texop_texture_samples
) {
8196 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8198 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8199 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8200 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8201 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8203 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8204 samples
, Operand(1u), bld
.scc(is_msaa
));
8208 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8209 aco_ptr
<Instruction
> tmp_instr
;
8210 Temp acc
, pack
= Temp();
8212 uint32_t pack_const
= 0;
8213 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8214 if (!const_offset
[i
])
8216 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8219 if (offset
.type() == RegType::sgpr
) {
8220 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8221 if (const_offset
[i
])
8224 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8225 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8228 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8231 if (pack
== Temp()) {
8234 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8238 if (pack_const
&& pack
!= Temp())
8239 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8241 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8242 if (const_offset
[i
])
8245 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8246 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8249 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8252 if (pack
== Temp()) {
8255 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8259 if (pack_const
&& pack
!= Temp())
8260 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8262 if (pack_const
&& pack
== Temp())
8263 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8264 else if (pack
== Temp())
8270 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8271 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8273 /* pack derivatives */
8274 if (has_ddx
|| has_ddy
) {
8275 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8276 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8277 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8278 derivs
= {ddy
, zero
, ddy
, zero
};
8280 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8281 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8282 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8283 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8288 if (instr
->coord_components
> 1 &&
8289 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8291 instr
->op
!= nir_texop_txf
)
8292 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8294 if (instr
->coord_components
> 2 &&
8295 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8296 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8297 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8298 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8300 instr
->op
!= nir_texop_txf
&&
8301 instr
->op
!= nir_texop_txf_ms
&&
8302 instr
->op
!= nir_texop_fragment_fetch
&&
8303 instr
->op
!= nir_texop_fragment_mask_fetch
)
8304 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8306 if (ctx
->options
->chip_class
== GFX9
&&
8307 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8308 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8309 assert(coords
.size() > 0 && coords
.size() < 3);
8311 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8312 Operand((uint32_t) 0) :
8313 Operand((uint32_t) 0x3f000000)));
8316 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8318 if (instr
->op
== nir_texop_samples_identical
)
8319 resource
= fmask_ptr
;
8321 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8322 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8323 instr
->op
!= nir_texop_txs
&&
8324 instr
->op
!= nir_texop_fragment_fetch
&&
8325 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8326 assert(has_sample_index
);
8327 Operand
op(sample_index
);
8328 if (sample_index_cv
)
8329 op
= Operand(sample_index_cv
->u32
);
8330 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8333 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8334 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8335 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8336 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8341 /* Build tex instruction */
8342 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8343 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8344 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8346 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8349 /* gather4 selects the component by dmask and always returns vec4 */
8350 if (instr
->op
== nir_texop_tg4
) {
8351 assert(instr
->dest
.ssa
.num_components
== 4);
8352 if (instr
->is_shadow
)
8355 dmask
= 1 << instr
->component
;
8356 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8357 tmp_dst
= bld
.tmp(v4
);
8358 } else if (instr
->op
== nir_texop_samples_identical
) {
8359 tmp_dst
= bld
.tmp(v1
);
8360 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8361 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8364 aco_ptr
<MIMG_instruction
> tex
;
8365 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8367 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8369 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8370 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8373 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8374 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8376 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8377 tex
->operands
[0] = Operand(resource
);
8378 tex
->operands
[1] = Operand(s4
); /* no sampler */
8379 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8380 if (ctx
->options
->chip_class
== GFX9
&&
8381 instr
->op
== nir_texop_txs
&&
8382 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8384 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8385 } else if (instr
->op
== nir_texop_query_levels
) {
8386 tex
->dmask
= 1 << 3;
8391 tex
->definitions
[0] = Definition(tmp_dst
);
8393 tex
->can_reorder
= true;
8394 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8397 /* divide 3rd value by 6 by multiplying with magic number */
8398 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8399 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8400 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8401 assert(instr
->dest
.ssa
.num_components
== 3);
8402 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8403 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8404 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8405 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8410 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8414 Temp tg4_compare_cube_wa64
= Temp();
8416 if (tg4_integer_workarounds
) {
8417 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8418 tex
->operands
[0] = Operand(resource
);
8419 tex
->operands
[1] = Operand(s4
); /* no sampler */
8420 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8424 Temp size
= bld
.tmp(v2
);
8425 tex
->definitions
[0] = Definition(size
);
8426 tex
->can_reorder
= true;
8427 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8428 emit_split_vector(ctx
, size
, size
.size());
8431 for (unsigned i
= 0; i
< 2; i
++) {
8432 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8433 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8434 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8435 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8438 Temp new_coords
[2] = {
8439 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8440 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8443 if (tg4_integer_cube_workaround
) {
8444 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8445 Temp desc
[resource
.size()];
8446 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8447 Format::PSEUDO
, 1, resource
.size())};
8448 split
->operands
[0] = Operand(resource
);
8449 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8450 desc
[i
] = bld
.tmp(s1
);
8451 split
->definitions
[i
] = Definition(desc
[i
]);
8453 ctx
->block
->instructions
.emplace_back(std::move(split
));
8455 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8456 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8457 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8460 if (stype
== GLSL_TYPE_UINT
) {
8461 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8462 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8463 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8464 bld
.scc(compare_cube_wa
));
8466 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8467 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8468 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8469 bld
.scc(compare_cube_wa
));
8471 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8472 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8474 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8476 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8477 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8478 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8480 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8481 Format::PSEUDO
, resource
.size(), 1)};
8482 for (unsigned i
= 0; i
< resource
.size(); i
++)
8483 vec
->operands
[i
] = Operand(desc
[i
]);
8484 resource
= bld
.tmp(resource
.regClass());
8485 vec
->definitions
[0] = Definition(resource
);
8486 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8488 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8489 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8490 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8491 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8493 coords
[0] = new_coords
[0];
8494 coords
[1] = new_coords
[1];
8497 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8498 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8500 assert(coords
.size() == 1);
8501 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8505 op
= aco_opcode::buffer_load_format_x
; break;
8507 op
= aco_opcode::buffer_load_format_xy
; break;
8509 op
= aco_opcode::buffer_load_format_xyz
; break;
8511 op
= aco_opcode::buffer_load_format_xyzw
; break;
8513 unreachable("Tex instruction loads more than 4 components.");
8516 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8517 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8520 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8522 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8523 mubuf
->operands
[0] = Operand(resource
);
8524 mubuf
->operands
[1] = Operand(coords
[0]);
8525 mubuf
->operands
[2] = Operand((uint32_t) 0);
8526 mubuf
->definitions
[0] = Definition(tmp_dst
);
8527 mubuf
->idxen
= true;
8528 mubuf
->can_reorder
= true;
8529 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8531 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8535 /* gather MIMG address components */
8536 std::vector
<Temp
> args
;
8538 args
.emplace_back(offset
);
8540 args
.emplace_back(bias
);
8542 args
.emplace_back(compare
);
8544 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8546 args
.insert(args
.end(), coords
.begin(), coords
.end());
8547 if (has_sample_index
)
8548 args
.emplace_back(sample_index
);
8550 args
.emplace_back(lod
);
8552 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8553 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8554 vec
->definitions
[0] = Definition(arg
);
8555 for (unsigned i
= 0; i
< args
.size(); i
++)
8556 vec
->operands
[i
] = Operand(args
[i
]);
8557 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8560 if (instr
->op
== nir_texop_txf
||
8561 instr
->op
== nir_texop_txf_ms
||
8562 instr
->op
== nir_texop_samples_identical
||
8563 instr
->op
== nir_texop_fragment_fetch
||
8564 instr
->op
== nir_texop_fragment_mask_fetch
) {
8565 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8566 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8567 tex
->operands
[0] = Operand(resource
);
8568 tex
->operands
[1] = Operand(s4
); /* no sampler */
8569 tex
->operands
[2] = Operand(arg
);
8574 tex
->definitions
[0] = Definition(tmp_dst
);
8575 tex
->can_reorder
= true;
8576 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8578 if (instr
->op
== nir_texop_samples_identical
) {
8579 assert(dmask
== 1 && dst
.regClass() == v1
);
8580 assert(dst
.id() != tmp_dst
.id());
8582 Temp tmp
= bld
.tmp(bld
.lm
);
8583 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8584 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8587 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8592 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8593 aco_opcode opcode
= aco_opcode::image_sample
;
8594 if (has_offset
) { /* image_sample_*_o */
8596 opcode
= aco_opcode::image_sample_c_o
;
8598 opcode
= aco_opcode::image_sample_c_d_o
;
8600 opcode
= aco_opcode::image_sample_c_b_o
;
8602 opcode
= aco_opcode::image_sample_c_lz_o
;
8604 opcode
= aco_opcode::image_sample_c_l_o
;
8606 opcode
= aco_opcode::image_sample_o
;
8608 opcode
= aco_opcode::image_sample_d_o
;
8610 opcode
= aco_opcode::image_sample_b_o
;
8612 opcode
= aco_opcode::image_sample_lz_o
;
8614 opcode
= aco_opcode::image_sample_l_o
;
8616 } else { /* no offset */
8618 opcode
= aco_opcode::image_sample_c
;
8620 opcode
= aco_opcode::image_sample_c_d
;
8622 opcode
= aco_opcode::image_sample_c_b
;
8624 opcode
= aco_opcode::image_sample_c_lz
;
8626 opcode
= aco_opcode::image_sample_c_l
;
8628 opcode
= aco_opcode::image_sample
;
8630 opcode
= aco_opcode::image_sample_d
;
8632 opcode
= aco_opcode::image_sample_b
;
8634 opcode
= aco_opcode::image_sample_lz
;
8636 opcode
= aco_opcode::image_sample_l
;
8640 if (instr
->op
== nir_texop_tg4
) {
8642 opcode
= aco_opcode::image_gather4_lz_o
;
8644 opcode
= aco_opcode::image_gather4_c_lz_o
;
8646 opcode
= aco_opcode::image_gather4_lz
;
8648 opcode
= aco_opcode::image_gather4_c_lz
;
8650 } else if (instr
->op
== nir_texop_lod
) {
8651 opcode
= aco_opcode::image_get_lod
;
8654 /* we don't need the bias, sample index, compare value or offset to be
8655 * computed in WQM but if the p_create_vector copies the coordinates, then it
8656 * needs to be in WQM */
8657 if (ctx
->stage
== fragment_fs
&&
8658 !has_derivs
&& !has_lod
&& !level_zero
&&
8659 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8660 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8661 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8663 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8664 tex
->operands
[0] = Operand(resource
);
8665 tex
->operands
[1] = Operand(sampler
);
8666 tex
->operands
[2] = Operand(arg
);
8670 tex
->definitions
[0] = Definition(tmp_dst
);
8671 tex
->can_reorder
= true;
8672 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8674 if (tg4_integer_cube_workaround
) {
8675 assert(tmp_dst
.id() != dst
.id());
8676 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8678 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8680 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8681 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8683 if (stype
== GLSL_TYPE_UINT
)
8684 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8686 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8687 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8689 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8690 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8691 val
[0], val
[1], val
[2], val
[3]);
8693 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8694 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8699 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8701 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8702 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8703 return Operand(tmp
.regClass());
8705 return Operand(tmp
);
8708 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8710 aco_ptr
<Pseudo_instruction
> phi
;
8711 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8712 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8714 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8715 logical
|= ctx
->block
->kind
& block_kind_merge
;
8716 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8718 /* we want a sorted list of sources, since the predecessor list is also sorted */
8719 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8720 nir_foreach_phi_src(src
, instr
)
8721 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8723 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8724 unsigned num_operands
= 0;
8725 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8726 unsigned num_defined
= 0;
8727 unsigned cur_pred_idx
= 0;
8728 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8729 if (cur_pred_idx
< preds
.size()) {
8730 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8731 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8732 unsigned skipped
= 0;
8733 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8735 if (cur_pred_idx
+ skipped
< preds
.size()) {
8736 for (unsigned i
= 0; i
< skipped
; i
++)
8737 operands
[num_operands
++] = Operand(dst
.regClass());
8738 cur_pred_idx
+= skipped
;
8743 /* Handle missing predecessors at the end. This shouldn't happen with loop
8744 * headers and we can't ignore these sources for loop header phis. */
8745 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8748 Operand op
= get_phi_operand(ctx
, src
.second
);
8749 operands
[num_operands
++] = op
;
8750 num_defined
+= !op
.isUndefined();
8752 /* handle block_kind_continue_or_break at loop exit blocks */
8753 while (cur_pred_idx
++ < preds
.size())
8754 operands
[num_operands
++] = Operand(dst
.regClass());
8756 /* If the loop ends with a break, still add a linear continue edge in case
8757 * that break is divergent or continue_or_break is used. We'll either remove
8758 * this operand later in visit_loop() if it's not necessary or replace the
8759 * undef with something correct. */
8760 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8761 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8762 nir_block
*last
= nir_loop_last_block(loop
);
8763 if (last
->successors
[0] != instr
->instr
.block
)
8764 operands
[num_operands
++] = Operand(RegClass());
8767 if (num_defined
== 0) {
8768 Builder
bld(ctx
->program
, ctx
->block
);
8769 if (dst
.regClass() == s1
) {
8770 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8771 } else if (dst
.regClass() == v1
) {
8772 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8774 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8775 for (unsigned i
= 0; i
< dst
.size(); i
++)
8776 vec
->operands
[i
] = Operand(0u);
8777 vec
->definitions
[0] = Definition(dst
);
8778 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8783 /* we can use a linear phi in some cases if one src is undef */
8784 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8785 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8787 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8788 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8789 assert(invert
->kind
& block_kind_invert
);
8791 unsigned then_block
= invert
->linear_preds
[0];
8793 Block
* insert_block
= NULL
;
8794 for (unsigned i
= 0; i
< num_operands
; i
++) {
8795 Operand op
= operands
[i
];
8796 if (op
.isUndefined())
8798 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8799 phi
->operands
[0] = op
;
8802 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8803 phi
->operands
[1] = Operand(dst
.regClass());
8804 phi
->definitions
[0] = Definition(dst
);
8805 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8809 /* try to scalarize vector phis */
8810 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8811 // TODO: scalarize linear phis on divergent ifs
8812 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8813 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8814 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8815 Operand src
= operands
[i
];
8816 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8817 can_scalarize
= false;
8819 if (can_scalarize
) {
8820 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8821 assert(dst
.size() % num_components
== 0);
8822 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8824 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8825 for (unsigned k
= 0; k
< num_components
; k
++) {
8826 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8827 for (unsigned i
= 0; i
< num_operands
; i
++) {
8828 Operand src
= operands
[i
];
8829 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8831 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8832 phi
->definitions
[0] = Definition(phi_dst
);
8833 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8834 new_vec
[k
] = phi_dst
;
8835 vec
->operands
[k
] = Operand(phi_dst
);
8837 vec
->definitions
[0] = Definition(dst
);
8838 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8839 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8844 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8845 for (unsigned i
= 0; i
< num_operands
; i
++)
8846 phi
->operands
[i
] = operands
[i
];
8847 phi
->definitions
[0] = Definition(dst
);
8848 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8852 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8854 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8856 assert(dst
.type() == RegType::sgpr
);
8858 if (dst
.size() == 1) {
8859 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8861 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8862 for (unsigned i
= 0; i
< dst
.size(); i
++)
8863 vec
->operands
[i
] = Operand(0u);
8864 vec
->definitions
[0] = Definition(dst
);
8865 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8869 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8871 Builder
bld(ctx
->program
, ctx
->block
);
8872 Block
*logical_target
;
8873 append_logical_end(ctx
->block
);
8874 unsigned idx
= ctx
->block
->index
;
8876 switch (instr
->type
) {
8877 case nir_jump_break
:
8878 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8879 add_logical_edge(idx
, logical_target
);
8880 ctx
->block
->kind
|= block_kind_break
;
8882 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8883 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8884 /* uniform break - directly jump out of the loop */
8885 ctx
->block
->kind
|= block_kind_uniform
;
8886 ctx
->cf_info
.has_branch
= true;
8887 bld
.branch(aco_opcode::p_branch
);
8888 add_linear_edge(idx
, logical_target
);
8891 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8892 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8894 case nir_jump_continue
:
8895 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8896 add_logical_edge(idx
, logical_target
);
8897 ctx
->block
->kind
|= block_kind_continue
;
8899 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8900 /* for potential uniform breaks after this continue,
8901 we must ensure that they are handled correctly */
8902 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8903 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8904 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8906 /* uniform continue - directly jump to the loop header */
8907 ctx
->block
->kind
|= block_kind_uniform
;
8908 ctx
->cf_info
.has_branch
= true;
8909 bld
.branch(aco_opcode::p_branch
);
8910 add_linear_edge(idx
, logical_target
);
8915 fprintf(stderr
, "Unknown NIR jump instr: ");
8916 nir_print_instr(&instr
->instr
, stderr
);
8917 fprintf(stderr
, "\n");
8921 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8922 ctx
->cf_info
.exec_potentially_empty_break
= true;
8923 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8926 /* remove critical edges from linear CFG */
8927 bld
.branch(aco_opcode::p_branch
);
8928 Block
* break_block
= ctx
->program
->create_and_insert_block();
8929 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8930 break_block
->kind
|= block_kind_uniform
;
8931 add_linear_edge(idx
, break_block
);
8932 /* the loop_header pointer might be invalidated by this point */
8933 if (instr
->type
== nir_jump_continue
)
8934 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8935 add_linear_edge(break_block
->index
, logical_target
);
8936 bld
.reset(break_block
);
8937 bld
.branch(aco_opcode::p_branch
);
8939 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8940 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8941 add_linear_edge(idx
, continue_block
);
8942 append_logical_start(continue_block
);
8943 ctx
->block
= continue_block
;
8947 void visit_block(isel_context
*ctx
, nir_block
*block
)
8949 nir_foreach_instr(instr
, block
) {
8950 switch (instr
->type
) {
8951 case nir_instr_type_alu
:
8952 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8954 case nir_instr_type_load_const
:
8955 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8957 case nir_instr_type_intrinsic
:
8958 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8960 case nir_instr_type_tex
:
8961 visit_tex(ctx
, nir_instr_as_tex(instr
));
8963 case nir_instr_type_phi
:
8964 visit_phi(ctx
, nir_instr_as_phi(instr
));
8966 case nir_instr_type_ssa_undef
:
8967 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8969 case nir_instr_type_deref
:
8971 case nir_instr_type_jump
:
8972 visit_jump(ctx
, nir_instr_as_jump(instr
));
8975 fprintf(stderr
, "Unknown NIR instr type: ");
8976 nir_print_instr(instr
, stderr
);
8977 fprintf(stderr
, "\n");
8982 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8983 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8988 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8989 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8991 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8992 RegClass rc
= vals
[0].regClass();
8994 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8996 unsigned next_pred
= 1;
8998 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8999 Block
& block
= ctx
->program
->blocks
[idx
];
9000 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9001 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9005 if (block
.kind
& block_kind_continue
) {
9006 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9011 bool all_same
= true;
9012 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9013 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9017 val
= vals
[block
.linear_preds
[0] - first
];
9019 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9020 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9021 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9022 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9023 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9024 phi
->definitions
[0] = Definition(val
.getTemp());
9025 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9027 vals
[idx
- first
] = val
;
9030 return vals
[last
- first
];
9033 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9035 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9036 append_logical_end(ctx
->block
);
9037 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9038 Builder
bld(ctx
->program
, ctx
->block
);
9039 bld
.branch(aco_opcode::p_branch
);
9040 unsigned loop_preheader_idx
= ctx
->block
->index
;
9042 Block loop_exit
= Block();
9043 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9044 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9046 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9047 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9048 loop_header
->kind
|= block_kind_loop_header
;
9049 add_edge(loop_preheader_idx
, loop_header
);
9050 ctx
->block
= loop_header
;
9052 /* emit loop body */
9053 unsigned loop_header_idx
= loop_header
->index
;
9054 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9055 append_logical_start(ctx
->block
);
9056 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9058 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9059 if (!ctx
->cf_info
.has_branch
) {
9060 append_logical_end(ctx
->block
);
9061 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9062 /* Discards can result in code running with an empty exec mask.
9063 * This would result in divergent breaks not ever being taken. As a
9064 * workaround, break the loop when the loop mask is empty instead of
9065 * always continuing. */
9066 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9067 unsigned block_idx
= ctx
->block
->index
;
9069 /* create helper blocks to avoid critical edges */
9070 Block
*break_block
= ctx
->program
->create_and_insert_block();
9071 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9072 break_block
->kind
= block_kind_uniform
;
9073 bld
.reset(break_block
);
9074 bld
.branch(aco_opcode::p_branch
);
9075 add_linear_edge(block_idx
, break_block
);
9076 add_linear_edge(break_block
->index
, &loop_exit
);
9078 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9079 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9080 continue_block
->kind
= block_kind_uniform
;
9081 bld
.reset(continue_block
);
9082 bld
.branch(aco_opcode::p_branch
);
9083 add_linear_edge(block_idx
, continue_block
);
9084 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9086 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9087 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9088 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9090 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9091 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9092 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9094 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9097 bld
.reset(ctx
->block
);
9098 bld
.branch(aco_opcode::p_branch
);
9101 /* Fixup phis in loop header from unreachable blocks.
9102 * has_branch/has_divergent_branch also indicates if the loop ends with a
9103 * break/continue instruction, but we don't emit those if unreachable=true */
9105 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9106 bool linear
= ctx
->cf_info
.has_branch
;
9107 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9108 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9109 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9110 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9111 /* the last operand should be the one that needs to be removed */
9112 instr
->operands
.pop_back();
9113 } else if (!is_phi(instr
)) {
9119 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9120 * and the previous one shouldn't both happen at once because a break in the
9121 * merge block would get CSE'd */
9122 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9123 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9124 Operand vals
[num_vals
];
9125 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9126 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9127 if (ctx
->cf_info
.has_branch
)
9128 instr
->operands
.pop_back();
9130 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9131 } else if (!is_phi(instr
)) {
9137 ctx
->cf_info
.has_branch
= false;
9139 // TODO: if the loop has not a single exit, we must add one °°
9140 /* emit loop successor block */
9141 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9142 append_logical_start(ctx
->block
);
9145 // TODO: check if it is beneficial to not branch on continues
9146 /* trim linear phis in loop header */
9147 for (auto&& instr
: loop_entry
->instructions
) {
9148 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9149 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9150 new_phi
->definitions
[0] = instr
->definitions
[0];
9151 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9152 new_phi
->operands
[i
] = instr
->operands
[i
];
9153 /* check that the remaining operands are all the same */
9154 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9155 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9156 instr
.swap(new_phi
);
9157 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9166 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9170 append_logical_end(ctx
->block
);
9171 ctx
->block
->kind
|= block_kind_branch
;
9173 /* branch to linear then block */
9174 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9175 aco_ptr
<Pseudo_branch_instruction
> branch
;
9176 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9177 branch
->operands
[0] = Operand(cond
);
9178 ctx
->block
->instructions
.push_back(std::move(branch
));
9180 ic
->BB_if_idx
= ctx
->block
->index
;
9181 ic
->BB_invert
= Block();
9182 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9183 /* Invert blocks are intentionally not marked as top level because they
9184 * are not part of the logical cfg. */
9185 ic
->BB_invert
.kind
|= block_kind_invert
;
9186 ic
->BB_endif
= Block();
9187 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9188 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9190 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9191 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9192 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9193 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9194 ctx
->cf_info
.parent_if
.is_divergent
= true;
9196 /* divergent branches use cbranch_execz */
9197 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9198 ctx
->cf_info
.exec_potentially_empty_break
= false;
9199 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9201 /** emit logical then block */
9202 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9203 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9204 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9205 ctx
->block
= BB_then_logical
;
9206 append_logical_start(BB_then_logical
);
9209 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9211 Block
*BB_then_logical
= ctx
->block
;
9212 append_logical_end(BB_then_logical
);
9213 /* branch from logical then block to invert block */
9214 aco_ptr
<Pseudo_branch_instruction
> branch
;
9215 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9216 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9217 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9218 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9219 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9220 BB_then_logical
->kind
|= block_kind_uniform
;
9221 assert(!ctx
->cf_info
.has_branch
);
9222 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9223 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9225 /** emit linear then block */
9226 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9227 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9228 BB_then_linear
->kind
|= block_kind_uniform
;
9229 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9230 /* branch from linear then block to invert block */
9231 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9232 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9233 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9235 /** emit invert merge block */
9236 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9237 ic
->invert_idx
= ctx
->block
->index
;
9239 /* branch to linear else block (skip else) */
9240 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9241 branch
->operands
[0] = Operand(ic
->cond
);
9242 ctx
->block
->instructions
.push_back(std::move(branch
));
9244 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9245 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9246 ic
->exec_potentially_empty_break_depth_old
=
9247 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9248 /* divergent branches use cbranch_execz */
9249 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9250 ctx
->cf_info
.exec_potentially_empty_break
= false;
9251 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9253 /** emit logical else block */
9254 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9255 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9256 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9257 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9258 ctx
->block
= BB_else_logical
;
9259 append_logical_start(BB_else_logical
);
9262 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9264 Block
*BB_else_logical
= ctx
->block
;
9265 append_logical_end(BB_else_logical
);
9267 /* branch from logical else block to endif block */
9268 aco_ptr
<Pseudo_branch_instruction
> branch
;
9269 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9270 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9271 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9272 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9273 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9274 BB_else_logical
->kind
|= block_kind_uniform
;
9276 assert(!ctx
->cf_info
.has_branch
);
9277 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9280 /** emit linear else block */
9281 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9282 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9283 BB_else_linear
->kind
|= block_kind_uniform
;
9284 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9286 /* branch from linear else block to endif block */
9287 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9288 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9289 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9292 /** emit endif merge block */
9293 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9294 append_logical_start(ctx
->block
);
9297 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9298 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9299 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9300 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9301 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9302 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9303 !ctx
->cf_info
.parent_if
.is_divergent
) {
9304 ctx
->cf_info
.exec_potentially_empty_break
= false;
9305 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9307 /* uniform control flow never has an empty exec-mask */
9308 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9309 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9310 ctx
->cf_info
.exec_potentially_empty_break
= false;
9311 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9315 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9317 assert(cond
.regClass() == s1
);
9319 append_logical_end(ctx
->block
);
9320 ctx
->block
->kind
|= block_kind_uniform
;
9322 aco_ptr
<Pseudo_branch_instruction
> branch
;
9323 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9324 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9325 branch
->operands
[0] = Operand(cond
);
9326 branch
->operands
[0].setFixed(scc
);
9327 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9329 ic
->BB_if_idx
= ctx
->block
->index
;
9330 ic
->BB_endif
= Block();
9331 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9332 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9334 ctx
->cf_info
.has_branch
= false;
9335 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9337 /** emit then block */
9338 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9339 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9340 add_edge(ic
->BB_if_idx
, BB_then
);
9341 append_logical_start(BB_then
);
9342 ctx
->block
= BB_then
;
9345 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9347 Block
*BB_then
= ctx
->block
;
9349 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9350 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9352 if (!ic
->uniform_has_then_branch
) {
9353 append_logical_end(BB_then
);
9354 /* branch from then block to endif block */
9355 aco_ptr
<Pseudo_branch_instruction
> branch
;
9356 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9357 BB_then
->instructions
.emplace_back(std::move(branch
));
9358 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9359 if (!ic
->then_branch_divergent
)
9360 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9361 BB_then
->kind
|= block_kind_uniform
;
9364 ctx
->cf_info
.has_branch
= false;
9365 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9367 /** emit else block */
9368 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9369 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9370 add_edge(ic
->BB_if_idx
, BB_else
);
9371 append_logical_start(BB_else
);
9372 ctx
->block
= BB_else
;
9375 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9377 Block
*BB_else
= ctx
->block
;
9379 if (!ctx
->cf_info
.has_branch
) {
9380 append_logical_end(BB_else
);
9381 /* branch from then block to endif block */
9382 aco_ptr
<Pseudo_branch_instruction
> branch
;
9383 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9384 BB_else
->instructions
.emplace_back(std::move(branch
));
9385 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9386 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9387 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9388 BB_else
->kind
|= block_kind_uniform
;
9391 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9392 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9394 /** emit endif merge block */
9395 if (!ctx
->cf_info
.has_branch
) {
9396 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9397 append_logical_start(ctx
->block
);
9401 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9403 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9404 Builder
bld(ctx
->program
, ctx
->block
);
9405 aco_ptr
<Pseudo_branch_instruction
> branch
;
9408 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9410 * Uniform conditionals are represented in the following way*) :
9412 * The linear and logical CFG:
9415 * BB_THEN (logical) BB_ELSE (logical)
9419 * *) Exceptions may be due to break and continue statements within loops
9420 * If a break/continue happens within uniform control flow, it branches
9421 * to the loop exit/entry block. Otherwise, it branches to the next
9425 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9426 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9427 cond
= bool_to_scalar_condition(ctx
, cond
);
9429 begin_uniform_if_then(ctx
, &ic
, cond
);
9430 visit_cf_list(ctx
, &if_stmt
->then_list
);
9432 begin_uniform_if_else(ctx
, &ic
);
9433 visit_cf_list(ctx
, &if_stmt
->else_list
);
9435 end_uniform_if(ctx
, &ic
);
9437 return !ctx
->cf_info
.has_branch
;
9438 } else { /* non-uniform condition */
9440 * To maintain a logical and linear CFG without critical edges,
9441 * non-uniform conditionals are represented in the following way*) :
9446 * BB_THEN (logical) BB_THEN (linear)
9448 * BB_INVERT (linear)
9450 * BB_ELSE (logical) BB_ELSE (linear)
9457 * BB_THEN (logical) BB_ELSE (logical)
9461 * *) Exceptions may be due to break and continue statements within loops
9464 begin_divergent_if_then(ctx
, &ic
, cond
);
9465 visit_cf_list(ctx
, &if_stmt
->then_list
);
9467 begin_divergent_if_else(ctx
, &ic
);
9468 visit_cf_list(ctx
, &if_stmt
->else_list
);
9470 end_divergent_if(ctx
, &ic
);
9476 static bool visit_cf_list(isel_context
*ctx
,
9477 struct exec_list
*list
)
9479 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9480 switch (node
->type
) {
9481 case nir_cf_node_block
:
9482 visit_block(ctx
, nir_cf_node_as_block(node
));
9484 case nir_cf_node_if
:
9485 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9488 case nir_cf_node_loop
:
9489 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9492 unreachable("unimplemented cf list type");
9498 static void create_null_export(isel_context
*ctx
)
9500 /* Some shader stages always need to have exports.
9501 * So when there is none, we need to add a null export.
9504 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9505 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9506 Builder
bld(ctx
->program
, ctx
->block
);
9507 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9508 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9511 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9513 assert(ctx
->stage
== vertex_vs
||
9514 ctx
->stage
== tess_eval_vs
||
9515 ctx
->stage
== gs_copy_vs
||
9516 ctx
->stage
== ngg_vertex_gs
||
9517 ctx
->stage
== ngg_tess_eval_gs
);
9519 int offset
= (ctx
->stage
& sw_tes
)
9520 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9521 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9522 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9523 if (!is_pos
&& !mask
)
9525 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9527 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9528 exp
->enabled_mask
= mask
;
9529 for (unsigned i
= 0; i
< 4; ++i
) {
9530 if (mask
& (1 << i
))
9531 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9533 exp
->operands
[i
] = Operand(v1
);
9535 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9536 * Setting valid_mask=1 prevents it and has no other effect.
9538 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9540 exp
->compressed
= false;
9542 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9544 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9545 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9550 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9552 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9553 exp
->enabled_mask
= 0;
9554 for (unsigned i
= 0; i
< 4; ++i
)
9555 exp
->operands
[i
] = Operand(v1
);
9556 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9557 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9558 exp
->enabled_mask
|= 0x1;
9560 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9561 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9562 exp
->enabled_mask
|= 0x4;
9564 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9565 if (ctx
->options
->chip_class
< GFX9
) {
9566 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9567 exp
->enabled_mask
|= 0x8;
9569 Builder
bld(ctx
->program
, ctx
->block
);
9571 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9572 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9573 if (exp
->operands
[2].isTemp())
9574 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9576 exp
->operands
[2] = Operand(out
);
9577 exp
->enabled_mask
|= 0x4;
9580 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9582 exp
->compressed
= false;
9583 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9584 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9587 static void create_export_phis(isel_context
*ctx
)
9589 /* Used when exports are needed, but the output temps are defined in a preceding block.
9590 * This function will set up phis in order to access the outputs in the next block.
9593 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9594 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9595 ctx
->block
->instructions
.pop_back();
9597 Builder
bld(ctx
->program
, ctx
->block
);
9599 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9600 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9601 for (unsigned i
= 0; i
< 4; ++i
) {
9602 if (!(mask
& (1 << i
)))
9605 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9606 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9607 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9611 bld
.insert(std::move(logical_start
));
9614 static void create_vs_exports(isel_context
*ctx
)
9616 assert(ctx
->stage
== vertex_vs
||
9617 ctx
->stage
== tess_eval_vs
||
9618 ctx
->stage
== gs_copy_vs
||
9619 ctx
->stage
== ngg_vertex_gs
||
9620 ctx
->stage
== ngg_tess_eval_gs
);
9622 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9623 ? &ctx
->program
->info
->tes
.outinfo
9624 : &ctx
->program
->info
->vs
.outinfo
;
9626 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9627 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9628 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9631 if (ctx
->options
->key
.has_multiview_view_index
) {
9632 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9633 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9636 /* the order these position exports are created is important */
9638 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9639 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9640 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9641 exported_pos
= true;
9643 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9644 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9645 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9646 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9648 if (ctx
->export_clip_dists
) {
9649 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9650 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9651 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9652 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9655 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9656 if (i
< VARYING_SLOT_VAR0
&&
9657 i
!= VARYING_SLOT_LAYER
&&
9658 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9661 export_vs_varying(ctx
, i
, false, NULL
);
9665 create_null_export(ctx
);
9668 static bool export_fs_mrt_z(isel_context
*ctx
)
9670 Builder
bld(ctx
->program
, ctx
->block
);
9671 unsigned enabled_channels
= 0;
9675 for (unsigned i
= 0; i
< 4; ++i
) {
9676 values
[i
] = Operand(v1
);
9679 /* Both stencil and sample mask only need 16-bits. */
9680 if (!ctx
->program
->info
->ps
.writes_z
&&
9681 (ctx
->program
->info
->ps
.writes_stencil
||
9682 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9683 compr
= true; /* COMPR flag */
9685 if (ctx
->program
->info
->ps
.writes_stencil
) {
9686 /* Stencil should be in X[23:16]. */
9687 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9688 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9689 enabled_channels
|= 0x3;
9692 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9693 /* SampleMask should be in Y[15:0]. */
9694 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9695 enabled_channels
|= 0xc;
9698 if (ctx
->program
->info
->ps
.writes_z
) {
9699 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9700 enabled_channels
|= 0x1;
9703 if (ctx
->program
->info
->ps
.writes_stencil
) {
9704 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9705 enabled_channels
|= 0x2;
9708 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9709 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9710 enabled_channels
|= 0x4;
9714 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9715 * writemask component.
9717 if (ctx
->options
->chip_class
== GFX6
&&
9718 ctx
->options
->family
!= CHIP_OLAND
&&
9719 ctx
->options
->family
!= CHIP_HAINAN
) {
9720 enabled_channels
|= 0x1;
9723 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9724 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9729 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9731 Builder
bld(ctx
->program
, ctx
->block
);
9732 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9735 for (unsigned i
= 0; i
< 4; ++i
) {
9736 if (write_mask
& (1 << i
)) {
9737 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9739 values
[i
] = Operand(v1
);
9743 unsigned target
, col_format
;
9744 unsigned enabled_channels
= 0;
9745 aco_opcode compr_op
= (aco_opcode
)0;
9747 slot
-= FRAG_RESULT_DATA0
;
9748 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9749 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9751 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9752 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9756 case V_028714_SPI_SHADER_ZERO
:
9757 enabled_channels
= 0; /* writemask */
9758 target
= V_008DFC_SQ_EXP_NULL
;
9761 case V_028714_SPI_SHADER_32_R
:
9762 enabled_channels
= 1;
9765 case V_028714_SPI_SHADER_32_GR
:
9766 enabled_channels
= 0x3;
9769 case V_028714_SPI_SHADER_32_AR
:
9770 if (ctx
->options
->chip_class
>= GFX10
) {
9771 /* Special case: on GFX10, the outputs are different for 32_AR */
9772 enabled_channels
= 0x3;
9773 values
[1] = values
[3];
9774 values
[3] = Operand(v1
);
9776 enabled_channels
= 0x9;
9780 case V_028714_SPI_SHADER_FP16_ABGR
:
9781 enabled_channels
= 0x5;
9782 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9785 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9786 enabled_channels
= 0x5;
9787 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9790 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9791 enabled_channels
= 0x5;
9792 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9795 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9796 enabled_channels
= 0x5;
9797 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9798 if (is_int8
|| is_int10
) {
9800 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9801 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9803 for (unsigned i
= 0; i
< 4; i
++) {
9804 if ((write_mask
>> i
) & 1) {
9805 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9806 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9814 case V_028714_SPI_SHADER_SINT16_ABGR
:
9815 enabled_channels
= 0x5;
9816 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9817 if (is_int8
|| is_int10
) {
9819 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9820 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9821 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9822 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9824 for (unsigned i
= 0; i
< 4; i
++) {
9825 if ((write_mask
>> i
) & 1) {
9826 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9827 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9829 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9830 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9837 case V_028714_SPI_SHADER_32_ABGR
:
9838 enabled_channels
= 0xF;
9845 if (target
== V_008DFC_SQ_EXP_NULL
)
9848 if ((bool) compr_op
) {
9849 for (int i
= 0; i
< 2; i
++) {
9850 /* check if at least one of the values to be compressed is enabled */
9851 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9853 enabled_channels
|= enabled
<< (i
*2);
9854 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9855 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9856 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9858 values
[i
] = Operand(v1
);
9861 values
[2] = Operand(v1
);
9862 values
[3] = Operand(v1
);
9864 for (int i
= 0; i
< 4; i
++)
9865 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9868 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9869 enabled_channels
, target
, (bool) compr_op
);
9873 static void create_fs_exports(isel_context
*ctx
)
9875 bool exported
= false;
9877 /* Export depth, stencil and sample mask. */
9878 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9879 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9880 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9881 exported
|= export_fs_mrt_z(ctx
);
9883 /* Export all color render targets. */
9884 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9885 if (ctx
->outputs
.mask
[i
])
9886 exported
|= export_fs_mrt_color(ctx
, i
);
9889 create_null_export(ctx
);
9892 static void write_tcs_tess_factors(isel_context
*ctx
)
9894 unsigned outer_comps
;
9895 unsigned inner_comps
;
9897 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9914 Builder
bld(ctx
->program
, ctx
->block
);
9916 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9917 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9918 bld
.sopp(aco_opcode::s_barrier
);
9920 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9921 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9923 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9924 if_context ic_invocation_id_is_zero
;
9925 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9926 bld
.reset(ctx
->block
);
9928 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9930 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9931 unsigned stride
= inner_comps
+ outer_comps
;
9932 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9936 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9938 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9940 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9941 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9942 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9944 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9945 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9947 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9948 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9949 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9950 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9953 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9954 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9955 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9956 unsigned tf_const_offset
= 0;
9958 if (ctx
->program
->chip_class
<= GFX8
) {
9959 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9960 if_context ic_rel_patch_id_is_zero
;
9961 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9962 bld
.reset(ctx
->block
);
9964 /* Store the dynamic HS control word. */
9965 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9966 bld
.mubuf(aco_opcode::buffer_store_dword
,
9967 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9968 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9969 /* disable_wqm */ false, /* glc */ true);
9970 tf_const_offset
+= 4;
9972 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9973 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9974 bld
.reset(ctx
->block
);
9977 assert(stride
== 2 || stride
== 4 || stride
== 6);
9978 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9979 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9981 /* Store to offchip for TES to read - only if TES reads them */
9982 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9983 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9984 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9986 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9987 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9989 if (likely(inner_comps
)) {
9990 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9991 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9995 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9996 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9999 static void emit_stream_output(isel_context
*ctx
,
10000 Temp
const *so_buffers
,
10001 Temp
const *so_write_offset
,
10002 const struct radv_stream_output
*output
)
10004 unsigned num_comps
= util_bitcount(output
->component_mask
);
10005 unsigned writemask
= (1 << num_comps
) - 1;
10006 unsigned loc
= output
->location
;
10007 unsigned buf
= output
->buffer
;
10009 assert(num_comps
&& num_comps
<= 4);
10010 if (!num_comps
|| num_comps
> 4)
10013 unsigned start
= ffs(output
->component_mask
) - 1;
10016 bool all_undef
= true;
10017 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10018 for (unsigned i
= 0; i
< num_comps
; i
++) {
10019 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10020 all_undef
= all_undef
&& !out
[i
].id();
10025 while (writemask
) {
10027 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10028 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10029 /* GFX6 doesn't support storing vec3, split it. */
10030 writemask
|= 1u << (start
+ 2);
10034 unsigned offset
= output
->offset
+ start
* 4;
10036 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10037 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10038 for (int i
= 0; i
< count
; ++i
)
10039 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10040 vec
->definitions
[0] = Definition(write_data
);
10041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10046 opcode
= aco_opcode::buffer_store_dword
;
10049 opcode
= aco_opcode::buffer_store_dwordx2
;
10052 opcode
= aco_opcode::buffer_store_dwordx3
;
10055 opcode
= aco_opcode::buffer_store_dwordx4
;
10058 unreachable("Unsupported dword count.");
10061 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10062 store
->operands
[0] = Operand(so_buffers
[buf
]);
10063 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10064 store
->operands
[2] = Operand((uint32_t) 0);
10065 store
->operands
[3] = Operand(write_data
);
10066 if (offset
> 4095) {
10067 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10068 Builder
bld(ctx
->program
, ctx
->block
);
10069 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10071 store
->offset
= offset
;
10073 store
->offen
= true;
10075 store
->dlc
= false;
10077 store
->can_reorder
= true;
10078 ctx
->block
->instructions
.emplace_back(std::move(store
));
10082 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10084 Builder
bld(ctx
->program
, ctx
->block
);
10086 Temp so_buffers
[4];
10087 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10088 for (unsigned i
= 0; i
< 4; i
++) {
10089 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10093 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10094 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10097 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10098 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10100 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10102 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10105 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10107 bld
.reset(ctx
->block
);
10109 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10111 Temp so_write_offset
[4];
10113 for (unsigned i
= 0; i
< 4; i
++) {
10114 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10119 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10120 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10121 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10122 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10124 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10126 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10127 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10128 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10129 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10133 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10134 struct radv_stream_output
*output
=
10135 &ctx
->program
->info
->so
.outputs
[i
];
10136 if (stream
!= output
->stream
)
10139 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10142 begin_divergent_if_else(ctx
, &ic
);
10143 end_divergent_if(ctx
, &ic
);
10146 } /* end namespace */
10148 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10150 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10151 Builder
bld(ctx
->program
, ctx
->block
);
10152 constexpr unsigned hs_idx
= 1u;
10153 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10154 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10155 Operand((8u << 16) | (hs_idx
* 8u)));
10156 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10158 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10160 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10161 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10162 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10163 ls_has_nonzero_hs_threads
);
10164 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10165 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10166 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10167 ls_has_nonzero_hs_threads
);
10168 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10169 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10170 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10171 ls_has_nonzero_hs_threads
);
10173 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10174 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10175 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10178 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10180 /* Split all arguments except for the first (ring_offsets) and the last
10181 * (exec) so that the dead channels don't stay live throughout the program.
10183 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10184 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10185 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10186 startpgm
->definitions
[i
].regClass().size());
10191 void handle_bc_optimize(isel_context
*ctx
)
10193 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10194 Builder
bld(ctx
->program
, ctx
->block
);
10195 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10196 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10197 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10198 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10199 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10200 if (uses_center
&& uses_centroid
) {
10201 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10202 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10204 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10206 for (unsigned i
= 0; i
< 2; i
++) {
10207 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10208 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10209 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10210 persp_centroid
, persp_center
, sel
);
10212 ctx
->persp_centroid
= bld
.tmp(v2
);
10213 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10214 Operand(new_coord
[0]), Operand(new_coord
[1]));
10215 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10218 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10220 for (unsigned i
= 0; i
< 2; i
++) {
10221 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10222 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10223 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10224 linear_centroid
, linear_center
, sel
);
10226 ctx
->linear_centroid
= bld
.tmp(v2
);
10227 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10228 Operand(new_coord
[0]), Operand(new_coord
[1]));
10229 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10234 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10236 Program
*program
= ctx
->program
;
10238 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10240 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10241 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10242 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10243 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10244 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10246 program
->next_fp_mode
.must_flush_denorms32
=
10247 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10248 program
->next_fp_mode
.must_flush_denorms16_64
=
10249 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10250 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10252 program
->next_fp_mode
.care_about_round32
=
10253 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10255 program
->next_fp_mode
.care_about_round16_64
=
10256 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10257 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10259 /* default to preserving fp16 and fp64 denorms, since it's free */
10260 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10261 program
->next_fp_mode
.denorm16_64
= 0;
10263 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10265 /* preserving fp32 denorms is expensive, so only do it if asked */
10266 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10267 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10269 program
->next_fp_mode
.denorm32
= 0;
10271 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10272 program
->next_fp_mode
.round32
= fp_round_tz
;
10274 program
->next_fp_mode
.round32
= fp_round_ne
;
10276 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10277 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10279 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10281 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10284 void cleanup_cfg(Program
*program
)
10286 /* create linear_succs/logical_succs */
10287 for (Block
& BB
: program
->blocks
) {
10288 for (unsigned idx
: BB
.linear_preds
)
10289 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10290 for (unsigned idx
: BB
.logical_preds
)
10291 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10295 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10297 Builder
bld(ctx
->program
, ctx
->block
);
10299 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10300 Temp count
= i
== 0
10301 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10302 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10303 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10305 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10308 if (ctx
->program
->wave_size
== 64) {
10309 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10310 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10311 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10313 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10314 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10320 bool ngg_early_prim_export(isel_context
*ctx
)
10322 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10326 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10328 Builder
bld(ctx
->program
, ctx
->block
);
10330 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10331 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10333 /* Get the id of the current wave within the threadgroup (workgroup) */
10334 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10335 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10337 /* Execute the following code only on the first wave (wave id 0),
10338 * use the SCC def to tell if the wave id is zero or not.
10340 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10342 begin_uniform_if_then(ctx
, &ic
, cond
);
10343 begin_uniform_if_else(ctx
, &ic
);
10344 bld
.reset(ctx
->block
);
10346 /* Number of vertices output by VS/TES */
10347 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10348 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10349 /* Number of primitives output by VS/TES */
10350 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10351 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10353 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10354 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10355 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10357 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10358 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10360 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10361 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10363 end_uniform_if(ctx
, &ic
);
10366 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10368 Builder
bld(ctx
->program
, ctx
->block
);
10370 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10371 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10374 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10377 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10378 assert(vtxindex
[i
].id());
10381 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10385 /* The initial edge flag is always false in tess eval shaders. */
10386 if (ctx
->stage
== ngg_vertex_gs
) {
10387 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10388 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10392 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10397 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10399 Builder
bld(ctx
->program
, ctx
->block
);
10400 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10402 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10403 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10404 false /* compressed */, true/* done */, false /* valid mask */);
10407 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10409 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10410 * These must always come before VS exports.
10412 * It is recommended to do these as early as possible. They can be at the beginning when
10413 * there is no SW GS and the shader doesn't write edge flags.
10417 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10418 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10420 Builder
bld(ctx
->program
, ctx
->block
);
10421 constexpr unsigned max_vertices_per_primitive
= 3;
10422 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10424 if (ctx
->stage
== ngg_vertex_gs
) {
10425 /* TODO: optimize for points & lines */
10426 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10427 if (ctx
->shader
->info
.tess
.point_mode
)
10428 num_vertices_per_primitive
= 1;
10429 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10430 num_vertices_per_primitive
= 2;
10432 unreachable("Unsupported NGG shader stage");
10435 Temp vtxindex
[max_vertices_per_primitive
];
10436 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10437 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10438 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10439 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10440 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10441 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10442 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10443 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10445 /* Export primitive data to the index buffer. */
10446 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10448 /* Export primitive ID. */
10449 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10450 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10451 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10452 Temp provoking_vtx_index
= vtxindex
[0];
10453 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10455 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10458 begin_divergent_if_else(ctx
, &ic
);
10459 end_divergent_if(ctx
, &ic
);
10462 void ngg_emit_nogs_output(isel_context
*ctx
)
10464 /* Emits NGG GS output, for stages that don't have SW GS. */
10467 Builder
bld(ctx
->program
, ctx
->block
);
10468 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10470 /* NGG streamout is currently disabled by default. */
10471 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10473 if (late_prim_export
) {
10474 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10475 create_export_phis(ctx
);
10476 /* Do what we need to do in the GS threads. */
10477 ngg_emit_nogs_gsthreads(ctx
);
10479 /* What comes next should be executed on ES threads. */
10480 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10481 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10482 bld
.reset(ctx
->block
);
10485 /* Export VS outputs */
10486 ctx
->block
->kind
|= block_kind_export_end
;
10487 create_vs_exports(ctx
);
10489 /* Export primitive ID */
10490 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10493 if (ctx
->stage
== ngg_vertex_gs
) {
10494 /* Wait for GS threads to store primitive ID in LDS. */
10495 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10496 bld
.sopp(aco_opcode::s_barrier
);
10498 /* Calculate LDS address where the GS threads stored the primitive ID. */
10499 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10500 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10501 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10502 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10503 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10504 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10506 /* Load primitive ID from LDS. */
10507 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10508 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10509 /* TES: Just use the patch ID as the primitive ID. */
10510 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10512 unreachable("unsupported NGG shader stage.");
10515 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10516 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10518 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10521 if (late_prim_export
) {
10522 begin_divergent_if_else(ctx
, &ic
);
10523 end_divergent_if(ctx
, &ic
);
10524 bld
.reset(ctx
->block
);
10528 void select_program(Program
*program
,
10529 unsigned shader_count
,
10530 struct nir_shader
*const *shaders
,
10531 ac_shader_config
* config
,
10532 struct radv_shader_args
*args
)
10534 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10535 if_context ic_merged_wave_info
;
10536 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10538 for (unsigned i
= 0; i
< shader_count
; i
++) {
10539 nir_shader
*nir
= shaders
[i
];
10540 init_context(&ctx
, nir
);
10542 setup_fp_mode(&ctx
, nir
);
10545 /* needs to be after init_context() for FS */
10546 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10547 append_logical_start(ctx
.block
);
10549 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10550 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10552 split_arguments(&ctx
, startpgm
);
10556 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10558 if (ngg_early_prim_export(&ctx
))
10559 ngg_emit_nogs_gsthreads(&ctx
);
10562 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10563 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10564 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10565 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10566 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10567 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10568 ctx
.stage
== tess_eval_geometry_gs
));
10570 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10571 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10572 if (check_merged_wave_info
) {
10573 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10574 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10578 Builder
bld(ctx
.program
, ctx
.block
);
10580 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10581 bld
.sopp(aco_opcode::s_barrier
);
10583 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10584 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10586 } else if (ctx
.stage
== geometry_gs
)
10587 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10589 if (ctx
.stage
== fragment_fs
)
10590 handle_bc_optimize(&ctx
);
10592 visit_cf_list(&ctx
, &func
->body
);
10594 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10595 emit_streamout(&ctx
, 0);
10597 if (ctx
.stage
& hw_vs
) {
10598 create_vs_exports(&ctx
);
10599 ctx
.block
->kind
|= block_kind_export_end
;
10600 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10601 ngg_emit_nogs_output(&ctx
);
10602 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10603 Builder
bld(ctx
.program
, ctx
.block
);
10604 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10605 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10606 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10607 write_tcs_tess_factors(&ctx
);
10610 if (ctx
.stage
== fragment_fs
) {
10611 create_fs_exports(&ctx
);
10612 ctx
.block
->kind
|= block_kind_export_end
;
10615 if (endif_merged_wave_info
) {
10616 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10617 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10620 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10621 ngg_emit_nogs_output(&ctx
);
10623 ralloc_free(ctx
.divergent_vals
);
10625 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10626 /* Outputs of the previous stage are inputs to the next stage */
10627 ctx
.inputs
= ctx
.outputs
;
10628 ctx
.outputs
= shader_io_state();
10632 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10634 append_logical_end(ctx
.block
);
10635 ctx
.block
->kind
|= block_kind_uniform
;
10636 Builder
bld(ctx
.program
, ctx
.block
);
10637 if (ctx
.program
->wb_smem_l1_on_end
)
10638 bld
.smem(aco_opcode::s_dcache_wb
, false);
10639 bld
.sopp(aco_opcode::s_endpgm
);
10641 cleanup_cfg(program
);
10644 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10645 ac_shader_config
* config
,
10646 struct radv_shader_args
*args
)
10648 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10650 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10651 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10652 program
->next_fp_mode
.must_flush_denorms32
= false;
10653 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10654 program
->next_fp_mode
.care_about_round32
= false;
10655 program
->next_fp_mode
.care_about_round16_64
= false;
10656 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10657 program
->next_fp_mode
.denorm32
= 0;
10658 program
->next_fp_mode
.round32
= fp_round_ne
;
10659 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10660 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10662 add_startpgm(&ctx
);
10663 append_logical_start(ctx
.block
);
10665 Builder
bld(ctx
.program
, ctx
.block
);
10667 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10669 Operand
stream_id(0u);
10670 if (args
->shader_info
->so
.num_outputs
)
10671 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10672 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10674 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10676 std::stack
<Block
> endif_blocks
;
10678 for (unsigned stream
= 0; stream
< 4; stream
++) {
10679 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10682 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10683 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10686 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10688 unsigned BB_if_idx
= ctx
.block
->index
;
10689 Block BB_endif
= Block();
10690 if (!stream_id
.isConstant()) {
10692 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10693 append_logical_end(ctx
.block
);
10694 ctx
.block
->kind
|= block_kind_uniform
;
10695 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10697 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10699 ctx
.block
= ctx
.program
->create_and_insert_block();
10700 add_edge(BB_if_idx
, ctx
.block
);
10701 bld
.reset(ctx
.block
);
10702 append_logical_start(ctx
.block
);
10705 unsigned offset
= 0;
10706 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10707 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10710 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10711 unsigned length
= util_last_bit(output_usage_mask
);
10712 for (unsigned j
= 0; j
< length
; ++j
) {
10713 if (!(output_usage_mask
& (1 << j
)))
10716 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10717 Temp voffset
= vtx_offset
;
10718 if (const_offset
>= 4096u) {
10719 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10720 const_offset
%= 4096u;
10723 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10724 mubuf
->definitions
[0] = bld
.def(v1
);
10725 mubuf
->operands
[0] = Operand(gsvs_ring
);
10726 mubuf
->operands
[1] = Operand(voffset
);
10727 mubuf
->operands
[2] = Operand(0u);
10728 mubuf
->offen
= true;
10729 mubuf
->offset
= const_offset
;
10732 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10733 mubuf
->barrier
= barrier_none
;
10734 mubuf
->can_reorder
= true;
10736 ctx
.outputs
.mask
[i
] |= 1 << j
;
10737 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10739 bld
.insert(std::move(mubuf
));
10745 if (args
->shader_info
->so
.num_outputs
) {
10746 emit_streamout(&ctx
, stream
);
10747 bld
.reset(ctx
.block
);
10751 create_vs_exports(&ctx
);
10752 ctx
.block
->kind
|= block_kind_export_end
;
10755 if (!stream_id
.isConstant()) {
10756 append_logical_end(ctx
.block
);
10758 /* branch from then block to endif block */
10759 bld
.branch(aco_opcode::p_branch
);
10760 add_edge(ctx
.block
->index
, &BB_endif
);
10761 ctx
.block
->kind
|= block_kind_uniform
;
10763 /* emit else block */
10764 ctx
.block
= ctx
.program
->create_and_insert_block();
10765 add_edge(BB_if_idx
, ctx
.block
);
10766 bld
.reset(ctx
.block
);
10767 append_logical_start(ctx
.block
);
10769 endif_blocks
.push(std::move(BB_endif
));
10773 while (!endif_blocks
.empty()) {
10774 Block BB_endif
= std::move(endif_blocks
.top());
10775 endif_blocks
.pop();
10777 Block
*BB_else
= ctx
.block
;
10779 append_logical_end(BB_else
);
10780 /* branch from else block to endif block */
10781 bld
.branch(aco_opcode::p_branch
);
10782 add_edge(BB_else
->index
, &BB_endif
);
10783 BB_else
->kind
|= block_kind_uniform
;
10785 /** emit endif merge block */
10786 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10787 bld
.reset(ctx
.block
);
10788 append_logical_start(ctx
.block
);
10791 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10793 append_logical_end(ctx
.block
);
10794 ctx
.block
->kind
|= block_kind_uniform
;
10795 bld
.sopp(aco_opcode::s_endpgm
);
10797 cleanup_cfg(program
);