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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
721 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
723 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
724 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
725 aco_opcode op
= use_valu
? v_op
: s_op
;
726 assert(op
!= aco_opcode::num_opcodes
);
727 assert(dst
.regClass() == ctx
->program
->lane_mask
);
730 emit_vopc_instruction(ctx
, instr
, op
, dst
);
732 emit_sopc_instruction(ctx
, instr
, op
, dst
);
735 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
737 Builder
bld(ctx
->program
, ctx
->block
);
738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
741 assert(dst
.regClass() == bld
.lm
);
742 assert(src0
.regClass() == bld
.lm
);
743 assert(src1
.regClass() == bld
.lm
);
745 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
748 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
750 Builder
bld(ctx
->program
, ctx
->block
);
751 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
752 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
753 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
755 assert(cond
.regClass() == bld
.lm
);
757 if (dst
.type() == RegType::vgpr
) {
758 aco_ptr
<Instruction
> bcsel
;
759 if (dst
.regClass() == v2b
) {
760 then
= as_vgpr(ctx
, then
);
761 els
= as_vgpr(ctx
, els
);
763 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
765 } else if (dst
.regClass() == v1
) {
766 then
= as_vgpr(ctx
, then
);
767 els
= as_vgpr(ctx
, els
);
769 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
770 } else if (dst
.regClass() == v2
) {
771 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
773 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
776 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
777 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
781 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
782 nir_print_instr(&instr
->instr
, stderr
);
783 fprintf(stderr
, "\n");
788 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
789 assert(dst
.regClass() == bld
.lm
);
790 assert(then
.regClass() == bld
.lm
);
791 assert(els
.regClass() == bld
.lm
);
794 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
795 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
796 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
797 assert(dst
.size() == then
.size());
798 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
799 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
801 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
802 nir_print_instr(&instr
->instr
, stderr
);
803 fprintf(stderr
, "\n");
808 /* divergent boolean bcsel
809 * this implements bcsel on bools: dst = s0 ? s1 : s2
810 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
811 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
813 if (cond
.id() != then
.id())
814 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
816 if (cond
.id() == els
.id())
817 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
819 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
820 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
823 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
824 aco_opcode op
, uint32_t undo
)
826 /* multiply by 16777216 to handle denormals */
827 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
828 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
829 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
830 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
831 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
833 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
835 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
838 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
840 if (ctx
->block
->fp_mode
.denorm32
== 0) {
841 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
845 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
848 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
850 if (ctx
->block
->fp_mode
.denorm32
== 0) {
851 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
855 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
858 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
860 if (ctx
->block
->fp_mode
.denorm32
== 0) {
861 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
865 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
868 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
870 if (ctx
->block
->fp_mode
.denorm32
== 0) {
871 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
875 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
878 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
880 if (ctx
->options
->chip_class
>= GFX7
)
881 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
883 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
884 /* TODO: create more efficient code! */
885 if (val
.type() == RegType::sgpr
)
886 val
= as_vgpr(ctx
, val
);
888 /* Split the input value. */
889 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
890 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
892 /* Extract the exponent and compute the unbiased value. */
893 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
895 /* Extract the fractional part. */
896 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
897 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
899 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
902 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
903 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
904 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
905 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
906 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
908 /* Get the sign bit. */
909 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
911 /* Decide the operation to apply depending on the unbiased exponent. */
912 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
913 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
914 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
915 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
916 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
917 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
919 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
922 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->options
->chip_class
>= GFX7
)
925 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
927 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
928 Temp src0
= as_vgpr(ctx
, val
);
930 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
931 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
933 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
934 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
935 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
937 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
939 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
942 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
943 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
945 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
947 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
948 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
950 return add
->definitions
[0].getTemp();
953 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
955 if (!instr
->dest
.dest
.is_ssa
) {
956 fprintf(stderr
, "nir alu dst not in ssa: ");
957 nir_print_instr(&instr
->instr
, stderr
);
958 fprintf(stderr
, "\n");
961 Builder
bld(ctx
->program
, ctx
->block
);
962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
967 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
968 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
969 for (unsigned i
= 0; i
< num
; ++i
)
970 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
972 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
973 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
974 for (unsigned i
= 0; i
< num
; ++i
)
975 vec
->operands
[i
] = Operand
{elems
[i
]};
976 vec
->definitions
[0] = Definition(dst
);
977 ctx
->block
->instructions
.emplace_back(std::move(vec
));
978 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
980 // TODO: that is a bit suboptimal..
981 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
982 for (unsigned i
= 0; i
< num
- 1; ++i
)
983 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
984 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
985 for (unsigned i
= 0; i
< num
; ++i
) {
986 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
988 elems
[bit
/ 32] = elems
[i
];
990 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
991 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
992 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
996 bld
.copy(Definition(dst
), elems
[0]);
998 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1003 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1004 aco_ptr
<Instruction
> mov
;
1005 if (dst
.type() == RegType::sgpr
) {
1006 if (src
.type() == RegType::vgpr
)
1007 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1008 else if (src
.regClass() == s1
)
1009 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1010 else if (src
.regClass() == s2
)
1011 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1013 unreachable("wrong src register class for nir_op_imov");
1014 } else if (dst
.regClass() == v1
) {
1015 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1016 } else if (dst
.regClass() == v2
) {
1017 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1019 nir_print_instr(&instr
->instr
, stderr
);
1020 unreachable("Should have been lowered to scalar.");
1025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1026 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1027 assert(src
.regClass() == bld
.lm
);
1028 assert(dst
.regClass() == bld
.lm
);
1029 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1030 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1031 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1032 } else if (dst
.regClass() == v1
) {
1033 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1034 } else if (dst
.type() == RegType::sgpr
) {
1035 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1036 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1038 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1039 nir_print_instr(&instr
->instr
, stderr
);
1040 fprintf(stderr
, "\n");
1045 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1046 if (dst
.regClass() == v1
) {
1047 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1048 } else if (dst
.regClass() == s1
) {
1049 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1050 } else if (dst
.size() == 2) {
1051 Temp src0
= bld
.tmp(dst
.type(), 1);
1052 Temp src1
= bld
.tmp(dst
.type(), 1);
1053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1055 if (dst
.regClass() == s2
) {
1056 Temp carry
= bld
.tmp(s1
);
1057 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1058 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1061 Temp lower
= bld
.tmp(v1
);
1062 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1063 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1064 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1067 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1068 nir_print_instr(&instr
->instr
, stderr
);
1069 fprintf(stderr
, "\n");
1074 if (dst
.regClass() == s1
) {
1075 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1076 } else if (dst
.regClass() == v1
) {
1077 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1078 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1081 nir_print_instr(&instr
->instr
, stderr
);
1082 fprintf(stderr
, "\n");
1086 case nir_op_isign
: {
1087 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1088 if (dst
.regClass() == s1
) {
1089 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1090 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1091 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1092 } else if (dst
.regClass() == s2
) {
1093 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1095 if (ctx
->program
->chip_class
>= GFX8
)
1096 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1098 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1099 /* SCC gets zero-extended to 64 bit */
1100 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1101 } else if (dst
.regClass() == v1
) {
1102 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1103 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1104 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1105 } else if (dst
.regClass() == v2
) {
1106 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1107 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1108 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1109 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1110 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (dst
.regClass() == v1
) {
1145 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1146 } else if (dst
.regClass() == s1
) {
1147 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1149 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1150 nir_print_instr(&instr
->instr
, stderr
);
1151 fprintf(stderr
, "\n");
1156 if (dst
.regClass() == v1
) {
1157 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1158 } else if (dst
.regClass() == s1
) {
1159 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1161 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1162 nir_print_instr(&instr
->instr
, stderr
);
1163 fprintf(stderr
, "\n");
1168 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1169 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1170 } else if (dst
.regClass() == v1
) {
1171 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1172 } else if (dst
.regClass() == s1
) {
1173 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1174 } else if (dst
.regClass() == s2
) {
1175 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1177 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1178 nir_print_instr(&instr
->instr
, stderr
);
1179 fprintf(stderr
, "\n");
1184 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1185 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1186 } else if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1190 } else if (dst
.regClass() == s2
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1201 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1202 } else if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1206 } else if (dst
.regClass() == s2
) {
1207 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1209 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1210 nir_print_instr(&instr
->instr
, stderr
);
1211 fprintf(stderr
, "\n");
1216 if (dst
.regClass() == v1
) {
1217 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1218 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1219 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1220 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1221 } else if (dst
.regClass() == v2
) {
1222 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1223 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1224 } else if (dst
.regClass() == s2
) {
1225 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1230 nir_print_instr(&instr
->instr
, stderr
);
1231 fprintf(stderr
, "\n");
1236 if (dst
.regClass() == v1
) {
1237 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1238 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1239 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1241 } else if (dst
.regClass() == v2
) {
1242 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1243 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1244 } else if (dst
.regClass() == s1
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1246 } else if (dst
.regClass() == s2
) {
1247 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1249 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1250 nir_print_instr(&instr
->instr
, stderr
);
1251 fprintf(stderr
, "\n");
1256 if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1258 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1259 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1260 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1261 } else if (dst
.regClass() == v2
) {
1262 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1263 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1264 } else if (dst
.regClass() == s1
) {
1265 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1266 } else if (dst
.regClass() == s2
) {
1267 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_find_lsb
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (src
.regClass() == s1
) {
1278 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1279 } else if (src
.regClass() == v1
) {
1280 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1281 } else if (src
.regClass() == s2
) {
1282 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1290 case nir_op_ufind_msb
:
1291 case nir_op_ifind_msb
: {
1292 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1293 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1294 aco_opcode op
= src
.regClass() == s2
?
1295 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1296 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1297 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1299 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1300 Operand(src
.size() * 32u - 1u), msb_rev
);
1301 Temp msb
= sub
.def(0).getTemp();
1302 Temp carry
= sub
.def(1).getTemp();
1304 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1305 } else if (src
.regClass() == v1
) {
1306 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1307 Temp msb_rev
= bld
.tmp(v1
);
1308 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1309 Temp msb
= bld
.tmp(v1
);
1310 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1311 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_bitfield_reverse
: {
1320 if (dst
.regClass() == s1
) {
1321 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1322 } else if (dst
.regClass() == v1
) {
1323 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1332 if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1337 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1338 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1339 if (dst
.regClass() == v1
) {
1340 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1344 assert(src0
.size() == 2 && src1
.size() == 2);
1345 Temp src00
= bld
.tmp(src0
.type(), 1);
1346 Temp src01
= bld
.tmp(dst
.type(), 1);
1347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1348 Temp src10
= bld
.tmp(src1
.type(), 1);
1349 Temp src11
= bld
.tmp(dst
.type(), 1);
1350 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1352 if (dst
.regClass() == s2
) {
1353 Temp carry
= bld
.tmp(s1
);
1354 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1355 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1357 } else if (dst
.regClass() == v2
) {
1358 Temp dst0
= bld
.tmp(v1
);
1359 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1360 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1363 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1364 nir_print_instr(&instr
->instr
, stderr
);
1365 fprintf(stderr
, "\n");
1369 case nir_op_uadd_sat
: {
1370 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1371 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1372 if (dst
.regClass() == s1
) {
1373 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1374 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1376 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1377 } else if (dst
.regClass() == v1
) {
1378 if (ctx
->options
->chip_class
>= GFX9
) {
1379 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1380 add
->operands
[0] = Operand(src0
);
1381 add
->operands
[1] = Operand(src1
);
1382 add
->definitions
[0] = Definition(dst
);
1384 ctx
->block
->instructions
.emplace_back(std::move(add
));
1386 if (src1
.regClass() != v1
)
1387 std::swap(src0
, src1
);
1388 assert(src1
.regClass() == v1
);
1389 Temp tmp
= bld
.tmp(v1
);
1390 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1391 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1394 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1395 nir_print_instr(&instr
->instr
, stderr
);
1396 fprintf(stderr
, "\n");
1400 case nir_op_uadd_carry
: {
1401 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1402 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1403 if (dst
.regClass() == s1
) {
1404 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1407 if (dst
.regClass() == v1
) {
1408 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1409 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1413 Temp src00
= bld
.tmp(src0
.type(), 1);
1414 Temp src01
= bld
.tmp(dst
.type(), 1);
1415 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1416 Temp src10
= bld
.tmp(src1
.type(), 1);
1417 Temp src11
= bld
.tmp(dst
.type(), 1);
1418 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1419 if (dst
.regClass() == s2
) {
1420 Temp carry
= bld
.tmp(s1
);
1421 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1422 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1423 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1424 } else if (dst
.regClass() == v2
) {
1425 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1426 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1427 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1430 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1431 nir_print_instr(&instr
->instr
, stderr
);
1432 fprintf(stderr
, "\n");
1437 if (dst
.regClass() == s1
) {
1438 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == v1
) {
1445 bld
.vsub32(Definition(dst
), src0
, src1
);
1449 Temp src00
= bld
.tmp(src0
.type(), 1);
1450 Temp src01
= bld
.tmp(dst
.type(), 1);
1451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1452 Temp src10
= bld
.tmp(src1
.type(), 1);
1453 Temp src11
= bld
.tmp(dst
.type(), 1);
1454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1455 if (dst
.regClass() == s2
) {
1456 Temp carry
= bld
.tmp(s1
);
1457 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1458 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1459 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1460 } else if (dst
.regClass() == v2
) {
1461 Temp lower
= bld
.tmp(v1
);
1462 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1463 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1466 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1467 nir_print_instr(&instr
->instr
, stderr
);
1468 fprintf(stderr
, "\n");
1472 case nir_op_usub_borrow
: {
1473 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1474 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1475 if (dst
.regClass() == s1
) {
1476 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1478 } else if (dst
.regClass() == v1
) {
1479 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1480 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1484 Temp src00
= bld
.tmp(src0
.type(), 1);
1485 Temp src01
= bld
.tmp(dst
.type(), 1);
1486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1487 Temp src10
= bld
.tmp(src1
.type(), 1);
1488 Temp src11
= bld
.tmp(dst
.type(), 1);
1489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1490 if (dst
.regClass() == s2
) {
1491 Temp borrow
= bld
.tmp(s1
);
1492 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1493 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1495 } else if (dst
.regClass() == v2
) {
1496 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1497 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1498 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1499 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1501 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1502 nir_print_instr(&instr
->instr
, stderr
);
1503 fprintf(stderr
, "\n");
1508 if (dst
.regClass() == v1
) {
1509 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1510 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1511 } else if (dst
.regClass() == s1
) {
1512 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1515 nir_print_instr(&instr
->instr
, stderr
);
1516 fprintf(stderr
, "\n");
1520 case nir_op_umul_high
: {
1521 if (dst
.regClass() == v1
) {
1522 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1523 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1524 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1525 } else if (dst
.regClass() == s1
) {
1526 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1527 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1528 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1530 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1531 nir_print_instr(&instr
->instr
, stderr
);
1532 fprintf(stderr
, "\n");
1536 case nir_op_imul_high
: {
1537 if (dst
.regClass() == v1
) {
1538 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1539 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1540 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1541 } else if (dst
.regClass() == s1
) {
1542 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1543 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1544 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1546 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1547 nir_print_instr(&instr
->instr
, stderr
);
1548 fprintf(stderr
, "\n");
1553 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1554 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1555 if (dst
.regClass() == v2b
) {
1556 Temp tmp
= bld
.tmp(v1
);
1557 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1558 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1559 } else if (dst
.regClass() == v1
) {
1560 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1561 } else if (dst
.regClass() == v2
) {
1562 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1564 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1565 nir_print_instr(&instr
->instr
, stderr
);
1566 fprintf(stderr
, "\n");
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1573 if (dst
.regClass() == v2b
) {
1574 Temp tmp
= bld
.tmp(v1
);
1575 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1576 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1577 } else if (dst
.regClass() == v1
) {
1578 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1579 } else if (dst
.regClass() == v2
) {
1580 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1582 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1583 nir_print_instr(&instr
->instr
, stderr
);
1584 fprintf(stderr
, "\n");
1589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1590 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1591 if (dst
.regClass() == v2b
) {
1592 Temp tmp
= bld
.tmp(v1
);
1593 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1594 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1596 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1598 } else if (dst
.regClass() == v1
) {
1599 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1606 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1609 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1610 nir_print_instr(&instr
->instr
, stderr
);
1611 fprintf(stderr
, "\n");
1616 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1617 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1618 if (dst
.regClass() == v2b
) {
1619 // TODO: check fp_mode.must_flush_denorms16_64
1620 Temp tmp
= bld
.tmp(v1
);
1621 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1622 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1623 } else if (dst
.regClass() == v1
) {
1624 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1625 } else if (dst
.regClass() == v2
) {
1626 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1627 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1628 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1630 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1634 nir_print_instr(&instr
->instr
, stderr
);
1635 fprintf(stderr
, "\n");
1640 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1641 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1642 if (dst
.regClass() == v2b
) {
1643 // TODO: check fp_mode.must_flush_denorms16_64
1644 Temp tmp
= bld
.tmp(v1
);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1647 } else if (dst
.regClass() == v1
) {
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1649 } else if (dst
.regClass() == v2
) {
1650 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1651 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1652 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1654 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1663 case nir_op_fmax3
: {
1664 if (dst
.regClass() == v2b
) {
1665 Temp tmp
= bld
.tmp(v1
);
1666 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1667 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1668 } else if (dst
.regClass() == v1
) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_fmin3
: {
1678 if (dst
.regClass() == v2b
) {
1679 Temp tmp
= bld
.tmp(v1
);
1680 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1682 } else if (dst
.regClass() == v1
) {
1683 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1691 case nir_op_fmed3
: {
1692 if (dst
.regClass() == v2b
) {
1693 Temp tmp
= bld
.tmp(v1
);
1694 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1695 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1696 } else if (dst
.regClass() == v1
) {
1697 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1700 nir_print_instr(&instr
->instr
, stderr
);
1701 fprintf(stderr
, "\n");
1705 case nir_op_umax3
: {
1706 if (dst
.size() == 1) {
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1710 nir_print_instr(&instr
->instr
, stderr
);
1711 fprintf(stderr
, "\n");
1715 case nir_op_umin3
: {
1716 if (dst
.size() == 1) {
1717 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1720 nir_print_instr(&instr
->instr
, stderr
);
1721 fprintf(stderr
, "\n");
1725 case nir_op_umed3
: {
1726 if (dst
.size() == 1) {
1727 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_imax3
: {
1736 if (dst
.size() == 1) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1745 case nir_op_imin3
: {
1746 if (dst
.size() == 1) {
1747 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1750 nir_print_instr(&instr
->instr
, stderr
);
1751 fprintf(stderr
, "\n");
1755 case nir_op_imed3
: {
1756 if (dst
.size() == 1) {
1757 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1765 case nir_op_cube_face_coord
: {
1766 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1767 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1768 emit_extract_vector(ctx
, in
, 1, v1
),
1769 emit_extract_vector(ctx
, in
, 2, v1
) };
1770 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1771 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1772 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1773 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1774 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1775 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1776 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1779 case nir_op_cube_face_index
: {
1780 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1781 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1782 emit_extract_vector(ctx
, in
, 1, v1
),
1783 emit_extract_vector(ctx
, in
, 2, v1
) };
1784 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1787 case nir_op_bcsel
: {
1788 emit_bcsel(ctx
, instr
, dst
);
1792 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1793 if (dst
.regClass() == v2b
) {
1794 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1796 } else if (dst
.regClass() == v1
) {
1797 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1798 } else if (dst
.regClass() == v2
) {
1799 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1802 nir_print_instr(&instr
->instr
, stderr
);
1803 fprintf(stderr
, "\n");
1808 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1809 if (dst
.regClass() == v2b
) {
1810 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1811 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1812 } else if (dst
.regClass() == v1
) {
1813 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1814 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1815 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1816 } else if (dst
.regClass() == v2
) {
1817 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1818 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1819 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1820 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1821 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1822 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1825 nir_print_instr(&instr
->instr
, stderr
);
1826 fprintf(stderr
, "\n");
1831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1832 if (dst
.regClass() == v2b
) {
1833 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1834 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1835 } else if (dst
.regClass() == v1
) {
1836 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1837 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1839 } else if (dst
.regClass() == v2
) {
1840 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1841 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1842 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1844 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1847 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1848 nir_print_instr(&instr
->instr
, stderr
);
1849 fprintf(stderr
, "\n");
1854 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1855 if (dst
.regClass() == v2b
) {
1856 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1858 } else if (dst
.regClass() == v1
) {
1859 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1860 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1861 // TODO: confirm that this holds under any circumstances
1862 } else if (dst
.regClass() == v2
) {
1863 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1864 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1867 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1868 nir_print_instr(&instr
->instr
, stderr
);
1869 fprintf(stderr
, "\n");
1873 case nir_op_flog2
: {
1874 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1875 if (dst
.regClass() == v2b
) {
1876 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1878 } else if (dst
.regClass() == v1
) {
1879 emit_log2(ctx
, bld
, Definition(dst
), src
);
1881 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1882 nir_print_instr(&instr
->instr
, stderr
);
1883 fprintf(stderr
, "\n");
1888 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1889 if (dst
.regClass() == v2b
) {
1890 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1892 } else if (dst
.regClass() == v1
) {
1893 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1894 } else if (dst
.regClass() == v2
) {
1895 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1898 nir_print_instr(&instr
->instr
, stderr
);
1899 fprintf(stderr
, "\n");
1903 case nir_op_fexp2
: {
1904 if (dst
.regClass() == v2b
) {
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1907 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1912 nir_print_instr(&instr
->instr
, stderr
);
1913 fprintf(stderr
, "\n");
1917 case nir_op_fsqrt
: {
1918 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1919 if (dst
.regClass() == v2b
) {
1920 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1922 } else if (dst
.regClass() == v1
) {
1923 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1924 } else if (dst
.regClass() == v2
) {
1925 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1927 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1928 nir_print_instr(&instr
->instr
, stderr
);
1929 fprintf(stderr
, "\n");
1933 case nir_op_ffract
: {
1934 if (dst
.regClass() == v2b
) {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1940 } else if (dst
.regClass() == v2
) {
1941 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1943 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1944 nir_print_instr(&instr
->instr
, stderr
);
1945 fprintf(stderr
, "\n");
1949 case nir_op_ffloor
: {
1950 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1951 if (dst
.regClass() == v2b
) {
1952 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1953 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1954 } else if (dst
.regClass() == v1
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1956 } else if (dst
.regClass() == v2
) {
1957 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1959 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1960 nir_print_instr(&instr
->instr
, stderr
);
1961 fprintf(stderr
, "\n");
1965 case nir_op_fceil
: {
1966 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1967 if (dst
.regClass() == v2b
) {
1968 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
1969 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 if (ctx
->options
->chip_class
>= GFX7
) {
1974 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1976 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1977 /* trunc = trunc(src0)
1978 * if (src0 > 0.0 && src0 != trunc)
1981 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1982 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1983 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1984 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1985 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1986 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1987 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1996 case nir_op_ftrunc
: {
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2000 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2001 } else if (dst
.regClass() == v1
) {
2002 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2003 } else if (dst
.regClass() == v2
) {
2004 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fround_even
: {
2013 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2016 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2017 } else if (dst
.regClass() == v1
) {
2018 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2019 } else if (dst
.regClass() == v2
) {
2020 if (ctx
->options
->chip_class
>= GFX7
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2023 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2024 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2025 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2027 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2028 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2029 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2030 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2032 tmp
= sub
->definitions
[0].getTemp();
2034 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2035 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2036 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2037 Temp cond
= vop3
->definitions
[0].getTemp();
2039 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2040 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2041 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2042 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2044 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2055 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2056 aco_ptr
<Instruction
> norm
;
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2058 if (dst
.regClass() == v2b
) {
2059 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2060 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2061 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2066 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2067 if (ctx
->options
->chip_class
< GFX9
)
2068 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2070 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2071 bld
.vop1(opcode
, Definition(dst
), tmp
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_ldexp
: {
2080 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2081 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2082 if (dst
.regClass() == v2b
) {
2083 Temp tmp
= bld
.tmp(v1
);
2084 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2085 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2086 } else if (dst
.regClass() == v1
) {
2087 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 } else if (dst
.regClass() == v2
) {
2089 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2091 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2092 nir_print_instr(&instr
->instr
, stderr
);
2093 fprintf(stderr
, "\n");
2097 case nir_op_frexp_sig
: {
2098 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2101 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2102 } else if (dst
.regClass() == v1
) {
2103 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2104 } else if (dst
.regClass() == v2
) {
2105 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2107 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2108 nir_print_instr(&instr
->instr
, stderr
);
2109 fprintf(stderr
, "\n");
2113 case nir_op_frexp_exp
: {
2114 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2115 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2116 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2117 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), tmp
, Operand(0u));
2118 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2119 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2120 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2121 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_fsign
: {
2130 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2131 if (dst
.regClass() == v2b
) {
2132 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2133 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2134 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2135 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2136 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2137 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2141 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2142 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2143 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2144 } else if (dst
.regClass() == v2
) {
2145 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2146 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2147 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2149 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2155 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2156 nir_print_instr(&instr
->instr
, stderr
);
2157 fprintf(stderr
, "\n");
2162 case nir_op_f2f16_rtne
: {
2163 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2164 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2165 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2166 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2167 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2170 case nir_op_f2f16_rtz
: {
2171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2172 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2173 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2174 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2178 case nir_op_f2f32
: {
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2180 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2181 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2182 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2184 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2185 nir_print_instr(&instr
->instr
, stderr
);
2186 fprintf(stderr
, "\n");
2190 case nir_op_f2f64
: {
2191 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2192 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2193 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2194 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2197 case nir_op_i2f16
: {
2198 assert(dst
.regClass() == v2b
);
2199 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
),
2200 get_alu_src(ctx
, instr
->src
[0]));
2201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2204 case nir_op_i2f32
: {
2205 assert(dst
.size() == 1);
2206 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2209 case nir_op_i2f64
: {
2210 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2211 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2212 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 RegClass rc
= RegClass(src
.type(), 1);
2215 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2217 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2218 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2219 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2220 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2223 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2224 nir_print_instr(&instr
->instr
, stderr
);
2225 fprintf(stderr
, "\n");
2229 case nir_op_u2f16
: {
2230 assert(dst
.regClass() == v2b
);
2231 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
),
2232 get_alu_src(ctx
, instr
->src
[0]));
2233 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2236 case nir_op_u2f32
: {
2237 assert(dst
.size() == 1);
2238 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2241 case nir_op_u2f64
: {
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2243 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2244 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 RegClass rc
= RegClass(src
.type(), 1);
2247 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2248 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2249 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2250 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2251 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2252 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2254 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2255 nir_print_instr(&instr
->instr
, stderr
);
2256 fprintf(stderr
, "\n");
2260 case nir_op_f2i16
: {
2261 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2262 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2263 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2264 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2265 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2267 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2269 if (dst
.type() == RegType::vgpr
)
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2272 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2275 case nir_op_f2u16
: {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2278 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2279 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2280 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2282 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2284 if (dst
.type() == RegType::vgpr
)
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2287 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2290 case nir_op_f2i32
: {
2291 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2292 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2293 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2294 if (dst
.type() == RegType::vgpr
) {
2295 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2297 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2298 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2300 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2301 if (dst
.type() == RegType::vgpr
)
2302 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2305 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 if (dst
.type() == RegType::vgpr
)
2309 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2311 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2312 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2315 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2316 nir_print_instr(&instr
->instr
, stderr
);
2317 fprintf(stderr
, "\n");
2321 case nir_op_f2u32
: {
2322 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2323 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2324 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2325 if (dst
.type() == RegType::vgpr
) {
2326 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2328 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2329 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2331 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2332 if (dst
.type() == RegType::vgpr
)
2333 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2346 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2347 nir_print_instr(&instr
->instr
, stderr
);
2348 fprintf(stderr
, "\n");
2352 case nir_op_f2i64
: {
2353 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2354 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2355 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2356 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2357 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2358 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2359 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2360 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2361 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2362 Temp new_exponent
= bld
.tmp(v1
);
2363 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2364 if (ctx
->program
->chip_class
>= GFX8
)
2365 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2367 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2368 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2369 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2370 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2371 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2372 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2373 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2374 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2375 Temp new_lower
= bld
.tmp(v1
);
2376 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2377 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2378 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2380 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2381 if (src
.type() == RegType::vgpr
)
2382 src
= bld
.as_uniform(src
);
2383 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2384 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2385 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2386 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2387 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2388 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2389 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2390 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2391 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2392 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2393 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2394 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2395 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2396 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2397 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2398 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2399 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2400 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2401 Temp borrow
= bld
.tmp(s1
);
2402 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2403 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2406 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2407 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2408 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2409 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2410 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2411 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2412 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2413 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2414 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2415 if (dst
.type() == RegType::sgpr
) {
2416 lower
= bld
.as_uniform(lower
);
2417 upper
= bld
.as_uniform(upper
);
2419 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2422 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2423 nir_print_instr(&instr
->instr
, stderr
);
2424 fprintf(stderr
, "\n");
2428 case nir_op_f2u64
: {
2429 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2430 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2431 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2432 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2433 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2434 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2435 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2436 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2437 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2438 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2439 Temp new_exponent
= bld
.tmp(v1
);
2440 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2441 if (ctx
->program
->chip_class
>= GFX8
)
2442 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2444 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2445 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2446 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2447 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2448 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2449 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2450 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2453 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2454 if (src
.type() == RegType::vgpr
)
2455 src
= bld
.as_uniform(src
);
2456 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2457 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2458 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2459 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2460 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2461 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2462 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2463 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2464 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2465 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2466 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2467 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2468 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2469 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2470 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2471 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2472 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2473 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2475 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2476 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2477 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2478 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2479 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2480 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2481 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2482 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2483 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2484 if (dst
.type() == RegType::sgpr
) {
2485 lower
= bld
.as_uniform(lower
);
2486 upper
= bld
.as_uniform(upper
);
2488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2491 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2492 nir_print_instr(&instr
->instr
, stderr
);
2493 fprintf(stderr
, "\n");
2497 case nir_op_b2f16
: {
2498 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2499 assert(src
.regClass() == bld
.lm
);
2501 if (dst
.regClass() == s1
) {
2502 src
= bool_to_scalar_condition(ctx
, src
);
2503 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2504 } else if (dst
.regClass() == v2b
) {
2505 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2506 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2507 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2509 unreachable("Wrong destination register class for nir_op_b2f16.");
2513 case nir_op_b2f32
: {
2514 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2515 assert(src
.regClass() == bld
.lm
);
2517 if (dst
.regClass() == s1
) {
2518 src
= bool_to_scalar_condition(ctx
, src
);
2519 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2520 } else if (dst
.regClass() == v1
) {
2521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2523 unreachable("Wrong destination register class for nir_op_b2f32.");
2527 case nir_op_b2f64
: {
2528 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2529 assert(src
.regClass() == bld
.lm
);
2531 if (dst
.regClass() == s2
) {
2532 src
= bool_to_scalar_condition(ctx
, src
);
2533 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2534 } else if (dst
.regClass() == v2
) {
2535 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2536 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2539 unreachable("Wrong destination register class for nir_op_b2f64.");
2545 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2546 /* we can actually just say dst = src */
2547 if (src
.regClass() == s1
)
2548 bld
.copy(Definition(dst
), src
);
2550 emit_extract_vector(ctx
, src
, 0, dst
);
2553 case nir_op_i2i16
: {
2554 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2555 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2556 if (dst
.regClass() == s1
) {
2557 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2559 assert(src
.regClass() == v1b
);
2560 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2561 sdwa
->operands
[0] = Operand(src
);
2562 sdwa
->definitions
[0] = Definition(dst
);
2563 sdwa
->sel
[0] = sdwa_sbyte
;
2564 sdwa
->dst_sel
= sdwa_sword
;
2565 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2568 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2569 /* we can actually just say dst = src */
2570 if (src
.regClass() == s1
)
2571 bld
.copy(Definition(dst
), src
);
2573 emit_extract_vector(ctx
, src
, 0, dst
);
2577 case nir_op_u2u16
: {
2578 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2579 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2580 if (dst
.regClass() == s1
)
2581 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2583 assert(src
.regClass() == v1b
);
2584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2585 sdwa
->operands
[0] = Operand(src
);
2586 sdwa
->definitions
[0] = Definition(dst
);
2587 sdwa
->sel
[0] = sdwa_ubyte
;
2588 sdwa
->dst_sel
= sdwa_uword
;
2589 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 /* we can actually just say dst = src */
2594 if (src
.regClass() == s1
)
2595 bld
.copy(Definition(dst
), src
);
2597 emit_extract_vector(ctx
, src
, 0, dst
);
2601 case nir_op_i2i32
: {
2602 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2603 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2604 if (dst
.regClass() == s1
) {
2605 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2607 assert(src
.regClass() == v1b
);
2608 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2609 sdwa
->operands
[0] = Operand(src
);
2610 sdwa
->definitions
[0] = Definition(dst
);
2611 sdwa
->sel
[0] = sdwa_sbyte
;
2612 sdwa
->dst_sel
= sdwa_sdword
;
2613 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2615 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2616 if (dst
.regClass() == s1
) {
2617 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2619 assert(src
.regClass() == v2b
);
2620 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2621 sdwa
->operands
[0] = Operand(src
);
2622 sdwa
->definitions
[0] = Definition(dst
);
2623 sdwa
->sel
[0] = sdwa_sword
;
2624 sdwa
->dst_sel
= sdwa_udword
;
2625 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2627 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2628 /* we can actually just say dst = src, as it would map the lower register */
2629 emit_extract_vector(ctx
, src
, 0, dst
);
2631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2632 nir_print_instr(&instr
->instr
, stderr
);
2633 fprintf(stderr
, "\n");
2637 case nir_op_u2u32
: {
2638 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2639 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2640 if (dst
.regClass() == s1
)
2641 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2643 assert(src
.regClass() == v1b
);
2644 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2645 sdwa
->operands
[0] = Operand(src
);
2646 sdwa
->definitions
[0] = Definition(dst
);
2647 sdwa
->sel
[0] = sdwa_ubyte
;
2648 sdwa
->dst_sel
= sdwa_udword
;
2649 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2651 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2652 if (dst
.regClass() == s1
) {
2653 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2655 assert(src
.regClass() == v2b
);
2656 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2657 sdwa
->operands
[0] = Operand(src
);
2658 sdwa
->definitions
[0] = Definition(dst
);
2659 sdwa
->sel
[0] = sdwa_uword
;
2660 sdwa
->dst_sel
= sdwa_udword
;
2661 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2663 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2664 /* we can actually just say dst = src, as it would map the lower register */
2665 emit_extract_vector(ctx
, src
, 0, dst
);
2667 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2668 nir_print_instr(&instr
->instr
, stderr
);
2669 fprintf(stderr
, "\n");
2673 case nir_op_i2i64
: {
2674 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2675 if (src
.regClass() == s1
) {
2676 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2677 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2678 } else if (src
.regClass() == v1
) {
2679 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2680 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2682 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2683 nir_print_instr(&instr
->instr
, stderr
);
2684 fprintf(stderr
, "\n");
2688 case nir_op_u2u64
: {
2689 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2690 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2691 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2694 nir_print_instr(&instr
->instr
, stderr
);
2695 fprintf(stderr
, "\n");
2700 case nir_op_b2i32
: {
2701 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2702 assert(src
.regClass() == bld
.lm
);
2704 if (dst
.regClass() == s1
) {
2705 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2706 bool_to_scalar_condition(ctx
, src
, dst
);
2707 } else if (dst
.regClass() == v1
) {
2708 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2710 unreachable("Invalid register class for b2i32");
2716 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2717 assert(dst
.regClass() == bld
.lm
);
2719 if (src
.type() == RegType::vgpr
) {
2720 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2721 assert(dst
.regClass() == bld
.lm
);
2722 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2723 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2725 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2727 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2728 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2730 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2731 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2733 bool_to_vector_condition(ctx
, tmp
, dst
);
2737 case nir_op_pack_64_2x32_split
: {
2738 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2739 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2741 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2744 case nir_op_unpack_64_2x32_split_x
:
2745 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2747 case nir_op_unpack_64_2x32_split_y
:
2748 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2750 case nir_op_unpack_32_2x16_split_x
:
2751 if (dst
.type() == RegType::vgpr
) {
2752 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2754 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2757 case nir_op_unpack_32_2x16_split_y
:
2758 if (dst
.type() == RegType::vgpr
) {
2759 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2761 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2764 case nir_op_pack_32_2x16_split
: {
2765 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2766 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2767 if (dst
.regClass() == v1
) {
2768 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2770 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2771 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2772 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2776 case nir_op_pack_half_2x16
: {
2777 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2779 if (dst
.regClass() == v1
) {
2780 Temp src0
= bld
.tmp(v1
);
2781 Temp src1
= bld
.tmp(v1
);
2782 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2783 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2784 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2786 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2787 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2788 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_unpack_half_2x16_split_x
: {
2797 if (dst
.regClass() == v1
) {
2798 Builder
bld(ctx
->program
, ctx
->block
);
2799 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2801 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2802 nir_print_instr(&instr
->instr
, stderr
);
2803 fprintf(stderr
, "\n");
2807 case nir_op_unpack_half_2x16_split_y
: {
2808 if (dst
.regClass() == v1
) {
2809 Builder
bld(ctx
->program
, ctx
->block
);
2810 /* TODO: use SDWA here */
2811 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2812 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2814 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2815 nir_print_instr(&instr
->instr
, stderr
);
2816 fprintf(stderr
, "\n");
2820 case nir_op_fquantize2f16
: {
2821 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2822 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2825 if (ctx
->program
->chip_class
>= GFX8
) {
2826 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2827 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2828 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2830 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2831 * so compare the result and flush to 0 if it's smaller.
2833 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2834 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2835 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2836 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2837 cmp_res
= vop3
->definitions
[0].getTemp();
2840 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2841 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2842 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2844 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2849 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2850 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2852 if (dst
.regClass() == s1
) {
2853 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2854 } else if (dst
.regClass() == v1
) {
2855 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2857 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2858 nir_print_instr(&instr
->instr
, stderr
);
2859 fprintf(stderr
, "\n");
2863 case nir_op_bitfield_select
: {
2864 /* (mask & insert) | (~mask & base) */
2865 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2866 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2867 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2869 /* dst = (insert & bitmask) | (base & ~bitmask) */
2870 if (dst
.regClass() == s1
) {
2871 aco_ptr
<Instruction
> sop2
;
2872 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2873 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2875 if (const_insert
&& const_bitmask
) {
2876 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2878 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2879 lhs
= Operand(insert
);
2883 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2884 if (const_base
&& const_bitmask
) {
2885 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2887 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2888 rhs
= Operand(base
);
2891 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2893 } else if (dst
.regClass() == v1
) {
2894 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2895 base
= as_vgpr(ctx
, base
);
2896 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2897 insert
= as_vgpr(ctx
, insert
);
2899 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2902 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2903 nir_print_instr(&instr
->instr
, stderr
);
2904 fprintf(stderr
, "\n");
2910 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2911 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2912 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2914 if (dst
.type() == RegType::sgpr
) {
2916 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2917 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2918 if (const_offset
&& const_bits
) {
2919 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2920 extract
= Operand(const_extract
);
2924 width
= Operand(const_bits
->u32
<< 16);
2926 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2928 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2932 if (dst
.regClass() == s1
) {
2933 if (instr
->op
== nir_op_ubfe
)
2934 opcode
= aco_opcode::s_bfe_u32
;
2936 opcode
= aco_opcode::s_bfe_i32
;
2937 } else if (dst
.regClass() == s2
) {
2938 if (instr
->op
== nir_op_ubfe
)
2939 opcode
= aco_opcode::s_bfe_u64
;
2941 opcode
= aco_opcode::s_bfe_i64
;
2943 unreachable("Unsupported BFE bit size");
2946 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2950 if (dst
.regClass() == v1
) {
2951 if (instr
->op
== nir_op_ubfe
)
2952 opcode
= aco_opcode::v_bfe_u32
;
2954 opcode
= aco_opcode::v_bfe_i32
;
2956 unreachable("Unsupported BFE bit size");
2959 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2963 case nir_op_bit_count
: {
2964 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2965 if (src
.regClass() == s1
) {
2966 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2967 } else if (src
.regClass() == v1
) {
2968 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2969 } else if (src
.regClass() == v2
) {
2970 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2971 emit_extract_vector(ctx
, src
, 1, v1
),
2972 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2973 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2974 } else if (src
.regClass() == s2
) {
2975 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2978 nir_print_instr(&instr
->instr
, stderr
);
2979 fprintf(stderr
, "\n");
2984 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2988 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2992 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2996 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3000 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3004 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3008 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3009 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3011 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3012 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3016 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3017 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3019 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3020 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3024 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3028 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3033 case nir_op_fddx_fine
:
3034 case nir_op_fddy_fine
:
3035 case nir_op_fddx_coarse
:
3036 case nir_op_fddy_coarse
: {
3037 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3038 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3039 if (instr
->op
== nir_op_fddx_fine
) {
3040 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3041 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3042 } else if (instr
->op
== nir_op_fddy_fine
) {
3043 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3044 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3046 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3047 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3048 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3050 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3054 if (ctx
->program
->chip_class
>= GFX8
) {
3055 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3056 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3058 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3059 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3060 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3062 emit_wqm(ctx
, tmp
, dst
, true);
3066 fprintf(stderr
, "Unknown NIR ALU instr: ");
3067 nir_print_instr(&instr
->instr
, stderr
);
3068 fprintf(stderr
, "\n");
3072 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3074 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3076 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3077 // which get truncated the lsb if double and msb if int
3078 // for now, we only use s_mov_b64 with 64bit inline constants
3079 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3080 assert(dst
.type() == RegType::sgpr
);
3082 Builder
bld(ctx
->program
, ctx
->block
);
3084 if (instr
->def
.bit_size
== 1) {
3085 assert(dst
.regClass() == bld
.lm
);
3086 int val
= instr
->value
[0].b
? -1 : 0;
3087 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3088 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3089 } else if (dst
.size() == 1) {
3090 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3092 assert(dst
.size() != 1);
3093 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3094 if (instr
->def
.bit_size
== 64)
3095 for (unsigned i
= 0; i
< dst
.size(); i
++)
3096 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3098 for (unsigned i
= 0; i
< dst
.size(); i
++)
3099 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3101 vec
->definitions
[0] = Definition(dst
);
3102 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3106 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3108 uint32_t new_mask
= 0;
3109 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3110 if (mask
& (1u << i
))
3111 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3115 Operand
load_lds_size_m0(isel_context
*ctx
)
3117 /* TODO: m0 does not need to be initialized on GFX9+ */
3118 Builder
bld(ctx
->program
, ctx
->block
);
3119 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3122 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3123 Temp address
, unsigned base_offset
, unsigned align
)
3125 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3127 Builder
bld(ctx
->program
, ctx
->block
);
3129 Operand m
= load_lds_size_m0(ctx
);
3131 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
3132 unsigned bytes_read
= 0;
3133 unsigned result_size
= 0;
3134 unsigned total_bytes
= num_components
* elem_size_bytes
;
3135 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
3136 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
3137 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
3139 while (bytes_read
< total_bytes
) {
3140 unsigned todo
= total_bytes
- bytes_read
;
3141 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
3142 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
3144 aco_opcode op
= aco_opcode::last_opcode
;
3146 if (todo
>= 16 && aligned16
&& large_ds_read
) {
3147 op
= aco_opcode::ds_read_b128
;
3149 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
3150 op
= aco_opcode::ds_read2_b64
;
3153 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
3154 op
= aco_opcode::ds_read_b96
;
3156 } else if (todo
>= 8 && aligned8
) {
3157 op
= aco_opcode::ds_read_b64
;
3159 } else if (todo
>= 8 && usable_read2
) {
3160 op
= aco_opcode::ds_read2_b32
;
3163 } else if (todo
>= 4) {
3164 op
= aco_opcode::ds_read_b32
;
3169 assert(todo
% elem_size_bytes
== 0);
3170 unsigned num_elements
= todo
/ elem_size_bytes
;
3171 unsigned offset
= base_offset
+ bytes_read
;
3172 unsigned max_offset
= read2
? 1019 : 65535;
3174 Temp address_offset
= address
;
3175 if (offset
> max_offset
) {
3176 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3177 offset
= bytes_read
;
3179 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3182 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3185 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3188 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3190 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3192 if (num_components
== 1) {
3193 assert(todo
== total_bytes
);
3194 if (dst
.type() == RegType::sgpr
)
3195 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3199 if (dst
.type() == RegType::sgpr
) {
3200 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3201 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3205 if (num_elements
== 1) {
3206 result
[result_size
++] = res
;
3208 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3209 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3210 split
->operands
[0] = Operand(res
);
3211 for (unsigned i
= 0; i
< num_elements
; i
++)
3212 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3213 ctx
->block
->instructions
.emplace_back(std::move(split
));
3219 assert(result_size
== num_components
&& result_size
> 1);
3220 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3221 for (unsigned i
= 0; i
< result_size
; i
++)
3222 vec
->operands
[i
] = Operand(result
[i
]);
3223 vec
->definitions
[0] = Definition(dst
);
3224 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3225 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3230 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3232 if (start
== 0 && size
== data
.size())
3233 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3235 unsigned size_hint
= 1;
3236 auto it
= ctx
->allocated_vec
.find(data
.id());
3237 if (it
!= ctx
->allocated_vec
.end())
3238 size_hint
= it
->second
[0].size();
3239 if (size
% size_hint
|| start
% size_hint
)
3246 for (unsigned i
= 0; i
< size
; i
++)
3247 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3250 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3252 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3253 for (unsigned i
= 0; i
< size
; i
++)
3254 vec
->operands
[i
] = Operand(elems
[i
]);
3255 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3256 vec
->definitions
[0] = Definition(res
);
3257 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3261 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3263 Builder
bld(ctx
->program
, ctx
->block
);
3264 unsigned bytes_written
= 0;
3265 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3266 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3268 while (bytes_written
< total_size
* 4) {
3269 unsigned todo
= total_size
* 4 - bytes_written
;
3270 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3271 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3273 aco_opcode op
= aco_opcode::last_opcode
;
3274 bool write2
= false;
3276 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3277 op
= aco_opcode::ds_write_b128
;
3279 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3280 op
= aco_opcode::ds_write2_b64
;
3283 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3284 op
= aco_opcode::ds_write_b96
;
3286 } else if (todo
>= 8 && aligned8
) {
3287 op
= aco_opcode::ds_write_b64
;
3289 } else if (todo
>= 8 && usable_write2
) {
3290 op
= aco_opcode::ds_write2_b32
;
3293 } else if (todo
>= 4) {
3294 op
= aco_opcode::ds_write_b32
;
3300 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3301 unsigned max_offset
= write2
? 1020 : 65535;
3302 Temp address_offset
= address
;
3303 if (offset
> max_offset
) {
3304 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3305 offset
= offset1
+ bytes_written
;
3307 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3310 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3311 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3312 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3314 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3315 bld
.ds(op
, address_offset
, val
, m
, offset
);
3318 bytes_written
+= size
* 4;
3322 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3323 Temp address
, unsigned base_offset
, unsigned align
)
3325 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3326 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3328 Operand m
= load_lds_size_m0(ctx
);
3330 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3331 assert(wrmask
<= 0x0f);
3332 int start
[2], count
[2];
3333 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3334 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3335 assert(wrmask
== 0);
3337 /* one combined store is sufficient */
3338 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3339 Builder
bld(ctx
->program
, ctx
->block
);
3341 Temp address_offset
= address
;
3342 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3343 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3347 assert(count
[0] == 1);
3348 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3350 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3351 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3352 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3353 base_offset
= base_offset
/ elem_size_bytes
;
3354 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3355 base_offset
+ start
[0], base_offset
+ start
[1]);
3359 for (unsigned i
= 0; i
< 2; i
++) {
3363 unsigned elem_size_words
= elem_size_bytes
/ 4;
3364 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3365 base_offset
, start
[i
] * elem_size_bytes
, align
);
3370 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3372 unsigned align
= 16;
3374 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3380 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3381 unsigned split_cnt
= 0u, Temp dst
= Temp())
3383 Builder
bld(ctx
->program
, ctx
->block
);
3384 unsigned dword_size
= elem_size_bytes
/ 4;
3387 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3389 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3390 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3391 instr
->definitions
[0] = Definition(dst
);
3393 for (unsigned i
= 0; i
< cnt
; ++i
) {
3395 assert(arr
[i
].size() == dword_size
);
3396 allocated_vec
[i
] = arr
[i
];
3397 instr
->operands
[i
] = Operand(arr
[i
]);
3399 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3400 allocated_vec
[i
] = zero
;
3401 instr
->operands
[i
] = Operand(zero
);
3405 bld
.insert(std::move(instr
));
3408 emit_split_vector(ctx
, dst
, split_cnt
);
3410 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3415 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3417 if (const_offset
>= 4096) {
3418 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3419 const_offset
%= 4096u;
3422 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3423 else if (unlikely(voffset
.regClass() == s1
))
3424 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3425 else if (likely(voffset
.regClass() == v1
))
3426 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3428 unreachable("Unsupported register class of voffset");
3431 return const_offset
;
3434 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3435 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3438 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3439 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3441 Builder
bld(ctx
->program
, ctx
->block
);
3442 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3443 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3445 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3446 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3447 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3448 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3449 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3451 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3454 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3455 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3456 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3458 Builder
bld(ctx
->program
, ctx
->block
);
3459 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3462 if (elem_size_bytes
== 8) {
3463 elem_size_bytes
= 4;
3464 write_mask
= widen_mask(write_mask
, 2);
3467 while (write_mask
) {
3470 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3475 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3476 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3478 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3479 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3482 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3483 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3493 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3494 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3496 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3497 assert(size_dwords
>= 1 && size_dwords
<= 4);
3499 Builder
bld(ctx
->program
, ctx
->block
);
3500 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3501 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3502 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3504 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3505 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3506 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3507 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3508 /* disable_wqm */ false, /* glc */ true,
3509 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3511 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3516 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3517 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3518 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3520 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3521 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3522 assert(!!stride
!= allow_combining
);
3524 Builder
bld(ctx
->program
, ctx
->block
);
3525 unsigned split_cnt
= num_components
;
3527 if (elem_size_bytes
== 8) {
3528 elem_size_bytes
= 4;
3529 num_components
*= 2;
3533 stride
= elem_size_bytes
;
3535 unsigned load_size
= 1;
3536 if (allow_combining
) {
3537 if ((num_components
% 4) == 0)
3539 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3541 else if ((num_components
% 2) == 0)
3545 unsigned num_loads
= num_components
/ load_size
;
3546 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3548 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3549 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3550 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3553 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3556 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3558 Builder
bld(ctx
->program
, ctx
->block
);
3559 Temp offset
= base_offset
.first
;
3560 unsigned const_offset
= base_offset
.second
;
3562 if (!nir_src_is_const(*off_src
)) {
3563 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3566 /* Calculate indirect offset with stride */
3567 if (likely(indirect_offset_arg
.regClass() == v1
))
3568 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3569 else if (indirect_offset_arg
.regClass() == s1
)
3570 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3572 unreachable("Unsupported register class of indirect offset");
3574 /* Add to the supplied base offset */
3575 if (offset
.id() == 0)
3576 offset
= with_stride
;
3577 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3578 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3579 else if (offset
.size() == 1 && with_stride
.size() == 1)
3580 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3582 unreachable("Unsupported register class of indirect offset");
3584 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3585 const_offset
+= const_offset_arg
* stride
;
3588 return std::make_pair(offset
, const_offset
);
3591 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3593 Builder
bld(ctx
->program
, ctx
->block
);
3596 if (off1
.first
.id() && off2
.first
.id()) {
3597 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3598 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3599 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3600 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3602 unreachable("Unsupported register class of indirect offset");
3604 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3607 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3610 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3612 Builder
bld(ctx
->program
, ctx
->block
);
3613 unsigned const_offset
= offs
.second
* multiplier
;
3615 if (!offs
.first
.id())
3616 return std::make_pair(offs
.first
, const_offset
);
3618 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3619 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3620 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3622 return std::make_pair(offset
, const_offset
);
3625 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3627 Builder
bld(ctx
->program
, ctx
->block
);
3629 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3630 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3631 /* component is in bytes */
3632 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3634 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3635 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3636 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3639 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3641 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3644 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3646 Builder
bld(ctx
->program
, ctx
->block
);
3648 switch (ctx
->shader
->info
.stage
) {
3649 case MESA_SHADER_TESS_CTRL
:
3650 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3651 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3652 case MESA_SHADER_TESS_EVAL
:
3653 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3655 unreachable("Unsupported stage in get_tess_rel_patch_id");
3659 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3661 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3662 Builder
bld(ctx
->program
, ctx
->block
);
3664 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3665 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3667 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3669 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3670 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3672 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3673 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3674 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3676 return offset_mul(ctx
, offs
, 4u);
3679 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3681 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3682 Builder
bld(ctx
->program
, ctx
->block
);
3684 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3685 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3686 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3687 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3688 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3689 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3691 std::pair
<Temp
, unsigned> offs
= instr
3692 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3693 : std::make_pair(Temp(), 0u);
3695 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3696 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3701 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3702 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3704 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3705 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3707 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3708 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3714 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3716 Builder
bld(ctx
->program
, ctx
->block
);
3718 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3719 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3721 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3723 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3724 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3725 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3727 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3728 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3733 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3735 Builder
bld(ctx
->program
, ctx
->block
);
3737 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3738 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3739 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3741 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3742 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3743 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3744 unsigned attr_stride
= ctx
->tcs_num_patches
;
3746 std::pair
<Temp
, unsigned> offs
= instr
3747 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3748 : std::make_pair(Temp(), 0u);
3750 if (const_base_offset
)
3751 offs
.second
+= const_base_offset
* attr_stride
;
3753 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3754 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3755 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3760 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3762 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3763 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3765 if (!nir_src_is_const(*off_src
)) {
3771 off
+= nir_src_as_uint(*off_src
) * 16u;
3774 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3775 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3782 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3784 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3785 unsigned component
= nir_intrinsic_component(instr
);
3786 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3788 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3789 if (off_instr
->type
!= nir_instr_type_load_const
)
3792 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3793 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3795 if (instr
->src
[0].ssa
->bit_size
== 64)
3796 write_mask
= widen_mask(write_mask
, 2);
3798 for (unsigned i
= 0; i
< 8; ++i
) {
3799 if (write_mask
& (1 << i
)) {
3800 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3801 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3809 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3811 /* Only TCS per-vertex inputs are supported by this function.
3812 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3814 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3817 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3818 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3819 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3820 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3821 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3822 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3827 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3828 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3829 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3830 assert(vec
.size() == dst
.size());
3832 Builder
bld(ctx
->program
, ctx
->block
);
3833 bld
.copy(Definition(dst
), vec
);
3837 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3839 Builder
bld(ctx
->program
, ctx
->block
);
3841 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3842 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3843 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3844 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3846 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3847 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3848 bool indirect_write
;
3849 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3850 if (temp_only_input
&& !indirect_write
)
3854 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3855 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3856 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3857 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3858 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3862 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3863 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3864 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3865 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3866 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3867 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3868 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3869 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3870 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3871 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3872 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3873 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3874 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3876 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3877 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3878 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3880 unreachable("Invalid LS or ES stage");
3883 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3884 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3885 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3889 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3891 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3892 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3893 off
!= ctx
->tcs_tess_lvl_in_loc
;
3896 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3898 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3899 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3902 uint64_t mask
= per_vertex
3903 ? ctx
->shader
->info
.outputs_read
3904 : ctx
->shader
->info
.patch_outputs_read
;
3905 bool indirect_write
;
3906 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3907 return indirect_write
|| output_read
;
3910 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3912 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3913 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3915 Builder
bld(ctx
->program
, ctx
->block
);
3917 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3918 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3919 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3921 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3922 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3923 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3924 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3926 if (write_to_vmem
) {
3927 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3928 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3929 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3931 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3932 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3933 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3937 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3938 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3939 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3943 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3945 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3946 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3948 Builder
bld(ctx
->program
, ctx
->block
);
3950 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3951 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3952 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3953 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3955 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3958 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3960 if (ctx
->stage
== vertex_vs
||
3961 ctx
->stage
== tess_eval_vs
||
3962 ctx
->stage
== fragment_fs
||
3963 ctx
->stage
== ngg_vertex_gs
||
3964 ctx
->stage
== ngg_tess_eval_gs
||
3965 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3966 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3967 if (!stored_to_temps
) {
3968 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3969 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3970 fprintf(stderr
, "\n");
3973 } else if (ctx
->stage
== vertex_es
||
3974 ctx
->stage
== vertex_ls
||
3975 ctx
->stage
== tess_eval_es
||
3976 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3977 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3978 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3979 visit_store_ls_or_es_output(ctx
, instr
);
3980 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3981 visit_store_tcs_output(ctx
, instr
, false);
3983 unreachable("Shader stage not implemented");
3987 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3989 visit_load_tcs_output(ctx
, instr
, false);
3992 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3994 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3995 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3997 Builder
bld(ctx
->program
, ctx
->block
);
3998 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3999 if (ctx
->program
->has_16bank_lds
)
4000 interp_p1
.instr
->operands
[0].setLateKill(true);
4001 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4004 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4006 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4007 for (unsigned i
= 0; i
< num_components
; i
++)
4008 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4009 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4010 assert(num_components
== 4);
4011 Builder
bld(ctx
->program
, ctx
->block
);
4012 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4015 for (Operand
& op
: vec
->operands
)
4016 op
= op
.isUndefined() ? Operand(0u) : op
;
4018 vec
->definitions
[0] = Definition(dst
);
4019 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4020 emit_split_vector(ctx
, dst
, num_components
);
4024 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4026 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4027 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4028 unsigned idx
= nir_intrinsic_base(instr
);
4029 unsigned component
= nir_intrinsic_component(instr
);
4030 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4032 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4034 assert(offset
->u32
== 0);
4036 /* the lower 15bit of the prim_mask contain the offset into LDS
4037 * while the upper bits contain the number of prims */
4038 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4039 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4040 Builder
bld(ctx
->program
, ctx
->block
);
4041 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4042 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4043 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4044 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4045 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4048 if (instr
->dest
.ssa
.num_components
== 1) {
4049 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4051 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4052 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4054 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4055 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4056 vec
->operands
[i
] = Operand(tmp
);
4058 vec
->definitions
[0] = Definition(dst
);
4059 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4063 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4064 unsigned offset
, unsigned stride
, unsigned channels
)
4066 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4067 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4069 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4070 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4073 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4074 unsigned offset
, unsigned stride
, unsigned *channels
)
4076 if (!vtx_info
->chan_byte_size
) {
4077 *channels
= vtx_info
->num_channels
;
4078 return vtx_info
->chan_format
;
4081 unsigned num_channels
= *channels
;
4082 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4083 unsigned new_channels
= num_channels
+ 1;
4084 /* first, assume more loads is worse and try using a larger data format */
4085 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4087 /* don't make the attribute potentially out-of-bounds */
4088 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4092 if (new_channels
== 5) {
4093 /* then try decreasing load size (at the cost of more loads) */
4094 new_channels
= *channels
;
4095 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4099 if (new_channels
< *channels
)
4100 *channels
= new_channels
;
4101 num_channels
= new_channels
;
4104 switch (vtx_info
->chan_format
) {
4105 case V_008F0C_BUF_DATA_FORMAT_8
:
4106 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4107 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4108 case V_008F0C_BUF_DATA_FORMAT_16
:
4109 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4110 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4111 case V_008F0C_BUF_DATA_FORMAT_32
:
4112 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4113 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4115 unreachable("shouldn't reach here");
4116 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4119 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4120 * so we may need to fix it up. */
4121 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4123 Builder
bld(ctx
->program
, ctx
->block
);
4125 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4126 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4128 /* For the integer-like cases, do a natural sign extension.
4130 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4131 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4134 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4135 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4137 /* Convert back to the right type. */
4138 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4139 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4140 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4141 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4142 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4143 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4149 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4151 Builder
bld(ctx
->program
, ctx
->block
);
4152 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4153 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4155 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4156 if (off_instr
->type
!= nir_instr_type_load_const
) {
4157 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4158 nir_print_instr(off_instr
, stderr
);
4159 fprintf(stderr
, "\n");
4161 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4163 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4165 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4166 unsigned component
= nir_intrinsic_component(instr
);
4167 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4168 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4169 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4170 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4172 unsigned dfmt
= attrib_format
& 0xf;
4173 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4174 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4176 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4177 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4178 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4179 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4181 num_channels
= MAX2(num_channels
, 3);
4183 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4184 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4187 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4188 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4189 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4191 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4193 Temp divided
= bld
.tmp(v1
);
4194 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4195 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4197 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4200 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4203 index
= bld
.vadd32(bld
.def(v1
),
4204 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4205 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4208 Temp channels
[num_channels
];
4209 unsigned channel_start
= 0;
4210 bool direct_fetch
= false;
4212 /* skip unused channels at the start */
4213 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4214 channel_start
= ffs(mask
) - 1;
4215 for (unsigned i
= 0; i
< channel_start
; i
++)
4216 channels
[i
] = Temp(0, s1
);
4217 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4218 num_channels
= 3 - (ffs(mask
) - 1);
4222 while (channel_start
< num_channels
) {
4223 unsigned fetch_size
= num_channels
- channel_start
;
4224 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4225 bool expanded
= false;
4227 /* use MUBUF when possible to avoid possible alignment issues */
4228 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4229 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4230 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4231 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4232 vtx_info
->chan_byte_size
== 4;
4233 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4235 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4237 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4238 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4244 Temp fetch_index
= index
;
4245 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4246 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4247 fetch_offset
= fetch_offset
% attrib_stride
;
4250 Operand
soffset(0u);
4251 if (fetch_offset
>= 4096) {
4252 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4253 fetch_offset
%= 4096;
4257 switch (fetch_size
) {
4259 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4262 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4265 assert(ctx
->options
->chip_class
>= GFX7
||
4266 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4267 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4270 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4273 unreachable("Unimplemented load_input vector size");
4277 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4278 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4279 num_channels
<= 3)) {
4280 direct_fetch
= true;
4283 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4287 Instruction
*mubuf
= bld
.mubuf(opcode
,
4288 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4289 fetch_offset
, false, true).instr
;
4290 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4292 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4293 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4294 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4295 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4298 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4300 if (fetch_size
== 1) {
4301 channels
[channel_start
] = fetch_dst
;
4303 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4304 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4307 channel_start
+= fetch_size
;
4310 if (!direct_fetch
) {
4311 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4312 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4314 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4315 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4316 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4318 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4319 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4320 unsigned num_temp
= 0;
4321 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4322 unsigned idx
= i
+ component
;
4323 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4324 Temp channel
= channels
[swizzle
[idx
]];
4325 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4326 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4327 vec
->operands
[i
] = Operand(channel
);
4331 } else if (is_float
&& idx
== 3) {
4332 vec
->operands
[i
] = Operand(0x3f800000u
);
4333 } else if (!is_float
&& idx
== 3) {
4334 vec
->operands
[i
] = Operand(1u);
4336 vec
->operands
[i
] = Operand(0u);
4339 vec
->definitions
[0] = Definition(dst
);
4340 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4341 emit_split_vector(ctx
, dst
, dst
.size());
4343 if (num_temp
== dst
.size())
4344 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4346 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4347 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4348 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4349 if (off_instr
->type
!= nir_instr_type_load_const
||
4350 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4351 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4352 nir_print_instr(off_instr
, stderr
);
4353 fprintf(stderr
, "\n");
4356 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4357 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4359 assert(offset
->u32
== 0);
4361 /* the lower 15bit of the prim_mask contain the offset into LDS
4362 * while the upper bits contain the number of prims */
4363 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4364 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4365 Builder
bld(ctx
->program
, ctx
->block
);
4366 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4367 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4368 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4369 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4370 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4373 unsigned idx
= nir_intrinsic_base(instr
);
4374 unsigned component
= nir_intrinsic_component(instr
);
4375 unsigned vertex_id
= 2; /* P0 */
4377 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4378 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4379 switch (src0
->u32
) {
4381 vertex_id
= 2; /* P0 */
4384 vertex_id
= 0; /* P10 */
4387 vertex_id
= 1; /* P20 */
4390 unreachable("invalid vertex index");
4394 if (dst
.size() == 1) {
4395 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4397 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4398 for (unsigned i
= 0; i
< dst
.size(); i
++)
4399 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4400 vec
->definitions
[0] = Definition(dst
);
4401 bld
.insert(std::move(vec
));
4404 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4405 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4406 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4407 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4408 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4410 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4412 unreachable("Shader stage not implemented");
4416 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4418 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4420 Builder
bld(ctx
->program
, ctx
->block
);
4421 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4424 if (!nir_src_is_const(*vertex_src
)) {
4425 /* better code could be created, but this case probably doesn't happen
4426 * much in practice */
4427 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4428 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4431 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4432 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4434 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4436 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4439 if (vertex_offset
.id()) {
4440 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4441 Operand(i
), indirect_vertex
);
4442 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4444 vertex_offset
= elem
;
4448 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4449 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4451 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4452 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4453 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4454 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4455 Operand((vertex
% 2u) * 16u), Operand(16u));
4457 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4460 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4461 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4462 return offset_mul(ctx
, offs
, 4u);
4465 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4467 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4469 Builder
bld(ctx
->program
, ctx
->block
);
4470 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4471 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4473 if (ctx
->stage
== geometry_gs
) {
4474 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4475 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4476 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4477 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4478 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4479 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4480 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4482 unreachable("Unsupported GS stage.");
4486 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4488 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4490 Builder
bld(ctx
->program
, ctx
->block
);
4491 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4493 if (load_input_from_temps(ctx
, instr
, dst
))
4496 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4497 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4498 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4500 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4503 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4505 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4507 Builder
bld(ctx
->program
, ctx
->block
);
4509 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4510 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4511 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4513 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4514 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4516 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4519 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4521 switch (ctx
->shader
->info
.stage
) {
4522 case MESA_SHADER_GEOMETRY
:
4523 visit_load_gs_per_vertex_input(ctx
, instr
);
4525 case MESA_SHADER_TESS_CTRL
:
4526 visit_load_tcs_per_vertex_input(ctx
, instr
);
4528 case MESA_SHADER_TESS_EVAL
:
4529 visit_load_tes_per_vertex_input(ctx
, instr
);
4532 unreachable("Unimplemented shader stage");
4536 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4538 visit_load_tcs_output(ctx
, instr
, true);
4541 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4543 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4544 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4546 visit_store_tcs_output(ctx
, instr
, true);
4549 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4551 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4553 Builder
bld(ctx
->program
, ctx
->block
);
4554 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4556 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4557 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4560 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4561 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4562 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4563 tes_w
= Operand(tmp
);
4566 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4567 emit_split_vector(ctx
, tess_coord
, 3);
4570 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4572 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4573 Builder
bld(ctx
->program
, ctx
->block
);
4574 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4575 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4576 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4579 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4583 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4585 Builder
bld(ctx
->program
, ctx
->block
);
4586 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4587 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4588 index
= bld
.as_uniform(index
);
4589 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4590 unsigned binding
= nir_intrinsic_binding(instr
);
4593 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4594 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4595 unsigned offset
= layout
->binding
[binding
].offset
;
4597 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4598 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4599 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4600 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4601 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4604 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4605 stride
= layout
->binding
[binding
].size
;
4608 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4609 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4611 if (nir_const_index
) {
4612 const_index
= const_index
* stride
;
4613 } else if (index
.type() == RegType::vgpr
) {
4614 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4615 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4617 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4621 if (nir_const_index
) {
4622 const_index
= const_index
+ offset
;
4623 } else if (index
.type() == RegType::vgpr
) {
4624 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4626 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4630 if (nir_const_index
&& const_index
== 0) {
4632 } else if (index
.type() == RegType::vgpr
) {
4633 index
= bld
.vadd32(bld
.def(v1
),
4634 nir_const_index
? Operand(const_index
) : Operand(index
),
4637 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4638 nir_const_index
? Operand(const_index
) : Operand(index
),
4642 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4645 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4646 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4647 bool glc
=false, bool readonly
=true)
4649 Builder
bld(ctx
->program
, ctx
->block
);
4650 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4651 unsigned num_bytes
= num_components
* component_size
;
4654 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4655 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4656 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4657 unsigned const_offset
= 0;
4659 /* for small bit sizes add buffer for unaligned loads */
4662 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4667 Temp lower
= Temp();
4668 if (num_bytes
> 16) {
4669 assert(num_components
== 3 || num_components
== 4);
4670 op
= aco_opcode::buffer_load_dwordx4
;
4671 lower
= bld
.tmp(v4
);
4672 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4673 mubuf
->definitions
[0] = Definition(lower
);
4674 mubuf
->operands
[0] = Operand(rsrc
);
4675 mubuf
->operands
[1] = vaddr
;
4676 mubuf
->operands
[2] = soffset
;
4677 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4680 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4681 mubuf
->can_reorder
= readonly
;
4682 bld
.insert(std::move(mubuf
));
4683 emit_split_vector(ctx
, lower
, 2);
4686 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4687 /* GFX6 doesn't support loading vec3, expand to vec4. */
4691 switch (num_bytes
) {
4693 op
= aco_opcode::buffer_load_ubyte
;
4696 op
= aco_opcode::buffer_load_ushort
;
4700 op
= aco_opcode::buffer_load_dword
;
4706 op
= aco_opcode::buffer_load_dwordx2
;
4710 assert(ctx
->options
->chip_class
> GFX6
);
4711 op
= aco_opcode::buffer_load_dwordx3
;
4714 op
= aco_opcode::buffer_load_dwordx4
;
4717 unreachable("Load SSBO not implemented for this size.");
4719 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4720 mubuf
->operands
[0] = Operand(rsrc
);
4721 mubuf
->operands
[1] = vaddr
;
4722 mubuf
->operands
[2] = soffset
;
4723 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4726 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4727 mubuf
->can_reorder
= readonly
;
4728 mubuf
->offset
= const_offset
;
4729 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4731 if (component_size
< 4) {
4732 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4733 instr
->definitions
[0] = Definition(vec
);
4734 bld
.insert(std::move(instr
));
4736 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4737 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4738 Temp tmp
[3] = {vec
, vec
, vec
};
4740 if (vec
.size() == 3) {
4741 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4742 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4743 } else if (vec
.size() == 2) {
4744 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4745 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4747 for (unsigned i
= 0; i
< dst
.size(); i
++)
4748 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4751 if (dst
.size() == 2)
4752 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4757 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4758 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4760 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4765 } else if (dst
.size() > 4) {
4766 assert(lower
!= Temp());
4767 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4768 instr
->definitions
[0] = Definition(upper
);
4769 bld
.insert(std::move(instr
));
4770 if (dst
.size() == 8)
4771 emit_split_vector(ctx
, upper
, 2);
4772 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4773 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4774 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4775 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4776 if (dst
.size() == 8)
4777 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4778 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4779 Temp vec
= bld
.tmp(v4
);
4780 instr
->definitions
[0] = Definition(vec
);
4781 bld
.insert(std::move(instr
));
4782 emit_split_vector(ctx
, vec
, 4);
4784 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4785 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4786 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4787 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4790 if (dst
.type() == RegType::sgpr
) {
4791 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4792 instr
->definitions
[0] = Definition(vec
);
4793 bld
.insert(std::move(instr
));
4794 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4796 instr
->definitions
[0] = Definition(dst
);
4797 bld
.insert(std::move(instr
));
4798 emit_split_vector(ctx
, dst
, num_components
);
4801 /* for small bit sizes add buffer for unaligned loads */
4803 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4805 switch (num_bytes
) {
4810 op
= aco_opcode::s_buffer_load_dword
;
4816 op
= aco_opcode::s_buffer_load_dwordx2
;
4821 op
= aco_opcode::s_buffer_load_dwordx4
;
4825 op
= aco_opcode::s_buffer_load_dwordx8
;
4828 unreachable("Load SSBO not implemented for this size.");
4830 offset
= bld
.as_uniform(offset
);
4831 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4832 load
->operands
[0] = Operand(rsrc
);
4833 load
->operands
[1] = Operand(offset
);
4834 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4835 load
->definitions
[0] = Definition(dst
);
4838 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4839 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4840 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4842 /* adjust misaligned small bit size loads */
4844 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4845 load
->definitions
[0] = Definition(vec
);
4846 bld
.insert(std::move(load
));
4847 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4848 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4851 } else if (dst
.size() == 3) {
4852 Temp vec
= bld
.tmp(s4
);
4853 load
->definitions
[0] = Definition(vec
);
4854 bld
.insert(std::move(load
));
4855 emit_split_vector(ctx
, vec
, 4);
4857 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4858 emit_extract_vector(ctx
, vec
, 0, s1
),
4859 emit_extract_vector(ctx
, vec
, 1, s1
),
4860 emit_extract_vector(ctx
, vec
, 2, s1
));
4861 } else if (dst
.size() == 6) {
4862 Temp vec
= bld
.tmp(s8
);
4863 load
->definitions
[0] = Definition(vec
);
4864 bld
.insert(std::move(load
));
4865 emit_split_vector(ctx
, vec
, 4);
4867 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4868 emit_extract_vector(ctx
, vec
, 0, s2
),
4869 emit_extract_vector(ctx
, vec
, 1, s2
),
4870 emit_extract_vector(ctx
, vec
, 2, s2
));
4872 bld
.insert(std::move(load
));
4874 emit_split_vector(ctx
, dst
, num_components
);
4878 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4880 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4881 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4883 Builder
bld(ctx
->program
, ctx
->block
);
4885 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4886 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4887 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4888 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4890 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4891 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4892 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4893 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4894 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4895 if (ctx
->options
->chip_class
>= GFX10
) {
4896 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4897 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4898 S_008F0C_RESOURCE_LEVEL(1);
4900 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4901 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4903 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4904 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4905 Operand(0xFFFFFFFFu
),
4906 Operand(desc_type
));
4907 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4908 rsrc
, upper_dwords
);
4910 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4911 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4913 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4916 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4917 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4918 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4920 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4923 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4925 Builder
bld(ctx
->program
, ctx
->block
);
4926 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4927 unsigned offset
= nir_intrinsic_base(instr
);
4928 unsigned count
= instr
->dest
.ssa
.num_components
;
4929 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4931 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4932 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4933 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4934 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4935 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4936 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4937 for (unsigned i
= 0; i
< count
; ++i
) {
4938 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4939 vec
->operands
[i
] = Operand
{elems
[i
]};
4941 vec
->definitions
[0] = Definition(dst
);
4942 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4943 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4948 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4949 if (offset
!= 0) // TODO check if index != 0 as well
4950 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4951 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4954 bool aligned
= true;
4956 if (instr
->dest
.ssa
.bit_size
== 8) {
4957 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4958 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4960 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4961 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4962 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4964 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4969 switch (vec
.size()) {
4971 op
= aco_opcode::s_load_dword
;
4974 op
= aco_opcode::s_load_dwordx2
;
4980 op
= aco_opcode::s_load_dwordx4
;
4986 op
= aco_opcode::s_load_dwordx8
;
4989 unreachable("unimplemented or forbidden load_push_constant.");
4992 bld
.smem(op
, Definition(vec
), ptr
, index
);
4995 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4996 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5001 emit_split_vector(ctx
, vec
, 4);
5002 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5003 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5004 emit_extract_vector(ctx
, vec
, 0, rc
),
5005 emit_extract_vector(ctx
, vec
, 1, rc
),
5006 emit_extract_vector(ctx
, vec
, 2, rc
));
5009 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5012 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5016 Builder
bld(ctx
->program
, ctx
->block
);
5018 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5019 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5020 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5021 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5022 if (ctx
->options
->chip_class
>= GFX10
) {
5023 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5024 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5025 S_008F0C_RESOURCE_LEVEL(1);
5027 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5028 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5031 unsigned base
= nir_intrinsic_base(instr
);
5032 unsigned range
= nir_intrinsic_range(instr
);
5034 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5035 if (base
&& offset
.type() == RegType::sgpr
)
5036 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5037 else if (base
&& offset
.type() == RegType::vgpr
)
5038 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5040 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5041 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5042 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5043 Operand(desc_type
));
5044 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5045 // TODO: get alignment information for subdword constants
5046 unsigned byte_align
= size
< 4 ? -1 : 0;
5047 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
5050 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5052 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5053 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5055 ctx
->program
->needs_exact
= true;
5057 // TODO: optimize uniform conditions
5058 Builder
bld(ctx
->program
, ctx
->block
);
5059 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5060 assert(src
.regClass() == bld
.lm
);
5061 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5062 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5063 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5067 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5069 Builder
bld(ctx
->program
, ctx
->block
);
5071 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5072 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5074 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5075 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5077 if (ctx
->block
->loop_nest_depth
&&
5078 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5079 /* we handle discards the same way as jump instructions */
5080 append_logical_end(ctx
->block
);
5082 /* in loops, discard behaves like break */
5083 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5084 ctx
->block
->kind
|= block_kind_discard
;
5087 /* uniform discard - loop ends here */
5088 assert(nir_instr_is_last(&instr
->instr
));
5089 ctx
->block
->kind
|= block_kind_uniform
;
5090 ctx
->cf_info
.has_branch
= true;
5091 bld
.branch(aco_opcode::p_branch
);
5092 add_linear_edge(ctx
->block
->index
, linear_target
);
5096 /* we add a break right behind the discard() instructions */
5097 ctx
->block
->kind
|= block_kind_break
;
5098 unsigned idx
= ctx
->block
->index
;
5100 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5101 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5103 /* remove critical edges from linear CFG */
5104 bld
.branch(aco_opcode::p_branch
);
5105 Block
* break_block
= ctx
->program
->create_and_insert_block();
5106 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5107 break_block
->kind
|= block_kind_uniform
;
5108 add_linear_edge(idx
, break_block
);
5109 add_linear_edge(break_block
->index
, linear_target
);
5110 bld
.reset(break_block
);
5111 bld
.branch(aco_opcode::p_branch
);
5113 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5114 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5115 add_linear_edge(idx
, continue_block
);
5116 append_logical_start(continue_block
);
5117 ctx
->block
= continue_block
;
5122 /* it can currently happen that NIR doesn't remove the unreachable code */
5123 if (!nir_instr_is_last(&instr
->instr
)) {
5124 ctx
->program
->needs_exact
= true;
5125 /* save exec somewhere temporarily so that it doesn't get
5126 * overwritten before the discard from outer exec masks */
5127 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5128 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5129 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5133 /* This condition is incorrect for uniformly branched discards in a loop
5134 * predicated by a divergent condition, but the above code catches that case
5135 * and the discard would end up turning into a discard_if.
5145 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5146 /* program just ends here */
5147 ctx
->block
->kind
|= block_kind_uniform
;
5148 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5149 0 /* enabled mask */, 9 /* dest */,
5150 false /* compressed */, true/* done */, true /* valid mask */);
5151 bld
.sopp(aco_opcode::s_endpgm
);
5152 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5154 ctx
->block
->kind
|= block_kind_discard
;
5155 /* branch and linear edge is added by visit_if() */
5159 enum aco_descriptor_type
{
5170 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5171 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5173 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5174 return dim
== ac_image_cube
||
5175 dim
== ac_image_1darray
||
5176 dim
== ac_image_2darray
||
5177 dim
== ac_image_2darraymsaa
;
5180 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5181 enum aco_descriptor_type desc_type
,
5182 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5184 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5185 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5186 if (it != ctx->tex_desc.end())
5189 Temp index
= Temp();
5190 bool index_set
= false;
5191 unsigned constant_index
= 0;
5192 unsigned descriptor_set
;
5193 unsigned base_index
;
5194 Builder
bld(ctx
->program
, ctx
->block
);
5197 assert(tex_instr
&& !image
);
5199 base_index
= tex_instr
->sampler_index
;
5201 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5202 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5206 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5207 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5209 constant_index
+= array_size
* const_value
->u32
;
5211 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5212 if (indirect
.type() == RegType::vgpr
)
5213 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5215 if (array_size
!= 1)
5216 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5222 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5226 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5228 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5229 base_index
= deref_instr
->var
->data
.binding
;
5232 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5233 list
= convert_pointer_to_64_bit(ctx
, list
);
5235 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5236 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5237 unsigned offset
= binding
->offset
;
5238 unsigned stride
= binding
->size
;
5242 assert(base_index
< layout
->binding_count
);
5244 switch (desc_type
) {
5245 case ACO_DESC_IMAGE
:
5247 opcode
= aco_opcode::s_load_dwordx8
;
5249 case ACO_DESC_FMASK
:
5251 opcode
= aco_opcode::s_load_dwordx8
;
5254 case ACO_DESC_SAMPLER
:
5256 opcode
= aco_opcode::s_load_dwordx4
;
5257 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5258 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5260 case ACO_DESC_BUFFER
:
5262 opcode
= aco_opcode::s_load_dwordx4
;
5264 case ACO_DESC_PLANE_0
:
5265 case ACO_DESC_PLANE_1
:
5267 opcode
= aco_opcode::s_load_dwordx8
;
5268 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5270 case ACO_DESC_PLANE_2
:
5272 opcode
= aco_opcode::s_load_dwordx4
;
5276 unreachable("invalid desc_type\n");
5279 offset
+= constant_index
* stride
;
5281 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5282 (!index_set
|| binding
->immutable_samplers_equal
)) {
5283 if (binding
->immutable_samplers_equal
)
5286 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5287 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5288 Operand(samplers
[constant_index
* 4 + 0]),
5289 Operand(samplers
[constant_index
* 4 + 1]),
5290 Operand(samplers
[constant_index
* 4 + 2]),
5291 Operand(samplers
[constant_index
* 4 + 3]));
5296 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5298 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5299 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5302 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5304 if (desc_type
== ACO_DESC_PLANE_2
) {
5306 for (unsigned i
= 0; i
< 8; i
++)
5307 components
[i
] = bld
.tmp(s1
);
5308 bld
.pseudo(aco_opcode::p_split_vector
,
5309 Definition(components
[0]),
5310 Definition(components
[1]),
5311 Definition(components
[2]),
5312 Definition(components
[3]),
5315 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5316 bld
.pseudo(aco_opcode::p_split_vector
,
5317 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5318 Definition(components
[4]),
5319 Definition(components
[5]),
5320 Definition(components
[6]),
5321 Definition(components
[7]),
5324 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5325 components
[0], components
[1], components
[2], components
[3],
5326 components
[4], components
[5], components
[6], components
[7]);
5332 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5335 case GLSL_SAMPLER_DIM_BUF
:
5337 case GLSL_SAMPLER_DIM_1D
:
5338 return array
? 2 : 1;
5339 case GLSL_SAMPLER_DIM_2D
:
5340 return array
? 3 : 2;
5341 case GLSL_SAMPLER_DIM_MS
:
5342 return array
? 4 : 3;
5343 case GLSL_SAMPLER_DIM_3D
:
5344 case GLSL_SAMPLER_DIM_CUBE
:
5346 case GLSL_SAMPLER_DIM_RECT
:
5347 case GLSL_SAMPLER_DIM_SUBPASS
:
5349 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5358 /* Adjust the sample index according to FMASK.
5360 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5361 * which is the identity mapping. Each nibble says which physical sample
5362 * should be fetched to get that sample.
5364 * For example, 0x11111100 means there are only 2 samples stored and
5365 * the second sample covers 3/4 of the pixel. When reading samples 0
5366 * and 1, return physical sample 0 (determined by the first two 0s
5367 * in FMASK), otherwise return physical sample 1.
5369 * The sample index should be adjusted as follows:
5370 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5372 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5374 Builder
bld(ctx
->program
, ctx
->block
);
5375 Temp fmask
= bld
.tmp(v1
);
5376 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5377 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5380 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5381 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5382 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5383 load
->operands
[0] = Operand(fmask_desc_ptr
);
5384 load
->operands
[1] = Operand(s4
); /* no sampler */
5385 load
->operands
[2] = Operand(coord
);
5386 load
->definitions
[0] = Definition(fmask
);
5393 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5394 ctx
->block
->instructions
.emplace_back(std::move(load
));
5396 Operand sample_index4
;
5397 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5398 sample_index4
= Operand(sample_index
.constantValue() << 2);
5399 } else if (sample_index
.regClass() == s1
) {
5400 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5402 assert(sample_index
.regClass() == v1
);
5403 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5407 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5408 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5409 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5410 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5412 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5414 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5415 * resource descriptor is 0 (invalid),
5417 Temp compare
= bld
.tmp(bld
.lm
);
5418 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5419 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5421 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5423 /* Replace the MSAA sample index. */
5424 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5427 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5430 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5431 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5432 bool is_array
= glsl_sampler_type_is_array(type
);
5433 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5434 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5435 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5436 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5437 int count
= image_type_to_components_count(dim
, is_array
);
5438 std::vector
<Temp
> coords(count
);
5439 Builder
bld(ctx
->program
, ctx
->block
);
5443 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5444 /* get sample index */
5445 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5446 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5447 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5448 std::vector
<Temp
> fmask_load_address
;
5449 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5450 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5452 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5453 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5455 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5460 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5461 coords
.resize(coords
.size() + 1);
5462 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5464 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5466 for (int i
= 0; i
< count
; i
++)
5467 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5470 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5471 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5472 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5473 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5476 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5479 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5480 for (unsigned i
= 0; i
< coords
.size(); i
++)
5481 vec
->operands
[i
] = Operand(coords
[i
]);
5482 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5483 vec
->definitions
[0] = Definition(res
);
5484 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5489 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5491 Builder
bld(ctx
->program
, ctx
->block
);
5492 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5493 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5494 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5495 bool is_array
= glsl_sampler_type_is_array(type
);
5496 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5498 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5499 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5500 unsigned num_channels
= util_last_bit(mask
);
5501 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5502 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5505 switch (num_channels
) {
5507 opcode
= aco_opcode::buffer_load_format_x
;
5510 opcode
= aco_opcode::buffer_load_format_xy
;
5513 opcode
= aco_opcode::buffer_load_format_xyz
;
5516 opcode
= aco_opcode::buffer_load_format_xyzw
;
5519 unreachable(">4 channel buffer image load");
5521 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5522 load
->operands
[0] = Operand(rsrc
);
5523 load
->operands
[1] = Operand(vindex
);
5524 load
->operands
[2] = Operand((uint32_t) 0);
5526 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5529 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5530 load
->definitions
[0] = Definition(tmp
);
5532 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5533 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5534 load
->barrier
= barrier_image
;
5535 ctx
->block
->instructions
.emplace_back(std::move(load
));
5537 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5541 Temp coords
= get_image_coords(ctx
, instr
, type
);
5542 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5544 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5545 unsigned num_components
= util_bitcount(dmask
);
5547 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5550 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5552 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5553 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5555 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5556 load
->operands
[0] = Operand(resource
);
5557 load
->operands
[1] = Operand(s4
); /* no sampler */
5558 load
->operands
[2] = Operand(coords
);
5559 load
->definitions
[0] = Definition(tmp
);
5560 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5561 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5562 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5563 load
->dmask
= dmask
;
5565 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5566 load
->barrier
= barrier_image
;
5567 ctx
->block
->instructions
.emplace_back(std::move(load
));
5569 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5573 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5575 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5576 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5577 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5578 bool is_array
= glsl_sampler_type_is_array(type
);
5579 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5581 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5583 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5584 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5585 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5587 switch (data
.size()) {
5589 opcode
= aco_opcode::buffer_store_format_x
;
5592 opcode
= aco_opcode::buffer_store_format_xy
;
5595 opcode
= aco_opcode::buffer_store_format_xyz
;
5598 opcode
= aco_opcode::buffer_store_format_xyzw
;
5601 unreachable(">4 channel buffer image store");
5603 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5604 store
->operands
[0] = Operand(rsrc
);
5605 store
->operands
[1] = Operand(vindex
);
5606 store
->operands
[2] = Operand((uint32_t) 0);
5607 store
->operands
[3] = Operand(data
);
5608 store
->idxen
= true;
5611 store
->disable_wqm
= true;
5612 store
->barrier
= barrier_image
;
5613 ctx
->program
->needs_exact
= true;
5614 ctx
->block
->instructions
.emplace_back(std::move(store
));
5618 assert(data
.type() == RegType::vgpr
);
5619 Temp coords
= get_image_coords(ctx
, instr
, type
);
5620 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5622 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5623 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5625 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5626 store
->operands
[0] = Operand(resource
);
5627 store
->operands
[1] = Operand(data
);
5628 store
->operands
[2] = Operand(coords
);
5631 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5632 store
->dmask
= (1 << data
.size()) - 1;
5634 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5635 store
->disable_wqm
= true;
5636 store
->barrier
= barrier_image
;
5637 ctx
->program
->needs_exact
= true;
5638 ctx
->block
->instructions
.emplace_back(std::move(store
));
5642 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5644 /* return the previous value if dest is ever used */
5645 bool return_previous
= false;
5646 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5647 return_previous
= true;
5650 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5651 return_previous
= true;
5655 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5656 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5657 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5658 bool is_array
= glsl_sampler_type_is_array(type
);
5659 Builder
bld(ctx
->program
, ctx
->block
);
5661 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5662 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5664 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5665 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5667 aco_opcode buf_op
, image_op
;
5668 switch (instr
->intrinsic
) {
5669 case nir_intrinsic_image_deref_atomic_add
:
5670 buf_op
= aco_opcode::buffer_atomic_add
;
5671 image_op
= aco_opcode::image_atomic_add
;
5673 case nir_intrinsic_image_deref_atomic_umin
:
5674 buf_op
= aco_opcode::buffer_atomic_umin
;
5675 image_op
= aco_opcode::image_atomic_umin
;
5677 case nir_intrinsic_image_deref_atomic_imin
:
5678 buf_op
= aco_opcode::buffer_atomic_smin
;
5679 image_op
= aco_opcode::image_atomic_smin
;
5681 case nir_intrinsic_image_deref_atomic_umax
:
5682 buf_op
= aco_opcode::buffer_atomic_umax
;
5683 image_op
= aco_opcode::image_atomic_umax
;
5685 case nir_intrinsic_image_deref_atomic_imax
:
5686 buf_op
= aco_opcode::buffer_atomic_smax
;
5687 image_op
= aco_opcode::image_atomic_smax
;
5689 case nir_intrinsic_image_deref_atomic_and
:
5690 buf_op
= aco_opcode::buffer_atomic_and
;
5691 image_op
= aco_opcode::image_atomic_and
;
5693 case nir_intrinsic_image_deref_atomic_or
:
5694 buf_op
= aco_opcode::buffer_atomic_or
;
5695 image_op
= aco_opcode::image_atomic_or
;
5697 case nir_intrinsic_image_deref_atomic_xor
:
5698 buf_op
= aco_opcode::buffer_atomic_xor
;
5699 image_op
= aco_opcode::image_atomic_xor
;
5701 case nir_intrinsic_image_deref_atomic_exchange
:
5702 buf_op
= aco_opcode::buffer_atomic_swap
;
5703 image_op
= aco_opcode::image_atomic_swap
;
5705 case nir_intrinsic_image_deref_atomic_comp_swap
:
5706 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5707 image_op
= aco_opcode::image_atomic_cmpswap
;
5710 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5713 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5715 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5716 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5717 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5718 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5719 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5720 mubuf
->operands
[0] = Operand(resource
);
5721 mubuf
->operands
[1] = Operand(vindex
);
5722 mubuf
->operands
[2] = Operand((uint32_t)0);
5723 mubuf
->operands
[3] = Operand(data
);
5724 if (return_previous
)
5725 mubuf
->definitions
[0] = Definition(dst
);
5727 mubuf
->idxen
= true;
5728 mubuf
->glc
= return_previous
;
5729 mubuf
->dlc
= false; /* Not needed for atomics */
5730 mubuf
->disable_wqm
= true;
5731 mubuf
->barrier
= barrier_image
;
5732 ctx
->program
->needs_exact
= true;
5733 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5737 Temp coords
= get_image_coords(ctx
, instr
, type
);
5738 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5739 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5740 mimg
->operands
[0] = Operand(resource
);
5741 mimg
->operands
[1] = Operand(data
);
5742 mimg
->operands
[2] = Operand(coords
);
5743 if (return_previous
)
5744 mimg
->definitions
[0] = Definition(dst
);
5745 mimg
->glc
= return_previous
;
5746 mimg
->dlc
= false; /* Not needed for atomics */
5747 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5748 mimg
->dmask
= (1 << data
.size()) - 1;
5750 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5751 mimg
->disable_wqm
= true;
5752 mimg
->barrier
= barrier_image
;
5753 ctx
->program
->needs_exact
= true;
5754 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5758 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5760 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5761 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5762 Builder
bld(ctx
->program
, ctx
->block
);
5764 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5766 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5767 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5769 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5770 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5772 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5773 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5775 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5776 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5777 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5778 if (dst
.type() == RegType::vgpr
)
5779 bld
.copy(Definition(dst
), shr_dst
);
5781 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5783 emit_extract_vector(ctx
, desc
, 2, dst
);
5787 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5789 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5790 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5791 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5792 bool is_array
= glsl_sampler_type_is_array(type
);
5793 Builder
bld(ctx
->program
, ctx
->block
);
5795 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5796 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5797 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5801 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5804 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5806 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5808 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5809 mimg
->operands
[0] = Operand(resource
);
5810 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5811 mimg
->operands
[2] = Operand(lod
);
5812 uint8_t& dmask
= mimg
->dmask
;
5813 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5814 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5815 mimg
->da
= glsl_sampler_type_is_array(type
);
5816 mimg
->can_reorder
= true;
5817 Definition
& def
= mimg
->definitions
[0];
5818 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5820 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5821 glsl_sampler_type_is_array(type
)) {
5823 assert(instr
->dest
.ssa
.num_components
== 3);
5824 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5825 def
= Definition(tmp
);
5826 emit_split_vector(ctx
, tmp
, 3);
5828 /* divide 3rd value by 6 by multiplying with magic number */
5829 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5830 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5832 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5833 emit_extract_vector(ctx
, tmp
, 0, v1
),
5834 emit_extract_vector(ctx
, tmp
, 1, v1
),
5837 } else if (ctx
->options
->chip_class
== GFX9
&&
5838 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5839 glsl_sampler_type_is_array(type
)) {
5840 assert(instr
->dest
.ssa
.num_components
== 2);
5841 def
= Definition(dst
);
5844 def
= Definition(dst
);
5847 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5850 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5852 Builder
bld(ctx
->program
, ctx
->block
);
5853 unsigned num_components
= instr
->num_components
;
5855 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5856 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5857 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5859 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5860 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5863 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5864 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5865 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5867 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5870 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5872 Builder
bld(ctx
->program
, ctx
->block
);
5873 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5874 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5875 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5876 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5878 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5879 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5881 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5882 ctx
->options
->chip_class
>= GFX8
&&
5883 elem_size_bytes
>= 4;
5885 offset
= bld
.as_uniform(offset
);
5886 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5890 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5891 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5892 /* GFX6 doesn't support storing vec3, split it. */
5893 writemask
|= 1u << (start
+ 2);
5896 int num_bytes
= count
* elem_size_bytes
;
5898 /* dword or larger stores have to be dword-aligned */
5899 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5900 // TODO: improve alignment check of sub-dword stores
5901 unsigned count_new
= 2 / elem_size_bytes
;
5902 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5907 if (num_bytes
> 16) {
5908 assert(elem_size_bytes
== 8);
5909 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5915 if (elem_size_bytes
< 4) {
5916 if (data
.type() == RegType::sgpr
) {
5917 data
= as_vgpr(ctx
, data
);
5918 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5920 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5921 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5922 for (int i
= 0; i
< count
; i
++)
5923 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5924 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5925 vec
->definitions
[0] = Definition(write_data
);
5926 bld
.insert(std::move(vec
));
5927 } else if (count
!= instr
->num_components
) {
5928 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5929 for (int i
= 0; i
< count
; i
++) {
5930 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5931 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5933 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5934 vec
->definitions
[0] = Definition(write_data
);
5935 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5936 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5937 assert(num_bytes
% 4 == 0);
5938 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5939 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5940 assert(num_bytes
% 4 == 0);
5941 write_data
= bld
.as_uniform(data
);
5946 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5947 switch (num_bytes
) {
5949 vmem_op
= aco_opcode::buffer_store_byte
;
5952 vmem_op
= aco_opcode::buffer_store_short
;
5955 vmem_op
= aco_opcode::buffer_store_dword
;
5956 smem_op
= aco_opcode::s_buffer_store_dword
;
5959 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5960 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5963 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5964 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5967 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5968 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5971 unreachable("Store SSBO not implemented for this size.");
5973 if (ctx
->stage
== fragment_fs
)
5974 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5977 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5978 store
->operands
[0] = Operand(rsrc
);
5980 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5981 offset
, Operand(start
* elem_size_bytes
));
5982 store
->operands
[1] = Operand(off
);
5984 store
->operands
[1] = Operand(offset
);
5986 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5987 store
->operands
[1].setFixed(m0
);
5988 store
->operands
[2] = Operand(write_data
);
5989 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5991 store
->disable_wqm
= true;
5992 store
->barrier
= barrier_buffer
;
5993 ctx
->block
->instructions
.emplace_back(std::move(store
));
5994 ctx
->program
->wb_smem_l1_on_end
= true;
5995 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5996 ctx
->block
->kind
|= block_kind_needs_lowering
;
5997 ctx
->program
->needs_exact
= true;
6000 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6001 store
->operands
[0] = Operand(rsrc
);
6002 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6003 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6004 store
->operands
[3] = Operand(write_data
);
6005 store
->offset
= start
* elem_size_bytes
;
6006 store
->offen
= (offset
.type() == RegType::vgpr
);
6007 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6009 store
->disable_wqm
= true;
6010 store
->barrier
= barrier_buffer
;
6011 ctx
->program
->needs_exact
= true;
6012 ctx
->block
->instructions
.emplace_back(std::move(store
));
6017 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6019 /* return the previous value if dest is ever used */
6020 bool return_previous
= false;
6021 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6022 return_previous
= true;
6025 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6026 return_previous
= true;
6030 Builder
bld(ctx
->program
, ctx
->block
);
6031 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6033 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6034 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6035 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6037 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6038 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6039 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6043 aco_opcode op32
, op64
;
6044 switch (instr
->intrinsic
) {
6045 case nir_intrinsic_ssbo_atomic_add
:
6046 op32
= aco_opcode::buffer_atomic_add
;
6047 op64
= aco_opcode::buffer_atomic_add_x2
;
6049 case nir_intrinsic_ssbo_atomic_imin
:
6050 op32
= aco_opcode::buffer_atomic_smin
;
6051 op64
= aco_opcode::buffer_atomic_smin_x2
;
6053 case nir_intrinsic_ssbo_atomic_umin
:
6054 op32
= aco_opcode::buffer_atomic_umin
;
6055 op64
= aco_opcode::buffer_atomic_umin_x2
;
6057 case nir_intrinsic_ssbo_atomic_imax
:
6058 op32
= aco_opcode::buffer_atomic_smax
;
6059 op64
= aco_opcode::buffer_atomic_smax_x2
;
6061 case nir_intrinsic_ssbo_atomic_umax
:
6062 op32
= aco_opcode::buffer_atomic_umax
;
6063 op64
= aco_opcode::buffer_atomic_umax_x2
;
6065 case nir_intrinsic_ssbo_atomic_and
:
6066 op32
= aco_opcode::buffer_atomic_and
;
6067 op64
= aco_opcode::buffer_atomic_and_x2
;
6069 case nir_intrinsic_ssbo_atomic_or
:
6070 op32
= aco_opcode::buffer_atomic_or
;
6071 op64
= aco_opcode::buffer_atomic_or_x2
;
6073 case nir_intrinsic_ssbo_atomic_xor
:
6074 op32
= aco_opcode::buffer_atomic_xor
;
6075 op64
= aco_opcode::buffer_atomic_xor_x2
;
6077 case nir_intrinsic_ssbo_atomic_exchange
:
6078 op32
= aco_opcode::buffer_atomic_swap
;
6079 op64
= aco_opcode::buffer_atomic_swap_x2
;
6081 case nir_intrinsic_ssbo_atomic_comp_swap
:
6082 op32
= aco_opcode::buffer_atomic_cmpswap
;
6083 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6086 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6088 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6089 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6090 mubuf
->operands
[0] = Operand(rsrc
);
6091 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6092 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6093 mubuf
->operands
[3] = Operand(data
);
6094 if (return_previous
)
6095 mubuf
->definitions
[0] = Definition(dst
);
6097 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6098 mubuf
->glc
= return_previous
;
6099 mubuf
->dlc
= false; /* Not needed for atomics */
6100 mubuf
->disable_wqm
= true;
6101 mubuf
->barrier
= barrier_buffer
;
6102 ctx
->program
->needs_exact
= true;
6103 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6106 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6108 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6109 Builder
bld(ctx
->program
, ctx
->block
);
6110 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6111 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6114 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
6116 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6117 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6119 if (addr
.type() == RegType::vgpr
)
6120 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
6121 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
6124 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6126 Builder
bld(ctx
->program
, ctx
->block
);
6127 unsigned num_components
= instr
->num_components
;
6128 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
6130 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6131 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6133 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6134 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
6136 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
6137 bool global
= ctx
->options
->chip_class
>= GFX9
;
6139 if (ctx
->options
->chip_class
>= GFX7
) {
6141 switch (num_bytes
) {
6143 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
6146 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
6149 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
6152 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
6155 unreachable("load_global not implemented for this size.");
6158 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
6159 flat
->operands
[0] = Operand(addr
);
6160 flat
->operands
[1] = Operand(s1
);
6163 flat
->barrier
= barrier_buffer
;
6165 if (dst
.type() == RegType::sgpr
) {
6166 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6167 flat
->definitions
[0] = Definition(vec
);
6168 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6169 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6171 flat
->definitions
[0] = Definition(dst
);
6172 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6174 emit_split_vector(ctx
, dst
, num_components
);
6176 assert(ctx
->options
->chip_class
== GFX6
);
6178 /* GFX6 doesn't support loading vec3, expand to vec4. */
6179 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6182 switch (num_bytes
) {
6184 op
= aco_opcode::buffer_load_dword
;
6187 op
= aco_opcode::buffer_load_dwordx2
;
6190 op
= aco_opcode::buffer_load_dwordx4
;
6193 unreachable("load_global not implemented for this size.");
6196 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6198 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6199 mubuf
->operands
[0] = Operand(rsrc
);
6200 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6201 mubuf
->operands
[2] = Operand(0u);
6205 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6206 mubuf
->disable_wqm
= false;
6207 mubuf
->barrier
= barrier_buffer
;
6208 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6211 if (dst
.size() == 3) {
6212 Temp vec
= bld
.tmp(v4
);
6213 instr
->definitions
[0] = Definition(vec
);
6214 bld
.insert(std::move(instr
));
6215 emit_split_vector(ctx
, vec
, 4);
6217 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6218 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6219 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6220 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6223 if (dst
.type() == RegType::sgpr
) {
6224 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6225 instr
->definitions
[0] = Definition(vec
);
6226 bld
.insert(std::move(instr
));
6227 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6228 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6230 instr
->definitions
[0] = Definition(dst
);
6231 bld
.insert(std::move(instr
));
6232 emit_split_vector(ctx
, dst
, num_components
);
6236 switch (num_bytes
) {
6238 op
= aco_opcode::s_load_dword
;
6241 op
= aco_opcode::s_load_dwordx2
;
6245 op
= aco_opcode::s_load_dwordx4
;
6248 unreachable("load_global not implemented for this size.");
6250 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6251 load
->operands
[0] = Operand(addr
);
6252 load
->operands
[1] = Operand(0u);
6253 load
->definitions
[0] = Definition(dst
);
6256 load
->barrier
= barrier_buffer
;
6257 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6259 if (dst
.size() == 3) {
6261 Temp vec
= bld
.tmp(s4
);
6262 load
->definitions
[0] = Definition(vec
);
6263 ctx
->block
->instructions
.emplace_back(std::move(load
));
6264 emit_split_vector(ctx
, vec
, 4);
6266 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6267 emit_extract_vector(ctx
, vec
, 0, s1
),
6268 emit_extract_vector(ctx
, vec
, 1, s1
),
6269 emit_extract_vector(ctx
, vec
, 2, s1
));
6271 ctx
->block
->instructions
.emplace_back(std::move(load
));
6276 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6278 Builder
bld(ctx
->program
, ctx
->block
);
6279 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6281 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6282 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6284 if (ctx
->options
->chip_class
>= GFX7
)
6285 addr
= as_vgpr(ctx
, addr
);
6287 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6290 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6291 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6292 /* GFX6 doesn't support storing vec3, split it. */
6293 writemask
|= 1u << (start
+ 2);
6296 unsigned num_bytes
= count
* elem_size_bytes
;
6298 Temp write_data
= data
;
6299 if (count
!= instr
->num_components
) {
6300 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6301 for (int i
= 0; i
< count
; i
++)
6302 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6303 write_data
= bld
.tmp(RegType::vgpr
, count
);
6304 vec
->definitions
[0] = Definition(write_data
);
6305 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6308 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6309 unsigned offset
= start
* elem_size_bytes
;
6311 if (ctx
->options
->chip_class
>= GFX7
) {
6312 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6313 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6314 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6315 Temp carry
= bld
.tmp(bld
.lm
);
6316 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6318 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6319 Operand(offset
), addr0
);
6320 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6322 carry
).def(1).setHint(vcc
);
6324 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6329 bool global
= ctx
->options
->chip_class
>= GFX9
;
6331 switch (num_bytes
) {
6333 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6336 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6339 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6342 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6345 unreachable("store_global not implemented for this size.");
6348 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6349 flat
->operands
[0] = Operand(addr
);
6350 flat
->operands
[1] = Operand(s1
);
6351 flat
->operands
[2] = Operand(data
);
6354 flat
->offset
= offset
;
6355 flat
->disable_wqm
= true;
6356 flat
->barrier
= barrier_buffer
;
6357 ctx
->program
->needs_exact
= true;
6358 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6360 assert(ctx
->options
->chip_class
== GFX6
);
6363 switch (num_bytes
) {
6365 op
= aco_opcode::buffer_store_dword
;
6368 op
= aco_opcode::buffer_store_dwordx2
;
6371 op
= aco_opcode::buffer_store_dwordx4
;
6374 unreachable("store_global not implemented for this size.");
6377 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6379 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6380 mubuf
->operands
[0] = Operand(rsrc
);
6381 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6382 mubuf
->operands
[2] = Operand(0u);
6383 mubuf
->operands
[3] = Operand(write_data
);
6386 mubuf
->offset
= offset
;
6387 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6388 mubuf
->disable_wqm
= true;
6389 mubuf
->barrier
= barrier_buffer
;
6390 ctx
->program
->needs_exact
= true;
6391 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6396 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6398 /* return the previous value if dest is ever used */
6399 bool return_previous
= false;
6400 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6401 return_previous
= true;
6404 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6405 return_previous
= true;
6409 Builder
bld(ctx
->program
, ctx
->block
);
6410 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6411 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6413 if (ctx
->options
->chip_class
>= GFX7
)
6414 addr
= as_vgpr(ctx
, addr
);
6416 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6417 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6418 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6420 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6422 aco_opcode op32
, op64
;
6424 if (ctx
->options
->chip_class
>= GFX7
) {
6425 bool global
= ctx
->options
->chip_class
>= GFX9
;
6426 switch (instr
->intrinsic
) {
6427 case nir_intrinsic_global_atomic_add
:
6428 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6429 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6431 case nir_intrinsic_global_atomic_imin
:
6432 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6433 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6435 case nir_intrinsic_global_atomic_umin
:
6436 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6437 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6439 case nir_intrinsic_global_atomic_imax
:
6440 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6441 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6443 case nir_intrinsic_global_atomic_umax
:
6444 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6445 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6447 case nir_intrinsic_global_atomic_and
:
6448 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6449 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6451 case nir_intrinsic_global_atomic_or
:
6452 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6453 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6455 case nir_intrinsic_global_atomic_xor
:
6456 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6457 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6459 case nir_intrinsic_global_atomic_exchange
:
6460 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6461 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6463 case nir_intrinsic_global_atomic_comp_swap
:
6464 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6465 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6468 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6471 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6472 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6473 flat
->operands
[0] = Operand(addr
);
6474 flat
->operands
[1] = Operand(s1
);
6475 flat
->operands
[2] = Operand(data
);
6476 if (return_previous
)
6477 flat
->definitions
[0] = Definition(dst
);
6478 flat
->glc
= return_previous
;
6479 flat
->dlc
= false; /* Not needed for atomics */
6481 flat
->disable_wqm
= true;
6482 flat
->barrier
= barrier_buffer
;
6483 ctx
->program
->needs_exact
= true;
6484 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6486 assert(ctx
->options
->chip_class
== GFX6
);
6488 switch (instr
->intrinsic
) {
6489 case nir_intrinsic_global_atomic_add
:
6490 op32
= aco_opcode::buffer_atomic_add
;
6491 op64
= aco_opcode::buffer_atomic_add_x2
;
6493 case nir_intrinsic_global_atomic_imin
:
6494 op32
= aco_opcode::buffer_atomic_smin
;
6495 op64
= aco_opcode::buffer_atomic_smin_x2
;
6497 case nir_intrinsic_global_atomic_umin
:
6498 op32
= aco_opcode::buffer_atomic_umin
;
6499 op64
= aco_opcode::buffer_atomic_umin_x2
;
6501 case nir_intrinsic_global_atomic_imax
:
6502 op32
= aco_opcode::buffer_atomic_smax
;
6503 op64
= aco_opcode::buffer_atomic_smax_x2
;
6505 case nir_intrinsic_global_atomic_umax
:
6506 op32
= aco_opcode::buffer_atomic_umax
;
6507 op64
= aco_opcode::buffer_atomic_umax_x2
;
6509 case nir_intrinsic_global_atomic_and
:
6510 op32
= aco_opcode::buffer_atomic_and
;
6511 op64
= aco_opcode::buffer_atomic_and_x2
;
6513 case nir_intrinsic_global_atomic_or
:
6514 op32
= aco_opcode::buffer_atomic_or
;
6515 op64
= aco_opcode::buffer_atomic_or_x2
;
6517 case nir_intrinsic_global_atomic_xor
:
6518 op32
= aco_opcode::buffer_atomic_xor
;
6519 op64
= aco_opcode::buffer_atomic_xor_x2
;
6521 case nir_intrinsic_global_atomic_exchange
:
6522 op32
= aco_opcode::buffer_atomic_swap
;
6523 op64
= aco_opcode::buffer_atomic_swap_x2
;
6525 case nir_intrinsic_global_atomic_comp_swap
:
6526 op32
= aco_opcode::buffer_atomic_cmpswap
;
6527 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6530 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6533 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6535 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6537 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6538 mubuf
->operands
[0] = Operand(rsrc
);
6539 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6540 mubuf
->operands
[2] = Operand(0u);
6541 mubuf
->operands
[3] = Operand(data
);
6542 if (return_previous
)
6543 mubuf
->definitions
[0] = Definition(dst
);
6544 mubuf
->glc
= return_previous
;
6547 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6548 mubuf
->disable_wqm
= true;
6549 mubuf
->barrier
= barrier_buffer
;
6550 ctx
->program
->needs_exact
= true;
6551 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6555 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6556 Builder
bld(ctx
->program
, ctx
->block
);
6557 switch(instr
->intrinsic
) {
6558 case nir_intrinsic_group_memory_barrier
:
6559 case nir_intrinsic_memory_barrier
:
6560 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6562 case nir_intrinsic_memory_barrier_buffer
:
6563 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6565 case nir_intrinsic_memory_barrier_image
:
6566 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6568 case nir_intrinsic_memory_barrier_tcs_patch
:
6569 case nir_intrinsic_memory_barrier_shared
:
6570 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6573 unreachable("Unimplemented memory barrier intrinsic");
6578 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6580 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6581 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6582 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6583 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6584 Builder
bld(ctx
->program
, ctx
->block
);
6586 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6587 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6588 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6591 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6593 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6594 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6595 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6596 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6597 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6599 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6600 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6603 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6605 unsigned offset
= nir_intrinsic_base(instr
);
6606 Operand m
= load_lds_size_m0(ctx
);
6607 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6608 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6610 unsigned num_operands
= 3;
6611 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6612 switch(instr
->intrinsic
) {
6613 case nir_intrinsic_shared_atomic_add
:
6614 op32
= aco_opcode::ds_add_u32
;
6615 op64
= aco_opcode::ds_add_u64
;
6616 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6617 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6619 case nir_intrinsic_shared_atomic_imin
:
6620 op32
= aco_opcode::ds_min_i32
;
6621 op64
= aco_opcode::ds_min_i64
;
6622 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6623 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6625 case nir_intrinsic_shared_atomic_umin
:
6626 op32
= aco_opcode::ds_min_u32
;
6627 op64
= aco_opcode::ds_min_u64
;
6628 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6629 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6631 case nir_intrinsic_shared_atomic_imax
:
6632 op32
= aco_opcode::ds_max_i32
;
6633 op64
= aco_opcode::ds_max_i64
;
6634 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6635 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6637 case nir_intrinsic_shared_atomic_umax
:
6638 op32
= aco_opcode::ds_max_u32
;
6639 op64
= aco_opcode::ds_max_u64
;
6640 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6641 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6643 case nir_intrinsic_shared_atomic_and
:
6644 op32
= aco_opcode::ds_and_b32
;
6645 op64
= aco_opcode::ds_and_b64
;
6646 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6647 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6649 case nir_intrinsic_shared_atomic_or
:
6650 op32
= aco_opcode::ds_or_b32
;
6651 op64
= aco_opcode::ds_or_b64
;
6652 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6653 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6655 case nir_intrinsic_shared_atomic_xor
:
6656 op32
= aco_opcode::ds_xor_b32
;
6657 op64
= aco_opcode::ds_xor_b64
;
6658 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6659 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6661 case nir_intrinsic_shared_atomic_exchange
:
6662 op32
= aco_opcode::ds_write_b32
;
6663 op64
= aco_opcode::ds_write_b64
;
6664 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6665 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6667 case nir_intrinsic_shared_atomic_comp_swap
:
6668 op32
= aco_opcode::ds_cmpst_b32
;
6669 op64
= aco_opcode::ds_cmpst_b64
;
6670 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6671 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6675 unreachable("Unhandled shared atomic intrinsic");
6678 /* return the previous value if dest is ever used */
6679 bool return_previous
= false;
6680 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6681 return_previous
= true;
6684 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6685 return_previous
= true;
6690 if (data
.size() == 1) {
6691 assert(instr
->dest
.ssa
.bit_size
== 32);
6692 op
= return_previous
? op32_rtn
: op32
;
6694 assert(instr
->dest
.ssa
.bit_size
== 64);
6695 op
= return_previous
? op64_rtn
: op64
;
6698 if (offset
> 65535) {
6699 Builder
bld(ctx
->program
, ctx
->block
);
6700 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6704 aco_ptr
<DS_instruction
> ds
;
6705 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6706 ds
->operands
[0] = Operand(address
);
6707 ds
->operands
[1] = Operand(data
);
6708 if (num_operands
== 4)
6709 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6710 ds
->operands
[num_operands
- 1] = m
;
6711 ds
->offset0
= offset
;
6712 if (return_previous
)
6713 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6714 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6717 Temp
get_scratch_resource(isel_context
*ctx
)
6719 Builder
bld(ctx
->program
, ctx
->block
);
6720 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6721 if (ctx
->stage
!= compute_cs
)
6722 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6724 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6725 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6727 if (ctx
->program
->chip_class
>= GFX10
) {
6728 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6729 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6730 S_008F0C_RESOURCE_LEVEL(1);
6731 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6732 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6733 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6736 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6737 if (ctx
->program
->chip_class
<= GFX8
)
6738 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6740 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6743 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6744 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6745 Builder
bld(ctx
->program
, ctx
->block
);
6746 Temp rsrc
= get_scratch_resource(ctx
);
6747 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6748 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6751 switch (dst
.size()) {
6753 op
= aco_opcode::buffer_load_dword
;
6756 op
= aco_opcode::buffer_load_dwordx2
;
6759 op
= aco_opcode::buffer_load_dwordx3
;
6762 op
= aco_opcode::buffer_load_dwordx4
;
6766 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6767 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6768 bld
.def(v4
), rsrc
, offset
,
6769 ctx
->program
->scratch_offset
, 0, true);
6770 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6771 aco_opcode::buffer_load_dwordx4
,
6772 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6773 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6774 emit_split_vector(ctx
, lower
, 2);
6775 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6776 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6777 if (dst
.size() == 8) {
6778 emit_split_vector(ctx
, upper
, 2);
6779 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6780 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6785 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6786 Format::PSEUDO
, dst
.size() / 2, 1)};
6787 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6788 vec
->operands
[i
] = Operand(elems
[i
]);
6789 vec
->definitions
[0] = Definition(dst
);
6790 bld
.insert(std::move(vec
));
6791 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6795 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6798 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6799 emit_split_vector(ctx
, dst
, instr
->num_components
);
6802 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6803 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6804 Builder
bld(ctx
->program
, ctx
->block
);
6805 Temp rsrc
= get_scratch_resource(ctx
);
6806 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6807 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6809 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6810 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6814 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6815 int num_bytes
= count
* elem_size_bytes
;
6817 if (num_bytes
> 16) {
6818 assert(elem_size_bytes
== 8);
6819 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6824 // TODO: check alignment of sub-dword stores
6825 // TODO: split 3 bytes. there is no store instruction for that
6828 if (count
!= instr
->num_components
) {
6829 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6830 for (int i
= 0; i
< count
; i
++) {
6831 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6832 vec
->operands
[i
] = Operand(elem
);
6834 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6835 vec
->definitions
[0] = Definition(write_data
);
6836 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6842 switch (num_bytes
) {
6844 op
= aco_opcode::buffer_store_dword
;
6847 op
= aco_opcode::buffer_store_dwordx2
;
6850 op
= aco_opcode::buffer_store_dwordx3
;
6853 op
= aco_opcode::buffer_store_dwordx4
;
6856 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6859 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6863 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6864 uint8_t log2_ps_iter_samples
;
6865 if (ctx
->program
->info
->ps
.force_persample
) {
6866 log2_ps_iter_samples
=
6867 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6869 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6872 /* The bit pattern matches that used by fixed function fragment
6874 static const unsigned ps_iter_masks
[] = {
6875 0xffff, /* not used */
6881 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6883 Builder
bld(ctx
->program
, ctx
->block
);
6885 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6886 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6887 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6888 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6889 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6890 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6893 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6894 Builder
bld(ctx
->program
, ctx
->block
);
6896 unsigned stream
= nir_intrinsic_stream_id(instr
);
6897 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6898 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6899 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6902 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6904 unsigned num_components
=
6905 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6906 assert(num_components
);
6908 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6909 unsigned stream_offset
= 0;
6910 for (unsigned i
= 0; i
< stream
; i
++) {
6911 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6912 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6915 /* Limit on the stride field for <= GFX7. */
6916 assert(stride
< (1 << 14));
6918 Temp gsvs_dwords
[4];
6919 for (unsigned i
= 0; i
< 4; i
++)
6920 gsvs_dwords
[i
] = bld
.tmp(s1
);
6921 bld
.pseudo(aco_opcode::p_split_vector
,
6922 Definition(gsvs_dwords
[0]),
6923 Definition(gsvs_dwords
[1]),
6924 Definition(gsvs_dwords
[2]),
6925 Definition(gsvs_dwords
[3]),
6928 if (stream_offset
) {
6929 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6931 Temp carry
= bld
.tmp(s1
);
6932 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6933 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6936 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6937 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6939 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6940 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6942 unsigned offset
= 0;
6943 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6944 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6947 for (unsigned j
= 0; j
< 4; j
++) {
6948 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6951 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6952 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6953 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6954 if (const_offset
>= 4096u) {
6955 if (vaddr_offset
.isUndefined())
6956 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6958 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6959 const_offset
%= 4096u;
6962 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6963 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6964 mtbuf
->operands
[1] = vaddr_offset
;
6965 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6966 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6967 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6968 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6969 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6970 mtbuf
->offset
= const_offset
;
6973 mtbuf
->barrier
= barrier_gs_data
;
6974 mtbuf
->can_reorder
= true;
6975 bld
.insert(std::move(mtbuf
));
6978 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6981 /* outputs for the next vertex are undefined and keeping them around can
6982 * create invalid IR with control flow */
6983 ctx
->outputs
.mask
[i
] = 0;
6986 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6989 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6991 Builder
bld(ctx
->program
, ctx
->block
);
6993 if (cluster_size
== 1) {
6995 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6996 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6997 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6998 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6999 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7000 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7001 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7002 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7003 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7004 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7005 //subgroupAnd(val) -> (exec & ~val) == 0
7006 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7007 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7008 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7009 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7010 //subgroupOr(val) -> (val & exec) != 0
7011 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7012 return bool_to_vector_condition(ctx
, tmp
);
7013 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7014 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7015 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7016 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7017 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7018 return bool_to_vector_condition(ctx
, tmp
);
7020 //subgroupClustered{And,Or,Xor}(val, n) ->
7021 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7022 //cluster_offset = ~(n - 1) & lane_id
7023 //cluster_mask = ((1 << n) - 1)
7024 //subgroupClusteredAnd():
7025 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7026 //subgroupClusteredOr():
7027 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7028 //subgroupClusteredXor():
7029 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7030 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7031 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7034 if (op
== nir_op_iand
)
7035 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7037 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7039 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7041 if (ctx
->program
->chip_class
<= GFX7
)
7042 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7043 else if (ctx
->program
->wave_size
== 64)
7044 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7046 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7047 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7048 if (cluster_mask
!= 0xffffffff)
7049 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7051 Definition cmp_def
= Definition();
7052 if (op
== nir_op_iand
) {
7053 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7054 } else if (op
== nir_op_ior
) {
7055 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7056 } else if (op
== nir_op_ixor
) {
7057 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7058 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7059 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7061 cmp_def
.setHint(vcc
);
7062 return cmp_def
.getTemp();
7066 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7068 Builder
bld(ctx
->program
, ctx
->block
);
7070 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7071 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7072 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7074 if (op
== nir_op_iand
)
7075 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7077 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7079 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7080 Temp lo
= lohi
.def(0).getTemp();
7081 Temp hi
= lohi
.def(1).getTemp();
7082 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7084 Definition cmp_def
= Definition();
7085 if (op
== nir_op_iand
)
7086 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7087 else if (op
== nir_op_ior
)
7088 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7089 else if (op
== nir_op_ixor
)
7090 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7091 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7092 cmp_def
.setHint(vcc
);
7093 return cmp_def
.getTemp();
7096 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7098 Builder
bld(ctx
->program
, ctx
->block
);
7100 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7101 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7102 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7103 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7104 if (op
== nir_op_iand
)
7105 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7106 else if (op
== nir_op_ior
)
7107 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7108 else if (op
== nir_op_ixor
)
7109 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7115 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7117 Builder
bld(ctx
->program
, ctx
->block
);
7118 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7119 if (src
.regClass().type() == RegType::vgpr
) {
7120 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7121 } else if (src
.regClass() == s1
) {
7122 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7123 } else if (src
.regClass() == s2
) {
7124 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7127 nir_print_instr(&instr
->instr
, stderr
);
7128 fprintf(stderr
, "\n");
7132 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7134 Builder
bld(ctx
->program
, ctx
->block
);
7135 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7136 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7137 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7139 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7140 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7141 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7142 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7145 if (ctx
->program
->chip_class
>= GFX8
) {
7146 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7147 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7148 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7149 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7150 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7151 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7153 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7154 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7155 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7156 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7157 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7158 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7159 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7160 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7161 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7162 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7165 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7166 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7167 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7168 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7169 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7170 Temp wqm1
= bld
.tmp(v1
);
7171 emit_wqm(ctx
, tmp1
, wqm1
, true);
7172 Temp wqm2
= bld
.tmp(v1
);
7173 emit_wqm(ctx
, tmp2
, wqm2
, true);
7174 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7178 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7180 Builder
bld(ctx
->program
, ctx
->block
);
7181 switch(instr
->intrinsic
) {
7182 case nir_intrinsic_load_barycentric_sample
:
7183 case nir_intrinsic_load_barycentric_pixel
:
7184 case nir_intrinsic_load_barycentric_centroid
: {
7185 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7186 Temp bary
= Temp(0, s2
);
7188 case INTERP_MODE_SMOOTH
:
7189 case INTERP_MODE_NONE
:
7190 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7191 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7192 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7193 bary
= ctx
->persp_centroid
;
7194 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7195 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7197 case INTERP_MODE_NOPERSPECTIVE
:
7198 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7199 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7200 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7201 bary
= ctx
->linear_centroid
;
7202 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7203 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7208 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7209 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7210 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7211 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7212 Operand(p1
), Operand(p2
));
7213 emit_split_vector(ctx
, dst
, 2);
7216 case nir_intrinsic_load_barycentric_model
: {
7217 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7219 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7220 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7221 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7222 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7223 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7224 Operand(p1
), Operand(p2
), Operand(p3
));
7225 emit_split_vector(ctx
, dst
, 3);
7228 case nir_intrinsic_load_barycentric_at_sample
: {
7229 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7230 switch (ctx
->options
->key
.fs
.num_samples
) {
7231 case 2: sample_pos_offset
+= 1 << 3; break;
7232 case 4: sample_pos_offset
+= 3 << 3; break;
7233 case 8: sample_pos_offset
+= 7 << 3; break;
7237 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7238 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7239 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7240 if (addr
.type() == RegType::sgpr
) {
7243 sample_pos_offset
+= const_addr
->u32
<< 3;
7244 offset
= Operand(sample_pos_offset
);
7245 } else if (ctx
->options
->chip_class
>= GFX9
) {
7246 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7248 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7249 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7252 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7253 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7255 } else if (ctx
->options
->chip_class
>= GFX9
) {
7256 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7257 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7258 } else if (ctx
->options
->chip_class
>= GFX7
) {
7259 /* addr += private_segment_buffer + sample_pos_offset */
7260 Temp tmp0
= bld
.tmp(s1
);
7261 Temp tmp1
= bld
.tmp(s1
);
7262 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7263 Definition scc_tmp
= bld
.def(s1
, scc
);
7264 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7265 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7266 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7267 Temp pck0
= bld
.tmp(v1
);
7268 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7269 tmp1
= as_vgpr(ctx
, tmp1
);
7270 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7271 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7273 /* sample_pos = flat_load_dwordx2 addr */
7274 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7276 assert(ctx
->options
->chip_class
== GFX6
);
7278 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7279 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7280 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7282 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7283 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7285 sample_pos
= bld
.tmp(v2
);
7287 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7288 load
->definitions
[0] = Definition(sample_pos
);
7289 load
->operands
[0] = Operand(rsrc
);
7290 load
->operands
[1] = Operand(addr
);
7291 load
->operands
[2] = Operand(0u);
7292 load
->offset
= sample_pos_offset
;
7294 load
->addr64
= true;
7297 load
->disable_wqm
= false;
7298 load
->barrier
= barrier_none
;
7299 load
->can_reorder
= true;
7300 ctx
->block
->instructions
.emplace_back(std::move(load
));
7303 /* sample_pos -= 0.5 */
7304 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7305 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7306 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7307 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7308 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7310 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7313 case nir_intrinsic_load_barycentric_at_offset
: {
7314 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7315 RegClass rc
= RegClass(offset
.type(), 1);
7316 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7317 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7318 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7321 case nir_intrinsic_load_front_face
: {
7322 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7323 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7326 case nir_intrinsic_load_view_index
: {
7327 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7328 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7329 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7335 case nir_intrinsic_load_layer_id
: {
7336 unsigned idx
= nir_intrinsic_base(instr
);
7337 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7338 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7341 case nir_intrinsic_load_frag_coord
: {
7342 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7345 case nir_intrinsic_load_sample_pos
: {
7346 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7347 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7348 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7349 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7350 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7353 case nir_intrinsic_load_tess_coord
:
7354 visit_load_tess_coord(ctx
, instr
);
7356 case nir_intrinsic_load_interpolated_input
:
7357 visit_load_interpolated_input(ctx
, instr
);
7359 case nir_intrinsic_store_output
:
7360 visit_store_output(ctx
, instr
);
7362 case nir_intrinsic_load_input
:
7363 case nir_intrinsic_load_input_vertex
:
7364 visit_load_input(ctx
, instr
);
7366 case nir_intrinsic_load_output
:
7367 visit_load_output(ctx
, instr
);
7369 case nir_intrinsic_load_per_vertex_input
:
7370 visit_load_per_vertex_input(ctx
, instr
);
7372 case nir_intrinsic_load_per_vertex_output
:
7373 visit_load_per_vertex_output(ctx
, instr
);
7375 case nir_intrinsic_store_per_vertex_output
:
7376 visit_store_per_vertex_output(ctx
, instr
);
7378 case nir_intrinsic_load_ubo
:
7379 visit_load_ubo(ctx
, instr
);
7381 case nir_intrinsic_load_push_constant
:
7382 visit_load_push_constant(ctx
, instr
);
7384 case nir_intrinsic_load_constant
:
7385 visit_load_constant(ctx
, instr
);
7387 case nir_intrinsic_vulkan_resource_index
:
7388 visit_load_resource(ctx
, instr
);
7390 case nir_intrinsic_discard
:
7391 visit_discard(ctx
, instr
);
7393 case nir_intrinsic_discard_if
:
7394 visit_discard_if(ctx
, instr
);
7396 case nir_intrinsic_load_shared
:
7397 visit_load_shared(ctx
, instr
);
7399 case nir_intrinsic_store_shared
:
7400 visit_store_shared(ctx
, instr
);
7402 case nir_intrinsic_shared_atomic_add
:
7403 case nir_intrinsic_shared_atomic_imin
:
7404 case nir_intrinsic_shared_atomic_umin
:
7405 case nir_intrinsic_shared_atomic_imax
:
7406 case nir_intrinsic_shared_atomic_umax
:
7407 case nir_intrinsic_shared_atomic_and
:
7408 case nir_intrinsic_shared_atomic_or
:
7409 case nir_intrinsic_shared_atomic_xor
:
7410 case nir_intrinsic_shared_atomic_exchange
:
7411 case nir_intrinsic_shared_atomic_comp_swap
:
7412 visit_shared_atomic(ctx
, instr
);
7414 case nir_intrinsic_image_deref_load
:
7415 visit_image_load(ctx
, instr
);
7417 case nir_intrinsic_image_deref_store
:
7418 visit_image_store(ctx
, instr
);
7420 case nir_intrinsic_image_deref_atomic_add
:
7421 case nir_intrinsic_image_deref_atomic_umin
:
7422 case nir_intrinsic_image_deref_atomic_imin
:
7423 case nir_intrinsic_image_deref_atomic_umax
:
7424 case nir_intrinsic_image_deref_atomic_imax
:
7425 case nir_intrinsic_image_deref_atomic_and
:
7426 case nir_intrinsic_image_deref_atomic_or
:
7427 case nir_intrinsic_image_deref_atomic_xor
:
7428 case nir_intrinsic_image_deref_atomic_exchange
:
7429 case nir_intrinsic_image_deref_atomic_comp_swap
:
7430 visit_image_atomic(ctx
, instr
);
7432 case nir_intrinsic_image_deref_size
:
7433 visit_image_size(ctx
, instr
);
7435 case nir_intrinsic_load_ssbo
:
7436 visit_load_ssbo(ctx
, instr
);
7438 case nir_intrinsic_store_ssbo
:
7439 visit_store_ssbo(ctx
, instr
);
7441 case nir_intrinsic_load_global
:
7442 visit_load_global(ctx
, instr
);
7444 case nir_intrinsic_store_global
:
7445 visit_store_global(ctx
, instr
);
7447 case nir_intrinsic_global_atomic_add
:
7448 case nir_intrinsic_global_atomic_imin
:
7449 case nir_intrinsic_global_atomic_umin
:
7450 case nir_intrinsic_global_atomic_imax
:
7451 case nir_intrinsic_global_atomic_umax
:
7452 case nir_intrinsic_global_atomic_and
:
7453 case nir_intrinsic_global_atomic_or
:
7454 case nir_intrinsic_global_atomic_xor
:
7455 case nir_intrinsic_global_atomic_exchange
:
7456 case nir_intrinsic_global_atomic_comp_swap
:
7457 visit_global_atomic(ctx
, instr
);
7459 case nir_intrinsic_ssbo_atomic_add
:
7460 case nir_intrinsic_ssbo_atomic_imin
:
7461 case nir_intrinsic_ssbo_atomic_umin
:
7462 case nir_intrinsic_ssbo_atomic_imax
:
7463 case nir_intrinsic_ssbo_atomic_umax
:
7464 case nir_intrinsic_ssbo_atomic_and
:
7465 case nir_intrinsic_ssbo_atomic_or
:
7466 case nir_intrinsic_ssbo_atomic_xor
:
7467 case nir_intrinsic_ssbo_atomic_exchange
:
7468 case nir_intrinsic_ssbo_atomic_comp_swap
:
7469 visit_atomic_ssbo(ctx
, instr
);
7471 case nir_intrinsic_load_scratch
:
7472 visit_load_scratch(ctx
, instr
);
7474 case nir_intrinsic_store_scratch
:
7475 visit_store_scratch(ctx
, instr
);
7477 case nir_intrinsic_get_buffer_size
:
7478 visit_get_buffer_size(ctx
, instr
);
7480 case nir_intrinsic_control_barrier
: {
7481 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7482 /* GFX6 only (thanks to a hw bug workaround):
7483 * The real barrier instruction isn’t needed, because an entire patch
7484 * always fits into a single wave.
7489 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7490 bld
.sopp(aco_opcode::s_barrier
);
7494 case nir_intrinsic_memory_barrier_tcs_patch
:
7495 case nir_intrinsic_group_memory_barrier
:
7496 case nir_intrinsic_memory_barrier
:
7497 case nir_intrinsic_memory_barrier_buffer
:
7498 case nir_intrinsic_memory_barrier_image
:
7499 case nir_intrinsic_memory_barrier_shared
:
7500 emit_memory_barrier(ctx
, instr
);
7502 case nir_intrinsic_load_num_work_groups
: {
7503 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7504 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7505 emit_split_vector(ctx
, dst
, 3);
7508 case nir_intrinsic_load_local_invocation_id
: {
7509 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7510 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7511 emit_split_vector(ctx
, dst
, 3);
7514 case nir_intrinsic_load_work_group_id
: {
7515 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7516 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7518 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7519 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7520 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7521 emit_split_vector(ctx
, dst
, 3);
7524 case nir_intrinsic_load_local_invocation_index
: {
7525 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7527 /* The tg_size bits [6:11] contain the subgroup id,
7528 * we need this multiplied by the wave size, and then OR the thread id to it.
7530 if (ctx
->program
->wave_size
== 64) {
7531 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7532 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7533 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7534 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7536 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7537 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7538 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7539 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7543 case nir_intrinsic_load_subgroup_id
: {
7544 if (ctx
->stage
== compute_cs
) {
7545 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7546 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7548 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7552 case nir_intrinsic_load_subgroup_invocation
: {
7553 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7556 case nir_intrinsic_load_num_subgroups
: {
7557 if (ctx
->stage
== compute_cs
)
7558 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7559 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7561 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7564 case nir_intrinsic_ballot
: {
7565 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7566 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7567 Definition tmp
= bld
.def(dst
.regClass());
7568 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7569 if (instr
->src
[0].ssa
->bit_size
== 1) {
7570 assert(src
.regClass() == bld
.lm
);
7571 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7572 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7573 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7574 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7575 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7577 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7578 nir_print_instr(&instr
->instr
, stderr
);
7579 fprintf(stderr
, "\n");
7581 if (dst
.size() != bld
.lm
.size()) {
7582 /* Wave32 with ballot size set to 64 */
7583 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7585 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7588 case nir_intrinsic_shuffle
:
7589 case nir_intrinsic_read_invocation
: {
7590 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7591 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7592 emit_uniform_subgroup(ctx
, instr
, src
);
7594 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7595 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7596 tid
= bld
.as_uniform(tid
);
7597 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7598 if (src
.regClass() == v1
) {
7599 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7600 } else if (src
.regClass() == v2
) {
7601 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7602 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7603 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7604 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7606 emit_split_vector(ctx
, dst
, 2);
7607 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7608 assert(src
.regClass() == bld
.lm
);
7609 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7610 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7611 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7612 assert(src
.regClass() == bld
.lm
);
7614 if (ctx
->program
->chip_class
<= GFX7
)
7615 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7616 else if (ctx
->program
->wave_size
== 64)
7617 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7619 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7620 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7621 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7622 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7624 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7625 nir_print_instr(&instr
->instr
, stderr
);
7626 fprintf(stderr
, "\n");
7631 case nir_intrinsic_load_sample_id
: {
7632 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7633 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7636 case nir_intrinsic_load_sample_mask_in
: {
7637 visit_load_sample_mask_in(ctx
, instr
);
7640 case nir_intrinsic_read_first_invocation
: {
7641 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7642 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7643 if (src
.regClass() == v1
) {
7645 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7647 } else if (src
.regClass() == v2
) {
7648 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7649 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7650 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7651 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7652 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7653 emit_split_vector(ctx
, dst
, 2);
7654 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7655 assert(src
.regClass() == bld
.lm
);
7656 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7657 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7658 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7659 } else if (src
.regClass() == s1
) {
7660 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7661 } else if (src
.regClass() == s2
) {
7662 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7664 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7665 nir_print_instr(&instr
->instr
, stderr
);
7666 fprintf(stderr
, "\n");
7670 case nir_intrinsic_vote_all
: {
7671 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7672 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7673 assert(src
.regClass() == bld
.lm
);
7674 assert(dst
.regClass() == bld
.lm
);
7676 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7677 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7678 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7681 case nir_intrinsic_vote_any
: {
7682 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7683 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7684 assert(src
.regClass() == bld
.lm
);
7685 assert(dst
.regClass() == bld
.lm
);
7687 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7688 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7691 case nir_intrinsic_reduce
:
7692 case nir_intrinsic_inclusive_scan
:
7693 case nir_intrinsic_exclusive_scan
: {
7694 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7695 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7696 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7697 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7698 nir_intrinsic_cluster_size(instr
) : 0;
7699 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7701 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7702 emit_uniform_subgroup(ctx
, instr
, src
);
7703 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7704 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7706 else if (op
== nir_op_iadd
)
7708 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7710 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7712 switch (instr
->intrinsic
) {
7713 case nir_intrinsic_reduce
:
7714 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7716 case nir_intrinsic_exclusive_scan
:
7717 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7719 case nir_intrinsic_inclusive_scan
:
7720 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7725 } else if (cluster_size
== 1) {
7726 bld
.copy(Definition(dst
), src
);
7728 src
= as_vgpr(ctx
, src
);
7732 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7747 unreachable("unknown reduction op");
7752 switch (instr
->intrinsic
) {
7753 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7754 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7755 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7757 unreachable("unknown reduce intrinsic");
7760 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7761 reduce
->operands
[0] = Operand(src
);
7762 // filled in by aco_reduce_assign.cpp, used internally as part of the
7764 assert(dst
.size() == 1 || dst
.size() == 2);
7765 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7766 reduce
->operands
[2] = Operand(v1
.as_linear());
7768 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7769 reduce
->definitions
[0] = Definition(tmp_dst
);
7770 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7771 reduce
->definitions
[2] = Definition();
7772 reduce
->definitions
[3] = Definition(scc
, s1
);
7773 reduce
->definitions
[4] = Definition();
7774 reduce
->reduce_op
= reduce_op
;
7775 reduce
->cluster_size
= cluster_size
;
7776 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7778 emit_wqm(ctx
, tmp_dst
, dst
);
7782 case nir_intrinsic_quad_broadcast
: {
7783 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7784 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7785 emit_uniform_subgroup(ctx
, instr
, src
);
7787 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7788 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7789 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7791 if (instr
->dest
.ssa
.bit_size
== 1) {
7792 assert(src
.regClass() == bld
.lm
);
7793 assert(dst
.regClass() == bld
.lm
);
7794 uint32_t half_mask
= 0x11111111u
<< lane
;
7795 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7796 Temp tmp
= bld
.tmp(bld
.lm
);
7797 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7798 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7799 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7800 emit_wqm(ctx
, tmp
, dst
);
7801 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7802 if (ctx
->program
->chip_class
>= GFX8
)
7803 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7805 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7806 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7807 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7808 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7809 if (ctx
->program
->chip_class
>= GFX8
) {
7810 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7811 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7813 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7814 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7816 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7817 emit_split_vector(ctx
, dst
, 2);
7819 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7820 nir_print_instr(&instr
->instr
, stderr
);
7821 fprintf(stderr
, "\n");
7826 case nir_intrinsic_quad_swap_horizontal
:
7827 case nir_intrinsic_quad_swap_vertical
:
7828 case nir_intrinsic_quad_swap_diagonal
:
7829 case nir_intrinsic_quad_swizzle_amd
: {
7830 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7831 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7832 emit_uniform_subgroup(ctx
, instr
, src
);
7835 uint16_t dpp_ctrl
= 0;
7836 switch (instr
->intrinsic
) {
7837 case nir_intrinsic_quad_swap_horizontal
:
7838 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7840 case nir_intrinsic_quad_swap_vertical
:
7841 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7843 case nir_intrinsic_quad_swap_diagonal
:
7844 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7846 case nir_intrinsic_quad_swizzle_amd
:
7847 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7852 if (ctx
->program
->chip_class
< GFX8
)
7853 dpp_ctrl
|= (1 << 15);
7855 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7856 if (instr
->dest
.ssa
.bit_size
== 1) {
7857 assert(src
.regClass() == bld
.lm
);
7858 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7859 if (ctx
->program
->chip_class
>= GFX8
)
7860 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7862 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7863 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7864 emit_wqm(ctx
, tmp
, dst
);
7865 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7867 if (ctx
->program
->chip_class
>= GFX8
)
7868 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7870 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7871 emit_wqm(ctx
, tmp
, dst
);
7872 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7873 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7874 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7875 if (ctx
->program
->chip_class
>= GFX8
) {
7876 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7877 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7879 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7880 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7882 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7883 emit_split_vector(ctx
, dst
, 2);
7885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7886 nir_print_instr(&instr
->instr
, stderr
);
7887 fprintf(stderr
, "\n");
7891 case nir_intrinsic_masked_swizzle_amd
: {
7892 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7893 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7894 emit_uniform_subgroup(ctx
, instr
, src
);
7897 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7898 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7899 if (dst
.regClass() == v1
) {
7901 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7903 } else if (dst
.regClass() == v2
) {
7904 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7905 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7906 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7907 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7908 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7909 emit_split_vector(ctx
, dst
, 2);
7911 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7912 nir_print_instr(&instr
->instr
, stderr
);
7913 fprintf(stderr
, "\n");
7917 case nir_intrinsic_write_invocation_amd
: {
7918 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7919 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7920 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7921 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7922 if (dst
.regClass() == v1
) {
7923 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7924 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7925 } else if (dst
.regClass() == v2
) {
7926 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7927 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7928 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7929 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7930 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7931 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7932 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7933 emit_split_vector(ctx
, dst
, 2);
7935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7936 nir_print_instr(&instr
->instr
, stderr
);
7937 fprintf(stderr
, "\n");
7941 case nir_intrinsic_mbcnt_amd
: {
7942 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7943 RegClass rc
= RegClass(src
.type(), 1);
7944 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7945 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7947 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7948 emit_wqm(ctx
, wqm_tmp
, dst
);
7951 case nir_intrinsic_load_helper_invocation
: {
7952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7953 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7954 ctx
->block
->kind
|= block_kind_needs_lowering
;
7955 ctx
->program
->needs_exact
= true;
7958 case nir_intrinsic_is_helper_invocation
: {
7959 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7960 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7961 ctx
->block
->kind
|= block_kind_needs_lowering
;
7962 ctx
->program
->needs_exact
= true;
7965 case nir_intrinsic_demote
:
7966 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7968 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7969 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7970 ctx
->block
->kind
|= block_kind_uses_demote
;
7971 ctx
->program
->needs_exact
= true;
7973 case nir_intrinsic_demote_if
: {
7974 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7975 assert(src
.regClass() == bld
.lm
);
7976 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7977 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7979 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7980 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7981 ctx
->block
->kind
|= block_kind_uses_demote
;
7982 ctx
->program
->needs_exact
= true;
7985 case nir_intrinsic_first_invocation
: {
7986 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7987 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7990 case nir_intrinsic_shader_clock
:
7991 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7992 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7994 case nir_intrinsic_load_vertex_id_zero_base
: {
7995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7996 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7999 case nir_intrinsic_load_first_vertex
: {
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8004 case nir_intrinsic_load_base_instance
: {
8005 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8006 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8009 case nir_intrinsic_load_instance_id
: {
8010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8011 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8014 case nir_intrinsic_load_draw_id
: {
8015 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8016 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8019 case nir_intrinsic_load_invocation_id
: {
8020 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8023 if (ctx
->options
->chip_class
>= GFX10
)
8024 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8026 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8027 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8028 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8029 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8031 unreachable("Unsupported stage for load_invocation_id");
8036 case nir_intrinsic_load_primitive_id
: {
8037 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8039 switch (ctx
->shader
->info
.stage
) {
8040 case MESA_SHADER_GEOMETRY
:
8041 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8043 case MESA_SHADER_TESS_CTRL
:
8044 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8046 case MESA_SHADER_TESS_EVAL
:
8047 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8050 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8055 case nir_intrinsic_load_patch_vertices_in
: {
8056 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8057 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8059 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8060 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8063 case nir_intrinsic_emit_vertex_with_counter
: {
8064 visit_emit_vertex_with_counter(ctx
, instr
);
8067 case nir_intrinsic_end_primitive_with_counter
: {
8068 unsigned stream
= nir_intrinsic_stream_id(instr
);
8069 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8072 case nir_intrinsic_set_vertex_count
: {
8073 /* unused, the HW keeps track of this for us */
8077 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8078 nir_print_instr(&instr
->instr
, stderr
);
8079 fprintf(stderr
, "\n");
8087 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8088 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8089 enum glsl_base_type
*stype
)
8091 nir_deref_instr
*texture_deref_instr
= NULL
;
8092 nir_deref_instr
*sampler_deref_instr
= NULL
;
8095 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8096 switch (instr
->src
[i
].src_type
) {
8097 case nir_tex_src_texture_deref
:
8098 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8100 case nir_tex_src_sampler_deref
:
8101 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8103 case nir_tex_src_plane
:
8104 plane
= nir_src_as_int(instr
->src
[i
].src
);
8111 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8113 if (!sampler_deref_instr
)
8114 sampler_deref_instr
= texture_deref_instr
;
8117 assert(instr
->op
!= nir_texop_txf_ms
&&
8118 instr
->op
!= nir_texop_samples_identical
);
8119 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8120 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8121 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8122 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8123 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8124 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8126 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8129 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8131 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8132 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8133 Builder
bld(ctx
->program
, ctx
->block
);
8135 /* to avoid unnecessary moves, we split and recombine sampler and image */
8136 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8137 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8138 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8139 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8140 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8141 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8143 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8145 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8146 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8147 img
[0], img
[1], img
[2], img
[3],
8148 img
[4], img
[5], img
[6], img
[7]);
8149 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8150 samp
[0], samp
[1], samp
[2], samp
[3]);
8153 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8154 instr
->op
== nir_texop_samples_identical
))
8155 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8158 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8159 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8161 Builder
bld(ctx
->program
, ctx
->block
);
8163 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8164 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8165 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8167 Operand
neg_one(0xbf800000u
);
8168 Operand
one(0x3f800000u
);
8169 Operand
two(0x40000000u
);
8170 Operand
four(0x40800000u
);
8172 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8173 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8174 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8176 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8177 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8178 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8179 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8182 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8183 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8184 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8186 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8189 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8190 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8191 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8194 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8195 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8197 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8198 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8201 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8203 Builder
bld(ctx
->program
, ctx
->block
);
8204 Temp ma
, tc
, sc
, id
;
8207 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8209 // see comment in ac_prepare_cube_coords()
8210 if (ctx
->options
->chip_class
<= GFX8
)
8211 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8214 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8216 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8217 vop3a
->operands
[0] = Operand(ma
);
8218 vop3a
->abs
[0] = true;
8219 Temp invma
= bld
.tmp(v1
);
8220 vop3a
->definitions
[0] = Definition(invma
);
8221 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8223 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8225 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8227 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8229 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8231 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8234 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8235 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8237 for (unsigned i
= 0; i
< 2; i
++) {
8238 // see comment in ac_prepare_cube_coords()
8240 Temp deriv_sc
, deriv_tc
;
8241 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8242 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8244 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8246 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8247 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8248 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8249 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8250 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8251 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8252 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8255 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8256 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8260 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8267 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8269 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8271 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8272 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8275 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8276 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8277 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8281 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8283 Builder
bld(ctx
->program
, ctx
->block
);
8284 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8285 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8286 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8287 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8288 std::vector
<Temp
> coords
;
8289 std::vector
<Temp
> derivs
;
8290 nir_const_value
*sample_index_cv
= NULL
;
8291 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8292 enum glsl_base_type stype
;
8293 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8295 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8296 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8297 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8298 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8300 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8301 switch (instr
->src
[i
].src_type
) {
8302 case nir_tex_src_coord
: {
8303 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8304 for (unsigned i
= 0; i
< coord
.size(); i
++)
8305 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8308 case nir_tex_src_bias
:
8309 if (instr
->op
== nir_texop_txb
) {
8310 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8314 case nir_tex_src_lod
: {
8315 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8317 if (val
&& val
->f32
<= 0.0) {
8320 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8325 case nir_tex_src_comparator
:
8326 if (instr
->is_shadow
) {
8327 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8331 case nir_tex_src_offset
:
8332 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8333 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8336 case nir_tex_src_ddx
:
8337 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8340 case nir_tex_src_ddy
:
8341 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8344 case nir_tex_src_ms_index
:
8345 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8346 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8347 has_sample_index
= true;
8349 case nir_tex_src_texture_offset
:
8350 case nir_tex_src_sampler_offset
:
8356 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8357 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8359 if (instr
->op
== nir_texop_texture_samples
) {
8360 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8362 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8363 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8364 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8365 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8367 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8368 samples
, Operand(1u), bld
.scc(is_msaa
));
8372 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8373 aco_ptr
<Instruction
> tmp_instr
;
8374 Temp acc
, pack
= Temp();
8376 uint32_t pack_const
= 0;
8377 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8378 if (!const_offset
[i
])
8380 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8383 if (offset
.type() == RegType::sgpr
) {
8384 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8385 if (const_offset
[i
])
8388 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8389 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8392 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8395 if (pack
== Temp()) {
8398 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8402 if (pack_const
&& pack
!= Temp())
8403 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8405 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8406 if (const_offset
[i
])
8409 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8410 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8413 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8416 if (pack
== Temp()) {
8419 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8423 if (pack_const
&& pack
!= Temp())
8424 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8426 if (pack_const
&& pack
== Temp())
8427 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8428 else if (pack
== Temp())
8434 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8435 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8437 /* pack derivatives */
8438 if (has_ddx
|| has_ddy
) {
8439 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8440 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8441 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8442 derivs
= {ddy
, zero
, ddy
, zero
};
8444 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8445 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8446 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8447 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8452 if (instr
->coord_components
> 1 &&
8453 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8455 instr
->op
!= nir_texop_txf
)
8456 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8458 if (instr
->coord_components
> 2 &&
8459 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8460 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8461 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8462 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8464 instr
->op
!= nir_texop_txf
&&
8465 instr
->op
!= nir_texop_txf_ms
&&
8466 instr
->op
!= nir_texop_fragment_fetch
&&
8467 instr
->op
!= nir_texop_fragment_mask_fetch
)
8468 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8470 if (ctx
->options
->chip_class
== GFX9
&&
8471 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8472 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8473 assert(coords
.size() > 0 && coords
.size() < 3);
8475 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8476 Operand((uint32_t) 0) :
8477 Operand((uint32_t) 0x3f000000)));
8480 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8482 if (instr
->op
== nir_texop_samples_identical
)
8483 resource
= fmask_ptr
;
8485 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8486 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8487 instr
->op
!= nir_texop_txs
&&
8488 instr
->op
!= nir_texop_fragment_fetch
&&
8489 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8490 assert(has_sample_index
);
8491 Operand
op(sample_index
);
8492 if (sample_index_cv
)
8493 op
= Operand(sample_index_cv
->u32
);
8494 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8497 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8498 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8499 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8500 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8505 /* Build tex instruction */
8506 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8507 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8508 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8510 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8513 /* gather4 selects the component by dmask and always returns vec4 */
8514 if (instr
->op
== nir_texop_tg4
) {
8515 assert(instr
->dest
.ssa
.num_components
== 4);
8516 if (instr
->is_shadow
)
8519 dmask
= 1 << instr
->component
;
8520 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8521 tmp_dst
= bld
.tmp(v4
);
8522 } else if (instr
->op
== nir_texop_samples_identical
) {
8523 tmp_dst
= bld
.tmp(v1
);
8524 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8525 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8528 aco_ptr
<MIMG_instruction
> tex
;
8529 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8531 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8533 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8534 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8537 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8538 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8540 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8541 tex
->operands
[0] = Operand(resource
);
8542 tex
->operands
[1] = Operand(s4
); /* no sampler */
8543 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8544 if (ctx
->options
->chip_class
== GFX9
&&
8545 instr
->op
== nir_texop_txs
&&
8546 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8548 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8549 } else if (instr
->op
== nir_texop_query_levels
) {
8550 tex
->dmask
= 1 << 3;
8555 tex
->definitions
[0] = Definition(tmp_dst
);
8557 tex
->can_reorder
= true;
8558 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8561 /* divide 3rd value by 6 by multiplying with magic number */
8562 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8563 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8564 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8565 assert(instr
->dest
.ssa
.num_components
== 3);
8566 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8567 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8568 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8569 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8574 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8578 Temp tg4_compare_cube_wa64
= Temp();
8580 if (tg4_integer_workarounds
) {
8581 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8582 tex
->operands
[0] = Operand(resource
);
8583 tex
->operands
[1] = Operand(s4
); /* no sampler */
8584 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8588 Temp size
= bld
.tmp(v2
);
8589 tex
->definitions
[0] = Definition(size
);
8590 tex
->can_reorder
= true;
8591 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8592 emit_split_vector(ctx
, size
, size
.size());
8595 for (unsigned i
= 0; i
< 2; i
++) {
8596 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8597 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8598 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8599 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8602 Temp new_coords
[2] = {
8603 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8604 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8607 if (tg4_integer_cube_workaround
) {
8608 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8609 Temp desc
[resource
.size()];
8610 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8611 Format::PSEUDO
, 1, resource
.size())};
8612 split
->operands
[0] = Operand(resource
);
8613 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8614 desc
[i
] = bld
.tmp(s1
);
8615 split
->definitions
[i
] = Definition(desc
[i
]);
8617 ctx
->block
->instructions
.emplace_back(std::move(split
));
8619 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8620 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8621 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8624 if (stype
== GLSL_TYPE_UINT
) {
8625 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8626 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8627 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8628 bld
.scc(compare_cube_wa
));
8630 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8631 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8632 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8633 bld
.scc(compare_cube_wa
));
8635 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8636 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8638 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8640 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8641 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8642 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8644 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8645 Format::PSEUDO
, resource
.size(), 1)};
8646 for (unsigned i
= 0; i
< resource
.size(); i
++)
8647 vec
->operands
[i
] = Operand(desc
[i
]);
8648 resource
= bld
.tmp(resource
.regClass());
8649 vec
->definitions
[0] = Definition(resource
);
8650 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8652 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8653 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8654 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8655 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8657 coords
[0] = new_coords
[0];
8658 coords
[1] = new_coords
[1];
8661 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8662 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8664 assert(coords
.size() == 1);
8665 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8669 op
= aco_opcode::buffer_load_format_x
; break;
8671 op
= aco_opcode::buffer_load_format_xy
; break;
8673 op
= aco_opcode::buffer_load_format_xyz
; break;
8675 op
= aco_opcode::buffer_load_format_xyzw
; break;
8677 unreachable("Tex instruction loads more than 4 components.");
8680 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8681 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8684 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8686 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8687 mubuf
->operands
[0] = Operand(resource
);
8688 mubuf
->operands
[1] = Operand(coords
[0]);
8689 mubuf
->operands
[2] = Operand((uint32_t) 0);
8690 mubuf
->definitions
[0] = Definition(tmp_dst
);
8691 mubuf
->idxen
= true;
8692 mubuf
->can_reorder
= true;
8693 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8695 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8699 /* gather MIMG address components */
8700 std::vector
<Temp
> args
;
8702 args
.emplace_back(offset
);
8704 args
.emplace_back(bias
);
8706 args
.emplace_back(compare
);
8708 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8710 args
.insert(args
.end(), coords
.begin(), coords
.end());
8711 if (has_sample_index
)
8712 args
.emplace_back(sample_index
);
8714 args
.emplace_back(lod
);
8716 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8717 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8718 vec
->definitions
[0] = Definition(arg
);
8719 for (unsigned i
= 0; i
< args
.size(); i
++)
8720 vec
->operands
[i
] = Operand(args
[i
]);
8721 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8724 if (instr
->op
== nir_texop_txf
||
8725 instr
->op
== nir_texop_txf_ms
||
8726 instr
->op
== nir_texop_samples_identical
||
8727 instr
->op
== nir_texop_fragment_fetch
||
8728 instr
->op
== nir_texop_fragment_mask_fetch
) {
8729 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8730 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8731 tex
->operands
[0] = Operand(resource
);
8732 tex
->operands
[1] = Operand(s4
); /* no sampler */
8733 tex
->operands
[2] = Operand(arg
);
8738 tex
->definitions
[0] = Definition(tmp_dst
);
8739 tex
->can_reorder
= true;
8740 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8742 if (instr
->op
== nir_texop_samples_identical
) {
8743 assert(dmask
== 1 && dst
.regClass() == v1
);
8744 assert(dst
.id() != tmp_dst
.id());
8746 Temp tmp
= bld
.tmp(bld
.lm
);
8747 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8748 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8751 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8756 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8757 aco_opcode opcode
= aco_opcode::image_sample
;
8758 if (has_offset
) { /* image_sample_*_o */
8760 opcode
= aco_opcode::image_sample_c_o
;
8762 opcode
= aco_opcode::image_sample_c_d_o
;
8764 opcode
= aco_opcode::image_sample_c_b_o
;
8766 opcode
= aco_opcode::image_sample_c_lz_o
;
8768 opcode
= aco_opcode::image_sample_c_l_o
;
8770 opcode
= aco_opcode::image_sample_o
;
8772 opcode
= aco_opcode::image_sample_d_o
;
8774 opcode
= aco_opcode::image_sample_b_o
;
8776 opcode
= aco_opcode::image_sample_lz_o
;
8778 opcode
= aco_opcode::image_sample_l_o
;
8780 } else { /* no offset */
8782 opcode
= aco_opcode::image_sample_c
;
8784 opcode
= aco_opcode::image_sample_c_d
;
8786 opcode
= aco_opcode::image_sample_c_b
;
8788 opcode
= aco_opcode::image_sample_c_lz
;
8790 opcode
= aco_opcode::image_sample_c_l
;
8792 opcode
= aco_opcode::image_sample
;
8794 opcode
= aco_opcode::image_sample_d
;
8796 opcode
= aco_opcode::image_sample_b
;
8798 opcode
= aco_opcode::image_sample_lz
;
8800 opcode
= aco_opcode::image_sample_l
;
8804 if (instr
->op
== nir_texop_tg4
) {
8806 opcode
= aco_opcode::image_gather4_lz_o
;
8808 opcode
= aco_opcode::image_gather4_c_lz_o
;
8810 opcode
= aco_opcode::image_gather4_lz
;
8812 opcode
= aco_opcode::image_gather4_c_lz
;
8814 } else if (instr
->op
== nir_texop_lod
) {
8815 opcode
= aco_opcode::image_get_lod
;
8818 /* we don't need the bias, sample index, compare value or offset to be
8819 * computed in WQM but if the p_create_vector copies the coordinates, then it
8820 * needs to be in WQM */
8821 if (ctx
->stage
== fragment_fs
&&
8822 !has_derivs
&& !has_lod
&& !level_zero
&&
8823 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8824 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8825 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8827 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8828 tex
->operands
[0] = Operand(resource
);
8829 tex
->operands
[1] = Operand(sampler
);
8830 tex
->operands
[2] = Operand(arg
);
8834 tex
->definitions
[0] = Definition(tmp_dst
);
8835 tex
->can_reorder
= true;
8836 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8838 if (tg4_integer_cube_workaround
) {
8839 assert(tmp_dst
.id() != dst
.id());
8840 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8842 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8844 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8845 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8847 if (stype
== GLSL_TYPE_UINT
)
8848 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8850 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8851 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8853 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8854 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8855 val
[0], val
[1], val
[2], val
[3]);
8857 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8858 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8863 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8865 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8866 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8867 return Operand(tmp
.regClass());
8869 return Operand(tmp
);
8872 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8874 aco_ptr
<Pseudo_instruction
> phi
;
8875 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8876 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8878 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8879 logical
|= ctx
->block
->kind
& block_kind_merge
;
8880 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8882 /* we want a sorted list of sources, since the predecessor list is also sorted */
8883 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8884 nir_foreach_phi_src(src
, instr
)
8885 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8887 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8888 unsigned num_operands
= 0;
8889 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8890 unsigned num_defined
= 0;
8891 unsigned cur_pred_idx
= 0;
8892 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8893 if (cur_pred_idx
< preds
.size()) {
8894 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8895 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8896 unsigned skipped
= 0;
8897 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8899 if (cur_pred_idx
+ skipped
< preds
.size()) {
8900 for (unsigned i
= 0; i
< skipped
; i
++)
8901 operands
[num_operands
++] = Operand(dst
.regClass());
8902 cur_pred_idx
+= skipped
;
8907 /* Handle missing predecessors at the end. This shouldn't happen with loop
8908 * headers and we can't ignore these sources for loop header phis. */
8909 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8912 Operand op
= get_phi_operand(ctx
, src
.second
);
8913 operands
[num_operands
++] = op
;
8914 num_defined
+= !op
.isUndefined();
8916 /* handle block_kind_continue_or_break at loop exit blocks */
8917 while (cur_pred_idx
++ < preds
.size())
8918 operands
[num_operands
++] = Operand(dst
.regClass());
8920 /* If the loop ends with a break, still add a linear continue edge in case
8921 * that break is divergent or continue_or_break is used. We'll either remove
8922 * this operand later in visit_loop() if it's not necessary or replace the
8923 * undef with something correct. */
8924 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8925 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8926 nir_block
*last
= nir_loop_last_block(loop
);
8927 if (last
->successors
[0] != instr
->instr
.block
)
8928 operands
[num_operands
++] = Operand(RegClass());
8931 if (num_defined
== 0) {
8932 Builder
bld(ctx
->program
, ctx
->block
);
8933 if (dst
.regClass() == s1
) {
8934 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8935 } else if (dst
.regClass() == v1
) {
8936 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8938 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8939 for (unsigned i
= 0; i
< dst
.size(); i
++)
8940 vec
->operands
[i
] = Operand(0u);
8941 vec
->definitions
[0] = Definition(dst
);
8942 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8947 /* we can use a linear phi in some cases if one src is undef */
8948 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8949 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8951 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8952 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8953 assert(invert
->kind
& block_kind_invert
);
8955 unsigned then_block
= invert
->linear_preds
[0];
8957 Block
* insert_block
= NULL
;
8958 for (unsigned i
= 0; i
< num_operands
; i
++) {
8959 Operand op
= operands
[i
];
8960 if (op
.isUndefined())
8962 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8963 phi
->operands
[0] = op
;
8966 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8967 phi
->operands
[1] = Operand(dst
.regClass());
8968 phi
->definitions
[0] = Definition(dst
);
8969 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8973 /* try to scalarize vector phis */
8974 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8975 // TODO: scalarize linear phis on divergent ifs
8976 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8977 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8978 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8979 Operand src
= operands
[i
];
8980 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8981 can_scalarize
= false;
8983 if (can_scalarize
) {
8984 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8985 assert(dst
.size() % num_components
== 0);
8986 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8988 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8989 for (unsigned k
= 0; k
< num_components
; k
++) {
8990 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8991 for (unsigned i
= 0; i
< num_operands
; i
++) {
8992 Operand src
= operands
[i
];
8993 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8995 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8996 phi
->definitions
[0] = Definition(phi_dst
);
8997 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8998 new_vec
[k
] = phi_dst
;
8999 vec
->operands
[k
] = Operand(phi_dst
);
9001 vec
->definitions
[0] = Definition(dst
);
9002 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9003 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9008 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9009 for (unsigned i
= 0; i
< num_operands
; i
++)
9010 phi
->operands
[i
] = operands
[i
];
9011 phi
->definitions
[0] = Definition(dst
);
9012 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9016 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9018 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9020 assert(dst
.type() == RegType::sgpr
);
9022 if (dst
.size() == 1) {
9023 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9025 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9026 for (unsigned i
= 0; i
< dst
.size(); i
++)
9027 vec
->operands
[i
] = Operand(0u);
9028 vec
->definitions
[0] = Definition(dst
);
9029 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9033 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9035 Builder
bld(ctx
->program
, ctx
->block
);
9036 Block
*logical_target
;
9037 append_logical_end(ctx
->block
);
9038 unsigned idx
= ctx
->block
->index
;
9040 switch (instr
->type
) {
9041 case nir_jump_break
:
9042 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9043 add_logical_edge(idx
, logical_target
);
9044 ctx
->block
->kind
|= block_kind_break
;
9046 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9047 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9048 /* uniform break - directly jump out of the loop */
9049 ctx
->block
->kind
|= block_kind_uniform
;
9050 ctx
->cf_info
.has_branch
= true;
9051 bld
.branch(aco_opcode::p_branch
);
9052 add_linear_edge(idx
, logical_target
);
9055 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9056 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9058 case nir_jump_continue
:
9059 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9060 add_logical_edge(idx
, logical_target
);
9061 ctx
->block
->kind
|= block_kind_continue
;
9063 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9064 /* for potential uniform breaks after this continue,
9065 we must ensure that they are handled correctly */
9066 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9067 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9068 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9070 /* uniform continue - directly jump to the loop header */
9071 ctx
->block
->kind
|= block_kind_uniform
;
9072 ctx
->cf_info
.has_branch
= true;
9073 bld
.branch(aco_opcode::p_branch
);
9074 add_linear_edge(idx
, logical_target
);
9079 fprintf(stderr
, "Unknown NIR jump instr: ");
9080 nir_print_instr(&instr
->instr
, stderr
);
9081 fprintf(stderr
, "\n");
9085 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9086 ctx
->cf_info
.exec_potentially_empty_break
= true;
9087 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9090 /* remove critical edges from linear CFG */
9091 bld
.branch(aco_opcode::p_branch
);
9092 Block
* break_block
= ctx
->program
->create_and_insert_block();
9093 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9094 break_block
->kind
|= block_kind_uniform
;
9095 add_linear_edge(idx
, break_block
);
9096 /* the loop_header pointer might be invalidated by this point */
9097 if (instr
->type
== nir_jump_continue
)
9098 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9099 add_linear_edge(break_block
->index
, logical_target
);
9100 bld
.reset(break_block
);
9101 bld
.branch(aco_opcode::p_branch
);
9103 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9104 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9105 add_linear_edge(idx
, continue_block
);
9106 append_logical_start(continue_block
);
9107 ctx
->block
= continue_block
;
9111 void visit_block(isel_context
*ctx
, nir_block
*block
)
9113 nir_foreach_instr(instr
, block
) {
9114 switch (instr
->type
) {
9115 case nir_instr_type_alu
:
9116 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9118 case nir_instr_type_load_const
:
9119 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9121 case nir_instr_type_intrinsic
:
9122 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9124 case nir_instr_type_tex
:
9125 visit_tex(ctx
, nir_instr_as_tex(instr
));
9127 case nir_instr_type_phi
:
9128 visit_phi(ctx
, nir_instr_as_phi(instr
));
9130 case nir_instr_type_ssa_undef
:
9131 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9133 case nir_instr_type_deref
:
9135 case nir_instr_type_jump
:
9136 visit_jump(ctx
, nir_instr_as_jump(instr
));
9139 fprintf(stderr
, "Unknown NIR instr type: ");
9140 nir_print_instr(instr
, stderr
);
9141 fprintf(stderr
, "\n");
9146 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9147 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9152 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9153 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9155 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9156 RegClass rc
= vals
[0].regClass();
9158 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9160 unsigned next_pred
= 1;
9162 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9163 Block
& block
= ctx
->program
->blocks
[idx
];
9164 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9165 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9169 if (block
.kind
& block_kind_continue
) {
9170 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9175 bool all_same
= true;
9176 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9177 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9181 val
= vals
[block
.linear_preds
[0] - first
];
9183 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9184 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9185 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9186 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9187 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9188 phi
->definitions
[0] = Definition(val
.getTemp());
9189 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9191 vals
[idx
- first
] = val
;
9194 return vals
[last
- first
];
9197 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9199 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9200 append_logical_end(ctx
->block
);
9201 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9202 Builder
bld(ctx
->program
, ctx
->block
);
9203 bld
.branch(aco_opcode::p_branch
);
9204 unsigned loop_preheader_idx
= ctx
->block
->index
;
9206 Block loop_exit
= Block();
9207 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9208 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9210 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9211 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9212 loop_header
->kind
|= block_kind_loop_header
;
9213 add_edge(loop_preheader_idx
, loop_header
);
9214 ctx
->block
= loop_header
;
9216 /* emit loop body */
9217 unsigned loop_header_idx
= loop_header
->index
;
9218 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9219 append_logical_start(ctx
->block
);
9220 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9222 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9223 if (!ctx
->cf_info
.has_branch
) {
9224 append_logical_end(ctx
->block
);
9225 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9226 /* Discards can result in code running with an empty exec mask.
9227 * This would result in divergent breaks not ever being taken. As a
9228 * workaround, break the loop when the loop mask is empty instead of
9229 * always continuing. */
9230 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9231 unsigned block_idx
= ctx
->block
->index
;
9233 /* create helper blocks to avoid critical edges */
9234 Block
*break_block
= ctx
->program
->create_and_insert_block();
9235 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9236 break_block
->kind
= block_kind_uniform
;
9237 bld
.reset(break_block
);
9238 bld
.branch(aco_opcode::p_branch
);
9239 add_linear_edge(block_idx
, break_block
);
9240 add_linear_edge(break_block
->index
, &loop_exit
);
9242 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9243 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9244 continue_block
->kind
= block_kind_uniform
;
9245 bld
.reset(continue_block
);
9246 bld
.branch(aco_opcode::p_branch
);
9247 add_linear_edge(block_idx
, continue_block
);
9248 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9250 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9251 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9252 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9254 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9255 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9256 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9258 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9261 bld
.reset(ctx
->block
);
9262 bld
.branch(aco_opcode::p_branch
);
9265 /* Fixup phis in loop header from unreachable blocks.
9266 * has_branch/has_divergent_branch also indicates if the loop ends with a
9267 * break/continue instruction, but we don't emit those if unreachable=true */
9269 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9270 bool linear
= ctx
->cf_info
.has_branch
;
9271 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9272 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9273 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9274 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9275 /* the last operand should be the one that needs to be removed */
9276 instr
->operands
.pop_back();
9277 } else if (!is_phi(instr
)) {
9283 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9284 * and the previous one shouldn't both happen at once because a break in the
9285 * merge block would get CSE'd */
9286 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9287 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9288 Operand vals
[num_vals
];
9289 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9290 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9291 if (ctx
->cf_info
.has_branch
)
9292 instr
->operands
.pop_back();
9294 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9295 } else if (!is_phi(instr
)) {
9301 ctx
->cf_info
.has_branch
= false;
9303 // TODO: if the loop has not a single exit, we must add one °°
9304 /* emit loop successor block */
9305 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9306 append_logical_start(ctx
->block
);
9309 // TODO: check if it is beneficial to not branch on continues
9310 /* trim linear phis in loop header */
9311 for (auto&& instr
: loop_entry
->instructions
) {
9312 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9313 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9314 new_phi
->definitions
[0] = instr
->definitions
[0];
9315 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9316 new_phi
->operands
[i
] = instr
->operands
[i
];
9317 /* check that the remaining operands are all the same */
9318 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9319 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9320 instr
.swap(new_phi
);
9321 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9330 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9334 append_logical_end(ctx
->block
);
9335 ctx
->block
->kind
|= block_kind_branch
;
9337 /* branch to linear then block */
9338 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9339 aco_ptr
<Pseudo_branch_instruction
> branch
;
9340 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9341 branch
->operands
[0] = Operand(cond
);
9342 ctx
->block
->instructions
.push_back(std::move(branch
));
9344 ic
->BB_if_idx
= ctx
->block
->index
;
9345 ic
->BB_invert
= Block();
9346 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9347 /* Invert blocks are intentionally not marked as top level because they
9348 * are not part of the logical cfg. */
9349 ic
->BB_invert
.kind
|= block_kind_invert
;
9350 ic
->BB_endif
= Block();
9351 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9352 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9354 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9355 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9356 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9357 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9358 ctx
->cf_info
.parent_if
.is_divergent
= true;
9360 /* divergent branches use cbranch_execz */
9361 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9362 ctx
->cf_info
.exec_potentially_empty_break
= false;
9363 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9365 /** emit logical then block */
9366 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9367 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9368 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9369 ctx
->block
= BB_then_logical
;
9370 append_logical_start(BB_then_logical
);
9373 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9375 Block
*BB_then_logical
= ctx
->block
;
9376 append_logical_end(BB_then_logical
);
9377 /* branch from logical then block to invert block */
9378 aco_ptr
<Pseudo_branch_instruction
> branch
;
9379 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9380 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9381 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9382 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9383 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9384 BB_then_logical
->kind
|= block_kind_uniform
;
9385 assert(!ctx
->cf_info
.has_branch
);
9386 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9387 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9389 /** emit linear then block */
9390 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9391 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9392 BB_then_linear
->kind
|= block_kind_uniform
;
9393 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9394 /* branch from linear then block to invert block */
9395 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9396 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9397 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9399 /** emit invert merge block */
9400 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9401 ic
->invert_idx
= ctx
->block
->index
;
9403 /* branch to linear else block (skip else) */
9404 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9405 branch
->operands
[0] = Operand(ic
->cond
);
9406 ctx
->block
->instructions
.push_back(std::move(branch
));
9408 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9409 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9410 ic
->exec_potentially_empty_break_depth_old
=
9411 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9412 /* divergent branches use cbranch_execz */
9413 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9414 ctx
->cf_info
.exec_potentially_empty_break
= false;
9415 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9417 /** emit logical else block */
9418 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9419 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9420 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9421 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9422 ctx
->block
= BB_else_logical
;
9423 append_logical_start(BB_else_logical
);
9426 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9428 Block
*BB_else_logical
= ctx
->block
;
9429 append_logical_end(BB_else_logical
);
9431 /* branch from logical else block to endif block */
9432 aco_ptr
<Pseudo_branch_instruction
> branch
;
9433 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9434 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9435 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9436 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9437 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9438 BB_else_logical
->kind
|= block_kind_uniform
;
9440 assert(!ctx
->cf_info
.has_branch
);
9441 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9444 /** emit linear else block */
9445 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9446 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9447 BB_else_linear
->kind
|= block_kind_uniform
;
9448 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9450 /* branch from linear else block to endif block */
9451 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9452 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9453 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9456 /** emit endif merge block */
9457 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9458 append_logical_start(ctx
->block
);
9461 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9462 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9463 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9464 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9465 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9466 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9467 !ctx
->cf_info
.parent_if
.is_divergent
) {
9468 ctx
->cf_info
.exec_potentially_empty_break
= false;
9469 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9471 /* uniform control flow never has an empty exec-mask */
9472 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9473 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9474 ctx
->cf_info
.exec_potentially_empty_break
= false;
9475 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9479 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9481 assert(cond
.regClass() == s1
);
9483 append_logical_end(ctx
->block
);
9484 ctx
->block
->kind
|= block_kind_uniform
;
9486 aco_ptr
<Pseudo_branch_instruction
> branch
;
9487 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9488 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9489 branch
->operands
[0] = Operand(cond
);
9490 branch
->operands
[0].setFixed(scc
);
9491 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9493 ic
->BB_if_idx
= ctx
->block
->index
;
9494 ic
->BB_endif
= Block();
9495 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9496 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9498 ctx
->cf_info
.has_branch
= false;
9499 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9501 /** emit then block */
9502 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9503 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9504 add_edge(ic
->BB_if_idx
, BB_then
);
9505 append_logical_start(BB_then
);
9506 ctx
->block
= BB_then
;
9509 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9511 Block
*BB_then
= ctx
->block
;
9513 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9514 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9516 if (!ic
->uniform_has_then_branch
) {
9517 append_logical_end(BB_then
);
9518 /* branch from then block to endif block */
9519 aco_ptr
<Pseudo_branch_instruction
> branch
;
9520 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9521 BB_then
->instructions
.emplace_back(std::move(branch
));
9522 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9523 if (!ic
->then_branch_divergent
)
9524 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9525 BB_then
->kind
|= block_kind_uniform
;
9528 ctx
->cf_info
.has_branch
= false;
9529 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9531 /** emit else block */
9532 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9533 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9534 add_edge(ic
->BB_if_idx
, BB_else
);
9535 append_logical_start(BB_else
);
9536 ctx
->block
= BB_else
;
9539 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9541 Block
*BB_else
= ctx
->block
;
9543 if (!ctx
->cf_info
.has_branch
) {
9544 append_logical_end(BB_else
);
9545 /* branch from then block to endif block */
9546 aco_ptr
<Pseudo_branch_instruction
> branch
;
9547 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9548 BB_else
->instructions
.emplace_back(std::move(branch
));
9549 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9550 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9551 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9552 BB_else
->kind
|= block_kind_uniform
;
9555 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9556 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9558 /** emit endif merge block */
9559 if (!ctx
->cf_info
.has_branch
) {
9560 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9561 append_logical_start(ctx
->block
);
9565 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9567 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9568 Builder
bld(ctx
->program
, ctx
->block
);
9569 aco_ptr
<Pseudo_branch_instruction
> branch
;
9572 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9574 * Uniform conditionals are represented in the following way*) :
9576 * The linear and logical CFG:
9579 * BB_THEN (logical) BB_ELSE (logical)
9583 * *) Exceptions may be due to break and continue statements within loops
9584 * If a break/continue happens within uniform control flow, it branches
9585 * to the loop exit/entry block. Otherwise, it branches to the next
9589 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9590 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9591 cond
= bool_to_scalar_condition(ctx
, cond
);
9593 begin_uniform_if_then(ctx
, &ic
, cond
);
9594 visit_cf_list(ctx
, &if_stmt
->then_list
);
9596 begin_uniform_if_else(ctx
, &ic
);
9597 visit_cf_list(ctx
, &if_stmt
->else_list
);
9599 end_uniform_if(ctx
, &ic
);
9601 return !ctx
->cf_info
.has_branch
;
9602 } else { /* non-uniform condition */
9604 * To maintain a logical and linear CFG without critical edges,
9605 * non-uniform conditionals are represented in the following way*) :
9610 * BB_THEN (logical) BB_THEN (linear)
9612 * BB_INVERT (linear)
9614 * BB_ELSE (logical) BB_ELSE (linear)
9621 * BB_THEN (logical) BB_ELSE (logical)
9625 * *) Exceptions may be due to break and continue statements within loops
9628 begin_divergent_if_then(ctx
, &ic
, cond
);
9629 visit_cf_list(ctx
, &if_stmt
->then_list
);
9631 begin_divergent_if_else(ctx
, &ic
);
9632 visit_cf_list(ctx
, &if_stmt
->else_list
);
9634 end_divergent_if(ctx
, &ic
);
9640 static bool visit_cf_list(isel_context
*ctx
,
9641 struct exec_list
*list
)
9643 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9644 switch (node
->type
) {
9645 case nir_cf_node_block
:
9646 visit_block(ctx
, nir_cf_node_as_block(node
));
9648 case nir_cf_node_if
:
9649 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9652 case nir_cf_node_loop
:
9653 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9656 unreachable("unimplemented cf list type");
9662 static void create_null_export(isel_context
*ctx
)
9664 /* Some shader stages always need to have exports.
9665 * So when there is none, we need to add a null export.
9668 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9669 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9670 Builder
bld(ctx
->program
, ctx
->block
);
9671 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9672 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9675 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9677 assert(ctx
->stage
== vertex_vs
||
9678 ctx
->stage
== tess_eval_vs
||
9679 ctx
->stage
== gs_copy_vs
||
9680 ctx
->stage
== ngg_vertex_gs
||
9681 ctx
->stage
== ngg_tess_eval_gs
);
9683 int offset
= (ctx
->stage
& sw_tes
)
9684 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9685 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9686 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9687 if (!is_pos
&& !mask
)
9689 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9691 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9692 exp
->enabled_mask
= mask
;
9693 for (unsigned i
= 0; i
< 4; ++i
) {
9694 if (mask
& (1 << i
))
9695 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9697 exp
->operands
[i
] = Operand(v1
);
9699 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9700 * Setting valid_mask=1 prevents it and has no other effect.
9702 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9704 exp
->compressed
= false;
9706 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9708 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9709 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9714 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9716 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9717 exp
->enabled_mask
= 0;
9718 for (unsigned i
= 0; i
< 4; ++i
)
9719 exp
->operands
[i
] = Operand(v1
);
9720 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9721 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9722 exp
->enabled_mask
|= 0x1;
9724 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9725 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9726 exp
->enabled_mask
|= 0x4;
9728 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9729 if (ctx
->options
->chip_class
< GFX9
) {
9730 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9731 exp
->enabled_mask
|= 0x8;
9733 Builder
bld(ctx
->program
, ctx
->block
);
9735 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9736 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9737 if (exp
->operands
[2].isTemp())
9738 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9740 exp
->operands
[2] = Operand(out
);
9741 exp
->enabled_mask
|= 0x4;
9744 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9746 exp
->compressed
= false;
9747 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9748 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9751 static void create_export_phis(isel_context
*ctx
)
9753 /* Used when exports are needed, but the output temps are defined in a preceding block.
9754 * This function will set up phis in order to access the outputs in the next block.
9757 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9758 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9759 ctx
->block
->instructions
.pop_back();
9761 Builder
bld(ctx
->program
, ctx
->block
);
9763 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9764 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9765 for (unsigned i
= 0; i
< 4; ++i
) {
9766 if (!(mask
& (1 << i
)))
9769 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9770 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9771 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9775 bld
.insert(std::move(logical_start
));
9778 static void create_vs_exports(isel_context
*ctx
)
9780 assert(ctx
->stage
== vertex_vs
||
9781 ctx
->stage
== tess_eval_vs
||
9782 ctx
->stage
== gs_copy_vs
||
9783 ctx
->stage
== ngg_vertex_gs
||
9784 ctx
->stage
== ngg_tess_eval_gs
);
9786 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9787 ? &ctx
->program
->info
->tes
.outinfo
9788 : &ctx
->program
->info
->vs
.outinfo
;
9790 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9791 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9792 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9795 if (ctx
->options
->key
.has_multiview_view_index
) {
9796 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9797 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9800 /* the order these position exports are created is important */
9802 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9803 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9804 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9805 exported_pos
= true;
9807 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9808 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9809 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9810 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9812 if (ctx
->export_clip_dists
) {
9813 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9814 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9815 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9816 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9819 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9820 if (i
< VARYING_SLOT_VAR0
&&
9821 i
!= VARYING_SLOT_LAYER
&&
9822 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9825 export_vs_varying(ctx
, i
, false, NULL
);
9829 create_null_export(ctx
);
9832 static bool export_fs_mrt_z(isel_context
*ctx
)
9834 Builder
bld(ctx
->program
, ctx
->block
);
9835 unsigned enabled_channels
= 0;
9839 for (unsigned i
= 0; i
< 4; ++i
) {
9840 values
[i
] = Operand(v1
);
9843 /* Both stencil and sample mask only need 16-bits. */
9844 if (!ctx
->program
->info
->ps
.writes_z
&&
9845 (ctx
->program
->info
->ps
.writes_stencil
||
9846 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9847 compr
= true; /* COMPR flag */
9849 if (ctx
->program
->info
->ps
.writes_stencil
) {
9850 /* Stencil should be in X[23:16]. */
9851 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9852 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9853 enabled_channels
|= 0x3;
9856 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9857 /* SampleMask should be in Y[15:0]. */
9858 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9859 enabled_channels
|= 0xc;
9862 if (ctx
->program
->info
->ps
.writes_z
) {
9863 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9864 enabled_channels
|= 0x1;
9867 if (ctx
->program
->info
->ps
.writes_stencil
) {
9868 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9869 enabled_channels
|= 0x2;
9872 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9873 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9874 enabled_channels
|= 0x4;
9878 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9879 * writemask component.
9881 if (ctx
->options
->chip_class
== GFX6
&&
9882 ctx
->options
->family
!= CHIP_OLAND
&&
9883 ctx
->options
->family
!= CHIP_HAINAN
) {
9884 enabled_channels
|= 0x1;
9887 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9888 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9893 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9895 Builder
bld(ctx
->program
, ctx
->block
);
9896 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9899 for (unsigned i
= 0; i
< 4; ++i
) {
9900 if (write_mask
& (1 << i
)) {
9901 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9903 values
[i
] = Operand(v1
);
9907 unsigned target
, col_format
;
9908 unsigned enabled_channels
= 0;
9909 aco_opcode compr_op
= (aco_opcode
)0;
9911 slot
-= FRAG_RESULT_DATA0
;
9912 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9913 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9915 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9916 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9920 case V_028714_SPI_SHADER_ZERO
:
9921 enabled_channels
= 0; /* writemask */
9922 target
= V_008DFC_SQ_EXP_NULL
;
9925 case V_028714_SPI_SHADER_32_R
:
9926 enabled_channels
= 1;
9929 case V_028714_SPI_SHADER_32_GR
:
9930 enabled_channels
= 0x3;
9933 case V_028714_SPI_SHADER_32_AR
:
9934 if (ctx
->options
->chip_class
>= GFX10
) {
9935 /* Special case: on GFX10, the outputs are different for 32_AR */
9936 enabled_channels
= 0x3;
9937 values
[1] = values
[3];
9938 values
[3] = Operand(v1
);
9940 enabled_channels
= 0x9;
9944 case V_028714_SPI_SHADER_FP16_ABGR
:
9945 enabled_channels
= 0x5;
9946 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9949 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9950 enabled_channels
= 0x5;
9951 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9954 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9955 enabled_channels
= 0x5;
9956 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9959 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9960 enabled_channels
= 0x5;
9961 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9962 if (is_int8
|| is_int10
) {
9964 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9965 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9967 for (unsigned i
= 0; i
< 4; i
++) {
9968 if ((write_mask
>> i
) & 1) {
9969 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9970 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9978 case V_028714_SPI_SHADER_SINT16_ABGR
:
9979 enabled_channels
= 0x5;
9980 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9981 if (is_int8
|| is_int10
) {
9983 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9984 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9985 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9986 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9988 for (unsigned i
= 0; i
< 4; i
++) {
9989 if ((write_mask
>> i
) & 1) {
9990 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9991 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9993 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9994 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10001 case V_028714_SPI_SHADER_32_ABGR
:
10002 enabled_channels
= 0xF;
10009 if (target
== V_008DFC_SQ_EXP_NULL
)
10012 if ((bool) compr_op
) {
10013 for (int i
= 0; i
< 2; i
++) {
10014 /* check if at least one of the values to be compressed is enabled */
10015 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10017 enabled_channels
|= enabled
<< (i
*2);
10018 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10019 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10020 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10022 values
[i
] = Operand(v1
);
10025 values
[2] = Operand(v1
);
10026 values
[3] = Operand(v1
);
10028 for (int i
= 0; i
< 4; i
++)
10029 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10032 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10033 enabled_channels
, target
, (bool) compr_op
);
10037 static void create_fs_exports(isel_context
*ctx
)
10039 bool exported
= false;
10041 /* Export depth, stencil and sample mask. */
10042 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10043 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10044 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10045 exported
|= export_fs_mrt_z(ctx
);
10047 /* Export all color render targets. */
10048 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10049 if (ctx
->outputs
.mask
[i
])
10050 exported
|= export_fs_mrt_color(ctx
, i
);
10053 create_null_export(ctx
);
10056 static void write_tcs_tess_factors(isel_context
*ctx
)
10058 unsigned outer_comps
;
10059 unsigned inner_comps
;
10061 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10078 Builder
bld(ctx
->program
, ctx
->block
);
10080 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10081 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10082 bld
.sopp(aco_opcode::s_barrier
);
10084 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10085 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10087 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10088 if_context ic_invocation_id_is_zero
;
10089 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10090 bld
.reset(ctx
->block
);
10092 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10094 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10095 unsigned stride
= inner_comps
+ outer_comps
;
10096 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10100 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10102 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10104 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10105 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10106 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10108 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10109 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10111 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10112 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10113 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10114 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10117 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10118 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10119 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10120 unsigned tf_const_offset
= 0;
10122 if (ctx
->program
->chip_class
<= GFX8
) {
10123 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10124 if_context ic_rel_patch_id_is_zero
;
10125 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10126 bld
.reset(ctx
->block
);
10128 /* Store the dynamic HS control word. */
10129 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10130 bld
.mubuf(aco_opcode::buffer_store_dword
,
10131 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10132 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10133 /* disable_wqm */ false, /* glc */ true);
10134 tf_const_offset
+= 4;
10136 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10137 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10138 bld
.reset(ctx
->block
);
10141 assert(stride
== 2 || stride
== 4 || stride
== 6);
10142 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10143 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10145 /* Store to offchip for TES to read - only if TES reads them */
10146 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10147 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10148 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10150 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10151 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10153 if (likely(inner_comps
)) {
10154 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10155 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10159 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10160 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10163 static void emit_stream_output(isel_context
*ctx
,
10164 Temp
const *so_buffers
,
10165 Temp
const *so_write_offset
,
10166 const struct radv_stream_output
*output
)
10168 unsigned num_comps
= util_bitcount(output
->component_mask
);
10169 unsigned writemask
= (1 << num_comps
) - 1;
10170 unsigned loc
= output
->location
;
10171 unsigned buf
= output
->buffer
;
10173 assert(num_comps
&& num_comps
<= 4);
10174 if (!num_comps
|| num_comps
> 4)
10177 unsigned start
= ffs(output
->component_mask
) - 1;
10180 bool all_undef
= true;
10181 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10182 for (unsigned i
= 0; i
< num_comps
; i
++) {
10183 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10184 all_undef
= all_undef
&& !out
[i
].id();
10189 while (writemask
) {
10191 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10192 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10193 /* GFX6 doesn't support storing vec3, split it. */
10194 writemask
|= 1u << (start
+ 2);
10198 unsigned offset
= output
->offset
+ start
* 4;
10200 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10201 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10202 for (int i
= 0; i
< count
; ++i
)
10203 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10204 vec
->definitions
[0] = Definition(write_data
);
10205 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10210 opcode
= aco_opcode::buffer_store_dword
;
10213 opcode
= aco_opcode::buffer_store_dwordx2
;
10216 opcode
= aco_opcode::buffer_store_dwordx3
;
10219 opcode
= aco_opcode::buffer_store_dwordx4
;
10222 unreachable("Unsupported dword count.");
10225 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10226 store
->operands
[0] = Operand(so_buffers
[buf
]);
10227 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10228 store
->operands
[2] = Operand((uint32_t) 0);
10229 store
->operands
[3] = Operand(write_data
);
10230 if (offset
> 4095) {
10231 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10232 Builder
bld(ctx
->program
, ctx
->block
);
10233 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10235 store
->offset
= offset
;
10237 store
->offen
= true;
10239 store
->dlc
= false;
10241 store
->can_reorder
= true;
10242 ctx
->block
->instructions
.emplace_back(std::move(store
));
10246 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10248 Builder
bld(ctx
->program
, ctx
->block
);
10250 Temp so_buffers
[4];
10251 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10252 for (unsigned i
= 0; i
< 4; i
++) {
10253 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10257 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10258 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10261 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10262 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10264 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10266 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10269 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10271 bld
.reset(ctx
->block
);
10273 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10275 Temp so_write_offset
[4];
10277 for (unsigned i
= 0; i
< 4; i
++) {
10278 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10283 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10284 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10285 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10286 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10288 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10290 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10291 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10292 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10293 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10297 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10298 struct radv_stream_output
*output
=
10299 &ctx
->program
->info
->so
.outputs
[i
];
10300 if (stream
!= output
->stream
)
10303 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10306 begin_divergent_if_else(ctx
, &ic
);
10307 end_divergent_if(ctx
, &ic
);
10310 } /* end namespace */
10312 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10314 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10315 Builder
bld(ctx
->program
, ctx
->block
);
10316 constexpr unsigned hs_idx
= 1u;
10317 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10318 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10319 Operand((8u << 16) | (hs_idx
* 8u)));
10320 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10322 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10324 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10325 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10326 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10327 ls_has_nonzero_hs_threads
);
10328 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10329 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10330 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10331 ls_has_nonzero_hs_threads
);
10332 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10333 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10334 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10335 ls_has_nonzero_hs_threads
);
10337 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10338 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10339 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10342 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10344 /* Split all arguments except for the first (ring_offsets) and the last
10345 * (exec) so that the dead channels don't stay live throughout the program.
10347 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10348 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10349 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10350 startpgm
->definitions
[i
].regClass().size());
10355 void handle_bc_optimize(isel_context
*ctx
)
10357 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10358 Builder
bld(ctx
->program
, ctx
->block
);
10359 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10360 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10361 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10362 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10363 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10364 if (uses_center
&& uses_centroid
) {
10365 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10366 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10368 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10370 for (unsigned i
= 0; i
< 2; i
++) {
10371 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10372 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10373 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10374 persp_centroid
, persp_center
, sel
);
10376 ctx
->persp_centroid
= bld
.tmp(v2
);
10377 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10378 Operand(new_coord
[0]), Operand(new_coord
[1]));
10379 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10382 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10384 for (unsigned i
= 0; i
< 2; i
++) {
10385 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10386 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10387 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10388 linear_centroid
, linear_center
, sel
);
10390 ctx
->linear_centroid
= bld
.tmp(v2
);
10391 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10392 Operand(new_coord
[0]), Operand(new_coord
[1]));
10393 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10398 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10400 Program
*program
= ctx
->program
;
10402 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10404 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10405 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10406 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10407 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10408 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10410 program
->next_fp_mode
.must_flush_denorms32
=
10411 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10412 program
->next_fp_mode
.must_flush_denorms16_64
=
10413 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10414 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10416 program
->next_fp_mode
.care_about_round32
=
10417 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10419 program
->next_fp_mode
.care_about_round16_64
=
10420 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10421 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10423 /* default to preserving fp16 and fp64 denorms, since it's free */
10424 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10425 program
->next_fp_mode
.denorm16_64
= 0;
10427 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10429 /* preserving fp32 denorms is expensive, so only do it if asked */
10430 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10431 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10433 program
->next_fp_mode
.denorm32
= 0;
10435 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10436 program
->next_fp_mode
.round32
= fp_round_tz
;
10438 program
->next_fp_mode
.round32
= fp_round_ne
;
10440 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10441 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10443 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10445 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10448 void cleanup_cfg(Program
*program
)
10450 /* create linear_succs/logical_succs */
10451 for (Block
& BB
: program
->blocks
) {
10452 for (unsigned idx
: BB
.linear_preds
)
10453 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10454 for (unsigned idx
: BB
.logical_preds
)
10455 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10459 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10461 Builder
bld(ctx
->program
, ctx
->block
);
10463 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10464 Temp count
= i
== 0
10465 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10466 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10467 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10469 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10472 if (ctx
->program
->wave_size
== 64) {
10473 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10474 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10475 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10477 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10478 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10484 bool ngg_early_prim_export(isel_context
*ctx
)
10486 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10490 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10492 Builder
bld(ctx
->program
, ctx
->block
);
10494 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10495 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10497 /* Get the id of the current wave within the threadgroup (workgroup) */
10498 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10499 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10501 /* Execute the following code only on the first wave (wave id 0),
10502 * use the SCC def to tell if the wave id is zero or not.
10504 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10506 begin_uniform_if_then(ctx
, &ic
, cond
);
10507 begin_uniform_if_else(ctx
, &ic
);
10508 bld
.reset(ctx
->block
);
10510 /* Number of vertices output by VS/TES */
10511 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10512 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10513 /* Number of primitives output by VS/TES */
10514 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10515 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10517 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10518 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10519 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10521 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10522 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10524 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10525 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10527 end_uniform_if(ctx
, &ic
);
10530 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10532 Builder
bld(ctx
->program
, ctx
->block
);
10534 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10535 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10538 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10541 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10542 assert(vtxindex
[i
].id());
10545 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10549 /* The initial edge flag is always false in tess eval shaders. */
10550 if (ctx
->stage
== ngg_vertex_gs
) {
10551 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10552 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10556 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10561 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10563 Builder
bld(ctx
->program
, ctx
->block
);
10564 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10566 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10567 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10568 false /* compressed */, true/* done */, false /* valid mask */);
10571 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10573 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10574 * These must always come before VS exports.
10576 * It is recommended to do these as early as possible. They can be at the beginning when
10577 * there is no SW GS and the shader doesn't write edge flags.
10581 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10582 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10584 Builder
bld(ctx
->program
, ctx
->block
);
10585 constexpr unsigned max_vertices_per_primitive
= 3;
10586 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10588 if (ctx
->stage
== ngg_vertex_gs
) {
10589 /* TODO: optimize for points & lines */
10590 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10591 if (ctx
->shader
->info
.tess
.point_mode
)
10592 num_vertices_per_primitive
= 1;
10593 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10594 num_vertices_per_primitive
= 2;
10596 unreachable("Unsupported NGG shader stage");
10599 Temp vtxindex
[max_vertices_per_primitive
];
10600 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10601 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10602 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10603 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10604 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10605 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10606 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10607 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10609 /* Export primitive data to the index buffer. */
10610 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10612 /* Export primitive ID. */
10613 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10614 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10615 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10616 Temp provoking_vtx_index
= vtxindex
[0];
10617 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10619 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10622 begin_divergent_if_else(ctx
, &ic
);
10623 end_divergent_if(ctx
, &ic
);
10626 void ngg_emit_nogs_output(isel_context
*ctx
)
10628 /* Emits NGG GS output, for stages that don't have SW GS. */
10631 Builder
bld(ctx
->program
, ctx
->block
);
10632 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10634 /* NGG streamout is currently disabled by default. */
10635 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10637 if (late_prim_export
) {
10638 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10639 create_export_phis(ctx
);
10640 /* Do what we need to do in the GS threads. */
10641 ngg_emit_nogs_gsthreads(ctx
);
10643 /* What comes next should be executed on ES threads. */
10644 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10645 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10646 bld
.reset(ctx
->block
);
10649 /* Export VS outputs */
10650 ctx
->block
->kind
|= block_kind_export_end
;
10651 create_vs_exports(ctx
);
10653 /* Export primitive ID */
10654 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10657 if (ctx
->stage
== ngg_vertex_gs
) {
10658 /* Wait for GS threads to store primitive ID in LDS. */
10659 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10660 bld
.sopp(aco_opcode::s_barrier
);
10662 /* Calculate LDS address where the GS threads stored the primitive ID. */
10663 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10664 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10665 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10666 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10667 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10668 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10670 /* Load primitive ID from LDS. */
10671 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10672 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10673 /* TES: Just use the patch ID as the primitive ID. */
10674 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10676 unreachable("unsupported NGG shader stage.");
10679 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10680 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10682 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10685 if (late_prim_export
) {
10686 begin_divergent_if_else(ctx
, &ic
);
10687 end_divergent_if(ctx
, &ic
);
10688 bld
.reset(ctx
->block
);
10692 void select_program(Program
*program
,
10693 unsigned shader_count
,
10694 struct nir_shader
*const *shaders
,
10695 ac_shader_config
* config
,
10696 struct radv_shader_args
*args
)
10698 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10699 if_context ic_merged_wave_info
;
10700 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10702 for (unsigned i
= 0; i
< shader_count
; i
++) {
10703 nir_shader
*nir
= shaders
[i
];
10704 init_context(&ctx
, nir
);
10706 setup_fp_mode(&ctx
, nir
);
10709 /* needs to be after init_context() for FS */
10710 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10711 append_logical_start(ctx
.block
);
10713 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10714 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10716 split_arguments(&ctx
, startpgm
);
10720 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10722 if (ngg_early_prim_export(&ctx
))
10723 ngg_emit_nogs_gsthreads(&ctx
);
10726 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10727 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10728 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10729 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10730 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10731 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10732 ctx
.stage
== tess_eval_geometry_gs
));
10734 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10735 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10736 if (check_merged_wave_info
) {
10737 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10738 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10742 Builder
bld(ctx
.program
, ctx
.block
);
10744 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10745 bld
.sopp(aco_opcode::s_barrier
);
10747 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10748 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10750 } else if (ctx
.stage
== geometry_gs
)
10751 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10753 if (ctx
.stage
== fragment_fs
)
10754 handle_bc_optimize(&ctx
);
10756 visit_cf_list(&ctx
, &func
->body
);
10758 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10759 emit_streamout(&ctx
, 0);
10761 if (ctx
.stage
& hw_vs
) {
10762 create_vs_exports(&ctx
);
10763 ctx
.block
->kind
|= block_kind_export_end
;
10764 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10765 ngg_emit_nogs_output(&ctx
);
10766 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10767 Builder
bld(ctx
.program
, ctx
.block
);
10768 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10769 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10770 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10771 write_tcs_tess_factors(&ctx
);
10774 if (ctx
.stage
== fragment_fs
) {
10775 create_fs_exports(&ctx
);
10776 ctx
.block
->kind
|= block_kind_export_end
;
10779 if (endif_merged_wave_info
) {
10780 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10781 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10784 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10785 ngg_emit_nogs_output(&ctx
);
10787 ralloc_free(ctx
.divergent_vals
);
10789 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10790 /* Outputs of the previous stage are inputs to the next stage */
10791 ctx
.inputs
= ctx
.outputs
;
10792 ctx
.outputs
= shader_io_state();
10796 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10798 append_logical_end(ctx
.block
);
10799 ctx
.block
->kind
|= block_kind_uniform
;
10800 Builder
bld(ctx
.program
, ctx
.block
);
10801 if (ctx
.program
->wb_smem_l1_on_end
)
10802 bld
.smem(aco_opcode::s_dcache_wb
, false);
10803 bld
.sopp(aco_opcode::s_endpgm
);
10805 cleanup_cfg(program
);
10808 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10809 ac_shader_config
* config
,
10810 struct radv_shader_args
*args
)
10812 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10814 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10815 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10816 program
->next_fp_mode
.must_flush_denorms32
= false;
10817 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10818 program
->next_fp_mode
.care_about_round32
= false;
10819 program
->next_fp_mode
.care_about_round16_64
= false;
10820 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10821 program
->next_fp_mode
.denorm32
= 0;
10822 program
->next_fp_mode
.round32
= fp_round_ne
;
10823 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10824 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10826 add_startpgm(&ctx
);
10827 append_logical_start(ctx
.block
);
10829 Builder
bld(ctx
.program
, ctx
.block
);
10831 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10833 Operand
stream_id(0u);
10834 if (args
->shader_info
->so
.num_outputs
)
10835 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10836 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10838 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10840 std::stack
<Block
> endif_blocks
;
10842 for (unsigned stream
= 0; stream
< 4; stream
++) {
10843 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10846 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10847 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10850 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10852 unsigned BB_if_idx
= ctx
.block
->index
;
10853 Block BB_endif
= Block();
10854 if (!stream_id
.isConstant()) {
10856 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10857 append_logical_end(ctx
.block
);
10858 ctx
.block
->kind
|= block_kind_uniform
;
10859 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10861 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10863 ctx
.block
= ctx
.program
->create_and_insert_block();
10864 add_edge(BB_if_idx
, ctx
.block
);
10865 bld
.reset(ctx
.block
);
10866 append_logical_start(ctx
.block
);
10869 unsigned offset
= 0;
10870 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10871 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10874 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10875 unsigned length
= util_last_bit(output_usage_mask
);
10876 for (unsigned j
= 0; j
< length
; ++j
) {
10877 if (!(output_usage_mask
& (1 << j
)))
10880 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10881 Temp voffset
= vtx_offset
;
10882 if (const_offset
>= 4096u) {
10883 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10884 const_offset
%= 4096u;
10887 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10888 mubuf
->definitions
[0] = bld
.def(v1
);
10889 mubuf
->operands
[0] = Operand(gsvs_ring
);
10890 mubuf
->operands
[1] = Operand(voffset
);
10891 mubuf
->operands
[2] = Operand(0u);
10892 mubuf
->offen
= true;
10893 mubuf
->offset
= const_offset
;
10896 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10897 mubuf
->barrier
= barrier_none
;
10898 mubuf
->can_reorder
= true;
10900 ctx
.outputs
.mask
[i
] |= 1 << j
;
10901 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10903 bld
.insert(std::move(mubuf
));
10909 if (args
->shader_info
->so
.num_outputs
) {
10910 emit_streamout(&ctx
, stream
);
10911 bld
.reset(ctx
.block
);
10915 create_vs_exports(&ctx
);
10916 ctx
.block
->kind
|= block_kind_export_end
;
10919 if (!stream_id
.isConstant()) {
10920 append_logical_end(ctx
.block
);
10922 /* branch from then block to endif block */
10923 bld
.branch(aco_opcode::p_branch
);
10924 add_edge(ctx
.block
->index
, &BB_endif
);
10925 ctx
.block
->kind
|= block_kind_uniform
;
10927 /* emit else block */
10928 ctx
.block
= ctx
.program
->create_and_insert_block();
10929 add_edge(BB_if_idx
, ctx
.block
);
10930 bld
.reset(ctx
.block
);
10931 append_logical_start(ctx
.block
);
10933 endif_blocks
.push(std::move(BB_endif
));
10937 while (!endif_blocks
.empty()) {
10938 Block BB_endif
= std::move(endif_blocks
.top());
10939 endif_blocks
.pop();
10941 Block
*BB_else
= ctx
.block
;
10943 append_logical_end(BB_else
);
10944 /* branch from else block to endif block */
10945 bld
.branch(aco_opcode::p_branch
);
10946 add_edge(BB_else
->index
, &BB_endif
);
10947 BB_else
->kind
|= block_kind_uniform
;
10949 /** emit endif merge block */
10950 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10951 bld
.reset(ctx
.block
);
10952 append_logical_start(ctx
.block
);
10955 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10957 append_logical_end(ctx
.block
);
10958 ctx
.block
->kind
|= block_kind_uniform
;
10959 bld
.sopp(aco_opcode::s_endpgm
);
10961 cleanup_cfg(program
);