2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_cube_face_coord
: {
1797 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1798 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1799 emit_extract_vector(ctx
, in
, 1, v1
),
1800 emit_extract_vector(ctx
, in
, 2, v1
) };
1801 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1803 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1804 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1805 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1806 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1807 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1808 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1809 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1812 case nir_op_cube_face_index
: {
1813 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1814 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1815 emit_extract_vector(ctx
, in
, 1, v1
),
1816 emit_extract_vector(ctx
, in
, 2, v1
) };
1817 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1820 case nir_op_bcsel
: {
1821 emit_bcsel(ctx
, instr
, dst
);
1825 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1826 if (dst
.regClass() == v2b
) {
1827 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1828 } else if (dst
.regClass() == v1
) {
1829 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1830 } else if (dst
.regClass() == v2
) {
1831 /* Lowered at NIR level for precision reasons. */
1832 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1834 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1839 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1840 if (dst
.regClass() == v2b
) {
1841 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1842 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1843 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1844 } else if (dst
.regClass() == v1
) {
1845 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1846 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1847 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1848 } else if (dst
.regClass() == v2
) {
1849 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1850 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1851 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1853 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1854 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1856 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1861 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1862 if (dst
.regClass() == v2b
) {
1863 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1864 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1865 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1866 } else if (dst
.regClass() == v1
) {
1867 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1868 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1869 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1870 } else if (dst
.regClass() == v2
) {
1871 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1872 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1873 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1874 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1875 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1876 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1878 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1883 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1884 if (dst
.regClass() == v2b
) {
1885 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1886 } else if (dst
.regClass() == v1
) {
1887 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1888 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1889 // TODO: confirm that this holds under any circumstances
1890 } else if (dst
.regClass() == v2
) {
1891 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1892 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1895 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1899 case nir_op_flog2
: {
1900 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1901 if (dst
.regClass() == v2b
) {
1902 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1903 } else if (dst
.regClass() == v1
) {
1904 emit_log2(ctx
, bld
, Definition(dst
), src
);
1906 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1911 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1912 if (dst
.regClass() == v2b
) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1914 } else if (dst
.regClass() == v1
) {
1915 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1916 } else if (dst
.regClass() == v2
) {
1917 /* Lowered at NIR level for precision reasons. */
1918 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1920 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1924 case nir_op_fexp2
: {
1925 if (dst
.regClass() == v2b
) {
1926 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1927 } else if (dst
.regClass() == v1
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1930 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1934 case nir_op_fsqrt
: {
1935 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1936 if (dst
.regClass() == v2b
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1940 } else if (dst
.regClass() == v2
) {
1941 /* Lowered at NIR level for precision reasons. */
1942 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1944 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1948 case nir_op_ffract
: {
1949 if (dst
.regClass() == v2b
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1951 } else if (dst
.regClass() == v1
) {
1952 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1953 } else if (dst
.regClass() == v2
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1960 case nir_op_ffloor
: {
1961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1962 if (dst
.regClass() == v2b
) {
1963 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1964 } else if (dst
.regClass() == v1
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1966 } else if (dst
.regClass() == v2
) {
1967 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1969 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1973 case nir_op_fceil
: {
1974 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1975 if (dst
.regClass() == v2b
) {
1976 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1977 } else if (dst
.regClass() == v1
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1979 } else if (dst
.regClass() == v2
) {
1980 if (ctx
->options
->chip_class
>= GFX7
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1983 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1984 /* trunc = trunc(src0)
1985 * if (src0 > 0.0 && src0 != trunc)
1988 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1989 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1990 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1991 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1992 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1993 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1994 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1997 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2001 case nir_op_ftrunc
: {
2002 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2003 if (dst
.regClass() == v2b
) {
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2005 } else if (dst
.regClass() == v1
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2007 } else if (dst
.regClass() == v2
) {
2008 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2010 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2014 case nir_op_fround_even
: {
2015 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2016 if (dst
.regClass() == v2b
) {
2017 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2018 } else if (dst
.regClass() == v1
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2020 } else if (dst
.regClass() == v2
) {
2021 if (ctx
->options
->chip_class
>= GFX7
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2024 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2025 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2026 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2028 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2029 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2030 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2031 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2032 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2033 tmp
= sub
->definitions
[0].getTemp();
2035 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2036 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2037 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2038 Temp cond
= vop3
->definitions
[0].getTemp();
2040 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2042 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2043 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2045 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2048 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2054 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2055 aco_ptr
<Instruction
> norm
;
2056 if (dst
.regClass() == v2b
) {
2057 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2058 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2059 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2060 bld
.vop1(opcode
, Definition(dst
), tmp
);
2061 } else if (dst
.regClass() == v1
) {
2062 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2063 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2065 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2066 if (ctx
->options
->chip_class
< GFX9
)
2067 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2069 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2070 bld
.vop1(opcode
, Definition(dst
), tmp
);
2072 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2076 case nir_op_ldexp
: {
2077 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2078 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2079 if (dst
.regClass() == v2b
) {
2080 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2081 } else if (dst
.regClass() == v1
) {
2082 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2083 } else if (dst
.regClass() == v2
) {
2084 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2086 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2090 case nir_op_frexp_sig
: {
2091 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2092 if (dst
.regClass() == v2b
) {
2093 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2094 } else if (dst
.regClass() == v1
) {
2095 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2096 } else if (dst
.regClass() == v2
) {
2097 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2099 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2103 case nir_op_frexp_exp
: {
2104 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2105 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2106 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2107 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2108 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2109 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2110 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2111 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2112 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2114 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2118 case nir_op_fsign
: {
2119 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2120 if (dst
.regClass() == v2b
) {
2121 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2122 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2123 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2124 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2125 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2126 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2127 } else if (dst
.regClass() == v1
) {
2128 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2129 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2130 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2131 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2132 } else if (dst
.regClass() == v2
) {
2133 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2134 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2135 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2137 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2138 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2139 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2141 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2143 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2148 case nir_op_f2f16_rtne
: {
2149 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2150 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2151 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2152 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2153 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2154 * keep value numbering and the scheduler simpler.
2156 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2158 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2161 case nir_op_f2f16_rtz
: {
2162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2163 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2164 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2165 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2168 case nir_op_f2f32
: {
2169 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2170 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2171 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2172 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2174 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2178 case nir_op_f2f64
: {
2179 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2180 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2181 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2182 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2185 case nir_op_i2f16
: {
2186 assert(dst
.regClass() == v2b
);
2187 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2188 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2189 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2190 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2191 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2192 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2195 case nir_op_i2f32
: {
2196 assert(dst
.size() == 1);
2197 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2198 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2199 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2200 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2203 case nir_op_i2f64
: {
2204 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2207 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2208 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2209 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 RegClass rc
= RegClass(src
.type(), 1);
2212 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2213 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2214 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2215 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2216 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2217 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2220 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2224 case nir_op_u2f16
: {
2225 assert(dst
.regClass() == v2b
);
2226 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2227 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2228 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2229 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2230 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2231 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2234 case nir_op_u2f32
: {
2235 assert(dst
.size() == 1);
2236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2237 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2238 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2240 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2241 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2242 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2246 case nir_op_u2f64
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2248 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2249 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2250 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2251 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2252 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 RegClass rc
= RegClass(src
.type(), 1);
2255 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2256 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2257 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2258 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2259 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2260 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2262 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2267 case nir_op_f2i16
: {
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2270 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2271 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2273 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2277 case nir_op_f2u16
: {
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2279 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2280 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2281 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2283 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2286 case nir_op_f2i32
: {
2287 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2288 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2289 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2290 if (dst
.type() == RegType::vgpr
) {
2291 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2293 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2294 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2296 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2297 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2298 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2299 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2301 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2305 case nir_op_f2u32
: {
2306 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2307 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2308 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2309 if (dst
.type() == RegType::vgpr
) {
2310 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2312 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2313 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2315 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2316 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2318 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2320 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2324 case nir_op_f2i64
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2329 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2330 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2331 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2332 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2333 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2334 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2335 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2336 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2337 Temp new_exponent
= bld
.tmp(v1
);
2338 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2339 if (ctx
->program
->chip_class
>= GFX8
)
2340 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2342 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2343 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2344 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2345 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2346 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2347 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2348 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2349 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2350 Temp new_lower
= bld
.tmp(v1
);
2351 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2352 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2353 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2355 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2356 if (src
.type() == RegType::vgpr
)
2357 src
= bld
.as_uniform(src
);
2358 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2359 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2360 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2361 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2362 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2363 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2364 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2365 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2366 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2367 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2368 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2369 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2370 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2371 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2372 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2373 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2374 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2375 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2376 Temp borrow
= bld
.tmp(s1
);
2377 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2378 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2379 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2381 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2382 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2383 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2384 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2385 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2386 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2387 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2388 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2389 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2390 if (dst
.type() == RegType::sgpr
) {
2391 lower
= bld
.as_uniform(lower
);
2392 upper
= bld
.as_uniform(upper
);
2394 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2397 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2401 case nir_op_f2u64
: {
2402 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2403 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2404 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2406 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2407 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2408 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2409 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2410 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2411 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2412 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2413 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2414 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2415 Temp new_exponent
= bld
.tmp(v1
);
2416 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2417 if (ctx
->program
->chip_class
>= GFX8
)
2418 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2420 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2421 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2422 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2423 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2424 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2425 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2426 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2427 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2429 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2430 if (src
.type() == RegType::vgpr
)
2431 src
= bld
.as_uniform(src
);
2432 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2433 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2434 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2435 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2436 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2437 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2438 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2439 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2440 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2441 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2442 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2443 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2444 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2445 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2446 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2447 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2448 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2449 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2451 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2452 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2453 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2454 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2455 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2456 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2457 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2458 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2459 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2460 if (dst
.type() == RegType::sgpr
) {
2461 lower
= bld
.as_uniform(lower
);
2462 upper
= bld
.as_uniform(upper
);
2464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2467 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2471 case nir_op_b2f16
: {
2472 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2473 assert(src
.regClass() == bld
.lm
);
2475 if (dst
.regClass() == s1
) {
2476 src
= bool_to_scalar_condition(ctx
, src
);
2477 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2478 } else if (dst
.regClass() == v2b
) {
2479 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2480 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2482 unreachable("Wrong destination register class for nir_op_b2f16.");
2486 case nir_op_b2f32
: {
2487 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2488 assert(src
.regClass() == bld
.lm
);
2490 if (dst
.regClass() == s1
) {
2491 src
= bool_to_scalar_condition(ctx
, src
);
2492 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2493 } else if (dst
.regClass() == v1
) {
2494 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2496 unreachable("Wrong destination register class for nir_op_b2f32.");
2500 case nir_op_b2f64
: {
2501 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2502 assert(src
.regClass() == bld
.lm
);
2504 if (dst
.regClass() == s2
) {
2505 src
= bool_to_scalar_condition(ctx
, src
);
2506 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2507 } else if (dst
.regClass() == v2
) {
2508 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2509 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2512 unreachable("Wrong destination register class for nir_op_b2f64.");
2519 case nir_op_i2i64
: {
2520 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2521 /* no need to do the extract in get_alu_src() */
2522 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2523 sgpr_extract_sext
: sgpr_extract_undef
;
2524 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2526 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2527 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2534 case nir_op_u2u64
: {
2535 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2536 /* no need to do the extract in get_alu_src() */
2537 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2538 sgpr_extract_zext
: sgpr_extract_undef
;
2539 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2541 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2542 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2550 case nir_op_b2i64
: {
2551 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2552 assert(src
.regClass() == bld
.lm
);
2554 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2555 if (tmp
.regClass() == s1
) {
2556 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2557 bool_to_scalar_condition(ctx
, src
, tmp
);
2558 } else if (tmp
.type() == RegType::vgpr
) {
2559 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2561 unreachable("Invalid register class for b2i32");
2565 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2570 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2571 assert(dst
.regClass() == bld
.lm
);
2573 if (src
.type() == RegType::vgpr
) {
2574 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2575 assert(dst
.regClass() == bld
.lm
);
2576 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2577 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2579 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2581 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2582 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2584 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2585 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2587 bool_to_vector_condition(ctx
, tmp
, dst
);
2591 case nir_op_pack_64_2x32_split
: {
2592 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2593 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2598 case nir_op_unpack_64_2x32_split_x
:
2599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2601 case nir_op_unpack_64_2x32_split_y
:
2602 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2604 case nir_op_unpack_32_2x16_split_x
:
2605 if (dst
.type() == RegType::vgpr
) {
2606 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2608 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2611 case nir_op_unpack_32_2x16_split_y
:
2612 if (dst
.type() == RegType::vgpr
) {
2613 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2615 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2618 case nir_op_pack_32_2x16_split
: {
2619 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2620 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2621 if (dst
.regClass() == v1
) {
2622 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2623 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2626 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2627 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2628 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2632 case nir_op_pack_half_2x16
: {
2633 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2635 if (dst
.regClass() == v1
) {
2636 Temp src0
= bld
.tmp(v1
);
2637 Temp src1
= bld
.tmp(v1
);
2638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2639 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2640 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2642 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2643 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2644 if (ctx
->program
->chip_class
>= GFX10
) {
2645 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2646 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2648 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2652 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2656 case nir_op_unpack_half_2x16_split_x
: {
2657 if (dst
.regClass() == v1
) {
2658 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2660 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2664 case nir_op_unpack_half_2x16_split_y
: {
2665 if (dst
.regClass() == v1
) {
2666 /* TODO: use SDWA here */
2667 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2668 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2670 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2674 case nir_op_fquantize2f16
: {
2675 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2676 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2679 if (ctx
->program
->chip_class
>= GFX8
) {
2680 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2681 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2682 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2684 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2685 * so compare the result and flush to 0 if it's smaller.
2687 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2688 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2689 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2690 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2691 cmp_res
= vop3
->definitions
[0].getTemp();
2694 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2695 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2696 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2698 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2703 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2704 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2706 if (dst
.regClass() == s1
) {
2707 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2708 } else if (dst
.regClass() == v1
) {
2709 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2711 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2715 case nir_op_bitfield_select
: {
2716 /* (mask & insert) | (~mask & base) */
2717 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2718 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2719 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2721 /* dst = (insert & bitmask) | (base & ~bitmask) */
2722 if (dst
.regClass() == s1
) {
2723 aco_ptr
<Instruction
> sop2
;
2724 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2725 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2727 if (const_insert
&& const_bitmask
) {
2728 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2730 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2731 lhs
= Operand(insert
);
2735 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2736 if (const_base
&& const_bitmask
) {
2737 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2739 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2740 rhs
= Operand(base
);
2743 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2745 } else if (dst
.regClass() == v1
) {
2746 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2747 base
= as_vgpr(ctx
, base
);
2748 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2749 insert
= as_vgpr(ctx
, insert
);
2751 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2754 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2760 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2761 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2762 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2764 if (dst
.type() == RegType::sgpr
) {
2766 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2767 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2768 if (const_offset
&& const_bits
) {
2769 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2770 extract
= Operand(const_extract
);
2774 width
= Operand(const_bits
->u32
<< 16);
2776 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2778 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2782 if (dst
.regClass() == s1
) {
2783 if (instr
->op
== nir_op_ubfe
)
2784 opcode
= aco_opcode::s_bfe_u32
;
2786 opcode
= aco_opcode::s_bfe_i32
;
2787 } else if (dst
.regClass() == s2
) {
2788 if (instr
->op
== nir_op_ubfe
)
2789 opcode
= aco_opcode::s_bfe_u64
;
2791 opcode
= aco_opcode::s_bfe_i64
;
2793 unreachable("Unsupported BFE bit size");
2796 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2800 if (dst
.regClass() == v1
) {
2801 if (instr
->op
== nir_op_ubfe
)
2802 opcode
= aco_opcode::v_bfe_u32
;
2804 opcode
= aco_opcode::v_bfe_i32
;
2806 unreachable("Unsupported BFE bit size");
2809 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2813 case nir_op_bit_count
: {
2814 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2815 if (src
.regClass() == s1
) {
2816 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2817 } else if (src
.regClass() == v1
) {
2818 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2819 } else if (src
.regClass() == v2
) {
2820 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2821 emit_extract_vector(ctx
, src
, 1, v1
),
2822 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2823 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2824 } else if (src
.regClass() == s2
) {
2825 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2827 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2840 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2844 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2848 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2852 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2856 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2857 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2859 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2860 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2864 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2865 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2867 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2868 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2872 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2876 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2881 case nir_op_fddx_fine
:
2882 case nir_op_fddy_fine
:
2883 case nir_op_fddx_coarse
:
2884 case nir_op_fddy_coarse
: {
2885 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2886 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2887 if (instr
->op
== nir_op_fddx_fine
) {
2888 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2889 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2890 } else if (instr
->op
== nir_op_fddy_fine
) {
2891 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2892 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2894 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2895 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2896 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2898 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2902 if (ctx
->program
->chip_class
>= GFX8
) {
2903 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2904 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2906 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2907 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2908 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2910 emit_wqm(ctx
, tmp
, dst
, true);
2914 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2918 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2920 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2922 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2923 // which get truncated the lsb if double and msb if int
2924 // for now, we only use s_mov_b64 with 64bit inline constants
2925 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2926 assert(dst
.type() == RegType::sgpr
);
2928 Builder
bld(ctx
->program
, ctx
->block
);
2930 if (instr
->def
.bit_size
== 1) {
2931 assert(dst
.regClass() == bld
.lm
);
2932 int val
= instr
->value
[0].b
? -1 : 0;
2933 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2934 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2935 } else if (instr
->def
.bit_size
== 8) {
2936 /* ensure that the value is correctly represented in the low byte of the register */
2937 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2938 } else if (instr
->def
.bit_size
== 16) {
2939 /* ensure that the value is correctly represented in the low half of the register */
2940 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2941 } else if (dst
.size() == 1) {
2942 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2944 assert(dst
.size() != 1);
2945 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2946 if (instr
->def
.bit_size
== 64)
2947 for (unsigned i
= 0; i
< dst
.size(); i
++)
2948 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2950 for (unsigned i
= 0; i
< dst
.size(); i
++)
2951 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2953 vec
->definitions
[0] = Definition(dst
);
2954 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2958 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2960 uint32_t new_mask
= 0;
2961 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2962 if (mask
& (1u << i
))
2963 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2967 struct LoadEmitInfo
{
2970 unsigned num_components
;
2971 unsigned component_size
;
2972 Temp resource
= Temp(0, s1
);
2973 unsigned component_stride
= 0;
2974 unsigned const_offset
= 0;
2975 unsigned align_mul
= 0;
2976 unsigned align_offset
= 0;
2979 unsigned swizzle_component_size
= 0;
2980 memory_sync_info sync
;
2981 Temp soffset
= Temp(0, s1
);
2984 using LoadCallback
= Temp(*)(
2985 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
2986 unsigned align
, unsigned const_offset
, Temp dst_hint
);
2988 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
2989 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
2991 unsigned load_size
= info
->num_components
* info
->component_size
;
2992 unsigned component_size
= info
->component_size
;
2994 unsigned num_vals
= 0;
2995 Temp vals
[info
->dst
.bytes()];
2997 unsigned const_offset
= info
->const_offset
;
2999 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3000 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3002 unsigned bytes_read
= 0;
3003 while (bytes_read
< load_size
) {
3004 unsigned bytes_needed
= load_size
- bytes_read
;
3006 /* add buffer for unaligned loads */
3007 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3010 if ((bytes_needed
> 2 ||
3011 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3012 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3013 if (info
->component_stride
) {
3014 assert(supports_8bit_16bit_loads
&& "unimplemented");
3018 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3019 bytes_needed
= align(bytes_needed
, 4);
3026 if (info
->swizzle_component_size
)
3027 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3028 if (info
->component_stride
)
3029 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3031 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3033 /* reduce constant offset */
3034 Operand offset
= info
->offset
;
3035 unsigned reduced_const_offset
= const_offset
;
3036 bool remove_const_offset_completely
= need_to_align_offset
;
3037 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3038 unsigned to_add
= const_offset
;
3039 if (remove_const_offset_completely
) {
3040 reduced_const_offset
= 0;
3042 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3043 reduced_const_offset
%= max_const_offset_plus_one
;
3045 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3046 if (offset
.isConstant()) {
3047 offset
= Operand(offset
.constantValue() + to_add
);
3048 } else if (offset_tmp
.regClass() == s1
) {
3049 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3050 offset_tmp
, Operand(to_add
));
3051 } else if (offset_tmp
.regClass() == v1
) {
3052 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3054 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3055 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3056 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3058 if (offset_tmp
.regClass() == s2
) {
3059 Temp carry
= bld
.tmp(s1
);
3060 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3061 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3062 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3064 Temp new_lo
= bld
.tmp(v1
);
3065 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3066 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3067 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3072 /* align offset down if needed */
3073 Operand aligned_offset
= offset
;
3074 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3075 if (need_to_align_offset
) {
3077 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3078 if (offset
.isConstant()) {
3079 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3080 } else if (offset_tmp
.regClass() == s1
) {
3081 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3082 } else if (offset_tmp
.regClass() == s2
) {
3083 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3084 } else if (offset_tmp
.regClass() == v1
) {
3085 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3086 } else if (offset_tmp
.regClass() == v2
) {
3087 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3088 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3089 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3090 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3093 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3094 bld
.copy(bld
.def(s1
), aligned_offset
);
3096 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3097 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3099 /* the callback wrote directly to dst */
3100 if (val
== info
->dst
) {
3101 assert(num_vals
== 0);
3102 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3106 /* shift result right if needed */
3107 if (info
->component_size
< 4 && byte_align_loads
) {
3108 Operand
align((uint32_t)byte_align
);
3109 if (byte_align
== -1) {
3110 if (offset
.isConstant())
3111 align
= Operand(offset
.constantValue() % 4u);
3112 else if (offset
.size() == 2)
3113 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3118 assert(val
.bytes() >= load_size
&& "unimplemented");
3119 if (val
.type() == RegType::sgpr
)
3120 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3122 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3126 /* add result to list and advance */
3127 if (info
->component_stride
) {
3128 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3129 const_offset
+= info
->component_stride
;
3130 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3132 const_offset
+= val
.bytes();
3133 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3135 bytes_read
+= val
.bytes();
3136 vals
[num_vals
++] = val
;
3139 /* create array of components */
3140 unsigned components_split
= 0;
3141 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3142 bool has_vgprs
= false;
3143 for (unsigned i
= 0; i
< num_vals
;) {
3145 unsigned num_tmps
= 0;
3146 unsigned tmp_size
= 0;
3147 RegType reg_type
= RegType::sgpr
;
3148 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3149 if (vals
[i
].type() == RegType::vgpr
)
3150 reg_type
= RegType::vgpr
;
3151 tmp_size
+= vals
[i
].bytes();
3152 tmp
[num_tmps
++] = vals
[i
++];
3155 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3156 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3157 for (unsigned i
= 0; i
< num_tmps
; i
++)
3158 vec
->operands
[i
] = Operand(tmp
[i
]);
3159 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3160 vec
->definitions
[0] = Definition(tmp
[0]);
3161 bld
.insert(std::move(vec
));
3164 if (tmp
[0].bytes() % component_size
) {
3166 assert(i
== num_vals
);
3167 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3168 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3171 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3173 unsigned start
= components_split
;
3175 if (tmp_size
== elem_rc
.bytes()) {
3176 allocated_vec
[components_split
++] = tmp
[0];
3178 assert(tmp_size
% elem_rc
.bytes() == 0);
3179 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3180 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3181 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3182 Temp component
= bld
.tmp(elem_rc
);
3183 allocated_vec
[components_split
++] = component
;
3184 split
->definitions
[i
] = Definition(component
);
3186 split
->operands
[0] = Operand(tmp
[0]);
3187 bld
.insert(std::move(split
));
3190 /* try to p_as_uniform early so we can create more optimizable code and
3191 * also update allocated_vec */
3192 for (unsigned j
= start
; j
< components_split
; j
++) {
3193 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3194 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3195 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3199 /* concatenate components and p_as_uniform() result if needed */
3200 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3201 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3203 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3205 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3206 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3207 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3208 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3210 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3211 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3212 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3213 vec
->definitions
[0] = Definition(tmp
);
3214 bld
.insert(std::move(vec
));
3215 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3217 vec
->definitions
[0] = Definition(info
->dst
);
3218 bld
.insert(std::move(vec
));
3222 Operand
load_lds_size_m0(Builder
& bld
)
3224 /* TODO: m0 does not need to be initialized on GFX9+ */
3225 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3228 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3229 Temp offset
, unsigned bytes_needed
,
3230 unsigned align
, unsigned const_offset
,
3233 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3235 Operand m
= load_lds_size_m0(bld
);
3237 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3238 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3243 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3244 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3246 op
= aco_opcode::ds_read_b128
;
3247 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3250 op
= aco_opcode::ds_read2_b64
;
3251 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3253 op
= aco_opcode::ds_read_b96
;
3254 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3256 op
= aco_opcode::ds_read_b64
;
3257 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3260 op
= aco_opcode::ds_read2_b32
;
3261 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3263 op
= aco_opcode::ds_read_b32
;
3264 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3266 op
= aco_opcode::ds_read_u16
;
3269 op
= aco_opcode::ds_read_u8
;
3272 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3273 if (const_offset
>= max_offset_plus_one
) {
3274 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3275 const_offset
%= max_offset_plus_one
;
3279 const_offset
/= (size
/ 2u);
3281 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3282 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3285 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3287 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3288 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3291 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3296 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3298 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3299 Temp offset
, unsigned bytes_needed
,
3300 unsigned align
, unsigned const_offset
,
3305 if (bytes_needed
<= 4) {
3307 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3308 } else if (bytes_needed
<= 8) {
3310 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3311 } else if (bytes_needed
<= 16) {
3313 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3314 } else if (bytes_needed
<= 32) {
3316 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3319 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3321 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3322 if (info
->resource
.id()) {
3323 load
->operands
[0] = Operand(info
->resource
);
3324 load
->operands
[1] = Operand(offset
);
3326 load
->operands
[0] = Operand(offset
);
3327 load
->operands
[1] = Operand(0u);
3329 RegClass
rc(RegType::sgpr
, size
);
3330 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3331 load
->definitions
[0] = Definition(val
);
3332 load
->glc
= info
->glc
;
3333 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3334 load
->sync
= info
->sync
;
3335 bld
.insert(std::move(load
));
3339 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3341 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3342 Temp offset
, unsigned bytes_needed
,
3343 unsigned align_
, unsigned const_offset
,
3346 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3347 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3349 if (info
->soffset
.id()) {
3350 if (soffset
.isTemp())
3351 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3352 soffset
= Operand(info
->soffset
);
3355 unsigned bytes_size
= 0;
3357 if (bytes_needed
== 1 || align_
% 2) {
3359 op
= aco_opcode::buffer_load_ubyte
;
3360 } else if (bytes_needed
== 2 || align_
% 4) {
3362 op
= aco_opcode::buffer_load_ushort
;
3363 } else if (bytes_needed
<= 4) {
3365 op
= aco_opcode::buffer_load_dword
;
3366 } else if (bytes_needed
<= 8) {
3368 op
= aco_opcode::buffer_load_dwordx2
;
3369 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3371 op
= aco_opcode::buffer_load_dwordx3
;
3374 op
= aco_opcode::buffer_load_dwordx4
;
3376 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3377 mubuf
->operands
[0] = Operand(info
->resource
);
3378 mubuf
->operands
[1] = vaddr
;
3379 mubuf
->operands
[2] = soffset
;
3380 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3381 mubuf
->glc
= info
->glc
;
3382 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3383 mubuf
->sync
= info
->sync
;
3384 mubuf
->offset
= const_offset
;
3385 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3386 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3387 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3388 mubuf
->definitions
[0] = Definition(val
);
3389 bld
.insert(std::move(mubuf
));
3394 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3395 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3397 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3399 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3400 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3402 if (addr
.type() == RegType::vgpr
)
3403 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3404 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3407 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3408 Temp offset
, unsigned bytes_needed
,
3409 unsigned align_
, unsigned const_offset
,
3412 unsigned bytes_size
= 0;
3413 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3414 bool global
= bld
.program
->chip_class
>= GFX9
;
3416 if (bytes_needed
== 1) {
3418 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3419 } else if (bytes_needed
== 2) {
3421 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3422 } else if (bytes_needed
<= 4) {
3424 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3425 } else if (bytes_needed
<= 8) {
3427 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3428 } else if (bytes_needed
<= 12 && !mubuf
) {
3430 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3433 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3435 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3436 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3438 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3439 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3440 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3441 mubuf
->operands
[2] = Operand(0u);
3442 mubuf
->glc
= info
->glc
;
3445 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3446 mubuf
->disable_wqm
= false;
3447 mubuf
->sync
= info
->sync
;
3448 mubuf
->definitions
[0] = Definition(val
);
3449 bld
.insert(std::move(mubuf
));
3451 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3453 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3454 flat
->operands
[0] = Operand(offset
);
3455 flat
->operands
[1] = Operand(s1
);
3456 flat
->glc
= info
->glc
;
3457 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3458 flat
->sync
= info
->sync
;
3460 flat
->definitions
[0] = Definition(val
);
3461 bld
.insert(std::move(flat
));
3467 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3469 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3470 Temp address
, unsigned base_offset
, unsigned align
)
3472 assert(util_is_power_of_two_nonzero(align
));
3474 Builder
bld(ctx
->program
, ctx
->block
);
3476 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3477 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3478 info
.align_mul
= align
;
3479 info
.align_offset
= 0;
3480 info
.sync
= memory_sync_info(storage_shared
);
3481 info
.const_offset
= base_offset
;
3482 emit_lds_load(ctx
, bld
, &info
);
3487 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3492 Builder
bld(ctx
->program
, ctx
->block
);
3494 ASSERTED
bool is_subdword
= false;
3495 for (unsigned i
= 0; i
< count
; i
++)
3496 is_subdword
|= offsets
[i
] % 4;
3497 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3498 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3500 /* count == 1 fast path */
3502 if (dst_type
== RegType::sgpr
)
3503 dst
[0] = bld
.as_uniform(src
);
3505 dst
[0] = as_vgpr(ctx
, src
);
3509 for (unsigned i
= 0; i
< count
- 1; i
++)
3510 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3511 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3513 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3514 src
= as_vgpr(ctx
, src
);
3516 /* use allocated_vec if possible */
3517 auto it
= ctx
->allocated_vec
.find(src
.id());
3518 if (it
!= ctx
->allocated_vec
.end()) {
3519 if (!it
->second
[0].id())
3521 unsigned elem_size
= it
->second
[0].bytes();
3522 assert(src
.bytes() % elem_size
== 0);
3524 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3525 if (!it
->second
[i
].id())
3529 for (unsigned i
= 0; i
< count
; i
++) {
3530 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3534 for (unsigned i
= 0; i
< count
; i
++) {
3535 unsigned start_idx
= offsets
[i
] / elem_size
;
3536 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3537 if (op_count
== 1) {
3538 if (dst_type
== RegType::sgpr
)
3539 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3541 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3545 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3546 for (unsigned j
= 0; j
< op_count
; j
++) {
3547 Temp tmp
= it
->second
[start_idx
+ j
];
3548 if (dst_type
== RegType::sgpr
)
3549 tmp
= bld
.as_uniform(tmp
);
3550 vec
->operands
[j
] = Operand(tmp
);
3552 vec
->definitions
[0] = Definition(dst
[i
]);
3553 bld
.insert(std::move(vec
));
3561 if (dst_type
== RegType::sgpr
)
3562 src
= bld
.as_uniform(src
);
3565 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3566 split
->operands
[0] = Operand(src
);
3567 for (unsigned i
= 0; i
< count
; i
++)
3568 split
->definitions
[i
] = Definition(dst
[i
]);
3569 bld
.insert(std::move(split
));
3572 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3573 int *start
, int *count
)
3575 unsigned start_elem
= ffs(todo_mask
) - 1;
3576 bool skip
= !(mask
& (1 << start_elem
));
3578 mask
= ~mask
& todo_mask
;
3582 u_bit_scan_consecutive_range(&mask
, start
, count
);
3587 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3589 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3592 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3593 Temp address
, unsigned base_offset
, unsigned align
)
3595 assert(util_is_power_of_two_nonzero(align
));
3596 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3598 Builder
bld(ctx
->program
, ctx
->block
);
3599 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3600 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3602 unsigned write_count
= 0;
3603 Temp write_datas
[32];
3604 unsigned offsets
[32];
3605 aco_opcode opcodes
[32];
3607 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3609 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3612 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3613 offsets
[write_count
] = offset
;
3614 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3616 advance_write_mask(&todo
, offset
, bytes
);
3620 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3621 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3622 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3623 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3625 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3626 aco_opcode op
= aco_opcode::num_opcodes
;
3627 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3628 op
= aco_opcode::ds_write_b128
;
3630 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3631 op
= aco_opcode::ds_write_b96
;
3633 } else if (bytes
>= 8 && aligned8
) {
3634 op
= aco_opcode::ds_write_b64
;
3636 } else if (bytes
>= 4 && aligned4
) {
3637 op
= aco_opcode::ds_write_b32
;
3639 } else if (bytes
>= 2 && aligned2
) {
3640 op
= aco_opcode::ds_write_b16
;
3642 } else if (bytes
>= 1) {
3643 op
= aco_opcode::ds_write_b8
;
3649 offsets
[write_count
] = offset
;
3650 opcodes
[write_count
] = op
;
3652 advance_write_mask(&todo
, offset
, bytes
);
3655 Operand m
= load_lds_size_m0(bld
);
3657 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3659 for (unsigned i
= 0; i
< write_count
; i
++) {
3660 aco_opcode op
= opcodes
[i
];
3661 if (op
== aco_opcode::num_opcodes
)
3664 Temp data
= write_datas
[i
];
3666 unsigned second
= write_count
;
3667 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3668 for (second
= i
+ 1; second
< write_count
; second
++) {
3669 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3670 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3671 opcodes
[second
] = aco_opcode::num_opcodes
;
3677 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3678 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3680 unsigned inline_offset
= base_offset
+ offsets
[i
];
3681 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3682 Temp address_offset
= address
;
3683 if (inline_offset
> max_offset
) {
3684 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3685 inline_offset
= offsets
[i
];
3687 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3691 Temp second_data
= write_datas
[second
];
3692 inline_offset
/= data
.bytes();
3693 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3695 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3697 static_cast<DS_instruction
*>(instr
)->sync
=
3698 memory_sync_info(storage_shared
);
3702 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3704 unsigned align
= 16;
3706 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3712 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3717 return aco_opcode::buffer_store_byte
;
3720 return aco_opcode::buffer_store_short
;
3722 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3724 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3727 return aco_opcode::buffer_store_dwordx3
;
3729 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3731 unreachable("Unexpected store size");
3732 return aco_opcode::num_opcodes
;
3735 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3736 Temp data
, unsigned writemask
, int swizzle_element_size
,
3737 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3739 unsigned write_count_with_skips
= 0;
3742 /* determine how to split the data */
3743 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3746 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3747 offsets
[write_count_with_skips
] = offset
;
3748 if (skips
[write_count_with_skips
]) {
3749 advance_write_mask(&todo
, offset
, bytes
);
3750 write_count_with_skips
++;
3754 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3755 * larger than swizzle_element_size */
3756 bytes
= MIN2(bytes
, swizzle_element_size
);
3758 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3760 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3761 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3764 /* dword or larger stores have to be dword-aligned */
3765 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3766 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3767 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3769 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3771 advance_write_mask(&todo
, offset
, bytes
);
3772 write_count_with_skips
++;
3775 /* actually split data */
3776 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3779 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3782 write_datas
[*write_count
] = write_datas
[i
];
3783 offsets
[*write_count
] = offsets
[i
];
3788 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3789 unsigned split_cnt
= 0u, Temp dst
= Temp())
3791 Builder
bld(ctx
->program
, ctx
->block
);
3792 unsigned dword_size
= elem_size_bytes
/ 4;
3795 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3797 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3798 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3799 instr
->definitions
[0] = Definition(dst
);
3801 for (unsigned i
= 0; i
< cnt
; ++i
) {
3803 assert(arr
[i
].size() == dword_size
);
3804 allocated_vec
[i
] = arr
[i
];
3805 instr
->operands
[i
] = Operand(arr
[i
]);
3807 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3808 allocated_vec
[i
] = zero
;
3809 instr
->operands
[i
] = Operand(zero
);
3813 bld
.insert(std::move(instr
));
3816 emit_split_vector(ctx
, dst
, split_cnt
);
3818 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3823 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3825 if (const_offset
>= 4096) {
3826 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3827 const_offset
%= 4096u;
3830 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3831 else if (unlikely(voffset
.regClass() == s1
))
3832 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3833 else if (likely(voffset
.regClass() == v1
))
3834 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3836 unreachable("Unsupported register class of voffset");
3839 return const_offset
;
3842 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3843 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3844 bool slc
= false, bool swizzled
= false)
3847 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3848 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3850 Builder
bld(ctx
->program
, ctx
->block
);
3851 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3852 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3854 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3855 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3856 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3857 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3858 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3859 /* dlc*/ false, /* slc */ slc
);
3861 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3864 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3865 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3866 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3868 Builder
bld(ctx
->program
, ctx
->block
);
3869 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3871 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3873 unsigned write_count
= 0;
3874 Temp write_datas
[32];
3875 unsigned offsets
[32];
3876 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3877 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3879 for (unsigned i
= 0; i
< write_count
; i
++) {
3880 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3881 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3885 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3886 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3887 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3889 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3890 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3891 assert(!!stride
!= allow_combining
);
3893 Builder
bld(ctx
->program
, ctx
->block
);
3895 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3896 info
.component_stride
= allow_combining
? 0 : stride
;
3898 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3899 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3900 info
.align_offset
= 0;
3901 info
.soffset
= soffset
;
3902 info
.const_offset
= base_const_offset
;
3903 emit_mubuf_load(ctx
, bld
, &info
);
3906 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3908 Builder
bld(ctx
->program
, ctx
->block
);
3909 Temp offset
= base_offset
.first
;
3910 unsigned const_offset
= base_offset
.second
;
3912 if (!nir_src_is_const(*off_src
)) {
3913 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3916 /* Calculate indirect offset with stride */
3917 if (likely(indirect_offset_arg
.regClass() == v1
))
3918 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3919 else if (indirect_offset_arg
.regClass() == s1
)
3920 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3922 unreachable("Unsupported register class of indirect offset");
3924 /* Add to the supplied base offset */
3925 if (offset
.id() == 0)
3926 offset
= with_stride
;
3927 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3928 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3929 else if (offset
.size() == 1 && with_stride
.size() == 1)
3930 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3932 unreachable("Unsupported register class of indirect offset");
3934 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3935 const_offset
+= const_offset_arg
* stride
;
3938 return std::make_pair(offset
, const_offset
);
3941 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3943 Builder
bld(ctx
->program
, ctx
->block
);
3946 if (off1
.first
.id() && off2
.first
.id()) {
3947 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3948 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3949 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3950 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3952 unreachable("Unsupported register class of indirect offset");
3954 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3957 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3960 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3962 Builder
bld(ctx
->program
, ctx
->block
);
3963 unsigned const_offset
= offs
.second
* multiplier
;
3965 if (!offs
.first
.id())
3966 return std::make_pair(offs
.first
, const_offset
);
3968 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3969 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3970 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3972 return std::make_pair(offset
, const_offset
);
3975 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3977 Builder
bld(ctx
->program
, ctx
->block
);
3979 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3980 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3981 /* component is in bytes */
3982 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3984 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3985 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3986 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3989 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3991 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3994 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3996 Builder
bld(ctx
->program
, ctx
->block
);
3998 switch (ctx
->shader
->info
.stage
) {
3999 case MESA_SHADER_TESS_CTRL
:
4000 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4001 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4002 case MESA_SHADER_TESS_EVAL
:
4003 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4005 unreachable("Unsupported stage in get_tess_rel_patch_id");
4009 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4011 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4012 Builder
bld(ctx
->program
, ctx
->block
);
4014 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4015 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4017 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4019 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4020 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4022 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4023 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4024 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4026 return offset_mul(ctx
, offs
, 4u);
4029 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4031 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4032 Builder
bld(ctx
->program
, ctx
->block
);
4034 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4035 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4036 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4037 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4039 std::pair
<Temp
, unsigned> offs
= instr
4040 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4041 : std::make_pair(Temp(), 0u);
4043 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4044 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4049 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4050 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4052 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4053 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4055 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4056 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4062 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4064 Builder
bld(ctx
->program
, ctx
->block
);
4066 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4067 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4069 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4071 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4072 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4073 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4075 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4076 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4081 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4083 Builder
bld(ctx
->program
, ctx
->block
);
4085 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4086 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4087 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4088 unsigned attr_stride
= ctx
->tcs_num_patches
;
4090 std::pair
<Temp
, unsigned> offs
= instr
4091 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4092 : std::make_pair(Temp(), 0u);
4094 if (const_base_offset
)
4095 offs
.second
+= const_base_offset
* attr_stride
;
4097 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4098 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4099 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4104 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4106 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4111 unsigned drv_loc
= nir_intrinsic_base(instr
);
4112 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4114 if (!nir_src_is_const(*off_src
)) {
4120 uint64_t slot
= per_vertex
4121 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4122 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4123 return (((uint64_t) 1) << slot
) & mask
;
4126 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4128 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4129 unsigned component
= nir_intrinsic_component(instr
);
4130 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4132 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4133 if (off_instr
->type
!= nir_instr_type_load_const
)
4136 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4137 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4139 if (instr
->src
[0].ssa
->bit_size
== 64)
4140 write_mask
= widen_mask(write_mask
, 2);
4142 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4144 for (unsigned i
= 0; i
< 8; ++i
) {
4145 if (write_mask
& (1 << i
)) {
4146 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4147 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4155 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4157 /* Only TCS per-vertex inputs are supported by this function.
4158 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4160 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4163 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4164 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4165 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4166 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4167 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4168 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4173 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4174 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4175 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4180 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4182 Builder
bld(ctx
->program
, ctx
->block
);
4184 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4185 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4186 bool indirect_write
;
4187 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4188 if (temp_only_input
&& !indirect_write
)
4192 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4193 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4194 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4195 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4197 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4198 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4199 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4200 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4201 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4205 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4206 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4207 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4208 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4209 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4210 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4211 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4212 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4213 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4214 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4215 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4216 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4217 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4219 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4220 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4222 unreachable("Invalid LS or ES stage");
4225 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4226 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4227 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4231 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4236 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4237 return off
== ctx
->tcs_tess_lvl_out_loc
||
4238 off
== ctx
->tcs_tess_lvl_in_loc
;
4242 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4244 uint64_t mask
= per_vertex
4245 ? ctx
->program
->info
->tcs
.tes_inputs_read
4246 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4248 bool indirect_write
= false;
4249 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4250 return indirect_write
|| output_read_by_tes
;
4253 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4255 uint64_t mask
= per_vertex
4256 ? ctx
->shader
->info
.outputs_read
4257 : ctx
->shader
->info
.patch_outputs_read
;
4259 bool indirect_write
= false;
4260 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4261 return indirect_write
|| output_read
;
4264 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4266 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4267 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4269 Builder
bld(ctx
->program
, ctx
->block
);
4271 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4272 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4273 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4275 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4276 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4277 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4279 if (write_to_vmem
) {
4280 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4281 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4282 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4284 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4285 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4286 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4290 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4291 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4292 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4296 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4298 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4299 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4301 Builder
bld(ctx
->program
, ctx
->block
);
4303 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4304 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4305 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4306 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4308 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4311 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4313 if (ctx
->stage
== vertex_vs
||
4314 ctx
->stage
== tess_eval_vs
||
4315 ctx
->stage
== fragment_fs
||
4316 ctx
->stage
== ngg_vertex_gs
||
4317 ctx
->stage
== ngg_tess_eval_gs
||
4318 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4319 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4320 if (!stored_to_temps
) {
4321 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4324 } else if (ctx
->stage
== vertex_es
||
4325 ctx
->stage
== vertex_ls
||
4326 ctx
->stage
== tess_eval_es
||
4327 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4328 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4329 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4330 visit_store_ls_or_es_output(ctx
, instr
);
4331 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4332 visit_store_tcs_output(ctx
, instr
, false);
4334 unreachable("Shader stage not implemented");
4338 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4340 visit_load_tcs_output(ctx
, instr
, false);
4343 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4345 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4346 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4348 Builder
bld(ctx
->program
, ctx
->block
);
4350 if (dst
.regClass() == v2b
) {
4351 if (ctx
->program
->has_16bank_lds
) {
4352 assert(ctx
->options
->chip_class
<= GFX8
);
4353 Builder::Result interp_p1
=
4354 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4355 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4356 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4357 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4358 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4359 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4361 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4363 if (ctx
->options
->chip_class
== GFX8
)
4364 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4366 Builder::Result interp_p1
=
4367 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4368 coord1
, bld
.m0(prim_mask
), idx
, component
);
4369 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4370 interp_p1
, idx
, component
);
4373 Builder::Result interp_p1
=
4374 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4375 bld
.m0(prim_mask
), idx
, component
);
4377 if (ctx
->program
->has_16bank_lds
)
4378 interp_p1
.instr
->operands
[0].setLateKill(true);
4380 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4381 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4385 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4387 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4388 for (unsigned i
= 0; i
< num_components
; i
++)
4389 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4390 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4391 assert(num_components
== 4);
4392 Builder
bld(ctx
->program
, ctx
->block
);
4393 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4396 for (Operand
& op
: vec
->operands
)
4397 op
= op
.isUndefined() ? Operand(0u) : op
;
4399 vec
->definitions
[0] = Definition(dst
);
4400 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4401 emit_split_vector(ctx
, dst
, num_components
);
4405 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4407 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4408 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4409 unsigned idx
= nir_intrinsic_base(instr
);
4410 unsigned component
= nir_intrinsic_component(instr
);
4411 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4413 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4415 assert(offset
->u32
== 0);
4417 /* the lower 15bit of the prim_mask contain the offset into LDS
4418 * while the upper bits contain the number of prims */
4419 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4420 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4421 Builder
bld(ctx
->program
, ctx
->block
);
4422 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4423 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4424 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4425 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4426 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4429 if (instr
->dest
.ssa
.num_components
== 1) {
4430 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4432 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4433 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4435 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4436 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4437 vec
->operands
[i
] = Operand(tmp
);
4439 vec
->definitions
[0] = Definition(dst
);
4440 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4444 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4445 unsigned offset
, unsigned stride
, unsigned channels
)
4447 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4448 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4450 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4451 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4454 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4455 unsigned offset
, unsigned stride
, unsigned *channels
)
4457 if (!vtx_info
->chan_byte_size
) {
4458 *channels
= vtx_info
->num_channels
;
4459 return vtx_info
->chan_format
;
4462 unsigned num_channels
= *channels
;
4463 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4464 unsigned new_channels
= num_channels
+ 1;
4465 /* first, assume more loads is worse and try using a larger data format */
4466 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4468 /* don't make the attribute potentially out-of-bounds */
4469 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4473 if (new_channels
== 5) {
4474 /* then try decreasing load size (at the cost of more loads) */
4475 new_channels
= *channels
;
4476 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4480 if (new_channels
< *channels
)
4481 *channels
= new_channels
;
4482 num_channels
= new_channels
;
4485 switch (vtx_info
->chan_format
) {
4486 case V_008F0C_BUF_DATA_FORMAT_8
:
4487 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4488 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4489 case V_008F0C_BUF_DATA_FORMAT_16
:
4490 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4491 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4492 case V_008F0C_BUF_DATA_FORMAT_32
:
4493 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4494 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4496 unreachable("shouldn't reach here");
4497 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4500 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4501 * so we may need to fix it up. */
4502 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4504 Builder
bld(ctx
->program
, ctx
->block
);
4506 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4507 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4509 /* For the integer-like cases, do a natural sign extension.
4511 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4512 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4515 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4516 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4518 /* Convert back to the right type. */
4519 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4520 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4521 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4522 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4523 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4524 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4530 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4532 Builder
bld(ctx
->program
, ctx
->block
);
4533 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4534 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4536 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4537 if (off_instr
->type
!= nir_instr_type_load_const
) {
4538 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4540 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4542 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4544 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4545 unsigned component
= nir_intrinsic_component(instr
);
4546 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4547 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4548 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4549 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4550 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4552 unsigned dfmt
= attrib_format
& 0xf;
4553 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4554 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4556 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4557 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4558 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4559 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4561 num_channels
= MAX2(num_channels
, 3);
4563 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4564 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4567 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4568 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4569 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4571 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4573 Temp divided
= bld
.tmp(v1
);
4574 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4575 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4577 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4580 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4583 index
= bld
.vadd32(bld
.def(v1
),
4584 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4585 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4588 Temp channels
[num_channels
];
4589 unsigned channel_start
= 0;
4590 bool direct_fetch
= false;
4592 /* skip unused channels at the start */
4593 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4594 channel_start
= ffs(mask
) - 1;
4595 for (unsigned i
= 0; i
< channel_start
; i
++)
4596 channels
[i
] = Temp(0, s1
);
4597 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4598 num_channels
= 3 - (ffs(mask
) - 1);
4602 while (channel_start
< num_channels
) {
4603 unsigned fetch_component
= num_channels
- channel_start
;
4604 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4605 bool expanded
= false;
4607 /* use MUBUF when possible to avoid possible alignment issues */
4608 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4609 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4610 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4611 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4612 vtx_info
->chan_byte_size
== 4;
4613 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4615 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4617 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4618 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4619 fetch_component
= 4;
4624 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4626 Temp fetch_index
= index
;
4627 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4628 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4629 fetch_offset
= fetch_offset
% attrib_stride
;
4632 Operand
soffset(0u);
4633 if (fetch_offset
>= 4096) {
4634 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4635 fetch_offset
%= 4096;
4639 switch (fetch_bytes
) {
4641 assert(!use_mubuf
&& bitsize
== 16);
4642 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4645 if (bitsize
== 16) {
4647 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4649 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4653 assert(!use_mubuf
&& bitsize
== 16);
4654 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4657 if (bitsize
== 16) {
4659 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4661 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4665 assert(ctx
->options
->chip_class
>= GFX7
||
4666 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4667 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4670 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4673 unreachable("Unimplemented load_input vector size");
4677 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4678 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4679 num_channels
<= 3)) {
4680 direct_fetch
= true;
4683 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4688 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4689 fetch_offset
, false, false, true).instr
;
4692 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4693 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4696 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4698 if (fetch_component
== 1) {
4699 channels
[channel_start
] = fetch_dst
;
4701 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4702 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4703 bitsize
== 16 ? v2b
: v1
);
4706 channel_start
+= fetch_component
;
4709 if (!direct_fetch
) {
4710 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4711 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4713 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4714 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4715 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4717 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4718 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4719 unsigned num_temp
= 0;
4720 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4721 unsigned idx
= i
+ component
;
4722 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4723 Temp channel
= channels
[swizzle
[idx
]];
4724 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4725 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4726 vec
->operands
[i
] = Operand(channel
);
4730 } else if (is_float
&& idx
== 3) {
4731 vec
->operands
[i
] = Operand(0x3f800000u
);
4732 } else if (!is_float
&& idx
== 3) {
4733 vec
->operands
[i
] = Operand(1u);
4735 vec
->operands
[i
] = Operand(0u);
4738 vec
->definitions
[0] = Definition(dst
);
4739 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4740 emit_split_vector(ctx
, dst
, dst
.size());
4742 if (num_temp
== dst
.size())
4743 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4745 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4746 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4747 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4748 if (off_instr
->type
!= nir_instr_type_load_const
||
4749 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4750 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4753 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4754 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4756 assert(offset
->u32
== 0);
4758 /* the lower 15bit of the prim_mask contain the offset into LDS
4759 * while the upper bits contain the number of prims */
4760 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4761 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4762 Builder
bld(ctx
->program
, ctx
->block
);
4763 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4764 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4765 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4766 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4767 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4770 unsigned idx
= nir_intrinsic_base(instr
);
4771 unsigned component
= nir_intrinsic_component(instr
);
4772 unsigned vertex_id
= 2; /* P0 */
4774 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4775 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4776 switch (src0
->u32
) {
4778 vertex_id
= 2; /* P0 */
4781 vertex_id
= 0; /* P10 */
4784 vertex_id
= 1; /* P20 */
4787 unreachable("invalid vertex index");
4791 if (dst
.size() == 1) {
4792 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4794 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4795 for (unsigned i
= 0; i
< dst
.size(); i
++)
4796 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4797 vec
->definitions
[0] = Definition(dst
);
4798 bld
.insert(std::move(vec
));
4801 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4802 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4803 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4804 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4805 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4807 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4809 unreachable("Shader stage not implemented");
4813 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4815 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4817 Builder
bld(ctx
->program
, ctx
->block
);
4818 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4821 if (!nir_src_is_const(*vertex_src
)) {
4822 /* better code could be created, but this case probably doesn't happen
4823 * much in practice */
4824 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4825 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4828 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4829 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4831 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4833 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4836 if (vertex_offset
.id()) {
4837 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4838 Operand(i
), indirect_vertex
);
4839 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4841 vertex_offset
= elem
;
4845 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4846 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4848 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4849 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4850 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4851 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4852 Operand((vertex
% 2u) * 16u), Operand(16u));
4854 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4857 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4858 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4859 return offset_mul(ctx
, offs
, 4u);
4862 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4864 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4866 Builder
bld(ctx
->program
, ctx
->block
);
4867 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4868 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4870 if (ctx
->stage
== geometry_gs
) {
4871 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4872 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4873 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4874 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4875 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4876 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4877 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4879 unreachable("Unsupported GS stage.");
4883 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4885 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4887 Builder
bld(ctx
->program
, ctx
->block
);
4888 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4890 if (load_input_from_temps(ctx
, instr
, dst
))
4893 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4894 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4895 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4897 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4900 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4902 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4904 Builder
bld(ctx
->program
, ctx
->block
);
4906 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4907 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4908 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4910 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4911 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4913 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4916 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4918 switch (ctx
->shader
->info
.stage
) {
4919 case MESA_SHADER_GEOMETRY
:
4920 visit_load_gs_per_vertex_input(ctx
, instr
);
4922 case MESA_SHADER_TESS_CTRL
:
4923 visit_load_tcs_per_vertex_input(ctx
, instr
);
4925 case MESA_SHADER_TESS_EVAL
:
4926 visit_load_tes_per_vertex_input(ctx
, instr
);
4929 unreachable("Unimplemented shader stage");
4933 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4935 visit_load_tcs_output(ctx
, instr
, true);
4938 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4940 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4941 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4943 visit_store_tcs_output(ctx
, instr
, true);
4946 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4948 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4950 Builder
bld(ctx
->program
, ctx
->block
);
4951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4953 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4954 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4957 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4958 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4959 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4960 tes_w
= Operand(tmp
);
4963 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4964 emit_split_vector(ctx
, tess_coord
, 3);
4967 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4969 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4970 Builder
bld(ctx
->program
, ctx
->block
);
4971 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4972 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4973 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4976 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4980 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4982 Builder
bld(ctx
->program
, ctx
->block
);
4983 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4984 if (!nir_dest_is_divergent(instr
->dest
))
4985 index
= bld
.as_uniform(index
);
4986 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4987 unsigned binding
= nir_intrinsic_binding(instr
);
4990 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4991 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4992 unsigned offset
= layout
->binding
[binding
].offset
;
4994 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4995 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4996 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4997 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4998 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5001 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5002 stride
= layout
->binding
[binding
].size
;
5005 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5006 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5008 if (nir_const_index
) {
5009 const_index
= const_index
* stride
;
5010 } else if (index
.type() == RegType::vgpr
) {
5011 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5012 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5014 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5018 if (nir_const_index
) {
5019 const_index
= const_index
+ offset
;
5020 } else if (index
.type() == RegType::vgpr
) {
5021 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5023 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5027 if (nir_const_index
&& const_index
== 0) {
5029 } else if (index
.type() == RegType::vgpr
) {
5030 index
= bld
.vadd32(bld
.def(v1
),
5031 nir_const_index
? Operand(const_index
) : Operand(index
),
5034 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5035 nir_const_index
? Operand(const_index
) : Operand(index
),
5039 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5042 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5043 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5044 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5046 Builder
bld(ctx
->program
, ctx
->block
);
5048 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5050 offset
= bld
.as_uniform(offset
);
5052 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5055 info
.align_mul
= align_mul
;
5056 info
.align_offset
= align_offset
;
5058 emit_smem_load(ctx
, bld
, &info
);
5060 emit_mubuf_load(ctx
, bld
, &info
);
5063 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5065 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5066 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5068 Builder
bld(ctx
->program
, ctx
->block
);
5070 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5071 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5072 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5073 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5075 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5076 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5077 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5078 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5079 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5080 if (ctx
->options
->chip_class
>= GFX10
) {
5081 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5082 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5083 S_008F0C_RESOURCE_LEVEL(1);
5085 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5086 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5088 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5089 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5090 Operand(0xFFFFFFFFu
),
5091 Operand(desc_type
));
5092 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5093 rsrc
, upper_dwords
);
5095 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5096 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5098 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5099 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5100 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5103 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5105 Builder
bld(ctx
->program
, ctx
->block
);
5106 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5107 unsigned offset
= nir_intrinsic_base(instr
);
5108 unsigned count
= instr
->dest
.ssa
.num_components
;
5109 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5111 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5112 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5113 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5114 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5115 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5116 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5117 for (unsigned i
= 0; i
< count
; ++i
) {
5118 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5119 vec
->operands
[i
] = Operand
{elems
[i
]};
5121 vec
->definitions
[0] = Definition(dst
);
5122 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5123 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5128 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5129 if (offset
!= 0) // TODO check if index != 0 as well
5130 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5131 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5134 bool aligned
= true;
5136 if (instr
->dest
.ssa
.bit_size
== 8) {
5137 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5138 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5140 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5141 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5142 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5144 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5149 switch (vec
.size()) {
5151 op
= aco_opcode::s_load_dword
;
5154 op
= aco_opcode::s_load_dwordx2
;
5160 op
= aco_opcode::s_load_dwordx4
;
5166 op
= aco_opcode::s_load_dwordx8
;
5169 unreachable("unimplemented or forbidden load_push_constant.");
5172 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5175 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5176 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5181 emit_split_vector(ctx
, vec
, 4);
5182 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5183 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5184 emit_extract_vector(ctx
, vec
, 0, rc
),
5185 emit_extract_vector(ctx
, vec
, 1, rc
),
5186 emit_extract_vector(ctx
, vec
, 2, rc
));
5189 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5192 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5194 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5196 Builder
bld(ctx
->program
, ctx
->block
);
5198 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5199 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5200 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5201 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5202 if (ctx
->options
->chip_class
>= GFX10
) {
5203 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5204 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5205 S_008F0C_RESOURCE_LEVEL(1);
5207 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5208 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5211 unsigned base
= nir_intrinsic_base(instr
);
5212 unsigned range
= nir_intrinsic_range(instr
);
5214 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5215 if (base
&& offset
.type() == RegType::sgpr
)
5216 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5217 else if (base
&& offset
.type() == RegType::vgpr
)
5218 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5220 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5221 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5222 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5223 Operand(desc_type
));
5224 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5225 // TODO: get alignment information for subdword constants
5226 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5229 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5231 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5232 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5234 ctx
->program
->needs_exact
= true;
5236 // TODO: optimize uniform conditions
5237 Builder
bld(ctx
->program
, ctx
->block
);
5238 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5239 assert(src
.regClass() == bld
.lm
);
5240 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5241 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5242 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5246 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5248 Builder
bld(ctx
->program
, ctx
->block
);
5250 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5251 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5253 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5254 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5256 if (ctx
->block
->loop_nest_depth
&&
5257 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5258 /* we handle discards the same way as jump instructions */
5259 append_logical_end(ctx
->block
);
5261 /* in loops, discard behaves like break */
5262 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5263 ctx
->block
->kind
|= block_kind_discard
;
5266 /* uniform discard - loop ends here */
5267 assert(nir_instr_is_last(&instr
->instr
));
5268 ctx
->block
->kind
|= block_kind_uniform
;
5269 ctx
->cf_info
.has_branch
= true;
5270 bld
.branch(aco_opcode::p_branch
);
5271 add_linear_edge(ctx
->block
->index
, linear_target
);
5275 /* we add a break right behind the discard() instructions */
5276 ctx
->block
->kind
|= block_kind_break
;
5277 unsigned idx
= ctx
->block
->index
;
5279 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5280 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5282 /* remove critical edges from linear CFG */
5283 bld
.branch(aco_opcode::p_branch
);
5284 Block
* break_block
= ctx
->program
->create_and_insert_block();
5285 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5286 break_block
->kind
|= block_kind_uniform
;
5287 add_linear_edge(idx
, break_block
);
5288 add_linear_edge(break_block
->index
, linear_target
);
5289 bld
.reset(break_block
);
5290 bld
.branch(aco_opcode::p_branch
);
5292 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5293 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5294 add_linear_edge(idx
, continue_block
);
5295 append_logical_start(continue_block
);
5296 ctx
->block
= continue_block
;
5301 /* it can currently happen that NIR doesn't remove the unreachable code */
5302 if (!nir_instr_is_last(&instr
->instr
)) {
5303 ctx
->program
->needs_exact
= true;
5304 /* save exec somewhere temporarily so that it doesn't get
5305 * overwritten before the discard from outer exec masks */
5306 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5307 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5308 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5312 /* This condition is incorrect for uniformly branched discards in a loop
5313 * predicated by a divergent condition, but the above code catches that case
5314 * and the discard would end up turning into a discard_if.
5324 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5325 /* program just ends here */
5326 ctx
->block
->kind
|= block_kind_uniform
;
5327 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5328 0 /* enabled mask */, 9 /* dest */,
5329 false /* compressed */, true/* done */, true /* valid mask */);
5330 bld
.sopp(aco_opcode::s_endpgm
);
5331 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5333 ctx
->block
->kind
|= block_kind_discard
;
5334 /* branch and linear edge is added by visit_if() */
5338 enum aco_descriptor_type
{
5349 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5350 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5352 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5353 return dim
== ac_image_cube
||
5354 dim
== ac_image_1darray
||
5355 dim
== ac_image_2darray
||
5356 dim
== ac_image_2darraymsaa
;
5359 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5360 enum aco_descriptor_type desc_type
,
5361 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5363 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5364 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5365 if (it != ctx->tex_desc.end())
5368 Temp index
= Temp();
5369 bool index_set
= false;
5370 unsigned constant_index
= 0;
5371 unsigned descriptor_set
;
5372 unsigned base_index
;
5373 Builder
bld(ctx
->program
, ctx
->block
);
5376 assert(tex_instr
&& !image
);
5378 base_index
= tex_instr
->sampler_index
;
5380 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5381 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5385 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5386 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5388 constant_index
+= array_size
* const_value
->u32
;
5390 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5391 if (indirect
.type() == RegType::vgpr
)
5392 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5394 if (array_size
!= 1)
5395 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5401 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5405 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5407 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5408 base_index
= deref_instr
->var
->data
.binding
;
5411 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5412 list
= convert_pointer_to_64_bit(ctx
, list
);
5414 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5415 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5416 unsigned offset
= binding
->offset
;
5417 unsigned stride
= binding
->size
;
5421 assert(base_index
< layout
->binding_count
);
5423 switch (desc_type
) {
5424 case ACO_DESC_IMAGE
:
5426 opcode
= aco_opcode::s_load_dwordx8
;
5428 case ACO_DESC_FMASK
:
5430 opcode
= aco_opcode::s_load_dwordx8
;
5433 case ACO_DESC_SAMPLER
:
5435 opcode
= aco_opcode::s_load_dwordx4
;
5436 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5437 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5439 case ACO_DESC_BUFFER
:
5441 opcode
= aco_opcode::s_load_dwordx4
;
5443 case ACO_DESC_PLANE_0
:
5444 case ACO_DESC_PLANE_1
:
5446 opcode
= aco_opcode::s_load_dwordx8
;
5447 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5449 case ACO_DESC_PLANE_2
:
5451 opcode
= aco_opcode::s_load_dwordx4
;
5455 unreachable("invalid desc_type\n");
5458 offset
+= constant_index
* stride
;
5460 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5461 (!index_set
|| binding
->immutable_samplers_equal
)) {
5462 if (binding
->immutable_samplers_equal
)
5465 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5466 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5467 Operand(samplers
[constant_index
* 4 + 0]),
5468 Operand(samplers
[constant_index
* 4 + 1]),
5469 Operand(samplers
[constant_index
* 4 + 2]),
5470 Operand(samplers
[constant_index
* 4 + 3]));
5475 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5477 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5478 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5481 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5483 if (desc_type
== ACO_DESC_PLANE_2
) {
5485 for (unsigned i
= 0; i
< 8; i
++)
5486 components
[i
] = bld
.tmp(s1
);
5487 bld
.pseudo(aco_opcode::p_split_vector
,
5488 Definition(components
[0]),
5489 Definition(components
[1]),
5490 Definition(components
[2]),
5491 Definition(components
[3]),
5494 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5495 bld
.pseudo(aco_opcode::p_split_vector
,
5496 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5497 Definition(components
[4]),
5498 Definition(components
[5]),
5499 Definition(components
[6]),
5500 Definition(components
[7]),
5503 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5504 components
[0], components
[1], components
[2], components
[3],
5505 components
[4], components
[5], components
[6], components
[7]);
5511 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5514 case GLSL_SAMPLER_DIM_BUF
:
5516 case GLSL_SAMPLER_DIM_1D
:
5517 return array
? 2 : 1;
5518 case GLSL_SAMPLER_DIM_2D
:
5519 return array
? 3 : 2;
5520 case GLSL_SAMPLER_DIM_MS
:
5521 return array
? 4 : 3;
5522 case GLSL_SAMPLER_DIM_3D
:
5523 case GLSL_SAMPLER_DIM_CUBE
:
5525 case GLSL_SAMPLER_DIM_RECT
:
5526 case GLSL_SAMPLER_DIM_SUBPASS
:
5528 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5537 /* Adjust the sample index according to FMASK.
5539 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5540 * which is the identity mapping. Each nibble says which physical sample
5541 * should be fetched to get that sample.
5543 * For example, 0x11111100 means there are only 2 samples stored and
5544 * the second sample covers 3/4 of the pixel. When reading samples 0
5545 * and 1, return physical sample 0 (determined by the first two 0s
5546 * in FMASK), otherwise return physical sample 1.
5548 * The sample index should be adjusted as follows:
5549 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5551 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5553 Builder
bld(ctx
->program
, ctx
->block
);
5554 Temp fmask
= bld
.tmp(v1
);
5555 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5556 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5559 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5560 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5561 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5562 load
->operands
[0] = Operand(fmask_desc_ptr
);
5563 load
->operands
[1] = Operand(s4
); /* no sampler */
5564 load
->operands
[2] = Operand(coord
);
5565 load
->definitions
[0] = Definition(fmask
);
5572 ctx
->block
->instructions
.emplace_back(std::move(load
));
5574 Operand sample_index4
;
5575 if (sample_index
.isConstant()) {
5576 if (sample_index
.constantValue() < 16) {
5577 sample_index4
= Operand(sample_index
.constantValue() << 2);
5579 sample_index4
= Operand(0u);
5581 } else if (sample_index
.regClass() == s1
) {
5582 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5584 assert(sample_index
.regClass() == v1
);
5585 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5589 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5590 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5591 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5592 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5594 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5596 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5597 * resource descriptor is 0 (invalid),
5599 Temp compare
= bld
.tmp(bld
.lm
);
5600 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5601 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5603 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5605 /* Replace the MSAA sample index. */
5606 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5609 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5612 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5613 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5614 bool is_array
= glsl_sampler_type_is_array(type
);
5615 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5616 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5617 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5618 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5619 int count
= image_type_to_components_count(dim
, is_array
);
5620 std::vector
<Temp
> coords(count
);
5621 Builder
bld(ctx
->program
, ctx
->block
);
5625 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5626 /* get sample index */
5627 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5628 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5629 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5630 std::vector
<Temp
> fmask_load_address
;
5631 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5632 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5634 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5635 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5637 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5642 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5643 coords
.resize(coords
.size() + 1);
5644 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5646 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5648 for (int i
= 0; i
< count
; i
++)
5649 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5652 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5653 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5654 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5655 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5658 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5661 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5662 for (unsigned i
= 0; i
< coords
.size(); i
++)
5663 vec
->operands
[i
] = Operand(coords
[i
]);
5664 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5665 vec
->definitions
[0] = Definition(res
);
5666 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5671 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5673 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5674 if (semantics
& semantic_atomicrmw
)
5675 return memory_sync_info(storage
, semantics
);
5677 unsigned access
= nir_intrinsic_access(instr
);
5679 if (access
& ACCESS_VOLATILE
)
5680 semantics
|= semantic_volatile
;
5681 if (access
& ACCESS_CAN_REORDER
)
5682 semantics
|= semantic_can_reorder
| semantic_private
;
5684 return memory_sync_info(storage
, semantics
);
5687 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5689 Builder
bld(ctx
->program
, ctx
->block
);
5690 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5691 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5692 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5693 bool is_array
= glsl_sampler_type_is_array(type
);
5694 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5696 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5697 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5699 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5700 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5701 unsigned num_channels
= util_last_bit(mask
);
5702 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5703 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5706 switch (num_channels
) {
5708 opcode
= aco_opcode::buffer_load_format_x
;
5711 opcode
= aco_opcode::buffer_load_format_xy
;
5714 opcode
= aco_opcode::buffer_load_format_xyz
;
5717 opcode
= aco_opcode::buffer_load_format_xyzw
;
5720 unreachable(">4 channel buffer image load");
5722 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5723 load
->operands
[0] = Operand(rsrc
);
5724 load
->operands
[1] = Operand(vindex
);
5725 load
->operands
[2] = Operand((uint32_t) 0);
5727 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5730 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5731 load
->definitions
[0] = Definition(tmp
);
5733 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5734 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5736 ctx
->block
->instructions
.emplace_back(std::move(load
));
5738 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5742 Temp coords
= get_image_coords(ctx
, instr
, type
);
5743 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5745 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5746 unsigned num_components
= util_bitcount(dmask
);
5748 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5751 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5753 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5754 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5756 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5757 load
->operands
[0] = Operand(resource
);
5758 load
->operands
[1] = Operand(s4
); /* no sampler */
5759 load
->operands
[2] = Operand(coords
);
5760 load
->definitions
[0] = Definition(tmp
);
5761 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5762 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5763 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5764 load
->dmask
= dmask
;
5766 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5768 ctx
->block
->instructions
.emplace_back(std::move(load
));
5770 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5774 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5776 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5777 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5778 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5779 bool is_array
= glsl_sampler_type_is_array(type
);
5780 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5782 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5783 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5784 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5786 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5787 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5788 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5790 switch (data
.size()) {
5792 opcode
= aco_opcode::buffer_store_format_x
;
5795 opcode
= aco_opcode::buffer_store_format_xy
;
5798 opcode
= aco_opcode::buffer_store_format_xyz
;
5801 opcode
= aco_opcode::buffer_store_format_xyzw
;
5804 unreachable(">4 channel buffer image store");
5806 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5807 store
->operands
[0] = Operand(rsrc
);
5808 store
->operands
[1] = Operand(vindex
);
5809 store
->operands
[2] = Operand((uint32_t) 0);
5810 store
->operands
[3] = Operand(data
);
5811 store
->idxen
= true;
5814 store
->disable_wqm
= true;
5816 ctx
->program
->needs_exact
= true;
5817 ctx
->block
->instructions
.emplace_back(std::move(store
));
5821 assert(data
.type() == RegType::vgpr
);
5822 Temp coords
= get_image_coords(ctx
, instr
, type
);
5823 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5825 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5826 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5828 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5829 store
->operands
[0] = Operand(resource
);
5830 store
->operands
[1] = Operand(data
);
5831 store
->operands
[2] = Operand(coords
);
5834 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5835 store
->dmask
= (1 << data
.size()) - 1;
5837 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5838 store
->disable_wqm
= true;
5840 ctx
->program
->needs_exact
= true;
5841 ctx
->block
->instructions
.emplace_back(std::move(store
));
5845 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5847 /* return the previous value if dest is ever used */
5848 bool return_previous
= false;
5849 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5850 return_previous
= true;
5853 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5854 return_previous
= true;
5858 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5859 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5860 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5861 bool is_array
= glsl_sampler_type_is_array(type
);
5862 Builder
bld(ctx
->program
, ctx
->block
);
5864 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5865 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5867 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5868 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5870 aco_opcode buf_op
, image_op
;
5871 switch (instr
->intrinsic
) {
5872 case nir_intrinsic_image_deref_atomic_add
:
5873 buf_op
= aco_opcode::buffer_atomic_add
;
5874 image_op
= aco_opcode::image_atomic_add
;
5876 case nir_intrinsic_image_deref_atomic_umin
:
5877 buf_op
= aco_opcode::buffer_atomic_umin
;
5878 image_op
= aco_opcode::image_atomic_umin
;
5880 case nir_intrinsic_image_deref_atomic_imin
:
5881 buf_op
= aco_opcode::buffer_atomic_smin
;
5882 image_op
= aco_opcode::image_atomic_smin
;
5884 case nir_intrinsic_image_deref_atomic_umax
:
5885 buf_op
= aco_opcode::buffer_atomic_umax
;
5886 image_op
= aco_opcode::image_atomic_umax
;
5888 case nir_intrinsic_image_deref_atomic_imax
:
5889 buf_op
= aco_opcode::buffer_atomic_smax
;
5890 image_op
= aco_opcode::image_atomic_smax
;
5892 case nir_intrinsic_image_deref_atomic_and
:
5893 buf_op
= aco_opcode::buffer_atomic_and
;
5894 image_op
= aco_opcode::image_atomic_and
;
5896 case nir_intrinsic_image_deref_atomic_or
:
5897 buf_op
= aco_opcode::buffer_atomic_or
;
5898 image_op
= aco_opcode::image_atomic_or
;
5900 case nir_intrinsic_image_deref_atomic_xor
:
5901 buf_op
= aco_opcode::buffer_atomic_xor
;
5902 image_op
= aco_opcode::image_atomic_xor
;
5904 case nir_intrinsic_image_deref_atomic_exchange
:
5905 buf_op
= aco_opcode::buffer_atomic_swap
;
5906 image_op
= aco_opcode::image_atomic_swap
;
5908 case nir_intrinsic_image_deref_atomic_comp_swap
:
5909 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5910 image_op
= aco_opcode::image_atomic_cmpswap
;
5913 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5916 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5917 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5919 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5920 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5921 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5922 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5923 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5924 mubuf
->operands
[0] = Operand(resource
);
5925 mubuf
->operands
[1] = Operand(vindex
);
5926 mubuf
->operands
[2] = Operand((uint32_t)0);
5927 mubuf
->operands
[3] = Operand(data
);
5928 if (return_previous
)
5929 mubuf
->definitions
[0] = Definition(dst
);
5931 mubuf
->idxen
= true;
5932 mubuf
->glc
= return_previous
;
5933 mubuf
->dlc
= false; /* Not needed for atomics */
5934 mubuf
->disable_wqm
= true;
5936 ctx
->program
->needs_exact
= true;
5937 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5941 Temp coords
= get_image_coords(ctx
, instr
, type
);
5942 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5943 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5944 mimg
->operands
[0] = Operand(resource
);
5945 mimg
->operands
[1] = Operand(data
);
5946 mimg
->operands
[2] = Operand(coords
);
5947 if (return_previous
)
5948 mimg
->definitions
[0] = Definition(dst
);
5949 mimg
->glc
= return_previous
;
5950 mimg
->dlc
= false; /* Not needed for atomics */
5951 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5952 mimg
->dmask
= (1 << data
.size()) - 1;
5954 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5955 mimg
->disable_wqm
= true;
5957 ctx
->program
->needs_exact
= true;
5958 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5962 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5964 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5965 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5966 Builder
bld(ctx
->program
, ctx
->block
);
5968 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5970 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5971 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5973 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5974 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5976 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5977 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5979 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5980 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5981 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5982 if (dst
.type() == RegType::vgpr
)
5983 bld
.copy(Definition(dst
), shr_dst
);
5985 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5987 emit_extract_vector(ctx
, desc
, 2, dst
);
5991 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5993 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5994 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5995 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5996 bool is_array
= glsl_sampler_type_is_array(type
);
5997 Builder
bld(ctx
->program
, ctx
->block
);
5999 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6000 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6001 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6005 assert(nir_src_as_uint(instr
->src
[1]) == 0);
6006 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6009 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6011 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6013 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6014 mimg
->operands
[0] = Operand(resource
);
6015 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6016 mimg
->operands
[2] = Operand(lod
);
6017 uint8_t& dmask
= mimg
->dmask
;
6018 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6019 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6020 mimg
->da
= glsl_sampler_type_is_array(type
);
6021 Definition
& def
= mimg
->definitions
[0];
6022 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6024 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6025 glsl_sampler_type_is_array(type
)) {
6027 assert(instr
->dest
.ssa
.num_components
== 3);
6028 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6029 def
= Definition(tmp
);
6030 emit_split_vector(ctx
, tmp
, 3);
6032 /* divide 3rd value by 6 by multiplying with magic number */
6033 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6034 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6036 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6037 emit_extract_vector(ctx
, tmp
, 0, v1
),
6038 emit_extract_vector(ctx
, tmp
, 1, v1
),
6041 } else if (ctx
->options
->chip_class
== GFX9
&&
6042 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6043 glsl_sampler_type_is_array(type
)) {
6044 assert(instr
->dest
.ssa
.num_components
== 2);
6045 def
= Definition(dst
);
6048 def
= Definition(dst
);
6051 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6054 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6056 Builder
bld(ctx
->program
, ctx
->block
);
6057 unsigned num_components
= instr
->num_components
;
6059 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6060 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6061 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6063 unsigned access
= nir_intrinsic_access(instr
);
6064 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6065 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6067 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6068 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6069 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6071 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6072 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6074 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6075 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6076 get_memory_sync_info(instr
, storage_buffer
, 0));
6079 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6081 Builder
bld(ctx
->program
, ctx
->block
);
6082 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6083 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6084 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6085 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6087 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6088 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6090 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6091 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6092 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6093 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6094 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6096 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6098 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6099 ctx
->options
->chip_class
>= GFX8
&&
6100 ctx
->options
->chip_class
< GFX10_3
&&
6101 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6104 offset
= bld
.as_uniform(offset
);
6105 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6107 unsigned write_count
= 0;
6108 Temp write_datas
[32];
6109 unsigned offsets
[32];
6110 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6111 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6113 for (unsigned i
= 0; i
< write_count
; i
++) {
6114 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6115 if (smem
&& ctx
->stage
== fragment_fs
)
6116 op
= aco_opcode::p_fs_buffer_store_smem
;
6119 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6120 store
->operands
[0] = Operand(rsrc
);
6122 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6123 offset
, Operand(offsets
[i
]));
6124 store
->operands
[1] = Operand(off
);
6126 store
->operands
[1] = Operand(offset
);
6128 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6129 store
->operands
[1].setFixed(m0
);
6130 store
->operands
[2] = Operand(write_datas
[i
]);
6133 store
->disable_wqm
= true;
6135 ctx
->block
->instructions
.emplace_back(std::move(store
));
6136 ctx
->program
->wb_smem_l1_on_end
= true;
6137 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6138 ctx
->block
->kind
|= block_kind_needs_lowering
;
6139 ctx
->program
->needs_exact
= true;
6142 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6143 store
->operands
[0] = Operand(rsrc
);
6144 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6145 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6146 store
->operands
[3] = Operand(write_datas
[i
]);
6147 store
->offset
= offsets
[i
];
6148 store
->offen
= (offset
.type() == RegType::vgpr
);
6151 store
->disable_wqm
= true;
6153 ctx
->program
->needs_exact
= true;
6154 ctx
->block
->instructions
.emplace_back(std::move(store
));
6159 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6161 /* return the previous value if dest is ever used */
6162 bool return_previous
= false;
6163 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6164 return_previous
= true;
6167 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6168 return_previous
= true;
6172 Builder
bld(ctx
->program
, ctx
->block
);
6173 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6175 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6176 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6177 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6179 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6180 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6181 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6183 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6185 aco_opcode op32
, op64
;
6186 switch (instr
->intrinsic
) {
6187 case nir_intrinsic_ssbo_atomic_add
:
6188 op32
= aco_opcode::buffer_atomic_add
;
6189 op64
= aco_opcode::buffer_atomic_add_x2
;
6191 case nir_intrinsic_ssbo_atomic_imin
:
6192 op32
= aco_opcode::buffer_atomic_smin
;
6193 op64
= aco_opcode::buffer_atomic_smin_x2
;
6195 case nir_intrinsic_ssbo_atomic_umin
:
6196 op32
= aco_opcode::buffer_atomic_umin
;
6197 op64
= aco_opcode::buffer_atomic_umin_x2
;
6199 case nir_intrinsic_ssbo_atomic_imax
:
6200 op32
= aco_opcode::buffer_atomic_smax
;
6201 op64
= aco_opcode::buffer_atomic_smax_x2
;
6203 case nir_intrinsic_ssbo_atomic_umax
:
6204 op32
= aco_opcode::buffer_atomic_umax
;
6205 op64
= aco_opcode::buffer_atomic_umax_x2
;
6207 case nir_intrinsic_ssbo_atomic_and
:
6208 op32
= aco_opcode::buffer_atomic_and
;
6209 op64
= aco_opcode::buffer_atomic_and_x2
;
6211 case nir_intrinsic_ssbo_atomic_or
:
6212 op32
= aco_opcode::buffer_atomic_or
;
6213 op64
= aco_opcode::buffer_atomic_or_x2
;
6215 case nir_intrinsic_ssbo_atomic_xor
:
6216 op32
= aco_opcode::buffer_atomic_xor
;
6217 op64
= aco_opcode::buffer_atomic_xor_x2
;
6219 case nir_intrinsic_ssbo_atomic_exchange
:
6220 op32
= aco_opcode::buffer_atomic_swap
;
6221 op64
= aco_opcode::buffer_atomic_swap_x2
;
6223 case nir_intrinsic_ssbo_atomic_comp_swap
:
6224 op32
= aco_opcode::buffer_atomic_cmpswap
;
6225 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6228 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6230 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6231 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6232 mubuf
->operands
[0] = Operand(rsrc
);
6233 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6234 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6235 mubuf
->operands
[3] = Operand(data
);
6236 if (return_previous
)
6237 mubuf
->definitions
[0] = Definition(dst
);
6239 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6240 mubuf
->glc
= return_previous
;
6241 mubuf
->dlc
= false; /* Not needed for atomics */
6242 mubuf
->disable_wqm
= true;
6243 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6244 ctx
->program
->needs_exact
= true;
6245 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6248 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6250 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6251 Builder
bld(ctx
->program
, ctx
->block
);
6252 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6253 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6256 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6258 Builder
bld(ctx
->program
, ctx
->block
);
6259 unsigned num_components
= instr
->num_components
;
6260 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6262 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6263 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6264 num_components
, component_size
};
6265 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6266 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6267 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6268 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6269 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6270 * it's safe to use SMEM */
6271 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6272 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6273 emit_global_load(ctx
, bld
, &info
);
6275 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6276 emit_smem_load(ctx
, bld
, &info
);
6280 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6282 Builder
bld(ctx
->program
, ctx
->block
);
6283 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6284 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6286 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6287 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6288 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6289 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6291 if (ctx
->options
->chip_class
>= GFX7
)
6292 addr
= as_vgpr(ctx
, addr
);
6294 unsigned write_count
= 0;
6295 Temp write_datas
[32];
6296 unsigned offsets
[32];
6297 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6298 16, &write_count
, write_datas
, offsets
);
6300 for (unsigned i
= 0; i
< write_count
; i
++) {
6301 if (ctx
->options
->chip_class
>= GFX7
) {
6302 unsigned offset
= offsets
[i
];
6303 Temp store_addr
= addr
;
6304 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6305 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6306 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6307 Temp carry
= bld
.tmp(bld
.lm
);
6308 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6310 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6311 Operand(offset
), addr0
);
6312 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6314 carry
).def(1).setHint(vcc
);
6316 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6321 bool global
= ctx
->options
->chip_class
>= GFX9
;
6323 switch (write_datas
[i
].bytes()) {
6325 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6328 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6331 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6334 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6337 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6340 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6343 unreachable("store_global not implemented for this size.");
6346 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6347 flat
->operands
[0] = Operand(store_addr
);
6348 flat
->operands
[1] = Operand(s1
);
6349 flat
->operands
[2] = Operand(write_datas
[i
]);
6352 flat
->offset
= offset
;
6353 flat
->disable_wqm
= true;
6355 ctx
->program
->needs_exact
= true;
6356 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6358 assert(ctx
->options
->chip_class
== GFX6
);
6360 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6362 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6364 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6365 mubuf
->operands
[0] = Operand(rsrc
);
6366 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6367 mubuf
->operands
[2] = Operand(0u);
6368 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6371 mubuf
->offset
= offsets
[i
];
6372 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6373 mubuf
->disable_wqm
= true;
6375 ctx
->program
->needs_exact
= true;
6376 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6381 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6383 /* return the previous value if dest is ever used */
6384 bool return_previous
= false;
6385 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6386 return_previous
= true;
6389 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6390 return_previous
= true;
6394 Builder
bld(ctx
->program
, ctx
->block
);
6395 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6396 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6398 if (ctx
->options
->chip_class
>= GFX7
)
6399 addr
= as_vgpr(ctx
, addr
);
6401 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6402 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6403 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6405 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6407 aco_opcode op32
, op64
;
6409 if (ctx
->options
->chip_class
>= GFX7
) {
6410 bool global
= ctx
->options
->chip_class
>= GFX9
;
6411 switch (instr
->intrinsic
) {
6412 case nir_intrinsic_global_atomic_add
:
6413 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6414 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6416 case nir_intrinsic_global_atomic_imin
:
6417 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6418 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6420 case nir_intrinsic_global_atomic_umin
:
6421 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6422 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6424 case nir_intrinsic_global_atomic_imax
:
6425 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6426 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6428 case nir_intrinsic_global_atomic_umax
:
6429 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6430 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6432 case nir_intrinsic_global_atomic_and
:
6433 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6434 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6436 case nir_intrinsic_global_atomic_or
:
6437 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6438 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6440 case nir_intrinsic_global_atomic_xor
:
6441 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6442 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6444 case nir_intrinsic_global_atomic_exchange
:
6445 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6446 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6448 case nir_intrinsic_global_atomic_comp_swap
:
6449 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6450 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6453 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6456 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6457 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6458 flat
->operands
[0] = Operand(addr
);
6459 flat
->operands
[1] = Operand(s1
);
6460 flat
->operands
[2] = Operand(data
);
6461 if (return_previous
)
6462 flat
->definitions
[0] = Definition(dst
);
6463 flat
->glc
= return_previous
;
6464 flat
->dlc
= false; /* Not needed for atomics */
6466 flat
->disable_wqm
= true;
6467 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6468 ctx
->program
->needs_exact
= true;
6469 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6471 assert(ctx
->options
->chip_class
== GFX6
);
6473 switch (instr
->intrinsic
) {
6474 case nir_intrinsic_global_atomic_add
:
6475 op32
= aco_opcode::buffer_atomic_add
;
6476 op64
= aco_opcode::buffer_atomic_add_x2
;
6478 case nir_intrinsic_global_atomic_imin
:
6479 op32
= aco_opcode::buffer_atomic_smin
;
6480 op64
= aco_opcode::buffer_atomic_smin_x2
;
6482 case nir_intrinsic_global_atomic_umin
:
6483 op32
= aco_opcode::buffer_atomic_umin
;
6484 op64
= aco_opcode::buffer_atomic_umin_x2
;
6486 case nir_intrinsic_global_atomic_imax
:
6487 op32
= aco_opcode::buffer_atomic_smax
;
6488 op64
= aco_opcode::buffer_atomic_smax_x2
;
6490 case nir_intrinsic_global_atomic_umax
:
6491 op32
= aco_opcode::buffer_atomic_umax
;
6492 op64
= aco_opcode::buffer_atomic_umax_x2
;
6494 case nir_intrinsic_global_atomic_and
:
6495 op32
= aco_opcode::buffer_atomic_and
;
6496 op64
= aco_opcode::buffer_atomic_and_x2
;
6498 case nir_intrinsic_global_atomic_or
:
6499 op32
= aco_opcode::buffer_atomic_or
;
6500 op64
= aco_opcode::buffer_atomic_or_x2
;
6502 case nir_intrinsic_global_atomic_xor
:
6503 op32
= aco_opcode::buffer_atomic_xor
;
6504 op64
= aco_opcode::buffer_atomic_xor_x2
;
6506 case nir_intrinsic_global_atomic_exchange
:
6507 op32
= aco_opcode::buffer_atomic_swap
;
6508 op64
= aco_opcode::buffer_atomic_swap_x2
;
6510 case nir_intrinsic_global_atomic_comp_swap
:
6511 op32
= aco_opcode::buffer_atomic_cmpswap
;
6512 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6515 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6518 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6520 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6522 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6523 mubuf
->operands
[0] = Operand(rsrc
);
6524 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6525 mubuf
->operands
[2] = Operand(0u);
6526 mubuf
->operands
[3] = Operand(data
);
6527 if (return_previous
)
6528 mubuf
->definitions
[0] = Definition(dst
);
6529 mubuf
->glc
= return_previous
;
6532 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6533 mubuf
->disable_wqm
= true;
6534 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6535 ctx
->program
->needs_exact
= true;
6536 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6540 sync_scope
translate_nir_scope(nir_scope scope
)
6543 case NIR_SCOPE_NONE
:
6544 case NIR_SCOPE_INVOCATION
:
6545 return scope_invocation
;
6546 case NIR_SCOPE_SUBGROUP
:
6547 return scope_subgroup
;
6548 case NIR_SCOPE_WORKGROUP
:
6549 return scope_workgroup
;
6550 case NIR_SCOPE_QUEUE_FAMILY
:
6551 return scope_queuefamily
;
6552 case NIR_SCOPE_DEVICE
:
6553 return scope_device
;
6555 unreachable("invalid scope");
6558 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6559 Builder
bld(ctx
->program
, ctx
->block
);
6561 unsigned semantics
= 0;
6562 unsigned storage
= 0;
6563 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6564 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6566 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6567 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6568 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6569 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6570 storage
|= storage_shared
;
6571 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6572 storage
|= storage_shared
;
6574 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6575 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6576 semantics
|= semantic_acquire
| semantic_release
;
6577 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6578 semantics
|= semantic_acquire
| semantic_release
;
6580 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6582 bld
.barrier(aco_opcode::p_barrier
,
6583 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6587 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6589 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6590 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6591 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6592 Builder
bld(ctx
->program
, ctx
->block
);
6594 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6595 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6596 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6599 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6601 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6602 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6603 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6604 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6606 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6607 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6610 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6612 unsigned offset
= nir_intrinsic_base(instr
);
6613 Builder
bld(ctx
->program
, ctx
->block
);
6614 Operand m
= load_lds_size_m0(bld
);
6615 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6616 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6618 unsigned num_operands
= 3;
6619 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6620 switch(instr
->intrinsic
) {
6621 case nir_intrinsic_shared_atomic_add
:
6622 op32
= aco_opcode::ds_add_u32
;
6623 op64
= aco_opcode::ds_add_u64
;
6624 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6625 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6627 case nir_intrinsic_shared_atomic_imin
:
6628 op32
= aco_opcode::ds_min_i32
;
6629 op64
= aco_opcode::ds_min_i64
;
6630 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6631 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6633 case nir_intrinsic_shared_atomic_umin
:
6634 op32
= aco_opcode::ds_min_u32
;
6635 op64
= aco_opcode::ds_min_u64
;
6636 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6637 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6639 case nir_intrinsic_shared_atomic_imax
:
6640 op32
= aco_opcode::ds_max_i32
;
6641 op64
= aco_opcode::ds_max_i64
;
6642 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6643 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6645 case nir_intrinsic_shared_atomic_umax
:
6646 op32
= aco_opcode::ds_max_u32
;
6647 op64
= aco_opcode::ds_max_u64
;
6648 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6649 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6651 case nir_intrinsic_shared_atomic_and
:
6652 op32
= aco_opcode::ds_and_b32
;
6653 op64
= aco_opcode::ds_and_b64
;
6654 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6655 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6657 case nir_intrinsic_shared_atomic_or
:
6658 op32
= aco_opcode::ds_or_b32
;
6659 op64
= aco_opcode::ds_or_b64
;
6660 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6661 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6663 case nir_intrinsic_shared_atomic_xor
:
6664 op32
= aco_opcode::ds_xor_b32
;
6665 op64
= aco_opcode::ds_xor_b64
;
6666 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6667 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6669 case nir_intrinsic_shared_atomic_exchange
:
6670 op32
= aco_opcode::ds_write_b32
;
6671 op64
= aco_opcode::ds_write_b64
;
6672 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6673 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6675 case nir_intrinsic_shared_atomic_comp_swap
:
6676 op32
= aco_opcode::ds_cmpst_b32
;
6677 op64
= aco_opcode::ds_cmpst_b64
;
6678 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6679 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6682 case nir_intrinsic_shared_atomic_fadd
:
6683 op32
= aco_opcode::ds_add_f32
;
6684 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6685 op64
= aco_opcode::num_opcodes
;
6686 op64_rtn
= aco_opcode::num_opcodes
;
6689 unreachable("Unhandled shared atomic intrinsic");
6692 /* return the previous value if dest is ever used */
6693 bool return_previous
= false;
6694 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6695 return_previous
= true;
6698 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6699 return_previous
= true;
6704 if (data
.size() == 1) {
6705 assert(instr
->dest
.ssa
.bit_size
== 32);
6706 op
= return_previous
? op32_rtn
: op32
;
6708 assert(instr
->dest
.ssa
.bit_size
== 64);
6709 op
= return_previous
? op64_rtn
: op64
;
6712 if (offset
> 65535) {
6713 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6717 aco_ptr
<DS_instruction
> ds
;
6718 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6719 ds
->operands
[0] = Operand(address
);
6720 ds
->operands
[1] = Operand(data
);
6721 if (num_operands
== 4)
6722 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6723 ds
->operands
[num_operands
- 1] = m
;
6724 ds
->offset0
= offset
;
6725 if (return_previous
)
6726 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6727 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6728 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6731 Temp
get_scratch_resource(isel_context
*ctx
)
6733 Builder
bld(ctx
->program
, ctx
->block
);
6734 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6735 if (ctx
->stage
!= compute_cs
)
6736 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6738 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6739 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6741 if (ctx
->program
->chip_class
>= GFX10
) {
6742 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6743 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6744 S_008F0C_RESOURCE_LEVEL(1);
6745 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6746 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6747 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6750 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6751 if (ctx
->program
->chip_class
<= GFX8
)
6752 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6754 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6757 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6758 Builder
bld(ctx
->program
, ctx
->block
);
6759 Temp rsrc
= get_scratch_resource(ctx
);
6760 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6761 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6763 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6764 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6765 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6766 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6767 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6768 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6769 info
.soffset
= ctx
->program
->scratch_offset
;
6770 emit_scratch_load(ctx
, bld
, &info
);
6773 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6774 Builder
bld(ctx
->program
, ctx
->block
);
6775 Temp rsrc
= get_scratch_resource(ctx
);
6776 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6777 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6779 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6780 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6782 unsigned write_count
= 0;
6783 Temp write_datas
[32];
6784 unsigned offsets
[32];
6785 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6786 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6787 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6789 for (unsigned i
= 0; i
< write_count
; i
++) {
6790 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6791 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6792 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6796 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6797 uint8_t log2_ps_iter_samples
;
6798 if (ctx
->program
->info
->ps
.force_persample
) {
6799 log2_ps_iter_samples
=
6800 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6802 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6805 /* The bit pattern matches that used by fixed function fragment
6807 static const unsigned ps_iter_masks
[] = {
6808 0xffff, /* not used */
6814 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6816 Builder
bld(ctx
->program
, ctx
->block
);
6818 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6819 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6820 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6821 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6822 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6823 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6826 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6827 Builder
bld(ctx
->program
, ctx
->block
);
6829 unsigned stream
= nir_intrinsic_stream_id(instr
);
6830 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6831 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6832 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6835 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6837 unsigned num_components
=
6838 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6839 assert(num_components
);
6841 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6842 unsigned stream_offset
= 0;
6843 for (unsigned i
= 0; i
< stream
; i
++) {
6844 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6845 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6848 /* Limit on the stride field for <= GFX7. */
6849 assert(stride
< (1 << 14));
6851 Temp gsvs_dwords
[4];
6852 for (unsigned i
= 0; i
< 4; i
++)
6853 gsvs_dwords
[i
] = bld
.tmp(s1
);
6854 bld
.pseudo(aco_opcode::p_split_vector
,
6855 Definition(gsvs_dwords
[0]),
6856 Definition(gsvs_dwords
[1]),
6857 Definition(gsvs_dwords
[2]),
6858 Definition(gsvs_dwords
[3]),
6861 if (stream_offset
) {
6862 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6864 Temp carry
= bld
.tmp(s1
);
6865 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6866 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6869 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6870 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6872 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6873 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6875 unsigned offset
= 0;
6876 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6877 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6880 for (unsigned j
= 0; j
< 4; j
++) {
6881 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6884 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6885 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6886 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6887 if (const_offset
>= 4096u) {
6888 if (vaddr_offset
.isUndefined())
6889 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6891 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6892 const_offset
%= 4096u;
6895 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6896 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6897 mtbuf
->operands
[1] = vaddr_offset
;
6898 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6899 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6900 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6901 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6902 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6903 mtbuf
->offset
= const_offset
;
6906 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6907 bld
.insert(std::move(mtbuf
));
6910 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6913 /* outputs for the next vertex are undefined and keeping them around can
6914 * create invalid IR with control flow */
6915 ctx
->outputs
.mask
[i
] = 0;
6918 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6921 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6923 Builder
bld(ctx
->program
, ctx
->block
);
6925 if (cluster_size
== 1) {
6927 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6928 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6929 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6930 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6931 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6932 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6933 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6934 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6935 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6936 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6937 //subgroupAnd(val) -> (exec & ~val) == 0
6938 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6939 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6940 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6941 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6942 //subgroupOr(val) -> (val & exec) != 0
6943 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6944 return bool_to_vector_condition(ctx
, tmp
);
6945 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6946 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6947 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6948 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6949 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6950 return bool_to_vector_condition(ctx
, tmp
);
6952 //subgroupClustered{And,Or,Xor}(val, n) ->
6953 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6954 //cluster_offset = ~(n - 1) & lane_id
6955 //cluster_mask = ((1 << n) - 1)
6956 //subgroupClusteredAnd():
6957 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6958 //subgroupClusteredOr():
6959 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6960 //subgroupClusteredXor():
6961 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6962 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6963 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6966 if (op
== nir_op_iand
)
6967 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6969 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6971 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6973 if (ctx
->program
->chip_class
<= GFX7
)
6974 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6975 else if (ctx
->program
->wave_size
== 64)
6976 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6978 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6979 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6980 if (cluster_mask
!= 0xffffffff)
6981 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6983 Definition cmp_def
= Definition();
6984 if (op
== nir_op_iand
) {
6985 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6986 } else if (op
== nir_op_ior
) {
6987 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6988 } else if (op
== nir_op_ixor
) {
6989 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6990 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6991 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6993 cmp_def
.setHint(vcc
);
6994 return cmp_def
.getTemp();
6998 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7000 Builder
bld(ctx
->program
, ctx
->block
);
7002 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7003 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7004 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7006 if (op
== nir_op_iand
)
7007 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7009 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7011 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7012 Temp lo
= lohi
.def(0).getTemp();
7013 Temp hi
= lohi
.def(1).getTemp();
7014 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7016 Definition cmp_def
= Definition();
7017 if (op
== nir_op_iand
)
7018 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7019 else if (op
== nir_op_ior
)
7020 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7021 else if (op
== nir_op_ixor
)
7022 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7023 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7024 cmp_def
.setHint(vcc
);
7025 return cmp_def
.getTemp();
7028 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7030 Builder
bld(ctx
->program
, ctx
->block
);
7032 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7033 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7034 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7035 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7036 if (op
== nir_op_iand
)
7037 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7038 else if (op
== nir_op_ior
)
7039 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7040 else if (op
== nir_op_ixor
)
7041 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7047 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7049 Builder
bld(ctx
->program
, ctx
->block
);
7050 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7051 if (src
.regClass().type() == RegType::vgpr
) {
7052 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7053 } else if (src
.regClass() == s1
) {
7054 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7055 } else if (src
.regClass() == s2
) {
7056 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7058 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7062 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7064 Builder
bld(ctx
->program
, ctx
->block
);
7065 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7066 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7067 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7069 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7070 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7071 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7072 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7075 if (ctx
->program
->chip_class
>= GFX8
) {
7076 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7077 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7078 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7079 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7080 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7081 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7083 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7084 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7085 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7086 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7087 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7088 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7089 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7090 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7091 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7092 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7095 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7096 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7097 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7098 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7099 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7100 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7101 Temp wqm1
= bld
.tmp(v1
);
7102 emit_wqm(ctx
, tmp1
, wqm1
, true);
7103 Temp wqm2
= bld
.tmp(v1
);
7104 emit_wqm(ctx
, tmp2
, wqm2
, true);
7105 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7109 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7111 Builder
bld(ctx
->program
, ctx
->block
);
7112 switch(instr
->intrinsic
) {
7113 case nir_intrinsic_load_barycentric_sample
:
7114 case nir_intrinsic_load_barycentric_pixel
:
7115 case nir_intrinsic_load_barycentric_centroid
: {
7116 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7117 Temp bary
= Temp(0, s2
);
7119 case INTERP_MODE_SMOOTH
:
7120 case INTERP_MODE_NONE
:
7121 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7122 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7123 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7124 bary
= ctx
->persp_centroid
;
7125 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7126 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7128 case INTERP_MODE_NOPERSPECTIVE
:
7129 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7130 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7131 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7132 bary
= ctx
->linear_centroid
;
7133 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7134 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7139 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7140 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7141 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7142 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7143 Operand(p1
), Operand(p2
));
7144 emit_split_vector(ctx
, dst
, 2);
7147 case nir_intrinsic_load_barycentric_model
: {
7148 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7150 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7151 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7152 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7153 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7154 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7155 Operand(p1
), Operand(p2
), Operand(p3
));
7156 emit_split_vector(ctx
, dst
, 3);
7159 case nir_intrinsic_load_barycentric_at_sample
: {
7160 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7161 switch (ctx
->options
->key
.fs
.num_samples
) {
7162 case 2: sample_pos_offset
+= 1 << 3; break;
7163 case 4: sample_pos_offset
+= 3 << 3; break;
7164 case 8: sample_pos_offset
+= 7 << 3; break;
7168 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7169 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7170 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7171 //TODO: bounds checking?
7172 if (addr
.type() == RegType::sgpr
) {
7175 sample_pos_offset
+= const_addr
->u32
<< 3;
7176 offset
= Operand(sample_pos_offset
);
7177 } else if (ctx
->options
->chip_class
>= GFX9
) {
7178 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7180 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7181 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7184 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7185 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7187 } else if (ctx
->options
->chip_class
>= GFX9
) {
7188 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7189 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7190 } else if (ctx
->options
->chip_class
>= GFX7
) {
7191 /* addr += private_segment_buffer + sample_pos_offset */
7192 Temp tmp0
= bld
.tmp(s1
);
7193 Temp tmp1
= bld
.tmp(s1
);
7194 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7195 Definition scc_tmp
= bld
.def(s1
, scc
);
7196 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7197 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7198 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7199 Temp pck0
= bld
.tmp(v1
);
7200 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7201 tmp1
= as_vgpr(ctx
, tmp1
);
7202 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7203 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7205 /* sample_pos = flat_load_dwordx2 addr */
7206 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7208 assert(ctx
->options
->chip_class
== GFX6
);
7210 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7211 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7212 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7214 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7215 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7217 sample_pos
= bld
.tmp(v2
);
7219 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7220 load
->definitions
[0] = Definition(sample_pos
);
7221 load
->operands
[0] = Operand(rsrc
);
7222 load
->operands
[1] = Operand(addr
);
7223 load
->operands
[2] = Operand(0u);
7224 load
->offset
= sample_pos_offset
;
7226 load
->addr64
= true;
7229 load
->disable_wqm
= false;
7230 ctx
->block
->instructions
.emplace_back(std::move(load
));
7233 /* sample_pos -= 0.5 */
7234 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7235 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7236 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7237 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7238 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7240 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7243 case nir_intrinsic_load_barycentric_at_offset
: {
7244 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7245 RegClass rc
= RegClass(offset
.type(), 1);
7246 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7247 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7248 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7251 case nir_intrinsic_load_front_face
: {
7252 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7253 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7256 case nir_intrinsic_load_view_index
: {
7257 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7258 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7259 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7265 case nir_intrinsic_load_layer_id
: {
7266 unsigned idx
= nir_intrinsic_base(instr
);
7267 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7268 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7271 case nir_intrinsic_load_frag_coord
: {
7272 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7275 case nir_intrinsic_load_sample_pos
: {
7276 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7277 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7278 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7279 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7280 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7283 case nir_intrinsic_load_tess_coord
:
7284 visit_load_tess_coord(ctx
, instr
);
7286 case nir_intrinsic_load_interpolated_input
:
7287 visit_load_interpolated_input(ctx
, instr
);
7289 case nir_intrinsic_store_output
:
7290 visit_store_output(ctx
, instr
);
7292 case nir_intrinsic_load_input
:
7293 case nir_intrinsic_load_input_vertex
:
7294 visit_load_input(ctx
, instr
);
7296 case nir_intrinsic_load_output
:
7297 visit_load_output(ctx
, instr
);
7299 case nir_intrinsic_load_per_vertex_input
:
7300 visit_load_per_vertex_input(ctx
, instr
);
7302 case nir_intrinsic_load_per_vertex_output
:
7303 visit_load_per_vertex_output(ctx
, instr
);
7305 case nir_intrinsic_store_per_vertex_output
:
7306 visit_store_per_vertex_output(ctx
, instr
);
7308 case nir_intrinsic_load_ubo
:
7309 visit_load_ubo(ctx
, instr
);
7311 case nir_intrinsic_load_push_constant
:
7312 visit_load_push_constant(ctx
, instr
);
7314 case nir_intrinsic_load_constant
:
7315 visit_load_constant(ctx
, instr
);
7317 case nir_intrinsic_vulkan_resource_index
:
7318 visit_load_resource(ctx
, instr
);
7320 case nir_intrinsic_discard
:
7321 visit_discard(ctx
, instr
);
7323 case nir_intrinsic_discard_if
:
7324 visit_discard_if(ctx
, instr
);
7326 case nir_intrinsic_load_shared
:
7327 visit_load_shared(ctx
, instr
);
7329 case nir_intrinsic_store_shared
:
7330 visit_store_shared(ctx
, instr
);
7332 case nir_intrinsic_shared_atomic_add
:
7333 case nir_intrinsic_shared_atomic_imin
:
7334 case nir_intrinsic_shared_atomic_umin
:
7335 case nir_intrinsic_shared_atomic_imax
:
7336 case nir_intrinsic_shared_atomic_umax
:
7337 case nir_intrinsic_shared_atomic_and
:
7338 case nir_intrinsic_shared_atomic_or
:
7339 case nir_intrinsic_shared_atomic_xor
:
7340 case nir_intrinsic_shared_atomic_exchange
:
7341 case nir_intrinsic_shared_atomic_comp_swap
:
7342 case nir_intrinsic_shared_atomic_fadd
:
7343 visit_shared_atomic(ctx
, instr
);
7345 case nir_intrinsic_image_deref_load
:
7346 visit_image_load(ctx
, instr
);
7348 case nir_intrinsic_image_deref_store
:
7349 visit_image_store(ctx
, instr
);
7351 case nir_intrinsic_image_deref_atomic_add
:
7352 case nir_intrinsic_image_deref_atomic_umin
:
7353 case nir_intrinsic_image_deref_atomic_imin
:
7354 case nir_intrinsic_image_deref_atomic_umax
:
7355 case nir_intrinsic_image_deref_atomic_imax
:
7356 case nir_intrinsic_image_deref_atomic_and
:
7357 case nir_intrinsic_image_deref_atomic_or
:
7358 case nir_intrinsic_image_deref_atomic_xor
:
7359 case nir_intrinsic_image_deref_atomic_exchange
:
7360 case nir_intrinsic_image_deref_atomic_comp_swap
:
7361 visit_image_atomic(ctx
, instr
);
7363 case nir_intrinsic_image_deref_size
:
7364 visit_image_size(ctx
, instr
);
7366 case nir_intrinsic_load_ssbo
:
7367 visit_load_ssbo(ctx
, instr
);
7369 case nir_intrinsic_store_ssbo
:
7370 visit_store_ssbo(ctx
, instr
);
7372 case nir_intrinsic_load_global
:
7373 visit_load_global(ctx
, instr
);
7375 case nir_intrinsic_store_global
:
7376 visit_store_global(ctx
, instr
);
7378 case nir_intrinsic_global_atomic_add
:
7379 case nir_intrinsic_global_atomic_imin
:
7380 case nir_intrinsic_global_atomic_umin
:
7381 case nir_intrinsic_global_atomic_imax
:
7382 case nir_intrinsic_global_atomic_umax
:
7383 case nir_intrinsic_global_atomic_and
:
7384 case nir_intrinsic_global_atomic_or
:
7385 case nir_intrinsic_global_atomic_xor
:
7386 case nir_intrinsic_global_atomic_exchange
:
7387 case nir_intrinsic_global_atomic_comp_swap
:
7388 visit_global_atomic(ctx
, instr
);
7390 case nir_intrinsic_ssbo_atomic_add
:
7391 case nir_intrinsic_ssbo_atomic_imin
:
7392 case nir_intrinsic_ssbo_atomic_umin
:
7393 case nir_intrinsic_ssbo_atomic_imax
:
7394 case nir_intrinsic_ssbo_atomic_umax
:
7395 case nir_intrinsic_ssbo_atomic_and
:
7396 case nir_intrinsic_ssbo_atomic_or
:
7397 case nir_intrinsic_ssbo_atomic_xor
:
7398 case nir_intrinsic_ssbo_atomic_exchange
:
7399 case nir_intrinsic_ssbo_atomic_comp_swap
:
7400 visit_atomic_ssbo(ctx
, instr
);
7402 case nir_intrinsic_load_scratch
:
7403 visit_load_scratch(ctx
, instr
);
7405 case nir_intrinsic_store_scratch
:
7406 visit_store_scratch(ctx
, instr
);
7408 case nir_intrinsic_get_buffer_size
:
7409 visit_get_buffer_size(ctx
, instr
);
7411 case nir_intrinsic_scoped_barrier
:
7412 emit_scoped_barrier(ctx
, instr
);
7414 case nir_intrinsic_load_num_work_groups
: {
7415 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7416 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7417 emit_split_vector(ctx
, dst
, 3);
7420 case nir_intrinsic_load_local_invocation_id
: {
7421 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7422 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7423 emit_split_vector(ctx
, dst
, 3);
7426 case nir_intrinsic_load_work_group_id
: {
7427 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7428 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7429 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7430 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7431 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7432 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7433 emit_split_vector(ctx
, dst
, 3);
7436 case nir_intrinsic_load_local_invocation_index
: {
7437 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7439 /* The tg_size bits [6:11] contain the subgroup id,
7440 * we need this multiplied by the wave size, and then OR the thread id to it.
7442 if (ctx
->program
->wave_size
== 64) {
7443 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7444 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7445 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7446 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7448 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7449 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7450 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7451 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7455 case nir_intrinsic_load_subgroup_id
: {
7456 if (ctx
->stage
== compute_cs
) {
7457 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7458 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7460 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7464 case nir_intrinsic_load_subgroup_invocation
: {
7465 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7468 case nir_intrinsic_load_num_subgroups
: {
7469 if (ctx
->stage
== compute_cs
)
7470 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7471 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7473 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7476 case nir_intrinsic_ballot
: {
7477 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7478 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7479 Definition tmp
= bld
.def(dst
.regClass());
7480 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7481 if (instr
->src
[0].ssa
->bit_size
== 1) {
7482 assert(src
.regClass() == bld
.lm
);
7483 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7484 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7485 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7486 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7487 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7489 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7491 if (dst
.size() != bld
.lm
.size()) {
7492 /* Wave32 with ballot size set to 64 */
7493 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7495 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7498 case nir_intrinsic_shuffle
:
7499 case nir_intrinsic_read_invocation
: {
7500 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7501 if (!nir_src_is_divergent(instr
->src
[0])) {
7502 emit_uniform_subgroup(ctx
, instr
, src
);
7504 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7505 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7506 tid
= bld
.as_uniform(tid
);
7507 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7508 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7509 Temp tmp
= bld
.tmp(v1
);
7510 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7511 if (dst
.type() == RegType::vgpr
)
7512 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7514 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7515 } else if (src
.regClass() == v1
) {
7516 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7517 } else if (src
.regClass() == v2
) {
7518 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7520 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7521 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7523 emit_split_vector(ctx
, dst
, 2);
7524 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7525 assert(src
.regClass() == bld
.lm
);
7526 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7527 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7528 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7529 assert(src
.regClass() == bld
.lm
);
7531 if (ctx
->program
->chip_class
<= GFX7
)
7532 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7533 else if (ctx
->program
->wave_size
== 64)
7534 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7536 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7537 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7538 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7539 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7541 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7546 case nir_intrinsic_load_sample_id
: {
7547 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7548 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7551 case nir_intrinsic_load_sample_mask_in
: {
7552 visit_load_sample_mask_in(ctx
, instr
);
7555 case nir_intrinsic_read_first_invocation
: {
7556 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7557 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7558 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7560 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7562 } else if (src
.regClass() == v2
) {
7563 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7564 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7565 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7566 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7567 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7568 emit_split_vector(ctx
, dst
, 2);
7569 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7570 assert(src
.regClass() == bld
.lm
);
7571 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7572 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7573 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7574 } else if (src
.regClass() == s1
) {
7575 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7576 } else if (src
.regClass() == s2
) {
7577 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7579 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7583 case nir_intrinsic_vote_all
: {
7584 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7585 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7586 assert(src
.regClass() == bld
.lm
);
7587 assert(dst
.regClass() == bld
.lm
);
7589 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7590 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7591 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7594 case nir_intrinsic_vote_any
: {
7595 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7596 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7597 assert(src
.regClass() == bld
.lm
);
7598 assert(dst
.regClass() == bld
.lm
);
7600 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7601 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7604 case nir_intrinsic_reduce
:
7605 case nir_intrinsic_inclusive_scan
:
7606 case nir_intrinsic_exclusive_scan
: {
7607 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7608 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7609 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7610 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7611 nir_intrinsic_cluster_size(instr
) : 0;
7612 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7614 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7615 emit_uniform_subgroup(ctx
, instr
, src
);
7616 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7617 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7619 else if (op
== nir_op_iadd
)
7621 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7623 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7625 switch (instr
->intrinsic
) {
7626 case nir_intrinsic_reduce
:
7627 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7629 case nir_intrinsic_exclusive_scan
:
7630 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7632 case nir_intrinsic_inclusive_scan
:
7633 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7638 } else if (cluster_size
== 1) {
7639 bld
.copy(Definition(dst
), src
);
7641 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7643 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7647 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7648 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7663 unreachable("unknown reduction op");
7669 switch (instr
->intrinsic
) {
7670 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7671 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7672 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7674 unreachable("unknown reduce intrinsic");
7677 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7678 reduce
->operands
[0] = Operand(src
);
7679 // filled in by aco_reduce_assign.cpp, used internally as part of the
7681 assert(dst
.size() == 1 || dst
.size() == 2);
7682 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7683 reduce
->operands
[2] = Operand(v1
.as_linear());
7685 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7686 reduce
->definitions
[0] = Definition(tmp_dst
);
7687 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7688 reduce
->definitions
[2] = Definition();
7689 reduce
->definitions
[3] = Definition(scc
, s1
);
7690 reduce
->definitions
[4] = Definition();
7691 reduce
->reduce_op
= reduce_op
;
7692 reduce
->cluster_size
= cluster_size
;
7693 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7695 emit_wqm(ctx
, tmp_dst
, dst
);
7699 case nir_intrinsic_quad_broadcast
: {
7700 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7701 if (!nir_dest_is_divergent(instr
->dest
)) {
7702 emit_uniform_subgroup(ctx
, instr
, src
);
7704 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7705 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7706 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7708 if (instr
->dest
.ssa
.bit_size
== 1) {
7709 assert(src
.regClass() == bld
.lm
);
7710 assert(dst
.regClass() == bld
.lm
);
7711 uint32_t half_mask
= 0x11111111u
<< lane
;
7712 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7713 Temp tmp
= bld
.tmp(bld
.lm
);
7714 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7715 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7716 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7717 emit_wqm(ctx
, tmp
, dst
);
7718 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7719 Temp tmp
= bld
.tmp(v1
);
7720 if (ctx
->program
->chip_class
>= GFX8
)
7721 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7723 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7724 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7725 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7726 Temp tmp
= bld
.tmp(v1
);
7727 if (ctx
->program
->chip_class
>= GFX8
)
7728 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7730 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7731 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7732 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7733 if (ctx
->program
->chip_class
>= GFX8
)
7734 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7736 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7737 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7738 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7739 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7740 if (ctx
->program
->chip_class
>= GFX8
) {
7741 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7742 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7744 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7745 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7747 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7748 emit_split_vector(ctx
, dst
, 2);
7750 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7755 case nir_intrinsic_quad_swap_horizontal
:
7756 case nir_intrinsic_quad_swap_vertical
:
7757 case nir_intrinsic_quad_swap_diagonal
:
7758 case nir_intrinsic_quad_swizzle_amd
: {
7759 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7760 if (!nir_dest_is_divergent(instr
->dest
)) {
7761 emit_uniform_subgroup(ctx
, instr
, src
);
7764 uint16_t dpp_ctrl
= 0;
7765 switch (instr
->intrinsic
) {
7766 case nir_intrinsic_quad_swap_horizontal
:
7767 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7769 case nir_intrinsic_quad_swap_vertical
:
7770 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7772 case nir_intrinsic_quad_swap_diagonal
:
7773 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7775 case nir_intrinsic_quad_swizzle_amd
:
7776 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7781 if (ctx
->program
->chip_class
< GFX8
)
7782 dpp_ctrl
|= (1 << 15);
7784 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7785 if (instr
->dest
.ssa
.bit_size
== 1) {
7786 assert(src
.regClass() == bld
.lm
);
7787 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7788 if (ctx
->program
->chip_class
>= GFX8
)
7789 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7791 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7792 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7793 emit_wqm(ctx
, tmp
, dst
);
7794 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7795 Temp tmp
= bld
.tmp(v1
);
7796 if (ctx
->program
->chip_class
>= GFX8
)
7797 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7799 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7800 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7801 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7802 Temp tmp
= bld
.tmp(v1
);
7803 if (ctx
->program
->chip_class
>= GFX8
)
7804 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7806 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7807 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7808 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7810 if (ctx
->program
->chip_class
>= GFX8
)
7811 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7813 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7814 emit_wqm(ctx
, tmp
, dst
);
7815 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7816 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7817 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7818 if (ctx
->program
->chip_class
>= GFX8
) {
7819 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7820 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7822 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7823 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7825 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7826 emit_split_vector(ctx
, dst
, 2);
7828 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7832 case nir_intrinsic_masked_swizzle_amd
: {
7833 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7834 if (!nir_dest_is_divergent(instr
->dest
)) {
7835 emit_uniform_subgroup(ctx
, instr
, src
);
7838 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7839 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7840 if (instr
->dest
.ssa
.bit_size
== 1) {
7841 assert(src
.regClass() == bld
.lm
);
7842 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7843 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7844 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7845 emit_wqm(ctx
, tmp
, dst
);
7846 } else if (dst
.regClass() == v1b
) {
7847 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7848 emit_extract_vector(ctx
, tmp
, 0, dst
);
7849 } else if (dst
.regClass() == v2b
) {
7850 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7851 emit_extract_vector(ctx
, tmp
, 0, dst
);
7852 } else if (dst
.regClass() == v1
) {
7853 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7854 } else if (dst
.regClass() == v2
) {
7855 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7856 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7857 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7858 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7859 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7860 emit_split_vector(ctx
, dst
, 2);
7862 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7866 case nir_intrinsic_write_invocation_amd
: {
7867 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7868 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7869 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7870 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7871 if (dst
.regClass() == v1
) {
7872 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7873 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7874 } else if (dst
.regClass() == v2
) {
7875 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7876 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7879 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7880 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7881 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7882 emit_split_vector(ctx
, dst
, 2);
7884 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7888 case nir_intrinsic_mbcnt_amd
: {
7889 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7890 RegClass rc
= RegClass(src
.type(), 1);
7891 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7893 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7894 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7895 emit_wqm(ctx
, wqm_tmp
, dst
);
7898 case nir_intrinsic_load_helper_invocation
: {
7899 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7900 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7901 ctx
->block
->kind
|= block_kind_needs_lowering
;
7902 ctx
->program
->needs_exact
= true;
7905 case nir_intrinsic_is_helper_invocation
: {
7906 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7907 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7908 ctx
->block
->kind
|= block_kind_needs_lowering
;
7909 ctx
->program
->needs_exact
= true;
7912 case nir_intrinsic_demote
:
7913 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7915 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7916 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7917 ctx
->block
->kind
|= block_kind_uses_demote
;
7918 ctx
->program
->needs_exact
= true;
7920 case nir_intrinsic_demote_if
: {
7921 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7922 assert(src
.regClass() == bld
.lm
);
7923 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7924 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7926 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7927 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7928 ctx
->block
->kind
|= block_kind_uses_demote
;
7929 ctx
->program
->needs_exact
= true;
7932 case nir_intrinsic_first_invocation
: {
7933 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7934 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7937 case nir_intrinsic_shader_clock
: {
7938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7939 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
7940 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
7941 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
7942 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
7945 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7946 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7947 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
7949 emit_split_vector(ctx
, dst
, 2);
7952 case nir_intrinsic_load_vertex_id_zero_base
: {
7953 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7954 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7957 case nir_intrinsic_load_first_vertex
: {
7958 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7959 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7962 case nir_intrinsic_load_base_instance
: {
7963 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7964 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7967 case nir_intrinsic_load_instance_id
: {
7968 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7969 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7972 case nir_intrinsic_load_draw_id
: {
7973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7974 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7977 case nir_intrinsic_load_invocation_id
: {
7978 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7980 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7981 if (ctx
->options
->chip_class
>= GFX10
)
7982 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7984 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7985 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7986 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7987 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7989 unreachable("Unsupported stage for load_invocation_id");
7994 case nir_intrinsic_load_primitive_id
: {
7995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7997 switch (ctx
->shader
->info
.stage
) {
7998 case MESA_SHADER_GEOMETRY
:
7999 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8001 case MESA_SHADER_TESS_CTRL
:
8002 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8004 case MESA_SHADER_TESS_EVAL
:
8005 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8008 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8013 case nir_intrinsic_load_patch_vertices_in
: {
8014 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8015 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8017 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8018 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8021 case nir_intrinsic_emit_vertex_with_counter
: {
8022 visit_emit_vertex_with_counter(ctx
, instr
);
8025 case nir_intrinsic_end_primitive_with_counter
: {
8026 unsigned stream
= nir_intrinsic_stream_id(instr
);
8027 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8030 case nir_intrinsic_set_vertex_count
: {
8031 /* unused, the HW keeps track of this for us */
8035 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8043 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8044 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8045 enum glsl_base_type
*stype
)
8047 nir_deref_instr
*texture_deref_instr
= NULL
;
8048 nir_deref_instr
*sampler_deref_instr
= NULL
;
8051 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8052 switch (instr
->src
[i
].src_type
) {
8053 case nir_tex_src_texture_deref
:
8054 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8056 case nir_tex_src_sampler_deref
:
8057 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8059 case nir_tex_src_plane
:
8060 plane
= nir_src_as_int(instr
->src
[i
].src
);
8067 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8069 if (!sampler_deref_instr
)
8070 sampler_deref_instr
= texture_deref_instr
;
8073 assert(instr
->op
!= nir_texop_txf_ms
&&
8074 instr
->op
!= nir_texop_samples_identical
);
8075 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8076 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8077 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8078 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8079 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8080 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8082 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8085 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8087 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8088 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8089 Builder
bld(ctx
->program
, ctx
->block
);
8091 /* to avoid unnecessary moves, we split and recombine sampler and image */
8092 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8093 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8094 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8095 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8096 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8097 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8098 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8099 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8101 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8102 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8103 img
[0], img
[1], img
[2], img
[3],
8104 img
[4], img
[5], img
[6], img
[7]);
8105 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8106 samp
[0], samp
[1], samp
[2], samp
[3]);
8109 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8110 instr
->op
== nir_texop_samples_identical
))
8111 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8114 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8115 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8117 Builder
bld(ctx
->program
, ctx
->block
);
8119 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8120 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8121 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8123 Operand
neg_one(0xbf800000u
);
8124 Operand
one(0x3f800000u
);
8125 Operand
two(0x40000000u
);
8126 Operand
four(0x40800000u
);
8128 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8129 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8130 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8132 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8133 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8134 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8135 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8138 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8139 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8140 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8142 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8145 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8146 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8147 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8150 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8151 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8153 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8154 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8157 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8159 Builder
bld(ctx
->program
, ctx
->block
);
8160 Temp ma
, tc
, sc
, id
;
8161 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8162 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8165 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8167 // see comment in ac_prepare_cube_coords()
8168 if (ctx
->options
->chip_class
<= GFX8
)
8169 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8172 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8174 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8175 vop3a
->operands
[0] = Operand(ma
);
8176 vop3a
->abs
[0] = true;
8177 Temp invma
= bld
.tmp(v1
);
8178 vop3a
->definitions
[0] = Definition(invma
);
8179 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8181 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8183 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8185 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8187 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8189 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8192 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8193 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8195 for (unsigned i
= 0; i
< 2; i
++) {
8196 // see comment in ac_prepare_cube_coords()
8198 Temp deriv_sc
, deriv_tc
;
8199 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8200 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8202 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8204 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8205 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8206 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8207 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8208 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8209 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8210 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8213 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8214 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8218 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8225 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8227 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8229 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8230 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8233 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8234 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8235 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8239 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8241 Builder
bld(ctx
->program
, ctx
->block
);
8242 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8243 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8244 has_clamped_lod
= false;
8245 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8246 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8247 clamped_lod
= Temp();
8248 std::vector
<Temp
> coords
;
8249 std::vector
<Temp
> derivs
;
8250 nir_const_value
*sample_index_cv
= NULL
;
8251 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8252 enum glsl_base_type stype
;
8253 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8255 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8256 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8257 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8258 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8260 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8261 switch (instr
->src
[i
].src_type
) {
8262 case nir_tex_src_coord
: {
8263 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8264 for (unsigned i
= 0; i
< coord
.size(); i
++)
8265 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8268 case nir_tex_src_bias
:
8269 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8272 case nir_tex_src_lod
: {
8273 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8275 if (val
&& val
->f32
<= 0.0) {
8278 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8283 case nir_tex_src_min_lod
:
8284 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8285 has_clamped_lod
= true;
8287 case nir_tex_src_comparator
:
8288 if (instr
->is_shadow
) {
8289 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8293 case nir_tex_src_offset
:
8294 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8295 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8298 case nir_tex_src_ddx
:
8299 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8302 case nir_tex_src_ddy
:
8303 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8306 case nir_tex_src_ms_index
:
8307 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8308 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8309 has_sample_index
= true;
8311 case nir_tex_src_texture_offset
:
8312 case nir_tex_src_sampler_offset
:
8318 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8319 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8321 if (instr
->op
== nir_texop_texture_samples
) {
8322 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8324 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8325 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8326 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8328 Operand default_sample
= Operand(1u);
8329 if (ctx
->options
->robust_buffer_access
) {
8330 /* Extract the second dword of the descriptor, if it's
8331 * all zero, then it's a null descriptor.
8333 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8334 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8335 default_sample
= Operand(is_non_null_descriptor
);
8338 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8339 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8340 samples
, default_sample
, bld
.scc(is_msaa
));
8344 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8345 aco_ptr
<Instruction
> tmp_instr
;
8346 Temp acc
, pack
= Temp();
8348 uint32_t pack_const
= 0;
8349 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8350 if (!const_offset
[i
])
8352 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8355 if (offset
.type() == RegType::sgpr
) {
8356 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8357 if (const_offset
[i
])
8360 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8361 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8364 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8367 if (pack
== Temp()) {
8370 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8374 if (pack_const
&& pack
!= Temp())
8375 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8377 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8378 if (const_offset
[i
])
8381 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8382 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8385 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8388 if (pack
== Temp()) {
8391 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8395 if (pack_const
&& pack
!= Temp())
8396 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8398 if (pack_const
&& pack
== Temp())
8399 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8400 else if (pack
== Temp())
8406 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8407 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8409 /* pack derivatives */
8410 if (has_ddx
|| has_ddy
) {
8411 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8412 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8413 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8414 derivs
= {ddx
, zero
, ddy
, zero
};
8416 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8417 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8418 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8419 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8424 if (instr
->coord_components
> 1 &&
8425 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8427 instr
->op
!= nir_texop_txf
)
8428 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8430 if (instr
->coord_components
> 2 &&
8431 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8432 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8433 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8434 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8436 instr
->op
!= nir_texop_txf
&&
8437 instr
->op
!= nir_texop_txf_ms
&&
8438 instr
->op
!= nir_texop_fragment_fetch
&&
8439 instr
->op
!= nir_texop_fragment_mask_fetch
)
8440 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8442 if (ctx
->options
->chip_class
== GFX9
&&
8443 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8444 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8445 assert(coords
.size() > 0 && coords
.size() < 3);
8447 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8448 Operand((uint32_t) 0) :
8449 Operand((uint32_t) 0x3f000000)));
8452 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8454 if (instr
->op
== nir_texop_samples_identical
)
8455 resource
= fmask_ptr
;
8457 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8458 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8459 instr
->op
!= nir_texop_txs
&&
8460 instr
->op
!= nir_texop_fragment_fetch
&&
8461 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8462 assert(has_sample_index
);
8463 Operand
op(sample_index
);
8464 if (sample_index_cv
)
8465 op
= Operand(sample_index_cv
->u32
);
8466 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8469 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8470 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8471 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8472 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8477 /* Build tex instruction */
8478 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8479 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8480 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8482 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8485 /* gather4 selects the component by dmask and always returns vec4 */
8486 if (instr
->op
== nir_texop_tg4
) {
8487 assert(instr
->dest
.ssa
.num_components
== 4);
8488 if (instr
->is_shadow
)
8491 dmask
= 1 << instr
->component
;
8492 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8493 tmp_dst
= bld
.tmp(v4
);
8494 } else if (instr
->op
== nir_texop_samples_identical
) {
8495 tmp_dst
= bld
.tmp(v1
);
8496 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8497 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8500 aco_ptr
<MIMG_instruction
> tex
;
8501 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8503 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8505 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8506 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8509 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8510 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8512 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8513 tex
->operands
[0] = Operand(resource
);
8514 tex
->operands
[1] = Operand(s4
); /* no sampler */
8515 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8516 if (ctx
->options
->chip_class
== GFX9
&&
8517 instr
->op
== nir_texop_txs
&&
8518 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8520 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8521 } else if (instr
->op
== nir_texop_query_levels
) {
8522 tex
->dmask
= 1 << 3;
8527 tex
->definitions
[0] = Definition(tmp_dst
);
8529 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8532 /* divide 3rd value by 6 by multiplying with magic number */
8533 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8534 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8535 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8536 assert(instr
->dest
.ssa
.num_components
== 3);
8537 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8538 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8539 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8540 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8545 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8549 Temp tg4_compare_cube_wa64
= Temp();
8551 if (tg4_integer_workarounds
) {
8552 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8553 tex
->operands
[0] = Operand(resource
);
8554 tex
->operands
[1] = Operand(s4
); /* no sampler */
8555 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8559 Temp size
= bld
.tmp(v2
);
8560 tex
->definitions
[0] = Definition(size
);
8561 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8562 emit_split_vector(ctx
, size
, size
.size());
8565 for (unsigned i
= 0; i
< 2; i
++) {
8566 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8567 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8568 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8569 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8572 Temp new_coords
[2] = {
8573 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8574 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8577 if (tg4_integer_cube_workaround
) {
8578 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8579 Temp desc
[resource
.size()];
8580 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8581 Format::PSEUDO
, 1, resource
.size())};
8582 split
->operands
[0] = Operand(resource
);
8583 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8584 desc
[i
] = bld
.tmp(s1
);
8585 split
->definitions
[i
] = Definition(desc
[i
]);
8587 ctx
->block
->instructions
.emplace_back(std::move(split
));
8589 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8590 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8591 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8594 if (stype
== GLSL_TYPE_UINT
) {
8595 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8596 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8597 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8598 bld
.scc(compare_cube_wa
));
8600 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8601 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8602 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8603 bld
.scc(compare_cube_wa
));
8605 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8606 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8608 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8610 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8611 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8612 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8614 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8615 Format::PSEUDO
, resource
.size(), 1)};
8616 for (unsigned i
= 0; i
< resource
.size(); i
++)
8617 vec
->operands
[i
] = Operand(desc
[i
]);
8618 resource
= bld
.tmp(resource
.regClass());
8619 vec
->definitions
[0] = Definition(resource
);
8620 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8622 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8623 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8624 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8625 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8627 coords
[0] = new_coords
[0];
8628 coords
[1] = new_coords
[1];
8631 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8632 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8634 assert(coords
.size() == 1);
8635 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8639 op
= aco_opcode::buffer_load_format_x
; break;
8641 op
= aco_opcode::buffer_load_format_xy
; break;
8643 op
= aco_opcode::buffer_load_format_xyz
; break;
8645 op
= aco_opcode::buffer_load_format_xyzw
; break;
8647 unreachable("Tex instruction loads more than 4 components.");
8650 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8651 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8654 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8656 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8657 mubuf
->operands
[0] = Operand(resource
);
8658 mubuf
->operands
[1] = Operand(coords
[0]);
8659 mubuf
->operands
[2] = Operand((uint32_t) 0);
8660 mubuf
->definitions
[0] = Definition(tmp_dst
);
8661 mubuf
->idxen
= true;
8662 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8664 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8668 /* gather MIMG address components */
8669 std::vector
<Temp
> args
;
8671 args
.emplace_back(offset
);
8673 args
.emplace_back(bias
);
8675 args
.emplace_back(compare
);
8677 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8679 args
.insert(args
.end(), coords
.begin(), coords
.end());
8680 if (has_sample_index
)
8681 args
.emplace_back(sample_index
);
8683 args
.emplace_back(lod
);
8684 if (has_clamped_lod
)
8685 args
.emplace_back(clamped_lod
);
8687 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8688 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8689 vec
->definitions
[0] = Definition(arg
);
8690 for (unsigned i
= 0; i
< args
.size(); i
++)
8691 vec
->operands
[i
] = Operand(args
[i
]);
8692 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8695 if (instr
->op
== nir_texop_txf
||
8696 instr
->op
== nir_texop_txf_ms
||
8697 instr
->op
== nir_texop_samples_identical
||
8698 instr
->op
== nir_texop_fragment_fetch
||
8699 instr
->op
== nir_texop_fragment_mask_fetch
) {
8700 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8701 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8702 tex
->operands
[0] = Operand(resource
);
8703 tex
->operands
[1] = Operand(s4
); /* no sampler */
8704 tex
->operands
[2] = Operand(arg
);
8709 tex
->definitions
[0] = Definition(tmp_dst
);
8710 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8712 if (instr
->op
== nir_texop_samples_identical
) {
8713 assert(dmask
== 1 && dst
.regClass() == v1
);
8714 assert(dst
.id() != tmp_dst
.id());
8716 Temp tmp
= bld
.tmp(bld
.lm
);
8717 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8718 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8721 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8726 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8727 aco_opcode opcode
= aco_opcode::image_sample
;
8728 if (has_offset
) { /* image_sample_*_o */
8729 if (has_clamped_lod
) {
8731 opcode
= aco_opcode::image_sample_c_cl_o
;
8733 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8735 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8737 opcode
= aco_opcode::image_sample_cl_o
;
8739 opcode
= aco_opcode::image_sample_d_cl_o
;
8741 opcode
= aco_opcode::image_sample_b_cl_o
;
8743 } else if (has_compare
) {
8744 opcode
= aco_opcode::image_sample_c_o
;
8746 opcode
= aco_opcode::image_sample_c_d_o
;
8748 opcode
= aco_opcode::image_sample_c_b_o
;
8750 opcode
= aco_opcode::image_sample_c_lz_o
;
8752 opcode
= aco_opcode::image_sample_c_l_o
;
8754 opcode
= aco_opcode::image_sample_o
;
8756 opcode
= aco_opcode::image_sample_d_o
;
8758 opcode
= aco_opcode::image_sample_b_o
;
8760 opcode
= aco_opcode::image_sample_lz_o
;
8762 opcode
= aco_opcode::image_sample_l_o
;
8764 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8766 opcode
= aco_opcode::image_sample_c_cl
;
8768 opcode
= aco_opcode::image_sample_c_d_cl
;
8770 opcode
= aco_opcode::image_sample_c_b_cl
;
8772 opcode
= aco_opcode::image_sample_cl
;
8774 opcode
= aco_opcode::image_sample_d_cl
;
8776 opcode
= aco_opcode::image_sample_b_cl
;
8778 } else { /* no offset */
8780 opcode
= aco_opcode::image_sample_c
;
8782 opcode
= aco_opcode::image_sample_c_d
;
8784 opcode
= aco_opcode::image_sample_c_b
;
8786 opcode
= aco_opcode::image_sample_c_lz
;
8788 opcode
= aco_opcode::image_sample_c_l
;
8790 opcode
= aco_opcode::image_sample
;
8792 opcode
= aco_opcode::image_sample_d
;
8794 opcode
= aco_opcode::image_sample_b
;
8796 opcode
= aco_opcode::image_sample_lz
;
8798 opcode
= aco_opcode::image_sample_l
;
8802 if (instr
->op
== nir_texop_tg4
) {
8803 if (has_offset
) { /* image_gather4_*_o */
8805 opcode
= aco_opcode::image_gather4_c_lz_o
;
8807 opcode
= aco_opcode::image_gather4_c_l_o
;
8809 opcode
= aco_opcode::image_gather4_c_b_o
;
8811 opcode
= aco_opcode::image_gather4_lz_o
;
8813 opcode
= aco_opcode::image_gather4_l_o
;
8815 opcode
= aco_opcode::image_gather4_b_o
;
8819 opcode
= aco_opcode::image_gather4_c_lz
;
8821 opcode
= aco_opcode::image_gather4_c_l
;
8823 opcode
= aco_opcode::image_gather4_c_b
;
8825 opcode
= aco_opcode::image_gather4_lz
;
8827 opcode
= aco_opcode::image_gather4_l
;
8829 opcode
= aco_opcode::image_gather4_b
;
8832 } else if (instr
->op
== nir_texop_lod
) {
8833 opcode
= aco_opcode::image_get_lod
;
8836 /* we don't need the bias, sample index, compare value or offset to be
8837 * computed in WQM but if the p_create_vector copies the coordinates, then it
8838 * needs to be in WQM */
8839 if (ctx
->stage
== fragment_fs
&&
8840 !has_derivs
&& !has_lod
&& !level_zero
&&
8841 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8842 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8843 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8845 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8846 tex
->operands
[0] = Operand(resource
);
8847 tex
->operands
[1] = Operand(sampler
);
8848 tex
->operands
[2] = Operand(arg
);
8852 tex
->definitions
[0] = Definition(tmp_dst
);
8853 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8855 if (tg4_integer_cube_workaround
) {
8856 assert(tmp_dst
.id() != dst
.id());
8857 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8859 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8861 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8862 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8864 if (stype
== GLSL_TYPE_UINT
)
8865 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8867 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8868 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8870 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8871 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8872 val
[0], val
[1], val
[2], val
[3]);
8874 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8875 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8880 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8882 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8883 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8885 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8886 if (ctx
->program
->wave_size
== 64)
8887 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8889 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8891 return Operand(tmp
);
8895 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8897 aco_ptr
<Pseudo_instruction
> phi
;
8898 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8899 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8901 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8902 logical
|= ctx
->block
->kind
& block_kind_merge
;
8903 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8905 /* we want a sorted list of sources, since the predecessor list is also sorted */
8906 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8907 nir_foreach_phi_src(src
, instr
)
8908 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8910 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8911 unsigned num_operands
= 0;
8912 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8913 unsigned num_defined
= 0;
8914 unsigned cur_pred_idx
= 0;
8915 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8916 if (cur_pred_idx
< preds
.size()) {
8917 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8918 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8919 unsigned skipped
= 0;
8920 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8922 if (cur_pred_idx
+ skipped
< preds
.size()) {
8923 for (unsigned i
= 0; i
< skipped
; i
++)
8924 operands
[num_operands
++] = Operand(dst
.regClass());
8925 cur_pred_idx
+= skipped
;
8930 /* Handle missing predecessors at the end. This shouldn't happen with loop
8931 * headers and we can't ignore these sources for loop header phis. */
8932 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8935 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
8936 operands
[num_operands
++] = op
;
8937 num_defined
+= !op
.isUndefined();
8939 /* handle block_kind_continue_or_break at loop exit blocks */
8940 while (cur_pred_idx
++ < preds
.size())
8941 operands
[num_operands
++] = Operand(dst
.regClass());
8943 /* If the loop ends with a break, still add a linear continue edge in case
8944 * that break is divergent or continue_or_break is used. We'll either remove
8945 * this operand later in visit_loop() if it's not necessary or replace the
8946 * undef with something correct. */
8947 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8948 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8949 nir_block
*last
= nir_loop_last_block(loop
);
8950 if (last
->successors
[0] != instr
->instr
.block
)
8951 operands
[num_operands
++] = Operand(RegClass());
8954 if (num_defined
== 0) {
8955 Builder
bld(ctx
->program
, ctx
->block
);
8956 if (dst
.regClass() == s1
) {
8957 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8958 } else if (dst
.regClass() == v1
) {
8959 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8961 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8962 for (unsigned i
= 0; i
< dst
.size(); i
++)
8963 vec
->operands
[i
] = Operand(0u);
8964 vec
->definitions
[0] = Definition(dst
);
8965 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8970 /* we can use a linear phi in some cases if one src is undef */
8971 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8972 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8974 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8975 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8976 assert(invert
->kind
& block_kind_invert
);
8978 unsigned then_block
= invert
->linear_preds
[0];
8980 Block
* insert_block
= NULL
;
8981 for (unsigned i
= 0; i
< num_operands
; i
++) {
8982 Operand op
= operands
[i
];
8983 if (op
.isUndefined())
8985 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8986 phi
->operands
[0] = op
;
8989 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8990 phi
->operands
[1] = Operand(dst
.regClass());
8991 phi
->definitions
[0] = Definition(dst
);
8992 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8996 /* try to scalarize vector phis */
8997 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8998 // TODO: scalarize linear phis on divergent ifs
8999 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9000 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9001 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9002 Operand src
= operands
[i
];
9003 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9004 can_scalarize
= false;
9006 if (can_scalarize
) {
9007 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9008 assert(dst
.size() % num_components
== 0);
9009 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9011 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9012 for (unsigned k
= 0; k
< num_components
; k
++) {
9013 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9014 for (unsigned i
= 0; i
< num_operands
; i
++) {
9015 Operand src
= operands
[i
];
9016 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9018 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9019 phi
->definitions
[0] = Definition(phi_dst
);
9020 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9021 new_vec
[k
] = phi_dst
;
9022 vec
->operands
[k
] = Operand(phi_dst
);
9024 vec
->definitions
[0] = Definition(dst
);
9025 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9026 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9031 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9032 for (unsigned i
= 0; i
< num_operands
; i
++)
9033 phi
->operands
[i
] = operands
[i
];
9034 phi
->definitions
[0] = Definition(dst
);
9035 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9039 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9041 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9043 assert(dst
.type() == RegType::sgpr
);
9045 if (dst
.size() == 1) {
9046 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9048 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9049 for (unsigned i
= 0; i
< dst
.size(); i
++)
9050 vec
->operands
[i
] = Operand(0u);
9051 vec
->definitions
[0] = Definition(dst
);
9052 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9056 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9058 Builder
bld(ctx
->program
, ctx
->block
);
9059 Block
*logical_target
;
9060 append_logical_end(ctx
->block
);
9061 unsigned idx
= ctx
->block
->index
;
9063 switch (instr
->type
) {
9064 case nir_jump_break
:
9065 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9066 add_logical_edge(idx
, logical_target
);
9067 ctx
->block
->kind
|= block_kind_break
;
9069 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9070 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9071 /* uniform break - directly jump out of the loop */
9072 ctx
->block
->kind
|= block_kind_uniform
;
9073 ctx
->cf_info
.has_branch
= true;
9074 bld
.branch(aco_opcode::p_branch
);
9075 add_linear_edge(idx
, logical_target
);
9078 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9079 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9081 case nir_jump_continue
:
9082 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9083 add_logical_edge(idx
, logical_target
);
9084 ctx
->block
->kind
|= block_kind_continue
;
9086 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9087 /* for potential uniform breaks after this continue,
9088 we must ensure that they are handled correctly */
9089 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9090 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9091 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9093 /* uniform continue - directly jump to the loop header */
9094 ctx
->block
->kind
|= block_kind_uniform
;
9095 ctx
->cf_info
.has_branch
= true;
9096 bld
.branch(aco_opcode::p_branch
);
9097 add_linear_edge(idx
, logical_target
);
9102 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9106 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9107 ctx
->cf_info
.exec_potentially_empty_break
= true;
9108 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9111 /* remove critical edges from linear CFG */
9112 bld
.branch(aco_opcode::p_branch
);
9113 Block
* break_block
= ctx
->program
->create_and_insert_block();
9114 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9115 break_block
->kind
|= block_kind_uniform
;
9116 add_linear_edge(idx
, break_block
);
9117 /* the loop_header pointer might be invalidated by this point */
9118 if (instr
->type
== nir_jump_continue
)
9119 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9120 add_linear_edge(break_block
->index
, logical_target
);
9121 bld
.reset(break_block
);
9122 bld
.branch(aco_opcode::p_branch
);
9124 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9125 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9126 add_linear_edge(idx
, continue_block
);
9127 append_logical_start(continue_block
);
9128 ctx
->block
= continue_block
;
9132 void visit_block(isel_context
*ctx
, nir_block
*block
)
9134 nir_foreach_instr(instr
, block
) {
9135 switch (instr
->type
) {
9136 case nir_instr_type_alu
:
9137 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9139 case nir_instr_type_load_const
:
9140 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9142 case nir_instr_type_intrinsic
:
9143 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9145 case nir_instr_type_tex
:
9146 visit_tex(ctx
, nir_instr_as_tex(instr
));
9148 case nir_instr_type_phi
:
9149 visit_phi(ctx
, nir_instr_as_phi(instr
));
9151 case nir_instr_type_ssa_undef
:
9152 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9154 case nir_instr_type_deref
:
9156 case nir_instr_type_jump
:
9157 visit_jump(ctx
, nir_instr_as_jump(instr
));
9160 isel_err(instr
, "Unknown NIR instr type");
9165 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9166 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9171 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9172 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9174 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9175 RegClass rc
= vals
[0].regClass();
9177 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9179 unsigned next_pred
= 1;
9181 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9182 Block
& block
= ctx
->program
->blocks
[idx
];
9183 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9184 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9188 if (block
.kind
& block_kind_continue
) {
9189 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9194 bool all_same
= true;
9195 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9196 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9200 val
= vals
[block
.linear_preds
[0] - first
];
9202 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9203 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9204 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9205 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9206 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9207 phi
->definitions
[0] = Definition(val
.getTemp());
9208 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9210 vals
[idx
- first
] = val
;
9213 return vals
[last
- first
];
9216 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9218 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9219 append_logical_end(ctx
->block
);
9220 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9221 Builder
bld(ctx
->program
, ctx
->block
);
9222 bld
.branch(aco_opcode::p_branch
);
9223 unsigned loop_preheader_idx
= ctx
->block
->index
;
9225 Block loop_exit
= Block();
9226 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9227 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9229 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9230 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9231 loop_header
->kind
|= block_kind_loop_header
;
9232 add_edge(loop_preheader_idx
, loop_header
);
9233 ctx
->block
= loop_header
;
9235 /* emit loop body */
9236 unsigned loop_header_idx
= loop_header
->index
;
9237 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9238 append_logical_start(ctx
->block
);
9239 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9241 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9242 if (!ctx
->cf_info
.has_branch
) {
9243 append_logical_end(ctx
->block
);
9244 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9245 /* Discards can result in code running with an empty exec mask.
9246 * This would result in divergent breaks not ever being taken. As a
9247 * workaround, break the loop when the loop mask is empty instead of
9248 * always continuing. */
9249 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9250 unsigned block_idx
= ctx
->block
->index
;
9252 /* create helper blocks to avoid critical edges */
9253 Block
*break_block
= ctx
->program
->create_and_insert_block();
9254 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9255 break_block
->kind
= block_kind_uniform
;
9256 bld
.reset(break_block
);
9257 bld
.branch(aco_opcode::p_branch
);
9258 add_linear_edge(block_idx
, break_block
);
9259 add_linear_edge(break_block
->index
, &loop_exit
);
9261 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9262 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9263 continue_block
->kind
= block_kind_uniform
;
9264 bld
.reset(continue_block
);
9265 bld
.branch(aco_opcode::p_branch
);
9266 add_linear_edge(block_idx
, continue_block
);
9267 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9269 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9270 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9271 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9273 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9274 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9275 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9277 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9280 bld
.reset(ctx
->block
);
9281 bld
.branch(aco_opcode::p_branch
);
9284 /* Fixup phis in loop header from unreachable blocks.
9285 * has_branch/has_divergent_branch also indicates if the loop ends with a
9286 * break/continue instruction, but we don't emit those if unreachable=true */
9288 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9289 bool linear
= ctx
->cf_info
.has_branch
;
9290 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9291 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9292 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9293 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9294 /* the last operand should be the one that needs to be removed */
9295 instr
->operands
.pop_back();
9296 } else if (!is_phi(instr
)) {
9302 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9303 * and the previous one shouldn't both happen at once because a break in the
9304 * merge block would get CSE'd */
9305 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9306 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9307 Operand vals
[num_vals
];
9308 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9309 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9310 if (ctx
->cf_info
.has_branch
)
9311 instr
->operands
.pop_back();
9313 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9314 } else if (!is_phi(instr
)) {
9320 ctx
->cf_info
.has_branch
= false;
9322 // TODO: if the loop has not a single exit, we must add one °°
9323 /* emit loop successor block */
9324 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9325 append_logical_start(ctx
->block
);
9328 // TODO: check if it is beneficial to not branch on continues
9329 /* trim linear phis in loop header */
9330 for (auto&& instr
: loop_entry
->instructions
) {
9331 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9332 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9333 new_phi
->definitions
[0] = instr
->definitions
[0];
9334 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9335 new_phi
->operands
[i
] = instr
->operands
[i
];
9336 /* check that the remaining operands are all the same */
9337 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9338 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9339 instr
.swap(new_phi
);
9340 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9349 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9353 append_logical_end(ctx
->block
);
9354 ctx
->block
->kind
|= block_kind_branch
;
9356 /* branch to linear then block */
9357 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9358 aco_ptr
<Pseudo_branch_instruction
> branch
;
9359 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9360 branch
->operands
[0] = Operand(cond
);
9361 ctx
->block
->instructions
.push_back(std::move(branch
));
9363 ic
->BB_if_idx
= ctx
->block
->index
;
9364 ic
->BB_invert
= Block();
9365 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9366 /* Invert blocks are intentionally not marked as top level because they
9367 * are not part of the logical cfg. */
9368 ic
->BB_invert
.kind
|= block_kind_invert
;
9369 ic
->BB_endif
= Block();
9370 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9371 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9373 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9374 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9375 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9376 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9377 ctx
->cf_info
.parent_if
.is_divergent
= true;
9379 /* divergent branches use cbranch_execz */
9380 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9381 ctx
->cf_info
.exec_potentially_empty_break
= false;
9382 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9384 /** emit logical then block */
9385 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9386 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9387 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9388 ctx
->block
= BB_then_logical
;
9389 append_logical_start(BB_then_logical
);
9392 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9394 Block
*BB_then_logical
= ctx
->block
;
9395 append_logical_end(BB_then_logical
);
9396 /* branch from logical then block to invert block */
9397 aco_ptr
<Pseudo_branch_instruction
> branch
;
9398 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9399 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9400 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9401 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9402 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9403 BB_then_logical
->kind
|= block_kind_uniform
;
9404 assert(!ctx
->cf_info
.has_branch
);
9405 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9406 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9408 /** emit linear then block */
9409 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9410 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9411 BB_then_linear
->kind
|= block_kind_uniform
;
9412 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9413 /* branch from linear then block to invert block */
9414 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9415 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9416 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9418 /** emit invert merge block */
9419 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9420 ic
->invert_idx
= ctx
->block
->index
;
9422 /* branch to linear else block (skip else) */
9423 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9424 branch
->operands
[0] = Operand(ic
->cond
);
9425 ctx
->block
->instructions
.push_back(std::move(branch
));
9427 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9428 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9429 ic
->exec_potentially_empty_break_depth_old
=
9430 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9431 /* divergent branches use cbranch_execz */
9432 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9433 ctx
->cf_info
.exec_potentially_empty_break
= false;
9434 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9436 /** emit logical else block */
9437 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9438 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9439 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9440 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9441 ctx
->block
= BB_else_logical
;
9442 append_logical_start(BB_else_logical
);
9445 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9447 Block
*BB_else_logical
= ctx
->block
;
9448 append_logical_end(BB_else_logical
);
9450 /* branch from logical else block to endif block */
9451 aco_ptr
<Pseudo_branch_instruction
> branch
;
9452 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9453 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9454 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9455 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9456 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9457 BB_else_logical
->kind
|= block_kind_uniform
;
9459 assert(!ctx
->cf_info
.has_branch
);
9460 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9463 /** emit linear else block */
9464 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9465 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9466 BB_else_linear
->kind
|= block_kind_uniform
;
9467 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9469 /* branch from linear else block to endif block */
9470 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9471 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9472 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9475 /** emit endif merge block */
9476 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9477 append_logical_start(ctx
->block
);
9480 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9481 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9482 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9483 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9484 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9485 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9486 !ctx
->cf_info
.parent_if
.is_divergent
) {
9487 ctx
->cf_info
.exec_potentially_empty_break
= false;
9488 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9490 /* uniform control flow never has an empty exec-mask */
9491 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9492 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9493 ctx
->cf_info
.exec_potentially_empty_break
= false;
9494 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9498 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9500 assert(cond
.regClass() == s1
);
9502 append_logical_end(ctx
->block
);
9503 ctx
->block
->kind
|= block_kind_uniform
;
9505 aco_ptr
<Pseudo_branch_instruction
> branch
;
9506 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9507 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9508 branch
->operands
[0] = Operand(cond
);
9509 branch
->operands
[0].setFixed(scc
);
9510 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9512 ic
->BB_if_idx
= ctx
->block
->index
;
9513 ic
->BB_endif
= Block();
9514 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9515 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9517 ctx
->cf_info
.has_branch
= false;
9518 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9520 /** emit then block */
9521 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9522 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9523 add_edge(ic
->BB_if_idx
, BB_then
);
9524 append_logical_start(BB_then
);
9525 ctx
->block
= BB_then
;
9528 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9530 Block
*BB_then
= ctx
->block
;
9532 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9533 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9535 if (!ic
->uniform_has_then_branch
) {
9536 append_logical_end(BB_then
);
9537 /* branch from then block to endif block */
9538 aco_ptr
<Pseudo_branch_instruction
> branch
;
9539 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9540 BB_then
->instructions
.emplace_back(std::move(branch
));
9541 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9542 if (!ic
->then_branch_divergent
)
9543 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9544 BB_then
->kind
|= block_kind_uniform
;
9547 ctx
->cf_info
.has_branch
= false;
9548 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9550 /** emit else block */
9551 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9552 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9553 add_edge(ic
->BB_if_idx
, BB_else
);
9554 append_logical_start(BB_else
);
9555 ctx
->block
= BB_else
;
9558 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9560 Block
*BB_else
= ctx
->block
;
9562 if (!ctx
->cf_info
.has_branch
) {
9563 append_logical_end(BB_else
);
9564 /* branch from then block to endif block */
9565 aco_ptr
<Pseudo_branch_instruction
> branch
;
9566 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9567 BB_else
->instructions
.emplace_back(std::move(branch
));
9568 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9569 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9570 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9571 BB_else
->kind
|= block_kind_uniform
;
9574 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9575 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9577 /** emit endif merge block */
9578 if (!ctx
->cf_info
.has_branch
) {
9579 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9580 append_logical_start(ctx
->block
);
9584 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9586 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9587 Builder
bld(ctx
->program
, ctx
->block
);
9588 aco_ptr
<Pseudo_branch_instruction
> branch
;
9591 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9593 * Uniform conditionals are represented in the following way*) :
9595 * The linear and logical CFG:
9598 * BB_THEN (logical) BB_ELSE (logical)
9602 * *) Exceptions may be due to break and continue statements within loops
9603 * If a break/continue happens within uniform control flow, it branches
9604 * to the loop exit/entry block. Otherwise, it branches to the next
9608 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9609 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9610 cond
= bool_to_scalar_condition(ctx
, cond
);
9612 begin_uniform_if_then(ctx
, &ic
, cond
);
9613 visit_cf_list(ctx
, &if_stmt
->then_list
);
9615 begin_uniform_if_else(ctx
, &ic
);
9616 visit_cf_list(ctx
, &if_stmt
->else_list
);
9618 end_uniform_if(ctx
, &ic
);
9619 } else { /* non-uniform condition */
9621 * To maintain a logical and linear CFG without critical edges,
9622 * non-uniform conditionals are represented in the following way*) :
9627 * BB_THEN (logical) BB_THEN (linear)
9629 * BB_INVERT (linear)
9631 * BB_ELSE (logical) BB_ELSE (linear)
9638 * BB_THEN (logical) BB_ELSE (logical)
9642 * *) Exceptions may be due to break and continue statements within loops
9645 begin_divergent_if_then(ctx
, &ic
, cond
);
9646 visit_cf_list(ctx
, &if_stmt
->then_list
);
9648 begin_divergent_if_else(ctx
, &ic
);
9649 visit_cf_list(ctx
, &if_stmt
->else_list
);
9651 end_divergent_if(ctx
, &ic
);
9654 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9657 static bool visit_cf_list(isel_context
*ctx
,
9658 struct exec_list
*list
)
9660 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9661 switch (node
->type
) {
9662 case nir_cf_node_block
:
9663 visit_block(ctx
, nir_cf_node_as_block(node
));
9665 case nir_cf_node_if
:
9666 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9669 case nir_cf_node_loop
:
9670 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9673 unreachable("unimplemented cf list type");
9679 static void create_null_export(isel_context
*ctx
)
9681 /* Some shader stages always need to have exports.
9682 * So when there is none, we need to add a null export.
9685 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9686 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9687 Builder
bld(ctx
->program
, ctx
->block
);
9688 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9689 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9692 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9694 assert(ctx
->stage
== vertex_vs
||
9695 ctx
->stage
== tess_eval_vs
||
9696 ctx
->stage
== gs_copy_vs
||
9697 ctx
->stage
== ngg_vertex_gs
||
9698 ctx
->stage
== ngg_tess_eval_gs
);
9700 int offset
= (ctx
->stage
& sw_tes
)
9701 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9702 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9703 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9704 if (!is_pos
&& !mask
)
9706 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9708 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9709 exp
->enabled_mask
= mask
;
9710 for (unsigned i
= 0; i
< 4; ++i
) {
9711 if (mask
& (1 << i
))
9712 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9714 exp
->operands
[i
] = Operand(v1
);
9716 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9717 * Setting valid_mask=1 prevents it and has no other effect.
9719 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9721 exp
->compressed
= false;
9723 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9725 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9726 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9731 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9733 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9734 exp
->enabled_mask
= 0;
9735 for (unsigned i
= 0; i
< 4; ++i
)
9736 exp
->operands
[i
] = Operand(v1
);
9737 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9738 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9739 exp
->enabled_mask
|= 0x1;
9741 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9742 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9743 exp
->enabled_mask
|= 0x4;
9745 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9746 if (ctx
->options
->chip_class
< GFX9
) {
9747 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9748 exp
->enabled_mask
|= 0x8;
9750 Builder
bld(ctx
->program
, ctx
->block
);
9752 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9753 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9754 if (exp
->operands
[2].isTemp())
9755 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9757 exp
->operands
[2] = Operand(out
);
9758 exp
->enabled_mask
|= 0x4;
9761 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9763 exp
->compressed
= false;
9764 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9765 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9768 static void create_export_phis(isel_context
*ctx
)
9770 /* Used when exports are needed, but the output temps are defined in a preceding block.
9771 * This function will set up phis in order to access the outputs in the next block.
9774 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9775 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9776 ctx
->block
->instructions
.pop_back();
9778 Builder
bld(ctx
->program
, ctx
->block
);
9780 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9781 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9782 for (unsigned i
= 0; i
< 4; ++i
) {
9783 if (!(mask
& (1 << i
)))
9786 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9787 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9788 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9792 bld
.insert(std::move(logical_start
));
9795 static void create_vs_exports(isel_context
*ctx
)
9797 assert(ctx
->stage
== vertex_vs
||
9798 ctx
->stage
== tess_eval_vs
||
9799 ctx
->stage
== gs_copy_vs
||
9800 ctx
->stage
== ngg_vertex_gs
||
9801 ctx
->stage
== ngg_tess_eval_gs
);
9803 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9804 ? &ctx
->program
->info
->tes
.outinfo
9805 : &ctx
->program
->info
->vs
.outinfo
;
9807 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9808 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9809 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9812 if (ctx
->options
->key
.has_multiview_view_index
) {
9813 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9814 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9817 /* the order these position exports are created is important */
9819 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9820 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9821 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9822 exported_pos
= true;
9824 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9825 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9826 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9827 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9829 if (ctx
->export_clip_dists
) {
9830 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9831 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9832 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9833 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9836 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9837 if (i
< VARYING_SLOT_VAR0
&&
9838 i
!= VARYING_SLOT_LAYER
&&
9839 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9840 i
!= VARYING_SLOT_VIEWPORT
)
9843 export_vs_varying(ctx
, i
, false, NULL
);
9847 create_null_export(ctx
);
9850 static bool export_fs_mrt_z(isel_context
*ctx
)
9852 Builder
bld(ctx
->program
, ctx
->block
);
9853 unsigned enabled_channels
= 0;
9857 for (unsigned i
= 0; i
< 4; ++i
) {
9858 values
[i
] = Operand(v1
);
9861 /* Both stencil and sample mask only need 16-bits. */
9862 if (!ctx
->program
->info
->ps
.writes_z
&&
9863 (ctx
->program
->info
->ps
.writes_stencil
||
9864 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9865 compr
= true; /* COMPR flag */
9867 if (ctx
->program
->info
->ps
.writes_stencil
) {
9868 /* Stencil should be in X[23:16]. */
9869 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9870 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9871 enabled_channels
|= 0x3;
9874 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9875 /* SampleMask should be in Y[15:0]. */
9876 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9877 enabled_channels
|= 0xc;
9880 if (ctx
->program
->info
->ps
.writes_z
) {
9881 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9882 enabled_channels
|= 0x1;
9885 if (ctx
->program
->info
->ps
.writes_stencil
) {
9886 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9887 enabled_channels
|= 0x2;
9890 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9891 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9892 enabled_channels
|= 0x4;
9896 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9897 * writemask component.
9899 if (ctx
->options
->chip_class
== GFX6
&&
9900 ctx
->options
->family
!= CHIP_OLAND
&&
9901 ctx
->options
->family
!= CHIP_HAINAN
) {
9902 enabled_channels
|= 0x1;
9905 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9906 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9911 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9913 Builder
bld(ctx
->program
, ctx
->block
);
9914 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9917 for (unsigned i
= 0; i
< 4; ++i
) {
9918 if (write_mask
& (1 << i
)) {
9919 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9921 values
[i
] = Operand(v1
);
9925 unsigned target
, col_format
;
9926 unsigned enabled_channels
= 0;
9927 aco_opcode compr_op
= (aco_opcode
)0;
9929 slot
-= FRAG_RESULT_DATA0
;
9930 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9931 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9933 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9934 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9935 bool is_16bit
= values
[0].regClass() == v2b
;
9939 case V_028714_SPI_SHADER_ZERO
:
9940 enabled_channels
= 0; /* writemask */
9941 target
= V_008DFC_SQ_EXP_NULL
;
9944 case V_028714_SPI_SHADER_32_R
:
9945 enabled_channels
= 1;
9948 case V_028714_SPI_SHADER_32_GR
:
9949 enabled_channels
= 0x3;
9952 case V_028714_SPI_SHADER_32_AR
:
9953 if (ctx
->options
->chip_class
>= GFX10
) {
9954 /* Special case: on GFX10, the outputs are different for 32_AR */
9955 enabled_channels
= 0x3;
9956 values
[1] = values
[3];
9957 values
[3] = Operand(v1
);
9959 enabled_channels
= 0x9;
9963 case V_028714_SPI_SHADER_FP16_ABGR
:
9964 enabled_channels
= 0x5;
9965 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9967 if (ctx
->options
->chip_class
>= GFX9
) {
9968 /* Pack the FP16 values together instead of converting them to
9969 * FP32 and back to FP16.
9970 * TODO: use p_create_vector and let the compiler optimizes.
9972 compr_op
= aco_opcode::v_pack_b32_f16
;
9974 for (unsigned i
= 0; i
< 4; i
++) {
9975 if ((write_mask
>> i
) & 1)
9976 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9982 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9983 enabled_channels
= 0x5;
9984 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9985 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9987 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9991 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9992 enabled_channels
= 0x5;
9993 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9994 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
9996 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10000 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10001 enabled_channels
= 0x5;
10002 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10003 if (is_int8
|| is_int10
) {
10005 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10006 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10008 for (unsigned i
= 0; i
< 4; i
++) {
10009 if ((write_mask
>> i
) & 1) {
10010 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10011 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10015 } else if (is_16bit
) {
10016 for (unsigned i
= 0; i
< 4; i
++) {
10017 if ((write_mask
>> i
) & 1) {
10018 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10019 values
[i
] = Operand(tmp
);
10026 case V_028714_SPI_SHADER_SINT16_ABGR
:
10027 enabled_channels
= 0x5;
10028 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10029 if (is_int8
|| is_int10
) {
10031 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10032 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10033 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10034 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10036 for (unsigned i
= 0; i
< 4; i
++) {
10037 if ((write_mask
>> i
) & 1) {
10038 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10039 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10041 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10042 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10046 } else if (is_16bit
) {
10047 for (unsigned i
= 0; i
< 4; i
++) {
10048 if ((write_mask
>> i
) & 1) {
10049 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10050 values
[i
] = Operand(tmp
);
10056 case V_028714_SPI_SHADER_32_ABGR
:
10057 enabled_channels
= 0xF;
10064 if (target
== V_008DFC_SQ_EXP_NULL
)
10067 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10068 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10070 (col_format
== V_028714_SPI_SHADER_32_R
||
10071 col_format
== V_028714_SPI_SHADER_32_GR
||
10072 col_format
== V_028714_SPI_SHADER_32_AR
||
10073 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10074 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10075 for (int i
= 0; i
< 4; i
++) {
10076 if (!(write_mask
& (1 << i
)))
10079 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10080 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10081 bld
.copy(bld
.def(v1
), Operand(3u)));
10082 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10083 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10087 if ((bool) compr_op
) {
10088 for (int i
= 0; i
< 2; i
++) {
10089 /* check if at least one of the values to be compressed is enabled */
10090 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10092 enabled_channels
|= enabled
<< (i
*2);
10093 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10094 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10095 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10097 values
[i
] = Operand(v1
);
10100 values
[2] = Operand(v1
);
10101 values
[3] = Operand(v1
);
10103 for (int i
= 0; i
< 4; i
++)
10104 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10107 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10108 enabled_channels
, target
, (bool) compr_op
);
10112 static void create_fs_exports(isel_context
*ctx
)
10114 bool exported
= false;
10116 /* Export depth, stencil and sample mask. */
10117 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10118 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10119 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10120 exported
|= export_fs_mrt_z(ctx
);
10122 /* Export all color render targets. */
10123 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10124 if (ctx
->outputs
.mask
[i
])
10125 exported
|= export_fs_mrt_color(ctx
, i
);
10128 create_null_export(ctx
);
10131 static void create_workgroup_barrier(Builder
& bld
)
10133 bld
.barrier(aco_opcode::p_barrier
,
10134 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10138 static void write_tcs_tess_factors(isel_context
*ctx
)
10140 unsigned outer_comps
;
10141 unsigned inner_comps
;
10143 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10160 Builder
bld(ctx
->program
, ctx
->block
);
10162 create_workgroup_barrier(bld
);
10164 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10165 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10167 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10168 if_context ic_invocation_id_is_zero
;
10169 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10170 bld
.reset(ctx
->block
);
10172 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10174 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10175 unsigned stride
= inner_comps
+ outer_comps
;
10176 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10180 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10182 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10184 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10185 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10186 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10188 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10189 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10191 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10192 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10193 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10194 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10197 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10198 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10199 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10200 unsigned tf_const_offset
= 0;
10202 if (ctx
->program
->chip_class
<= GFX8
) {
10203 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10204 if_context ic_rel_patch_id_is_zero
;
10205 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10206 bld
.reset(ctx
->block
);
10208 /* Store the dynamic HS control word. */
10209 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10210 bld
.mubuf(aco_opcode::buffer_store_dword
,
10211 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10212 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10213 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10214 tf_const_offset
+= 4;
10216 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10217 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10218 bld
.reset(ctx
->block
);
10221 assert(stride
== 2 || stride
== 4 || stride
== 6);
10222 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10223 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10225 /* Store to offchip for TES to read - only if TES reads them */
10226 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10227 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10228 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10230 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10231 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10233 if (likely(inner_comps
)) {
10234 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10235 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10239 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10240 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10243 static void emit_stream_output(isel_context
*ctx
,
10244 Temp
const *so_buffers
,
10245 Temp
const *so_write_offset
,
10246 const struct radv_stream_output
*output
)
10248 unsigned num_comps
= util_bitcount(output
->component_mask
);
10249 unsigned writemask
= (1 << num_comps
) - 1;
10250 unsigned loc
= output
->location
;
10251 unsigned buf
= output
->buffer
;
10253 assert(num_comps
&& num_comps
<= 4);
10254 if (!num_comps
|| num_comps
> 4)
10257 unsigned start
= ffs(output
->component_mask
) - 1;
10260 bool all_undef
= true;
10261 assert(ctx
->stage
& hw_vs
);
10262 for (unsigned i
= 0; i
< num_comps
; i
++) {
10263 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10264 all_undef
= all_undef
&& !out
[i
].id();
10269 while (writemask
) {
10271 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10272 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10273 /* GFX6 doesn't support storing vec3, split it. */
10274 writemask
|= 1u << (start
+ 2);
10278 unsigned offset
= output
->offset
+ start
* 4;
10280 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10281 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10282 for (int i
= 0; i
< count
; ++i
)
10283 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10284 vec
->definitions
[0] = Definition(write_data
);
10285 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10290 opcode
= aco_opcode::buffer_store_dword
;
10293 opcode
= aco_opcode::buffer_store_dwordx2
;
10296 opcode
= aco_opcode::buffer_store_dwordx3
;
10299 opcode
= aco_opcode::buffer_store_dwordx4
;
10302 unreachable("Unsupported dword count.");
10305 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10306 store
->operands
[0] = Operand(so_buffers
[buf
]);
10307 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10308 store
->operands
[2] = Operand((uint32_t) 0);
10309 store
->operands
[3] = Operand(write_data
);
10310 if (offset
> 4095) {
10311 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10312 Builder
bld(ctx
->program
, ctx
->block
);
10313 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10315 store
->offset
= offset
;
10317 store
->offen
= true;
10319 store
->dlc
= false;
10321 ctx
->block
->instructions
.emplace_back(std::move(store
));
10325 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10327 Builder
bld(ctx
->program
, ctx
->block
);
10329 Temp so_buffers
[4];
10330 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10331 for (unsigned i
= 0; i
< 4; i
++) {
10332 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10336 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10337 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10340 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10341 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10343 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10345 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10348 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10350 bld
.reset(ctx
->block
);
10352 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10354 Temp so_write_offset
[4];
10356 for (unsigned i
= 0; i
< 4; i
++) {
10357 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10362 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10363 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10364 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10365 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10367 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10369 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10370 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10371 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10372 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10376 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10377 struct radv_stream_output
*output
=
10378 &ctx
->program
->info
->so
.outputs
[i
];
10379 if (stream
!= output
->stream
)
10382 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10385 begin_divergent_if_else(ctx
, &ic
);
10386 end_divergent_if(ctx
, &ic
);
10389 } /* end namespace */
10391 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10393 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10394 Builder
bld(ctx
->program
, ctx
->block
);
10395 constexpr unsigned hs_idx
= 1u;
10396 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10397 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10398 Operand((8u << 16) | (hs_idx
* 8u)));
10399 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10401 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10403 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10404 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10405 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10406 ls_has_nonzero_hs_threads
);
10407 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10408 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10409 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10410 ls_has_nonzero_hs_threads
);
10411 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10412 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10413 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10414 ls_has_nonzero_hs_threads
);
10416 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10417 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10418 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10421 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10423 /* Split all arguments except for the first (ring_offsets) and the last
10424 * (exec) so that the dead channels don't stay live throughout the program.
10426 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10427 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10428 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10429 startpgm
->definitions
[i
].regClass().size());
10434 void handle_bc_optimize(isel_context
*ctx
)
10436 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10437 Builder
bld(ctx
->program
, ctx
->block
);
10438 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10439 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10440 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10441 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10442 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10443 if (uses_center
&& uses_centroid
) {
10444 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10445 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10447 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10449 for (unsigned i
= 0; i
< 2; i
++) {
10450 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10451 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10452 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10453 persp_centroid
, persp_center
, sel
);
10455 ctx
->persp_centroid
= bld
.tmp(v2
);
10456 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10457 Operand(new_coord
[0]), Operand(new_coord
[1]));
10458 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10461 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10463 for (unsigned i
= 0; i
< 2; i
++) {
10464 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10465 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10466 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10467 linear_centroid
, linear_center
, sel
);
10469 ctx
->linear_centroid
= bld
.tmp(v2
);
10470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10471 Operand(new_coord
[0]), Operand(new_coord
[1]));
10472 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10477 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10479 Program
*program
= ctx
->program
;
10481 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10483 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10484 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10485 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10486 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10487 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10489 program
->next_fp_mode
.must_flush_denorms32
=
10490 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10491 program
->next_fp_mode
.must_flush_denorms16_64
=
10492 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10493 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10495 program
->next_fp_mode
.care_about_round32
=
10496 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10498 program
->next_fp_mode
.care_about_round16_64
=
10499 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10500 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10502 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10503 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10504 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10505 program
->next_fp_mode
.denorm16_64
= 0;
10507 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10509 /* preserving fp32 denorms is expensive, so only do it if asked */
10510 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10511 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10513 program
->next_fp_mode
.denorm32
= 0;
10515 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10516 program
->next_fp_mode
.round32
= fp_round_tz
;
10518 program
->next_fp_mode
.round32
= fp_round_ne
;
10520 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10521 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10523 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10525 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10528 void cleanup_cfg(Program
*program
)
10530 /* create linear_succs/logical_succs */
10531 for (Block
& BB
: program
->blocks
) {
10532 for (unsigned idx
: BB
.linear_preds
)
10533 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10534 for (unsigned idx
: BB
.logical_preds
)
10535 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10539 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10541 Builder
bld(ctx
->program
, ctx
->block
);
10543 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10544 Temp count
= i
== 0
10545 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10546 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10547 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10549 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10552 if (ctx
->program
->wave_size
== 64) {
10553 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10554 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10555 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10557 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10558 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10564 bool ngg_early_prim_export(isel_context
*ctx
)
10566 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10570 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10572 Builder
bld(ctx
->program
, ctx
->block
);
10574 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10575 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10577 /* Get the id of the current wave within the threadgroup (workgroup) */
10578 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10579 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10581 /* Execute the following code only on the first wave (wave id 0),
10582 * use the SCC def to tell if the wave id is zero or not.
10584 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10586 begin_uniform_if_then(ctx
, &ic
, cond
);
10587 begin_uniform_if_else(ctx
, &ic
);
10588 bld
.reset(ctx
->block
);
10590 /* Number of vertices output by VS/TES */
10591 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10592 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10593 /* Number of primitives output by VS/TES */
10594 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10595 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10597 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10598 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10599 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10601 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10602 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10604 end_uniform_if(ctx
, &ic
);
10606 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10607 bld
.reset(ctx
->block
);
10608 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10611 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10613 Builder
bld(ctx
->program
, ctx
->block
);
10615 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10616 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10619 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10622 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10623 assert(vtxindex
[i
].id());
10626 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10630 /* The initial edge flag is always false in tess eval shaders. */
10631 if (ctx
->stage
== ngg_vertex_gs
) {
10632 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10633 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10637 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10642 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10644 Builder
bld(ctx
->program
, ctx
->block
);
10645 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10647 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10648 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10649 false /* compressed */, true/* done */, false /* valid mask */);
10652 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10654 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10655 * These must always come before VS exports.
10657 * It is recommended to do these as early as possible. They can be at the beginning when
10658 * there is no SW GS and the shader doesn't write edge flags.
10662 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10663 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10665 Builder
bld(ctx
->program
, ctx
->block
);
10666 constexpr unsigned max_vertices_per_primitive
= 3;
10667 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10669 if (ctx
->stage
== ngg_vertex_gs
) {
10670 /* TODO: optimize for points & lines */
10671 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10672 if (ctx
->shader
->info
.tess
.point_mode
)
10673 num_vertices_per_primitive
= 1;
10674 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10675 num_vertices_per_primitive
= 2;
10677 unreachable("Unsupported NGG shader stage");
10680 Temp vtxindex
[max_vertices_per_primitive
];
10681 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10682 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10683 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10684 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10685 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10686 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10687 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10688 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10690 /* Export primitive data to the index buffer. */
10691 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10693 /* Export primitive ID. */
10694 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10695 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10696 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10697 Temp provoking_vtx_index
= vtxindex
[0];
10698 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10700 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10703 begin_divergent_if_else(ctx
, &ic
);
10704 end_divergent_if(ctx
, &ic
);
10707 void ngg_emit_nogs_output(isel_context
*ctx
)
10709 /* Emits NGG GS output, for stages that don't have SW GS. */
10712 Builder
bld(ctx
->program
, ctx
->block
);
10713 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10715 /* NGG streamout is currently disabled by default. */
10716 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10718 if (late_prim_export
) {
10719 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10720 create_export_phis(ctx
);
10721 /* Do what we need to do in the GS threads. */
10722 ngg_emit_nogs_gsthreads(ctx
);
10724 /* What comes next should be executed on ES threads. */
10725 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10726 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10727 bld
.reset(ctx
->block
);
10730 /* Export VS outputs */
10731 ctx
->block
->kind
|= block_kind_export_end
;
10732 create_vs_exports(ctx
);
10734 /* Export primitive ID */
10735 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10738 if (ctx
->stage
== ngg_vertex_gs
) {
10739 /* Wait for GS threads to store primitive ID in LDS. */
10740 create_workgroup_barrier(bld
);
10742 /* Calculate LDS address where the GS threads stored the primitive ID. */
10743 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10744 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10745 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10746 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10747 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10748 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10750 /* Load primitive ID from LDS. */
10751 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10752 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10753 /* TES: Just use the patch ID as the primitive ID. */
10754 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10756 unreachable("unsupported NGG shader stage.");
10759 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10760 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10762 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10765 if (late_prim_export
) {
10766 begin_divergent_if_else(ctx
, &ic
);
10767 end_divergent_if(ctx
, &ic
);
10768 bld
.reset(ctx
->block
);
10772 void select_program(Program
*program
,
10773 unsigned shader_count
,
10774 struct nir_shader
*const *shaders
,
10775 ac_shader_config
* config
,
10776 struct radv_shader_args
*args
)
10778 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10779 if_context ic_merged_wave_info
;
10780 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10782 for (unsigned i
= 0; i
< shader_count
; i
++) {
10783 nir_shader
*nir
= shaders
[i
];
10784 init_context(&ctx
, nir
);
10786 setup_fp_mode(&ctx
, nir
);
10789 /* needs to be after init_context() for FS */
10790 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10791 append_logical_start(ctx
.block
);
10793 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10794 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10796 split_arguments(&ctx
, startpgm
);
10800 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10802 if (ngg_early_prim_export(&ctx
))
10803 ngg_emit_nogs_gsthreads(&ctx
);
10806 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10807 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10808 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10809 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10810 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10811 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10812 ctx
.stage
== tess_eval_geometry_gs
));
10814 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10815 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10816 if (check_merged_wave_info
) {
10817 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10818 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10822 Builder
bld(ctx
.program
, ctx
.block
);
10824 create_workgroup_barrier(bld
);
10826 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10827 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10829 } else if (ctx
.stage
== geometry_gs
)
10830 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10832 if (ctx
.stage
== fragment_fs
)
10833 handle_bc_optimize(&ctx
);
10835 visit_cf_list(&ctx
, &func
->body
);
10837 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10838 emit_streamout(&ctx
, 0);
10840 if (ctx
.stage
& hw_vs
) {
10841 create_vs_exports(&ctx
);
10842 ctx
.block
->kind
|= block_kind_export_end
;
10843 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10844 ngg_emit_nogs_output(&ctx
);
10845 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10846 Builder
bld(ctx
.program
, ctx
.block
);
10847 bld
.barrier(aco_opcode::p_barrier
,
10848 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10849 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10850 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10851 write_tcs_tess_factors(&ctx
);
10854 if (ctx
.stage
== fragment_fs
) {
10855 create_fs_exports(&ctx
);
10856 ctx
.block
->kind
|= block_kind_export_end
;
10859 if (endif_merged_wave_info
) {
10860 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10861 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10864 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10865 ngg_emit_nogs_output(&ctx
);
10867 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10868 /* Outputs of the previous stage are inputs to the next stage */
10869 ctx
.inputs
= ctx
.outputs
;
10870 ctx
.outputs
= shader_io_state();
10874 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10876 append_logical_end(ctx
.block
);
10877 ctx
.block
->kind
|= block_kind_uniform
;
10878 Builder
bld(ctx
.program
, ctx
.block
);
10879 if (ctx
.program
->wb_smem_l1_on_end
)
10880 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10881 bld
.sopp(aco_opcode::s_endpgm
);
10883 cleanup_cfg(program
);
10886 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10887 ac_shader_config
* config
,
10888 struct radv_shader_args
*args
)
10890 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10892 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10894 add_startpgm(&ctx
);
10895 append_logical_start(ctx
.block
);
10897 Builder
bld(ctx
.program
, ctx
.block
);
10899 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10901 Operand
stream_id(0u);
10902 if (args
->shader_info
->so
.num_outputs
)
10903 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10904 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10906 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10908 std::stack
<Block
> endif_blocks
;
10910 for (unsigned stream
= 0; stream
< 4; stream
++) {
10911 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10914 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10915 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10918 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10920 unsigned BB_if_idx
= ctx
.block
->index
;
10921 Block BB_endif
= Block();
10922 if (!stream_id
.isConstant()) {
10924 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10925 append_logical_end(ctx
.block
);
10926 ctx
.block
->kind
|= block_kind_uniform
;
10927 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10929 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10931 ctx
.block
= ctx
.program
->create_and_insert_block();
10932 add_edge(BB_if_idx
, ctx
.block
);
10933 bld
.reset(ctx
.block
);
10934 append_logical_start(ctx
.block
);
10937 unsigned offset
= 0;
10938 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10939 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10942 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10943 unsigned length
= util_last_bit(output_usage_mask
);
10944 for (unsigned j
= 0; j
< length
; ++j
) {
10945 if (!(output_usage_mask
& (1 << j
)))
10948 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10949 Temp voffset
= vtx_offset
;
10950 if (const_offset
>= 4096u) {
10951 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10952 const_offset
%= 4096u;
10955 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10956 mubuf
->definitions
[0] = bld
.def(v1
);
10957 mubuf
->operands
[0] = Operand(gsvs_ring
);
10958 mubuf
->operands
[1] = Operand(voffset
);
10959 mubuf
->operands
[2] = Operand(0u);
10960 mubuf
->offen
= true;
10961 mubuf
->offset
= const_offset
;
10964 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10966 ctx
.outputs
.mask
[i
] |= 1 << j
;
10967 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10969 bld
.insert(std::move(mubuf
));
10975 if (args
->shader_info
->so
.num_outputs
) {
10976 emit_streamout(&ctx
, stream
);
10977 bld
.reset(ctx
.block
);
10981 create_vs_exports(&ctx
);
10982 ctx
.block
->kind
|= block_kind_export_end
;
10985 if (!stream_id
.isConstant()) {
10986 append_logical_end(ctx
.block
);
10988 /* branch from then block to endif block */
10989 bld
.branch(aco_opcode::p_branch
);
10990 add_edge(ctx
.block
->index
, &BB_endif
);
10991 ctx
.block
->kind
|= block_kind_uniform
;
10993 /* emit else block */
10994 ctx
.block
= ctx
.program
->create_and_insert_block();
10995 add_edge(BB_if_idx
, ctx
.block
);
10996 bld
.reset(ctx
.block
);
10997 append_logical_start(ctx
.block
);
10999 endif_blocks
.push(std::move(BB_endif
));
11003 while (!endif_blocks
.empty()) {
11004 Block BB_endif
= std::move(endif_blocks
.top());
11005 endif_blocks
.pop();
11007 Block
*BB_else
= ctx
.block
;
11009 append_logical_end(BB_else
);
11010 /* branch from else block to endif block */
11011 bld
.branch(aco_opcode::p_branch
);
11012 add_edge(BB_else
->index
, &BB_endif
);
11013 BB_else
->kind
|= block_kind_uniform
;
11015 /** emit endif merge block */
11016 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11017 bld
.reset(ctx
.block
);
11018 append_logical_start(ctx
.block
);
11021 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11023 append_logical_end(ctx
.block
);
11024 ctx
.block
->kind
|= block_kind_uniform
;
11025 bld
.sopp(aco_opcode::s_endpgm
);
11027 cleanup_cfg(program
);
11030 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11031 ac_shader_config
* config
,
11032 struct radv_shader_args
*args
)
11034 assert(args
->options
->chip_class
== GFX8
);
11036 init_program(program
, compute_cs
, args
->shader_info
,
11037 args
->options
->chip_class
, args
->options
->family
, config
);
11039 isel_context ctx
= {};
11040 ctx
.program
= program
;
11042 ctx
.options
= args
->options
;
11043 ctx
.stage
= program
->stage
;
11045 ctx
.block
= ctx
.program
->create_and_insert_block();
11046 ctx
.block
->loop_nest_depth
= 0;
11047 ctx
.block
->kind
= block_kind_top_level
;
11049 program
->workgroup_size
= 1; /* XXX */
11051 add_startpgm(&ctx
);
11052 append_logical_start(ctx
.block
);
11054 Builder
bld(ctx
.program
, ctx
.block
);
11056 /* Load the buffer descriptor from TMA. */
11057 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11058 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11060 /* Store TTMP0-TTMP1. */
11061 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11062 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11064 uint32_t hw_regs_idx
[] = {
11065 2, /* HW_REG_STATUS */
11066 3, /* HW_REG_TRAP_STS */
11067 4, /* HW_REG_HW_ID */
11068 7, /* HW_REG_IB_STS */
11071 /* Store some hardware registers. */
11072 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11073 /* "((size - 1) << 11) | register" */
11074 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11075 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11077 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11078 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11081 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11083 append_logical_end(ctx
.block
);
11084 ctx
.block
->kind
|= block_kind_uniform
;
11085 bld
.sopp(aco_opcode::s_endpgm
);
11087 cleanup_cfg(program
);