src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <map>
  29
  30 #include "ac_shader_util.h"
  31 #include "aco_ir.h"
  32 #include "aco_builder.h"
  33 #include "aco_interface.h"
  34 #include "aco_instruction_selection_setup.cpp"
  35 #include "util/fast_idiv_by_const.h"
  36
  37 namespace aco {
  38 namespace {
  39
  40 class loop_info_RAII {
  41    isel_context* ctx;
  42    unsigned header_idx_old;
  43    Block* exit_old;
  44    bool divergent_cont_old;
  45    bool divergent_branch_old;
  46    bool divergent_if_old;
  47
  48 public:
  49    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  50       : ctx(ctx),
  51         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  52         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  53         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  54         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  55    {
  56       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  57       ctx->cf_info.parent_loop.exit = loop_exit;
  58       ctx->cf_info.parent_loop.has_divergent_continue = false;
  59       ctx->cf_info.parent_loop.has_divergent_branch = false;
  60       ctx->cf_info.parent_if.is_divergent = false;
  61       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  62    }
  63
  64    ~loop_info_RAII()
  65    {
  66       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  67       ctx->cf_info.parent_loop.exit = exit_old;
  68       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  69       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  70       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  71       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  72       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  73          ctx->cf_info.exec_potentially_empty = false;
  74    }
  75 };
  76
  77 struct if_context {
  78    Temp cond;
  79
  80    bool divergent_old;
  81    bool exec_potentially_empty_old;
  82
  83    unsigned BB_if_idx;
  84    unsigned invert_idx;
  85    bool then_branch_divergent;
  86    Block BB_invert;
  87    Block BB_endif;
  88 };
  89
  90 static void visit_cf_list(struct isel_context *ctx,
  91                           struct exec_list *list);
  92
  93 static void add_logical_edge(unsigned pred_idx, Block *succ)
  94 {
  95    succ->logical_preds.emplace_back(pred_idx);
  96 }
  97
  98
  99 static void add_linear_edge(unsigned pred_idx, Block *succ)
 100 {
 101    succ->linear_preds.emplace_back(pred_idx);
 102 }
 103
 104 static void add_edge(unsigned pred_idx, Block *succ)
 105 {
 106    add_logical_edge(pred_idx, succ);
 107    add_linear_edge(pred_idx, succ);
 108 }
 109
 110 static void append_logical_start(Block *b)
 111 {
 112    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 113 }
 114
 115 static void append_logical_end(Block *b)
 116 {
 117    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 118 }
 119
 120 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 121 {
 122    assert(ctx->allocated[def->index].id());
 123    return ctx->allocated[def->index];
 124 }
 125
 126 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 127 {
 128    Builder bld(ctx->program, ctx->block);
 129
 130    if (!dst.id())
 131       dst = bld.tmp(src.regClass());
 132
 133    if (ctx->stage != fragment_fs) {
 134       if (!dst.id())
 135          return src;
 136
 137       if (src.type() == RegType::vgpr || src.size() > 1)
 138          bld.copy(Definition(dst), src);
 139       else
 140          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 141       return dst;
 142    }
 143
 144    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 145    ctx->program->needs_wqm |= program_needs_wqm;
 146    return dst;
 147 }
 148
 149 Temp as_vgpr(isel_context *ctx, Temp val)
 150 {
 151    if (val.type() == RegType::sgpr) {
 152       Builder bld(ctx->program, ctx->block);
 153       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 154    }
 155    assert(val.type() == RegType::vgpr);
 156    return val;
 157 }
 158
 159 //assumes a != 0xffffffff
 160 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 161 {
 162    assert(b != 0);
 163    Builder bld(ctx->program, ctx->block);
 164
 165    if (util_is_power_of_two_or_zero(b)) {
 166       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 167       return;
 168    }
 169
 170    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 171
 172    assert(info.multiplier <= 0xffffffff);
 173
 174    bool pre_shift = info.pre_shift != 0;
 175    bool increment = info.increment != 0;
 176    bool multiply = true;
 177    bool post_shift = info.post_shift != 0;
 178
 179    if (!pre_shift && !increment && !multiply && !post_shift) {
 180       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 181       return;
 182    }
 183
 184    Temp pre_shift_dst = a;
 185    if (pre_shift) {
 186       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 187       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 188    }
 189
 190    Temp increment_dst = pre_shift_dst;
 191    if (increment) {
 192       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 193       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 194    }
 195
 196    Temp multiply_dst = increment_dst;
 197    if (multiply) {
 198       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 199       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 200                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 201    }
 202
 203    if (post_shift) {
 204       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 205    }
 206 }
 207
 208 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 209 {
 210    Builder bld(ctx->program, ctx->block);
 211    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 212 }
 213
 214
 215 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 216 {
 217    /* no need to extract the whole vector */
 218    if (src.regClass() == dst_rc) {
 219       assert(idx == 0);
 220       return src;
 221    }
 222    assert(src.size() > idx);
 223    Builder bld(ctx->program, ctx->block);
 224    auto it = ctx->allocated_vec.find(src.id());
 225    /* the size check needs to be early because elements other than 0 may be garbage */
 226    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 227       if (it->second[idx].regClass() == dst_rc) {
 228          return it->second[idx];
 229       } else {
 230          assert(dst_rc.size() == it->second[idx].regClass().size());
 231          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 232          return bld.copy(bld.def(dst_rc), it->second[idx]);
 233       }
 234    }
 235
 236    if (src.size() == dst_rc.size()) {
 237       assert(idx == 0);
 238       return bld.copy(bld.def(dst_rc), src);
 239    } else {
 240       Temp dst = bld.tmp(dst_rc);
 241       emit_extract_vector(ctx, src, idx, dst);
 242       return dst;
 243    }
 244 }
 245
 246 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 247 {
 248    if (num_components == 1)
 249       return;
 250    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 251       return;
 252    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 253    split->operands[0] = Operand(vec_src);
 254    std::array<Temp,4> elems;
 255    for (unsigned i = 0; i < num_components; i++) {
 256       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 257       split->definitions[i] = Definition(elems[i]);
 258    }
 259    ctx->block->instructions.emplace_back(std::move(split));
 260    ctx->allocated_vec.emplace(vec_src.id(), elems);
 261 }
 262
 263 /* This vector expansion uses a mask to determine which elements in the new vector
 264  * come from the original vector. The other elements are undefined. */
 265 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 266 {
 267    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 268
 269    if (vec_src == dst)
 270       return;
 271
 272    Builder bld(ctx->program, ctx->block);
 273    if (num_components == 1) {
 274       if (dst.type() == RegType::sgpr)
 275          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 276       else
 277          bld.copy(Definition(dst), vec_src);
 278       return;
 279    }
 280
 281    unsigned component_size = dst.size() / num_components;
 282    std::array<Temp,4> elems;
 283
 284    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 285    vec->definitions[0] = Definition(dst);
 286    unsigned k = 0;
 287    for (unsigned i = 0; i < num_components; i++) {
 288       if (mask & (1 << i)) {
 289          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 290          if (dst.type() == RegType::sgpr)
 291             src = bld.as_uniform(src);
 292          vec->operands[i] = Operand(src);
 293       } else {
 294          vec->operands[i] = Operand(0u);
 295       }
 296       elems[i] = vec->operands[i].getTemp();
 297    }
 298    ctx->block->instructions.emplace_back(std::move(vec));
 299    ctx->allocated_vec.emplace(dst.id(), elems);
 300 }
 301
 302 Temp as_divergent_bool(isel_context *ctx, Temp val, bool vcc_hint)
 303 {
 304    if (val.regClass() == s2) {
 305       return val;
 306    } else {
 307       assert(val.regClass() == s1);
 308       Builder bld(ctx->program, ctx->block);
 309       Definition& def = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2),
 310                                  Operand((uint32_t) -1), Operand(0u), bld.scc(val)).def(0);
 311       if (vcc_hint)
 312          def.setHint(vcc);
 313       return def.getTemp();
 314    }
 315 }
 316
 317 Temp as_uniform_bool(isel_context *ctx, Temp val)
 318 {
 319    if (val.regClass() == s1) {
 320       return val;
 321    } else {
 322       assert(val.regClass() == s2);
 323       Builder bld(ctx->program, ctx->block);
 324       return bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), Operand(0u), Operand(val));
 325    }
 326 }
 327
 328 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 329 {
 330    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 331       return get_ssa_temp(ctx, src.src.ssa);
 332
 333    if (src.src.ssa->num_components == size) {
 334       bool identity_swizzle = true;
 335       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 336          if (src.swizzle[i] != i)
 337             identity_swizzle = false;
 338       }
 339       if (identity_swizzle)
 340          return get_ssa_temp(ctx, src.src.ssa);
 341    }
 342
 343    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 344    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 345    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 346    assert(vec.size() % elem_size == 0);
 347
 348    RegClass elem_rc = RegClass(vec.type(), elem_size);
 349    if (size == 1) {
 350       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 351    } else {
 352       assert(size <= 4);
 353       std::array<Temp,4> elems;
 354       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 355       for (unsigned i = 0; i < size; ++i) {
 356          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 357          vec_instr->operands[i] = Operand{elems[i]};
 358       }
 359       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 360       vec_instr->definitions[0] = Definition(dst);
 361       ctx->block->instructions.emplace_back(std::move(vec_instr));
 362       ctx->allocated_vec.emplace(dst.id(), elems);
 363       return dst;
 364    }
 365 }
 366
 367 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 368 {
 369    if (ptr.size() == 2)
 370       return ptr;
 371    Builder bld(ctx->program, ctx->block);
 372    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 373                      ptr, Operand((unsigned)ctx->options->address32_hi));
 374 }
 375
 376 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 377 {
 378    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 379    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 380    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 381    sop2->definitions[0] = Definition(dst);
 382    if (writes_scc)
 383       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 384    ctx->block->instructions.emplace_back(std::move(sop2));
 385 }
 386
 387 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool commutative, bool swap_srcs=false)
 388 {
 389    Builder bld(ctx->program, ctx->block);
 390    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 391    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 392    if (src1.type() == RegType::sgpr) {
 393       if (commutative && src0.type() == RegType::vgpr) {
 394          Temp t = src0;
 395          src0 = src1;
 396          src1 = t;
 397       } else if (src0.type() == RegType::vgpr &&
 398                  op != aco_opcode::v_madmk_f32 &&
 399                  op != aco_opcode::v_madak_f32 &&
 400                  op != aco_opcode::v_madmk_f16 &&
 401                  op != aco_opcode::v_madak_f16) {
 402          /* If the instruction is not commutative, we emit a VOP3A instruction */
 403          bld.vop2_e64(op, Definition(dst), src0, src1);
 404          return;
 405       } else {
 406          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 407       }
 408    }
 409    bld.vop2(op, Definition(dst), src0, src1);
 410 }
 411
 412 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 413 {
 414    Temp src0 = get_alu_src(ctx, instr->src[0]);
 415    Temp src1 = get_alu_src(ctx, instr->src[1]);
 416    Temp src2 = get_alu_src(ctx, instr->src[2]);
 417
 418    /* ensure that the instruction has at most 1 sgpr operand
 419     * The optimizer will inline constants for us */
 420    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 421       src0 = as_vgpr(ctx, src0);
 422    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 423       src1 = as_vgpr(ctx, src1);
 424    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 425       src2 = as_vgpr(ctx, src2);
 426
 427    Builder bld(ctx->program, ctx->block);
 428    bld.vop3(op, Definition(dst), src0, src1, src2);
 429 }
 430
 431 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 432 {
 433    Builder bld(ctx->program, ctx->block);
 434    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 435 }
 436
 437 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 438 {
 439    Temp src0 = get_alu_src(ctx, instr->src[0]);
 440    Temp src1 = get_alu_src(ctx, instr->src[1]);
 441    aco_ptr<Instruction> vopc;
 442    if (src1.type() == RegType::sgpr) {
 443       if (src0.type() == RegType::vgpr) {
 444          /* to swap the operands, we might also have to change the opcode */
 445          switch (op) {
 446             case aco_opcode::v_cmp_lt_f32:
 447                op = aco_opcode::v_cmp_gt_f32;
 448                break;
 449             case aco_opcode::v_cmp_ge_f32:
 450                op = aco_opcode::v_cmp_le_f32;
 451                break;
 452             case aco_opcode::v_cmp_lt_i32:
 453                op = aco_opcode::v_cmp_gt_i32;
 454                break;
 455             case aco_opcode::v_cmp_ge_i32:
 456                op = aco_opcode::v_cmp_le_i32;
 457                break;
 458             case aco_opcode::v_cmp_lt_u32:
 459                op = aco_opcode::v_cmp_gt_u32;
 460                break;
 461             case aco_opcode::v_cmp_ge_u32:
 462                op = aco_opcode::v_cmp_le_u32;
 463                break;
 464             case aco_opcode::v_cmp_lt_f64:
 465                op = aco_opcode::v_cmp_gt_f64;
 466                break;
 467             case aco_opcode::v_cmp_ge_f64:
 468                op = aco_opcode::v_cmp_le_f64;
 469                break;
 470             case aco_opcode::v_cmp_lt_i64:
 471                op = aco_opcode::v_cmp_gt_i64;
 472                break;
 473             case aco_opcode::v_cmp_ge_i64:
 474                op = aco_opcode::v_cmp_le_i64;
 475                break;
 476             case aco_opcode::v_cmp_lt_u64:
 477                op = aco_opcode::v_cmp_gt_u64;
 478                break;
 479             case aco_opcode::v_cmp_ge_u64:
 480                op = aco_opcode::v_cmp_le_u64;
 481                break;
 482             default: /* eq and ne are commutative */
 483                break;
 484          }
 485          Temp t = src0;
 486          src0 = src1;
 487          src1 = t;
 488       } else {
 489          src1 = as_vgpr(ctx, src1);
 490       }
 491    }
 492    Builder bld(ctx->program, ctx->block);
 493    bld.vopc(op, Definition(dst), src0, src1).def(0).setHint(vcc);
 494 }
 495
 496 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 497 {
 498    if (dst.regClass() == s2) {
 499       emit_vopc_instruction(ctx, instr, op, dst);
 500       if (!ctx->divergent_vals[instr->dest.dest.ssa.index])
 501          emit_split_vector(ctx, dst, 2);
 502    } else if (dst.regClass() == s1) {
 503       Temp src0 = get_alu_src(ctx, instr->src[0]);
 504       Temp src1 = get_alu_src(ctx, instr->src[1]);
 505       assert(src0.type() == RegType::sgpr && src1.type() == RegType::sgpr);
 506
 507       Builder bld(ctx->program, ctx->block);
 508       bld.sopc(op, bld.scc(Definition(dst)), src0, src1);
 509
 510    } else {
 511       assert(false);
 512    }
 513 }
 514
 515 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, aco_opcode op32, aco_opcode op64, Temp dst)
 516 {
 517    Builder bld(ctx->program, ctx->block);
 518    Temp src0 = get_alu_src(ctx, instr->src[0]);
 519    Temp src1 = get_alu_src(ctx, instr->src[1]);
 520    if (dst.regClass() == s2) {
 521       bld.sop2(op64, Definition(dst), bld.def(s1, scc),
 522                as_divergent_bool(ctx, src0, false), as_divergent_bool(ctx, src1, false));
 523    } else {
 524       assert(dst.regClass() == s1);
 525       bld.sop2(op32, bld.def(s1), bld.scc(Definition(dst)),
 526                as_uniform_bool(ctx, src0), as_uniform_bool(ctx, src1));
 527    }
 528 }
 529
 530
 531 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 532 {
 533    Builder bld(ctx->program, ctx->block);
 534    Temp cond = get_alu_src(ctx, instr->src[0]);
 535    Temp then = get_alu_src(ctx, instr->src[1]);
 536    Temp els = get_alu_src(ctx, instr->src[2]);
 537
 538    if (dst.type() == RegType::vgpr) {
 539       cond = as_divergent_bool(ctx, cond, true);
 540
 541       aco_ptr<Instruction> bcsel;
 542       if (dst.size() == 1) {
 543          then = as_vgpr(ctx, then);
 544          els = as_vgpr(ctx, els);
 545
 546          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 547       } else if (dst.size() == 2) {
 548          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 549          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 550          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 551          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 552
 553          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 554          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 555
 556          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 557       } else {
 558          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 559          nir_print_instr(&instr->instr, stderr);
 560          fprintf(stderr, "\n");
 561       }
 562       return;
 563    }
 564
 565    if (instr->dest.dest.ssa.bit_size != 1) { /* uniform condition and values in sgpr */
 566       if (dst.regClass() == s1 || dst.regClass() == s2) {
 567          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 568          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 569          bld.sop2(op, Definition(dst), then, els, bld.scc(as_uniform_bool(ctx, cond)));
 570       } else {
 571          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 572          nir_print_instr(&instr->instr, stderr);
 573          fprintf(stderr, "\n");
 574       }
 575       return;
 576    }
 577
 578    /* boolean bcsel */
 579    assert(instr->dest.dest.ssa.bit_size == 1);
 580
 581    if (dst.regClass() == s1)
 582       cond = as_uniform_bool(ctx, cond);
 583
 584    if (cond.regClass() == s1) { /* uniform selection */
 585       aco_opcode op;
 586       if (dst.regClass() == s2) {
 587          op = aco_opcode::s_cselect_b64;
 588          then = as_divergent_bool(ctx, then, false);
 589          els = as_divergent_bool(ctx, els, false);
 590       } else {
 591          assert(dst.regClass() == s1);
 592          op = aco_opcode::s_cselect_b32;
 593          then = as_uniform_bool(ctx, then);
 594          els = as_uniform_bool(ctx, els);
 595       }
 596       bld.sop2(op, Definition(dst), then, els, bld.scc(cond));
 597       return;
 598    }
 599
 600    /* divergent boolean bcsel
 601     * this implements bcsel on bools: dst = s0 ? s1 : s2
 602     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 603    assert (dst.regClass() == s2);
 604    then = as_divergent_bool(ctx, then, false);
 605    els = as_divergent_bool(ctx, els, false);
 606
 607    if (cond.id() != then.id())
 608       then = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), cond, then);
 609
 610    if (cond.id() == els.id())
 611       bld.sop1(aco_opcode::s_mov_b64, Definition(dst), then);
 612    else
 613       bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), then,
 614                bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), els, cond));
 615 }
 616
 617 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 618 {
 619    if (!instr->dest.dest.is_ssa) {
 620       fprintf(stderr, "nir alu dst not in ssa: ");
 621       nir_print_instr(&instr->instr, stderr);
 622       fprintf(stderr, "\n");
 623       abort();
 624    }
 625    Builder bld(ctx->program, ctx->block);
 626    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 627    switch(instr->op) {
 628    case nir_op_vec2:
 629    case nir_op_vec3:
 630    case nir_op_vec4: {
 631       std::array<Temp,4> elems;
 632       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 633       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 634          elems[i] = get_alu_src(ctx, instr->src[i]);
 635          vec->operands[i] = Operand{elems[i]};
 636       }
 637       vec->definitions[0] = Definition(dst);
 638       ctx->block->instructions.emplace_back(std::move(vec));
 639       ctx->allocated_vec.emplace(dst.id(), elems);
 640       break;
 641    }
 642    case nir_op_mov: {
 643       Temp src = get_alu_src(ctx, instr->src[0]);
 644       aco_ptr<Instruction> mov;
 645       if (dst.type() == RegType::sgpr) {
 646          if (src.type() == RegType::vgpr)
 647             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 648          else if (src.regClass() == s1)
 649             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 650          else if (src.regClass() == s2)
 651             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 652          else
 653             unreachable("wrong src register class for nir_op_imov");
 654       } else if (dst.regClass() == v1) {
 655          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 656       } else if (dst.regClass() == v2) {
 657          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 658       } else {
 659          nir_print_instr(&instr->instr, stderr);
 660          unreachable("Should have been lowered to scalar.");
 661       }
 662       break;
 663    }
 664    case nir_op_inot: {
 665       Temp src = get_alu_src(ctx, instr->src[0]);
 666       /* uniform booleans */
 667       if (instr->dest.dest.ssa.bit_size == 1 && dst.regClass() == s1) {
 668          if (src.regClass() == s1) {
 669             /* in this case, src is either 1 or 0 */
 670             bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.scc(Definition(dst)), Operand(1u), src);
 671          } else {
 672             /* src is either exec_mask or 0 */
 673             assert(src.regClass() == s2);
 674             bld.sopc(aco_opcode::s_cmp_eq_u64, bld.scc(Definition(dst)), Operand(0u), src);
 675          }
 676       } else if (dst.regClass() == v1) {
 677          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 678       } else if (dst.type() == RegType::sgpr) {
 679          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 680          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 681       } else {
 682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 683          nir_print_instr(&instr->instr, stderr);
 684          fprintf(stderr, "\n");
 685       }
 686       break;
 687    }
 688    case nir_op_ineg: {
 689       Temp src = get_alu_src(ctx, instr->src[0]);
 690       if (dst.regClass() == v1) {
 691          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 692       } else if (dst.regClass() == s1) {
 693          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 694       } else if (dst.size() == 2) {
 695          Temp src0 = bld.tmp(dst.type(), 1);
 696          Temp src1 = bld.tmp(dst.type(), 1);
 697          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 698
 699          if (dst.regClass() == s2) {
 700             Temp carry = bld.tmp(s1);
 701             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 702             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 703             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 704          } else {
 705             Temp lower = bld.tmp(v1);
 706             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 707             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 708             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 709          }
 710       } else {
 711          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 712          nir_print_instr(&instr->instr, stderr);
 713          fprintf(stderr, "\n");
 714       }
 715       break;
 716    }
 717    case nir_op_iabs: {
 718       if (dst.regClass() == s1) {
 719          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 720       } else if (dst.regClass() == v1) {
 721          Temp src = get_alu_src(ctx, instr->src[0]);
 722          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 723       } else {
 724          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 725          nir_print_instr(&instr->instr, stderr);
 726          fprintf(stderr, "\n");
 727       }
 728       break;
 729    }
 730    case nir_op_isign: {
 731       Temp src = get_alu_src(ctx, instr->src[0]);
 732       if (dst.regClass() == s1) {
 733          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 734          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 735          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 736       } else if (dst.regClass() == s2) {
 737          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 738          Temp neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 739          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, neqz);
 740       } else if (dst.regClass() == v1) {
 741          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 742          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
 743          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 744       } else if (dst.regClass() == v2) {
 745          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 746          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 747          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
 748          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 749          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 750          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 751       } else {
 752          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 753          nir_print_instr(&instr->instr, stderr);
 754          fprintf(stderr, "\n");
 755       }
 756       break;
 757    }
 758    case nir_op_imax: {
 759       if (dst.regClass() == v1) {
 760          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 761       } else if (dst.regClass() == s1) {
 762          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 763       } else {
 764          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 765          nir_print_instr(&instr->instr, stderr);
 766          fprintf(stderr, "\n");
 767       }
 768       break;
 769    }
 770    case nir_op_umax: {
 771       if (dst.regClass() == v1) {
 772          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 773       } else if (dst.regClass() == s1) {
 774          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 775       } else {
 776          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 777          nir_print_instr(&instr->instr, stderr);
 778          fprintf(stderr, "\n");
 779       }
 780       break;
 781    }
 782    case nir_op_imin: {
 783       if (dst.regClass() == v1) {
 784          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 785       } else if (dst.regClass() == s1) {
 786          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 787       } else {
 788          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 789          nir_print_instr(&instr->instr, stderr);
 790          fprintf(stderr, "\n");
 791       }
 792       break;
 793    }
 794    case nir_op_umin: {
 795       if (dst.regClass() == v1) {
 796          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 797       } else if (dst.regClass() == s1) {
 798          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
 799       } else {
 800          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 801          nir_print_instr(&instr->instr, stderr);
 802          fprintf(stderr, "\n");
 803       }
 804       break;
 805    }
 806    case nir_op_ior: {
 807       if (instr->dest.dest.ssa.bit_size == 1) {
 808          emit_boolean_logic(ctx, instr, aco_opcode::s_or_b32, aco_opcode::s_or_b64, dst);
 809       } else if (dst.regClass() == v1) {
 810          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
 811       } else if (dst.regClass() == s1) {
 812          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
 813       } else if (dst.regClass() == s2) {
 814          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
 815       } else {
 816          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 817          nir_print_instr(&instr->instr, stderr);
 818          fprintf(stderr, "\n");
 819       }
 820       break;
 821    }
 822    case nir_op_iand: {
 823       if (instr->dest.dest.ssa.bit_size == 1) {
 824          emit_boolean_logic(ctx, instr, aco_opcode::s_and_b32, aco_opcode::s_and_b64, dst);
 825       } else if (dst.regClass() == v1) {
 826          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
 827       } else if (dst.regClass() == s1) {
 828          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
 829       } else if (dst.regClass() == s2) {
 830          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
 831       } else {
 832          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 833          nir_print_instr(&instr->instr, stderr);
 834          fprintf(stderr, "\n");
 835       }
 836       break;
 837    }
 838    case nir_op_ixor: {
 839       if (instr->dest.dest.ssa.bit_size == 1) {
 840          emit_boolean_logic(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::s_xor_b64, dst);
 841       } else if (dst.regClass() == v1) {
 842          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
 843       } else if (dst.regClass() == s1) {
 844          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
 845       } else if (dst.regClass() == s2) {
 846          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
 847       } else {
 848          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 849          nir_print_instr(&instr->instr, stderr);
 850          fprintf(stderr, "\n");
 851       }
 852       break;
 853    }
 854    case nir_op_ushr: {
 855       if (dst.regClass() == v1) {
 856          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
 857       } else if (dst.regClass() == v2) {
 858          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
 859                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 860       } else if (dst.regClass() == s2) {
 861          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
 862       } else if (dst.regClass() == s1) {
 863          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
 864       } else {
 865          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 866          nir_print_instr(&instr->instr, stderr);
 867          fprintf(stderr, "\n");
 868       }
 869       break;
 870    }
 871    case nir_op_ishl: {
 872       if (dst.regClass() == v1) {
 873          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
 874       } else if (dst.regClass() == v2) {
 875          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
 876                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 877       } else if (dst.regClass() == s1) {
 878          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
 879       } else if (dst.regClass() == s2) {
 880          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
 881       } else {
 882          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 883          nir_print_instr(&instr->instr, stderr);
 884          fprintf(stderr, "\n");
 885       }
 886       break;
 887    }
 888    case nir_op_ishr: {
 889       if (dst.regClass() == v1) {
 890          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
 891       } else if (dst.regClass() == v2) {
 892          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
 893                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 894       } else if (dst.regClass() == s1) {
 895          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
 896       } else if (dst.regClass() == s2) {
 897          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
 898       } else {
 899          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 900          nir_print_instr(&instr->instr, stderr);
 901          fprintf(stderr, "\n");
 902       }
 903       break;
 904    }
 905    case nir_op_find_lsb: {
 906       Temp src = get_alu_src(ctx, instr->src[0]);
 907       if (src.regClass() == s1) {
 908          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
 909       } else if (src.regClass() == v1) {
 910          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
 911       } else if (src.regClass() == s2) {
 912          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
 913       } else {
 914          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 915          nir_print_instr(&instr->instr, stderr);
 916          fprintf(stderr, "\n");
 917       }
 918       break;
 919    }
 920    case nir_op_ufind_msb:
 921    case nir_op_ifind_msb: {
 922       Temp src = get_alu_src(ctx, instr->src[0]);
 923       if (src.regClass() == s1 || src.regClass() == s2) {
 924          aco_opcode op = src.regClass() == s2 ?
 925                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
 926                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
 927          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
 928
 929          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
 930                                         Operand(src.size() * 32u - 1u), msb_rev);
 931          Temp msb = sub.def(0).getTemp();
 932          Temp carry = sub.def(1).getTemp();
 933
 934          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, carry);
 935       } else if (src.regClass() == v1) {
 936          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
 937          Temp msb_rev = bld.tmp(v1);
 938          emit_vop1_instruction(ctx, instr, op, msb_rev);
 939          Temp msb = bld.tmp(v1);
 940          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
 941          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
 942       } else {
 943          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 944          nir_print_instr(&instr->instr, stderr);
 945          fprintf(stderr, "\n");
 946       }
 947       break;
 948    }
 949    case nir_op_bitfield_reverse: {
 950       if (dst.regClass() == s1) {
 951          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
 952       } else if (dst.regClass() == v1) {
 953          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
 954       } else {
 955          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 956          nir_print_instr(&instr->instr, stderr);
 957          fprintf(stderr, "\n");
 958       }
 959       break;
 960    }
 961    case nir_op_iadd: {
 962       if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
 964          break;
 965       }
 966
 967       Temp src0 = get_alu_src(ctx, instr->src[0]);
 968       Temp src1 = get_alu_src(ctx, instr->src[1]);
 969       if (dst.regClass() == v1) {
 970          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
 971          break;
 972       }
 973
 974       assert(src0.size() == 2 && src1.size() == 2);
 975       Temp src00 = bld.tmp(src0.type(), 1);
 976       Temp src01 = bld.tmp(dst.type(), 1);
 977       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
 978       Temp src10 = bld.tmp(src1.type(), 1);
 979       Temp src11 = bld.tmp(dst.type(), 1);
 980       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
 981
 982       if (dst.regClass() == s2) {
 983          Temp carry = bld.tmp(s1);
 984          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
 985          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
 986          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 987       } else if (dst.regClass() == v2) {
 988          Temp dst0 = bld.tmp(v1);
 989          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
 990          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
 991          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 992       } else {
 993          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 994          nir_print_instr(&instr->instr, stderr);
 995          fprintf(stderr, "\n");
 996       }
 997       break;
 998    }
 999    case nir_op_uadd_sat: {
1000       Temp src0 = get_alu_src(ctx, instr->src[0]);
1001       Temp src1 = get_alu_src(ctx, instr->src[1]);
1002       if (dst.regClass() == s1) {
1003          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1004          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1005                   src0, src1);
1006          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1007       } else if (dst.regClass() == v1) {
1008          if (ctx->options->chip_class >= GFX9) {
1009             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1010             add->operands[0] = Operand(src0);
1011             add->operands[1] = Operand(src1);
1012             add->definitions[0] = Definition(dst);
1013             add->clamp = 1;
1014             ctx->block->instructions.emplace_back(std::move(add));
1015          } else {
1016             if (src1.regClass() != v1)
1017                std::swap(src0, src1);
1018             assert(src1.regClass() == v1);
1019             Temp tmp = bld.tmp(v1);
1020             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1021             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1022          }
1023       } else {
1024          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1025          nir_print_instr(&instr->instr, stderr);
1026          fprintf(stderr, "\n");
1027       }
1028       break;
1029    }
1030    case nir_op_uadd_carry: {
1031       Temp src0 = get_alu_src(ctx, instr->src[0]);
1032       Temp src1 = get_alu_src(ctx, instr->src[1]);
1033       if (dst.regClass() == s1) {
1034          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1035          break;
1036       }
1037       if (dst.regClass() == v1) {
1038          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1039          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1040          break;
1041       }
1042
1043       Temp src00 = bld.tmp(src0.type(), 1);
1044       Temp src01 = bld.tmp(dst.type(), 1);
1045       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1046       Temp src10 = bld.tmp(src1.type(), 1);
1047       Temp src11 = bld.tmp(dst.type(), 1);
1048       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1049       if (dst.regClass() == s2) {
1050          Temp carry = bld.tmp(s1);
1051          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1052          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1053          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1054       } else if (dst.regClass() == v2) {
1055          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1056          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1057          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1058          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1059       } else {
1060          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1061          nir_print_instr(&instr->instr, stderr);
1062          fprintf(stderr, "\n");
1063       }
1064       break;
1065    }
1066    case nir_op_isub: {
1067       if (dst.regClass() == s1) {
1068          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1069          break;
1070       }
1071
1072       Temp src0 = get_alu_src(ctx, instr->src[0]);
1073       Temp src1 = get_alu_src(ctx, instr->src[1]);
1074       if (dst.regClass() == v1) {
1075          bld.vsub32(Definition(dst), src0, src1);
1076          break;
1077       }
1078
1079       Temp src00 = bld.tmp(src0.type(), 1);
1080       Temp src01 = bld.tmp(dst.type(), 1);
1081       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1082       Temp src10 = bld.tmp(src1.type(), 1);
1083       Temp src11 = bld.tmp(dst.type(), 1);
1084       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1085       if (dst.regClass() == s2) {
1086          Temp carry = bld.tmp(s1);
1087          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1088          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1089          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1090       } else if (dst.regClass() == v2) {
1091          Temp lower = bld.tmp(v1);
1092          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1093          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1094          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1095       } else {
1096          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1097          nir_print_instr(&instr->instr, stderr);
1098          fprintf(stderr, "\n");
1099       }
1100       break;
1101    }
1102    case nir_op_usub_borrow: {
1103       Temp src0 = get_alu_src(ctx, instr->src[0]);
1104       Temp src1 = get_alu_src(ctx, instr->src[1]);
1105       if (dst.regClass() == s1) {
1106          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1107          break;
1108       } else if (dst.regClass() == v1) {
1109          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1110          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1111          break;
1112       }
1113
1114       Temp src00 = bld.tmp(src0.type(), 1);
1115       Temp src01 = bld.tmp(dst.type(), 1);
1116       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1117       Temp src10 = bld.tmp(src1.type(), 1);
1118       Temp src11 = bld.tmp(dst.type(), 1);
1119       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1120       if (dst.regClass() == s2) {
1121          Temp borrow = bld.tmp(s1);
1122          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1123          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1124          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1125       } else if (dst.regClass() == v2) {
1126          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1127          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1128          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1129          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1130       } else {
1131          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1132          nir_print_instr(&instr->instr, stderr);
1133          fprintf(stderr, "\n");
1134       }
1135       break;
1136    }
1137    case nir_op_imul: {
1138       if (dst.regClass() == v1) {
1139          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1140                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1141       } else if (dst.regClass() == s1) {
1142          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1143       } else {
1144          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1145          nir_print_instr(&instr->instr, stderr);
1146          fprintf(stderr, "\n");
1147       }
1148       break;
1149    }
1150    case nir_op_umul_high: {
1151       if (dst.regClass() == v1) {
1152          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1153       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1154          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1155       } else if (dst.regClass() == s1) {
1156          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1157                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1158          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1159       } else {
1160          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1161          nir_print_instr(&instr->instr, stderr);
1162          fprintf(stderr, "\n");
1163       }
1164       break;
1165    }
1166    case nir_op_imul_high: {
1167       if (dst.regClass() == v1) {
1168          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1169       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1170          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1171       } else if (dst.regClass() == s1) {
1172          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1173                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1174          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1175       } else {
1176          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1177          nir_print_instr(&instr->instr, stderr);
1178          fprintf(stderr, "\n");
1179       }
1180       break;
1181    }
1182    case nir_op_fmul: {
1183       if (dst.size() == 1) {
1184          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1185       } else if (dst.size() == 2) {
1186          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1187                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1188       } else {
1189          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1190          nir_print_instr(&instr->instr, stderr);
1191          fprintf(stderr, "\n");
1192       }
1193       break;
1194    }
1195    case nir_op_fadd: {
1196       if (dst.size() == 1) {
1197          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1198       } else if (dst.size() == 2) {
1199          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1200                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1201       } else {
1202          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1203          nir_print_instr(&instr->instr, stderr);
1204          fprintf(stderr, "\n");
1205       }
1206       break;
1207    }
1208    case nir_op_fsub: {
1209       Temp src0 = get_alu_src(ctx, instr->src[0]);
1210       Temp src1 = get_alu_src(ctx, instr->src[1]);
1211       if (dst.size() == 1) {
1212          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1213             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1214          else
1215             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1216       } else if (dst.size() == 2) {
1217          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1218                                      get_alu_src(ctx, instr->src[0]),
1219                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1220          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1221          sub->neg[1] = true;
1222       } else {
1223          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1224          nir_print_instr(&instr->instr, stderr);
1225          fprintf(stderr, "\n");
1226       }
1227       break;
1228    }
1229    case nir_op_fmax: {
1230       if (dst.size() == 1) {
1231          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true);
1232       } else if (dst.size() == 2) {
1233          bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1234                   get_alu_src(ctx, instr->src[0]),
1235                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1236       } else {
1237          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1238          nir_print_instr(&instr->instr, stderr);
1239          fprintf(stderr, "\n");
1240       }
1241       break;
1242    }
1243    case nir_op_fmin: {
1244       if (dst.size() == 1) {
1245          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true);
1246       } else if (dst.size() == 2) {
1247          bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1248                   get_alu_src(ctx, instr->src[0]),
1249                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1250       } else {
1251          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1252          nir_print_instr(&instr->instr, stderr);
1253          fprintf(stderr, "\n");
1254       }
1255       break;
1256    }
1257    case nir_op_fmax3: {
1258       if (dst.size() == 1) {
1259          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst);
1260       } else {
1261          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1262          nir_print_instr(&instr->instr, stderr);
1263          fprintf(stderr, "\n");
1264       }
1265       break;
1266    }
1267    case nir_op_fmin3: {
1268       if (dst.size() == 1) {
1269          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst);
1270       } else {
1271          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1272          nir_print_instr(&instr->instr, stderr);
1273          fprintf(stderr, "\n");
1274       }
1275       break;
1276    }
1277    case nir_op_fmed3: {
1278       if (dst.size() == 1) {
1279          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst);
1280       } else {
1281          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1282          nir_print_instr(&instr->instr, stderr);
1283          fprintf(stderr, "\n");
1284       }
1285       break;
1286    }
1287    case nir_op_umax3: {
1288       if (dst.size() == 1) {
1289          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1290       } else {
1291          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1292          nir_print_instr(&instr->instr, stderr);
1293          fprintf(stderr, "\n");
1294       }
1295       break;
1296    }
1297    case nir_op_umin3: {
1298       if (dst.size() == 1) {
1299          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1300       } else {
1301          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1302          nir_print_instr(&instr->instr, stderr);
1303          fprintf(stderr, "\n");
1304       }
1305       break;
1306    }
1307    case nir_op_umed3: {
1308       if (dst.size() == 1) {
1309          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1310       } else {
1311          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1312          nir_print_instr(&instr->instr, stderr);
1313          fprintf(stderr, "\n");
1314       }
1315       break;
1316    }
1317    case nir_op_imax3: {
1318       if (dst.size() == 1) {
1319          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1320       } else {
1321          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1322          nir_print_instr(&instr->instr, stderr);
1323          fprintf(stderr, "\n");
1324       }
1325       break;
1326    }
1327    case nir_op_imin3: {
1328       if (dst.size() == 1) {
1329          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1330       } else {
1331          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1332          nir_print_instr(&instr->instr, stderr);
1333          fprintf(stderr, "\n");
1334       }
1335       break;
1336    }
1337    case nir_op_imed3: {
1338       if (dst.size() == 1) {
1339          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_cube_face_coord: {
1348       Temp in = get_alu_src(ctx, instr->src[0], 3);
1349       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1350                       emit_extract_vector(ctx, in, 1, v1),
1351                       emit_extract_vector(ctx, in, 2, v1) };
1352       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1353       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1354       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1355       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1356       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1357       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1358       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1359       break;
1360    }
1361    case nir_op_cube_face_index: {
1362       Temp in = get_alu_src(ctx, instr->src[0], 3);
1363       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1364                       emit_extract_vector(ctx, in, 1, v1),
1365                       emit_extract_vector(ctx, in, 2, v1) };
1366       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1367       break;
1368    }
1369    case nir_op_bcsel: {
1370       emit_bcsel(ctx, instr, dst);
1371       break;
1372    }
1373    case nir_op_frsq: {
1374       if (dst.size() == 1) {
1375          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f32, dst);
1376       } else if (dst.size() == 2) {
1377          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1378       } else {
1379          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1380          nir_print_instr(&instr->instr, stderr);
1381          fprintf(stderr, "\n");
1382       }
1383       break;
1384    }
1385    case nir_op_fneg: {
1386       Temp src = get_alu_src(ctx, instr->src[0]);
1387       if (dst.size() == 1) {
1388          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1389       } else if (dst.size() == 2) {
1390          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1391          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1392          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1393          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1394       } else {
1395          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1396          nir_print_instr(&instr->instr, stderr);
1397          fprintf(stderr, "\n");
1398       }
1399       break;
1400    }
1401    case nir_op_fabs: {
1402       Temp src = get_alu_src(ctx, instr->src[0]);
1403       if (dst.size() == 1) {
1404          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1405       } else if (dst.size() == 2) {
1406          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1407          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1408          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1409          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1410       } else {
1411          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1412          nir_print_instr(&instr->instr, stderr);
1413          fprintf(stderr, "\n");
1414       }
1415       break;
1416    }
1417    case nir_op_fsat: {
1418       Temp src = get_alu_src(ctx, instr->src[0]);
1419       if (dst.size() == 1) {
1420          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1421       } else if (dst.size() == 2) {
1422          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1423          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1424          vop3->clamp = true;
1425       } else {
1426          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1427          nir_print_instr(&instr->instr, stderr);
1428          fprintf(stderr, "\n");
1429       }
1430       break;
1431    }
1432    case nir_op_flog2: {
1433       if (dst.size() == 1) {
1434          emit_vop1_instruction(ctx, instr, aco_opcode::v_log_f32, dst);
1435       } else {
1436          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1437          nir_print_instr(&instr->instr, stderr);
1438          fprintf(stderr, "\n");
1439       }
1440       break;
1441    }
1442    case nir_op_frcp: {
1443       if (dst.size() == 1) {
1444          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f32, dst);
1445       } else if (dst.size() == 2) {
1446          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1447       } else {
1448          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1449          nir_print_instr(&instr->instr, stderr);
1450          fprintf(stderr, "\n");
1451       }
1452       break;
1453    }
1454    case nir_op_fexp2: {
1455       if (dst.size() == 1) {
1456          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1457       } else {
1458          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1459          nir_print_instr(&instr->instr, stderr);
1460          fprintf(stderr, "\n");
1461       }
1462       break;
1463    }
1464    case nir_op_fsqrt: {
1465       if (dst.size() == 1) {
1466          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f32, dst);
1467       } else if (dst.size() == 2) {
1468          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1469       } else {
1470          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1471          nir_print_instr(&instr->instr, stderr);
1472          fprintf(stderr, "\n");
1473       }
1474       break;
1475    }
1476    case nir_op_ffract: {
1477       if (dst.size() == 1) {
1478          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1479       } else if (dst.size() == 2) {
1480          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1481       } else {
1482          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1483          nir_print_instr(&instr->instr, stderr);
1484          fprintf(stderr, "\n");
1485       }
1486       break;
1487    }
1488    case nir_op_ffloor: {
1489       if (dst.size() == 1) {
1490          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1491       } else if (dst.size() == 2) {
1492          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst);
1493       } else {
1494          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1495          nir_print_instr(&instr->instr, stderr);
1496          fprintf(stderr, "\n");
1497       }
1498       break;
1499    }
1500    case nir_op_fceil: {
1501       if (dst.size() == 1) {
1502          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1503       } else if (dst.size() == 2) {
1504          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1505       } else {
1506          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1507          nir_print_instr(&instr->instr, stderr);
1508          fprintf(stderr, "\n");
1509       }
1510       break;
1511    }
1512    case nir_op_ftrunc: {
1513       if (dst.size() == 1) {
1514          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1515       } else if (dst.size() == 2) {
1516          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f64, dst);
1517       } else {
1518          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1519          nir_print_instr(&instr->instr, stderr);
1520          fprintf(stderr, "\n");
1521       }
1522       break;
1523    }
1524    case nir_op_fround_even: {
1525       if (dst.size() == 1) {
1526          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1527       } else if (dst.size() == 2) {
1528          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1529       } else {
1530          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1531          nir_print_instr(&instr->instr, stderr);
1532          fprintf(stderr, "\n");
1533       }
1534       break;
1535    }
1536    case nir_op_fsin:
1537    case nir_op_fcos: {
1538       Temp src = get_alu_src(ctx, instr->src[0]);
1539       aco_ptr<Instruction> norm;
1540       if (dst.size() == 1) {
1541          Temp tmp;
1542          Operand half_pi(0x3e22f983u);
1543          if (src.type() == RegType::sgpr)
1544             tmp = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1545          else
1546             tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1547
1548          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1549          if (ctx->options->chip_class < GFX9)
1550             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1551
1552          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1553          bld.vop1(opcode, Definition(dst), tmp);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_ldexp: {
1562       if (dst.size() == 1) {
1563          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1564                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1565                   get_alu_src(ctx, instr->src[1]));
1566       } else if (dst.size() == 2) {
1567          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1568                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1569                   get_alu_src(ctx, instr->src[1]));
1570       } else {
1571          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1572          nir_print_instr(&instr->instr, stderr);
1573          fprintf(stderr, "\n");
1574       }
1575       break;
1576    }
1577    case nir_op_frexp_sig: {
1578       if (dst.size() == 1) {
1579          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1580                   get_alu_src(ctx, instr->src[0]));
1581       } else if (dst.size() == 2) {
1582          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1583                   get_alu_src(ctx, instr->src[0]));
1584       } else {
1585          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1586          nir_print_instr(&instr->instr, stderr);
1587          fprintf(stderr, "\n");
1588       }
1589       break;
1590    }
1591    case nir_op_frexp_exp: {
1592       if (instr->src[0].src.ssa->bit_size == 32) {
1593          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1594                   get_alu_src(ctx, instr->src[0]));
1595       } else if (instr->src[0].src.ssa->bit_size == 64) {
1596          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1597                   get_alu_src(ctx, instr->src[0]));
1598       } else {
1599          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1600          nir_print_instr(&instr->instr, stderr);
1601          fprintf(stderr, "\n");
1602       }
1603       break;
1604    }
1605    case nir_op_fsign: {
1606       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1607       if (dst.size() == 1) {
1608          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1609          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1610          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1611          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1612       } else if (dst.size() == 2) {
1613          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1614          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1615          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, src, cond);
1616
1617          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1618          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1619          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1620
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_f2f32: {
1630       if (instr->src[0].src.ssa->bit_size == 64) {
1631          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1632       } else {
1633          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1634          nir_print_instr(&instr->instr, stderr);
1635          fprintf(stderr, "\n");
1636       }
1637       break;
1638    }
1639    case nir_op_f2f64: {
1640       if (instr->src[0].src.ssa->bit_size == 32) {
1641          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_i2f32: {
1650       assert(dst.size() == 1);
1651       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1652       break;
1653    }
1654    case nir_op_i2f64: {
1655       if (instr->src[0].src.ssa->bit_size == 32) {
1656          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1657       } else if (instr->src[0].src.ssa->bit_size == 64) {
1658          Temp src = get_alu_src(ctx, instr->src[0]);
1659          RegClass rc = RegClass(src.type(), 1);
1660          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1661          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1662          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1663          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1664          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1665          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1666
1667       } else {
1668          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1669          nir_print_instr(&instr->instr, stderr);
1670          fprintf(stderr, "\n");
1671       }
1672       break;
1673    }
1674    case nir_op_u2f32: {
1675       assert(dst.size() == 1);
1676       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1677       break;
1678    }
1679    case nir_op_u2f64: {
1680       if (instr->src[0].src.ssa->bit_size == 32) {
1681          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1682       } else if (instr->src[0].src.ssa->bit_size == 64) {
1683          Temp src = get_alu_src(ctx, instr->src[0]);
1684          RegClass rc = RegClass(src.type(), 1);
1685          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1686          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1687          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1688          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1689          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1690          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_f2i32: {
1699       Temp src = get_alu_src(ctx, instr->src[0]);
1700       if (instr->src[0].src.ssa->bit_size == 32) {
1701          if (dst.type() == RegType::vgpr)
1702             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1703          else
1704             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1705                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1706
1707       } else if (instr->src[0].src.ssa->bit_size == 64) {
1708          if (dst.type() == RegType::vgpr)
1709             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1710          else
1711             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1712                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1713
1714       } else {
1715          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1716          nir_print_instr(&instr->instr, stderr);
1717          fprintf(stderr, "\n");
1718       }
1719       break;
1720    }
1721    case nir_op_f2u32: {
1722       Temp src = get_alu_src(ctx, instr->src[0]);
1723       if (instr->src[0].src.ssa->bit_size == 32) {
1724          if (dst.type() == RegType::vgpr)
1725             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
1726          else
1727             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1728                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
1729
1730       } else if (instr->src[0].src.ssa->bit_size == 64) {
1731          if (dst.type() == RegType::vgpr)
1732             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
1733          else
1734             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1735                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
1736
1737       } else {
1738          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1739          nir_print_instr(&instr->instr, stderr);
1740          fprintf(stderr, "\n");
1741       }
1742       break;
1743    }
1744    case nir_op_f2i64: {
1745       Temp src = get_alu_src(ctx, instr->src[0]);
1746       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1747          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1748          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
1749          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1750          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
1751          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1752          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
1753          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1754          Temp new_exponent = bld.tmp(v1);
1755          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
1756          mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
1757          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
1758          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1759          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1760          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
1761          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
1762          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
1763          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
1764          Temp new_lower = bld.tmp(v1);
1765          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
1766          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
1767          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
1768
1769       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1770          if (src.type() == RegType::vgpr)
1771             src = bld.as_uniform(src);
1772          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1773          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1774          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1775          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
1776          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1777          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
1778          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1779          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
1780          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1781          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
1782          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
1783          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
1784          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
1785          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
1786          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1787          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1788          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
1789          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
1790          Temp borrow = bld.tmp(s1);
1791          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
1792          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
1793          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1794
1795       } else if (instr->src[0].src.ssa->bit_size == 64) {
1796          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1797          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1798          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1799          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1800          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1801          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1802          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1803          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
1804          if (dst.type() == RegType::sgpr) {
1805             lower = bld.as_uniform(lower);
1806             upper = bld.as_uniform(upper);
1807          }
1808          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1809
1810       } else {
1811          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1812          nir_print_instr(&instr->instr, stderr);
1813          fprintf(stderr, "\n");
1814       }
1815       break;
1816    }
1817    case nir_op_f2u64: {
1818       Temp src = get_alu_src(ctx, instr->src[0]);
1819       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1820          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1821          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(s2)), Operand(64u), exponent);
1822          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
1823          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1824          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1825          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
1826          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
1827          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1828          Temp new_exponent = bld.tmp(v1);
1829          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
1830          mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
1831          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1832          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1833          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
1834          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
1835          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
1836          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
1837          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1838
1839       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1840          if (src.type() == RegType::vgpr)
1841             src = bld.as_uniform(src);
1842          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1843          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1844          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1845          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1846          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1847          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
1848          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
1849          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1850          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
1851          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
1852          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
1853          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
1854          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1855          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1856          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
1857          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
1858          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
1859          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1860
1861       } else if (instr->src[0].src.ssa->bit_size == 64) {
1862          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1863          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1864          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1865          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1866          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1867          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1868          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1869          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
1870          if (dst.type() == RegType::sgpr) {
1871             lower = bld.as_uniform(lower);
1872             upper = bld.as_uniform(upper);
1873          }
1874          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1875
1876       } else {
1877          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1878          nir_print_instr(&instr->instr, stderr);
1879          fprintf(stderr, "\n");
1880       }
1881       break;
1882    }
1883    case nir_op_b2f32: {
1884       Temp src = get_alu_src(ctx, instr->src[0]);
1885       if (dst.regClass() == s1) {
1886          src = as_uniform_bool(ctx, src);
1887          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
1888       } else if (dst.regClass() == v1) {
1889          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u),
1890                       as_divergent_bool(ctx, src, true));
1891       } else {
1892          unreachable("Wrong destination register class for nir_op_b2f32.");
1893       }
1894       break;
1895    }
1896    case nir_op_b2f64: {
1897       Temp src = get_alu_src(ctx, instr->src[0]);
1898       if (dst.regClass() == s2) {
1899          src = as_uniform_bool(ctx, src);
1900          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
1901       } else if (dst.regClass() == v2) {
1902          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
1903          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one,
1904                       as_divergent_bool(ctx, src, true));
1905          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1906       } else {
1907          unreachable("Wrong destination register class for nir_op_b2f64.");
1908       }
1909       break;
1910    }
1911    case nir_op_i2i32: {
1912       Temp src = get_alu_src(ctx, instr->src[0]);
1913       if (instr->src[0].src.ssa->bit_size == 64) {
1914          /* we can actually just say dst = src, as it would map the lower register */
1915          emit_extract_vector(ctx, src, 0, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_u2u32: {
1924       Temp src = get_alu_src(ctx, instr->src[0]);
1925       if (instr->src[0].src.ssa->bit_size == 16) {
1926          if (dst.regClass() == s1) {
1927             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
1928          } else {
1929             // TODO: do better with SDWA
1930             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
1931          }
1932       } else if (instr->src[0].src.ssa->bit_size == 64) {
1933          /* we can actually just say dst = src, as it would map the lower register */
1934          emit_extract_vector(ctx, src, 0, dst);
1935       } else {
1936          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1937          nir_print_instr(&instr->instr, stderr);
1938          fprintf(stderr, "\n");
1939       }
1940       break;
1941    }
1942    case nir_op_i2i64: {
1943       Temp src = get_alu_src(ctx, instr->src[0]);
1944       if (instr->src[0].src.ssa->bit_size == 32) {
1945          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
1946       } else {
1947          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1948          nir_print_instr(&instr->instr, stderr);
1949          fprintf(stderr, "\n");
1950       }
1951       break;
1952    }
1953    case nir_op_u2u64: {
1954       Temp src = get_alu_src(ctx, instr->src[0]);
1955       if (instr->src[0].src.ssa->bit_size == 32) {
1956          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
1957       } else {
1958          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1959          nir_print_instr(&instr->instr, stderr);
1960          fprintf(stderr, "\n");
1961       }
1962       break;
1963    }
1964    case nir_op_b2i32: {
1965       Temp src = get_alu_src(ctx, instr->src[0]);
1966       if (dst.regClass() == s1) {
1967          if (src.regClass() == s1) {
1968             bld.copy(Definition(dst), src);
1969          } else {
1970             // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
1971             assert(src.regClass() == s2);
1972             bld.sopc(aco_opcode::s_cmp_lg_u64, bld.scc(Definition(dst)), Operand(0u), src);
1973          }
1974       } else {
1975          assert(dst.regClass() == v1 && src.regClass() == s2);
1976          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
1977       }
1978       break;
1979    }
1980    case nir_op_i2b1: {
1981       Temp src = get_alu_src(ctx, instr->src[0]);
1982       if (dst.regClass() == s2) {
1983          assert(src.regClass() == v1 || src.regClass() == v2);
1984          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
1985                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
1986       } else {
1987          assert(src.regClass() == s1 && dst.regClass() == s1);
1988          bld.sopc(aco_opcode::s_cmp_lg_u32, bld.scc(Definition(dst)), Operand(0u), src);
1989       }
1990       break;
1991    }
1992    case nir_op_pack_64_2x32_split: {
1993       Temp src0 = get_alu_src(ctx, instr->src[0]);
1994       Temp src1 = get_alu_src(ctx, instr->src[1]);
1995
1996       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
1997       break;
1998    }
1999    case nir_op_unpack_64_2x32_split_x:
2000       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2001       break;
2002    case nir_op_unpack_64_2x32_split_y:
2003       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2004       break;
2005    case nir_op_pack_half_2x16: {
2006       Temp src = get_alu_src(ctx, instr->src[0], 2);
2007
2008       if (dst.regClass() == v1) {
2009          Temp src0 = bld.tmp(v1);
2010          Temp src1 = bld.tmp(v1);
2011          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2012          bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2013
2014       } else {
2015          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2016          nir_print_instr(&instr->instr, stderr);
2017          fprintf(stderr, "\n");
2018       }
2019       break;
2020    }
2021    case nir_op_unpack_half_2x16_split_x: {
2022       if (dst.regClass() == v1) {
2023          Builder bld(ctx->program, ctx->block);
2024          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2025       } else {
2026          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2027          nir_print_instr(&instr->instr, stderr);
2028          fprintf(stderr, "\n");
2029       }
2030       break;
2031    }
2032    case nir_op_unpack_half_2x16_split_y: {
2033       if (dst.regClass() == v1) {
2034          Builder bld(ctx->program, ctx->block);
2035          /* TODO: use SDWA here */
2036          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2037                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2038       } else {
2039          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2040          nir_print_instr(&instr->instr, stderr);
2041          fprintf(stderr, "\n");
2042       }
2043       break;
2044    }
2045    case nir_op_fquantize2f16: {
2046       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), get_alu_src(ctx, instr->src[0]));
2047
2048       Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2049
2050       Temp cmp_res = bld.tmp(s2);
2051       bld.vopc_e64(aco_opcode::v_cmp_class_f16, Definition(cmp_res), f16, mask).def(0).setHint(vcc);
2052
2053       Temp f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2054
2055       bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2056       break;
2057    }
2058    case nir_op_bfm: {
2059       Temp bits = get_alu_src(ctx, instr->src[0]);
2060       Temp offset = get_alu_src(ctx, instr->src[1]);
2061
2062       if (dst.regClass() == s1) {
2063          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2064       } else if (dst.regClass() == v1) {
2065          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2066       } else {
2067          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2068          nir_print_instr(&instr->instr, stderr);
2069          fprintf(stderr, "\n");
2070       }
2071       break;
2072    }
2073    case nir_op_bitfield_select: {
2074       /* (mask & insert) | (~mask & base) */
2075       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2076       Temp insert = get_alu_src(ctx, instr->src[1]);
2077       Temp base = get_alu_src(ctx, instr->src[2]);
2078
2079       /* dst = (insert & bitmask) | (base & ~bitmask) */
2080       if (dst.regClass() == s1) {
2081          aco_ptr<Instruction> sop2;
2082          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2083          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2084          Operand lhs;
2085          if (const_insert && const_bitmask) {
2086             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2087          } else {
2088             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2089             lhs = Operand(insert);
2090          }
2091
2092          Operand rhs;
2093          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2094          if (const_base && const_bitmask) {
2095             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2096          } else {
2097             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2098             rhs = Operand(base);
2099          }
2100
2101          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2102
2103       } else if (dst.regClass() == v1) {
2104          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2105             base = as_vgpr(ctx, base);
2106          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2107             insert = as_vgpr(ctx, insert);
2108
2109          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2110
2111       } else {
2112          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2113          nir_print_instr(&instr->instr, stderr);
2114          fprintf(stderr, "\n");
2115       }
2116       break;
2117    }
2118    case nir_op_ubfe:
2119    case nir_op_ibfe: {
2120       Temp base = get_alu_src(ctx, instr->src[0]);
2121       Temp offset = get_alu_src(ctx, instr->src[1]);
2122       Temp bits = get_alu_src(ctx, instr->src[2]);
2123
2124       if (dst.type() == RegType::sgpr) {
2125          Operand extract;
2126          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2127          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2128          if (const_offset && const_bits) {
2129             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2130             extract = Operand(const_extract);
2131          } else {
2132             Operand width;
2133             if (const_bits) {
2134                width = Operand(const_bits->u32 << 16);
2135             } else {
2136                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2137             }
2138             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2139          }
2140
2141          aco_opcode opcode;
2142          if (dst.regClass() == s1) {
2143             if (instr->op == nir_op_ubfe)
2144                opcode = aco_opcode::s_bfe_u32;
2145             else
2146                opcode = aco_opcode::s_bfe_i32;
2147          } else if (dst.regClass() == s2) {
2148             if (instr->op == nir_op_ubfe)
2149                opcode = aco_opcode::s_bfe_u64;
2150             else
2151                opcode = aco_opcode::s_bfe_i64;
2152          } else {
2153             unreachable("Unsupported BFE bit size");
2154          }
2155
2156          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2157
2158       } else {
2159          aco_opcode opcode;
2160          if (dst.regClass() == v1) {
2161             if (instr->op == nir_op_ubfe)
2162                opcode = aco_opcode::v_bfe_u32;
2163             else
2164                opcode = aco_opcode::v_bfe_i32;
2165          } else {
2166             unreachable("Unsupported BFE bit size");
2167          }
2168
2169          emit_vop3a_instruction(ctx, instr, opcode, dst);
2170       }
2171       break;
2172    }
2173    case nir_op_bit_count: {
2174       Temp src = get_alu_src(ctx, instr->src[0]);
2175       if (src.regClass() == s1) {
2176          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2177       } else if (src.regClass() == v1) {
2178          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2179       } else if (src.regClass() == v2) {
2180          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2181                   emit_extract_vector(ctx, src, 1, v1),
2182                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2183                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2184       } else if (src.regClass() == s2) {
2185          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2186       } else {
2187          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2188          nir_print_instr(&instr->instr, stderr);
2189          fprintf(stderr, "\n");
2190       }
2191       break;
2192    }
2193    case nir_op_flt: {
2194       if (instr->src[0].src.ssa->bit_size == 32)
2195          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_f32, dst);
2196       else if (instr->src[0].src.ssa->bit_size == 64)
2197          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_f64, dst);
2198       break;
2199    }
2200    case nir_op_fge: {
2201       if (instr->src[0].src.ssa->bit_size == 32)
2202          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_f32, dst);
2203       else if (instr->src[0].src.ssa->bit_size == 64)
2204          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_f64, dst);
2205       break;
2206    }
2207    case nir_op_feq: {
2208       if (instr->src[0].src.ssa->bit_size == 32)
2209          emit_comparison(ctx, instr, aco_opcode::v_cmp_eq_f32, dst);
2210       else if (instr->src[0].src.ssa->bit_size == 64)
2211          emit_comparison(ctx, instr, aco_opcode::v_cmp_eq_f64, dst);
2212       break;
2213    }
2214    case nir_op_fne: {
2215       if (instr->src[0].src.ssa->bit_size == 32)
2216          emit_comparison(ctx, instr, aco_opcode::v_cmp_neq_f32, dst);
2217       else if (instr->src[0].src.ssa->bit_size == 64)
2218          emit_comparison(ctx, instr, aco_opcode::v_cmp_neq_f64, dst);
2219       break;
2220    }
2221    case nir_op_ilt: {
2222       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32)
2223          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_i32, dst);
2224       else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32)
2225          emit_comparison(ctx, instr, aco_opcode::s_cmp_lt_i32, dst);
2226       else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64)
2227          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_i64, dst);
2228       break;
2229    }
2230    case nir_op_ige: {
2231       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32)
2232          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_i32, dst);
2233       else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32)
2234          emit_comparison(ctx, instr, aco_opcode::s_cmp_ge_i32, dst);
2235       else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64)
2236          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_i64, dst);
2237       break;
2238    }
2239    case nir_op_ieq: {
2240       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32) {
2241          emit_comparison(ctx, instr, aco_opcode::v_cmp_eq_i32, dst);
2242       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32) {
2243          emit_comparison(ctx, instr, aco_opcode::s_cmp_eq_i32, dst);
2244       } else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64) {
2245          emit_comparison(ctx, instr, aco_opcode::v_cmp_eq_i64, dst);
2246       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 64) {
2247          emit_comparison(ctx, instr, aco_opcode::s_cmp_eq_u64, dst);
2248       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 1) {
2249          Temp src0 = get_alu_src(ctx, instr->src[0]);
2250          Temp src1 = get_alu_src(ctx, instr->src[1]);
2251          bld.sopc(aco_opcode::s_cmp_eq_i32, bld.scc(Definition(dst)),
2252                   as_uniform_bool(ctx, src0), as_uniform_bool(ctx, src1));
2253       } else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 1) {
2254          Temp src0 = get_alu_src(ctx, instr->src[0]);
2255          Temp src1 = get_alu_src(ctx, instr->src[1]);
2256          bld.sop2(aco_opcode::s_xnor_b64, Definition(dst), bld.def(s1, scc),
2257                   as_divergent_bool(ctx, src0, false), as_divergent_bool(ctx, src1, false));
2258       } else {
2259          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2260          nir_print_instr(&instr->instr, stderr);
2261          fprintf(stderr, "\n");
2262       }
2263       break;
2264    }
2265    case nir_op_ine: {
2266       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32) {
2267          emit_comparison(ctx, instr, aco_opcode::v_cmp_lg_i32, dst);
2268       } else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64) {
2269          emit_comparison(ctx, instr, aco_opcode::v_cmp_lg_i64, dst);
2270       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32) {
2271          emit_comparison(ctx, instr, aco_opcode::s_cmp_lg_i32, dst);
2272       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 64) {
2273          emit_comparison(ctx, instr, aco_opcode::s_cmp_lg_u64, dst);
2274       } else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 1) {
2275          Temp src0 = get_alu_src(ctx, instr->src[0]);
2276          Temp src1 = get_alu_src(ctx, instr->src[1]);
2277          bld.sopc(aco_opcode::s_cmp_lg_i32, bld.scc(Definition(dst)),
2278                   as_uniform_bool(ctx, src0), as_uniform_bool(ctx, src1));
2279       } else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 1) {
2280          Temp src0 = get_alu_src(ctx, instr->src[0]);
2281          Temp src1 = get_alu_src(ctx, instr->src[1]);
2282          bld.sop2(aco_opcode::s_xor_b64, Definition(dst), bld.def(s1, scc),
2283                   as_divergent_bool(ctx, src0, false), as_divergent_bool(ctx, src1, false));
2284       } else {
2285          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2286          nir_print_instr(&instr->instr, stderr);
2287          fprintf(stderr, "\n");
2288       }
2289       break;
2290    }
2291    case nir_op_ult: {
2292       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32)
2293          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_u32, dst);
2294       else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32)
2295          emit_comparison(ctx, instr, aco_opcode::s_cmp_lt_u32, dst);
2296       else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64)
2297          emit_comparison(ctx, instr, aco_opcode::v_cmp_lt_u64, dst);
2298       break;
2299    }
2300    case nir_op_uge: {
2301       if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 32)
2302          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_u32, dst);
2303       else if (dst.regClass() == s1 && instr->src[0].src.ssa->bit_size == 32)
2304          emit_comparison(ctx, instr, aco_opcode::s_cmp_ge_u32, dst);
2305       else if (dst.regClass() == s2 && instr->src[0].src.ssa->bit_size == 64)
2306          emit_comparison(ctx, instr, aco_opcode::v_cmp_ge_u64, dst);
2307       break;
2308    }
2309    case nir_op_fddx:
2310    case nir_op_fddy:
2311    case nir_op_fddx_fine:
2312    case nir_op_fddy_fine:
2313    case nir_op_fddx_coarse:
2314    case nir_op_fddy_coarse: {
2315       Definition tl = bld.def(v1);
2316       uint16_t dpp_ctrl;
2317       if (instr->op == nir_op_fddx_fine) {
2318          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 2, 2));
2319          dpp_ctrl = dpp_quad_perm(1, 1, 3, 3);
2320       } else if (instr->op == nir_op_fddy_fine) {
2321          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 1, 0, 1));
2322          dpp_ctrl = dpp_quad_perm(2, 3, 2, 3);
2323       } else {
2324          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 0, 0));
2325          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2326             dpp_ctrl = dpp_quad_perm(1, 1, 1, 1);
2327          else
2328             dpp_ctrl = dpp_quad_perm(2, 2, 2, 2);
2329       }
2330
2331       Definition tmp = bld.def(v1);
2332       bld.vop2_dpp(aco_opcode::v_sub_f32, tmp, get_alu_src(ctx, instr->src[0]), tl.getTemp(), dpp_ctrl);
2333       emit_wqm(ctx, tmp.getTemp(), dst, true);
2334       break;
2335    }
2336    default:
2337       fprintf(stderr, "Unknown NIR ALU instr: ");
2338       nir_print_instr(&instr->instr, stderr);
2339       fprintf(stderr, "\n");
2340    }
2341 }
2342
2343 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2344 {
2345    Temp dst = get_ssa_temp(ctx, &instr->def);
2346
2347    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2348    // which get truncated the lsb if double and msb if int
2349    // for now, we only use s_mov_b64 with 64bit inline constants
2350    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2351    assert(dst.type() == RegType::sgpr);
2352
2353    if (dst.size() == 1)
2354    {
2355       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(instr->value[0].u32));
2356    } else {
2357       assert(dst.size() != 1);
2358       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2359       if (instr->def.bit_size == 64)
2360          for (unsigned i = 0; i < dst.size(); i++)
2361             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2362       else {
2363          for (unsigned i = 0; i < dst.size(); i++)
2364             vec->operands[i] = Operand{instr->value[i].u32};
2365       }
2366       vec->definitions[0] = Definition(dst);
2367       ctx->block->instructions.emplace_back(std::move(vec));
2368    }
2369 }
2370
2371 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2372 {
2373    uint32_t new_mask = 0;
2374    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2375       if (mask & (1u << i))
2376          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2377    return new_mask;
2378 }
2379
2380 void visit_store_vs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2381 {
2382    /* This wouldn't work inside control flow or with indirect offsets but
2383     * that doesn't happen because of nir_lower_io_to_temporaries(). */
2384
2385    unsigned write_mask = nir_intrinsic_write_mask(instr);
2386    unsigned component = nir_intrinsic_component(instr);
2387    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2388    unsigned idx = nir_intrinsic_base(instr) + component;
2389
2390    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2391    if (off_instr->type != nir_instr_type_load_const) {
2392       fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2393       nir_print_instr(off_instr, stderr);
2394       fprintf(stderr, "\n");
2395    }
2396    idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2397
2398    if (instr->src[0].ssa->bit_size == 64)
2399       write_mask = widen_mask(write_mask, 2);
2400
2401    for (unsigned i = 0; i < 8; ++i) {
2402       if (write_mask & (1 << i)) {
2403          ctx->vs_output.mask[idx / 4u] |= 1 << (idx % 4u);
2404          ctx->vs_output.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2405       }
2406       idx++;
2407    }
2408 }
2409
2410 void visit_store_fs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2411 {
2412    unsigned write_mask = nir_intrinsic_write_mask(instr);
2413    Operand values[4];
2414    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2415    for (unsigned i = 0; i < 4; ++i) {
2416       if (write_mask & (1 << i)) {
2417          Temp tmp = emit_extract_vector(ctx, src, i, v1);
2418          values[i] = Operand(tmp);
2419       } else {
2420          values[i] = Operand(v1);
2421       }
2422    }
2423
2424    unsigned index = nir_intrinsic_base(instr) / 4;
2425    unsigned target, col_format;
2426    unsigned enabled_channels = 0xF;
2427    aco_opcode compr_op = (aco_opcode)0;
2428
2429    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2430    assert(offset && "Non-const offsets on exports not yet supported");
2431    index += offset->u32;
2432
2433    assert(index != FRAG_RESULT_COLOR);
2434
2435    /* Unlike vertex shader exports, it's fine to use multiple exports to
2436     * export separate channels of one target. So shaders which export both
2437     * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2438     * TODO: combine the exports in those cases and create better code
2439     */
2440
2441    if (index == FRAG_RESULT_SAMPLE_MASK) {
2442
2443       if (ctx->program->info->ps.writes_z) {
2444          target = V_008DFC_SQ_EXP_MRTZ;
2445          enabled_channels = 0x4;
2446          col_format = (unsigned) -1;
2447
2448          values[2] = values[0];
2449          values[0] = Operand(v1);
2450       } else {
2451          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2452          exp->valid_mask = false;
2453          exp->done = false;
2454          exp->compressed = true;
2455          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2456          exp->enabled_mask = 0xc;
2457          for (int i = 0; i < 4; i++)
2458             exp->operands[i] = Operand(v1);
2459          exp->operands[1] = Operand(values[0]);
2460          ctx->block->instructions.emplace_back(std::move(exp));
2461          return;
2462       }
2463
2464    } else if (index == FRAG_RESULT_DEPTH) {
2465
2466       target = V_008DFC_SQ_EXP_MRTZ;
2467       enabled_channels = 0x1;
2468       col_format = (unsigned) -1;
2469
2470    } else if (index == FRAG_RESULT_STENCIL) {
2471
2472       if (ctx->program->info->ps.writes_z) {
2473          target = V_008DFC_SQ_EXP_MRTZ;
2474          enabled_channels = 0x2;
2475          col_format = (unsigned) -1;
2476
2477          values[1] = values[0];
2478          values[0] = Operand(v1);
2479       } else {
2480          aco_ptr<Instruction> shift{create_instruction<VOP2_instruction>(aco_opcode::v_lshlrev_b32, Format::VOP2, 2, 1)};
2481          shift->operands[0] = Operand((uint32_t) 16);
2482          shift->operands[1] = values[0];
2483          Temp tmp = {ctx->program->allocateId(), v1};
2484          shift->definitions[0] = Definition(tmp);
2485          ctx->block->instructions.emplace_back(std::move(shift));
2486
2487          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2488          exp->valid_mask = false;
2489          exp->done = false;
2490          exp->compressed = true;
2491          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2492          exp->enabled_mask = 0x3;
2493          exp->operands[0] = Operand(tmp);
2494          for (int i = 1; i < 4; i++)
2495             exp->operands[i] = Operand(v1);
2496          ctx->block->instructions.emplace_back(std::move(exp));
2497          return;
2498       }
2499
2500    } else {
2501       index -= FRAG_RESULT_DATA0;
2502       target = V_008DFC_SQ_EXP_MRT + index;
2503       col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2504    }
2505    ASSERTED bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2506    ASSERTED bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2507    assert(!is_int8 && !is_int10);
2508
2509    switch (col_format)
2510    {
2511    case V_028714_SPI_SHADER_ZERO:
2512       enabled_channels = 0; /* writemask */
2513       target = V_008DFC_SQ_EXP_NULL;
2514       break;
2515
2516    case V_028714_SPI_SHADER_32_R:
2517       enabled_channels = 1;
2518       break;
2519
2520    case V_028714_SPI_SHADER_32_GR:
2521       enabled_channels = 0x3;
2522       break;
2523
2524    case V_028714_SPI_SHADER_32_AR:
2525       enabled_channels = 0x9;
2526       break;
2527
2528    case V_028714_SPI_SHADER_FP16_ABGR:
2529       enabled_channels = 0x5;
2530       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
2531       break;
2532
2533    case V_028714_SPI_SHADER_UNORM16_ABGR:
2534       enabled_channels = 0x5;
2535       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
2536       break;
2537
2538    case V_028714_SPI_SHADER_SNORM16_ABGR:
2539       enabled_channels = 0x5;
2540       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
2541       break;
2542
2543    case V_028714_SPI_SHADER_UINT16_ABGR:
2544       enabled_channels = 0x5;
2545       compr_op = aco_opcode::v_cvt_pk_u16_u32;
2546       break;
2547
2548    case V_028714_SPI_SHADER_SINT16_ABGR:
2549       enabled_channels = 0x5;
2550       compr_op = aco_opcode::v_cvt_pk_i16_i32;
2551       break;
2552
2553    case V_028714_SPI_SHADER_32_ABGR:
2554       enabled_channels = 0xF;
2555       break;
2556
2557    default:
2558       break;
2559    }
2560
2561    if (target == V_008DFC_SQ_EXP_NULL)
2562       return;
2563
2564    if ((bool)compr_op)
2565    {
2566       for (int i = 0; i < 2; i++)
2567       {
2568          /* check if at least one of the values to be compressed is enabled */
2569          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
2570          if (enabled) {
2571             enabled_channels |= enabled << (i*2);
2572             aco_ptr<VOP3A_instruction> compr{create_instruction<VOP3A_instruction>(compr_op, Format::VOP3A, 2, 1)};
2573             Temp tmp{ctx->program->allocateId(), v1};
2574             compr->operands[0] = values[i*2].isUndefined() ? Operand(0u) : values[i*2];
2575             compr->operands[1] = values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1];
2576             compr->definitions[0] = Definition(tmp);
2577             values[i] = Operand(tmp);
2578             ctx->block->instructions.emplace_back(std::move(compr));
2579          } else {
2580             values[i] = Operand(v1);
2581          }
2582       }
2583    }
2584
2585    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2586    exp->valid_mask = false;
2587    exp->done = false;
2588    exp->compressed = (bool) compr_op;
2589    exp->dest = target;
2590    exp->enabled_mask = enabled_channels;
2591    if ((bool) compr_op) {
2592       for (int i = 0; i < 2; i++)
2593          exp->operands[i] = enabled_channels & (3 << (i * 2)) ? values[i] : Operand(v1);
2594       exp->operands[2] = Operand(v1);
2595       exp->operands[3] = Operand(v1);
2596    } else {
2597       for (int i = 0; i < 4; i++)
2598          exp->operands[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
2599    }
2600
2601    ctx->block->instructions.emplace_back(std::move(exp));
2602 }
2603
2604 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2605 {
2606    if (ctx->stage == vertex_vs) {
2607       visit_store_vs_output(ctx, instr);
2608    } else if (ctx->stage == fragment_fs) {
2609       visit_store_fs_output(ctx, instr);
2610    } else {
2611       unreachable("Shader stage not implemented");
2612    }
2613 }
2614
2615 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
2616 {
2617    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
2618    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
2619
2620    Builder bld(ctx->program, ctx->block);
2621    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
2622    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
2623 }
2624
2625 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
2626 {
2627    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
2628    for (unsigned i = 0; i < num_components; i++)
2629       vec->operands[i] = Operand(ctx->fs_inputs[fs_input::frag_pos_0 + i]);
2630
2631    if (ctx->fs_vgpr_args[fs_input::frag_pos_3]) {
2632       assert(num_components == 4);
2633       Builder bld(ctx->program, ctx->block);
2634       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ctx->fs_inputs[fs_input::frag_pos_3]);
2635    }
2636
2637    for (Operand& op : vec->operands)
2638       op = op.isUndefined() ? Operand(0u) : op;
2639
2640    vec->definitions[0] = Definition(dst);
2641    ctx->block->instructions.emplace_back(std::move(vec));
2642    emit_split_vector(ctx, dst, num_components);
2643    return;
2644 }
2645
2646 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
2647 {
2648    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2649    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
2650    unsigned idx = nir_intrinsic_base(instr);
2651    unsigned component = nir_intrinsic_component(instr);
2652    Temp prim_mask = ctx->prim_mask;
2653
2654    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2655    if (offset) {
2656       assert(offset->u32 == 0);
2657    } else {
2658       /* the lower 15bit of the prim_mask contain the offset into LDS
2659        * while the upper bits contain the number of prims */
2660       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
2661       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
2662       Builder bld(ctx->program, ctx->block);
2663       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
2664       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
2665       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
2666       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
2667       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
2668    }
2669
2670    if (instr->dest.ssa.num_components == 1) {
2671       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
2672    } else {
2673       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
2674       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
2675       {
2676          Temp tmp = {ctx->program->allocateId(), v1};
2677          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
2678          vec->operands[i] = Operand(tmp);
2679       }
2680       vec->definitions[0] = Definition(dst);
2681       ctx->block->instructions.emplace_back(std::move(vec));
2682    }
2683 }
2684
2685 unsigned get_num_channels_from_data_format(unsigned data_format)
2686 {
2687    switch (data_format) {
2688    case V_008F0C_BUF_DATA_FORMAT_8:
2689    case V_008F0C_BUF_DATA_FORMAT_16:
2690    case V_008F0C_BUF_DATA_FORMAT_32:
2691       return 1;
2692    case V_008F0C_BUF_DATA_FORMAT_8_8:
2693    case V_008F0C_BUF_DATA_FORMAT_16_16:
2694    case V_008F0C_BUF_DATA_FORMAT_32_32:
2695       return 2;
2696    case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2697    case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2698    case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2699       return 3;
2700    case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2701    case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2702    case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2703    case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2704    case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2705       return 4;
2706    default:
2707       break;
2708    }
2709
2710    return 4;
2711 }
2712
2713 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2714  * so we may need to fix it up. */
2715 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
2716 {
2717    Builder bld(ctx->program, ctx->block);
2718
2719    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
2720       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
2721
2722    /* For the integer-like cases, do a natural sign extension.
2723     *
2724     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2725     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2726     * exponent.
2727     */
2728    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
2729    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
2730
2731    /* Convert back to the right type. */
2732    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
2733       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
2734       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0xbf800000u), alpha);
2735       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
2736    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2737       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
2738    }
2739
2740    return alpha;
2741 }
2742
2743 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
2744 {
2745    Builder bld(ctx->program, ctx->block);
2746    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2747    if (ctx->stage & sw_vs) {
2748
2749       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
2750       if (off_instr->type != nir_instr_type_load_const) {
2751          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2752          nir_print_instr(off_instr, stderr);
2753          fprintf(stderr, "\n");
2754       }
2755       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
2756
2757       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, ctx->vertex_buffers);
2758
2759       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
2760       unsigned component = nir_intrinsic_component(instr);
2761       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
2762       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
2763       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
2764       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
2765
2766       unsigned dfmt = attrib_format & 0xf;
2767
2768       unsigned nfmt = (attrib_format >> 4) & 0x7;
2769       unsigned num_dfmt_channels = get_num_channels_from_data_format(dfmt);
2770       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
2771       unsigned num_channels = MIN2(util_last_bit(mask), num_dfmt_channels);
2772       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
2773       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
2774       if (post_shuffle)
2775          num_channels = MAX2(num_channels, 3);
2776
2777       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, Operand(attrib_binding * 16u));
2778
2779       Temp index;
2780       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
2781          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
2782          if (divisor) {
2783             ctx->needs_instance_id = true;
2784
2785             if (divisor != 1) {
2786                Temp divided = bld.tmp(v1);
2787                emit_v_div_u32(ctx, divided, as_vgpr(ctx, ctx->instance_id), divisor);
2788                index = bld.vadd32(bld.def(v1), ctx->start_instance, divided);
2789             } else {
2790                index = bld.vadd32(bld.def(v1), ctx->start_instance, ctx->instance_id);
2791             }
2792          } else {
2793             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), ctx->start_instance);
2794          }
2795       } else {
2796          index = bld.vadd32(bld.def(v1), ctx->base_vertex, ctx->vertex_id);
2797       }
2798
2799       if (attrib_stride != 0 && attrib_offset > attrib_stride) {
2800          index = bld.vadd32(bld.def(v1), Operand(attrib_offset / attrib_stride), index);
2801          attrib_offset = attrib_offset % attrib_stride;
2802       }
2803
2804       Operand soffset(0u);
2805       if (attrib_offset >= 4096) {
2806          soffset = bld.copy(bld.def(s1), Operand(attrib_offset));
2807          attrib_offset = 0;
2808       }
2809
2810       aco_opcode opcode;
2811       switch (num_channels) {
2812       case 1:
2813          opcode = aco_opcode::tbuffer_load_format_x;
2814          break;
2815       case 2:
2816          opcode = aco_opcode::tbuffer_load_format_xy;
2817          break;
2818       case 3:
2819          opcode = aco_opcode::tbuffer_load_format_xyz;
2820          break;
2821       case 4:
2822          opcode = aco_opcode::tbuffer_load_format_xyzw;
2823          break;
2824       default:
2825          unreachable("Unimplemented load_input vector size");
2826       }
2827
2828       Temp tmp = post_shuffle || num_channels != dst.size() || alpha_adjust != RADV_ALPHA_ADJUST_NONE || component ? bld.tmp(RegType::vgpr, num_channels) : dst;
2829
2830       aco_ptr<MTBUF_instruction> mubuf{create_instruction<MTBUF_instruction>(opcode, Format::MTBUF, 3, 1)};
2831       mubuf->operands[0] = Operand(index);
2832       mubuf->operands[1] = Operand(list);
2833       mubuf->operands[2] = soffset;
2834       mubuf->definitions[0] = Definition(tmp);
2835       mubuf->idxen = true;
2836       mubuf->can_reorder = true;
2837       mubuf->dfmt = dfmt;
2838       mubuf->nfmt = nfmt;
2839       assert(attrib_offset < 4096);
2840       mubuf->offset = attrib_offset;
2841       ctx->block->instructions.emplace_back(std::move(mubuf));
2842
2843       emit_split_vector(ctx, tmp, tmp.size());
2844
2845       if (tmp.id() != dst.id()) {
2846          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
2847                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
2848
2849          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
2850          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
2851          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
2852
2853          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2854          for (unsigned i = 0; i < dst.size(); i++) {
2855             unsigned idx = i + component;
2856             if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE && num_channels >= 4) {
2857                Temp alpha = emit_extract_vector(ctx, tmp, swizzle[3], v1);
2858                vec->operands[3] = Operand(adjust_vertex_fetch_alpha(ctx, alpha_adjust, alpha));
2859             } else if (idx < num_channels) {
2860                vec->operands[i] = Operand(emit_extract_vector(ctx, tmp, swizzle[idx], v1));
2861             } else if (is_float && idx == 3) {
2862                vec->operands[i] = Operand(0x3f800000u);
2863             } else if (!is_float && idx == 3) {
2864                vec->operands[i] = Operand(1u);
2865             } else {
2866                vec->operands[i] = Operand(0u);
2867             }
2868          }
2869          vec->definitions[0] = Definition(dst);
2870          ctx->block->instructions.emplace_back(std::move(vec));
2871          emit_split_vector(ctx, dst, dst.size());
2872       }
2873
2874    } else if (ctx->stage == fragment_fs) {
2875       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
2876       if (off_instr->type != nir_instr_type_load_const ||
2877           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
2878          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2879          nir_print_instr(off_instr, stderr);
2880          fprintf(stderr, "\n");
2881       }
2882
2883       Temp prim_mask = ctx->prim_mask;
2884       nir_const_value* offset = nir_src_as_const_value(instr->src[0]);
2885       if (offset) {
2886          assert(offset->u32 == 0);
2887       } else {
2888          /* the lower 15bit of the prim_mask contain the offset into LDS
2889           * while the upper bits contain the number of prims */
2890          Temp offset_src = get_ssa_temp(ctx, instr->src[0].ssa);
2891          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
2892          Builder bld(ctx->program, ctx->block);
2893          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
2894          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
2895          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
2896          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
2897          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
2898       }
2899
2900       unsigned idx = nir_intrinsic_base(instr);
2901       unsigned component = nir_intrinsic_component(instr);
2902
2903       if (dst.size() == 1) {
2904          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(2u), bld.m0(prim_mask), idx, component);
2905       } else {
2906          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2907          for (unsigned i = 0; i < dst.size(); i++)
2908             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(2u), bld.m0(prim_mask), idx, component + i);
2909          vec->definitions[0] = Definition(dst);
2910          bld.insert(std::move(vec));
2911       }
2912
2913    } else {
2914       unreachable("Shader stage not implemented");
2915    }
2916 }
2917
2918 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
2919 {
2920    if (ctx->program->info->need_indirect_descriptor_sets) {
2921       Builder bld(ctx->program, ctx->block);
2922       Temp ptr64 = convert_pointer_to_64_bit(ctx, ctx->descriptor_sets[0]);
2923       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, Operand(desc_set << 2));//, false, false, false);
2924    }
2925
2926    return ctx->descriptor_sets[desc_set];
2927 }
2928
2929
2930 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
2931 {
2932    Builder bld(ctx->program, ctx->block);
2933    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
2934    unsigned desc_set = nir_intrinsic_desc_set(instr);
2935    unsigned binding = nir_intrinsic_binding(instr);
2936
2937    Temp desc_ptr;
2938    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2939    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2940    unsigned offset = layout->binding[binding].offset;
2941    unsigned stride;
2942    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2943        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2944       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
2945       desc_ptr = ctx->push_constants;
2946       offset = pipeline_layout->push_constant_size + 16 * idx;
2947       stride = 16;
2948    } else {
2949       desc_ptr = load_desc_ptr(ctx, desc_set);
2950       stride = layout->binding[binding].size;
2951    }
2952
2953    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
2954    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
2955    if (stride != 1) {
2956       if (nir_const_index) {
2957          const_index = const_index * stride;
2958       } else {
2959          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
2960       }
2961    }
2962    if (offset) {
2963       if (nir_const_index) {
2964          const_index = const_index + offset;
2965       } else {
2966          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
2967       }
2968    }
2969
2970    if (nir_const_index && const_index == 0) {
2971       index = desc_ptr;
2972    } else {
2973       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
2974                        nir_const_index ? Operand(const_index) : Operand(index),
2975                        Operand(desc_ptr));
2976    }
2977
2978    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2979    bld.sop1(aco_opcode::s_mov_b32, Definition(dst), index);
2980 }
2981
2982 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst, Temp rsrc, Temp offset, bool glc=false)
2983 {
2984    Builder bld(ctx->program, ctx->block);
2985
2986    unsigned num_bytes = dst.size() * 4;
2987    bool dlc = glc && ctx->options->chip_class >= GFX10;
2988
2989    aco_opcode op;
2990    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
2991       if (ctx->options->chip_class < GFX8)
2992          offset = as_vgpr(ctx, offset);
2993
2994       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
2995       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
2996       unsigned const_offset = 0;
2997
2998       Temp lower = Temp();
2999       if (num_bytes > 16) {
3000          assert(num_components == 3 || num_components == 4);
3001          op = aco_opcode::buffer_load_dwordx4;
3002          lower = bld.tmp(v4);
3003          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3004          mubuf->definitions[0] = Definition(lower);
3005          mubuf->operands[0] = vaddr;
3006          mubuf->operands[1] = Operand(rsrc);
3007          mubuf->operands[2] = soffset;
3008          mubuf->offen = (offset.type() == RegType::vgpr);
3009          mubuf->glc = glc;
3010          mubuf->dlc = dlc;
3011          mubuf->barrier = barrier_buffer;
3012          bld.insert(std::move(mubuf));
3013          emit_split_vector(ctx, lower, 2);
3014          num_bytes -= 16;
3015          const_offset = 16;
3016       }
3017
3018       switch (num_bytes) {
3019          case 4:
3020             op = aco_opcode::buffer_load_dword;
3021             break;
3022          case 8:
3023             op = aco_opcode::buffer_load_dwordx2;
3024             break;
3025          case 12:
3026             op = aco_opcode::buffer_load_dwordx3;
3027             break;
3028          case 16:
3029             op = aco_opcode::buffer_load_dwordx4;
3030             break;
3031          default:
3032             unreachable("Load SSBO not implemented for this size.");
3033       }
3034       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3035       mubuf->operands[0] = vaddr;
3036       mubuf->operands[1] = Operand(rsrc);
3037       mubuf->operands[2] = soffset;
3038       mubuf->offen = (offset.type() == RegType::vgpr);
3039       mubuf->glc = glc;
3040       mubuf->dlc = dlc;
3041       mubuf->barrier = barrier_buffer;
3042       mubuf->offset = const_offset;
3043       aco_ptr<Instruction> instr = std::move(mubuf);
3044
3045       if (dst.size() > 4) {
3046          assert(lower != Temp());
3047          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3048          instr->definitions[0] = Definition(upper);
3049          bld.insert(std::move(instr));
3050          if (dst.size() == 8)
3051             emit_split_vector(ctx, upper, 2);
3052          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3053          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3054          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3055          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3056          if (dst.size() == 8)
3057             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3058       }
3059
3060       if (dst.type() == RegType::sgpr) {
3061          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3062          instr->definitions[0] = Definition(vec);
3063          bld.insert(std::move(instr));
3064          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
3065       } else {
3066          instr->definitions[0] = Definition(dst);
3067          bld.insert(std::move(instr));
3068       }
3069    } else {
3070       switch (num_bytes) {
3071          case 4:
3072             op = aco_opcode::s_buffer_load_dword;
3073             break;
3074          case 8:
3075             op = aco_opcode::s_buffer_load_dwordx2;
3076             break;
3077          case 12:
3078          case 16:
3079             op = aco_opcode::s_buffer_load_dwordx4;
3080             break;
3081          case 24:
3082          case 32:
3083             op = aco_opcode::s_buffer_load_dwordx8;
3084             break;
3085          default:
3086             unreachable("Load SSBO not implemented for this size.");
3087       }
3088       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3089       load->operands[0] = Operand(rsrc);
3090       load->operands[1] = Operand(bld.as_uniform(offset));
3091       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3092       load->definitions[0] = Definition(dst);
3093       load->glc = glc;
3094       load->dlc = dlc;
3095       load->barrier = barrier_buffer;
3096       assert(ctx->options->chip_class >= GFX8 || !glc);
3097
3098       /* trim vector */
3099       if (dst.size() == 3) {
3100          Temp vec = bld.tmp(s4);
3101          load->definitions[0] = Definition(vec);
3102          bld.insert(std::move(load));
3103          emit_split_vector(ctx, vec, 4);
3104
3105          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3106                     emit_extract_vector(ctx, vec, 0, s1),
3107                     emit_extract_vector(ctx, vec, 1, s1),
3108                     emit_extract_vector(ctx, vec, 2, s1));
3109       } else if (dst.size() == 6) {
3110          Temp vec = bld.tmp(s8);
3111          load->definitions[0] = Definition(vec);
3112          bld.insert(std::move(load));
3113          emit_split_vector(ctx, vec, 4);
3114
3115          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3116                     emit_extract_vector(ctx, vec, 0, s2),
3117                     emit_extract_vector(ctx, vec, 1, s2),
3118                     emit_extract_vector(ctx, vec, 2, s2));
3119       } else {
3120          bld.insert(std::move(load));
3121       }
3122
3123    }
3124    emit_split_vector(ctx, dst, num_components);
3125 }
3126
3127 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3128 {
3129    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3130    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3131
3132    Builder bld(ctx->program, ctx->block);
3133
3134    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3135    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3136    unsigned binding = nir_intrinsic_binding(idx_instr);
3137    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3138
3139    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3140       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3141                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3142                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3143                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3144                            S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3145                            S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3146       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3147                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3148                                      Operand(0xFFFFFFFFu),
3149                                      Operand(desc_type));
3150       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3151                         rsrc, upper_dwords);
3152    } else {
3153       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3154       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3155    }
3156
3157    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3158 }
3159
3160 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3161 {
3162    Builder bld(ctx->program, ctx->block);
3163    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3164
3165    unsigned offset = nir_intrinsic_base(instr);
3166    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3167    if (index_cv && instr->dest.ssa.bit_size == 32) {
3168
3169       unsigned count = instr->dest.ssa.num_components;
3170       unsigned start = (offset + index_cv->u32) / 4u;
3171       start -= ctx->base_inline_push_consts;
3172       if (start + count <= ctx->num_inline_push_consts) {
3173          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3174          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3175          for (unsigned i = 0; i < count; ++i) {
3176             elems[i] = ctx->inline_push_consts[start + i];
3177             vec->operands[i] = Operand{elems[i]};
3178          }
3179          vec->definitions[0] = Definition(dst);
3180          ctx->block->instructions.emplace_back(std::move(vec));
3181          ctx->allocated_vec.emplace(dst.id(), elems);
3182          return;
3183       }
3184    }
3185
3186    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3187    if (offset != 0) // TODO check if index != 0 as well
3188       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3189    Temp ptr = convert_pointer_to_64_bit(ctx, ctx->push_constants);
3190    Temp vec = dst;
3191    bool trim = false;
3192    aco_opcode op;
3193
3194    switch (dst.size()) {
3195    case 1:
3196       op = aco_opcode::s_load_dword;
3197       break;
3198    case 2:
3199       op = aco_opcode::s_load_dwordx2;
3200       break;
3201    case 3:
3202       vec = bld.tmp(s4);
3203       trim = true;
3204    case 4:
3205       op = aco_opcode::s_load_dwordx4;
3206       break;
3207    case 6:
3208       vec = bld.tmp(s8);
3209       trim = true;
3210    case 8:
3211       op = aco_opcode::s_load_dwordx8;
3212       break;
3213    default:
3214       unreachable("unimplemented or forbidden load_push_constant.");
3215    }
3216
3217    bld.smem(op, Definition(vec), ptr, index);
3218
3219    if (trim) {
3220       emit_split_vector(ctx, vec, 4);
3221       RegClass rc = dst.size() == 3 ? s1 : s2;
3222       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3223                  emit_extract_vector(ctx, vec, 0, rc),
3224                  emit_extract_vector(ctx, vec, 1, rc),
3225                  emit_extract_vector(ctx, vec, 2, rc));
3226
3227    }
3228    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3229 }
3230
3231 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3232 {
3233    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3234
3235    Builder bld(ctx->program, ctx->block);
3236
3237    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3238                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3239                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3240                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3241    if (ctx->options->chip_class >= GFX10) {
3242       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3243                    S_008F0C_OOB_SELECT(3) |
3244                    S_008F0C_RESOURCE_LEVEL(1);
3245    } else {
3246       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3247                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3248    }
3249
3250    unsigned base = nir_intrinsic_base(instr);
3251    unsigned range = nir_intrinsic_range(instr);
3252
3253    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3254    if (base && offset.type() == RegType::sgpr)
3255       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3256    else if (base && offset.type() == RegType::vgpr)
3257       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3258
3259    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3260                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3261                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3262                           Operand(desc_type));
3263
3264    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3265 }
3266
3267 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3268 {
3269    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3270       ctx->cf_info.exec_potentially_empty = true;
3271
3272    ctx->program->needs_exact = true;
3273
3274    // TODO: optimize uniform conditions
3275    Builder bld(ctx->program, ctx->block);
3276    Temp src = as_divergent_bool(ctx, get_ssa_temp(ctx, instr->src[0].ssa), false);
3277    src = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
3278    bld.pseudo(aco_opcode::p_discard_if, src);
3279    ctx->block->kind |= block_kind_uses_discard_if;
3280    return;
3281 }
3282
3283 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3284 {
3285    Builder bld(ctx->program, ctx->block);
3286
3287    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3288       ctx->cf_info.exec_potentially_empty = true;
3289
3290    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3291                     ctx->cf_info.parent_loop.has_divergent_continue;
3292
3293    if (ctx->block->loop_nest_depth &&
3294        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3295       /* we handle discards the same way as jump instructions */
3296       append_logical_end(ctx->block);
3297
3298       /* in loops, discard behaves like break */
3299       Block *linear_target = ctx->cf_info.parent_loop.exit;
3300       ctx->block->kind |= block_kind_discard;
3301
3302       if (!divergent) {
3303          /* uniform discard - loop ends here */
3304          assert(nir_instr_is_last(&instr->instr));
3305          ctx->block->kind |= block_kind_uniform;
3306          ctx->cf_info.has_branch = true;
3307          bld.branch(aco_opcode::p_branch);
3308          add_linear_edge(ctx->block->index, linear_target);
3309          return;
3310       }
3311
3312       /* we add a break right behind the discard() instructions */
3313       ctx->block->kind |= block_kind_break;
3314       unsigned idx = ctx->block->index;
3315
3316       /* remove critical edges from linear CFG */
3317       bld.branch(aco_opcode::p_branch);
3318       Block* break_block = ctx->program->create_and_insert_block();
3319       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3320       break_block->kind |= block_kind_uniform;
3321       add_linear_edge(idx, break_block);
3322       add_linear_edge(break_block->index, linear_target);
3323       bld.reset(break_block);
3324       bld.branch(aco_opcode::p_branch);
3325
3326       Block* continue_block = ctx->program->create_and_insert_block();
3327       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3328       add_linear_edge(idx, continue_block);
3329       append_logical_start(continue_block);
3330       ctx->block = continue_block;
3331
3332       return;
3333    }
3334
3335    /* it can currently happen that NIR doesn't remove the unreachable code */
3336    if (!nir_instr_is_last(&instr->instr)) {
3337       ctx->program->needs_exact = true;
3338       /* save exec somewhere temporarily so that it doesn't get
3339        * overwritten before the discard from outer exec masks */
3340       Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, s2));
3341       bld.pseudo(aco_opcode::p_discard_if, cond);
3342       ctx->block->kind |= block_kind_uses_discard_if;
3343       return;
3344    }
3345
3346    /* This condition is incorrect for uniformly branched discards in a loop
3347     * predicated by a divergent condition, but the above code catches that case
3348     * and the discard would end up turning into a discard_if.
3349     * For example:
3350     * if (divergent) {
3351     *    while (...) {
3352     *       if (uniform) {
3353     *          discard;
3354     *       }
3355     *    }
3356     * }
3357     */
3358    if (!ctx->cf_info.parent_if.is_divergent) {
3359       /* program just ends here */
3360       ctx->block->kind |= block_kind_uniform;
3361       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
3362               0 /* enabled mask */, 9 /* dest */,
3363               false /* compressed */, true/* done */, true /* valid mask */);
3364       bld.sopp(aco_opcode::s_endpgm);
3365       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3366    } else {
3367       ctx->block->kind |= block_kind_discard;
3368       /* branch and linear edge is added by visit_if() */
3369    }
3370 }
3371
3372 enum aco_descriptor_type {
3373    ACO_DESC_IMAGE,
3374    ACO_DESC_FMASK,
3375    ACO_DESC_SAMPLER,
3376    ACO_DESC_BUFFER,
3377    ACO_DESC_PLANE_0,
3378    ACO_DESC_PLANE_1,
3379    ACO_DESC_PLANE_2,
3380 };
3381
3382 static bool
3383 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
3384    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
3385       return false;
3386    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
3387    return dim == ac_image_cube ||
3388           dim == ac_image_1darray ||
3389           dim == ac_image_2darray ||
3390           dim == ac_image_2darraymsaa;
3391 }
3392
3393 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
3394                       enum aco_descriptor_type desc_type,
3395                       const nir_tex_instr *tex_instr, bool image, bool write)
3396 {
3397 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3398    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3399    if (it != ctx->tex_desc.end())
3400       return it->second;
3401 */
3402    Temp index = Temp();
3403    bool index_set = false;
3404    unsigned constant_index = 0;
3405    unsigned descriptor_set;
3406    unsigned base_index;
3407    Builder bld(ctx->program, ctx->block);
3408
3409    if (!deref_instr) {
3410       assert(tex_instr && !image);
3411       descriptor_set = 0;
3412       base_index = tex_instr->sampler_index;
3413    } else {
3414       while(deref_instr->deref_type != nir_deref_type_var) {
3415          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
3416          if (!array_size)
3417             array_size = 1;
3418
3419          assert(deref_instr->deref_type == nir_deref_type_array);
3420          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
3421          if (const_value) {
3422             constant_index += array_size * const_value->u32;
3423          } else {
3424             Temp indirect = bld.as_uniform(get_ssa_temp(ctx, deref_instr->arr.index.ssa));
3425
3426             if (array_size != 1)
3427                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
3428
3429             if (!index_set) {
3430                index = indirect;
3431                index_set = true;
3432             } else {
3433                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
3434             }
3435          }
3436
3437          deref_instr = nir_src_as_deref(deref_instr->parent);
3438       }
3439       descriptor_set = deref_instr->var->data.descriptor_set;
3440       base_index = deref_instr->var->data.binding;
3441    }
3442
3443    Temp list = load_desc_ptr(ctx, descriptor_set);
3444    list = convert_pointer_to_64_bit(ctx, list);
3445
3446    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
3447    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
3448    unsigned offset = binding->offset;
3449    unsigned stride = binding->size;
3450    aco_opcode opcode;
3451    RegClass type;
3452
3453    assert(base_index < layout->binding_count);
3454
3455    switch (desc_type) {
3456    case ACO_DESC_IMAGE:
3457       type = s8;
3458       opcode = aco_opcode::s_load_dwordx8;
3459       break;
3460    case ACO_DESC_FMASK:
3461       type = s8;
3462       opcode = aco_opcode::s_load_dwordx8;
3463       offset += 32;
3464       break;
3465    case ACO_DESC_SAMPLER:
3466       type = s4;
3467       opcode = aco_opcode::s_load_dwordx4;
3468       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3469          offset += radv_combined_image_descriptor_sampler_offset(binding);
3470       break;
3471    case ACO_DESC_BUFFER:
3472       type = s4;
3473       opcode = aco_opcode::s_load_dwordx4;
3474       break;
3475    case ACO_DESC_PLANE_0:
3476    case ACO_DESC_PLANE_1:
3477       type = s8;
3478       opcode = aco_opcode::s_load_dwordx8;
3479       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
3480       break;
3481    case ACO_DESC_PLANE_2:
3482       type = s4;
3483       opcode = aco_opcode::s_load_dwordx4;
3484       offset += 64;
3485       break;
3486    default:
3487       unreachable("invalid desc_type\n");
3488    }
3489
3490    offset += constant_index * stride;
3491
3492    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
3493       (!index_set || binding->immutable_samplers_equal)) {
3494       if (binding->immutable_samplers_equal)
3495          constant_index = 0;
3496
3497       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3498       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3499                         Operand(samplers[constant_index * 4 + 0]),
3500                         Operand(samplers[constant_index * 4 + 1]),
3501                         Operand(samplers[constant_index * 4 + 2]),
3502                         Operand(samplers[constant_index * 4 + 3]));
3503    }
3504
3505    Operand off;
3506    if (!index_set) {
3507       off = Operand(offset);
3508    } else {
3509       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
3510                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
3511    }
3512
3513    Temp res = bld.smem(opcode, bld.def(type), list, off);
3514
3515    if (desc_type == ACO_DESC_PLANE_2) {
3516       Temp components[8];
3517       for (unsigned i = 0; i < 8; i++)
3518          components[i] = bld.tmp(s1);
3519       bld.pseudo(aco_opcode::p_split_vector,
3520                  Definition(components[0]),
3521                  Definition(components[1]),
3522                  Definition(components[2]),
3523                  Definition(components[3]),
3524                  res);
3525
3526       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
3527       bld.pseudo(aco_opcode::p_split_vector,
3528                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
3529                  Definition(components[4]),
3530                  Definition(components[5]),
3531                  Definition(components[6]),
3532                  Definition(components[7]),
3533                  desc2);
3534
3535       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
3536                        components[0], components[1], components[2], components[3],
3537                        components[4], components[5], components[6], components[7]);
3538    }
3539
3540    return res;
3541 }
3542
3543 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3544 {
3545    switch (dim) {
3546    case GLSL_SAMPLER_DIM_BUF:
3547       return 1;
3548    case GLSL_SAMPLER_DIM_1D:
3549       return array ? 2 : 1;
3550    case GLSL_SAMPLER_DIM_2D:
3551       return array ? 3 : 2;
3552    case GLSL_SAMPLER_DIM_MS:
3553       return array ? 4 : 3;
3554    case GLSL_SAMPLER_DIM_3D:
3555    case GLSL_SAMPLER_DIM_CUBE:
3556       return 3;
3557    case GLSL_SAMPLER_DIM_RECT:
3558    case GLSL_SAMPLER_DIM_SUBPASS:
3559       return 2;
3560    case GLSL_SAMPLER_DIM_SUBPASS_MS:
3561       return 3;
3562    default:
3563       break;
3564    }
3565    return 0;
3566 }
3567
3568
3569 /* Adjust the sample index according to FMASK.
3570  *
3571  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3572  * which is the identity mapping. Each nibble says which physical sample
3573  * should be fetched to get that sample.
3574  *
3575  * For example, 0x11111100 means there are only 2 samples stored and
3576  * the second sample covers 3/4 of the pixel. When reading samples 0
3577  * and 1, return physical sample 0 (determined by the first two 0s
3578  * in FMASK), otherwise return physical sample 1.
3579  *
3580  * The sample index should be adjusted as follows:
3581  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
3582  */
3583 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, Temp coords, Operand sample_index, Temp fmask_desc_ptr)
3584 {
3585    Builder bld(ctx->program, ctx->block);
3586    Temp fmask = bld.tmp(v1);
3587    unsigned dim = ctx->options->chip_class >= GFX10
3588                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
3589                   : 0;
3590
3591    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3592    load->operands[0] = Operand(coords);
3593    load->operands[1] = Operand(fmask_desc_ptr);
3594    load->definitions[0] = Definition(fmask);
3595    load->glc = false;
3596    load->dlc = false;
3597    load->dmask = 0x1;
3598    load->unrm = true;
3599    load->da = da;
3600    load->dim = dim;
3601    load->can_reorder = true; /* fmask images shouldn't be modified */
3602    ctx->block->instructions.emplace_back(std::move(load));
3603
3604    Operand sample_index4;
3605    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
3606       sample_index4 = Operand(sample_index.constantValue() << 2);
3607    } else if (sample_index.regClass() == s1) {
3608       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
3609    } else {
3610       assert(sample_index.regClass() == v1);
3611       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
3612    }
3613
3614    Temp final_sample;
3615    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
3616       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
3617    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
3618       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
3619    else
3620       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
3621
3622    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3623     * resource descriptor is 0 (invalid),
3624     */
3625    Temp compare = bld.tmp(s2);
3626    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
3627                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
3628
3629    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
3630
3631    /* Replace the MSAA sample index. */
3632    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
3633 }
3634
3635 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
3636 {
3637
3638    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
3639    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3640    bool is_array = glsl_sampler_type_is_array(type);
3641    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3642    assert(!add_frag_pos && "Input attachments should be lowered.");
3643    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3644    bool gfx9_1d = ctx->options->chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3645    int count = image_type_to_components_count(dim, is_array);
3646    std::vector<Operand> coords(count);
3647
3648    if (is_ms) {
3649       Operand sample_index;
3650       nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
3651       if (sample_cv)
3652          sample_index = Operand(sample_cv->u32);
3653       else
3654          sample_index = Operand(emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[2].ssa), 0, v1));
3655
3656       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
3657          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, is_array ? 3 : 2, 1)};
3658          for (unsigned i = 0; i < vec->operands.size(); i++)
3659             vec->operands[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
3660          Temp fmask_load_address = {ctx->program->allocateId(), is_array ? v3 : v2};
3661          vec->definitions[0] = Definition(fmask_load_address);
3662          ctx->block->instructions.emplace_back(std::move(vec));
3663
3664          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
3665          sample_index = Operand(adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr));
3666       }
3667       count--;
3668       coords[count] = sample_index;
3669    }
3670
3671    if (count == 1 && !gfx9_1d)
3672       return emit_extract_vector(ctx, src0, 0, v1);
3673
3674    if (gfx9_1d) {
3675       coords[0] = Operand(emit_extract_vector(ctx, src0, 0, v1));
3676       coords.resize(coords.size() + 1);
3677       coords[1] = Operand((uint32_t) 0);
3678       if (is_array)
3679          coords[2] = Operand(emit_extract_vector(ctx, src0, 1, v1));
3680    } else {
3681       for (int i = 0; i < count; i++)
3682          coords[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
3683    }
3684
3685    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
3686    for (unsigned i = 0; i < coords.size(); i++)
3687       vec->operands[i] = coords[i];
3688    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
3689    vec->definitions[0] = Definition(res);
3690    ctx->block->instructions.emplace_back(std::move(vec));
3691    return res;
3692 }
3693
3694
3695 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
3696 {
3697    Builder bld(ctx->program, ctx->block);
3698    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
3699    const struct glsl_type *type = glsl_without_array(var->type);
3700    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3701    bool is_array = glsl_sampler_type_is_array(type);
3702    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3703
3704    if (dim == GLSL_SAMPLER_DIM_BUF) {
3705       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3706       unsigned num_channels = util_last_bit(mask);
3707       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
3708       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
3709
3710       aco_opcode opcode;
3711       switch (num_channels) {
3712       case 1:
3713          opcode = aco_opcode::buffer_load_format_x;
3714          break;
3715       case 2:
3716          opcode = aco_opcode::buffer_load_format_xy;
3717          break;
3718       case 3:
3719          opcode = aco_opcode::buffer_load_format_xyz;
3720          break;
3721       case 4:
3722          opcode = aco_opcode::buffer_load_format_xyzw;
3723          break;
3724       default:
3725          unreachable(">4 channel buffer image load");
3726       }
3727       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
3728       load->operands[0] = Operand(vindex);
3729       load->operands[1] = Operand(rsrc);
3730       load->operands[2] = Operand((uint32_t) 0);
3731       Temp tmp;
3732       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
3733          tmp = dst;
3734       else
3735          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
3736       load->definitions[0] = Definition(tmp);
3737       load->idxen = true;
3738       load->barrier = barrier_image;
3739       ctx->block->instructions.emplace_back(std::move(load));
3740
3741       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
3742       return;
3743    }
3744
3745    Temp coords = get_image_coords(ctx, instr, type);
3746    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
3747
3748    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
3749    unsigned num_components = util_bitcount(dmask);
3750    Temp tmp;
3751    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
3752       tmp = dst;
3753    else
3754       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
3755
3756    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3757    load->operands[0] = Operand(coords);
3758    load->operands[1] = Operand(resource);
3759    load->definitions[0] = Definition(tmp);
3760    load->glc = var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
3761    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
3762    load->dmask = dmask;
3763    load->unrm = true;
3764    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
3765    load->barrier = barrier_image;
3766    ctx->block->instructions.emplace_back(std::move(load));
3767
3768    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
3769    return;
3770 }
3771
3772 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
3773 {
3774    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
3775    const struct glsl_type *type = glsl_without_array(var->type);
3776    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3777    bool is_array = glsl_sampler_type_is_array(type);
3778    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
3779
3780    bool glc = ctx->options->chip_class == GFX6 || var->data.image.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
3781
3782    if (dim == GLSL_SAMPLER_DIM_BUF) {
3783       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
3784       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
3785       aco_opcode opcode;
3786       switch (data.size()) {
3787       case 1:
3788          opcode = aco_opcode::buffer_store_format_x;
3789          break;
3790       case 2:
3791          opcode = aco_opcode::buffer_store_format_xy;
3792          break;
3793       case 3:
3794          opcode = aco_opcode::buffer_store_format_xyz;
3795          break;
3796       case 4:
3797          opcode = aco_opcode::buffer_store_format_xyzw;
3798          break;
3799       default:
3800          unreachable(">4 channel buffer image store");
3801       }
3802       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
3803       store->operands[0] = Operand(vindex);
3804       store->operands[1] = Operand(rsrc);
3805       store->operands[2] = Operand((uint32_t) 0);
3806       store->operands[3] = Operand(data);
3807       store->idxen = true;
3808       store->glc = glc;
3809       store->dlc = false;
3810       store->disable_wqm = true;
3811       store->barrier = barrier_image;
3812       ctx->program->needs_exact = true;
3813       ctx->block->instructions.emplace_back(std::move(store));
3814       return;
3815    }
3816
3817    assert(data.type() == RegType::vgpr);
3818    Temp coords = get_image_coords(ctx, instr, type);
3819    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
3820
3821    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(aco_opcode::image_store, Format::MIMG, 4, 0)};
3822    store->operands[0] = Operand(coords);
3823    store->operands[1] = Operand(resource);
3824    store->operands[2] = Operand(s4);
3825    store->operands[3] = Operand(data);
3826    store->glc = glc;
3827    store->dlc = false;
3828    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
3829    store->dmask = (1 << data.size()) - 1;
3830    store->unrm = true;
3831    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
3832    store->disable_wqm = true;
3833    store->barrier = barrier_image;
3834    ctx->program->needs_exact = true;
3835    ctx->block->instructions.emplace_back(std::move(store));
3836    return;
3837 }
3838
3839 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
3840 {
3841    /* return the previous value if dest is ever used */
3842    bool return_previous = false;
3843    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
3844       return_previous = true;
3845       break;
3846    }
3847    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
3848       return_previous = true;
3849       break;
3850    }
3851
3852    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
3853    const struct glsl_type *type = glsl_without_array(var->type);
3854    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3855    bool is_array = glsl_sampler_type_is_array(type);
3856    Builder bld(ctx->program, ctx->block);
3857
3858    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
3859    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
3860
3861    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
3862       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
3863
3864    aco_opcode buf_op, image_op;
3865    switch (instr->intrinsic) {
3866       case nir_intrinsic_image_deref_atomic_add:
3867          buf_op = aco_opcode::buffer_atomic_add;
3868          image_op = aco_opcode::image_atomic_add;
3869          break;
3870       case nir_intrinsic_image_deref_atomic_umin:
3871          buf_op = aco_opcode::buffer_atomic_umin;
3872          image_op = aco_opcode::image_atomic_umin;
3873          break;
3874       case nir_intrinsic_image_deref_atomic_imin:
3875          buf_op = aco_opcode::buffer_atomic_smin;
3876          image_op = aco_opcode::image_atomic_smin;
3877          break;
3878       case nir_intrinsic_image_deref_atomic_umax:
3879          buf_op = aco_opcode::buffer_atomic_umax;
3880          image_op = aco_opcode::image_atomic_umax;
3881          break;
3882       case nir_intrinsic_image_deref_atomic_imax:
3883          buf_op = aco_opcode::buffer_atomic_smax;
3884          image_op = aco_opcode::image_atomic_smax;
3885          break;
3886       case nir_intrinsic_image_deref_atomic_and:
3887          buf_op = aco_opcode::buffer_atomic_and;
3888          image_op = aco_opcode::image_atomic_and;
3889          break;
3890       case nir_intrinsic_image_deref_atomic_or:
3891          buf_op = aco_opcode::buffer_atomic_or;
3892          image_op = aco_opcode::image_atomic_or;
3893          break;
3894       case nir_intrinsic_image_deref_atomic_xor:
3895          buf_op = aco_opcode::buffer_atomic_xor;
3896          image_op = aco_opcode::image_atomic_xor;
3897          break;
3898       case nir_intrinsic_image_deref_atomic_exchange:
3899          buf_op = aco_opcode::buffer_atomic_swap;
3900          image_op = aco_opcode::image_atomic_swap;
3901          break;
3902       case nir_intrinsic_image_deref_atomic_comp_swap:
3903          buf_op = aco_opcode::buffer_atomic_cmpswap;
3904          image_op = aco_opcode::image_atomic_cmpswap;
3905          break;
3906       default:
3907          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
3908    }
3909
3910    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3911
3912    if (dim == GLSL_SAMPLER_DIM_BUF) {
3913       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
3914       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
3915       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
3916       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
3917       mubuf->operands[0] = Operand(vindex);
3918       mubuf->operands[1] = Operand(resource);
3919       mubuf->operands[2] = Operand((uint32_t)0);
3920       mubuf->operands[3] = Operand(data);
3921       if (return_previous)
3922          mubuf->definitions[0] = Definition(dst);
3923       mubuf->offset = 0;
3924       mubuf->idxen = true;
3925       mubuf->glc = return_previous;
3926       mubuf->dlc = false; /* Not needed for atomics */
3927       mubuf->disable_wqm = true;
3928       mubuf->barrier = barrier_image;
3929       ctx->program->needs_exact = true;
3930       ctx->block->instructions.emplace_back(std::move(mubuf));
3931       return;
3932    }
3933
3934    Temp coords = get_image_coords(ctx, instr, type);
3935    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
3936    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 4, return_previous ? 1 : 0)};
3937    mimg->operands[0] = Operand(coords);
3938    mimg->operands[1] = Operand(resource);
3939    mimg->operands[2] = Operand(s4); /* no sampler */
3940    mimg->operands[3] = Operand(data);
3941    if (return_previous)
3942       mimg->definitions[0] = Definition(dst);
3943    mimg->glc = return_previous;
3944    mimg->dlc = false; /* Not needed for atomics */
3945    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
3946    mimg->dmask = (1 << data.size()) - 1;
3947    mimg->unrm = true;
3948    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
3949    mimg->disable_wqm = true;
3950    mimg->barrier = barrier_image;
3951    ctx->program->needs_exact = true;
3952    ctx->block->instructions.emplace_back(std::move(mimg));
3953    return;
3954 }
3955
3956 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
3957 {
3958    if (in_elements && ctx->options->chip_class == GFX8) {
3959       Builder bld(ctx->program, ctx->block);
3960
3961       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
3962       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
3963       stride = bld.vop1(aco_opcode::v_cvt_f32_ubyte0, bld.def(v1), stride);
3964       stride = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), stride);
3965
3966       Temp size = emit_extract_vector(ctx, desc, 2, s1);
3967       size = bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), size);
3968
3969       Temp res = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), size, stride);
3970       res = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), res);
3971       bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
3972
3973       // TODO: we can probably calculate this faster on the scalar unit to do: size / stride{1,2,4,8,12,16}
3974       /* idea
3975        * for 1,2,4,8,16, the result is just (stride >> S_FF1_I32_B32)
3976        * in case 12 (or 3?), we have to divide by 3:
3977        * set v_skip in case it's 12 (if we also have to take care of 3, shift first)
3978        * use v_mul_hi_u32 with magic number to divide
3979        * we need some pseudo merge opcode to overwrite the original SALU result with readfirstlane
3980        * disable v_skip
3981        * total: 6 SALU + 2 VALU instructions vs 1 SALU + 6 VALU instructions
3982        */
3983
3984    } else {
3985       emit_extract_vector(ctx, desc, 2, dst);
3986    }
3987 }
3988
3989 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
3990 {
3991    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
3992    const struct glsl_type *type = glsl_without_array(var->type);
3993    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3994    bool is_array = glsl_sampler_type_is_array(type);
3995    Builder bld(ctx->program, ctx->block);
3996
3997    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3998       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
3999       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4000    }
4001
4002    /* LOD */
4003    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4004
4005    /* Resource */
4006    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4007
4008    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4009
4010    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1)};
4011    mimg->operands[0] = Operand(lod);
4012    mimg->operands[1] = Operand(resource);
4013    unsigned& dmask = mimg->dmask;
4014    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4015    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4016    mimg->da = glsl_sampler_type_is_array(type);
4017    mimg->can_reorder = true;
4018    Definition& def = mimg->definitions[0];
4019    ctx->block->instructions.emplace_back(std::move(mimg));
4020
4021    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4022        glsl_sampler_type_is_array(type)) {
4023
4024       assert(instr->dest.ssa.num_components == 3);
4025       Temp tmp = {ctx->program->allocateId(), v3};
4026       def = Definition(tmp);
4027       emit_split_vector(ctx, tmp, 3);
4028
4029       /* divide 3rd value by 6 by multiplying with magic number */
4030       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4031       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4032
4033       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4034                  emit_extract_vector(ctx, tmp, 0, v1),
4035                  emit_extract_vector(ctx, tmp, 1, v1),
4036                  by_6);
4037
4038    } else if (ctx->options->chip_class >= GFX9 &&
4039               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4040               glsl_sampler_type_is_array(type)) {
4041       assert(instr->dest.ssa.num_components == 2);
4042       def = Definition(dst);
4043       dmask = 0x5;
4044    } else {
4045       def = Definition(dst);
4046    }
4047
4048    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4049 }
4050
4051 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4052 {
4053    Builder bld(ctx->program, ctx->block);
4054    unsigned num_components = instr->num_components;
4055
4056    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4057    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4058    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4059
4060    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4061    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc);
4062 }
4063
4064 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4065 {
4066    Builder bld(ctx->program, ctx->block);
4067    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4068    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4069    unsigned writemask = nir_intrinsic_write_mask(instr);
4070
4071    Temp offset;
4072    if (ctx->options->chip_class < GFX8)
4073       offset = as_vgpr(ctx,get_ssa_temp(ctx, instr->src[2].ssa));
4074    else
4075       offset = get_ssa_temp(ctx, instr->src[2].ssa);
4076
4077    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4078    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4079
4080    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4081                ctx->options->chip_class >= GFX8;
4082    if (smem)
4083       offset = bld.as_uniform(offset);
4084    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4085
4086    while (writemask) {
4087       int start, count;
4088       u_bit_scan_consecutive_range(&writemask, &start, &count);
4089       if (count == 3 && smem) {
4090          writemask |= 1u << (start + 2);
4091          count = 2;
4092       }
4093       int num_bytes = count * elem_size_bytes;
4094
4095       if (num_bytes > 16) {
4096          assert(elem_size_bytes == 8);
4097          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4098          count = 2;
4099          num_bytes = 16;
4100       }
4101
4102       // TODO: check alignment of sub-dword stores
4103       // TODO: split 3 bytes. there is no store instruction for that
4104
4105       Temp write_data;
4106       if (count != instr->num_components) {
4107          emit_split_vector(ctx, data, instr->num_components);
4108          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4109          for (int i = 0; i < count; i++) {
4110             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4111             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4112          }
4113          write_data = bld.tmp(smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4114          vec->definitions[0] = Definition(write_data);
4115          ctx->block->instructions.emplace_back(std::move(vec));
4116       } else if (!smem && data.type() != RegType::vgpr) {
4117          assert(num_bytes % 4 == 0);
4118          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4119       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4120          assert(num_bytes % 4 == 0);
4121          write_data = bld.as_uniform(data);
4122       } else {
4123          write_data = data;
4124       }
4125
4126       aco_opcode vmem_op, smem_op;
4127       switch (num_bytes) {
4128          case 4:
4129             vmem_op = aco_opcode::buffer_store_dword;
4130             smem_op = aco_opcode::s_buffer_store_dword;
4131             break;
4132          case 8:
4133             vmem_op = aco_opcode::buffer_store_dwordx2;
4134             smem_op = aco_opcode::s_buffer_store_dwordx2;
4135             break;
4136          case 12:
4137             vmem_op = aco_opcode::buffer_store_dwordx3;
4138             smem_op = aco_opcode::last_opcode;
4139             assert(!smem);
4140             break;
4141          case 16:
4142             vmem_op = aco_opcode::buffer_store_dwordx4;
4143             smem_op = aco_opcode::s_buffer_store_dwordx4;
4144             break;
4145          default:
4146             unreachable("Store SSBO not implemented for this size.");
4147       }
4148       if (ctx->stage == fragment_fs)
4149          smem_op = aco_opcode::p_fs_buffer_store_smem;
4150
4151       if (smem) {
4152          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4153          store->operands[0] = Operand(rsrc);
4154          if (start) {
4155             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4156                                 offset, Operand(start * elem_size_bytes));
4157             store->operands[1] = Operand(off);
4158          } else {
4159             store->operands[1] = Operand(offset);
4160          }
4161          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4162             store->operands[1].setFixed(m0);
4163          store->operands[2] = Operand(write_data);
4164          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4165          store->dlc = false;
4166          store->disable_wqm = true;
4167          store->barrier = barrier_buffer;
4168          ctx->block->instructions.emplace_back(std::move(store));
4169          ctx->program->wb_smem_l1_on_end = true;
4170          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4171             ctx->block->kind |= block_kind_needs_lowering;
4172             ctx->program->needs_exact = true;
4173          }
4174       } else {
4175          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4176          store->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4177          store->operands[1] = Operand(rsrc);
4178          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4179          store->operands[3] = Operand(write_data);
4180          store->offset = start * elem_size_bytes;
4181          store->offen = (offset.type() == RegType::vgpr);
4182          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4183          store->dlc = false;
4184          store->disable_wqm = true;
4185          store->barrier = barrier_buffer;
4186          ctx->program->needs_exact = true;
4187          ctx->block->instructions.emplace_back(std::move(store));
4188       }
4189    }
4190 }
4191
4192 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4193 {
4194    /* return the previous value if dest is ever used */
4195    bool return_previous = false;
4196    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4197       return_previous = true;
4198       break;
4199    }
4200    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4201       return_previous = true;
4202       break;
4203    }
4204
4205    Builder bld(ctx->program, ctx->block);
4206    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4207
4208    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4209       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4210                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4211
4212    Temp offset;
4213    if (ctx->options->chip_class < GFX8)
4214       offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4215    else
4216       offset = get_ssa_temp(ctx, instr->src[1].ssa);
4217
4218    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4219    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4220
4221    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4222
4223    aco_opcode op32, op64;
4224    switch (instr->intrinsic) {
4225       case nir_intrinsic_ssbo_atomic_add:
4226          op32 = aco_opcode::buffer_atomic_add;
4227          op64 = aco_opcode::buffer_atomic_add_x2;
4228          break;
4229       case nir_intrinsic_ssbo_atomic_imin:
4230          op32 = aco_opcode::buffer_atomic_smin;
4231          op64 = aco_opcode::buffer_atomic_smin_x2;
4232          break;
4233       case nir_intrinsic_ssbo_atomic_umin:
4234          op32 = aco_opcode::buffer_atomic_umin;
4235          op64 = aco_opcode::buffer_atomic_umin_x2;
4236          break;
4237       case nir_intrinsic_ssbo_atomic_imax:
4238          op32 = aco_opcode::buffer_atomic_smax;
4239          op64 = aco_opcode::buffer_atomic_smax_x2;
4240          break;
4241       case nir_intrinsic_ssbo_atomic_umax:
4242          op32 = aco_opcode::buffer_atomic_umax;
4243          op64 = aco_opcode::buffer_atomic_umax_x2;
4244          break;
4245       case nir_intrinsic_ssbo_atomic_and:
4246          op32 = aco_opcode::buffer_atomic_and;
4247          op64 = aco_opcode::buffer_atomic_and_x2;
4248          break;
4249       case nir_intrinsic_ssbo_atomic_or:
4250          op32 = aco_opcode::buffer_atomic_or;
4251          op64 = aco_opcode::buffer_atomic_or_x2;
4252          break;
4253       case nir_intrinsic_ssbo_atomic_xor:
4254          op32 = aco_opcode::buffer_atomic_xor;
4255          op64 = aco_opcode::buffer_atomic_xor_x2;
4256          break;
4257       case nir_intrinsic_ssbo_atomic_exchange:
4258          op32 = aco_opcode::buffer_atomic_swap;
4259          op64 = aco_opcode::buffer_atomic_swap_x2;
4260          break;
4261       case nir_intrinsic_ssbo_atomic_comp_swap:
4262          op32 = aco_opcode::buffer_atomic_cmpswap;
4263          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4264          break;
4265       default:
4266          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4267    }
4268    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4269    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4270    mubuf->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4271    mubuf->operands[1] = Operand(rsrc);
4272    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4273    mubuf->operands[3] = Operand(data);
4274    if (return_previous)
4275       mubuf->definitions[0] = Definition(dst);
4276    mubuf->offset = 0;
4277    mubuf->offen = (offset.type() == RegType::vgpr);
4278    mubuf->glc = return_previous;
4279    mubuf->dlc = false; /* Not needed for atomics */
4280    mubuf->disable_wqm = true;
4281    mubuf->barrier = barrier_buffer;
4282    ctx->program->needs_exact = true;
4283    ctx->block->instructions.emplace_back(std::move(mubuf));
4284 }
4285
4286 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4287
4288    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4289    Builder bld(ctx->program, ctx->block);
4290    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4291    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4292 }
4293
4294 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4295 {
4296    Builder bld(ctx->program, ctx->block);
4297    unsigned num_components = instr->num_components;
4298    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4299
4300    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4301    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4302
4303    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4304    bool dlc = glc && ctx->options->chip_class >= GFX10;
4305    aco_opcode op;
4306    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4307       bool global = ctx->options->chip_class >= GFX9;
4308       aco_opcode op;
4309       switch (num_bytes) {
4310       case 4:
4311          op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4312          break;
4313       case 8:
4314          op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4315          break;
4316       case 12:
4317          op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4318          break;
4319       case 16:
4320          op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
4321          break;
4322       default:
4323          unreachable("load_global not implemented for this size.");
4324       }
4325       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
4326       flat->operands[0] = Operand(addr);
4327       flat->operands[1] = Operand(s1);
4328       flat->glc = glc;
4329       flat->dlc = dlc;
4330
4331       if (dst.type() == RegType::sgpr) {
4332          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4333          flat->definitions[0] = Definition(vec);
4334          ctx->block->instructions.emplace_back(std::move(flat));
4335          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
4336       } else {
4337          flat->definitions[0] = Definition(dst);
4338          ctx->block->instructions.emplace_back(std::move(flat));
4339       }
4340       emit_split_vector(ctx, dst, num_components);
4341    } else {
4342       switch (num_bytes) {
4343          case 4:
4344             op = aco_opcode::s_load_dword;
4345             break;
4346          case 8:
4347             op = aco_opcode::s_load_dwordx2;
4348             break;
4349          case 12:
4350          case 16:
4351             op = aco_opcode::s_load_dwordx4;
4352             break;
4353          default:
4354             unreachable("load_global not implemented for this size.");
4355       }
4356       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4357       load->operands[0] = Operand(addr);
4358       load->operands[1] = Operand(0u);
4359       load->definitions[0] = Definition(dst);
4360       load->glc = glc;
4361       load->dlc = dlc;
4362       load->barrier = barrier_buffer;
4363       assert(ctx->options->chip_class >= GFX8 || !glc);
4364
4365       if (dst.size() == 3) {
4366          /* trim vector */
4367          Temp vec = bld.tmp(s4);
4368          load->definitions[0] = Definition(vec);
4369          ctx->block->instructions.emplace_back(std::move(load));
4370          emit_split_vector(ctx, vec, 4);
4371
4372          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4373                     emit_extract_vector(ctx, vec, 0, s1),
4374                     emit_extract_vector(ctx, vec, 1, s1),
4375                     emit_extract_vector(ctx, vec, 2, s1));
4376       } else {
4377          ctx->block->instructions.emplace_back(std::move(load));
4378       }
4379    }
4380 }
4381
4382 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
4383 {
4384    Builder bld(ctx->program, ctx->block);
4385    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4386
4387    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4388    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4389
4390    unsigned writemask = nir_intrinsic_write_mask(instr);
4391    while (writemask) {
4392       int start, count;
4393       u_bit_scan_consecutive_range(&writemask, &start, &count);
4394       unsigned num_bytes = count * elem_size_bytes;
4395
4396       Temp write_data = data;
4397       if (count != instr->num_components) {
4398          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4399          for (int i = 0; i < count; i++)
4400             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
4401          write_data = bld.tmp(RegType::vgpr, count);
4402          vec->definitions[0] = Definition(write_data);
4403          ctx->block->instructions.emplace_back(std::move(vec));
4404       }
4405
4406       unsigned offset = start * elem_size_bytes;
4407       if (offset > 0 && ctx->options->chip_class < GFX9) {
4408          Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
4409          Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
4410          Temp carry = bld.tmp(s2);
4411          bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
4412
4413          bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
4414                   Operand(offset), addr0);
4415          bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(s2),
4416                   Operand(0u), addr1,
4417                   carry).def(1).setHint(vcc);
4418
4419          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
4420
4421          offset = 0;
4422       }
4423
4424       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4425       bool global = ctx->options->chip_class >= GFX9;
4426       aco_opcode op;
4427       switch (num_bytes) {
4428       case 4:
4429          op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
4430          break;
4431       case 8:
4432          op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
4433          break;
4434       case 12:
4435          op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
4436          break;
4437       case 16:
4438          op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
4439          break;
4440       default:
4441          unreachable("store_global not implemented for this size.");
4442       }
4443       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
4444       flat->operands[0] = Operand(addr);
4445       flat->operands[1] = Operand(s1);
4446       flat->operands[2] = Operand(data);
4447       flat->glc = glc;
4448       flat->dlc = false;
4449       flat->offset = offset;
4450       ctx->block->instructions.emplace_back(std::move(flat));
4451    }
4452 }
4453
4454 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
4455    Builder bld(ctx->program, ctx->block);
4456    switch(instr->intrinsic) {
4457       case nir_intrinsic_group_memory_barrier:
4458       case nir_intrinsic_memory_barrier:
4459          bld.barrier(aco_opcode::p_memory_barrier_all);
4460          break;
4461       case nir_intrinsic_memory_barrier_atomic_counter:
4462          bld.barrier(aco_opcode::p_memory_barrier_atomic);
4463          break;
4464       case nir_intrinsic_memory_barrier_buffer:
4465          bld.barrier(aco_opcode::p_memory_barrier_buffer);
4466          break;
4467       case nir_intrinsic_memory_barrier_image:
4468          bld.barrier(aco_opcode::p_memory_barrier_image);
4469          break;
4470       case nir_intrinsic_memory_barrier_shared:
4471          bld.barrier(aco_opcode::p_memory_barrier_shared);
4472          break;
4473       default:
4474          unreachable("Unimplemented memory barrier intrinsic");
4475          break;
4476    }
4477 }
4478
4479 Operand load_lds_size_m0(isel_context *ctx)
4480 {
4481    /* TODO: m0 does not need to be initialized on GFX9+ */
4482    Builder bld(ctx->program, ctx->block);
4483    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
4484 }
4485
4486
4487 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4488 {
4489    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4490    Operand m = load_lds_size_m0(ctx);
4491    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4492    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
4493    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4494    Builder bld(ctx->program, ctx->block);
4495
4496    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
4497    unsigned bytes_read = 0;
4498    unsigned result_size = 0;
4499    unsigned total_bytes = instr->num_components * elem_size_bytes;
4500    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : instr->dest.ssa.bit_size / 8;
4501    std::array<Temp, 4> result;
4502
4503    while (bytes_read < total_bytes) {
4504       unsigned todo = total_bytes - bytes_read;
4505       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
4506       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
4507
4508       aco_opcode op = aco_opcode::last_opcode;
4509       if (todo >= 16 && aligned16) {
4510          op = aco_opcode::ds_read_b128;
4511          todo = 16;
4512       } else if (todo >= 12 && aligned16) {
4513          op = aco_opcode::ds_read_b96;
4514          todo = 12;
4515       } else if (todo >= 8) {
4516          op = aligned8 ? aco_opcode::ds_read_b64 : aco_opcode::ds_read2_b32;
4517          todo = 8;
4518       } else if (todo >= 4) {
4519          op = aco_opcode::ds_read_b32;
4520          todo = 4;
4521       } else {
4522          assert(false);
4523       }
4524       assert(todo % elem_size_bytes == 0);
4525       unsigned num_elements = todo / elem_size_bytes;
4526       unsigned offset = nir_intrinsic_base(instr) + bytes_read;
4527       unsigned max_offset = op == aco_opcode::ds_read2_b32 ? 1019 : 65535;
4528
4529       Temp address_offset = address;
4530       if (offset > max_offset) {
4531          address_offset = bld.vadd32(bld.def(v1), Operand((uint32_t)nir_intrinsic_base(instr)), address_offset);
4532          offset = bytes_read;
4533       }
4534       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
4535
4536       Temp res;
4537       if (instr->num_components == 1 && dst.type() == RegType::vgpr)
4538          res = dst;
4539       else
4540          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
4541
4542       if (op == aco_opcode::ds_read2_b32)
4543          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
4544       else
4545          res = bld.ds(op, Definition(res), address_offset, m, offset);
4546
4547       if (instr->num_components == 1) {
4548          assert(todo == total_bytes);
4549          if (dst.type() == RegType::sgpr)
4550             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
4551          return;
4552       }
4553
4554       if (dst.type() == RegType::sgpr)
4555          res = bld.as_uniform(res);
4556
4557       if (num_elements == 1) {
4558          result[result_size++] = res;
4559       } else {
4560          assert(res != dst && res.size() % num_elements == 0);
4561          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
4562          split->operands[0] = Operand(res);
4563          for (unsigned i = 0; i < num_elements; i++)
4564             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
4565          ctx->block->instructions.emplace_back(std::move(split));
4566       }
4567
4568       bytes_read += todo;
4569    }
4570
4571    assert(result_size == instr->num_components && result_size > 1);
4572    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
4573    for (unsigned i = 0; i < result_size; i++)
4574       vec->operands[i] = Operand(result[i]);
4575    vec->definitions[0] = Definition(dst);
4576    ctx->block->instructions.emplace_back(std::move(vec));
4577    ctx->allocated_vec.emplace(dst.id(), result);
4578 }
4579
4580 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned offset0, unsigned offset1, unsigned align)
4581 {
4582    Builder bld(ctx->program, ctx->block);
4583    unsigned bytes_written = 0;
4584    while (bytes_written < data.size() * 4) {
4585       unsigned todo = data.size() * 4 - bytes_written;
4586       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
4587       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
4588
4589       aco_opcode op = aco_opcode::last_opcode;
4590       unsigned size = 0;
4591       if (todo >= 16 && aligned16) {
4592          op = aco_opcode::ds_write_b128;
4593          size = 4;
4594       } else if (todo >= 12 && aligned16) {
4595          op = aco_opcode::ds_write_b96;
4596          size = 3;
4597       } else if (todo >= 8) {
4598          op = aligned8 ? aco_opcode::ds_write_b64 : aco_opcode::ds_write2_b32;
4599          size = 2;
4600       } else if (todo >= 4) {
4601          op = aco_opcode::ds_write_b32;
4602          size = 1;
4603       } else {
4604          assert(false);
4605       }
4606
4607       bool write2 = op == aco_opcode::ds_write2_b32;
4608       unsigned offset = offset0 + offset1 + bytes_written;
4609       unsigned max_offset = write2 ? 1020 : 65535;
4610       Temp address_offset = address;
4611       if (offset > max_offset) {
4612          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
4613          offset = offset1 + bytes_written;
4614       }
4615       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
4616
4617       if (write2) {
4618          Temp val0 = emit_extract_vector(ctx, data, bytes_written >> 2, v1);
4619          Temp val1 = emit_extract_vector(ctx, data, (bytes_written >> 2) + 1, v1);
4620          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
4621       } else {
4622          Temp val = emit_extract_vector(ctx, data, bytes_written >> 2, RegClass(RegType::vgpr, size));
4623          bld.ds(op, address_offset, val, m, offset);
4624       }
4625
4626       bytes_written += size * 4;
4627    }
4628 }
4629
4630 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4631 {
4632    unsigned offset = nir_intrinsic_base(instr);
4633    unsigned writemask = nir_intrinsic_write_mask(instr);
4634    Operand m = load_lds_size_m0(ctx);
4635    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4636    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4637    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4638    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
4639
4640    /* we need at most two stores for 32bit variables */
4641    int start[2], count[2];
4642    u_bit_scan_consecutive_range(&writemask, &start[0], &count[0]);
4643    u_bit_scan_consecutive_range(&writemask, &start[1], &count[1]);
4644    assert(writemask == 0);
4645
4646    /* one combined store is sufficient */
4647    if (count[0] == count[1]) {
4648       Builder bld(ctx->program, ctx->block);
4649
4650       Temp address_offset = address;
4651       if ((offset >> 2) + start[1] > 255) {
4652          address_offset = bld.vadd32(bld.def(v1), Operand(offset), address_offset);
4653          offset = 0;
4654       }
4655
4656       assert(count[0] == 1);
4657       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
4658       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
4659       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
4660       offset = offset / elem_size_bytes;
4661       bld.ds(op, address_offset, val0, val1, m,
4662              offset + start[0], offset + start[1]);
4663       return;
4664    }
4665
4666    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4667    for (unsigned i = 0; i < 2; i++) {
4668       if (count[i] == 0)
4669          continue;
4670
4671       Temp write_data = emit_extract_vector(ctx, data, start[i], RegClass(RegType::vgpr, count[i] * elem_size_bytes / 4));
4672       ds_write_helper(ctx, m, address, write_data, offset, start[i] * elem_size_bytes, align);
4673    }
4674    return;
4675 }
4676
4677 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4678 {
4679    unsigned offset = nir_intrinsic_base(instr);
4680    Operand m = load_lds_size_m0(ctx);
4681    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4682    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4683
4684    unsigned num_operands = 3;
4685    aco_opcode op32, op64, op32_rtn, op64_rtn;
4686    switch(instr->intrinsic) {
4687       case nir_intrinsic_shared_atomic_add:
4688          op32 = aco_opcode::ds_add_u32;
4689          op64 = aco_opcode::ds_add_u64;
4690          op32_rtn = aco_opcode::ds_add_rtn_u32;
4691          op64_rtn = aco_opcode::ds_add_rtn_u64;
4692          break;
4693       case nir_intrinsic_shared_atomic_imin:
4694          op32 = aco_opcode::ds_min_i32;
4695          op64 = aco_opcode::ds_min_i64;
4696          op32_rtn = aco_opcode::ds_min_rtn_i32;
4697          op64_rtn = aco_opcode::ds_min_rtn_i64;
4698          break;
4699       case nir_intrinsic_shared_atomic_umin:
4700          op32 = aco_opcode::ds_min_u32;
4701          op64 = aco_opcode::ds_min_u64;
4702          op32_rtn = aco_opcode::ds_min_rtn_u32;
4703          op64_rtn = aco_opcode::ds_min_rtn_u64;
4704          break;
4705       case nir_intrinsic_shared_atomic_imax:
4706          op32 = aco_opcode::ds_max_i32;
4707          op64 = aco_opcode::ds_max_i64;
4708          op32_rtn = aco_opcode::ds_max_rtn_i32;
4709          op64_rtn = aco_opcode::ds_max_rtn_i64;
4710          break;
4711       case nir_intrinsic_shared_atomic_umax:
4712          op32 = aco_opcode::ds_max_u32;
4713          op64 = aco_opcode::ds_max_u64;
4714          op32_rtn = aco_opcode::ds_max_rtn_u32;
4715          op64_rtn = aco_opcode::ds_max_rtn_u64;
4716          break;
4717       case nir_intrinsic_shared_atomic_and:
4718          op32 = aco_opcode::ds_and_b32;
4719          op64 = aco_opcode::ds_and_b64;
4720          op32_rtn = aco_opcode::ds_and_rtn_b32;
4721          op64_rtn = aco_opcode::ds_and_rtn_b64;
4722          break;
4723       case nir_intrinsic_shared_atomic_or:
4724          op32 = aco_opcode::ds_or_b32;
4725          op64 = aco_opcode::ds_or_b64;
4726          op32_rtn = aco_opcode::ds_or_rtn_b32;
4727          op64_rtn = aco_opcode::ds_or_rtn_b64;
4728          break;
4729       case nir_intrinsic_shared_atomic_xor:
4730          op32 = aco_opcode::ds_xor_b32;
4731          op64 = aco_opcode::ds_xor_b64;
4732          op32_rtn = aco_opcode::ds_xor_rtn_b32;
4733          op64_rtn = aco_opcode::ds_xor_rtn_b64;
4734          break;
4735       case nir_intrinsic_shared_atomic_exchange:
4736          op32 = aco_opcode::ds_write_b32;
4737          op64 = aco_opcode::ds_write_b64;
4738          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
4739          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
4740          break;
4741       case nir_intrinsic_shared_atomic_comp_swap:
4742          op32 = aco_opcode::ds_cmpst_b32;
4743          op64 = aco_opcode::ds_cmpst_b64;
4744          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
4745          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
4746          num_operands = 4;
4747          break;
4748       default:
4749          unreachable("Unhandled shared atomic intrinsic");
4750    }
4751
4752    /* return the previous value if dest is ever used */
4753    bool return_previous = false;
4754    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4755       return_previous = true;
4756       break;
4757    }
4758    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4759       return_previous = true;
4760       break;
4761    }
4762
4763    aco_opcode op;
4764    if (data.size() == 1) {
4765       assert(instr->dest.ssa.bit_size == 32);
4766       op = return_previous ? op32_rtn : op32;
4767    } else {
4768       assert(instr->dest.ssa.bit_size == 64);
4769       op = return_previous ? op64_rtn : op64;
4770    }
4771
4772    if (offset > 65535) {
4773       Builder bld(ctx->program, ctx->block);
4774       address = bld.vadd32(bld.def(v1), Operand(offset), address);
4775       offset = 0;
4776    }
4777
4778    aco_ptr<DS_instruction> ds;
4779    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
4780    ds->operands[0] = Operand(address);
4781    ds->operands[1] = Operand(data);
4782    if (num_operands == 4)
4783       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
4784    ds->operands[num_operands - 1] = m;
4785    ds->offset0 = offset;
4786    if (return_previous)
4787       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
4788    ctx->block->instructions.emplace_back(std::move(ds));
4789 }
4790
4791 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
4792    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
4793    Builder bld(ctx->program, ctx->block);
4794    Temp scratch_addr = ctx->private_segment_buffer;
4795    if (ctx->stage != MESA_SHADER_COMPUTE)
4796       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), ctx->private_segment_buffer, Operand(0u));
4797    uint32_t rsrc_conf;
4798    /* older generations need element size = 16 bytes */
4799    if (ctx->program->chip_class >= GFX9)
4800       rsrc_conf = 0x00E00000u;
4801    else
4802       rsrc_conf = 0x00F80000u;
4803    /* buffer res = addr + num_records = -1, index_stride = 64, add_tid_enable = true */
4804    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
4805    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4806    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4807
4808    aco_opcode op;
4809    switch (dst.size()) {
4810       case 1:
4811          op = aco_opcode::buffer_load_dword;
4812          break;
4813       case 2:
4814          op = aco_opcode::buffer_load_dwordx2;
4815          break;
4816       case 3:
4817          op = aco_opcode::buffer_load_dwordx3;
4818          break;
4819       case 4:
4820          op = aco_opcode::buffer_load_dwordx4;
4821          break;
4822       case 6:
4823       case 8: {
4824          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4825          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
4826                                 bld.def(v4), offset, rsrc,
4827                                 ctx->scratch_offset, 0, true);
4828          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
4829                                                   aco_opcode::buffer_load_dwordx4,
4830                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
4831                                 offset, rsrc, ctx->scratch_offset, 16, true);
4832          emit_split_vector(ctx, lower, 2);
4833          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
4834          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
4835          if (dst.size() == 8) {
4836             emit_split_vector(ctx, upper, 2);
4837             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
4838             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
4839          } else {
4840             elems[2] = upper;
4841          }
4842
4843          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
4844                                                                          Format::PSEUDO, dst.size() / 2, 1)};
4845          for (unsigned i = 0; i < dst.size() / 2; i++)
4846             vec->operands[i] = Operand(elems[i]);
4847          vec->definitions[0] = Definition(dst);
4848          bld.insert(std::move(vec));
4849          ctx->allocated_vec.emplace(dst.id(), elems);
4850          return;
4851       }
4852       default:
4853          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
4854    }
4855
4856    bld.mubuf(op, Definition(dst), offset, rsrc, ctx->scratch_offset, 0, true);
4857    emit_split_vector(ctx, dst, instr->num_components);
4858 }
4859
4860 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
4861    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
4862    Builder bld(ctx->program, ctx->block);
4863    Temp scratch_addr = ctx->private_segment_buffer;
4864    if (ctx->stage != MESA_SHADER_COMPUTE)
4865       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), ctx->private_segment_buffer, Operand(0u));
4866    uint32_t rsrc_conf;
4867    /* older generations need element size = 16 bytes */
4868    if (ctx->program->chip_class >= GFX9)
4869       rsrc_conf = 0x00E00000u;
4870    else
4871       rsrc_conf = 0x00F80000u;
4872    /* buffer res = addr + num_records = -1, index_stride = 64, add_tid_enable = true */
4873    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
4874    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4875    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4876
4877    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4878    unsigned writemask = nir_intrinsic_write_mask(instr);
4879
4880    while (writemask) {
4881       int start, count;
4882       u_bit_scan_consecutive_range(&writemask, &start, &count);
4883       int num_bytes = count * elem_size_bytes;
4884
4885       if (num_bytes > 16) {
4886          assert(elem_size_bytes == 8);
4887          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4888          count = 2;
4889          num_bytes = 16;
4890       }
4891
4892       // TODO: check alignment of sub-dword stores
4893       // TODO: split 3 bytes. there is no store instruction for that
4894
4895       Temp write_data;
4896       if (count != instr->num_components) {
4897          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4898          for (int i = 0; i < count; i++) {
4899             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
4900             vec->operands[i] = Operand(elem);
4901          }
4902          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
4903          vec->definitions[0] = Definition(write_data);
4904          ctx->block->instructions.emplace_back(std::move(vec));
4905       } else {
4906          write_data = data;
4907       }
4908
4909       aco_opcode op;
4910       switch (num_bytes) {
4911          case 4:
4912             op = aco_opcode::buffer_store_dword;
4913             break;
4914          case 8:
4915             op = aco_opcode::buffer_store_dwordx2;
4916             break;
4917          case 12:
4918             op = aco_opcode::buffer_store_dwordx3;
4919             break;
4920          case 16:
4921             op = aco_opcode::buffer_store_dwordx4;
4922             break;
4923          default:
4924             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
4925       }
4926
4927       bld.mubuf(op, offset, rsrc, ctx->scratch_offset, write_data, start * elem_size_bytes, true);
4928    }
4929 }
4930
4931 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
4932    uint8_t log2_ps_iter_samples;
4933    if (ctx->program->info->ps.force_persample) {
4934       log2_ps_iter_samples =
4935          util_logbase2(ctx->options->key.fs.num_samples);
4936    } else {
4937       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
4938    }
4939
4940    /* The bit pattern matches that used by fixed function fragment
4941     * processing. */
4942    static const unsigned ps_iter_masks[] = {
4943       0xffff, /* not used */
4944       0x5555,
4945       0x1111,
4946       0x0101,
4947       0x0001,
4948    };
4949    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4950
4951    Builder bld(ctx->program, ctx->block);
4952
4953    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), ctx->fs_inputs[fs_input::ancillary], Operand(8u), Operand(4u));
4954    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
4955    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
4956    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4957    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, ctx->fs_inputs[fs_input::sample_coverage]);
4958 }
4959
4960 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
4961 {
4962    Builder bld(ctx->program, ctx->block);
4963
4964    if (cluster_size == 1) {
4965       return src;
4966    } if (op == nir_op_iand && cluster_size == 4) {
4967       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
4968       Temp tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src);
4969       return bld.sop1(aco_opcode::s_not_b64, bld.def(s2), bld.def(s1, scc),
4970                       bld.sop1(aco_opcode::s_wqm_b64, bld.def(s2), bld.def(s1, scc), tmp));
4971    } else if (op == nir_op_ior && cluster_size == 4) {
4972       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
4973       return bld.sop1(aco_opcode::s_wqm_b64, bld.def(s2), bld.def(s1, scc),
4974                       bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2)));
4975    } else if (op == nir_op_iand && cluster_size == 64) {
4976       //subgroupAnd(val) -> (exec & ~val) == 0
4977       Temp tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src).def(1).getTemp();
4978       return bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), tmp, Operand(0u));
4979    } else if (op == nir_op_ior && cluster_size == 64) {
4980       //subgroupOr(val) -> (val & exec) != 0
4981       return bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2)).def(1).getTemp();
4982    } else if (op == nir_op_ixor && cluster_size == 64) {
4983       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
4984       Temp tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
4985       tmp = bld.sop1(aco_opcode::s_bcnt1_i32_b64, bld.def(s2), bld.def(s1, scc), tmp);
4986       return bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
4987    } else {
4988       //subgroupClustered{And,Or,Xor}(val, n) ->
4989       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0))
4990       //cluster_offset = ~(n - 1) & lane_id
4991       //cluster_mask = ((1 << n) - 1)
4992       //subgroupClusteredAnd():
4993       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
4994       //subgroupClusteredOr():
4995       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
4996       //subgroupClusteredXor():
4997       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
4998       Temp lane_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
4999                               bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5000       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5001
5002       Temp tmp;
5003       if (op == nir_op_iand)
5004          tmp = bld.sop2(aco_opcode::s_orn2_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5005       else
5006          tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5007
5008       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5009       tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5010       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5011       if (cluster_mask != 0xffffffff)
5012          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5013
5014       Definition cmp_def = Definition();
5015       if (op == nir_op_iand) {
5016          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2), Operand(cluster_mask), tmp).def(0);
5017       } else if (op == nir_op_ior) {
5018          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp).def(0);
5019       } else if (op == nir_op_ixor) {
5020          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5021                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5022          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp).def(0);
5023       }
5024       cmp_def.setHint(vcc);
5025       return cmp_def.getTemp();
5026    }
5027 }
5028
5029 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5030 {
5031    Builder bld(ctx->program, ctx->block);
5032
5033    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5034    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5035    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5036    Temp tmp;
5037    if (op == nir_op_iand)
5038       tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src);
5039    else
5040       tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5041
5042    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5043    Temp lo = lohi.def(0).getTemp();
5044    Temp hi = lohi.def(1).getTemp();
5045    Temp mbcnt = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), hi,
5046                          bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), lo, Operand(0u)));
5047
5048    Definition cmp_def = Definition();
5049    if (op == nir_op_iand)
5050       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2), Operand(0u), mbcnt).def(0);
5051    else if (op == nir_op_ior)
5052       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), mbcnt).def(0);
5053    else if (op == nir_op_ixor)
5054       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u),
5055                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5056    cmp_def.setHint(vcc);
5057    return cmp_def.getTemp();
5058 }
5059
5060 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5061 {
5062    Builder bld(ctx->program, ctx->block);
5063
5064    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5065    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5066    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5067    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5068    if (op == nir_op_iand)
5069       return bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5070    else if (op == nir_op_ior)
5071       return bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5072    else if (op == nir_op_ixor)
5073       return bld.sop2(aco_opcode::s_xor_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5074
5075    assert(false);
5076    return Temp();
5077 }
5078
5079 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5080 {
5081    Builder bld(ctx->program, ctx->block);
5082    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5083    if (src.regClass().type() == RegType::vgpr) {
5084       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5085    } else if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5086       bld.sopc(aco_opcode::s_cmp_lg_u64, bld.scc(dst), Operand(0u), Operand(src));
5087    } else if (src.regClass() == s1) {
5088       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5089    } else if (src.regClass() == s2) {
5090       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5091    } else {
5092       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5093       nir_print_instr(&instr->instr, stderr);
5094       fprintf(stderr, "\n");
5095    }
5096 }
5097
5098 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5099 {
5100    Builder bld(ctx->program, ctx->block);
5101    Temp p1 = ctx->fs_inputs[fs_input::persp_center_p1];
5102    Temp p2 = ctx->fs_inputs[fs_input::persp_center_p2];
5103
5104    /* Build DD X/Y */
5105    Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_quad_perm(0, 0, 0, 0));
5106    Temp ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(1, 1, 1, 1));
5107    Temp ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(2, 2, 2, 2));
5108    Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_quad_perm(0, 0, 0, 0));
5109    Temp ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(1, 1, 1, 1));
5110    Temp ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(2, 2, 2, 2));
5111
5112    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5113    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
5114    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
5115    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
5116    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
5117    Temp wqm1 = bld.tmp(v1);
5118    emit_wqm(ctx, tmp1, wqm1, true);
5119    Temp wqm2 = bld.tmp(v1);
5120    emit_wqm(ctx, tmp2, wqm2, true);
5121    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
5122    return;
5123 }
5124
5125 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
5126 {
5127    Builder bld(ctx->program, ctx->block);
5128    switch(instr->intrinsic) {
5129    case nir_intrinsic_load_barycentric_sample:
5130    case nir_intrinsic_load_barycentric_pixel:
5131    case nir_intrinsic_load_barycentric_centroid: {
5132       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
5133       fs_input input = get_interp_input(instr->intrinsic, mode);
5134
5135       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5136       if (input == fs_input::max_inputs) {
5137          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5138                     Operand(0u), Operand(0u));
5139       } else {
5140          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5141                     ctx->fs_inputs[input],
5142                     ctx->fs_inputs[input + 1]);
5143       }
5144       emit_split_vector(ctx, dst, 2);
5145       break;
5146    }
5147    case nir_intrinsic_load_barycentric_at_sample: {
5148       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
5149       switch (ctx->options->key.fs.num_samples) {
5150          case 2: sample_pos_offset += 1 << 3; break;
5151          case 4: sample_pos_offset += 3 << 3; break;
5152          case 8: sample_pos_offset += 7 << 3; break;
5153          default: break;
5154       }
5155       Temp sample_pos;
5156       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5157       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
5158       if (addr.type() == RegType::sgpr) {
5159          Operand offset;
5160          if (const_addr) {
5161             sample_pos_offset += const_addr->u32 << 3;
5162             offset = Operand(sample_pos_offset);
5163          } else if (ctx->options->chip_class >= GFX9) {
5164             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5165          } else {
5166             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
5167             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5168          }
5169          addr = ctx->private_segment_buffer;
5170          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), addr, Operand(offset));
5171
5172       } else if (ctx->options->chip_class >= GFX9) {
5173          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5174          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, ctx->private_segment_buffer, sample_pos_offset);
5175       } else {
5176          /* addr += ctx->private_segment_buffer + sample_pos_offset */
5177          Temp tmp0 = bld.tmp(s1);
5178          Temp tmp1 = bld.tmp(s1);
5179          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), ctx->private_segment_buffer);
5180          Definition scc_tmp = bld.def(s1, scc);
5181          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
5182          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), scc_tmp.getTemp());
5183          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5184          Temp pck0 = bld.tmp(v1);
5185          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
5186          tmp1 = as_vgpr(ctx, tmp1);
5187          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(s2)), tmp1, Operand(0u), carry);
5188          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
5189
5190          /* sample_pos = flat_load_dwordx2 addr */
5191          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
5192       }
5193
5194       /* sample_pos -= 0.5 */
5195       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
5196       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
5197       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
5198       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
5199       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
5200
5201       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5202       break;
5203    }
5204    case nir_intrinsic_load_barycentric_at_offset: {
5205       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
5206       RegClass rc = RegClass(offset.type(), 1);
5207       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
5208       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
5209       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5210       break;
5211    }
5212    case nir_intrinsic_load_front_face: {
5213       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5214                Operand(0u), ctx->fs_inputs[fs_input::front_face]).def(0).setHint(vcc);
5215       break;
5216    }
5217    case nir_intrinsic_load_view_index:
5218    case nir_intrinsic_load_layer_id: {
5219       if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & sw_vs)) {
5220          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5221          bld.copy(Definition(dst), Operand(ctx->view_index));
5222          break;
5223       }
5224
5225       unsigned idx = nir_intrinsic_base(instr);
5226       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5227                  Operand(2u), bld.m0(ctx->prim_mask), idx, 0);
5228       break;
5229    }
5230    case nir_intrinsic_load_frag_coord: {
5231       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
5232       break;
5233    }
5234    case nir_intrinsic_load_sample_pos: {
5235       Temp posx = ctx->fs_inputs[fs_input::frag_pos_0];
5236       Temp posy = ctx->fs_inputs[fs_input::frag_pos_1];
5237       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5238                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
5239                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
5240       break;
5241    }
5242    case nir_intrinsic_load_interpolated_input:
5243       visit_load_interpolated_input(ctx, instr);
5244       break;
5245    case nir_intrinsic_store_output:
5246       visit_store_output(ctx, instr);
5247       break;
5248    case nir_intrinsic_load_input:
5249       visit_load_input(ctx, instr);
5250       break;
5251    case nir_intrinsic_load_ubo:
5252       visit_load_ubo(ctx, instr);
5253       break;
5254    case nir_intrinsic_load_push_constant:
5255       visit_load_push_constant(ctx, instr);
5256       break;
5257    case nir_intrinsic_load_constant:
5258       visit_load_constant(ctx, instr);
5259       break;
5260    case nir_intrinsic_vulkan_resource_index:
5261       visit_load_resource(ctx, instr);
5262       break;
5263    case nir_intrinsic_discard:
5264       visit_discard(ctx, instr);
5265       break;
5266    case nir_intrinsic_discard_if:
5267       visit_discard_if(ctx, instr);
5268       break;
5269    case nir_intrinsic_load_shared:
5270       visit_load_shared(ctx, instr);
5271       break;
5272    case nir_intrinsic_store_shared:
5273       visit_store_shared(ctx, instr);
5274       break;
5275    case nir_intrinsic_shared_atomic_add:
5276    case nir_intrinsic_shared_atomic_imin:
5277    case nir_intrinsic_shared_atomic_umin:
5278    case nir_intrinsic_shared_atomic_imax:
5279    case nir_intrinsic_shared_atomic_umax:
5280    case nir_intrinsic_shared_atomic_and:
5281    case nir_intrinsic_shared_atomic_or:
5282    case nir_intrinsic_shared_atomic_xor:
5283    case nir_intrinsic_shared_atomic_exchange:
5284    case nir_intrinsic_shared_atomic_comp_swap:
5285       visit_shared_atomic(ctx, instr);
5286       break;
5287    case nir_intrinsic_image_deref_load:
5288       visit_image_load(ctx, instr);
5289       break;
5290    case nir_intrinsic_image_deref_store:
5291       visit_image_store(ctx, instr);
5292       break;
5293    case nir_intrinsic_image_deref_atomic_add:
5294    case nir_intrinsic_image_deref_atomic_umin:
5295    case nir_intrinsic_image_deref_atomic_imin:
5296    case nir_intrinsic_image_deref_atomic_umax:
5297    case nir_intrinsic_image_deref_atomic_imax:
5298    case nir_intrinsic_image_deref_atomic_and:
5299    case nir_intrinsic_image_deref_atomic_or:
5300    case nir_intrinsic_image_deref_atomic_xor:
5301    case nir_intrinsic_image_deref_atomic_exchange:
5302    case nir_intrinsic_image_deref_atomic_comp_swap:
5303       visit_image_atomic(ctx, instr);
5304       break;
5305    case nir_intrinsic_image_deref_size:
5306       visit_image_size(ctx, instr);
5307       break;
5308    case nir_intrinsic_load_ssbo:
5309       visit_load_ssbo(ctx, instr);
5310       break;
5311    case nir_intrinsic_store_ssbo:
5312       visit_store_ssbo(ctx, instr);
5313       break;
5314    case nir_intrinsic_load_global:
5315       visit_load_global(ctx, instr);
5316       break;
5317    case nir_intrinsic_store_global:
5318       visit_store_global(ctx, instr);
5319       break;
5320    case nir_intrinsic_ssbo_atomic_add:
5321    case nir_intrinsic_ssbo_atomic_imin:
5322    case nir_intrinsic_ssbo_atomic_umin:
5323    case nir_intrinsic_ssbo_atomic_imax:
5324    case nir_intrinsic_ssbo_atomic_umax:
5325    case nir_intrinsic_ssbo_atomic_and:
5326    case nir_intrinsic_ssbo_atomic_or:
5327    case nir_intrinsic_ssbo_atomic_xor:
5328    case nir_intrinsic_ssbo_atomic_exchange:
5329    case nir_intrinsic_ssbo_atomic_comp_swap:
5330       visit_atomic_ssbo(ctx, instr);
5331       break;
5332    case nir_intrinsic_load_scratch:
5333       visit_load_scratch(ctx, instr);
5334       break;
5335    case nir_intrinsic_store_scratch:
5336       visit_store_scratch(ctx, instr);
5337       break;
5338    case nir_intrinsic_get_buffer_size:
5339       visit_get_buffer_size(ctx, instr);
5340       break;
5341    case nir_intrinsic_barrier: {
5342       unsigned* bsize = ctx->program->info->cs.block_size;
5343       unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
5344       if (workgroup_size > 64)
5345          bld.sopp(aco_opcode::s_barrier);
5346       break;
5347    }
5348    case nir_intrinsic_group_memory_barrier:
5349    case nir_intrinsic_memory_barrier:
5350    case nir_intrinsic_memory_barrier_atomic_counter:
5351    case nir_intrinsic_memory_barrier_buffer:
5352    case nir_intrinsic_memory_barrier_image:
5353    case nir_intrinsic_memory_barrier_shared:
5354       emit_memory_barrier(ctx, instr);
5355       break;
5356    case nir_intrinsic_load_num_work_groups:
5357    case nir_intrinsic_load_work_group_id:
5358    case nir_intrinsic_load_local_invocation_id: {
5359       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5360       Temp* ids;
5361       if (instr->intrinsic == nir_intrinsic_load_num_work_groups)
5362          ids = ctx->num_workgroups;
5363       else if (instr->intrinsic == nir_intrinsic_load_work_group_id)
5364          ids = ctx->workgroup_ids;
5365       else
5366          ids = ctx->local_invocation_ids;
5367       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5368                  ids[0].id() ? Operand(ids[0]) : Operand(1u),
5369                  ids[1].id() ? Operand(ids[1]) : Operand(1u),
5370                  ids[2].id() ? Operand(ids[2]) : Operand(1u));
5371       emit_split_vector(ctx, dst, 3);
5372       break;
5373    }
5374    case nir_intrinsic_load_local_invocation_index: {
5375       Temp id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
5376                          bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5377       Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u), ctx->tg_size);
5378       bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
5379       break;
5380    }
5381    case nir_intrinsic_load_subgroup_id: {
5382       if (ctx->stage == compute_cs) {
5383          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u), ctx->tg_size);
5384          bld.sop2(aco_opcode::s_lshr_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), tg_num, Operand(0x6u));
5385       } else {
5386          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
5387       }
5388       break;
5389    }
5390    case nir_intrinsic_load_subgroup_invocation: {
5391       bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand((uint32_t) -1),
5392                bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5393       break;
5394    }
5395    case nir_intrinsic_load_num_subgroups: {
5396       if (ctx->stage == compute_cs)
5397          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu), ctx->tg_size);
5398       else
5399          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
5400       break;
5401    }
5402    case nir_intrinsic_ballot: {
5403       Definition tmp = bld.def(s2);
5404       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5405       if (instr->src[0].ssa->bit_size == 1 && src.regClass() == s2) {
5406          bld.sop2(aco_opcode::s_and_b64, tmp, bld.def(s1, scc), Operand(exec, s2), src);
5407       } else if (instr->src[0].ssa->bit_size == 1 && src.regClass() == s1) {
5408          bld.sop2(aco_opcode::s_cselect_b64, tmp, Operand(exec, s2), Operand(0u), bld.scc(src));
5409       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
5410          bld.vopc(aco_opcode::v_cmp_lg_u32, tmp, Operand(0u), src);
5411       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
5412          bld.vopc(aco_opcode::v_cmp_lg_u64, tmp, Operand(0u), src);
5413       } else {
5414          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5415          nir_print_instr(&instr->instr, stderr);
5416          fprintf(stderr, "\n");
5417       }
5418       emit_wqm(ctx, tmp.getTemp(), get_ssa_temp(ctx, &instr->dest.ssa));
5419       break;
5420    }
5421    case nir_intrinsic_shuffle: {
5422       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5423       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5424          emit_uniform_subgroup(ctx, instr, src);
5425       } else {
5426          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
5427          assert(tid.regClass() == v1);
5428          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5429          if (src.regClass() == v1) {
5430             tid = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), tid);
5431             emit_wqm(ctx, bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), tid, src), dst);
5432          } else if (src.regClass() == v2) {
5433             tid = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), tid);
5434
5435             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5436             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5437             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), tid, lo));
5438             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), tid, hi));
5439             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5440             emit_split_vector(ctx, dst, 2);
5441          } else if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5442             Temp tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
5443             tmp = emit_extract_vector(ctx, tmp, 0, v1);
5444             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
5445             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp), dst);
5446          } else {
5447             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5448             nir_print_instr(&instr->instr, stderr);
5449             fprintf(stderr, "\n");
5450          }
5451       }
5452       break;
5453    }
5454    case nir_intrinsic_load_sample_id: {
5455       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5456                ctx->fs_inputs[ancillary], Operand(8u), Operand(4u));
5457       break;
5458    }
5459    case nir_intrinsic_load_sample_mask_in: {
5460       visit_load_sample_mask_in(ctx, instr);
5461       break;
5462    }
5463    case nir_intrinsic_read_first_invocation: {
5464       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5465       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5466       if (src.regClass() == v1) {
5467          emit_wqm(ctx,
5468                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
5469                   dst);
5470       } else if (src.regClass() == v2) {
5471          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5472          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5473          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
5474          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
5475          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5476          emit_split_vector(ctx, dst, 2);
5477       } else if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5478          emit_wqm(ctx,
5479                   bld.sopc(aco_opcode::s_bitcmp1_b64, bld.def(s1, scc), src,
5480                            bld.sop1(aco_opcode::s_ff1_i32_b64, bld.def(s1), Operand(exec, s2))),
5481                   dst);
5482       } else if (src.regClass() == s1) {
5483          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5484       } else if (src.regClass() == s2) {
5485          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5486       } else {
5487          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5488          nir_print_instr(&instr->instr, stderr);
5489          fprintf(stderr, "\n");
5490       }
5491       break;
5492    }
5493    case nir_intrinsic_read_invocation: {
5494       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5495       Temp lane = get_ssa_temp(ctx, instr->src[1].ssa);
5496       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5497       assert(lane.regClass() == s1);
5498       if (src.regClass() == v1) {
5499          emit_wqm(ctx, bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), src, lane), dst);
5500       } else if (src.regClass() == v2) {
5501          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5502          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5503          lo = emit_wqm(ctx, bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), lo, lane));
5504          hi = emit_wqm(ctx, bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), hi, lane));
5505          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5506          emit_split_vector(ctx, dst, 2);
5507       } else if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5508          emit_wqm(ctx, bld.sopc(aco_opcode::s_bitcmp1_b64, bld.def(s1, scc), src, lane), dst);
5509       } else if (src.regClass() == s1) {
5510          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5511       } else if (src.regClass() == s2) {
5512          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5513       } else {
5514          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5515          nir_print_instr(&instr->instr, stderr);
5516          fprintf(stderr, "\n");
5517       }
5518       break;
5519    }
5520    case nir_intrinsic_vote_all: {
5521       Temp src = as_divergent_bool(ctx, get_ssa_temp(ctx, instr->src[0].ssa), false);
5522       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5523       assert(src.regClass() == s2);
5524       assert(dst.regClass() == s1);
5525
5526       Definition tmp = bld.def(s1);
5527       bld.sopc(aco_opcode::s_cmp_eq_u64, bld.scc(tmp),
5528                bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2)),
5529                Operand(exec, s2));
5530       emit_wqm(ctx, tmp.getTemp(), dst);
5531       break;
5532    }
5533    case nir_intrinsic_vote_any: {
5534       Temp src = as_divergent_bool(ctx, get_ssa_temp(ctx, instr->src[0].ssa), false);
5535       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5536       assert(src.regClass() == s2);
5537       assert(dst.regClass() == s1);
5538
5539       Definition tmp = bld.def(s1);
5540       bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.scc(tmp), src, Operand(exec, s2));
5541       emit_wqm(ctx, tmp.getTemp(), dst);
5542       break;
5543    }
5544    case nir_intrinsic_reduce:
5545    case nir_intrinsic_inclusive_scan:
5546    case nir_intrinsic_exclusive_scan: {
5547       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5548       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5549       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
5550       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
5551          nir_intrinsic_cluster_size(instr) : 0;
5552       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : 64, 64));
5553
5554       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
5555          emit_uniform_subgroup(ctx, instr, src);
5556       } else if (instr->dest.ssa.bit_size == 1) {
5557          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
5558             op = nir_op_iand;
5559          else if (op == nir_op_iadd)
5560             op = nir_op_ixor;
5561          else if (op == nir_op_umax || op == nir_op_imax)
5562             op = nir_op_ior;
5563          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
5564
5565          switch (instr->intrinsic) {
5566          case nir_intrinsic_reduce:
5567             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
5568             break;
5569          case nir_intrinsic_exclusive_scan:
5570             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
5571             break;
5572          case nir_intrinsic_inclusive_scan:
5573             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
5574             break;
5575          default:
5576             assert(false);
5577          }
5578       } else if (cluster_size == 1) {
5579          bld.copy(Definition(dst), src);
5580       } else {
5581          src = as_vgpr(ctx, src);
5582
5583          ReduceOp reduce_op;
5584          switch (op) {
5585          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5586             CASE(iadd)
5587             CASE(imul)
5588             CASE(fadd)
5589             CASE(fmul)
5590             CASE(imin)
5591             CASE(umin)
5592             CASE(fmin)
5593             CASE(imax)
5594             CASE(umax)
5595             CASE(fmax)
5596             CASE(iand)
5597             CASE(ior)
5598             CASE(ixor)
5599             default:
5600                unreachable("unknown reduction op");
5601          #undef CASE
5602          }
5603
5604          aco_opcode aco_op;
5605          switch (instr->intrinsic) {
5606             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
5607             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
5608             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
5609             default:
5610                unreachable("unknown reduce intrinsic");
5611          }
5612
5613          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
5614          reduce->operands[0] = Operand(src);
5615          // filled in by aco_reduce_assign.cpp, used internally as part of the
5616          // reduce sequence
5617          assert(dst.size() == 1 || dst.size() == 2);
5618          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
5619          reduce->operands[2] = Operand(v1.as_linear());
5620
5621          Temp tmp_dst = bld.tmp(dst.regClass());
5622          reduce->definitions[0] = Definition(tmp_dst);
5623          reduce->definitions[1] = bld.def(s2); // used internally
5624          reduce->definitions[2] = Definition();
5625          reduce->definitions[3] = Definition(scc, s1);
5626          reduce->definitions[4] = Definition();
5627          reduce->reduce_op = reduce_op;
5628          reduce->cluster_size = cluster_size;
5629          ctx->block->instructions.emplace_back(std::move(reduce));
5630
5631          emit_wqm(ctx, tmp_dst, dst);
5632       }
5633       break;
5634    }
5635    case nir_intrinsic_quad_broadcast: {
5636       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5637       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5638          emit_uniform_subgroup(ctx, instr, src);
5639       } else {
5640          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5641          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
5642          if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5643             uint32_t half_mask = 0x11111111u << lane;
5644             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
5645             Temp tmp = bld.tmp(s2);
5646             bld.sop1(aco_opcode::s_wqm_b64, Definition(tmp),
5647                      bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), mask_tmp,
5648                               bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2))));
5649             emit_wqm(ctx, tmp, dst);
5650          } else if (instr->dest.ssa.bit_size == 32) {
5651             emit_wqm(ctx,
5652                      bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src,
5653                                   dpp_quad_perm(lane, lane, lane, lane)),
5654                      dst);
5655          } else if (instr->dest.ssa.bit_size == 64) {
5656             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5657             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5658             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_quad_perm(lane, lane, lane, lane)));
5659             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_quad_perm(lane, lane, lane, lane)));
5660             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5661             emit_split_vector(ctx, dst, 2);
5662          } else {
5663             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5664             nir_print_instr(&instr->instr, stderr);
5665             fprintf(stderr, "\n");
5666          }
5667       }
5668       break;
5669    }
5670    case nir_intrinsic_quad_swap_horizontal:
5671    case nir_intrinsic_quad_swap_vertical:
5672    case nir_intrinsic_quad_swap_diagonal:
5673    case nir_intrinsic_quad_swizzle_amd: {
5674       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5675       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5676          emit_uniform_subgroup(ctx, instr, src);
5677          break;
5678       }
5679       uint16_t dpp_ctrl = 0;
5680       switch (instr->intrinsic) {
5681       case nir_intrinsic_quad_swap_horizontal:
5682          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
5683          break;
5684       case nir_intrinsic_quad_swap_vertical:
5685          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
5686          break;
5687       case nir_intrinsic_quad_swap_diagonal:
5688          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
5689          break;
5690       case nir_intrinsic_quad_swizzle_amd: {
5691          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
5692          break;
5693       }
5694       default:
5695          break;
5696       }
5697
5698       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5699       if (instr->dest.ssa.bit_size == 1 && src.regClass() == s2) {
5700          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
5701          src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5702          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), src);
5703          emit_wqm(ctx, tmp, dst);
5704       } else if (instr->dest.ssa.bit_size == 32) {
5705          Temp tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5706          emit_wqm(ctx, tmp, dst);
5707       } else if (instr->dest.ssa.bit_size == 64) {
5708          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5709          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5710          lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
5711          hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
5712          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5713          emit_split_vector(ctx, dst, 2);
5714       } else {
5715          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5716          nir_print_instr(&instr->instr, stderr);
5717          fprintf(stderr, "\n");
5718       }
5719       break;
5720    }
5721    case nir_intrinsic_masked_swizzle_amd: {
5722       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5723       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5724          emit_uniform_subgroup(ctx, instr, src);
5725          break;
5726       }
5727       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5728       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
5729       if (dst.regClass() == v1) {
5730          emit_wqm(ctx,
5731                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
5732                   dst);
5733       } else if (dst.regClass() == v2) {
5734          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5735          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5736          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
5737          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
5738          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5739          emit_split_vector(ctx, dst, 2);
5740       } else {
5741          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5742          nir_print_instr(&instr->instr, stderr);
5743          fprintf(stderr, "\n");
5744       }
5745       break;
5746    }
5747    case nir_intrinsic_write_invocation_amd: {
5748       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5749       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
5750       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
5751       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5752       if (dst.regClass() == v1) {
5753          /* src2 is ignored for writelane. RA assigns the same reg for dst */
5754          emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val, lane, src), dst);
5755       } else if (dst.regClass() == v2) {
5756          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
5757          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
5758          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
5759          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
5760          Temp lo = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_lo, lane, src_hi));
5761          Temp hi = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_hi, lane, src_hi));
5762          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5763          emit_split_vector(ctx, dst, 2);
5764       } else {
5765          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5766          nir_print_instr(&instr->instr, stderr);
5767          fprintf(stderr, "\n");
5768       }
5769       break;
5770    }
5771    case nir_intrinsic_mbcnt_amd: {
5772       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5773       RegClass rc = RegClass(src.type(), 1);
5774       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
5775       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
5776       Temp tmp = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), mask_lo, Operand(0u));
5777       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5778       Temp wqm_tmp = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), mask_hi, tmp);
5779       emit_wqm(ctx, wqm_tmp, dst);
5780       break;
5781    }
5782    case nir_intrinsic_load_helper_invocation: {
5783       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5784       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
5785       ctx->block->kind |= block_kind_needs_lowering;
5786       ctx->program->needs_exact = true;
5787       break;
5788    }
5789    case nir_intrinsic_is_helper_invocation: {
5790       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5791       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
5792       ctx->block->kind |= block_kind_needs_lowering;
5793       ctx->program->needs_exact = true;
5794       break;
5795    }
5796    case nir_intrinsic_demote:
5797       bld.pseudo(aco_opcode::p_demote_to_helper);
5798       ctx->block->kind |= block_kind_uses_demote;
5799       ctx->program->needs_exact = true;
5800       break;
5801    case nir_intrinsic_demote_if: {
5802       Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc),
5803                            as_divergent_bool(ctx, get_ssa_temp(ctx, instr->src[0].ssa), false),
5804                            Operand(exec, s2));
5805       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
5806       ctx->block->kind |= block_kind_uses_demote;
5807       ctx->program->needs_exact = true;
5808       break;
5809    }
5810    case nir_intrinsic_first_invocation: {
5811       emit_wqm(ctx, bld.sop1(aco_opcode::s_ff1_i32_b64, bld.def(s1), Operand(exec, s2)),
5812                get_ssa_temp(ctx, &instr->dest.ssa));
5813       break;
5814    }
5815    case nir_intrinsic_shader_clock:
5816       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
5817       break;
5818    case nir_intrinsic_load_vertex_id_zero_base: {
5819       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5820       bld.copy(Definition(dst), ctx->vertex_id);
5821       break;
5822    }
5823    case nir_intrinsic_load_first_vertex: {
5824       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5825       bld.copy(Definition(dst), ctx->base_vertex);
5826       break;
5827    }
5828    case nir_intrinsic_load_base_instance: {
5829       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5830       bld.copy(Definition(dst), ctx->start_instance);
5831       break;
5832    }
5833    case nir_intrinsic_load_instance_id: {
5834       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5835       bld.copy(Definition(dst), ctx->instance_id);
5836       break;
5837    }
5838    case nir_intrinsic_load_draw_id: {
5839       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5840       bld.copy(Definition(dst), ctx->draw_id);
5841       break;
5842    }
5843    default:
5844       fprintf(stderr, "Unimplemented intrinsic instr: ");
5845       nir_print_instr(&instr->instr, stderr);
5846       fprintf(stderr, "\n");
5847       abort();
5848
5849       break;
5850    }
5851 }
5852
5853
5854 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
5855                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
5856                     enum glsl_base_type *stype)
5857 {
5858    nir_deref_instr *texture_deref_instr = NULL;
5859    nir_deref_instr *sampler_deref_instr = NULL;
5860    int plane = -1;
5861
5862    for (unsigned i = 0; i < instr->num_srcs; i++) {
5863       switch (instr->src[i].src_type) {
5864       case nir_tex_src_texture_deref:
5865          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
5866          break;
5867       case nir_tex_src_sampler_deref:
5868          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
5869          break;
5870       case nir_tex_src_plane:
5871          plane = nir_src_as_int(instr->src[i].src);
5872          break;
5873       default:
5874          break;
5875       }
5876    }
5877
5878    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
5879
5880    if (!sampler_deref_instr)
5881       sampler_deref_instr = texture_deref_instr;
5882
5883    if (plane >= 0) {
5884       assert(instr->op != nir_texop_txf_ms &&
5885              instr->op != nir_texop_samples_identical);
5886       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
5887       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
5888    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
5889       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
5890    } else {
5891       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
5892    }
5893    if (samp_ptr) {
5894       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
5895       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
5896          fprintf(stderr, "Unimplemented sampler descriptor: ");
5897          nir_print_instr(&instr->instr, stderr);
5898          fprintf(stderr, "\n");
5899          abort();
5900          // TODO: build samp_ptr = and(samp_ptr, res_ptr)
5901       }
5902    }
5903    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
5904                      instr->op == nir_texop_samples_identical))
5905       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
5906 }
5907
5908 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
5909                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
5910 {
5911    Builder bld(ctx->program, ctx->block);
5912
5913    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
5914    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
5915    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
5916
5917    Operand neg_one(0xbf800000u);
5918    Operand one(0x3f800000u);
5919    Operand two(0x40000000u);
5920    Operand four(0x40800000u);
5921
5922    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), ma);
5923    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
5924    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
5925
5926    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), four, id);
5927    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(s2), two, id);
5928    is_ma_y = bld.sop2(aco_opcode::s_andn2_b64, bld.hint_vcc(bld.def(s2)), is_ma_y, is_ma_z);
5929    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), is_ma_z, is_ma_y);
5930
5931    // select sc
5932    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
5933    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
5934                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
5935                        one, is_ma_y);
5936    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
5937
5938    // select tc
5939    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
5940    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
5941    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
5942
5943    // select ma
5944    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
5945                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
5946                   deriv_z, is_ma_z);
5947    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
5948    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
5949 }
5950
5951 void prepare_cube_coords(isel_context *ctx, Temp* coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
5952 {
5953    Builder bld(ctx->program, ctx->block);
5954    Temp coord_args[4], ma, tc, sc, id;
5955    for (unsigned i = 0; i < (is_array ? 4 : 3); i++)
5956       coord_args[i] = emit_extract_vector(ctx, *coords, i, v1);
5957
5958    if (is_array) {
5959       coord_args[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_args[3]);
5960
5961       // see comment in ac_prepare_cube_coords()
5962       if (ctx->options->chip_class <= GFX8)
5963          coord_args[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coord_args[3]);
5964    }
5965
5966    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
5967
5968    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
5969    vop3a->operands[0] = Operand(ma);
5970    vop3a->abs[0] = true;
5971    Temp invma = bld.tmp(v1);
5972    vop3a->definitions[0] = Definition(invma);
5973    ctx->block->instructions.emplace_back(std::move(vop3a));
5974
5975    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
5976    if (!is_deriv)
5977       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
5978
5979    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
5980    if (!is_deriv)
5981       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
5982
5983    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
5984
5985    if (is_deriv) {
5986       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
5987       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
5988
5989       for (unsigned i = 0; i < 2; i++) {
5990          // see comment in ac_prepare_cube_coords()
5991          Temp deriv_ma;
5992          Temp deriv_sc, deriv_tc;
5993          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
5994                            &deriv_ma, &deriv_sc, &deriv_tc);
5995
5996          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
5997
5998          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
5999                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
6000                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
6001          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6002                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
6003                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
6004          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
6005       }
6006
6007       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
6008       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
6009    }
6010
6011    if (is_array)
6012       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coord_args[3], id, Operand(0x41000000u/*8.0*/));
6013    *coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), sc, tc, id);
6014
6015 }
6016
6017 Temp apply_round_slice(isel_context *ctx, Temp coords, unsigned idx)
6018 {
6019    Temp coord_vec[3];
6020    for (unsigned i = 0; i < coords.size(); i++)
6021       coord_vec[i] = emit_extract_vector(ctx, coords, i, v1);
6022
6023    Builder bld(ctx->program, ctx->block);
6024    coord_vec[idx] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_vec[idx]);
6025
6026    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6027    for (unsigned i = 0; i < coords.size(); i++)
6028       vec->operands[i] = Operand(coord_vec[i]);
6029    Temp res = bld.tmp(RegType::vgpr, coords.size());
6030    vec->definitions[0] = Definition(res);
6031    ctx->block->instructions.emplace_back(std::move(vec));
6032    return res;
6033 }
6034
6035 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
6036 {
6037    if (vec->parent_instr->type != nir_instr_type_alu)
6038       return;
6039    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
6040    if (vec_instr->op != nir_op_vec(vec->num_components))
6041       return;
6042
6043    for (unsigned i = 0; i < vec->num_components; i++) {
6044       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
6045               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
6046    }
6047 }
6048
6049 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
6050 {
6051    Builder bld(ctx->program, ctx->block);
6052    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
6053         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
6054    Temp resource, sampler, fmask_ptr, bias = Temp(), coords, compare = Temp(), sample_index = Temp(),
6055         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp(), derivs = Temp();
6056    nir_const_value *sample_index_cv = NULL;
6057    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
6058    enum glsl_base_type stype;
6059    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
6060
6061    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
6062                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
6063    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
6064                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
6065
6066    for (unsigned i = 0; i < instr->num_srcs; i++) {
6067       switch (instr->src[i].src_type) {
6068       case nir_tex_src_coord:
6069          coords = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[i].src.ssa));
6070          break;
6071       case nir_tex_src_bias:
6072          if (instr->op == nir_texop_txb) {
6073             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
6074             has_bias = true;
6075          }
6076          break;
6077       case nir_tex_src_lod: {
6078          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
6079
6080          if (val && val->f32 <= 0.0) {
6081             level_zero = true;
6082          } else {
6083             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
6084             has_lod = true;
6085          }
6086          break;
6087       }
6088       case nir_tex_src_comparator:
6089          if (instr->is_shadow) {
6090             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
6091             has_compare = true;
6092          }
6093          break;
6094       case nir_tex_src_offset:
6095          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
6096          get_const_vec(instr->src[i].src.ssa, const_offset);
6097          has_offset = true;
6098          break;
6099       case nir_tex_src_ddx:
6100          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
6101          has_ddx = true;
6102          break;
6103       case nir_tex_src_ddy:
6104          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
6105          has_ddy = true;
6106          break;
6107       case nir_tex_src_ms_index:
6108          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
6109          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
6110          has_sample_index = true;
6111          break;
6112       case nir_tex_src_texture_offset:
6113       case nir_tex_src_sampler_offset:
6114       default:
6115          break;
6116       }
6117    }
6118 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6119    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
6120       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
6121
6122    if (instr->op == nir_texop_texture_samples) {
6123       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
6124
6125       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
6126       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
6127       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6128       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
6129
6130       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6131                samples, Operand(1u), bld.scc(is_msaa));
6132       return;
6133    }
6134
6135    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
6136       aco_ptr<Instruction> tmp_instr;
6137       Temp acc, pack = Temp();
6138
6139       uint32_t pack_const = 0;
6140       for (unsigned i = 0; i < offset.size(); i++) {
6141          if (!const_offset[i])
6142             continue;
6143          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
6144       }
6145
6146       if (offset.type() == RegType::sgpr) {
6147          for (unsigned i = 0; i < offset.size(); i++) {
6148             if (const_offset[i])
6149                continue;
6150
6151             acc = emit_extract_vector(ctx, offset, i, s1);
6152             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
6153
6154             if (i) {
6155                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
6156             }
6157
6158             if (pack == Temp()) {
6159                pack = acc;
6160             } else {
6161                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
6162             }
6163          }
6164
6165          if (pack_const && pack != Temp())
6166             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
6167       } else {
6168          for (unsigned i = 0; i < offset.size(); i++) {
6169             if (const_offset[i])
6170                continue;
6171
6172             acc = emit_extract_vector(ctx, offset, i, v1);
6173             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
6174
6175             if (i) {
6176                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
6177             }
6178
6179             if (pack == Temp()) {
6180                pack = acc;
6181             } else {
6182                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
6183             }
6184          }
6185
6186          if (pack_const && pack != Temp())
6187             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
6188       }
6189       if (pack_const && pack == Temp())
6190          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
6191       else if (pack == Temp())
6192          has_offset = false;
6193       else
6194          offset = pack;
6195    }
6196
6197    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
6198       prepare_cube_coords(ctx, &coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
6199
6200    /* pack derivatives */
6201    if (has_ddx || has_ddy) {
6202       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class >= GFX9) {
6203          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(v4),
6204                              ddx, Operand(0u), ddy, Operand(0u));
6205       } else {
6206          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, ddx.size() + ddy.size()), ddx, ddy);
6207       }
6208       has_derivs = true;
6209    }
6210
6211    if (instr->coord_components > 1 &&
6212        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6213        instr->is_array &&
6214        instr->op != nir_texop_txf)
6215       coords = apply_round_slice(ctx, coords, 1);
6216
6217    if (instr->coord_components > 2 &&
6218       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
6219        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6220        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
6221        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6222        instr->is_array &&
6223        instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms)
6224       coords = apply_round_slice(ctx, coords, 2);
6225
6226    if (ctx->options->chip_class >= GFX9 &&
6227        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6228        instr->op != nir_texop_lod && instr->coord_components) {
6229       assert(coords.size() > 0 && coords.size() < 3);
6230
6231       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size() + 1, 1)};
6232       vec->operands[0] = Operand(emit_extract_vector(ctx, coords, 0, v1));
6233       vec->operands[1] = instr->op == nir_texop_txf ? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6234       if (coords.size() > 1)
6235          vec->operands[2] = Operand(emit_extract_vector(ctx, coords, 1, v1));
6236       coords = bld.tmp(RegType::vgpr, coords.size() + 1);
6237       vec->definitions[0] = Definition(coords);
6238       ctx->block->instructions.emplace_back(std::move(vec));
6239    }
6240
6241    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
6242
6243    if (instr->op == nir_texop_samples_identical)
6244       resource = fmask_ptr;
6245
6246    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6247              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6248             instr->op != nir_texop_txs) {
6249       assert(has_sample_index);
6250       Operand op(sample_index);
6251       if (sample_index_cv)
6252          op = Operand(sample_index_cv->u32);
6253       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
6254    }
6255
6256    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
6257       Temp split_coords[coords.size()];
6258       emit_split_vector(ctx, coords, coords.size());
6259       for (unsigned i = 0; i < coords.size(); i++)
6260          split_coords[i] = emit_extract_vector(ctx, coords, i, v1);
6261
6262       unsigned i = 0;
6263       for (; i < std::min(offset.size(), instr->coord_components); i++) {
6264          Temp off = emit_extract_vector(ctx, offset, i, v1);
6265          split_coords[i] = bld.vadd32(bld.def(v1), split_coords[i], off);
6266       }
6267
6268       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6269       for (unsigned i = 0; i < coords.size(); i++)
6270          vec->operands[i] = Operand(split_coords[i]);
6271       coords = bld.tmp(coords.regClass());
6272       vec->definitions[0] = Definition(coords);
6273       ctx->block->instructions.emplace_back(std::move(vec));
6274
6275       has_offset = false;
6276    }
6277
6278    /* Build tex instruction */
6279    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
6280    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
6281                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
6282                   : 0;
6283    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6284    Temp tmp_dst = dst;
6285
6286    /* gather4 selects the component by dmask and always returns vec4 */
6287    if (instr->op == nir_texop_tg4) {
6288       assert(instr->dest.ssa.num_components == 4);
6289       if (instr->is_shadow)
6290          dmask = 1;
6291       else
6292          dmask = 1 << instr->component;
6293       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
6294          tmp_dst = bld.tmp(v4);
6295    } else if (instr->op == nir_texop_samples_identical) {
6296       tmp_dst = bld.tmp(v1);
6297    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
6298       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
6299    }
6300
6301    aco_ptr<MIMG_instruction> tex;
6302    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
6303       if (!has_lod)
6304          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6305
6306       bool div_by_6 = instr->op == nir_texop_txs &&
6307                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
6308                       instr->is_array &&
6309                       (dmask & (1 << 2));
6310       if (tmp_dst.id() == dst.id() && div_by_6)
6311          tmp_dst = bld.tmp(tmp_dst.regClass());
6312
6313       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6314       tex->operands[0] = Operand(as_vgpr(ctx,lod));
6315       tex->operands[1] = Operand(resource);
6316       if (ctx->options->chip_class >= GFX9 &&
6317           instr->op == nir_texop_txs &&
6318           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6319           instr->is_array) {
6320          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
6321       } else if (instr->op == nir_texop_query_levels) {
6322          tex->dmask = 1 << 3;
6323       } else {
6324          tex->dmask = dmask;
6325       }
6326       tex->da = da;
6327       tex->definitions[0] = Definition(tmp_dst);
6328       tex->dim = dim;
6329       tex->can_reorder = true;
6330       ctx->block->instructions.emplace_back(std::move(tex));
6331
6332       if (div_by_6) {
6333          /* divide 3rd value by 6 by multiplying with magic number */
6334          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6335          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
6336          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
6337          assert(instr->dest.ssa.num_components == 3);
6338          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
6339          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6340                               emit_extract_vector(ctx, tmp_dst, 0, v1),
6341                               emit_extract_vector(ctx, tmp_dst, 1, v1),
6342                               by_6);
6343
6344       }
6345
6346       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6347       return;
6348    }
6349
6350    Temp tg4_compare_cube_wa64 = Temp();
6351
6352    if (tg4_integer_workarounds) {
6353       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6354       tex->operands[0] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6355       tex->operands[1] = Operand(resource);
6356       tex->dim = dim;
6357       tex->dmask = 0x3;
6358       tex->da = da;
6359       Temp size = bld.tmp(v2);
6360       tex->definitions[0] = Definition(size);
6361       tex->can_reorder = true;
6362       ctx->block->instructions.emplace_back(std::move(tex));
6363       emit_split_vector(ctx, size, size.size());
6364
6365       Temp half_texel[2];
6366       for (unsigned i = 0; i < 2; i++) {
6367          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
6368          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
6369          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
6370          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
6371       }
6372
6373       Temp orig_coords[2] = {
6374          emit_extract_vector(ctx, coords, 0, v1),
6375          emit_extract_vector(ctx, coords, 1, v1)};
6376       Temp new_coords[2] = {
6377          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[0], half_texel[0]),
6378          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[1], half_texel[1])
6379       };
6380
6381       if (tg4_integer_cube_workaround) {
6382          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6383          Temp desc[resource.size()];
6384          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
6385                                                                            Format::PSEUDO, 1, resource.size())};
6386          split->operands[0] = Operand(resource);
6387          for (unsigned i = 0; i < resource.size(); i++) {
6388             desc[i] = bld.tmp(s1);
6389             split->definitions[i] = Definition(desc[i]);
6390          }
6391          ctx->block->instructions.emplace_back(std::move(split));
6392
6393          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
6394          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
6395                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
6396
6397          Temp nfmt;
6398          if (stype == GLSL_TYPE_UINT) {
6399             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6400                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
6401                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
6402                             bld.scc(compare_cube_wa));
6403          } else {
6404             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6405                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
6406                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
6407                             bld.scc(compare_cube_wa));
6408          }
6409          tg4_compare_cube_wa64 = as_divergent_bool(ctx, compare_cube_wa, true);
6410          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
6411
6412          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
6413                             Operand((uint32_t)C_008F14_NUM_FORMAT));
6414          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
6415
6416          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6417                                                                          Format::PSEUDO, resource.size(), 1)};
6418          for (unsigned i = 0; i < resource.size(); i++)
6419             vec->operands[i] = Operand(desc[i]);
6420          resource = bld.tmp(resource.regClass());
6421          vec->definitions[0] = Definition(resource);
6422          ctx->block->instructions.emplace_back(std::move(vec));
6423
6424          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6425                                   new_coords[0], orig_coords[0], tg4_compare_cube_wa64);
6426          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6427                                   new_coords[1], orig_coords[1], tg4_compare_cube_wa64);
6428       }
6429
6430       if (coords.size() == 3) {
6431          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3),
6432                              new_coords[0], new_coords[1],
6433                              emit_extract_vector(ctx, coords, 2, v1));
6434       } else {
6435          assert(coords.size() == 2);
6436          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2),
6437                              new_coords[0], new_coords[1]);
6438       }
6439    }
6440
6441    if (!(has_ddx && has_ddy) && !has_lod && !level_zero &&
6442        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
6443        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
6444       coords = emit_wqm(ctx, coords, bld.tmp(coords.regClass()), true);
6445
6446    std::vector<Operand> args;
6447    if (has_offset)
6448       args.emplace_back(Operand(offset));
6449    if (has_bias)
6450       args.emplace_back(Operand(bias));
6451    if (has_compare)
6452       args.emplace_back(Operand(compare));
6453    if (has_derivs)
6454       args.emplace_back(Operand(derivs));
6455    args.emplace_back(Operand(coords));
6456    if (has_sample_index)
6457       args.emplace_back(Operand(sample_index));
6458    if (has_lod)
6459       args.emplace_back(lod);
6460
6461    Operand arg;
6462    if (args.size() > 1) {
6463       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
6464       unsigned size = 0;
6465       for (unsigned i = 0; i < args.size(); i++) {
6466          size += args[i].size();
6467          vec->operands[i] = args[i];
6468       }
6469       RegClass rc = RegClass(RegType::vgpr, size);
6470       Temp tmp = bld.tmp(rc);
6471       vec->definitions[0] = Definition(tmp);
6472       ctx->block->instructions.emplace_back(std::move(vec));
6473       arg = Operand(tmp);
6474    } else {
6475       assert(args[0].isTemp());
6476       arg = Operand(as_vgpr(ctx, args[0].getTemp()));
6477    }
6478
6479    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
6480       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6481
6482       assert(coords.size() == 1);
6483       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
6484       aco_opcode op;
6485       switch (last_bit) {
6486       case 1:
6487          op = aco_opcode::buffer_load_format_x; break;
6488       case 2:
6489          op = aco_opcode::buffer_load_format_xy; break;
6490       case 3:
6491          op = aco_opcode::buffer_load_format_xyz; break;
6492       case 4:
6493          op = aco_opcode::buffer_load_format_xyzw; break;
6494       default:
6495          unreachable("Tex instruction loads more than 4 components.");
6496       }
6497
6498       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6499       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
6500          tmp_dst = dst;
6501       else
6502          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
6503
6504       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
6505       mubuf->operands[0] = Operand(coords);
6506       mubuf->operands[1] = Operand(resource);
6507       mubuf->operands[2] = Operand((uint32_t) 0);
6508       mubuf->definitions[0] = Definition(tmp_dst);
6509       mubuf->idxen = true;
6510       mubuf->can_reorder = true;
6511       ctx->block->instructions.emplace_back(std::move(mubuf));
6512
6513       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
6514       return;
6515    }
6516
6517
6518    if (instr->op == nir_texop_txf ||
6519        instr->op == nir_texop_txf_ms ||
6520        instr->op == nir_texop_samples_identical) {
6521       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
6522       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 2, 1));
6523       tex->operands[0] = Operand(arg);
6524       tex->operands[1] = Operand(resource);
6525       tex->dim = dim;
6526       tex->dmask = dmask;
6527       tex->unrm = true;
6528       tex->da = da;
6529       tex->definitions[0] = Definition(tmp_dst);
6530       tex->can_reorder = true;
6531       ctx->block->instructions.emplace_back(std::move(tex));
6532
6533       if (instr->op == nir_texop_samples_identical) {
6534          assert(dmask == 1 && dst.regClass() == v1);
6535          assert(dst.id() != tmp_dst.id());
6536
6537          Temp tmp = bld.tmp(s2);
6538          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
6539          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
6540
6541       } else {
6542          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6543       }
6544       return;
6545    }
6546
6547    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6548    aco_opcode opcode = aco_opcode::image_sample;
6549    if (has_offset) { /* image_sample_*_o */
6550       if (has_compare) {
6551          opcode = aco_opcode::image_sample_c_o;
6552          if (has_derivs)
6553             opcode = aco_opcode::image_sample_c_d_o;
6554          if (has_bias)
6555             opcode = aco_opcode::image_sample_c_b_o;
6556          if (level_zero)
6557             opcode = aco_opcode::image_sample_c_lz_o;
6558          if (has_lod)
6559             opcode = aco_opcode::image_sample_c_l_o;
6560       } else {
6561          opcode = aco_opcode::image_sample_o;
6562          if (has_derivs)
6563             opcode = aco_opcode::image_sample_d_o;
6564          if (has_bias)
6565             opcode = aco_opcode::image_sample_b_o;
6566          if (level_zero)
6567             opcode = aco_opcode::image_sample_lz_o;
6568          if (has_lod)
6569             opcode = aco_opcode::image_sample_l_o;
6570       }
6571    } else { /* no offset */
6572       if (has_compare) {
6573          opcode = aco_opcode::image_sample_c;
6574          if (has_derivs)
6575             opcode = aco_opcode::image_sample_c_d;
6576          if (has_bias)
6577             opcode = aco_opcode::image_sample_c_b;
6578          if (level_zero)
6579             opcode = aco_opcode::image_sample_c_lz;
6580          if (has_lod)
6581             opcode = aco_opcode::image_sample_c_l;
6582       } else {
6583          opcode = aco_opcode::image_sample;
6584          if (has_derivs)
6585             opcode = aco_opcode::image_sample_d;
6586          if (has_bias)
6587             opcode = aco_opcode::image_sample_b;
6588          if (level_zero)
6589             opcode = aco_opcode::image_sample_lz;
6590          if (has_lod)
6591             opcode = aco_opcode::image_sample_l;
6592       }
6593    }
6594
6595    if (instr->op == nir_texop_tg4) {
6596       if (has_offset) {
6597          opcode = aco_opcode::image_gather4_lz_o;
6598          if (has_compare)
6599             opcode = aco_opcode::image_gather4_c_lz_o;
6600       } else {
6601          opcode = aco_opcode::image_gather4_lz;
6602          if (has_compare)
6603             opcode = aco_opcode::image_gather4_c_lz;
6604       }
6605    } else if (instr->op == nir_texop_lod) {
6606       opcode = aco_opcode::image_get_lod;
6607    }
6608
6609    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
6610    tex->operands[0] = arg;
6611    tex->operands[1] = Operand(resource);
6612    tex->operands[2] = Operand(sampler);
6613    tex->dim = dim;
6614    tex->dmask = dmask;
6615    tex->da = da;
6616    tex->definitions[0] = Definition(tmp_dst);
6617    tex->can_reorder = true;
6618    ctx->block->instructions.emplace_back(std::move(tex));
6619
6620    if (tg4_integer_cube_workaround) {
6621       assert(tmp_dst.id() != dst.id());
6622       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
6623
6624       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6625       Temp val[4];
6626       for (unsigned i = 0; i < dst.size(); i++) {
6627          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
6628          Temp cvt_val;
6629          if (stype == GLSL_TYPE_UINT)
6630             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
6631          else
6632             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
6633          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
6634       }
6635       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
6636       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6637                            val[0], val[1], val[2], val[3]);
6638    }
6639    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
6640    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
6641
6642 }
6643
6644
6645 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
6646 {
6647    Temp tmp = get_ssa_temp(ctx, ssa);
6648    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
6649       return Operand(tmp.regClass());
6650    else
6651       return Operand(tmp);
6652 }
6653
6654 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
6655 {
6656    aco_ptr<Pseudo_instruction> phi;
6657    unsigned num_src = exec_list_length(&instr->srcs);
6658    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6659
6660    aco_opcode opcode = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index] ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
6661
6662    std::map<unsigned, nir_ssa_def*> phi_src;
6663    bool all_undef = true;
6664    nir_foreach_phi_src(src, instr) {
6665       phi_src[src->pred->index] = src->src.ssa;
6666       if (src->src.ssa->parent_instr->type != nir_instr_type_ssa_undef)
6667          all_undef = false;
6668    }
6669    if (all_undef) {
6670       Builder bld(ctx->program, ctx->block);
6671       if (dst.regClass() == s1) {
6672          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
6673       } else if (dst.regClass() == v1) {
6674          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
6675       } else {
6676          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
6677          for (unsigned i = 0; i < dst.size(); i++)
6678             vec->operands[i] = Operand(0u);
6679          vec->definitions[0] = Definition(dst);
6680          ctx->block->instructions.emplace_back(std::move(vec));
6681       }
6682       return;
6683    }
6684
6685    /* try to scalarize vector phis */
6686    if (dst.size() > 1) {
6687       // TODO: scalarize linear phis on divergent ifs
6688       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
6689       std::array<Temp, 4> new_vec;
6690       for (std::pair<const unsigned, nir_ssa_def*>& pair : phi_src) {
6691          Operand src = get_phi_operand(ctx, pair.second);
6692          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end()) {
6693             can_scalarize = false;
6694             break;
6695          }
6696       }
6697       if (can_scalarize) {
6698          unsigned num_components = instr->dest.ssa.num_components;
6699          assert(dst.size() % num_components == 0);
6700          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
6701
6702          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
6703          for (unsigned k = 0; k < num_components; k++) {
6704             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_src, 1));
6705             std::map<unsigned, nir_ssa_def*>::iterator it = phi_src.begin();
6706             for (unsigned i = 0; i < num_src; i++) {
6707                Operand src = get_phi_operand(ctx, it->second);
6708                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
6709                ++it;
6710             }
6711             Temp phi_dst = {ctx->program->allocateId(), rc};
6712             phi->definitions[0] = Definition(phi_dst);
6713             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
6714             new_vec[k] = phi_dst;
6715             vec->operands[k] = Operand(phi_dst);
6716          }
6717          vec->definitions[0] = Definition(dst);
6718          ctx->block->instructions.emplace_back(std::move(vec));
6719          ctx->allocated_vec.emplace(dst.id(), new_vec);
6720          return;
6721       }
6722    }
6723
6724    unsigned extra_src = 0;
6725    if (opcode == aco_opcode::p_linear_phi && (ctx->block->kind & block_kind_loop_exit) &&
6726        ctx->program->blocks[ctx->block->index-2].kind & block_kind_continue_or_break) {
6727       extra_src++;
6728    }
6729
6730    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_src + extra_src, 1));
6731
6732    /* if we have a linear phi on a divergent if, we know that one src is undef */
6733    if (opcode == aco_opcode::p_linear_phi && ctx->block->kind & block_kind_merge) {
6734       assert(extra_src == 0);
6735       Block* block;
6736       /* we place the phi either in the invert-block or in the current block */
6737       if (phi_src.begin()->second->parent_instr->type != nir_instr_type_ssa_undef) {
6738          assert((++phi_src.begin())->second->parent_instr->type == nir_instr_type_ssa_undef);
6739          Block& linear_else = ctx->program->blocks[ctx->block->linear_preds[1]];
6740          block = &ctx->program->blocks[linear_else.linear_preds[0]];
6741          assert(block->kind & block_kind_invert);
6742          phi->operands[0] = get_phi_operand(ctx, phi_src.begin()->second);
6743       } else {
6744          assert((++phi_src.begin())->second->parent_instr->type != nir_instr_type_ssa_undef);
6745          block = ctx->block;
6746          phi->operands[0] = get_phi_operand(ctx, (++phi_src.begin())->second);
6747       }
6748       phi->operands[1] = Operand(dst.regClass());
6749       phi->definitions[0] = Definition(dst);
6750       block->instructions.emplace(block->instructions.begin(), std::move(phi));
6751       return;
6752    }
6753
6754    std::map<unsigned, nir_ssa_def*>::iterator it = phi_src.begin();
6755    for (unsigned i = 0; i < num_src; i++) {
6756       phi->operands[i] = get_phi_operand(ctx, it->second);
6757       ++it;
6758    }
6759    for (unsigned i = 0; i < extra_src; i++)
6760       phi->operands[num_src + i] = Operand(dst.regClass());
6761    phi->definitions[0] = Definition(dst);
6762    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
6763 }
6764
6765
6766 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
6767 {
6768    Temp dst = get_ssa_temp(ctx, &instr->def);
6769
6770    assert(dst.type() == RegType::sgpr);
6771
6772    if (dst.size() == 1) {
6773       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
6774    } else {
6775       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
6776       for (unsigned i = 0; i < dst.size(); i++)
6777          vec->operands[i] = Operand(0u);
6778       vec->definitions[0] = Definition(dst);
6779       ctx->block->instructions.emplace_back(std::move(vec));
6780    }
6781 }
6782
6783 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
6784 {
6785    Builder bld(ctx->program, ctx->block);
6786    Block *logical_target;
6787    append_logical_end(ctx->block);
6788    unsigned idx = ctx->block->index;
6789
6790    switch (instr->type) {
6791    case nir_jump_break:
6792       logical_target = ctx->cf_info.parent_loop.exit;
6793       add_logical_edge(idx, logical_target);
6794       ctx->block->kind |= block_kind_break;
6795
6796       if (!ctx->cf_info.parent_if.is_divergent &&
6797           !ctx->cf_info.parent_loop.has_divergent_continue) {
6798          /* uniform break - directly jump out of the loop */
6799          ctx->block->kind |= block_kind_uniform;
6800          ctx->cf_info.has_branch = true;
6801          bld.branch(aco_opcode::p_branch);
6802          add_linear_edge(idx, logical_target);
6803          return;
6804       }
6805       ctx->cf_info.parent_loop.has_divergent_branch = true;
6806       break;
6807    case nir_jump_continue:
6808       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
6809       add_logical_edge(idx, logical_target);
6810       ctx->block->kind |= block_kind_continue;
6811
6812       if (ctx->cf_info.parent_if.is_divergent) {
6813          /* for potential uniform breaks after this continue,
6814             we must ensure that they are handled correctly */
6815          ctx->cf_info.parent_loop.has_divergent_continue = true;
6816          ctx->cf_info.parent_loop.has_divergent_branch = true;
6817       } else {
6818          /* uniform continue - directly jump to the loop header */
6819          ctx->block->kind |= block_kind_uniform;
6820          ctx->cf_info.has_branch = true;
6821          bld.branch(aco_opcode::p_branch);
6822          add_linear_edge(idx, logical_target);
6823          return;
6824       }
6825       break;
6826    default:
6827       fprintf(stderr, "Unknown NIR jump instr: ");
6828       nir_print_instr(&instr->instr, stderr);
6829       fprintf(stderr, "\n");
6830       abort();
6831    }
6832
6833    /* remove critical edges from linear CFG */
6834    bld.branch(aco_opcode::p_branch);
6835    Block* break_block = ctx->program->create_and_insert_block();
6836    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
6837    break_block->kind |= block_kind_uniform;
6838    add_linear_edge(idx, break_block);
6839    /* the loop_header pointer might be invalidated by this point */
6840    if (instr->type == nir_jump_continue)
6841       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
6842    add_linear_edge(break_block->index, logical_target);
6843    bld.reset(break_block);
6844    bld.branch(aco_opcode::p_branch);
6845
6846    Block* continue_block = ctx->program->create_and_insert_block();
6847    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
6848    add_linear_edge(idx, continue_block);
6849    append_logical_start(continue_block);
6850    ctx->block = continue_block;
6851    return;
6852 }
6853
6854 void visit_block(isel_context *ctx, nir_block *block)
6855 {
6856    nir_foreach_instr(instr, block) {
6857       switch (instr->type) {
6858       case nir_instr_type_alu:
6859          visit_alu_instr(ctx, nir_instr_as_alu(instr));
6860          break;
6861       case nir_instr_type_load_const:
6862          visit_load_const(ctx, nir_instr_as_load_const(instr));
6863          break;
6864       case nir_instr_type_intrinsic:
6865          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
6866          break;
6867       case nir_instr_type_tex:
6868          visit_tex(ctx, nir_instr_as_tex(instr));
6869          break;
6870       case nir_instr_type_phi:
6871          visit_phi(ctx, nir_instr_as_phi(instr));
6872          break;
6873       case nir_instr_type_ssa_undef:
6874          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
6875          break;
6876       case nir_instr_type_deref:
6877          break;
6878       case nir_instr_type_jump:
6879          visit_jump(ctx, nir_instr_as_jump(instr));
6880          break;
6881       default:
6882          fprintf(stderr, "Unknown NIR instr type: ");
6883          nir_print_instr(instr, stderr);
6884          fprintf(stderr, "\n");
6885          //abort();
6886       }
6887    }
6888 }
6889
6890
6891
6892 static void visit_loop(isel_context *ctx, nir_loop *loop)
6893 {
6894    append_logical_end(ctx->block);
6895    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
6896    Builder bld(ctx->program, ctx->block);
6897    bld.branch(aco_opcode::p_branch);
6898    unsigned loop_preheader_idx = ctx->block->index;
6899
6900    Block loop_exit = Block();
6901    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
6902    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
6903
6904    Block* loop_header = ctx->program->create_and_insert_block();
6905    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
6906    loop_header->kind |= block_kind_loop_header;
6907    add_edge(loop_preheader_idx, loop_header);
6908    ctx->block = loop_header;
6909
6910    /* emit loop body */
6911    unsigned loop_header_idx = loop_header->index;
6912    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
6913    append_logical_start(ctx->block);
6914    visit_cf_list(ctx, &loop->body);
6915
6916    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
6917    if (!ctx->cf_info.has_branch) {
6918       append_logical_end(ctx->block);
6919       if (ctx->cf_info.exec_potentially_empty) {
6920          /* Discards can result in code running with an empty exec mask.
6921           * This would result in divergent breaks not ever being taken. As a
6922           * workaround, break the loop when the loop mask is empty instead of
6923           * always continuing. */
6924          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
6925
6926          /* create "loop_almost_exit" to avoid critical edges */
6927          unsigned block_idx = ctx->block->index;
6928          Block *loop_almost_exit = ctx->program->create_and_insert_block();
6929          loop_almost_exit->loop_nest_depth = ctx->cf_info.loop_nest_depth;
6930          loop_almost_exit->kind = block_kind_uniform;
6931          bld.reset(loop_almost_exit);
6932          bld.branch(aco_opcode::p_branch);
6933
6934          add_linear_edge(block_idx, loop_almost_exit);
6935          add_linear_edge(loop_almost_exit->index, &loop_exit);
6936
6937          ctx->block = &ctx->program->blocks[block_idx];
6938       } else {
6939          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
6940       }
6941       if (!ctx->cf_info.parent_loop.has_divergent_branch)
6942          add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
6943       else
6944          add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
6945       bld.reset(ctx->block);
6946       bld.branch(aco_opcode::p_branch);
6947    }
6948
6949    /* fixup phis in loop header from unreachable blocks */
6950    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
6951       bool linear = ctx->cf_info.has_branch;
6952       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
6953       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
6954          if ((logical && instr->opcode == aco_opcode::p_phi) ||
6955              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
6956             /* the last operand should be the one that needs to be removed */
6957             instr->operands.pop_back();
6958          } else if (!is_phi(instr)) {
6959             break;
6960          }
6961       }
6962    }
6963
6964    ctx->cf_info.has_branch = false;
6965
6966    // TODO: if the loop has not a single exit, we must add one °°
6967    /* emit loop successor block */
6968    ctx->block = ctx->program->insert_block(std::move(loop_exit));
6969    append_logical_start(ctx->block);
6970
6971    #if 0
6972    // TODO: check if it is beneficial to not branch on continues
6973    /* trim linear phis in loop header */
6974    for (auto&& instr : loop_entry->instructions) {
6975       if (instr->opcode == aco_opcode::p_linear_phi) {
6976          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
6977          new_phi->definitions[0] = instr->definitions[0];
6978          for (unsigned i = 0; i < new_phi->operands.size(); i++)
6979             new_phi->operands[i] = instr->operands[i];
6980          /* check that the remaining operands are all the same */
6981          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
6982             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
6983          instr.swap(new_phi);
6984       } else if (instr->opcode == aco_opcode::p_phi) {
6985          continue;
6986       } else {
6987          break;
6988       }
6989    }
6990    #endif
6991 }
6992
6993 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
6994 {
6995    ic->cond = cond;
6996
6997    append_logical_end(ctx->block);
6998    ctx->block->kind |= block_kind_branch;
6999
7000    /* branch to linear then block */
7001    assert(cond.regClass() == s2);
7002    aco_ptr<Pseudo_branch_instruction> branch;
7003    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7004    branch->operands[0] = Operand(cond);
7005    ctx->block->instructions.push_back(std::move(branch));
7006
7007    ic->BB_if_idx = ctx->block->index;
7008    ic->BB_invert = Block();
7009    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7010    /* Invert blocks are intentionally not marked as top level because they
7011     * are not part of the logical cfg. */
7012    ic->BB_invert.kind |= block_kind_invert;
7013    ic->BB_endif = Block();
7014    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7015    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
7016
7017    ic->exec_potentially_empty_old = ctx->cf_info.exec_potentially_empty;
7018    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
7019    ctx->cf_info.parent_if.is_divergent = true;
7020    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7021
7022    /** emit logical then block */
7023    Block* BB_then_logical = ctx->program->create_and_insert_block();
7024    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7025    add_edge(ic->BB_if_idx, BB_then_logical);
7026    ctx->block = BB_then_logical;
7027    append_logical_start(BB_then_logical);
7028 }
7029
7030 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
7031 {
7032    Block *BB_then_logical = ctx->block;
7033    append_logical_end(BB_then_logical);
7034     /* branch from logical then block to invert block */
7035    aco_ptr<Pseudo_branch_instruction> branch;
7036    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7037    BB_then_logical->instructions.emplace_back(std::move(branch));
7038    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
7039    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7040       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
7041    BB_then_logical->kind |= block_kind_uniform;
7042    assert(!ctx->cf_info.has_branch);
7043    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7044    ctx->cf_info.parent_loop.has_divergent_branch = false;
7045
7046    /** emit linear then block */
7047    Block* BB_then_linear = ctx->program->create_and_insert_block();
7048    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7049    BB_then_linear->kind |= block_kind_uniform;
7050    add_linear_edge(ic->BB_if_idx, BB_then_linear);
7051    /* branch from linear then block to invert block */
7052    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7053    BB_then_linear->instructions.emplace_back(std::move(branch));
7054    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
7055
7056    /** emit invert merge block */
7057    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
7058    ic->invert_idx = ctx->block->index;
7059
7060    /* branch to linear else block (skip else) */
7061    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
7062    branch->operands[0] = Operand(ic->cond);
7063    ctx->block->instructions.push_back(std::move(branch));
7064
7065    ic->exec_potentially_empty_old |= ctx->cf_info.exec_potentially_empty;
7066    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7067
7068    /** emit logical else block */
7069    Block* BB_else_logical = ctx->program->create_and_insert_block();
7070    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7071    add_logical_edge(ic->BB_if_idx, BB_else_logical);
7072    add_linear_edge(ic->invert_idx, BB_else_logical);
7073    ctx->block = BB_else_logical;
7074    append_logical_start(BB_else_logical);
7075 }
7076
7077 static void end_divergent_if(isel_context *ctx, if_context *ic)
7078 {
7079    Block *BB_else_logical = ctx->block;
7080    append_logical_end(BB_else_logical);
7081
7082    /* branch from logical else block to endif block */
7083    aco_ptr<Pseudo_branch_instruction> branch;
7084    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7085    BB_else_logical->instructions.emplace_back(std::move(branch));
7086    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
7087    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7088       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
7089    BB_else_logical->kind |= block_kind_uniform;
7090
7091    assert(!ctx->cf_info.has_branch);
7092    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
7093
7094
7095    /** emit linear else block */
7096    Block* BB_else_linear = ctx->program->create_and_insert_block();
7097    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7098    BB_else_linear->kind |= block_kind_uniform;
7099    add_linear_edge(ic->invert_idx, BB_else_linear);
7100
7101    /* branch from linear else block to endif block */
7102    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7103    BB_else_linear->instructions.emplace_back(std::move(branch));
7104    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
7105
7106
7107    /** emit endif merge block */
7108    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
7109    append_logical_start(ctx->block);
7110
7111
7112    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
7113    ctx->cf_info.exec_potentially_empty |= ic->exec_potentially_empty_old;
7114    /* uniform control flow never has an empty exec-mask */
7115    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
7116       ctx->cf_info.exec_potentially_empty = false;
7117 }
7118
7119 static void visit_if(isel_context *ctx, nir_if *if_stmt)
7120 {
7121    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
7122    Builder bld(ctx->program, ctx->block);
7123    aco_ptr<Pseudo_branch_instruction> branch;
7124
7125    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
7126       /**
7127        * Uniform conditionals are represented in the following way*) :
7128        *
7129        * The linear and logical CFG:
7130        *                        BB_IF
7131        *                        /    \
7132        *       BB_THEN (logical)      BB_ELSE (logical)
7133        *                        \    /
7134        *                        BB_ENDIF
7135        *
7136        * *) Exceptions may be due to break and continue statements within loops
7137        *    If a break/continue happens within uniform control flow, it branches
7138        *    to the loop exit/entry block. Otherwise, it branches to the next
7139        *    merge block.
7140        **/
7141       append_logical_end(ctx->block);
7142       ctx->block->kind |= block_kind_uniform;
7143
7144       /* emit branch */
7145       if (cond.regClass() == s2) {
7146          // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7147          cond = as_uniform_bool(ctx, cond);
7148       }
7149       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7150       branch->operands[0] = Operand(cond);
7151       branch->operands[0].setFixed(scc);
7152       ctx->block->instructions.emplace_back(std::move(branch));
7153
7154       unsigned BB_if_idx = ctx->block->index;
7155       Block BB_endif = Block();
7156       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7157       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
7158
7159       /** emit then block */
7160       Block* BB_then = ctx->program->create_and_insert_block();
7161       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7162       add_edge(BB_if_idx, BB_then);
7163       append_logical_start(BB_then);
7164       ctx->block = BB_then;
7165       visit_cf_list(ctx, &if_stmt->then_list);
7166       BB_then = ctx->block;
7167       bool then_branch = ctx->cf_info.has_branch;
7168       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7169
7170       if (!then_branch) {
7171          append_logical_end(BB_then);
7172          /* branch from then block to endif block */
7173          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7174          BB_then->instructions.emplace_back(std::move(branch));
7175          add_linear_edge(BB_then->index, &BB_endif);
7176          if (!then_branch_divergent)
7177             add_logical_edge(BB_then->index, &BB_endif);
7178          BB_then->kind |= block_kind_uniform;
7179       }
7180
7181       ctx->cf_info.has_branch = false;
7182       ctx->cf_info.parent_loop.has_divergent_branch = false;
7183
7184       /** emit else block */
7185       Block* BB_else = ctx->program->create_and_insert_block();
7186       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7187       add_edge(BB_if_idx, BB_else);
7188       append_logical_start(BB_else);
7189       ctx->block = BB_else;
7190       visit_cf_list(ctx, &if_stmt->else_list);
7191       BB_else = ctx->block;
7192
7193       if (!ctx->cf_info.has_branch) {
7194          append_logical_end(BB_else);
7195          /* branch from then block to endif block */
7196          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7197          BB_else->instructions.emplace_back(std::move(branch));
7198          add_linear_edge(BB_else->index, &BB_endif);
7199          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7200             add_logical_edge(BB_else->index, &BB_endif);
7201          BB_else->kind |= block_kind_uniform;
7202       }
7203
7204       ctx->cf_info.has_branch &= then_branch;
7205       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
7206
7207       /** emit endif merge block */
7208       if (!ctx->cf_info.has_branch) {
7209          ctx->block = ctx->program->insert_block(std::move(BB_endif));
7210          append_logical_start(ctx->block);
7211       }
7212    } else { /* non-uniform condition */
7213       /**
7214        * To maintain a logical and linear CFG without critical edges,
7215        * non-uniform conditionals are represented in the following way*) :
7216        *
7217        * The linear CFG:
7218        *                        BB_IF
7219        *                        /    \
7220        *       BB_THEN (logical)      BB_THEN (linear)
7221        *                        \    /
7222        *                        BB_INVERT (linear)
7223        *                        /    \
7224        *       BB_ELSE (logical)      BB_ELSE (linear)
7225        *                        \    /
7226        *                        BB_ENDIF
7227        *
7228        * The logical CFG:
7229        *                        BB_IF
7230        *                        /    \
7231        *       BB_THEN (logical)      BB_ELSE (logical)
7232        *                        \    /
7233        *                        BB_ENDIF
7234        *
7235        * *) Exceptions may be due to break and continue statements within loops
7236        **/
7237
7238       if_context ic;
7239
7240       begin_divergent_if_then(ctx, &ic, cond);
7241       visit_cf_list(ctx, &if_stmt->then_list);
7242
7243       begin_divergent_if_else(ctx, &ic);
7244       visit_cf_list(ctx, &if_stmt->else_list);
7245
7246       end_divergent_if(ctx, &ic);
7247    }
7248 }
7249
7250 static void visit_cf_list(isel_context *ctx,
7251                           struct exec_list *list)
7252 {
7253    foreach_list_typed(nir_cf_node, node, node, list) {
7254       switch (node->type) {
7255       case nir_cf_node_block:
7256          visit_block(ctx, nir_cf_node_as_block(node));
7257          break;
7258       case nir_cf_node_if:
7259          visit_if(ctx, nir_cf_node_as_if(node));
7260          break;
7261       case nir_cf_node_loop:
7262          visit_loop(ctx, nir_cf_node_as_loop(node));
7263          break;
7264       default:
7265          unreachable("unimplemented cf list type");
7266       }
7267    }
7268 }
7269
7270 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
7271 {
7272    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
7273    uint64_t mask = ctx->vs_output.mask[slot];
7274    if (!is_pos && !mask)
7275       return;
7276    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
7277       return;
7278    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7279    exp->enabled_mask = mask;
7280    for (unsigned i = 0; i < 4; ++i) {
7281       if (mask & (1 << i))
7282          exp->operands[i] = Operand(ctx->vs_output.outputs[slot][i]);
7283       else
7284          exp->operands[i] = Operand(v1);
7285    }
7286    exp->valid_mask = false;
7287    exp->done = false;
7288    exp->compressed = false;
7289    if (is_pos)
7290       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7291    else
7292       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
7293    ctx->block->instructions.emplace_back(std::move(exp));
7294 }
7295
7296 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
7297 {
7298    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7299    exp->enabled_mask = 0;
7300    for (unsigned i = 0; i < 4; ++i)
7301       exp->operands[i] = Operand(v1);
7302    if (ctx->vs_output.mask[VARYING_SLOT_PSIZ]) {
7303       exp->operands[0] = Operand(ctx->vs_output.outputs[VARYING_SLOT_PSIZ][0]);
7304       exp->enabled_mask |= 0x1;
7305    }
7306    if (ctx->vs_output.mask[VARYING_SLOT_LAYER]) {
7307       exp->operands[2] = Operand(ctx->vs_output.outputs[VARYING_SLOT_LAYER][0]);
7308       exp->enabled_mask |= 0x4;
7309    }
7310    if (ctx->vs_output.mask[VARYING_SLOT_VIEWPORT]) {
7311       if (ctx->options->chip_class < GFX9) {
7312          exp->operands[3] = Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]);
7313          exp->enabled_mask |= 0x8;
7314       } else {
7315          Builder bld(ctx->program, ctx->block);
7316
7317          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
7318                              Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]));
7319          if (exp->operands[2].isTemp())
7320             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
7321
7322          exp->operands[2] = Operand(out);
7323          exp->enabled_mask |= 0x4;
7324       }
7325    }
7326    exp->valid_mask = false;
7327    exp->done = false;
7328    exp->compressed = false;
7329    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7330    ctx->block->instructions.emplace_back(std::move(exp));
7331 }
7332
7333 static void create_vs_exports(isel_context *ctx)
7334 {
7335    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
7336
7337    if (outinfo->export_prim_id) {
7338       ctx->vs_output.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
7339       ctx->vs_output.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = ctx->vs_prim_id;
7340    }
7341
7342    if (ctx->options->key.has_multiview_view_index) {
7343       ctx->vs_output.mask[VARYING_SLOT_LAYER] |= 0x1;
7344       ctx->vs_output.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, ctx->view_index);
7345    }
7346
7347    /* the order these position exports are created is important */
7348    int next_pos = 0;
7349    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
7350    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
7351       export_vs_psiz_layer_viewport(ctx, &next_pos);
7352    }
7353    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7354       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
7355    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7356       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
7357
7358    if (ctx->options->key.vs_common_out.export_clip_dists) {
7359       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7360          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
7361       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7362          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
7363    }
7364
7365    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
7366       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
7367           i != VARYING_SLOT_PRIMITIVE_ID)
7368          continue;
7369
7370       export_vs_varying(ctx, i, false, NULL);
7371    }
7372 }
7373
7374 static void emit_stream_output(isel_context *ctx,
7375                                Temp const *so_buffers,
7376                                Temp const *so_write_offset,
7377                                const struct radv_stream_output *output)
7378 {
7379    unsigned num_comps = util_bitcount(output->component_mask);
7380    unsigned loc = output->location;
7381    unsigned buf = output->buffer;
7382    unsigned offset = output->offset;
7383
7384    assert(num_comps && num_comps <= 4);
7385    if (!num_comps || num_comps > 4)
7386       return;
7387
7388    unsigned start = ffs(output->component_mask) - 1;
7389
7390    Temp out[4];
7391    bool all_undef = true;
7392    assert(ctx->stage == vertex_vs);
7393    for (unsigned i = 0; i < num_comps; i++) {
7394       out[i] = ctx->vs_output.outputs[loc][start + i];
7395       all_undef = all_undef && !out[i].id();
7396    }
7397    if (all_undef)
7398       return;
7399
7400    Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_comps)};
7401    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_comps, 1)};
7402    for (unsigned i = 0; i < num_comps; ++i)
7403       vec->operands[i] = (ctx->vs_output.mask[loc] & 1 << i) ? Operand(out[i]) : Operand(0u);
7404    vec->definitions[0] = Definition(write_data);
7405    ctx->block->instructions.emplace_back(std::move(vec));
7406
7407    aco_opcode opcode;
7408    switch (num_comps) {
7409    case 1:
7410       opcode = aco_opcode::buffer_store_dword;
7411       break;
7412    case 2:
7413       opcode = aco_opcode::buffer_store_dwordx2;
7414       break;
7415    case 3:
7416       opcode = aco_opcode::buffer_store_dwordx3;
7417       break;
7418    case 4:
7419       opcode = aco_opcode::buffer_store_dwordx4;
7420       break;
7421    }
7422
7423    aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
7424    store->operands[0] = Operand(so_write_offset[buf]);
7425    store->operands[1] = Operand(so_buffers[buf]);
7426    store->operands[2] = Operand((uint32_t) 0);
7427    store->operands[3] = Operand(write_data);
7428    if (offset > 4095) {
7429       /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7430       Builder bld(ctx->program, ctx->block);
7431       store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
7432    } else {
7433       store->offset = offset;
7434    }
7435    store->offen = true;
7436    store->glc = true;
7437    store->dlc = false;
7438    store->slc = true;
7439    store->can_reorder = true;
7440    ctx->block->instructions.emplace_back(std::move(store));
7441 }
7442
7443 static void emit_streamout(isel_context *ctx, unsigned stream)
7444 {
7445    Builder bld(ctx->program, ctx->block);
7446
7447    Temp so_buffers[4];
7448    Temp buf_ptr = convert_pointer_to_64_bit(ctx, ctx->streamout_buffers);
7449    for (unsigned i = 0; i < 4; i++) {
7450       unsigned stride = ctx->program->info->so.strides[i];
7451       if (!stride)
7452          continue;
7453
7454       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, Operand(i * 16u));
7455    }
7456
7457    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
7458                                 ctx->streamout_config, Operand(0x70010u));
7459
7460    Temp tid = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
7461                        bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
7462
7463    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(s2), so_vtx_count, tid);
7464
7465    if_context ic;
7466    begin_divergent_if_then(ctx, &ic, can_emit);
7467
7468    bld.reset(ctx->block);
7469
7470    Temp so_write_index = bld.vadd32(bld.def(v1), ctx->streamout_write_idx, tid);
7471
7472    Temp so_write_offset[4];
7473
7474    for (unsigned i = 0; i < 4; i++) {
7475       unsigned stride = ctx->program->info->so.strides[i];
7476       if (!stride)
7477          continue;
7478
7479       if (stride == 1) {
7480          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
7481                                 ctx->streamout_write_idx, ctx->streamout_offset[i]);
7482          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
7483
7484          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
7485       } else {
7486          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
7487          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u), ctx->streamout_offset[i]);
7488          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
7489       }
7490    }
7491
7492    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
7493       struct radv_stream_output *output =
7494          &ctx->program->info->so.outputs[i];
7495       if (stream != output->stream)
7496          continue;
7497
7498       emit_stream_output(ctx, so_buffers, so_write_offset, output);
7499    }
7500
7501    begin_divergent_if_else(ctx, &ic);
7502    end_divergent_if(ctx, &ic);
7503 }
7504
7505 } /* end namespace */
7506
7507 void handle_bc_optimize(isel_context *ctx)
7508 {
7509    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7510    Builder bld(ctx->program, ctx->block);
7511    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
7512    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
7513    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
7514    if (uses_center && uses_centroid) {
7515       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(s2)), ctx->prim_mask, Operand(0u));
7516
7517       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
7518          for (unsigned i = 0; i < 2; i++) {
7519             Temp new_coord = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7520                                       ctx->fs_inputs[fs_input::persp_centroid_p1 + i],
7521                                       ctx->fs_inputs[fs_input::persp_center_p1 + i],
7522                                       sel);
7523             ctx->fs_inputs[fs_input::persp_centroid_p1 + i] = new_coord;
7524          }
7525       }
7526
7527       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
7528          for (unsigned i = 0; i < 2; i++) {
7529             Temp new_coord = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7530                                       ctx->fs_inputs[fs_input::linear_centroid_p1 + i],
7531                                       ctx->fs_inputs[fs_input::linear_center_p1 + i],
7532                                       sel);
7533             ctx->fs_inputs[fs_input::linear_centroid_p1 + i] = new_coord;
7534          }
7535       }
7536    }
7537 }
7538
7539 void select_program(Program *program,
7540                     unsigned shader_count,
7541                     struct nir_shader *const *shaders,
7542                     ac_shader_config* config,
7543                     struct radv_shader_info *info,
7544                     struct radv_nir_compiler_options *options)
7545 {
7546    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, info, options);
7547
7548    for (unsigned i = 0; i < shader_count; i++) {
7549       nir_shader *nir = shaders[i];
7550       init_context(&ctx, nir);
7551
7552       if (!i) {
7553          add_startpgm(&ctx); /* needs to be after init_context() for FS */
7554          append_logical_start(ctx.block);
7555       }
7556
7557       if_context ic;
7558       if (shader_count >= 2) {
7559          Builder bld(ctx.program, ctx.block);
7560          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), ctx.merged_wave_info, Operand((8u << 16) | (i * 8u)));
7561          Temp thread_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
7562                                    bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
7563          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(s2)), count, thread_id);
7564
7565          begin_divergent_if_then(&ctx, &ic, cond);
7566       }
7567
7568       if (i) {
7569          Builder bld(ctx.program, ctx.block);
7570          bld.barrier(aco_opcode::p_memory_barrier_shared); //TODO: different barriers are needed for different stages
7571          bld.sopp(aco_opcode::s_barrier);
7572       }
7573
7574       if (ctx.stage == fragment_fs)
7575          handle_bc_optimize(&ctx);
7576
7577       nir_function_impl *func = nir_shader_get_entrypoint(nir);
7578       visit_cf_list(&ctx, &func->body);
7579
7580       if (ctx.program->info->so.num_outputs/*&& !ctx->is_gs_copy_shader */)
7581          emit_streamout(&ctx, 0);
7582
7583       if (ctx.stage == vertex_vs)
7584          create_vs_exports(&ctx);
7585
7586       if (shader_count >= 2) {
7587          begin_divergent_if_else(&ctx, &ic);
7588          end_divergent_if(&ctx, &ic);
7589       }
7590
7591       ralloc_free(ctx.divergent_vals);
7592    }
7593
7594    append_logical_end(ctx.block);
7595    ctx.block->kind |= block_kind_uniform;
7596    Builder bld(ctx.program, ctx.block);
7597    if (ctx.program->wb_smem_l1_on_end)
7598       bld.smem(aco_opcode::s_dcache_wb, false);
7599    bld.sopp(aco_opcode::s_endpgm);
7600
7601    /* cleanup CFG */
7602    for (Block& BB : program->blocks) {
7603       for (unsigned idx : BB.linear_preds)
7604          program->blocks[idx].linear_succs.emplace_back(BB.index);
7605       for (unsigned idx : BB.logical_preds)
7606          program->blocks[idx].logical_succs.emplace_back(BB.index);
7607    }
7608 }
7609 }