src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <map>
  29
  30 #include "ac_shader_util.h"
  31 #include "aco_ir.h"
  32 #include "aco_builder.h"
  33 #include "aco_interface.h"
  34 #include "aco_instruction_selection_setup.cpp"
  35 #include "util/fast_idiv_by_const.h"
  36
  37 namespace aco {
  38 namespace {
  39
  40 class loop_info_RAII {
  41    isel_context* ctx;
  42    unsigned header_idx_old;
  43    Block* exit_old;
  44    bool divergent_cont_old;
  45    bool divergent_branch_old;
  46    bool divergent_if_old;
  47
  48 public:
  49    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  50       : ctx(ctx),
  51         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  52         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  53         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  54         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  55    {
  56       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  57       ctx->cf_info.parent_loop.exit = loop_exit;
  58       ctx->cf_info.parent_loop.has_divergent_continue = false;
  59       ctx->cf_info.parent_loop.has_divergent_branch = false;
  60       ctx->cf_info.parent_if.is_divergent = false;
  61       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  62    }
  63
  64    ~loop_info_RAII()
  65    {
  66       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  67       ctx->cf_info.parent_loop.exit = exit_old;
  68       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  69       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  70       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  71       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  72       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  73          ctx->cf_info.exec_potentially_empty = false;
  74    }
  75 };
  76
  77 struct if_context {
  78    Temp cond;
  79
  80    bool divergent_old;
  81    bool exec_potentially_empty_old;
  82
  83    unsigned BB_if_idx;
  84    unsigned invert_idx;
  85    bool then_branch_divergent;
  86    Block BB_invert;
  87    Block BB_endif;
  88 };
  89
  90 static void visit_cf_list(struct isel_context *ctx,
  91                           struct exec_list *list);
  92
  93 static void add_logical_edge(unsigned pred_idx, Block *succ)
  94 {
  95    succ->logical_preds.emplace_back(pred_idx);
  96 }
  97
  98
  99 static void add_linear_edge(unsigned pred_idx, Block *succ)
 100 {
 101    succ->linear_preds.emplace_back(pred_idx);
 102 }
 103
 104 static void add_edge(unsigned pred_idx, Block *succ)
 105 {
 106    add_logical_edge(pred_idx, succ);
 107    add_linear_edge(pred_idx, succ);
 108 }
 109
 110 static void append_logical_start(Block *b)
 111 {
 112    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 113 }
 114
 115 static void append_logical_end(Block *b)
 116 {
 117    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 118 }
 119
 120 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 121 {
 122    assert(ctx->allocated[def->index].id());
 123    return ctx->allocated[def->index];
 124 }
 125
 126 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 127                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 128 {
 129    Builder bld(ctx->program, ctx->block);
 130    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 131    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 132
 133    if (ctx->program->wave_size == 32) {
 134       return thread_id_lo;
 135    } else {
 136       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 137       return thread_id_hi;
 138    }
 139 }
 140
 141 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 142 {
 143    Builder bld(ctx->program, ctx->block);
 144
 145    if (!dst.id())
 146       dst = bld.tmp(src.regClass());
 147
 148    assert(src.size() == dst.size());
 149
 150    if (ctx->stage != fragment_fs) {
 151       if (!dst.id())
 152          return src;
 153
 154       bld.copy(Definition(dst), src);
 155       return dst;
 156    }
 157
 158    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 159    ctx->program->needs_wqm |= program_needs_wqm;
 160    return dst;
 161 }
 162
 163 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 164 {
 165    if (index.regClass() == s1)
 166       return bld.readlane(bld.def(s1), data, index);
 167
 168    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 169
 170    /* Currently not implemented on GFX6-7 */
 171    assert(ctx->options->chip_class >= GFX8);
 172
 173    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 174       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 175    }
 176
 177    /* GFX10, wave64 mode:
 178     * The bpermute instruction is limited to half-wave operation, which means that it can't
 179     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 180     * emulate it here.
 181     */
 182    if (!ctx->has_gfx10_wave64_bpermute) {
 183       ctx->has_gfx10_wave64_bpermute = true;
 184       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 185       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 186    }
 187
 188    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 189    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 190    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 191    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2, vcc), lane_is_hi, index_is_hi);
 192
 193    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 194                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 195 }
 196
 197 Temp as_vgpr(isel_context *ctx, Temp val)
 198 {
 199    if (val.type() == RegType::sgpr) {
 200       Builder bld(ctx->program, ctx->block);
 201       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 202    }
 203    assert(val.type() == RegType::vgpr);
 204    return val;
 205 }
 206
 207 //assumes a != 0xffffffff
 208 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 209 {
 210    assert(b != 0);
 211    Builder bld(ctx->program, ctx->block);
 212
 213    if (util_is_power_of_two_or_zero(b)) {
 214       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 215       return;
 216    }
 217
 218    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 219
 220    assert(info.multiplier <= 0xffffffff);
 221
 222    bool pre_shift = info.pre_shift != 0;
 223    bool increment = info.increment != 0;
 224    bool multiply = true;
 225    bool post_shift = info.post_shift != 0;
 226
 227    if (!pre_shift && !increment && !multiply && !post_shift) {
 228       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 229       return;
 230    }
 231
 232    Temp pre_shift_dst = a;
 233    if (pre_shift) {
 234       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 235       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 236    }
 237
 238    Temp increment_dst = pre_shift_dst;
 239    if (increment) {
 240       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 241       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 242    }
 243
 244    Temp multiply_dst = increment_dst;
 245    if (multiply) {
 246       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 247       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 248                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 249    }
 250
 251    if (post_shift) {
 252       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 253    }
 254 }
 255
 256 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 257 {
 258    Builder bld(ctx->program, ctx->block);
 259    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 260 }
 261
 262
 263 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 264 {
 265    /* no need to extract the whole vector */
 266    if (src.regClass() == dst_rc) {
 267       assert(idx == 0);
 268       return src;
 269    }
 270    assert(src.size() > idx);
 271    Builder bld(ctx->program, ctx->block);
 272    auto it = ctx->allocated_vec.find(src.id());
 273    /* the size check needs to be early because elements other than 0 may be garbage */
 274    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 275       if (it->second[idx].regClass() == dst_rc) {
 276          return it->second[idx];
 277       } else {
 278          assert(dst_rc.size() == it->second[idx].regClass().size());
 279          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 280          return bld.copy(bld.def(dst_rc), it->second[idx]);
 281       }
 282    }
 283
 284    if (src.size() == dst_rc.size()) {
 285       assert(idx == 0);
 286       return bld.copy(bld.def(dst_rc), src);
 287    } else {
 288       Temp dst = bld.tmp(dst_rc);
 289       emit_extract_vector(ctx, src, idx, dst);
 290       return dst;
 291    }
 292 }
 293
 294 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 295 {
 296    if (num_components == 1)
 297       return;
 298    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 299       return;
 300    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 301    split->operands[0] = Operand(vec_src);
 302    std::array<Temp,4> elems;
 303    for (unsigned i = 0; i < num_components; i++) {
 304       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 305       split->definitions[i] = Definition(elems[i]);
 306    }
 307    ctx->block->instructions.emplace_back(std::move(split));
 308    ctx->allocated_vec.emplace(vec_src.id(), elems);
 309 }
 310
 311 /* This vector expansion uses a mask to determine which elements in the new vector
 312  * come from the original vector. The other elements are undefined. */
 313 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 314 {
 315    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 316
 317    if (vec_src == dst)
 318       return;
 319
 320    Builder bld(ctx->program, ctx->block);
 321    if (num_components == 1) {
 322       if (dst.type() == RegType::sgpr)
 323          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 324       else
 325          bld.copy(Definition(dst), vec_src);
 326       return;
 327    }
 328
 329    unsigned component_size = dst.size() / num_components;
 330    std::array<Temp,4> elems;
 331
 332    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 333    vec->definitions[0] = Definition(dst);
 334    unsigned k = 0;
 335    for (unsigned i = 0; i < num_components; i++) {
 336       if (mask & (1 << i)) {
 337          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 338          if (dst.type() == RegType::sgpr)
 339             src = bld.as_uniform(src);
 340          vec->operands[i] = Operand(src);
 341       } else {
 342          vec->operands[i] = Operand(0u);
 343       }
 344       elems[i] = vec->operands[i].getTemp();
 345    }
 346    ctx->block->instructions.emplace_back(std::move(vec));
 347    ctx->allocated_vec.emplace(dst.id(), elems);
 348 }
 349
 350 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 351 {
 352    Builder bld(ctx->program, ctx->block);
 353    if (!dst.id())
 354       dst = bld.tmp(bld.lm);
 355
 356    assert(val.regClass() == s1);
 357    assert(dst.regClass() == bld.lm);
 358
 359    return bld.sop2(Builder::s_cselect, bld.hint_vcc(Definition(dst)), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 360 }
 361
 362 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 363 {
 364    Builder bld(ctx->program, ctx->block);
 365    if (!dst.id())
 366       dst = bld.tmp(s1);
 367
 368    assert(val.regClass() == bld.lm);
 369    assert(dst.regClass() == s1);
 370
 371    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 372    Temp tmp = bld.tmp(s1);
 373    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 374    return emit_wqm(ctx, tmp, dst);
 375 }
 376
 377 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 378 {
 379    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 380       return get_ssa_temp(ctx, src.src.ssa);
 381
 382    if (src.src.ssa->num_components == size) {
 383       bool identity_swizzle = true;
 384       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 385          if (src.swizzle[i] != i)
 386             identity_swizzle = false;
 387       }
 388       if (identity_swizzle)
 389          return get_ssa_temp(ctx, src.src.ssa);
 390    }
 391
 392    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 393    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 394    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 395    assert(vec.size() % elem_size == 0);
 396
 397    RegClass elem_rc = RegClass(vec.type(), elem_size);
 398    if (size == 1) {
 399       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 400    } else {
 401       assert(size <= 4);
 402       std::array<Temp,4> elems;
 403       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 404       for (unsigned i = 0; i < size; ++i) {
 405          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 406          vec_instr->operands[i] = Operand{elems[i]};
 407       }
 408       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 409       vec_instr->definitions[0] = Definition(dst);
 410       ctx->block->instructions.emplace_back(std::move(vec_instr));
 411       ctx->allocated_vec.emplace(dst.id(), elems);
 412       return dst;
 413    }
 414 }
 415
 416 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 417 {
 418    if (ptr.size() == 2)
 419       return ptr;
 420    Builder bld(ctx->program, ctx->block);
 421    if (ptr.type() == RegType::vgpr)
 422       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 423    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 424                      ptr, Operand((unsigned)ctx->options->address32_hi));
 425 }
 426
 427 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 428 {
 429    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 430    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 431    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 432    sop2->definitions[0] = Definition(dst);
 433    if (writes_scc)
 434       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 435    ctx->block->instructions.emplace_back(std::move(sop2));
 436 }
 437
 438 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool commutative, bool swap_srcs=false)
 439 {
 440    Builder bld(ctx->program, ctx->block);
 441    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 442    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 443    if (src1.type() == RegType::sgpr) {
 444       if (commutative && src0.type() == RegType::vgpr) {
 445          Temp t = src0;
 446          src0 = src1;
 447          src1 = t;
 448       } else if (src0.type() == RegType::vgpr &&
 449                  op != aco_opcode::v_madmk_f32 &&
 450                  op != aco_opcode::v_madak_f32 &&
 451                  op != aco_opcode::v_madmk_f16 &&
 452                  op != aco_opcode::v_madak_f16) {
 453          /* If the instruction is not commutative, we emit a VOP3A instruction */
 454          bld.vop2_e64(op, Definition(dst), src0, src1);
 455          return;
 456       } else {
 457          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 458       }
 459    }
 460    bld.vop2(op, Definition(dst), src0, src1);
 461 }
 462
 463 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 464 {
 465    Temp src0 = get_alu_src(ctx, instr->src[0]);
 466    Temp src1 = get_alu_src(ctx, instr->src[1]);
 467    Temp src2 = get_alu_src(ctx, instr->src[2]);
 468
 469    /* ensure that the instruction has at most 1 sgpr operand
 470     * The optimizer will inline constants for us */
 471    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 472       src0 = as_vgpr(ctx, src0);
 473    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 474       src1 = as_vgpr(ctx, src1);
 475    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 476       src2 = as_vgpr(ctx, src2);
 477
 478    Builder bld(ctx->program, ctx->block);
 479    bld.vop3(op, Definition(dst), src0, src1, src2);
 480 }
 481
 482 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 483 {
 484    Builder bld(ctx->program, ctx->block);
 485    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 486 }
 487
 488 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 489 {
 490    Temp src0 = get_alu_src(ctx, instr->src[0]);
 491    Temp src1 = get_alu_src(ctx, instr->src[1]);
 492    assert(src0.size() == src1.size());
 493
 494    aco_ptr<Instruction> vopc;
 495    if (src1.type() == RegType::sgpr) {
 496       if (src0.type() == RegType::vgpr) {
 497          /* to swap the operands, we might also have to change the opcode */
 498          switch (op) {
 499             case aco_opcode::v_cmp_lt_f32:
 500                op = aco_opcode::v_cmp_gt_f32;
 501                break;
 502             case aco_opcode::v_cmp_ge_f32:
 503                op = aco_opcode::v_cmp_le_f32;
 504                break;
 505             case aco_opcode::v_cmp_lt_i32:
 506                op = aco_opcode::v_cmp_gt_i32;
 507                break;
 508             case aco_opcode::v_cmp_ge_i32:
 509                op = aco_opcode::v_cmp_le_i32;
 510                break;
 511             case aco_opcode::v_cmp_lt_u32:
 512                op = aco_opcode::v_cmp_gt_u32;
 513                break;
 514             case aco_opcode::v_cmp_ge_u32:
 515                op = aco_opcode::v_cmp_le_u32;
 516                break;
 517             case aco_opcode::v_cmp_lt_f64:
 518                op = aco_opcode::v_cmp_gt_f64;
 519                break;
 520             case aco_opcode::v_cmp_ge_f64:
 521                op = aco_opcode::v_cmp_le_f64;
 522                break;
 523             case aco_opcode::v_cmp_lt_i64:
 524                op = aco_opcode::v_cmp_gt_i64;
 525                break;
 526             case aco_opcode::v_cmp_ge_i64:
 527                op = aco_opcode::v_cmp_le_i64;
 528                break;
 529             case aco_opcode::v_cmp_lt_u64:
 530                op = aco_opcode::v_cmp_gt_u64;
 531                break;
 532             case aco_opcode::v_cmp_ge_u64:
 533                op = aco_opcode::v_cmp_le_u64;
 534                break;
 535             default: /* eq and ne are commutative */
 536                break;
 537          }
 538          Temp t = src0;
 539          src0 = src1;
 540          src1 = t;
 541       } else {
 542          src1 = as_vgpr(ctx, src1);
 543       }
 544    }
 545
 546    Builder bld(ctx->program, ctx->block);
 547    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 548 }
 549
 550 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 551 {
 552    Temp src0 = get_alu_src(ctx, instr->src[0]);
 553    Temp src1 = get_alu_src(ctx, instr->src[1]);
 554    Builder bld(ctx->program, ctx->block);
 555
 556    assert(dst.regClass() == bld.lm);
 557    assert(src0.type() == RegType::sgpr);
 558    assert(src1.type() == RegType::sgpr);
 559    assert(src0.regClass() == src1.regClass());
 560
 561    /* Emit the SALU comparison instruction */
 562    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 563    /* Turn the result into a per-lane bool */
 564    bool_to_vector_condition(ctx, cmp, dst);
 565 }
 566
 567 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 568                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::last_opcode, aco_opcode s64_op = aco_opcode::last_opcode)
 569 {
 570    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 571    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 572    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 573    bool use_valu = s_op == aco_opcode::last_opcode ||
 574                    divergent_vals ||
 575                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 576                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 577    aco_opcode op = use_valu ? v_op : s_op;
 578    assert(op != aco_opcode::last_opcode);
 579
 580    if (use_valu)
 581       emit_vopc_instruction(ctx, instr, op, dst);
 582    else
 583       emit_sopc_instruction(ctx, instr, op, dst);
 584 }
 585
 586 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 587 {
 588    Builder bld(ctx->program, ctx->block);
 589    Temp src0 = get_alu_src(ctx, instr->src[0]);
 590    Temp src1 = get_alu_src(ctx, instr->src[1]);
 591
 592    assert(dst.regClass() == bld.lm);
 593    assert(src0.regClass() == bld.lm);
 594    assert(src1.regClass() == bld.lm);
 595
 596    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 597 }
 598
 599 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 600 {
 601    Builder bld(ctx->program, ctx->block);
 602    Temp cond = get_alu_src(ctx, instr->src[0]);
 603    Temp then = get_alu_src(ctx, instr->src[1]);
 604    Temp els = get_alu_src(ctx, instr->src[2]);
 605
 606    assert(cond.regClass() == bld.lm);
 607
 608    if (dst.type() == RegType::vgpr) {
 609       aco_ptr<Instruction> bcsel;
 610       if (dst.size() == 1) {
 611          then = as_vgpr(ctx, then);
 612          els = as_vgpr(ctx, els);
 613
 614          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 615       } else if (dst.size() == 2) {
 616          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 617          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 618          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 619          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 620
 621          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 622          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 623
 624          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 625       } else {
 626          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 627          nir_print_instr(&instr->instr, stderr);
 628          fprintf(stderr, "\n");
 629       }
 630       return;
 631    }
 632
 633    if (instr->dest.dest.ssa.bit_size == 1) {
 634       assert(dst.regClass() == bld.lm);
 635       assert(then.regClass() == bld.lm);
 636       assert(els.regClass() == bld.lm);
 637    }
 638
 639    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 640       if (dst.regClass() == s1 || dst.regClass() == s2) {
 641          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 642          assert(dst.size() == then.size());
 643          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 644          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 645       } else {
 646          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 647          nir_print_instr(&instr->instr, stderr);
 648          fprintf(stderr, "\n");
 649       }
 650       return;
 651    }
 652
 653    /* divergent boolean bcsel
 654     * this implements bcsel on bools: dst = s0 ? s1 : s2
 655     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 656    assert(instr->dest.dest.ssa.bit_size == 1);
 657
 658    if (cond.id() != then.id())
 659       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 660
 661    if (cond.id() == els.id())
 662       bld.sop1(Builder::s_mov, Definition(dst), then);
 663    else
 664       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 665                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 666 }
 667
 668 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 669                     aco_opcode op, uint32_t undo)
 670 {
 671    /* multiply by 16777216 to handle denormals */
 672    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 673                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 674    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 675    scaled = bld.vop1(op, bld.def(v1), scaled);
 676    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 677
 678    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 679
 680    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 681 }
 682
 683 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 684 {
 685    if (ctx->block->fp_mode.denorm32 == 0) {
 686       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 687       return;
 688    }
 689
 690    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 691 }
 692
 693 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 694 {
 695    if (ctx->block->fp_mode.denorm32 == 0) {
 696       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 697       return;
 698    }
 699
 700    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 701 }
 702
 703 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 704 {
 705    if (ctx->block->fp_mode.denorm32 == 0) {
 706       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 707       return;
 708    }
 709
 710    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 711 }
 712
 713 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 714 {
 715    if (ctx->block->fp_mode.denorm32 == 0) {
 716       bld.vop1(aco_opcode::v_log_f32, dst, val);
 717       return;
 718    }
 719
 720    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 721 }
 722
 723 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 724 {
 725    if (!instr->dest.dest.is_ssa) {
 726       fprintf(stderr, "nir alu dst not in ssa: ");
 727       nir_print_instr(&instr->instr, stderr);
 728       fprintf(stderr, "\n");
 729       abort();
 730    }
 731    Builder bld(ctx->program, ctx->block);
 732    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 733    switch(instr->op) {
 734    case nir_op_vec2:
 735    case nir_op_vec3:
 736    case nir_op_vec4: {
 737       std::array<Temp,4> elems;
 738       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 739       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 740          elems[i] = get_alu_src(ctx, instr->src[i]);
 741          vec->operands[i] = Operand{elems[i]};
 742       }
 743       vec->definitions[0] = Definition(dst);
 744       ctx->block->instructions.emplace_back(std::move(vec));
 745       ctx->allocated_vec.emplace(dst.id(), elems);
 746       break;
 747    }
 748    case nir_op_mov: {
 749       Temp src = get_alu_src(ctx, instr->src[0]);
 750       aco_ptr<Instruction> mov;
 751       if (dst.type() == RegType::sgpr) {
 752          if (src.type() == RegType::vgpr)
 753             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 754          else if (src.regClass() == s1)
 755             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 756          else if (src.regClass() == s2)
 757             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 758          else
 759             unreachable("wrong src register class for nir_op_imov");
 760       } else if (dst.regClass() == v1) {
 761          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 762       } else if (dst.regClass() == v2) {
 763          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 764       } else {
 765          nir_print_instr(&instr->instr, stderr);
 766          unreachable("Should have been lowered to scalar.");
 767       }
 768       break;
 769    }
 770    case nir_op_inot: {
 771       Temp src = get_alu_src(ctx, instr->src[0]);
 772       if (instr->dest.dest.ssa.bit_size == 1) {
 773          assert(src.regClass() == bld.lm);
 774          assert(dst.regClass() == bld.lm);
 775          bld.sop2(Builder::s_andn2, Definition(dst), bld.def(s1, scc), Operand(exec, bld.lm), src);
 776       } else if (dst.regClass() == v1) {
 777          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 778       } else if (dst.type() == RegType::sgpr) {
 779          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 780          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 781       } else {
 782          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 783          nir_print_instr(&instr->instr, stderr);
 784          fprintf(stderr, "\n");
 785       }
 786       break;
 787    }
 788    case nir_op_ineg: {
 789       Temp src = get_alu_src(ctx, instr->src[0]);
 790       if (dst.regClass() == v1) {
 791          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 792       } else if (dst.regClass() == s1) {
 793          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 794       } else if (dst.size() == 2) {
 795          Temp src0 = bld.tmp(dst.type(), 1);
 796          Temp src1 = bld.tmp(dst.type(), 1);
 797          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 798
 799          if (dst.regClass() == s2) {
 800             Temp carry = bld.tmp(s1);
 801             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 802             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 803             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 804          } else {
 805             Temp lower = bld.tmp(v1);
 806             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 807             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 808             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 809          }
 810       } else {
 811          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 812          nir_print_instr(&instr->instr, stderr);
 813          fprintf(stderr, "\n");
 814       }
 815       break;
 816    }
 817    case nir_op_iabs: {
 818       if (dst.regClass() == s1) {
 819          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 820       } else if (dst.regClass() == v1) {
 821          Temp src = get_alu_src(ctx, instr->src[0]);
 822          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 823       } else {
 824          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 825          nir_print_instr(&instr->instr, stderr);
 826          fprintf(stderr, "\n");
 827       }
 828       break;
 829    }
 830    case nir_op_isign: {
 831       Temp src = get_alu_src(ctx, instr->src[0]);
 832       if (dst.regClass() == s1) {
 833          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 834          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 835          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 836       } else if (dst.regClass() == s2) {
 837          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 838          Temp neqz;
 839          if (ctx->program->chip_class >= GFX8)
 840             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 841          else
 842             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 843          /* SCC gets zero-extended to 64 bit */
 844          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 845       } else if (dst.regClass() == v1) {
 846          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 847          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 848          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 849       } else if (dst.regClass() == v2) {
 850          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 851          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 852          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 853          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 854          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 855          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 856       } else {
 857          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 858          nir_print_instr(&instr->instr, stderr);
 859          fprintf(stderr, "\n");
 860       }
 861       break;
 862    }
 863    case nir_op_imax: {
 864       if (dst.regClass() == v1) {
 865          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 866       } else if (dst.regClass() == s1) {
 867          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 868       } else {
 869          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 870          nir_print_instr(&instr->instr, stderr);
 871          fprintf(stderr, "\n");
 872       }
 873       break;
 874    }
 875    case nir_op_umax: {
 876       if (dst.regClass() == v1) {
 877          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 878       } else if (dst.regClass() == s1) {
 879          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 880       } else {
 881          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 882          nir_print_instr(&instr->instr, stderr);
 883          fprintf(stderr, "\n");
 884       }
 885       break;
 886    }
 887    case nir_op_imin: {
 888       if (dst.regClass() == v1) {
 889          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 890       } else if (dst.regClass() == s1) {
 891          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 892       } else {
 893          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 894          nir_print_instr(&instr->instr, stderr);
 895          fprintf(stderr, "\n");
 896       }
 897       break;
 898    }
 899    case nir_op_umin: {
 900       if (dst.regClass() == v1) {
 901          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 902       } else if (dst.regClass() == s1) {
 903          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
 904       } else {
 905          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 906          nir_print_instr(&instr->instr, stderr);
 907          fprintf(stderr, "\n");
 908       }
 909       break;
 910    }
 911    case nir_op_ior: {
 912       if (instr->dest.dest.ssa.bit_size == 1) {
 913          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
 914       } else if (dst.regClass() == v1) {
 915          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
 916       } else if (dst.regClass() == s1) {
 917          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
 918       } else if (dst.regClass() == s2) {
 919          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
 920       } else {
 921          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 922          nir_print_instr(&instr->instr, stderr);
 923          fprintf(stderr, "\n");
 924       }
 925       break;
 926    }
 927    case nir_op_iand: {
 928       if (instr->dest.dest.ssa.bit_size == 1) {
 929          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
 930       } else if (dst.regClass() == v1) {
 931          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
 932       } else if (dst.regClass() == s1) {
 933          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
 934       } else if (dst.regClass() == s2) {
 935          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
 936       } else {
 937          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 938          nir_print_instr(&instr->instr, stderr);
 939          fprintf(stderr, "\n");
 940       }
 941       break;
 942    }
 943    case nir_op_ixor: {
 944       if (instr->dest.dest.ssa.bit_size == 1) {
 945          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
 946       } else if (dst.regClass() == v1) {
 947          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
 948       } else if (dst.regClass() == s1) {
 949          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
 950       } else if (dst.regClass() == s2) {
 951          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_ushr: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
 962       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
 963          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
 964                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 965       } else if (dst.regClass() == v2) {
 966          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
 967                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
 968       } else if (dst.regClass() == s2) {
 969          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
 970       } else if (dst.regClass() == s1) {
 971          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
 972       } else {
 973          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 974          nir_print_instr(&instr->instr, stderr);
 975          fprintf(stderr, "\n");
 976       }
 977       break;
 978    }
 979    case nir_op_ishl: {
 980       if (dst.regClass() == v1) {
 981          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
 982       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
 983          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
 984                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 985       } else if (dst.regClass() == v2) {
 986          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
 987                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
 988       } else if (dst.regClass() == s1) {
 989          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
 990       } else if (dst.regClass() == s2) {
 991          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
 992       } else {
 993          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 994          nir_print_instr(&instr->instr, stderr);
 995          fprintf(stderr, "\n");
 996       }
 997       break;
 998    }
 999    case nir_op_ishr: {
1000       if (dst.regClass() == v1) {
1001          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1002       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1003          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1004                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1005       } else if (dst.regClass() == v2) {
1006          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1007                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1008       } else if (dst.regClass() == s1) {
1009          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1010       } else if (dst.regClass() == s2) {
1011          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1012       } else {
1013          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1014          nir_print_instr(&instr->instr, stderr);
1015          fprintf(stderr, "\n");
1016       }
1017       break;
1018    }
1019    case nir_op_find_lsb: {
1020       Temp src = get_alu_src(ctx, instr->src[0]);
1021       if (src.regClass() == s1) {
1022          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1023       } else if (src.regClass() == v1) {
1024          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1025       } else if (src.regClass() == s2) {
1026          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1027       } else {
1028          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1029          nir_print_instr(&instr->instr, stderr);
1030          fprintf(stderr, "\n");
1031       }
1032       break;
1033    }
1034    case nir_op_ufind_msb:
1035    case nir_op_ifind_msb: {
1036       Temp src = get_alu_src(ctx, instr->src[0]);
1037       if (src.regClass() == s1 || src.regClass() == s2) {
1038          aco_opcode op = src.regClass() == s2 ?
1039                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1040                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1041          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1042
1043          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1044                                         Operand(src.size() * 32u - 1u), msb_rev);
1045          Temp msb = sub.def(0).getTemp();
1046          Temp carry = sub.def(1).getTemp();
1047
1048          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, carry);
1049       } else if (src.regClass() == v1) {
1050          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1051          Temp msb_rev = bld.tmp(v1);
1052          emit_vop1_instruction(ctx, instr, op, msb_rev);
1053          Temp msb = bld.tmp(v1);
1054          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1055          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1056       } else {
1057          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1058          nir_print_instr(&instr->instr, stderr);
1059          fprintf(stderr, "\n");
1060       }
1061       break;
1062    }
1063    case nir_op_bitfield_reverse: {
1064       if (dst.regClass() == s1) {
1065          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1066       } else if (dst.regClass() == v1) {
1067          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_iadd: {
1076       if (dst.regClass() == s1) {
1077          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1078          break;
1079       }
1080
1081       Temp src0 = get_alu_src(ctx, instr->src[0]);
1082       Temp src1 = get_alu_src(ctx, instr->src[1]);
1083       if (dst.regClass() == v1) {
1084          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1085          break;
1086       }
1087
1088       assert(src0.size() == 2 && src1.size() == 2);
1089       Temp src00 = bld.tmp(src0.type(), 1);
1090       Temp src01 = bld.tmp(dst.type(), 1);
1091       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1092       Temp src10 = bld.tmp(src1.type(), 1);
1093       Temp src11 = bld.tmp(dst.type(), 1);
1094       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1095
1096       if (dst.regClass() == s2) {
1097          Temp carry = bld.tmp(s1);
1098          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1099          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1100          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1101       } else if (dst.regClass() == v2) {
1102          Temp dst0 = bld.tmp(v1);
1103          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1104          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1105          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1106       } else {
1107          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1108          nir_print_instr(&instr->instr, stderr);
1109          fprintf(stderr, "\n");
1110       }
1111       break;
1112    }
1113    case nir_op_uadd_sat: {
1114       Temp src0 = get_alu_src(ctx, instr->src[0]);
1115       Temp src1 = get_alu_src(ctx, instr->src[1]);
1116       if (dst.regClass() == s1) {
1117          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1118          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1119                   src0, src1);
1120          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1121       } else if (dst.regClass() == v1) {
1122          if (ctx->options->chip_class >= GFX9) {
1123             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1124             add->operands[0] = Operand(src0);
1125             add->operands[1] = Operand(src1);
1126             add->definitions[0] = Definition(dst);
1127             add->clamp = 1;
1128             ctx->block->instructions.emplace_back(std::move(add));
1129          } else {
1130             if (src1.regClass() != v1)
1131                std::swap(src0, src1);
1132             assert(src1.regClass() == v1);
1133             Temp tmp = bld.tmp(v1);
1134             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1135             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1136          }
1137       } else {
1138          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1139          nir_print_instr(&instr->instr, stderr);
1140          fprintf(stderr, "\n");
1141       }
1142       break;
1143    }
1144    case nir_op_uadd_carry: {
1145       Temp src0 = get_alu_src(ctx, instr->src[0]);
1146       Temp src1 = get_alu_src(ctx, instr->src[1]);
1147       if (dst.regClass() == s1) {
1148          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1149          break;
1150       }
1151       if (dst.regClass() == v1) {
1152          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1153          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1154          break;
1155       }
1156
1157       Temp src00 = bld.tmp(src0.type(), 1);
1158       Temp src01 = bld.tmp(dst.type(), 1);
1159       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1160       Temp src10 = bld.tmp(src1.type(), 1);
1161       Temp src11 = bld.tmp(dst.type(), 1);
1162       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1163       if (dst.regClass() == s2) {
1164          Temp carry = bld.tmp(s1);
1165          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1166          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1167          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1168       } else if (dst.regClass() == v2) {
1169          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1170          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1171          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1172          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1173       } else {
1174          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1175          nir_print_instr(&instr->instr, stderr);
1176          fprintf(stderr, "\n");
1177       }
1178       break;
1179    }
1180    case nir_op_isub: {
1181       if (dst.regClass() == s1) {
1182          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1183          break;
1184       }
1185
1186       Temp src0 = get_alu_src(ctx, instr->src[0]);
1187       Temp src1 = get_alu_src(ctx, instr->src[1]);
1188       if (dst.regClass() == v1) {
1189          bld.vsub32(Definition(dst), src0, src1);
1190          break;
1191       }
1192
1193       Temp src00 = bld.tmp(src0.type(), 1);
1194       Temp src01 = bld.tmp(dst.type(), 1);
1195       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1196       Temp src10 = bld.tmp(src1.type(), 1);
1197       Temp src11 = bld.tmp(dst.type(), 1);
1198       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1199       if (dst.regClass() == s2) {
1200          Temp carry = bld.tmp(s1);
1201          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1202          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1203          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1204       } else if (dst.regClass() == v2) {
1205          Temp lower = bld.tmp(v1);
1206          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1207          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1208          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1209       } else {
1210          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1211          nir_print_instr(&instr->instr, stderr);
1212          fprintf(stderr, "\n");
1213       }
1214       break;
1215    }
1216    case nir_op_usub_borrow: {
1217       Temp src0 = get_alu_src(ctx, instr->src[0]);
1218       Temp src1 = get_alu_src(ctx, instr->src[1]);
1219       if (dst.regClass() == s1) {
1220          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1221          break;
1222       } else if (dst.regClass() == v1) {
1223          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1224          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1225          break;
1226       }
1227
1228       Temp src00 = bld.tmp(src0.type(), 1);
1229       Temp src01 = bld.tmp(dst.type(), 1);
1230       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1231       Temp src10 = bld.tmp(src1.type(), 1);
1232       Temp src11 = bld.tmp(dst.type(), 1);
1233       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1234       if (dst.regClass() == s2) {
1235          Temp borrow = bld.tmp(s1);
1236          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1237          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1238          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1239       } else if (dst.regClass() == v2) {
1240          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1241          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1242          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1243          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1244       } else {
1245          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1246          nir_print_instr(&instr->instr, stderr);
1247          fprintf(stderr, "\n");
1248       }
1249       break;
1250    }
1251    case nir_op_imul: {
1252       if (dst.regClass() == v1) {
1253          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1254                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1255       } else if (dst.regClass() == s1) {
1256          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1257       } else {
1258          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1259          nir_print_instr(&instr->instr, stderr);
1260          fprintf(stderr, "\n");
1261       }
1262       break;
1263    }
1264    case nir_op_umul_high: {
1265       if (dst.regClass() == v1) {
1266          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1267       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1268          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1269       } else if (dst.regClass() == s1) {
1270          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1271                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1272          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1273       } else {
1274          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1275          nir_print_instr(&instr->instr, stderr);
1276          fprintf(stderr, "\n");
1277       }
1278       break;
1279    }
1280    case nir_op_imul_high: {
1281       if (dst.regClass() == v1) {
1282          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1283       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1284          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1285       } else if (dst.regClass() == s1) {
1286          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1287                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1288          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1289       } else {
1290          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1291          nir_print_instr(&instr->instr, stderr);
1292          fprintf(stderr, "\n");
1293       }
1294       break;
1295    }
1296    case nir_op_fmul: {
1297       if (dst.size() == 1) {
1298          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1299       } else if (dst.size() == 2) {
1300          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1301                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1302       } else {
1303          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1304          nir_print_instr(&instr->instr, stderr);
1305          fprintf(stderr, "\n");
1306       }
1307       break;
1308    }
1309    case nir_op_fadd: {
1310       if (dst.size() == 1) {
1311          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1312       } else if (dst.size() == 2) {
1313          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1314                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1315       } else {
1316          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1317          nir_print_instr(&instr->instr, stderr);
1318          fprintf(stderr, "\n");
1319       }
1320       break;
1321    }
1322    case nir_op_fsub: {
1323       Temp src0 = get_alu_src(ctx, instr->src[0]);
1324       Temp src1 = get_alu_src(ctx, instr->src[1]);
1325       if (dst.size() == 1) {
1326          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1327             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1328          else
1329             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1330       } else if (dst.size() == 2) {
1331          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1332                                      get_alu_src(ctx, instr->src[0]),
1333                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1334          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1335          sub->neg[1] = true;
1336       } else {
1337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1338          nir_print_instr(&instr->instr, stderr);
1339          fprintf(stderr, "\n");
1340       }
1341       break;
1342    }
1343    case nir_op_fmax: {
1344       if (dst.size() == 1) {
1345          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true);
1346       } else if (dst.size() == 2) {
1347          bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1348                   get_alu_src(ctx, instr->src[0]),
1349                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1350       } else {
1351          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1352          nir_print_instr(&instr->instr, stderr);
1353          fprintf(stderr, "\n");
1354       }
1355       break;
1356    }
1357    case nir_op_fmin: {
1358       if (dst.size() == 1) {
1359          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true);
1360       } else if (dst.size() == 2) {
1361          bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1362                   get_alu_src(ctx, instr->src[0]),
1363                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1364       } else {
1365          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1366          nir_print_instr(&instr->instr, stderr);
1367          fprintf(stderr, "\n");
1368       }
1369       break;
1370    }
1371    case nir_op_fmax3: {
1372       if (dst.size() == 1) {
1373          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst);
1374       } else {
1375          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1376          nir_print_instr(&instr->instr, stderr);
1377          fprintf(stderr, "\n");
1378       }
1379       break;
1380    }
1381    case nir_op_fmin3: {
1382       if (dst.size() == 1) {
1383          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst);
1384       } else {
1385          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1386          nir_print_instr(&instr->instr, stderr);
1387          fprintf(stderr, "\n");
1388       }
1389       break;
1390    }
1391    case nir_op_fmed3: {
1392       if (dst.size() == 1) {
1393          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst);
1394       } else {
1395          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1396          nir_print_instr(&instr->instr, stderr);
1397          fprintf(stderr, "\n");
1398       }
1399       break;
1400    }
1401    case nir_op_umax3: {
1402       if (dst.size() == 1) {
1403          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1404       } else {
1405          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1406          nir_print_instr(&instr->instr, stderr);
1407          fprintf(stderr, "\n");
1408       }
1409       break;
1410    }
1411    case nir_op_umin3: {
1412       if (dst.size() == 1) {
1413          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1414       } else {
1415          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1416          nir_print_instr(&instr->instr, stderr);
1417          fprintf(stderr, "\n");
1418       }
1419       break;
1420    }
1421    case nir_op_umed3: {
1422       if (dst.size() == 1) {
1423          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1424       } else {
1425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1426          nir_print_instr(&instr->instr, stderr);
1427          fprintf(stderr, "\n");
1428       }
1429       break;
1430    }
1431    case nir_op_imax3: {
1432       if (dst.size() == 1) {
1433          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1434       } else {
1435          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1436          nir_print_instr(&instr->instr, stderr);
1437          fprintf(stderr, "\n");
1438       }
1439       break;
1440    }
1441    case nir_op_imin3: {
1442       if (dst.size() == 1) {
1443          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1444       } else {
1445          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1446          nir_print_instr(&instr->instr, stderr);
1447          fprintf(stderr, "\n");
1448       }
1449       break;
1450    }
1451    case nir_op_imed3: {
1452       if (dst.size() == 1) {
1453          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1454       } else {
1455          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1456          nir_print_instr(&instr->instr, stderr);
1457          fprintf(stderr, "\n");
1458       }
1459       break;
1460    }
1461    case nir_op_cube_face_coord: {
1462       Temp in = get_alu_src(ctx, instr->src[0], 3);
1463       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1464                       emit_extract_vector(ctx, in, 1, v1),
1465                       emit_extract_vector(ctx, in, 2, v1) };
1466       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1467       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1468       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1469       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1470       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1471       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1472       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1473       break;
1474    }
1475    case nir_op_cube_face_index: {
1476       Temp in = get_alu_src(ctx, instr->src[0], 3);
1477       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1478                       emit_extract_vector(ctx, in, 1, v1),
1479                       emit_extract_vector(ctx, in, 2, v1) };
1480       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1481       break;
1482    }
1483    case nir_op_bcsel: {
1484       emit_bcsel(ctx, instr, dst);
1485       break;
1486    }
1487    case nir_op_frsq: {
1488       if (dst.size() == 1) {
1489          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1490       } else if (dst.size() == 2) {
1491          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1492       } else {
1493          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1494          nir_print_instr(&instr->instr, stderr);
1495          fprintf(stderr, "\n");
1496       }
1497       break;
1498    }
1499    case nir_op_fneg: {
1500       Temp src = get_alu_src(ctx, instr->src[0]);
1501       if (dst.size() == 1) {
1502          if (ctx->block->fp_mode.must_flush_denorms32)
1503             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1504          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1505       } else if (dst.size() == 2) {
1506          if (ctx->block->fp_mode.must_flush_denorms16_64)
1507             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1508          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1509          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1510          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1511          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1512       } else {
1513          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1514          nir_print_instr(&instr->instr, stderr);
1515          fprintf(stderr, "\n");
1516       }
1517       break;
1518    }
1519    case nir_op_fabs: {
1520       Temp src = get_alu_src(ctx, instr->src[0]);
1521       if (dst.size() == 1) {
1522          if (ctx->block->fp_mode.must_flush_denorms32)
1523             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1524          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1525       } else if (dst.size() == 2) {
1526          if (ctx->block->fp_mode.must_flush_denorms16_64)
1527             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1528          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1529          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1530          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1531          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1532       } else {
1533          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1534          nir_print_instr(&instr->instr, stderr);
1535          fprintf(stderr, "\n");
1536       }
1537       break;
1538    }
1539    case nir_op_fsat: {
1540       Temp src = get_alu_src(ctx, instr->src[0]);
1541       if (dst.size() == 1) {
1542          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1543       } else if (dst.size() == 2) {
1544          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1545          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1546          vop3->clamp = true;
1547       } else {
1548          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1549          nir_print_instr(&instr->instr, stderr);
1550          fprintf(stderr, "\n");
1551       }
1552       break;
1553    }
1554    case nir_op_flog2: {
1555       if (dst.size() == 1) {
1556          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1557       } else {
1558          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1559          nir_print_instr(&instr->instr, stderr);
1560          fprintf(stderr, "\n");
1561       }
1562       break;
1563    }
1564    case nir_op_frcp: {
1565       if (dst.size() == 1) {
1566          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1567       } else if (dst.size() == 2) {
1568          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1569       } else {
1570          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1571          nir_print_instr(&instr->instr, stderr);
1572          fprintf(stderr, "\n");
1573       }
1574       break;
1575    }
1576    case nir_op_fexp2: {
1577       if (dst.size() == 1) {
1578          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1579       } else {
1580          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1581          nir_print_instr(&instr->instr, stderr);
1582          fprintf(stderr, "\n");
1583       }
1584       break;
1585    }
1586    case nir_op_fsqrt: {
1587       if (dst.size() == 1) {
1588          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1589       } else if (dst.size() == 2) {
1590          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1591       } else {
1592          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1593          nir_print_instr(&instr->instr, stderr);
1594          fprintf(stderr, "\n");
1595       }
1596       break;
1597    }
1598    case nir_op_ffract: {
1599       if (dst.size() == 1) {
1600          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1601       } else if (dst.size() == 2) {
1602          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1603       } else {
1604          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1605          nir_print_instr(&instr->instr, stderr);
1606          fprintf(stderr, "\n");
1607       }
1608       break;
1609    }
1610    case nir_op_ffloor: {
1611       if (dst.size() == 1) {
1612          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1613       } else if (dst.size() == 2) {
1614          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst);
1615       } else {
1616          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1617          nir_print_instr(&instr->instr, stderr);
1618          fprintf(stderr, "\n");
1619       }
1620       break;
1621    }
1622    case nir_op_fceil: {
1623       if (dst.size() == 1) {
1624          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1625       } else if (dst.size() == 2) {
1626          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1627       } else {
1628          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1629          nir_print_instr(&instr->instr, stderr);
1630          fprintf(stderr, "\n");
1631       }
1632       break;
1633    }
1634    case nir_op_ftrunc: {
1635       if (dst.size() == 1) {
1636          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1637       } else if (dst.size() == 2) {
1638          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f64, dst);
1639       } else {
1640          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1641          nir_print_instr(&instr->instr, stderr);
1642          fprintf(stderr, "\n");
1643       }
1644       break;
1645    }
1646    case nir_op_fround_even: {
1647       if (dst.size() == 1) {
1648          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1649       } else if (dst.size() == 2) {
1650          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1651       } else {
1652          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1653          nir_print_instr(&instr->instr, stderr);
1654          fprintf(stderr, "\n");
1655       }
1656       break;
1657    }
1658    case nir_op_fsin:
1659    case nir_op_fcos: {
1660       Temp src = get_alu_src(ctx, instr->src[0]);
1661       aco_ptr<Instruction> norm;
1662       if (dst.size() == 1) {
1663          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1664          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1665
1666          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1667          if (ctx->options->chip_class < GFX9)
1668             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1669
1670          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1671          bld.vop1(opcode, Definition(dst), tmp);
1672       } else {
1673          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1674          nir_print_instr(&instr->instr, stderr);
1675          fprintf(stderr, "\n");
1676       }
1677       break;
1678    }
1679    case nir_op_ldexp: {
1680       if (dst.size() == 1) {
1681          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1682                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1683                   get_alu_src(ctx, instr->src[1]));
1684       } else if (dst.size() == 2) {
1685          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1686                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1687                   get_alu_src(ctx, instr->src[1]));
1688       } else {
1689          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1690          nir_print_instr(&instr->instr, stderr);
1691          fprintf(stderr, "\n");
1692       }
1693       break;
1694    }
1695    case nir_op_frexp_sig: {
1696       if (dst.size() == 1) {
1697          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1698                   get_alu_src(ctx, instr->src[0]));
1699       } else if (dst.size() == 2) {
1700          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1701                   get_alu_src(ctx, instr->src[0]));
1702       } else {
1703          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1704          nir_print_instr(&instr->instr, stderr);
1705          fprintf(stderr, "\n");
1706       }
1707       break;
1708    }
1709    case nir_op_frexp_exp: {
1710       if (instr->src[0].src.ssa->bit_size == 32) {
1711          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1712                   get_alu_src(ctx, instr->src[0]));
1713       } else if (instr->src[0].src.ssa->bit_size == 64) {
1714          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1715                   get_alu_src(ctx, instr->src[0]));
1716       } else {
1717          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1718          nir_print_instr(&instr->instr, stderr);
1719          fprintf(stderr, "\n");
1720       }
1721       break;
1722    }
1723    case nir_op_fsign: {
1724       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1725       if (dst.size() == 1) {
1726          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1727          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1728          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1729          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1730       } else if (dst.size() == 2) {
1731          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1732          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1733          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1734
1735          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1736          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1737          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1738
1739          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1740       } else {
1741          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1742          nir_print_instr(&instr->instr, stderr);
1743          fprintf(stderr, "\n");
1744       }
1745       break;
1746    }
1747    case nir_op_f2f32: {
1748       if (instr->src[0].src.ssa->bit_size == 64) {
1749          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1750       } else {
1751          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1752          nir_print_instr(&instr->instr, stderr);
1753          fprintf(stderr, "\n");
1754       }
1755       break;
1756    }
1757    case nir_op_f2f64: {
1758       if (instr->src[0].src.ssa->bit_size == 32) {
1759          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1760       } else {
1761          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1762          nir_print_instr(&instr->instr, stderr);
1763          fprintf(stderr, "\n");
1764       }
1765       break;
1766    }
1767    case nir_op_i2f32: {
1768       assert(dst.size() == 1);
1769       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1770       break;
1771    }
1772    case nir_op_i2f64: {
1773       if (instr->src[0].src.ssa->bit_size == 32) {
1774          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1775       } else if (instr->src[0].src.ssa->bit_size == 64) {
1776          Temp src = get_alu_src(ctx, instr->src[0]);
1777          RegClass rc = RegClass(src.type(), 1);
1778          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1779          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1780          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1781          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1782          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1783          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1784
1785       } else {
1786          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1787          nir_print_instr(&instr->instr, stderr);
1788          fprintf(stderr, "\n");
1789       }
1790       break;
1791    }
1792    case nir_op_u2f32: {
1793       assert(dst.size() == 1);
1794       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1795       break;
1796    }
1797    case nir_op_u2f64: {
1798       if (instr->src[0].src.ssa->bit_size == 32) {
1799          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1800       } else if (instr->src[0].src.ssa->bit_size == 64) {
1801          Temp src = get_alu_src(ctx, instr->src[0]);
1802          RegClass rc = RegClass(src.type(), 1);
1803          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1804          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1805          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1806          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1807          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1808          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1809       } else {
1810          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1811          nir_print_instr(&instr->instr, stderr);
1812          fprintf(stderr, "\n");
1813       }
1814       break;
1815    }
1816    case nir_op_f2i32: {
1817       Temp src = get_alu_src(ctx, instr->src[0]);
1818       if (instr->src[0].src.ssa->bit_size == 32) {
1819          if (dst.type() == RegType::vgpr)
1820             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1821          else
1822             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1823                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1824
1825       } else if (instr->src[0].src.ssa->bit_size == 64) {
1826          if (dst.type() == RegType::vgpr)
1827             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1828          else
1829             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1830                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1831
1832       } else {
1833          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1834          nir_print_instr(&instr->instr, stderr);
1835          fprintf(stderr, "\n");
1836       }
1837       break;
1838    }
1839    case nir_op_f2u32: {
1840       Temp src = get_alu_src(ctx, instr->src[0]);
1841       if (instr->src[0].src.ssa->bit_size == 32) {
1842          if (dst.type() == RegType::vgpr)
1843             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
1844          else
1845             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1846                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
1847
1848       } else if (instr->src[0].src.ssa->bit_size == 64) {
1849          if (dst.type() == RegType::vgpr)
1850             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
1851          else
1852             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1853                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
1854
1855       } else {
1856          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1857          nir_print_instr(&instr->instr, stderr);
1858          fprintf(stderr, "\n");
1859       }
1860       break;
1861    }
1862    case nir_op_f2i64: {
1863       Temp src = get_alu_src(ctx, instr->src[0]);
1864       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1865          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1866          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
1867          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1868          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
1869          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1870          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
1871          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1872          Temp new_exponent = bld.tmp(v1);
1873          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
1874          if (ctx->program->chip_class >= GFX8)
1875             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
1876          else
1877             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
1878          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
1879          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1880          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1881          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
1882          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
1883          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
1884          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
1885          Temp new_lower = bld.tmp(v1);
1886          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
1887          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
1888          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
1889
1890       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1891          if (src.type() == RegType::vgpr)
1892             src = bld.as_uniform(src);
1893          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1894          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1895          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1896          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
1897          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1898          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
1899          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1900          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
1901          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1902          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
1903          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
1904          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
1905          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
1906          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
1907          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1908          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1909          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
1910          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
1911          Temp borrow = bld.tmp(s1);
1912          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
1913          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
1914          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1915
1916       } else if (instr->src[0].src.ssa->bit_size == 64) {
1917          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1918          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1919          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1920          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1921          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1922          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1923          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1924          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
1925          if (dst.type() == RegType::sgpr) {
1926             lower = bld.as_uniform(lower);
1927             upper = bld.as_uniform(upper);
1928          }
1929          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1930
1931       } else {
1932          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1933          nir_print_instr(&instr->instr, stderr);
1934          fprintf(stderr, "\n");
1935       }
1936       break;
1937    }
1938    case nir_op_f2u64: {
1939       Temp src = get_alu_src(ctx, instr->src[0]);
1940       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1941          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1942          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
1943          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
1944          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1945          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1946          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
1947          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
1948          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1949          Temp new_exponent = bld.tmp(v1);
1950          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
1951          if (ctx->program->chip_class >= GFX8)
1952             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
1953          else
1954             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
1955          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1956          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1957          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
1958          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
1959          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
1960          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
1961          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1962
1963       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1964          if (src.type() == RegType::vgpr)
1965             src = bld.as_uniform(src);
1966          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1967          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1968          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1969          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1970          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1971          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
1972          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
1973          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1974          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
1975          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
1976          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
1977          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
1978          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1979          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1980          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
1981          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
1982          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
1983          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1984
1985       } else if (instr->src[0].src.ssa->bit_size == 64) {
1986          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1987          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1988          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1989          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1990          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1991          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1992          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1993          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
1994          if (dst.type() == RegType::sgpr) {
1995             lower = bld.as_uniform(lower);
1996             upper = bld.as_uniform(upper);
1997          }
1998          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1999
2000       } else {
2001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2002          nir_print_instr(&instr->instr, stderr);
2003          fprintf(stderr, "\n");
2004       }
2005       break;
2006    }
2007    case nir_op_b2f32: {
2008       Temp src = get_alu_src(ctx, instr->src[0]);
2009       assert(src.regClass() == bld.lm);
2010
2011       if (dst.regClass() == s1) {
2012          src = bool_to_scalar_condition(ctx, src);
2013          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2014       } else if (dst.regClass() == v1) {
2015          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2016       } else {
2017          unreachable("Wrong destination register class for nir_op_b2f32.");
2018       }
2019       break;
2020    }
2021    case nir_op_b2f64: {
2022       Temp src = get_alu_src(ctx, instr->src[0]);
2023       assert(src.regClass() == bld.lm);
2024
2025       if (dst.regClass() == s2) {
2026          src = bool_to_scalar_condition(ctx, src);
2027          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2028       } else if (dst.regClass() == v2) {
2029          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2030          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2031          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2032       } else {
2033          unreachable("Wrong destination register class for nir_op_b2f64.");
2034       }
2035       break;
2036    }
2037    case nir_op_i2i32: {
2038       Temp src = get_alu_src(ctx, instr->src[0]);
2039       if (instr->src[0].src.ssa->bit_size == 64) {
2040          /* we can actually just say dst = src, as it would map the lower register */
2041          emit_extract_vector(ctx, src, 0, dst);
2042       } else {
2043          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2044          nir_print_instr(&instr->instr, stderr);
2045          fprintf(stderr, "\n");
2046       }
2047       break;
2048    }
2049    case nir_op_u2u32: {
2050       Temp src = get_alu_src(ctx, instr->src[0]);
2051       if (instr->src[0].src.ssa->bit_size == 16) {
2052          if (dst.regClass() == s1) {
2053             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2054          } else {
2055             // TODO: do better with SDWA
2056             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2057          }
2058       } else if (instr->src[0].src.ssa->bit_size == 64) {
2059          /* we can actually just say dst = src, as it would map the lower register */
2060          emit_extract_vector(ctx, src, 0, dst);
2061       } else {
2062          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2063          nir_print_instr(&instr->instr, stderr);
2064          fprintf(stderr, "\n");
2065       }
2066       break;
2067    }
2068    case nir_op_i2i64: {
2069       Temp src = get_alu_src(ctx, instr->src[0]);
2070       if (src.regClass() == s1) {
2071          Temp high = bld.sopc(aco_opcode::s_ashr_i32, bld.def(s1, scc), src, Operand(31u));
2072          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2073       } else if (src.regClass() == v1) {
2074          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2075          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2076       } else {
2077          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2078          nir_print_instr(&instr->instr, stderr);
2079          fprintf(stderr, "\n");
2080       }
2081       break;
2082    }
2083    case nir_op_u2u64: {
2084       Temp src = get_alu_src(ctx, instr->src[0]);
2085       if (instr->src[0].src.ssa->bit_size == 32) {
2086          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_b2i32: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       assert(src.regClass() == bld.lm);
2097
2098       if (dst.regClass() == s1) {
2099          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2100          bool_to_scalar_condition(ctx, src, dst);
2101       } else if (dst.regClass() == v1) {
2102          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2103       } else {
2104          unreachable("Invalid register class for b2i32");
2105       }
2106       break;
2107    }
2108    case nir_op_i2b1: {
2109       Temp src = get_alu_src(ctx, instr->src[0]);
2110       assert(dst.regClass() == bld.lm);
2111
2112       if (src.type() == RegType::vgpr) {
2113          assert(src.regClass() == v1 || src.regClass() == v2);
2114          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2115                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2116       } else {
2117          assert(src.regClass() == s1 || src.regClass() == s2);
2118          Temp tmp;
2119          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2120             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2121          } else {
2122             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2123                            bld.scc(bld.def(s1)), Operand(0u), src);
2124          }
2125          bool_to_vector_condition(ctx, tmp, dst);
2126       }
2127       break;
2128    }
2129    case nir_op_pack_64_2x32_split: {
2130       Temp src0 = get_alu_src(ctx, instr->src[0]);
2131       Temp src1 = get_alu_src(ctx, instr->src[1]);
2132
2133       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2134       break;
2135    }
2136    case nir_op_unpack_64_2x32_split_x:
2137       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2138       break;
2139    case nir_op_unpack_64_2x32_split_y:
2140       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2141       break;
2142    case nir_op_pack_half_2x16: {
2143       Temp src = get_alu_src(ctx, instr->src[0], 2);
2144
2145       if (dst.regClass() == v1) {
2146          Temp src0 = bld.tmp(v1);
2147          Temp src1 = bld.tmp(v1);
2148          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2149          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2150             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2151          else
2152             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2153                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2154                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2155       } else {
2156          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2157          nir_print_instr(&instr->instr, stderr);
2158          fprintf(stderr, "\n");
2159       }
2160       break;
2161    }
2162    case nir_op_unpack_half_2x16_split_x: {
2163       if (dst.regClass() == v1) {
2164          Builder bld(ctx->program, ctx->block);
2165          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2166       } else {
2167          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2168          nir_print_instr(&instr->instr, stderr);
2169          fprintf(stderr, "\n");
2170       }
2171       break;
2172    }
2173    case nir_op_unpack_half_2x16_split_y: {
2174       if (dst.regClass() == v1) {
2175          Builder bld(ctx->program, ctx->block);
2176          /* TODO: use SDWA here */
2177          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2178                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2179       } else {
2180          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2181          nir_print_instr(&instr->instr, stderr);
2182          fprintf(stderr, "\n");
2183       }
2184       break;
2185    }
2186    case nir_op_fquantize2f16: {
2187       Temp src = get_alu_src(ctx, instr->src[0]);
2188       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2189       Temp f32, cmp_res;
2190
2191       if (ctx->program->chip_class >= GFX8) {
2192          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2193          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2194          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2195       } else {
2196          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2197           * so compare the result and flush to 0 if it's smaller.
2198           */
2199          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2200          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2201          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(s2)), f32, smallest);
2202          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2203          cmp_res = vop3->definitions[0].getTemp();
2204       }
2205
2206       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2207          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2208          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2209       } else {
2210          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2211       }
2212       break;
2213    }
2214    case nir_op_bfm: {
2215       Temp bits = get_alu_src(ctx, instr->src[0]);
2216       Temp offset = get_alu_src(ctx, instr->src[1]);
2217
2218       if (dst.regClass() == s1) {
2219          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2220       } else if (dst.regClass() == v1) {
2221          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2222       } else {
2223          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2224          nir_print_instr(&instr->instr, stderr);
2225          fprintf(stderr, "\n");
2226       }
2227       break;
2228    }
2229    case nir_op_bitfield_select: {
2230       /* (mask & insert) | (~mask & base) */
2231       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2232       Temp insert = get_alu_src(ctx, instr->src[1]);
2233       Temp base = get_alu_src(ctx, instr->src[2]);
2234
2235       /* dst = (insert & bitmask) | (base & ~bitmask) */
2236       if (dst.regClass() == s1) {
2237          aco_ptr<Instruction> sop2;
2238          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2239          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2240          Operand lhs;
2241          if (const_insert && const_bitmask) {
2242             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2243          } else {
2244             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2245             lhs = Operand(insert);
2246          }
2247
2248          Operand rhs;
2249          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2250          if (const_base && const_bitmask) {
2251             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2252          } else {
2253             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2254             rhs = Operand(base);
2255          }
2256
2257          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2258
2259       } else if (dst.regClass() == v1) {
2260          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2261             base = as_vgpr(ctx, base);
2262          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2263             insert = as_vgpr(ctx, insert);
2264
2265          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2266
2267       } else {
2268          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2269          nir_print_instr(&instr->instr, stderr);
2270          fprintf(stderr, "\n");
2271       }
2272       break;
2273    }
2274    case nir_op_ubfe:
2275    case nir_op_ibfe: {
2276       Temp base = get_alu_src(ctx, instr->src[0]);
2277       Temp offset = get_alu_src(ctx, instr->src[1]);
2278       Temp bits = get_alu_src(ctx, instr->src[2]);
2279
2280       if (dst.type() == RegType::sgpr) {
2281          Operand extract;
2282          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2283          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2284          if (const_offset && const_bits) {
2285             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2286             extract = Operand(const_extract);
2287          } else {
2288             Operand width;
2289             if (const_bits) {
2290                width = Operand(const_bits->u32 << 16);
2291             } else {
2292                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2293             }
2294             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2295          }
2296
2297          aco_opcode opcode;
2298          if (dst.regClass() == s1) {
2299             if (instr->op == nir_op_ubfe)
2300                opcode = aco_opcode::s_bfe_u32;
2301             else
2302                opcode = aco_opcode::s_bfe_i32;
2303          } else if (dst.regClass() == s2) {
2304             if (instr->op == nir_op_ubfe)
2305                opcode = aco_opcode::s_bfe_u64;
2306             else
2307                opcode = aco_opcode::s_bfe_i64;
2308          } else {
2309             unreachable("Unsupported BFE bit size");
2310          }
2311
2312          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2313
2314       } else {
2315          aco_opcode opcode;
2316          if (dst.regClass() == v1) {
2317             if (instr->op == nir_op_ubfe)
2318                opcode = aco_opcode::v_bfe_u32;
2319             else
2320                opcode = aco_opcode::v_bfe_i32;
2321          } else {
2322             unreachable("Unsupported BFE bit size");
2323          }
2324
2325          emit_vop3a_instruction(ctx, instr, opcode, dst);
2326       }
2327       break;
2328    }
2329    case nir_op_bit_count: {
2330       Temp src = get_alu_src(ctx, instr->src[0]);
2331       if (src.regClass() == s1) {
2332          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2333       } else if (src.regClass() == v1) {
2334          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2335       } else if (src.regClass() == v2) {
2336          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2337                   emit_extract_vector(ctx, src, 1, v1),
2338                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2339                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2340       } else if (src.regClass() == s2) {
2341          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2342       } else {
2343          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2344          nir_print_instr(&instr->instr, stderr);
2345          fprintf(stderr, "\n");
2346       }
2347       break;
2348    }
2349    case nir_op_flt: {
2350       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2351       break;
2352    }
2353    case nir_op_fge: {
2354       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2355       break;
2356    }
2357    case nir_op_feq: {
2358       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2359       break;
2360    }
2361    case nir_op_fne: {
2362       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2363       break;
2364    }
2365    case nir_op_ilt: {
2366       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2367       break;
2368    }
2369    case nir_op_ige: {
2370       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2371       break;
2372    }
2373    case nir_op_ieq: {
2374       if (instr->src[0].src.ssa->bit_size == 1)
2375          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2376       else
2377          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32, aco_opcode::s_cmp_eq_u64);
2378       break;
2379    }
2380    case nir_op_ine: {
2381       if (instr->src[0].src.ssa->bit_size == 1)
2382          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2383       else
2384          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32, aco_opcode::s_cmp_lg_u64);
2385       break;
2386    }
2387    case nir_op_ult: {
2388       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2389       break;
2390    }
2391    case nir_op_uge: {
2392       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2393       break;
2394    }
2395    case nir_op_fddx:
2396    case nir_op_fddy:
2397    case nir_op_fddx_fine:
2398    case nir_op_fddy_fine:
2399    case nir_op_fddx_coarse:
2400    case nir_op_fddy_coarse: {
2401       Temp src = get_alu_src(ctx, instr->src[0]);
2402       uint16_t dpp_ctrl1, dpp_ctrl2;
2403       if (instr->op == nir_op_fddx_fine) {
2404          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2405          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2406       } else if (instr->op == nir_op_fddy_fine) {
2407          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2408          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2409       } else {
2410          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2411          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2412             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2413          else
2414             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2415       }
2416
2417       Temp tmp;
2418       if (ctx->program->chip_class >= GFX8) {
2419          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2420          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2421       } else {
2422          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2423          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2424          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2425       }
2426       emit_wqm(ctx, tmp, dst, true);
2427       break;
2428    }
2429    default:
2430       fprintf(stderr, "Unknown NIR ALU instr: ");
2431       nir_print_instr(&instr->instr, stderr);
2432       fprintf(stderr, "\n");
2433    }
2434 }
2435
2436 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2437 {
2438    Temp dst = get_ssa_temp(ctx, &instr->def);
2439
2440    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2441    // which get truncated the lsb if double and msb if int
2442    // for now, we only use s_mov_b64 with 64bit inline constants
2443    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2444    assert(dst.type() == RegType::sgpr);
2445
2446    Builder bld(ctx->program, ctx->block);
2447
2448    if (instr->def.bit_size == 1) {
2449       assert(dst.regClass() == bld.lm);
2450       int val = instr->value[0].b ? -1 : 0;
2451       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2452       bld.sop1(Builder::s_mov, Definition(dst), op);
2453    } else if (dst.size() == 1) {
2454       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2455    } else {
2456       assert(dst.size() != 1);
2457       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2458       if (instr->def.bit_size == 64)
2459          for (unsigned i = 0; i < dst.size(); i++)
2460             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2461       else {
2462          for (unsigned i = 0; i < dst.size(); i++)
2463             vec->operands[i] = Operand{instr->value[i].u32};
2464       }
2465       vec->definitions[0] = Definition(dst);
2466       ctx->block->instructions.emplace_back(std::move(vec));
2467    }
2468 }
2469
2470 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2471 {
2472    uint32_t new_mask = 0;
2473    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2474       if (mask & (1u << i))
2475          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2476    return new_mask;
2477 }
2478
2479 void visit_store_vs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2480 {
2481    /* This wouldn't work inside control flow or with indirect offsets but
2482     * that doesn't happen because of nir_lower_io_to_temporaries(). */
2483
2484    unsigned write_mask = nir_intrinsic_write_mask(instr);
2485    unsigned component = nir_intrinsic_component(instr);
2486    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2487    unsigned idx = nir_intrinsic_base(instr) + component;
2488
2489    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2490    if (off_instr->type != nir_instr_type_load_const) {
2491       fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2492       nir_print_instr(off_instr, stderr);
2493       fprintf(stderr, "\n");
2494    }
2495    idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2496
2497    if (instr->src[0].ssa->bit_size == 64)
2498       write_mask = widen_mask(write_mask, 2);
2499
2500    for (unsigned i = 0; i < 8; ++i) {
2501       if (write_mask & (1 << i)) {
2502          ctx->vs_output.mask[idx / 4u] |= 1 << (idx % 4u);
2503          ctx->vs_output.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2504       }
2505       idx++;
2506    }
2507 }
2508
2509 void visit_store_fs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2510 {
2511    Builder bld(ctx->program, ctx->block);
2512    unsigned write_mask = nir_intrinsic_write_mask(instr);
2513    Operand values[4];
2514    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2515    for (unsigned i = 0; i < 4; ++i) {
2516       if (write_mask & (1 << i)) {
2517          Temp tmp = emit_extract_vector(ctx, src, i, v1);
2518          values[i] = Operand(tmp);
2519       } else {
2520          values[i] = Operand(v1);
2521       }
2522    }
2523
2524    unsigned index = nir_intrinsic_base(instr) / 4;
2525    unsigned target, col_format;
2526    unsigned enabled_channels = 0xF;
2527    aco_opcode compr_op = (aco_opcode)0;
2528
2529    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2530    assert(offset && "Non-const offsets on exports not yet supported");
2531    index += offset->u32;
2532
2533    assert(index != FRAG_RESULT_COLOR);
2534
2535    /* Unlike vertex shader exports, it's fine to use multiple exports to
2536     * export separate channels of one target. So shaders which export both
2537     * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2538     * TODO: combine the exports in those cases and create better code
2539     */
2540
2541    if (index == FRAG_RESULT_SAMPLE_MASK) {
2542
2543       if (ctx->program->info->ps.writes_z) {
2544          target = V_008DFC_SQ_EXP_MRTZ;
2545          enabled_channels = 0x4;
2546          col_format = (unsigned) -1;
2547
2548          values[2] = values[0];
2549          values[0] = Operand(v1);
2550       } else {
2551          bld.exp(aco_opcode::exp, Operand(v1), Operand(values[0]), Operand(v1), Operand(v1),
2552                  0xc, V_008DFC_SQ_EXP_MRTZ, true);
2553          return;
2554       }
2555
2556    } else if (index == FRAG_RESULT_DEPTH) {
2557
2558       target = V_008DFC_SQ_EXP_MRTZ;
2559       enabled_channels = 0x1;
2560       col_format = (unsigned) -1;
2561
2562    } else if (index == FRAG_RESULT_STENCIL) {
2563
2564       if (ctx->program->info->ps.writes_z) {
2565          target = V_008DFC_SQ_EXP_MRTZ;
2566          enabled_channels = 0x2;
2567          col_format = (unsigned) -1;
2568
2569          values[1] = values[0];
2570          values[0] = Operand(v1);
2571       } else {
2572          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
2573          bld.exp(aco_opcode::exp, values[0], Operand(v1), Operand(v1), Operand(v1),
2574                  0x3, V_008DFC_SQ_EXP_MRTZ, true);
2575          return;
2576       }
2577
2578    } else {
2579       index -= FRAG_RESULT_DATA0;
2580       target = V_008DFC_SQ_EXP_MRT + index;
2581       col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2582    }
2583    bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2584    bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2585
2586    switch (col_format)
2587    {
2588    case V_028714_SPI_SHADER_ZERO:
2589       enabled_channels = 0; /* writemask */
2590       target = V_008DFC_SQ_EXP_NULL;
2591       break;
2592
2593    case V_028714_SPI_SHADER_32_R:
2594       enabled_channels = 1;
2595       break;
2596
2597    case V_028714_SPI_SHADER_32_GR:
2598       enabled_channels = 0x3;
2599       break;
2600
2601    case V_028714_SPI_SHADER_32_AR:
2602       if (ctx->options->chip_class >= GFX10) {
2603          /* Special case: on GFX10, the outputs are different for 32_AR */
2604          enabled_channels = 0x3;
2605          values[1] = values[3];
2606          values[3] = Operand(v1);
2607       } else {
2608          enabled_channels = 0x9;
2609       }
2610       break;
2611
2612    case V_028714_SPI_SHADER_FP16_ABGR:
2613       enabled_channels = 0x5;
2614       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
2615       break;
2616
2617    case V_028714_SPI_SHADER_UNORM16_ABGR:
2618       enabled_channels = 0x5;
2619       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
2620       break;
2621
2622    case V_028714_SPI_SHADER_SNORM16_ABGR:
2623       enabled_channels = 0x5;
2624       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
2625       break;
2626
2627    case V_028714_SPI_SHADER_UINT16_ABGR: {
2628       enabled_channels = 0x5;
2629       compr_op = aco_opcode::v_cvt_pk_u16_u32;
2630       if (is_int8 || is_int10) {
2631          /* clamp */
2632          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
2633          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
2634
2635          for (unsigned i = 0; i < 4; i++) {
2636             if ((write_mask >> i) & 1) {
2637                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
2638                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
2639                                     values[i]);
2640             }
2641          }
2642       }
2643       break;
2644    }
2645
2646    case V_028714_SPI_SHADER_SINT16_ABGR:
2647       enabled_channels = 0x5;
2648       compr_op = aco_opcode::v_cvt_pk_i16_i32;
2649       if (is_int8 || is_int10) {
2650          /* clamp */
2651          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
2652          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
2653          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
2654          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
2655
2656          for (unsigned i = 0; i < 4; i++) {
2657             if ((write_mask >> i) & 1) {
2658                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
2659                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
2660                                     values[i]);
2661                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
2662                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
2663                                     values[i]);
2664             }
2665          }
2666       }
2667       break;
2668
2669    case V_028714_SPI_SHADER_32_ABGR:
2670       enabled_channels = 0xF;
2671       break;
2672
2673    default:
2674       break;
2675    }
2676
2677    if (target == V_008DFC_SQ_EXP_NULL)
2678       return;
2679
2680    if ((bool) compr_op) {
2681       for (int i = 0; i < 2; i++) {
2682          /* check if at least one of the values to be compressed is enabled */
2683          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
2684          if (enabled) {
2685             enabled_channels |= enabled << (i*2);
2686             values[i] = bld.vop3(compr_op, bld.def(v1),
2687                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
2688                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
2689          } else {
2690             values[i] = Operand(v1);
2691          }
2692       }
2693       values[2] = Operand(v1);
2694       values[3] = Operand(v1);
2695    } else {
2696       for (int i = 0; i < 4; i++)
2697          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
2698    }
2699
2700    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
2701            enabled_channels, target, (bool) compr_op);
2702 }
2703
2704 Operand load_lds_size_m0(isel_context *ctx)
2705 {
2706    /* TODO: m0 does not need to be initialized on GFX9+ */
2707    Builder bld(ctx->program, ctx->block);
2708    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2709 }
2710
2711 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2712               Temp address, unsigned base_offset, unsigned align)
2713 {
2714    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2715
2716    Builder bld(ctx->program, ctx->block);
2717
2718    Operand m = load_lds_size_m0(ctx);
2719
2720    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2721    unsigned bytes_read = 0;
2722    unsigned result_size = 0;
2723    unsigned total_bytes = num_components * elem_size_bytes;
2724    std::array<Temp, 4> result;
2725
2726    while (bytes_read < total_bytes) {
2727       unsigned todo = total_bytes - bytes_read;
2728       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2729       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2730
2731       aco_opcode op = aco_opcode::last_opcode;
2732       bool read2 = false;
2733       if (todo >= 16 && aligned16) {
2734          op = aco_opcode::ds_read_b128;
2735          todo = 16;
2736       } else if (todo >= 16 && aligned8) {
2737          op = aco_opcode::ds_read2_b64;
2738          read2 = true;
2739          todo = 16;
2740       } else if (todo >= 12 && aligned16) {
2741          op = aco_opcode::ds_read_b96;
2742          todo = 12;
2743       } else if (todo >= 8 && aligned8) {
2744          op = aco_opcode::ds_read_b64;
2745          todo = 8;
2746       } else if (todo >= 8) {
2747          op = aco_opcode::ds_read2_b32;
2748          read2 = true;
2749          todo = 8;
2750       } else if (todo >= 4) {
2751          op = aco_opcode::ds_read_b32;
2752          todo = 4;
2753       } else {
2754          assert(false);
2755       }
2756       assert(todo % elem_size_bytes == 0);
2757       unsigned num_elements = todo / elem_size_bytes;
2758       unsigned offset = base_offset + bytes_read;
2759       unsigned max_offset = read2 ? 1019 : 65535;
2760
2761       Temp address_offset = address;
2762       if (offset > max_offset) {
2763          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2764          offset = bytes_read;
2765       }
2766       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2767
2768       Temp res;
2769       if (num_components == 1 && dst.type() == RegType::vgpr)
2770          res = dst;
2771       else
2772          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2773
2774       if (read2)
2775          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2776       else
2777          res = bld.ds(op, Definition(res), address_offset, m, offset);
2778
2779       if (num_components == 1) {
2780          assert(todo == total_bytes);
2781          if (dst.type() == RegType::sgpr)
2782             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2783          return;
2784       }
2785
2786       if (dst.type() == RegType::sgpr)
2787          res = bld.as_uniform(res);
2788
2789       if (num_elements == 1) {
2790          result[result_size++] = res;
2791       } else {
2792          assert(res != dst && res.size() % num_elements == 0);
2793          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2794          split->operands[0] = Operand(res);
2795          for (unsigned i = 0; i < num_elements; i++)
2796             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2797          ctx->block->instructions.emplace_back(std::move(split));
2798       }
2799
2800       bytes_read += todo;
2801    }
2802
2803    assert(result_size == num_components && result_size > 1);
2804    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2805    for (unsigned i = 0; i < result_size; i++)
2806       vec->operands[i] = Operand(result[i]);
2807    vec->definitions[0] = Definition(dst);
2808    ctx->block->instructions.emplace_back(std::move(vec));
2809    ctx->allocated_vec.emplace(dst.id(), result);
2810 }
2811
2812 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2813 {
2814    if (start == 0 && size == data.size())
2815       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2816
2817    unsigned size_hint = 1;
2818    auto it = ctx->allocated_vec.find(data.id());
2819    if (it != ctx->allocated_vec.end())
2820       size_hint = it->second[0].size();
2821    if (size % size_hint || start % size_hint)
2822       size_hint = 1;
2823
2824    start /= size_hint;
2825    size /= size_hint;
2826
2827    Temp elems[size];
2828    for (unsigned i = 0; i < size; i++)
2829       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2830
2831    if (size == 1)
2832       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2833
2834    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2835    for (unsigned i = 0; i < size; i++)
2836       vec->operands[i] = Operand(elems[i]);
2837    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2838    vec->definitions[0] = Definition(res);
2839    ctx->block->instructions.emplace_back(std::move(vec));
2840    return res;
2841 }
2842
2843 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2844 {
2845    Builder bld(ctx->program, ctx->block);
2846    unsigned bytes_written = 0;
2847    while (bytes_written < total_size * 4) {
2848       unsigned todo = total_size * 4 - bytes_written;
2849       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2850       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2851
2852       aco_opcode op = aco_opcode::last_opcode;
2853       bool write2 = false;
2854       unsigned size = 0;
2855       if (todo >= 16 && aligned16) {
2856          op = aco_opcode::ds_write_b128;
2857          size = 4;
2858       } else if (todo >= 16 && aligned8) {
2859          op = aco_opcode::ds_write2_b64;
2860          write2 = true;
2861          size = 4;
2862       } else if (todo >= 12 && aligned16) {
2863          op = aco_opcode::ds_write_b96;
2864          size = 3;
2865       } else if (todo >= 8 && aligned8) {
2866          op = aco_opcode::ds_write_b64;
2867          size = 2;
2868       } else if (todo >= 8) {
2869          op = aco_opcode::ds_write2_b32;
2870          write2 = true;
2871          size = 2;
2872       } else if (todo >= 4) {
2873          op = aco_opcode::ds_write_b32;
2874          size = 1;
2875       } else {
2876          assert(false);
2877       }
2878
2879       unsigned offset = offset0 + offset1 + bytes_written;
2880       unsigned max_offset = write2 ? 1020 : 65535;
2881       Temp address_offset = address;
2882       if (offset > max_offset) {
2883          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2884          offset = offset1 + bytes_written;
2885       }
2886       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2887
2888       if (write2) {
2889          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2890          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2891          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2892       } else {
2893          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2894          bld.ds(op, address_offset, val, m, offset);
2895       }
2896
2897       bytes_written += size * 4;
2898    }
2899 }
2900
2901 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2902                Temp address, unsigned base_offset, unsigned align)
2903 {
2904    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2905
2906    Operand m = load_lds_size_m0(ctx);
2907
2908    /* we need at most two stores for 32bit variables */
2909    int start[2], count[2];
2910    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2911    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2912    assert(wrmask == 0);
2913
2914    /* one combined store is sufficient */
2915    if (count[0] == count[1]) {
2916       Builder bld(ctx->program, ctx->block);
2917
2918       Temp address_offset = address;
2919       if ((base_offset >> 2) + start[1] > 255) {
2920          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2921          base_offset = 0;
2922       }
2923
2924       assert(count[0] == 1);
2925       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2926       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2927       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2928       base_offset = base_offset / elem_size_bytes;
2929       bld.ds(op, address_offset, val0, val1, m,
2930              base_offset + start[0], base_offset + start[1]);
2931       return;
2932    }
2933
2934    for (unsigned i = 0; i < 2; i++) {
2935       if (count[i] == 0)
2936          continue;
2937
2938       unsigned elem_size_words = elem_size_bytes / 4;
2939       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2940                       base_offset, start[i] * elem_size_bytes, align);
2941    }
2942    return;
2943 }
2944
2945 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2946 {
2947    if (ctx->stage == vertex_vs) {
2948       visit_store_vs_output(ctx, instr);
2949    } else if (ctx->stage == fragment_fs) {
2950       visit_store_fs_output(ctx, instr);
2951    } else {
2952       unreachable("Shader stage not implemented");
2953    }
2954 }
2955
2956 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
2957 {
2958    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
2959    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
2960
2961    Builder bld(ctx->program, ctx->block);
2962    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
2963    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
2964 }
2965
2966 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
2967 {
2968    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
2969    for (unsigned i = 0; i < num_components; i++)
2970       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
2971    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
2972       assert(num_components == 4);
2973       Builder bld(ctx->program, ctx->block);
2974       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
2975    }
2976
2977    for (Operand& op : vec->operands)
2978       op = op.isUndefined() ? Operand(0u) : op;
2979
2980    vec->definitions[0] = Definition(dst);
2981    ctx->block->instructions.emplace_back(std::move(vec));
2982    emit_split_vector(ctx, dst, num_components);
2983    return;
2984 }
2985
2986 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
2987 {
2988    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2989    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
2990    unsigned idx = nir_intrinsic_base(instr);
2991    unsigned component = nir_intrinsic_component(instr);
2992    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
2993
2994    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2995    if (offset) {
2996       assert(offset->u32 == 0);
2997    } else {
2998       /* the lower 15bit of the prim_mask contain the offset into LDS
2999        * while the upper bits contain the number of prims */
3000       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3001       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3002       Builder bld(ctx->program, ctx->block);
3003       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3004       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3005       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3006       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3007       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3008    }
3009
3010    if (instr->dest.ssa.num_components == 1) {
3011       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3012    } else {
3013       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3014       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3015       {
3016          Temp tmp = {ctx->program->allocateId(), v1};
3017          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3018          vec->operands[i] = Operand(tmp);
3019       }
3020       vec->definitions[0] = Definition(dst);
3021       ctx->block->instructions.emplace_back(std::move(vec));
3022    }
3023 }
3024
3025 unsigned get_num_channels_from_data_format(unsigned data_format)
3026 {
3027    switch (data_format) {
3028    case V_008F0C_BUF_DATA_FORMAT_8:
3029    case V_008F0C_BUF_DATA_FORMAT_16:
3030    case V_008F0C_BUF_DATA_FORMAT_32:
3031       return 1;
3032    case V_008F0C_BUF_DATA_FORMAT_8_8:
3033    case V_008F0C_BUF_DATA_FORMAT_16_16:
3034    case V_008F0C_BUF_DATA_FORMAT_32_32:
3035       return 2;
3036    case V_008F0C_BUF_DATA_FORMAT_10_11_11:
3037    case V_008F0C_BUF_DATA_FORMAT_11_11_10:
3038    case V_008F0C_BUF_DATA_FORMAT_32_32_32:
3039       return 3;
3040    case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
3041    case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
3042    case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
3043    case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
3044    case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
3045       return 4;
3046    default:
3047       break;
3048    }
3049
3050    return 4;
3051 }
3052
3053 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3054  * so we may need to fix it up. */
3055 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3056 {
3057    Builder bld(ctx->program, ctx->block);
3058
3059    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3060       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3061
3062    /* For the integer-like cases, do a natural sign extension.
3063     *
3064     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3065     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3066     * exponent.
3067     */
3068    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3069    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3070
3071    /* Convert back to the right type. */
3072    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3073       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3074       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3075       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3076    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3077       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3078    }
3079
3080    return alpha;
3081 }
3082
3083 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3084 {
3085    Builder bld(ctx->program, ctx->block);
3086    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3087    if (ctx->stage & sw_vs) {
3088
3089       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3090       if (off_instr->type != nir_instr_type_load_const) {
3091          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3092          nir_print_instr(off_instr, stderr);
3093          fprintf(stderr, "\n");
3094       }
3095       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3096
3097       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3098
3099       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3100       unsigned component = nir_intrinsic_component(instr);
3101       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3102       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3103       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3104       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3105
3106       unsigned dfmt = attrib_format & 0xf;
3107
3108       unsigned nfmt = (attrib_format >> 4) & 0x7;
3109       unsigned num_dfmt_channels = get_num_channels_from_data_format(dfmt);
3110       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3111       unsigned num_channels = MIN2(util_last_bit(mask), num_dfmt_channels);
3112       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3113       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3114       if (post_shuffle)
3115          num_channels = MAX2(num_channels, 3);
3116
3117       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, Operand(attrib_binding * 16u));
3118
3119       Temp index;
3120       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3121          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3122          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3123          if (divisor) {
3124             ctx->needs_instance_id = true;
3125             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3126             if (divisor != 1) {
3127                Temp divided = bld.tmp(v1);
3128                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3129                index = bld.vadd32(bld.def(v1), start_instance, divided);
3130             } else {
3131                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3132             }
3133          } else {
3134             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3135          }
3136       } else {
3137          index = bld.vadd32(bld.def(v1),
3138                             get_arg(ctx, ctx->args->ac.base_vertex),
3139                             get_arg(ctx, ctx->args->ac.vertex_id));
3140       }
3141
3142       if (attrib_stride != 0 && attrib_offset > attrib_stride) {
3143          index = bld.vadd32(bld.def(v1), Operand(attrib_offset / attrib_stride), index);
3144          attrib_offset = attrib_offset % attrib_stride;
3145       }
3146
3147       Operand soffset(0u);
3148       if (attrib_offset >= 4096) {
3149          soffset = bld.copy(bld.def(s1), Operand(attrib_offset));
3150          attrib_offset = 0;
3151       }
3152
3153       aco_opcode opcode;
3154       switch (num_channels) {
3155       case 1:
3156          opcode = aco_opcode::tbuffer_load_format_x;
3157          break;
3158       case 2:
3159          opcode = aco_opcode::tbuffer_load_format_xy;
3160          break;
3161       case 3:
3162          opcode = aco_opcode::tbuffer_load_format_xyz;
3163          break;
3164       case 4:
3165          opcode = aco_opcode::tbuffer_load_format_xyzw;
3166          break;
3167       default:
3168          unreachable("Unimplemented load_input vector size");
3169       }
3170
3171       Temp tmp = post_shuffle || num_channels != dst.size() || alpha_adjust != RADV_ALPHA_ADJUST_NONE || component ? bld.tmp(RegType::vgpr, num_channels) : dst;
3172
3173       aco_ptr<MTBUF_instruction> mubuf{create_instruction<MTBUF_instruction>(opcode, Format::MTBUF, 3, 1)};
3174       mubuf->operands[0] = Operand(index);
3175       mubuf->operands[1] = Operand(list);
3176       mubuf->operands[2] = soffset;
3177       mubuf->definitions[0] = Definition(tmp);
3178       mubuf->idxen = true;
3179       mubuf->can_reorder = true;
3180       mubuf->dfmt = dfmt;
3181       mubuf->nfmt = nfmt;
3182       assert(attrib_offset < 4096);
3183       mubuf->offset = attrib_offset;
3184       ctx->block->instructions.emplace_back(std::move(mubuf));
3185
3186       emit_split_vector(ctx, tmp, tmp.size());
3187
3188       if (tmp.id() != dst.id()) {
3189          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3190                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3191
3192          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3193          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3194          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3195
3196          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3197          for (unsigned i = 0; i < dst.size(); i++) {
3198             unsigned idx = i + component;
3199             if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE && num_channels >= 4) {
3200                Temp alpha = emit_extract_vector(ctx, tmp, swizzle[3], v1);
3201                vec->operands[3] = Operand(adjust_vertex_fetch_alpha(ctx, alpha_adjust, alpha));
3202             } else if (idx < num_channels) {
3203                vec->operands[i] = Operand(emit_extract_vector(ctx, tmp, swizzle[idx], v1));
3204             } else if (is_float && idx == 3) {
3205                vec->operands[i] = Operand(0x3f800000u);
3206             } else if (!is_float && idx == 3) {
3207                vec->operands[i] = Operand(1u);
3208             } else {
3209                vec->operands[i] = Operand(0u);
3210             }
3211          }
3212          vec->definitions[0] = Definition(dst);
3213          ctx->block->instructions.emplace_back(std::move(vec));
3214          emit_split_vector(ctx, dst, dst.size());
3215       }
3216
3217    } else if (ctx->stage == fragment_fs) {
3218       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3219       if (off_instr->type != nir_instr_type_load_const ||
3220           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3221          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3222          nir_print_instr(off_instr, stderr);
3223          fprintf(stderr, "\n");
3224       }
3225
3226       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3227       nir_const_value* offset = nir_src_as_const_value(instr->src[0]);
3228       if (offset) {
3229          assert(offset->u32 == 0);
3230       } else {
3231          /* the lower 15bit of the prim_mask contain the offset into LDS
3232           * while the upper bits contain the number of prims */
3233          Temp offset_src = get_ssa_temp(ctx, instr->src[0].ssa);
3234          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3235          Builder bld(ctx->program, ctx->block);
3236          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3237          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3238          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3239          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3240          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3241       }
3242
3243       unsigned idx = nir_intrinsic_base(instr);
3244       unsigned component = nir_intrinsic_component(instr);
3245
3246       if (dst.size() == 1) {
3247          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(2u), bld.m0(prim_mask), idx, component);
3248       } else {
3249          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3250          for (unsigned i = 0; i < dst.size(); i++)
3251             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(2u), bld.m0(prim_mask), idx, component + i);
3252          vec->definitions[0] = Definition(dst);
3253          bld.insert(std::move(vec));
3254       }
3255
3256    } else {
3257       unreachable("Shader stage not implemented");
3258    }
3259 }
3260
3261 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3262 {
3263    if (ctx->program->info->need_indirect_descriptor_sets) {
3264       Builder bld(ctx->program, ctx->block);
3265       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3266       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, Operand(desc_set << 2));//, false, false, false);
3267    }
3268
3269    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3270 }
3271
3272
3273 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3274 {
3275    Builder bld(ctx->program, ctx->block);
3276    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3277    if (!ctx->divergent_vals[instr->dest.ssa.index])
3278       index = bld.as_uniform(index);
3279    unsigned desc_set = nir_intrinsic_desc_set(instr);
3280    unsigned binding = nir_intrinsic_binding(instr);
3281
3282    Temp desc_ptr;
3283    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3284    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3285    unsigned offset = layout->binding[binding].offset;
3286    unsigned stride;
3287    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3288        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3289       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3290       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3291       offset = pipeline_layout->push_constant_size + 16 * idx;
3292       stride = 16;
3293    } else {
3294       desc_ptr = load_desc_ptr(ctx, desc_set);
3295       stride = layout->binding[binding].size;
3296    }
3297
3298    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3299    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3300    if (stride != 1) {
3301       if (nir_const_index) {
3302          const_index = const_index * stride;
3303       } else if (index.type() == RegType::vgpr) {
3304          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3305          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3306       } else {
3307          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3308       }
3309    }
3310    if (offset) {
3311       if (nir_const_index) {
3312          const_index = const_index + offset;
3313       } else if (index.type() == RegType::vgpr) {
3314          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3315       } else {
3316          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3317       }
3318    }
3319
3320    if (nir_const_index && const_index == 0) {
3321       index = desc_ptr;
3322    } else if (index.type() == RegType::vgpr) {
3323       index = bld.vadd32(bld.def(v1),
3324                          nir_const_index ? Operand(const_index) : Operand(index),
3325                          Operand(desc_ptr));
3326    } else {
3327       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3328                        nir_const_index ? Operand(const_index) : Operand(index),
3329                        Operand(desc_ptr));
3330    }
3331
3332    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3333 }
3334
3335 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3336                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3337 {
3338    Builder bld(ctx->program, ctx->block);
3339
3340    unsigned num_bytes = dst.size() * 4;
3341    bool dlc = glc && ctx->options->chip_class >= GFX10;
3342
3343    aco_opcode op;
3344    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3345       if (ctx->options->chip_class < GFX8)
3346          offset = as_vgpr(ctx, offset);
3347
3348       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3349       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3350       unsigned const_offset = 0;
3351
3352       Temp lower = Temp();
3353       if (num_bytes > 16) {
3354          assert(num_components == 3 || num_components == 4);
3355          op = aco_opcode::buffer_load_dwordx4;
3356          lower = bld.tmp(v4);
3357          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3358          mubuf->definitions[0] = Definition(lower);
3359          mubuf->operands[0] = vaddr;
3360          mubuf->operands[1] = Operand(rsrc);
3361          mubuf->operands[2] = soffset;
3362          mubuf->offen = (offset.type() == RegType::vgpr);
3363          mubuf->glc = glc;
3364          mubuf->dlc = dlc;
3365          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3366          mubuf->can_reorder = readonly;
3367          bld.insert(std::move(mubuf));
3368          emit_split_vector(ctx, lower, 2);
3369          num_bytes -= 16;
3370          const_offset = 16;
3371       }
3372
3373       switch (num_bytes) {
3374          case 4:
3375             op = aco_opcode::buffer_load_dword;
3376             break;
3377          case 8:
3378             op = aco_opcode::buffer_load_dwordx2;
3379             break;
3380          case 12:
3381             op = aco_opcode::buffer_load_dwordx3;
3382             break;
3383          case 16:
3384             op = aco_opcode::buffer_load_dwordx4;
3385             break;
3386          default:
3387             unreachable("Load SSBO not implemented for this size.");
3388       }
3389       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3390       mubuf->operands[0] = vaddr;
3391       mubuf->operands[1] = Operand(rsrc);
3392       mubuf->operands[2] = soffset;
3393       mubuf->offen = (offset.type() == RegType::vgpr);
3394       mubuf->glc = glc;
3395       mubuf->dlc = dlc;
3396       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3397       mubuf->can_reorder = readonly;
3398       mubuf->offset = const_offset;
3399       aco_ptr<Instruction> instr = std::move(mubuf);
3400
3401       if (dst.size() > 4) {
3402          assert(lower != Temp());
3403          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3404          instr->definitions[0] = Definition(upper);
3405          bld.insert(std::move(instr));
3406          if (dst.size() == 8)
3407             emit_split_vector(ctx, upper, 2);
3408          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3409          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3410          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3411          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3412          if (dst.size() == 8)
3413             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3414       }
3415
3416       if (dst.type() == RegType::sgpr) {
3417          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3418          instr->definitions[0] = Definition(vec);
3419          bld.insert(std::move(instr));
3420          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
3421       } else {
3422          instr->definitions[0] = Definition(dst);
3423          bld.insert(std::move(instr));
3424       }
3425    } else {
3426       switch (num_bytes) {
3427          case 4:
3428             op = aco_opcode::s_buffer_load_dword;
3429             break;
3430          case 8:
3431             op = aco_opcode::s_buffer_load_dwordx2;
3432             break;
3433          case 12:
3434          case 16:
3435             op = aco_opcode::s_buffer_load_dwordx4;
3436             break;
3437          case 24:
3438          case 32:
3439             op = aco_opcode::s_buffer_load_dwordx8;
3440             break;
3441          default:
3442             unreachable("Load SSBO not implemented for this size.");
3443       }
3444       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3445       load->operands[0] = Operand(rsrc);
3446       load->operands[1] = Operand(bld.as_uniform(offset));
3447       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3448       load->definitions[0] = Definition(dst);
3449       load->glc = glc;
3450       load->dlc = dlc;
3451       load->barrier = readonly ? barrier_none : barrier_buffer;
3452       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3453       assert(ctx->options->chip_class >= GFX8 || !glc);
3454
3455       /* trim vector */
3456       if (dst.size() == 3) {
3457          Temp vec = bld.tmp(s4);
3458          load->definitions[0] = Definition(vec);
3459          bld.insert(std::move(load));
3460          emit_split_vector(ctx, vec, 4);
3461
3462          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3463                     emit_extract_vector(ctx, vec, 0, s1),
3464                     emit_extract_vector(ctx, vec, 1, s1),
3465                     emit_extract_vector(ctx, vec, 2, s1));
3466       } else if (dst.size() == 6) {
3467          Temp vec = bld.tmp(s8);
3468          load->definitions[0] = Definition(vec);
3469          bld.insert(std::move(load));
3470          emit_split_vector(ctx, vec, 4);
3471
3472          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3473                     emit_extract_vector(ctx, vec, 0, s2),
3474                     emit_extract_vector(ctx, vec, 1, s2),
3475                     emit_extract_vector(ctx, vec, 2, s2));
3476       } else {
3477          bld.insert(std::move(load));
3478       }
3479
3480    }
3481    emit_split_vector(ctx, dst, num_components);
3482 }
3483
3484 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3485 {
3486    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3487    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3488
3489    Builder bld(ctx->program, ctx->block);
3490
3491    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3492    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3493    unsigned binding = nir_intrinsic_binding(idx_instr);
3494    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3495
3496    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3497       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3498                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3499                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3500                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3501       if (ctx->options->chip_class >= GFX10) {
3502          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3503                       S_008F0C_OOB_SELECT(3) |
3504                       S_008F0C_RESOURCE_LEVEL(1);
3505       } else {
3506          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3507                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3508       }
3509       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3510                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3511                                      Operand(0xFFFFFFFFu),
3512                                      Operand(desc_type));
3513       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3514                         rsrc, upper_dwords);
3515    } else {
3516       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3517       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3518    }
3519
3520    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3521 }
3522
3523 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3524 {
3525    Builder bld(ctx->program, ctx->block);
3526    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3527
3528    unsigned offset = nir_intrinsic_base(instr);
3529    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3530    if (index_cv && instr->dest.ssa.bit_size == 32) {
3531
3532       unsigned count = instr->dest.ssa.num_components;
3533       unsigned start = (offset + index_cv->u32) / 4u;
3534       start -= ctx->args->ac.base_inline_push_consts;
3535       if (start + count <= ctx->args->ac.num_inline_push_consts) {
3536          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3537          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3538          for (unsigned i = 0; i < count; ++i) {
3539             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
3540             vec->operands[i] = Operand{elems[i]};
3541          }
3542          vec->definitions[0] = Definition(dst);
3543          ctx->block->instructions.emplace_back(std::move(vec));
3544          ctx->allocated_vec.emplace(dst.id(), elems);
3545          return;
3546       }
3547    }
3548
3549    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3550    if (offset != 0) // TODO check if index != 0 as well
3551       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3552    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
3553    Temp vec = dst;
3554    bool trim = false;
3555    aco_opcode op;
3556
3557    switch (dst.size()) {
3558    case 1:
3559       op = aco_opcode::s_load_dword;
3560       break;
3561    case 2:
3562       op = aco_opcode::s_load_dwordx2;
3563       break;
3564    case 3:
3565       vec = bld.tmp(s4);
3566       trim = true;
3567    case 4:
3568       op = aco_opcode::s_load_dwordx4;
3569       break;
3570    case 6:
3571       vec = bld.tmp(s8);
3572       trim = true;
3573    case 8:
3574       op = aco_opcode::s_load_dwordx8;
3575       break;
3576    default:
3577       unreachable("unimplemented or forbidden load_push_constant.");
3578    }
3579
3580    bld.smem(op, Definition(vec), ptr, index);
3581
3582    if (trim) {
3583       emit_split_vector(ctx, vec, 4);
3584       RegClass rc = dst.size() == 3 ? s1 : s2;
3585       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3586                  emit_extract_vector(ctx, vec, 0, rc),
3587                  emit_extract_vector(ctx, vec, 1, rc),
3588                  emit_extract_vector(ctx, vec, 2, rc));
3589
3590    }
3591    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3592 }
3593
3594 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3595 {
3596    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3597
3598    Builder bld(ctx->program, ctx->block);
3599
3600    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3601                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3602                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3603                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3604    if (ctx->options->chip_class >= GFX10) {
3605       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3606                    S_008F0C_OOB_SELECT(3) |
3607                    S_008F0C_RESOURCE_LEVEL(1);
3608    } else {
3609       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3610                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3611    }
3612
3613    unsigned base = nir_intrinsic_base(instr);
3614    unsigned range = nir_intrinsic_range(instr);
3615
3616    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3617    if (base && offset.type() == RegType::sgpr)
3618       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3619    else if (base && offset.type() == RegType::vgpr)
3620       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3621
3622    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3623                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3624                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3625                           Operand(desc_type));
3626
3627    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3628 }
3629
3630 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3631 {
3632    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3633       ctx->cf_info.exec_potentially_empty = true;
3634
3635    ctx->program->needs_exact = true;
3636
3637    // TODO: optimize uniform conditions
3638    Builder bld(ctx->program, ctx->block);
3639    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3640    assert(src.regClass() == bld.lm);
3641    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
3642    bld.pseudo(aco_opcode::p_discard_if, src);
3643    ctx->block->kind |= block_kind_uses_discard_if;
3644    return;
3645 }
3646
3647 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3648 {
3649    Builder bld(ctx->program, ctx->block);
3650
3651    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3652       ctx->cf_info.exec_potentially_empty = true;
3653
3654    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3655                     ctx->cf_info.parent_loop.has_divergent_continue;
3656
3657    if (ctx->block->loop_nest_depth &&
3658        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3659       /* we handle discards the same way as jump instructions */
3660       append_logical_end(ctx->block);
3661
3662       /* in loops, discard behaves like break */
3663       Block *linear_target = ctx->cf_info.parent_loop.exit;
3664       ctx->block->kind |= block_kind_discard;
3665
3666       if (!divergent) {
3667          /* uniform discard - loop ends here */
3668          assert(nir_instr_is_last(&instr->instr));
3669          ctx->block->kind |= block_kind_uniform;
3670          ctx->cf_info.has_branch = true;
3671          bld.branch(aco_opcode::p_branch);
3672          add_linear_edge(ctx->block->index, linear_target);
3673          return;
3674       }
3675
3676       /* we add a break right behind the discard() instructions */
3677       ctx->block->kind |= block_kind_break;
3678       unsigned idx = ctx->block->index;
3679
3680       /* remove critical edges from linear CFG */
3681       bld.branch(aco_opcode::p_branch);
3682       Block* break_block = ctx->program->create_and_insert_block();
3683       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3684       break_block->kind |= block_kind_uniform;
3685       add_linear_edge(idx, break_block);
3686       add_linear_edge(break_block->index, linear_target);
3687       bld.reset(break_block);
3688       bld.branch(aco_opcode::p_branch);
3689
3690       Block* continue_block = ctx->program->create_and_insert_block();
3691       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3692       add_linear_edge(idx, continue_block);
3693       append_logical_start(continue_block);
3694       ctx->block = continue_block;
3695
3696       return;
3697    }
3698
3699    /* it can currently happen that NIR doesn't remove the unreachable code */
3700    if (!nir_instr_is_last(&instr->instr)) {
3701       ctx->program->needs_exact = true;
3702       /* save exec somewhere temporarily so that it doesn't get
3703        * overwritten before the discard from outer exec masks */
3704       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
3705       bld.pseudo(aco_opcode::p_discard_if, cond);
3706       ctx->block->kind |= block_kind_uses_discard_if;
3707       return;
3708    }
3709
3710    /* This condition is incorrect for uniformly branched discards in a loop
3711     * predicated by a divergent condition, but the above code catches that case
3712     * and the discard would end up turning into a discard_if.
3713     * For example:
3714     * if (divergent) {
3715     *    while (...) {
3716     *       if (uniform) {
3717     *          discard;
3718     *       }
3719     *    }
3720     * }
3721     */
3722    if (!ctx->cf_info.parent_if.is_divergent) {
3723       /* program just ends here */
3724       ctx->block->kind |= block_kind_uniform;
3725       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
3726               0 /* enabled mask */, 9 /* dest */,
3727               false /* compressed */, true/* done */, true /* valid mask */);
3728       bld.sopp(aco_opcode::s_endpgm);
3729       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3730    } else {
3731       ctx->block->kind |= block_kind_discard;
3732       /* branch and linear edge is added by visit_if() */
3733    }
3734 }
3735
3736 enum aco_descriptor_type {
3737    ACO_DESC_IMAGE,
3738    ACO_DESC_FMASK,
3739    ACO_DESC_SAMPLER,
3740    ACO_DESC_BUFFER,
3741    ACO_DESC_PLANE_0,
3742    ACO_DESC_PLANE_1,
3743    ACO_DESC_PLANE_2,
3744 };
3745
3746 static bool
3747 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
3748    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
3749       return false;
3750    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
3751    return dim == ac_image_cube ||
3752           dim == ac_image_1darray ||
3753           dim == ac_image_2darray ||
3754           dim == ac_image_2darraymsaa;
3755 }
3756
3757 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
3758                       enum aco_descriptor_type desc_type,
3759                       const nir_tex_instr *tex_instr, bool image, bool write)
3760 {
3761 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3762    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3763    if (it != ctx->tex_desc.end())
3764       return it->second;
3765 */
3766    Temp index = Temp();
3767    bool index_set = false;
3768    unsigned constant_index = 0;
3769    unsigned descriptor_set;
3770    unsigned base_index;
3771    Builder bld(ctx->program, ctx->block);
3772
3773    if (!deref_instr) {
3774       assert(tex_instr && !image);
3775       descriptor_set = 0;
3776       base_index = tex_instr->sampler_index;
3777    } else {
3778       while(deref_instr->deref_type != nir_deref_type_var) {
3779          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
3780          if (!array_size)
3781             array_size = 1;
3782
3783          assert(deref_instr->deref_type == nir_deref_type_array);
3784          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
3785          if (const_value) {
3786             constant_index += array_size * const_value->u32;
3787          } else {
3788             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
3789             if (indirect.type() == RegType::vgpr)
3790                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
3791
3792             if (array_size != 1)
3793                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
3794
3795             if (!index_set) {
3796                index = indirect;
3797                index_set = true;
3798             } else {
3799                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
3800             }
3801          }
3802
3803          deref_instr = nir_src_as_deref(deref_instr->parent);
3804       }
3805       descriptor_set = deref_instr->var->data.descriptor_set;
3806       base_index = deref_instr->var->data.binding;
3807    }
3808
3809    Temp list = load_desc_ptr(ctx, descriptor_set);
3810    list = convert_pointer_to_64_bit(ctx, list);
3811
3812    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
3813    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
3814    unsigned offset = binding->offset;
3815    unsigned stride = binding->size;
3816    aco_opcode opcode;
3817    RegClass type;
3818
3819    assert(base_index < layout->binding_count);
3820
3821    switch (desc_type) {
3822    case ACO_DESC_IMAGE:
3823       type = s8;
3824       opcode = aco_opcode::s_load_dwordx8;
3825       break;
3826    case ACO_DESC_FMASK:
3827       type = s8;
3828       opcode = aco_opcode::s_load_dwordx8;
3829       offset += 32;
3830       break;
3831    case ACO_DESC_SAMPLER:
3832       type = s4;
3833       opcode = aco_opcode::s_load_dwordx4;
3834       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3835          offset += radv_combined_image_descriptor_sampler_offset(binding);
3836       break;
3837    case ACO_DESC_BUFFER:
3838       type = s4;
3839       opcode = aco_opcode::s_load_dwordx4;
3840       break;
3841    case ACO_DESC_PLANE_0:
3842    case ACO_DESC_PLANE_1:
3843       type = s8;
3844       opcode = aco_opcode::s_load_dwordx8;
3845       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
3846       break;
3847    case ACO_DESC_PLANE_2:
3848       type = s4;
3849       opcode = aco_opcode::s_load_dwordx4;
3850       offset += 64;
3851       break;
3852    default:
3853       unreachable("invalid desc_type\n");
3854    }
3855
3856    offset += constant_index * stride;
3857
3858    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
3859       (!index_set || binding->immutable_samplers_equal)) {
3860       if (binding->immutable_samplers_equal)
3861          constant_index = 0;
3862
3863       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3864       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3865                         Operand(samplers[constant_index * 4 + 0]),
3866                         Operand(samplers[constant_index * 4 + 1]),
3867                         Operand(samplers[constant_index * 4 + 2]),
3868                         Operand(samplers[constant_index * 4 + 3]));
3869    }
3870
3871    Operand off;
3872    if (!index_set) {
3873       off = Operand(offset);
3874    } else {
3875       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
3876                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
3877    }
3878
3879    Temp res = bld.smem(opcode, bld.def(type), list, off);
3880
3881    if (desc_type == ACO_DESC_PLANE_2) {
3882       Temp components[8];
3883       for (unsigned i = 0; i < 8; i++)
3884          components[i] = bld.tmp(s1);
3885       bld.pseudo(aco_opcode::p_split_vector,
3886                  Definition(components[0]),
3887                  Definition(components[1]),
3888                  Definition(components[2]),
3889                  Definition(components[3]),
3890                  res);
3891
3892       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
3893       bld.pseudo(aco_opcode::p_split_vector,
3894                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
3895                  Definition(components[4]),
3896                  Definition(components[5]),
3897                  Definition(components[6]),
3898                  Definition(components[7]),
3899                  desc2);
3900
3901       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
3902                        components[0], components[1], components[2], components[3],
3903                        components[4], components[5], components[6], components[7]);
3904    }
3905
3906    return res;
3907 }
3908
3909 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3910 {
3911    switch (dim) {
3912    case GLSL_SAMPLER_DIM_BUF:
3913       return 1;
3914    case GLSL_SAMPLER_DIM_1D:
3915       return array ? 2 : 1;
3916    case GLSL_SAMPLER_DIM_2D:
3917       return array ? 3 : 2;
3918    case GLSL_SAMPLER_DIM_MS:
3919       return array ? 4 : 3;
3920    case GLSL_SAMPLER_DIM_3D:
3921    case GLSL_SAMPLER_DIM_CUBE:
3922       return 3;
3923    case GLSL_SAMPLER_DIM_RECT:
3924    case GLSL_SAMPLER_DIM_SUBPASS:
3925       return 2;
3926    case GLSL_SAMPLER_DIM_SUBPASS_MS:
3927       return 3;
3928    default:
3929       break;
3930    }
3931    return 0;
3932 }
3933
3934
3935 /* Adjust the sample index according to FMASK.
3936  *
3937  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3938  * which is the identity mapping. Each nibble says which physical sample
3939  * should be fetched to get that sample.
3940  *
3941  * For example, 0x11111100 means there are only 2 samples stored and
3942  * the second sample covers 3/4 of the pixel. When reading samples 0
3943  * and 1, return physical sample 0 (determined by the first two 0s
3944  * in FMASK), otherwise return physical sample 1.
3945  *
3946  * The sample index should be adjusted as follows:
3947  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
3948  */
3949 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, Temp coords, Operand sample_index, Temp fmask_desc_ptr)
3950 {
3951    Builder bld(ctx->program, ctx->block);
3952    Temp fmask = bld.tmp(v1);
3953    unsigned dim = ctx->options->chip_class >= GFX10
3954                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
3955                   : 0;
3956
3957    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3958    load->operands[0] = Operand(coords);
3959    load->operands[1] = Operand(fmask_desc_ptr);
3960    load->definitions[0] = Definition(fmask);
3961    load->glc = false;
3962    load->dlc = false;
3963    load->dmask = 0x1;
3964    load->unrm = true;
3965    load->da = da;
3966    load->dim = dim;
3967    load->can_reorder = true; /* fmask images shouldn't be modified */
3968    ctx->block->instructions.emplace_back(std::move(load));
3969
3970    Operand sample_index4;
3971    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
3972       sample_index4 = Operand(sample_index.constantValue() << 2);
3973    } else if (sample_index.regClass() == s1) {
3974       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
3975    } else {
3976       assert(sample_index.regClass() == v1);
3977       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
3978    }
3979
3980    Temp final_sample;
3981    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
3982       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
3983    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
3984       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
3985    else
3986       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
3987
3988    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3989     * resource descriptor is 0 (invalid),
3990     */
3991    Temp compare = bld.tmp(bld.lm);
3992    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
3993                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
3994
3995    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
3996
3997    /* Replace the MSAA sample index. */
3998    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
3999 }
4000
4001 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4002 {
4003
4004    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4005    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4006    bool is_array = glsl_sampler_type_is_array(type);
4007    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4008    assert(!add_frag_pos && "Input attachments should be lowered.");
4009    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4010    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4011    int count = image_type_to_components_count(dim, is_array);
4012    std::vector<Operand> coords(count);
4013
4014    if (is_ms) {
4015       Operand sample_index;
4016       nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4017       if (sample_cv)
4018          sample_index = Operand(sample_cv->u32);
4019       else
4020          sample_index = Operand(emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[2].ssa), 0, v1));
4021
4022       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4023          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, is_array ? 3 : 2, 1)};
4024          for (unsigned i = 0; i < vec->operands.size(); i++)
4025             vec->operands[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
4026          Temp fmask_load_address = {ctx->program->allocateId(), is_array ? v3 : v2};
4027          vec->definitions[0] = Definition(fmask_load_address);
4028          ctx->block->instructions.emplace_back(std::move(vec));
4029
4030          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4031          sample_index = Operand(adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr));
4032       }
4033       count--;
4034       coords[count] = sample_index;
4035    }
4036
4037    if (count == 1 && !gfx9_1d)
4038       return emit_extract_vector(ctx, src0, 0, v1);
4039
4040    if (gfx9_1d) {
4041       coords[0] = Operand(emit_extract_vector(ctx, src0, 0, v1));
4042       coords.resize(coords.size() + 1);
4043       coords[1] = Operand((uint32_t) 0);
4044       if (is_array)
4045          coords[2] = Operand(emit_extract_vector(ctx, src0, 1, v1));
4046    } else {
4047       for (int i = 0; i < count; i++)
4048          coords[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
4049    }
4050
4051    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4052    for (unsigned i = 0; i < coords.size(); i++)
4053       vec->operands[i] = coords[i];
4054    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4055    vec->definitions[0] = Definition(res);
4056    ctx->block->instructions.emplace_back(std::move(vec));
4057    return res;
4058 }
4059
4060
4061 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4062 {
4063    Builder bld(ctx->program, ctx->block);
4064    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4065    const struct glsl_type *type = glsl_without_array(var->type);
4066    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4067    bool is_array = glsl_sampler_type_is_array(type);
4068    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4069
4070    if (dim == GLSL_SAMPLER_DIM_BUF) {
4071       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4072       unsigned num_channels = util_last_bit(mask);
4073       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4074       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4075
4076       aco_opcode opcode;
4077       switch (num_channels) {
4078       case 1:
4079          opcode = aco_opcode::buffer_load_format_x;
4080          break;
4081       case 2:
4082          opcode = aco_opcode::buffer_load_format_xy;
4083          break;
4084       case 3:
4085          opcode = aco_opcode::buffer_load_format_xyz;
4086          break;
4087       case 4:
4088          opcode = aco_opcode::buffer_load_format_xyzw;
4089          break;
4090       default:
4091          unreachable(">4 channel buffer image load");
4092       }
4093       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4094       load->operands[0] = Operand(vindex);
4095       load->operands[1] = Operand(rsrc);
4096       load->operands[2] = Operand((uint32_t) 0);
4097       Temp tmp;
4098       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4099          tmp = dst;
4100       else
4101          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4102       load->definitions[0] = Definition(tmp);
4103       load->idxen = true;
4104       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4105       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4106       load->barrier = barrier_image;
4107       ctx->block->instructions.emplace_back(std::move(load));
4108
4109       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4110       return;
4111    }
4112
4113    Temp coords = get_image_coords(ctx, instr, type);
4114    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4115
4116    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4117    unsigned num_components = util_bitcount(dmask);
4118    Temp tmp;
4119    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4120       tmp = dst;
4121    else
4122       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4123
4124    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
4125    load->operands[0] = Operand(coords);
4126    load->operands[1] = Operand(resource);
4127    load->definitions[0] = Definition(tmp);
4128    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4129    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4130    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4131    load->dmask = dmask;
4132    load->unrm = true;
4133    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4134    load->barrier = barrier_image;
4135    ctx->block->instructions.emplace_back(std::move(load));
4136
4137    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4138    return;
4139 }
4140
4141 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4142 {
4143    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4144    const struct glsl_type *type = glsl_without_array(var->type);
4145    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4146    bool is_array = glsl_sampler_type_is_array(type);
4147    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4148
4149    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4150
4151    if (dim == GLSL_SAMPLER_DIM_BUF) {
4152       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4153       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4154       aco_opcode opcode;
4155       switch (data.size()) {
4156       case 1:
4157          opcode = aco_opcode::buffer_store_format_x;
4158          break;
4159       case 2:
4160          opcode = aco_opcode::buffer_store_format_xy;
4161          break;
4162       case 3:
4163          opcode = aco_opcode::buffer_store_format_xyz;
4164          break;
4165       case 4:
4166          opcode = aco_opcode::buffer_store_format_xyzw;
4167          break;
4168       default:
4169          unreachable(">4 channel buffer image store");
4170       }
4171       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4172       store->operands[0] = Operand(vindex);
4173       store->operands[1] = Operand(rsrc);
4174       store->operands[2] = Operand((uint32_t) 0);
4175       store->operands[3] = Operand(data);
4176       store->idxen = true;
4177       store->glc = glc;
4178       store->dlc = false;
4179       store->disable_wqm = true;
4180       store->barrier = barrier_image;
4181       ctx->program->needs_exact = true;
4182       ctx->block->instructions.emplace_back(std::move(store));
4183       return;
4184    }
4185
4186    assert(data.type() == RegType::vgpr);
4187    Temp coords = get_image_coords(ctx, instr, type);
4188    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4189
4190    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(aco_opcode::image_store, Format::MIMG, 4, 0)};
4191    store->operands[0] = Operand(coords);
4192    store->operands[1] = Operand(resource);
4193    store->operands[2] = Operand(s4);
4194    store->operands[3] = Operand(data);
4195    store->glc = glc;
4196    store->dlc = false;
4197    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4198    store->dmask = (1 << data.size()) - 1;
4199    store->unrm = true;
4200    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4201    store->disable_wqm = true;
4202    store->barrier = barrier_image;
4203    ctx->program->needs_exact = true;
4204    ctx->block->instructions.emplace_back(std::move(store));
4205    return;
4206 }
4207
4208 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4209 {
4210    /* return the previous value if dest is ever used */
4211    bool return_previous = false;
4212    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4213       return_previous = true;
4214       break;
4215    }
4216    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4217       return_previous = true;
4218       break;
4219    }
4220
4221    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4222    const struct glsl_type *type = glsl_without_array(var->type);
4223    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4224    bool is_array = glsl_sampler_type_is_array(type);
4225    Builder bld(ctx->program, ctx->block);
4226
4227    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4228    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4229
4230    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4231       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4232
4233    aco_opcode buf_op, image_op;
4234    switch (instr->intrinsic) {
4235       case nir_intrinsic_image_deref_atomic_add:
4236          buf_op = aco_opcode::buffer_atomic_add;
4237          image_op = aco_opcode::image_atomic_add;
4238          break;
4239       case nir_intrinsic_image_deref_atomic_umin:
4240          buf_op = aco_opcode::buffer_atomic_umin;
4241          image_op = aco_opcode::image_atomic_umin;
4242          break;
4243       case nir_intrinsic_image_deref_atomic_imin:
4244          buf_op = aco_opcode::buffer_atomic_smin;
4245          image_op = aco_opcode::image_atomic_smin;
4246          break;
4247       case nir_intrinsic_image_deref_atomic_umax:
4248          buf_op = aco_opcode::buffer_atomic_umax;
4249          image_op = aco_opcode::image_atomic_umax;
4250          break;
4251       case nir_intrinsic_image_deref_atomic_imax:
4252          buf_op = aco_opcode::buffer_atomic_smax;
4253          image_op = aco_opcode::image_atomic_smax;
4254          break;
4255       case nir_intrinsic_image_deref_atomic_and:
4256          buf_op = aco_opcode::buffer_atomic_and;
4257          image_op = aco_opcode::image_atomic_and;
4258          break;
4259       case nir_intrinsic_image_deref_atomic_or:
4260          buf_op = aco_opcode::buffer_atomic_or;
4261          image_op = aco_opcode::image_atomic_or;
4262          break;
4263       case nir_intrinsic_image_deref_atomic_xor:
4264          buf_op = aco_opcode::buffer_atomic_xor;
4265          image_op = aco_opcode::image_atomic_xor;
4266          break;
4267       case nir_intrinsic_image_deref_atomic_exchange:
4268          buf_op = aco_opcode::buffer_atomic_swap;
4269          image_op = aco_opcode::image_atomic_swap;
4270          break;
4271       case nir_intrinsic_image_deref_atomic_comp_swap:
4272          buf_op = aco_opcode::buffer_atomic_cmpswap;
4273          image_op = aco_opcode::image_atomic_cmpswap;
4274          break;
4275       default:
4276          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4277    }
4278
4279    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4280
4281    if (dim == GLSL_SAMPLER_DIM_BUF) {
4282       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4283       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4284       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4285       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4286       mubuf->operands[0] = Operand(vindex);
4287       mubuf->operands[1] = Operand(resource);
4288       mubuf->operands[2] = Operand((uint32_t)0);
4289       mubuf->operands[3] = Operand(data);
4290       if (return_previous)
4291          mubuf->definitions[0] = Definition(dst);
4292       mubuf->offset = 0;
4293       mubuf->idxen = true;
4294       mubuf->glc = return_previous;
4295       mubuf->dlc = false; /* Not needed for atomics */
4296       mubuf->disable_wqm = true;
4297       mubuf->barrier = barrier_image;
4298       ctx->program->needs_exact = true;
4299       ctx->block->instructions.emplace_back(std::move(mubuf));
4300       return;
4301    }
4302
4303    Temp coords = get_image_coords(ctx, instr, type);
4304    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4305    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 4, return_previous ? 1 : 0)};
4306    mimg->operands[0] = Operand(coords);
4307    mimg->operands[1] = Operand(resource);
4308    mimg->operands[2] = Operand(s4); /* no sampler */
4309    mimg->operands[3] = Operand(data);
4310    if (return_previous)
4311       mimg->definitions[0] = Definition(dst);
4312    mimg->glc = return_previous;
4313    mimg->dlc = false; /* Not needed for atomics */
4314    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4315    mimg->dmask = (1 << data.size()) - 1;
4316    mimg->unrm = true;
4317    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4318    mimg->disable_wqm = true;
4319    mimg->barrier = barrier_image;
4320    ctx->program->needs_exact = true;
4321    ctx->block->instructions.emplace_back(std::move(mimg));
4322    return;
4323 }
4324
4325 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4326 {
4327    if (in_elements && ctx->options->chip_class == GFX8) {
4328       Builder bld(ctx->program, ctx->block);
4329
4330       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4331       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4332       stride = bld.vop1(aco_opcode::v_cvt_f32_ubyte0, bld.def(v1), stride);
4333       stride = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), stride);
4334
4335       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4336       size = bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), size);
4337
4338       Temp res = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), size, stride);
4339       res = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), res);
4340       bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
4341
4342       // TODO: we can probably calculate this faster on the scalar unit to do: size / stride{1,2,4,8,12,16}
4343       /* idea
4344        * for 1,2,4,8,16, the result is just (stride >> S_FF1_I32_B32)
4345        * in case 12 (or 3?), we have to divide by 3:
4346        * set v_skip in case it's 12 (if we also have to take care of 3, shift first)
4347        * use v_mul_hi_u32 with magic number to divide
4348        * we need some pseudo merge opcode to overwrite the original SALU result with readfirstlane
4349        * disable v_skip
4350        * total: 6 SALU + 2 VALU instructions vs 1 SALU + 6 VALU instructions
4351        */
4352
4353    } else {
4354       emit_extract_vector(ctx, desc, 2, dst);
4355    }
4356 }
4357
4358 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4359 {
4360    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4361    const struct glsl_type *type = glsl_without_array(var->type);
4362    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4363    bool is_array = glsl_sampler_type_is_array(type);
4364    Builder bld(ctx->program, ctx->block);
4365
4366    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4367       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4368       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4369    }
4370
4371    /* LOD */
4372    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4373
4374    /* Resource */
4375    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4376
4377    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4378
4379    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1)};
4380    mimg->operands[0] = Operand(lod);
4381    mimg->operands[1] = Operand(resource);
4382    unsigned& dmask = mimg->dmask;
4383    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4384    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4385    mimg->da = glsl_sampler_type_is_array(type);
4386    mimg->can_reorder = true;
4387    Definition& def = mimg->definitions[0];
4388    ctx->block->instructions.emplace_back(std::move(mimg));
4389
4390    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4391        glsl_sampler_type_is_array(type)) {
4392
4393       assert(instr->dest.ssa.num_components == 3);
4394       Temp tmp = {ctx->program->allocateId(), v3};
4395       def = Definition(tmp);
4396       emit_split_vector(ctx, tmp, 3);
4397
4398       /* divide 3rd value by 6 by multiplying with magic number */
4399       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4400       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4401
4402       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4403                  emit_extract_vector(ctx, tmp, 0, v1),
4404                  emit_extract_vector(ctx, tmp, 1, v1),
4405                  by_6);
4406
4407    } else if (ctx->options->chip_class == GFX9 &&
4408               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4409               glsl_sampler_type_is_array(type)) {
4410       assert(instr->dest.ssa.num_components == 2);
4411       def = Definition(dst);
4412       dmask = 0x5;
4413    } else {
4414       def = Definition(dst);
4415    }
4416
4417    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4418 }
4419
4420 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4421 {
4422    Builder bld(ctx->program, ctx->block);
4423    unsigned num_components = instr->num_components;
4424
4425    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4426    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4427    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4428
4429    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4430    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4431 }
4432
4433 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4434 {
4435    Builder bld(ctx->program, ctx->block);
4436    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4437    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4438    unsigned writemask = nir_intrinsic_write_mask(instr);
4439
4440    Temp offset;
4441    if (ctx->options->chip_class < GFX8)
4442       offset = as_vgpr(ctx,get_ssa_temp(ctx, instr->src[2].ssa));
4443    else
4444       offset = get_ssa_temp(ctx, instr->src[2].ssa);
4445
4446    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4447    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4448
4449    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4450                ctx->options->chip_class >= GFX8;
4451    if (smem)
4452       offset = bld.as_uniform(offset);
4453    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4454
4455    while (writemask) {
4456       int start, count;
4457       u_bit_scan_consecutive_range(&writemask, &start, &count);
4458       if (count == 3 && smem) {
4459          writemask |= 1u << (start + 2);
4460          count = 2;
4461       }
4462       int num_bytes = count * elem_size_bytes;
4463
4464       if (num_bytes > 16) {
4465          assert(elem_size_bytes == 8);
4466          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4467          count = 2;
4468          num_bytes = 16;
4469       }
4470
4471       // TODO: check alignment of sub-dword stores
4472       // TODO: split 3 bytes. there is no store instruction for that
4473
4474       Temp write_data;
4475       if (count != instr->num_components) {
4476          emit_split_vector(ctx, data, instr->num_components);
4477          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4478          for (int i = 0; i < count; i++) {
4479             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4480             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4481          }
4482          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4483          vec->definitions[0] = Definition(write_data);
4484          ctx->block->instructions.emplace_back(std::move(vec));
4485       } else if (!smem && data.type() != RegType::vgpr) {
4486          assert(num_bytes % 4 == 0);
4487          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4488       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4489          assert(num_bytes % 4 == 0);
4490          write_data = bld.as_uniform(data);
4491       } else {
4492          write_data = data;
4493       }
4494
4495       aco_opcode vmem_op, smem_op;
4496       switch (num_bytes) {
4497          case 4:
4498             vmem_op = aco_opcode::buffer_store_dword;
4499             smem_op = aco_opcode::s_buffer_store_dword;
4500             break;
4501          case 8:
4502             vmem_op = aco_opcode::buffer_store_dwordx2;
4503             smem_op = aco_opcode::s_buffer_store_dwordx2;
4504             break;
4505          case 12:
4506             vmem_op = aco_opcode::buffer_store_dwordx3;
4507             smem_op = aco_opcode::last_opcode;
4508             assert(!smem);
4509             break;
4510          case 16:
4511             vmem_op = aco_opcode::buffer_store_dwordx4;
4512             smem_op = aco_opcode::s_buffer_store_dwordx4;
4513             break;
4514          default:
4515             unreachable("Store SSBO not implemented for this size.");
4516       }
4517       if (ctx->stage == fragment_fs)
4518          smem_op = aco_opcode::p_fs_buffer_store_smem;
4519
4520       if (smem) {
4521          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4522          store->operands[0] = Operand(rsrc);
4523          if (start) {
4524             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4525                                 offset, Operand(start * elem_size_bytes));
4526             store->operands[1] = Operand(off);
4527          } else {
4528             store->operands[1] = Operand(offset);
4529          }
4530          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4531             store->operands[1].setFixed(m0);
4532          store->operands[2] = Operand(write_data);
4533          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4534          store->dlc = false;
4535          store->disable_wqm = true;
4536          store->barrier = barrier_buffer;
4537          ctx->block->instructions.emplace_back(std::move(store));
4538          ctx->program->wb_smem_l1_on_end = true;
4539          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4540             ctx->block->kind |= block_kind_needs_lowering;
4541             ctx->program->needs_exact = true;
4542          }
4543       } else {
4544          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4545          store->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4546          store->operands[1] = Operand(rsrc);
4547          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4548          store->operands[3] = Operand(write_data);
4549          store->offset = start * elem_size_bytes;
4550          store->offen = (offset.type() == RegType::vgpr);
4551          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4552          store->dlc = false;
4553          store->disable_wqm = true;
4554          store->barrier = barrier_buffer;
4555          ctx->program->needs_exact = true;
4556          ctx->block->instructions.emplace_back(std::move(store));
4557       }
4558    }
4559 }
4560
4561 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4562 {
4563    /* return the previous value if dest is ever used */
4564    bool return_previous = false;
4565    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4566       return_previous = true;
4567       break;
4568    }
4569    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4570       return_previous = true;
4571       break;
4572    }
4573
4574    Builder bld(ctx->program, ctx->block);
4575    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4576
4577    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4578       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4579                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4580
4581    Temp offset;
4582    if (ctx->options->chip_class < GFX8)
4583       offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4584    else
4585       offset = get_ssa_temp(ctx, instr->src[1].ssa);
4586
4587    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4588    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4589
4590    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4591
4592    aco_opcode op32, op64;
4593    switch (instr->intrinsic) {
4594       case nir_intrinsic_ssbo_atomic_add:
4595          op32 = aco_opcode::buffer_atomic_add;
4596          op64 = aco_opcode::buffer_atomic_add_x2;
4597          break;
4598       case nir_intrinsic_ssbo_atomic_imin:
4599          op32 = aco_opcode::buffer_atomic_smin;
4600          op64 = aco_opcode::buffer_atomic_smin_x2;
4601          break;
4602       case nir_intrinsic_ssbo_atomic_umin:
4603          op32 = aco_opcode::buffer_atomic_umin;
4604          op64 = aco_opcode::buffer_atomic_umin_x2;
4605          break;
4606       case nir_intrinsic_ssbo_atomic_imax:
4607          op32 = aco_opcode::buffer_atomic_smax;
4608          op64 = aco_opcode::buffer_atomic_smax_x2;
4609          break;
4610       case nir_intrinsic_ssbo_atomic_umax:
4611          op32 = aco_opcode::buffer_atomic_umax;
4612          op64 = aco_opcode::buffer_atomic_umax_x2;
4613          break;
4614       case nir_intrinsic_ssbo_atomic_and:
4615          op32 = aco_opcode::buffer_atomic_and;
4616          op64 = aco_opcode::buffer_atomic_and_x2;
4617          break;
4618       case nir_intrinsic_ssbo_atomic_or:
4619          op32 = aco_opcode::buffer_atomic_or;
4620          op64 = aco_opcode::buffer_atomic_or_x2;
4621          break;
4622       case nir_intrinsic_ssbo_atomic_xor:
4623          op32 = aco_opcode::buffer_atomic_xor;
4624          op64 = aco_opcode::buffer_atomic_xor_x2;
4625          break;
4626       case nir_intrinsic_ssbo_atomic_exchange:
4627          op32 = aco_opcode::buffer_atomic_swap;
4628          op64 = aco_opcode::buffer_atomic_swap_x2;
4629          break;
4630       case nir_intrinsic_ssbo_atomic_comp_swap:
4631          op32 = aco_opcode::buffer_atomic_cmpswap;
4632          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4633          break;
4634       default:
4635          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4636    }
4637    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4638    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4639    mubuf->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4640    mubuf->operands[1] = Operand(rsrc);
4641    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4642    mubuf->operands[3] = Operand(data);
4643    if (return_previous)
4644       mubuf->definitions[0] = Definition(dst);
4645    mubuf->offset = 0;
4646    mubuf->offen = (offset.type() == RegType::vgpr);
4647    mubuf->glc = return_previous;
4648    mubuf->dlc = false; /* Not needed for atomics */
4649    mubuf->disable_wqm = true;
4650    mubuf->barrier = barrier_buffer;
4651    ctx->program->needs_exact = true;
4652    ctx->block->instructions.emplace_back(std::move(mubuf));
4653 }
4654
4655 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4656
4657    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4658    Builder bld(ctx->program, ctx->block);
4659    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4660    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4661 }
4662
4663 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4664 {
4665    Builder bld(ctx->program, ctx->block);
4666    unsigned num_components = instr->num_components;
4667    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4668
4669    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4670    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4671
4672    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4673    bool dlc = glc && ctx->options->chip_class >= GFX10;
4674    aco_opcode op;
4675    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4676       bool global = ctx->options->chip_class >= GFX9;
4677       aco_opcode op;
4678       switch (num_bytes) {
4679       case 4:
4680          op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4681          break;
4682       case 8:
4683          op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4684          break;
4685       case 12:
4686          op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4687          break;
4688       case 16:
4689          op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
4690          break;
4691       default:
4692          unreachable("load_global not implemented for this size.");
4693       }
4694       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
4695       flat->operands[0] = Operand(addr);
4696       flat->operands[1] = Operand(s1);
4697       flat->glc = glc;
4698       flat->dlc = dlc;
4699       flat->barrier = barrier_buffer;
4700
4701       if (dst.type() == RegType::sgpr) {
4702          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4703          flat->definitions[0] = Definition(vec);
4704          ctx->block->instructions.emplace_back(std::move(flat));
4705          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
4706       } else {
4707          flat->definitions[0] = Definition(dst);
4708          ctx->block->instructions.emplace_back(std::move(flat));
4709       }
4710       emit_split_vector(ctx, dst, num_components);
4711    } else {
4712       switch (num_bytes) {
4713          case 4:
4714             op = aco_opcode::s_load_dword;
4715             break;
4716          case 8:
4717             op = aco_opcode::s_load_dwordx2;
4718             break;
4719          case 12:
4720          case 16:
4721             op = aco_opcode::s_load_dwordx4;
4722             break;
4723          default:
4724             unreachable("load_global not implemented for this size.");
4725       }
4726       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4727       load->operands[0] = Operand(addr);
4728       load->operands[1] = Operand(0u);
4729       load->definitions[0] = Definition(dst);
4730       load->glc = glc;
4731       load->dlc = dlc;
4732       load->barrier = barrier_buffer;
4733       assert(ctx->options->chip_class >= GFX8 || !glc);
4734
4735       if (dst.size() == 3) {
4736          /* trim vector */
4737          Temp vec = bld.tmp(s4);
4738          load->definitions[0] = Definition(vec);
4739          ctx->block->instructions.emplace_back(std::move(load));
4740          emit_split_vector(ctx, vec, 4);
4741
4742          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4743                     emit_extract_vector(ctx, vec, 0, s1),
4744                     emit_extract_vector(ctx, vec, 1, s1),
4745                     emit_extract_vector(ctx, vec, 2, s1));
4746       } else {
4747          ctx->block->instructions.emplace_back(std::move(load));
4748       }
4749    }
4750 }
4751
4752 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
4753 {
4754    Builder bld(ctx->program, ctx->block);
4755    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4756
4757    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4758    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4759
4760    unsigned writemask = nir_intrinsic_write_mask(instr);
4761    while (writemask) {
4762       int start, count;
4763       u_bit_scan_consecutive_range(&writemask, &start, &count);
4764       unsigned num_bytes = count * elem_size_bytes;
4765
4766       Temp write_data = data;
4767       if (count != instr->num_components) {
4768          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4769          for (int i = 0; i < count; i++)
4770             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
4771          write_data = bld.tmp(RegType::vgpr, count);
4772          vec->definitions[0] = Definition(write_data);
4773          ctx->block->instructions.emplace_back(std::move(vec));
4774       }
4775
4776       unsigned offset = start * elem_size_bytes;
4777       if (offset > 0 && ctx->options->chip_class < GFX9) {
4778          Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
4779          Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
4780          Temp carry = bld.tmp(bld.lm);
4781          bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
4782
4783          bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
4784                   Operand(offset), addr0);
4785          bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
4786                   Operand(0u), addr1,
4787                   carry).def(1).setHint(vcc);
4788
4789          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
4790
4791          offset = 0;
4792       }
4793
4794       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4795       bool global = ctx->options->chip_class >= GFX9;
4796       aco_opcode op;
4797       switch (num_bytes) {
4798       case 4:
4799          op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
4800          break;
4801       case 8:
4802          op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
4803          break;
4804       case 12:
4805          op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
4806          break;
4807       case 16:
4808          op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
4809          break;
4810       default:
4811          unreachable("store_global not implemented for this size.");
4812       }
4813       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
4814       flat->operands[0] = Operand(addr);
4815       flat->operands[1] = Operand(s1);
4816       flat->operands[2] = Operand(data);
4817       flat->glc = glc;
4818       flat->dlc = false;
4819       flat->offset = offset;
4820       flat->disable_wqm = true;
4821       flat->barrier = barrier_buffer;
4822       ctx->program->needs_exact = true;
4823       ctx->block->instructions.emplace_back(std::move(flat));
4824    }
4825 }
4826
4827 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4828 {
4829    /* return the previous value if dest is ever used */
4830    bool return_previous = false;
4831    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4832       return_previous = true;
4833       break;
4834    }
4835    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4836       return_previous = true;
4837       break;
4838    }
4839
4840    Builder bld(ctx->program, ctx->block);
4841    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4842    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4843
4844    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
4845       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4846                         get_ssa_temp(ctx, instr->src[2].ssa), data);
4847
4848    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4849
4850    bool global = ctx->options->chip_class >= GFX9;
4851    aco_opcode op32, op64;
4852    switch (instr->intrinsic) {
4853       case nir_intrinsic_global_atomic_add:
4854          op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
4855          op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
4856          break;
4857       case nir_intrinsic_global_atomic_imin:
4858          op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
4859          op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
4860          break;
4861       case nir_intrinsic_global_atomic_umin:
4862          op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
4863          op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
4864          break;
4865       case nir_intrinsic_global_atomic_imax:
4866          op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
4867          op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
4868          break;
4869       case nir_intrinsic_global_atomic_umax:
4870          op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
4871          op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
4872          break;
4873       case nir_intrinsic_global_atomic_and:
4874          op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
4875          op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
4876          break;
4877       case nir_intrinsic_global_atomic_or:
4878          op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
4879          op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
4880          break;
4881       case nir_intrinsic_global_atomic_xor:
4882          op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
4883          op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
4884          break;
4885       case nir_intrinsic_global_atomic_exchange:
4886          op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
4887          op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
4888          break;
4889       case nir_intrinsic_global_atomic_comp_swap:
4890          op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
4891          op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
4892          break;
4893       default:
4894          unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
4895    }
4896    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4897    aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
4898    flat->operands[0] = Operand(addr);
4899    flat->operands[1] = Operand(s1);
4900    flat->operands[2] = Operand(data);
4901    if (return_previous)
4902       flat->definitions[0] = Definition(dst);
4903    flat->glc = return_previous;
4904    flat->dlc = false; /* Not needed for atomics */
4905    flat->offset = 0;
4906    flat->disable_wqm = true;
4907    flat->barrier = barrier_buffer;
4908    ctx->program->needs_exact = true;
4909    ctx->block->instructions.emplace_back(std::move(flat));
4910 }
4911
4912 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
4913    Builder bld(ctx->program, ctx->block);
4914    switch(instr->intrinsic) {
4915       case nir_intrinsic_group_memory_barrier:
4916       case nir_intrinsic_memory_barrier:
4917          bld.barrier(aco_opcode::p_memory_barrier_all);
4918          break;
4919       case nir_intrinsic_memory_barrier_atomic_counter:
4920          bld.barrier(aco_opcode::p_memory_barrier_atomic);
4921          break;
4922       case nir_intrinsic_memory_barrier_buffer:
4923          bld.barrier(aco_opcode::p_memory_barrier_buffer);
4924          break;
4925       case nir_intrinsic_memory_barrier_image:
4926          bld.barrier(aco_opcode::p_memory_barrier_image);
4927          break;
4928       case nir_intrinsic_memory_barrier_shared:
4929          bld.barrier(aco_opcode::p_memory_barrier_shared);
4930          break;
4931       default:
4932          unreachable("Unimplemented memory barrier intrinsic");
4933          break;
4934    }
4935 }
4936
4937 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4938 {
4939    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4940    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4941    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
4942    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4943    Builder bld(ctx->program, ctx->block);
4944
4945    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
4946    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4947    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
4948 }
4949
4950 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4951 {
4952    unsigned writemask = nir_intrinsic_write_mask(instr);
4953    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4954    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4955    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4956    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
4957
4958    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4959    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
4960 }
4961
4962 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4963 {
4964    unsigned offset = nir_intrinsic_base(instr);
4965    Operand m = load_lds_size_m0(ctx);
4966    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4967    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4968
4969    unsigned num_operands = 3;
4970    aco_opcode op32, op64, op32_rtn, op64_rtn;
4971    switch(instr->intrinsic) {
4972       case nir_intrinsic_shared_atomic_add:
4973          op32 = aco_opcode::ds_add_u32;
4974          op64 = aco_opcode::ds_add_u64;
4975          op32_rtn = aco_opcode::ds_add_rtn_u32;
4976          op64_rtn = aco_opcode::ds_add_rtn_u64;
4977          break;
4978       case nir_intrinsic_shared_atomic_imin:
4979          op32 = aco_opcode::ds_min_i32;
4980          op64 = aco_opcode::ds_min_i64;
4981          op32_rtn = aco_opcode::ds_min_rtn_i32;
4982          op64_rtn = aco_opcode::ds_min_rtn_i64;
4983          break;
4984       case nir_intrinsic_shared_atomic_umin:
4985          op32 = aco_opcode::ds_min_u32;
4986          op64 = aco_opcode::ds_min_u64;
4987          op32_rtn = aco_opcode::ds_min_rtn_u32;
4988          op64_rtn = aco_opcode::ds_min_rtn_u64;
4989          break;
4990       case nir_intrinsic_shared_atomic_imax:
4991          op32 = aco_opcode::ds_max_i32;
4992          op64 = aco_opcode::ds_max_i64;
4993          op32_rtn = aco_opcode::ds_max_rtn_i32;
4994          op64_rtn = aco_opcode::ds_max_rtn_i64;
4995          break;
4996       case nir_intrinsic_shared_atomic_umax:
4997          op32 = aco_opcode::ds_max_u32;
4998          op64 = aco_opcode::ds_max_u64;
4999          op32_rtn = aco_opcode::ds_max_rtn_u32;
5000          op64_rtn = aco_opcode::ds_max_rtn_u64;
5001          break;
5002       case nir_intrinsic_shared_atomic_and:
5003          op32 = aco_opcode::ds_and_b32;
5004          op64 = aco_opcode::ds_and_b64;
5005          op32_rtn = aco_opcode::ds_and_rtn_b32;
5006          op64_rtn = aco_opcode::ds_and_rtn_b64;
5007          break;
5008       case nir_intrinsic_shared_atomic_or:
5009          op32 = aco_opcode::ds_or_b32;
5010          op64 = aco_opcode::ds_or_b64;
5011          op32_rtn = aco_opcode::ds_or_rtn_b32;
5012          op64_rtn = aco_opcode::ds_or_rtn_b64;
5013          break;
5014       case nir_intrinsic_shared_atomic_xor:
5015          op32 = aco_opcode::ds_xor_b32;
5016          op64 = aco_opcode::ds_xor_b64;
5017          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5018          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5019          break;
5020       case nir_intrinsic_shared_atomic_exchange:
5021          op32 = aco_opcode::ds_write_b32;
5022          op64 = aco_opcode::ds_write_b64;
5023          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5024          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5025          break;
5026       case nir_intrinsic_shared_atomic_comp_swap:
5027          op32 = aco_opcode::ds_cmpst_b32;
5028          op64 = aco_opcode::ds_cmpst_b64;
5029          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5030          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5031          num_operands = 4;
5032          break;
5033       default:
5034          unreachable("Unhandled shared atomic intrinsic");
5035    }
5036
5037    /* return the previous value if dest is ever used */
5038    bool return_previous = false;
5039    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5040       return_previous = true;
5041       break;
5042    }
5043    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5044       return_previous = true;
5045       break;
5046    }
5047
5048    aco_opcode op;
5049    if (data.size() == 1) {
5050       assert(instr->dest.ssa.bit_size == 32);
5051       op = return_previous ? op32_rtn : op32;
5052    } else {
5053       assert(instr->dest.ssa.bit_size == 64);
5054       op = return_previous ? op64_rtn : op64;
5055    }
5056
5057    if (offset > 65535) {
5058       Builder bld(ctx->program, ctx->block);
5059       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5060       offset = 0;
5061    }
5062
5063    aco_ptr<DS_instruction> ds;
5064    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5065    ds->operands[0] = Operand(address);
5066    ds->operands[1] = Operand(data);
5067    if (num_operands == 4)
5068       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5069    ds->operands[num_operands - 1] = m;
5070    ds->offset0 = offset;
5071    if (return_previous)
5072       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5073    ctx->block->instructions.emplace_back(std::move(ds));
5074 }
5075
5076 Temp get_scratch_resource(isel_context *ctx)
5077 {
5078    Builder bld(ctx->program, ctx->block);
5079    Temp scratch_addr = ctx->program->private_segment_buffer;
5080    if (ctx->stage != compute_cs)
5081       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5082
5083    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5084                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5085
5086    if (ctx->program->chip_class >= GFX10) {
5087       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5088                    S_008F0C_OOB_SELECT(3) |
5089                    S_008F0C_RESOURCE_LEVEL(1);
5090    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5091       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5092                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5093    }
5094
5095    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5096    if (ctx->program->chip_class <= GFX8)
5097       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5098
5099    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5100 }
5101
5102 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5103    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5104    Builder bld(ctx->program, ctx->block);
5105    Temp rsrc = get_scratch_resource(ctx);
5106    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5107    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5108
5109    aco_opcode op;
5110    switch (dst.size()) {
5111       case 1:
5112          op = aco_opcode::buffer_load_dword;
5113          break;
5114       case 2:
5115          op = aco_opcode::buffer_load_dwordx2;
5116          break;
5117       case 3:
5118          op = aco_opcode::buffer_load_dwordx3;
5119          break;
5120       case 4:
5121          op = aco_opcode::buffer_load_dwordx4;
5122          break;
5123       case 6:
5124       case 8: {
5125          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5126          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5127                                 bld.def(v4), offset, rsrc,
5128                                 ctx->program->scratch_offset, 0, true);
5129          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5130                                                   aco_opcode::buffer_load_dwordx4,
5131                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5132                                 offset, rsrc, ctx->program->scratch_offset, 16, true);
5133          emit_split_vector(ctx, lower, 2);
5134          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5135          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5136          if (dst.size() == 8) {
5137             emit_split_vector(ctx, upper, 2);
5138             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5139             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5140          } else {
5141             elems[2] = upper;
5142          }
5143
5144          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5145                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5146          for (unsigned i = 0; i < dst.size() / 2; i++)
5147             vec->operands[i] = Operand(elems[i]);
5148          vec->definitions[0] = Definition(dst);
5149          bld.insert(std::move(vec));
5150          ctx->allocated_vec.emplace(dst.id(), elems);
5151          return;
5152       }
5153       default:
5154          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5155    }
5156
5157    bld.mubuf(op, Definition(dst), offset, rsrc, ctx->program->scratch_offset, 0, true);
5158    emit_split_vector(ctx, dst, instr->num_components);
5159 }
5160
5161 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5162    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5163    Builder bld(ctx->program, ctx->block);
5164    Temp rsrc = get_scratch_resource(ctx);
5165    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5166    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5167
5168    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5169    unsigned writemask = nir_intrinsic_write_mask(instr);
5170
5171    while (writemask) {
5172       int start, count;
5173       u_bit_scan_consecutive_range(&writemask, &start, &count);
5174       int num_bytes = count * elem_size_bytes;
5175
5176       if (num_bytes > 16) {
5177          assert(elem_size_bytes == 8);
5178          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5179          count = 2;
5180          num_bytes = 16;
5181       }
5182
5183       // TODO: check alignment of sub-dword stores
5184       // TODO: split 3 bytes. there is no store instruction for that
5185
5186       Temp write_data;
5187       if (count != instr->num_components) {
5188          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5189          for (int i = 0; i < count; i++) {
5190             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5191             vec->operands[i] = Operand(elem);
5192          }
5193          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5194          vec->definitions[0] = Definition(write_data);
5195          ctx->block->instructions.emplace_back(std::move(vec));
5196       } else {
5197          write_data = data;
5198       }
5199
5200       aco_opcode op;
5201       switch (num_bytes) {
5202          case 4:
5203             op = aco_opcode::buffer_store_dword;
5204             break;
5205          case 8:
5206             op = aco_opcode::buffer_store_dwordx2;
5207             break;
5208          case 12:
5209             op = aco_opcode::buffer_store_dwordx3;
5210             break;
5211          case 16:
5212             op = aco_opcode::buffer_store_dwordx4;
5213             break;
5214          default:
5215             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5216       }
5217
5218       bld.mubuf(op, offset, rsrc, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5219    }
5220 }
5221
5222 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5223    uint8_t log2_ps_iter_samples;
5224    if (ctx->program->info->ps.force_persample) {
5225       log2_ps_iter_samples =
5226          util_logbase2(ctx->options->key.fs.num_samples);
5227    } else {
5228       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5229    }
5230
5231    /* The bit pattern matches that used by fixed function fragment
5232     * processing. */
5233    static const unsigned ps_iter_masks[] = {
5234       0xffff, /* not used */
5235       0x5555,
5236       0x1111,
5237       0x0101,
5238       0x0001,
5239    };
5240    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5241
5242    Builder bld(ctx->program, ctx->block);
5243
5244    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5245                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5246    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5247    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5248    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5249    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5250 }
5251
5252 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5253 {
5254    Builder bld(ctx->program, ctx->block);
5255
5256    if (cluster_size == 1) {
5257       return src;
5258    } if (op == nir_op_iand && cluster_size == 4) {
5259       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5260       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5261       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
5262                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
5263    } else if (op == nir_op_ior && cluster_size == 4) {
5264       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5265       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
5266                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
5267    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
5268       //subgroupAnd(val) -> (exec & ~val) == 0
5269       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5270       return bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5271    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
5272       //subgroupOr(val) -> (val & exec) != 0
5273       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
5274       return bool_to_vector_condition(ctx, tmp);
5275    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
5276       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5277       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5278       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
5279       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5280       return bool_to_vector_condition(ctx, tmp);
5281    } else {
5282       //subgroupClustered{And,Or,Xor}(val, n) ->
5283       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
5284       //cluster_offset = ~(n - 1) & lane_id
5285       //cluster_mask = ((1 << n) - 1)
5286       //subgroupClusteredAnd():
5287       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5288       //subgroupClusteredOr():
5289       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5290       //subgroupClusteredXor():
5291       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5292       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
5293       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5294
5295       Temp tmp;
5296       if (op == nir_op_iand)
5297          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5298       else
5299          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5300
5301       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5302
5303       if (ctx->program->chip_class <= GFX7)
5304          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
5305       else if (ctx->program->wave_size == 64)
5306          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5307       else
5308          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
5309       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5310       if (cluster_mask != 0xffffffff)
5311          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5312
5313       Definition cmp_def = Definition();
5314       if (op == nir_op_iand) {
5315          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
5316       } else if (op == nir_op_ior) {
5317          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5318       } else if (op == nir_op_ixor) {
5319          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5320                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5321          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5322       }
5323       cmp_def.setHint(vcc);
5324       return cmp_def.getTemp();
5325    }
5326 }
5327
5328 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5329 {
5330    Builder bld(ctx->program, ctx->block);
5331
5332    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5333    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5334    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5335    Temp tmp;
5336    if (op == nir_op_iand)
5337       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5338    else
5339       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
5340
5341    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5342    Temp lo = lohi.def(0).getTemp();
5343    Temp hi = lohi.def(1).getTemp();
5344    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
5345
5346    Definition cmp_def = Definition();
5347    if (op == nir_op_iand)
5348       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5349    else if (op == nir_op_ior)
5350       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5351    else if (op == nir_op_ixor)
5352       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
5353                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5354    cmp_def.setHint(vcc);
5355    return cmp_def.getTemp();
5356 }
5357
5358 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5359 {
5360    Builder bld(ctx->program, ctx->block);
5361
5362    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5363    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5364    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5365    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5366    if (op == nir_op_iand)
5367       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5368    else if (op == nir_op_ior)
5369       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5370    else if (op == nir_op_ixor)
5371       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5372
5373    assert(false);
5374    return Temp();
5375 }
5376
5377 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5378 {
5379    Builder bld(ctx->program, ctx->block);
5380    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5381    if (src.regClass().type() == RegType::vgpr) {
5382       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5383    } else if (src.regClass() == s1) {
5384       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5385    } else if (src.regClass() == s2) {
5386       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5387    } else {
5388       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5389       nir_print_instr(&instr->instr, stderr);
5390       fprintf(stderr, "\n");
5391    }
5392 }
5393
5394 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5395 {
5396    Builder bld(ctx->program, ctx->block);
5397    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
5398    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
5399    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
5400
5401    Temp ddx_1, ddx_2, ddy_1, ddy_2;
5402    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
5403    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
5404    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
5405
5406    /* Build DD X/Y */
5407    if (ctx->program->chip_class >= GFX8) {
5408       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
5409       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
5410       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
5411       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
5412       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
5413       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
5414    } else {
5415       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
5416       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
5417       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
5418       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
5419       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
5420       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
5421       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
5422       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
5423       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
5424       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
5425    }
5426
5427    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5428    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
5429    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
5430    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
5431    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
5432    Temp wqm1 = bld.tmp(v1);
5433    emit_wqm(ctx, tmp1, wqm1, true);
5434    Temp wqm2 = bld.tmp(v1);
5435    emit_wqm(ctx, tmp2, wqm2, true);
5436    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
5437    return;
5438 }
5439
5440 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
5441 {
5442    Builder bld(ctx->program, ctx->block);
5443    switch(instr->intrinsic) {
5444    case nir_intrinsic_load_barycentric_sample:
5445    case nir_intrinsic_load_barycentric_pixel:
5446    case nir_intrinsic_load_barycentric_centroid: {
5447       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
5448       Temp bary = Temp(0, s2);
5449       switch (mode) {
5450       case INTERP_MODE_SMOOTH:
5451       case INTERP_MODE_NONE:
5452          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5453             bary = get_arg(ctx, ctx->args->ac.persp_center);
5454          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5455             bary = ctx->persp_centroid;
5456          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5457             bary = get_arg(ctx, ctx->args->ac.persp_sample);
5458          break;
5459       case INTERP_MODE_NOPERSPECTIVE:
5460          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5461             bary = get_arg(ctx, ctx->args->ac.linear_center);
5462          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5463             bary = ctx->linear_centroid;
5464          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5465             bary = get_arg(ctx, ctx->args->ac.linear_sample);
5466          break;
5467       default:
5468          break;
5469       }
5470       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5471       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
5472       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
5473       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5474                  Operand(p1), Operand(p2));
5475       emit_split_vector(ctx, dst, 2);
5476       break;
5477    }
5478    case nir_intrinsic_load_barycentric_at_sample: {
5479       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
5480       switch (ctx->options->key.fs.num_samples) {
5481          case 2: sample_pos_offset += 1 << 3; break;
5482          case 4: sample_pos_offset += 3 << 3; break;
5483          case 8: sample_pos_offset += 7 << 3; break;
5484          default: break;
5485       }
5486       Temp sample_pos;
5487       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5488       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
5489       Temp private_segment_buffer = ctx->program->private_segment_buffer;
5490       if (addr.type() == RegType::sgpr) {
5491          Operand offset;
5492          if (const_addr) {
5493             sample_pos_offset += const_addr->u32 << 3;
5494             offset = Operand(sample_pos_offset);
5495          } else if (ctx->options->chip_class >= GFX9) {
5496             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5497          } else {
5498             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
5499             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5500          }
5501          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand(offset));
5502
5503       } else if (ctx->options->chip_class >= GFX9) {
5504          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5505          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
5506       } else {
5507          /* addr += private_segment_buffer + sample_pos_offset */
5508          Temp tmp0 = bld.tmp(s1);
5509          Temp tmp1 = bld.tmp(s1);
5510          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
5511          Definition scc_tmp = bld.def(s1, scc);
5512          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
5513          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
5514          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5515          Temp pck0 = bld.tmp(v1);
5516          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
5517          tmp1 = as_vgpr(ctx, tmp1);
5518          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
5519          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
5520
5521          /* sample_pos = flat_load_dwordx2 addr */
5522          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
5523       }
5524
5525       /* sample_pos -= 0.5 */
5526       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
5527       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
5528       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
5529       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
5530       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
5531
5532       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5533       break;
5534    }
5535    case nir_intrinsic_load_barycentric_at_offset: {
5536       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
5537       RegClass rc = RegClass(offset.type(), 1);
5538       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
5539       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
5540       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5541       break;
5542    }
5543    case nir_intrinsic_load_front_face: {
5544       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5545                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
5546       break;
5547    }
5548    case nir_intrinsic_load_view_index:
5549    case nir_intrinsic_load_layer_id: {
5550       if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & sw_vs)) {
5551          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5552          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
5553          break;
5554       }
5555
5556       unsigned idx = nir_intrinsic_base(instr);
5557       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5558                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
5559       break;
5560    }
5561    case nir_intrinsic_load_frag_coord: {
5562       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
5563       break;
5564    }
5565    case nir_intrinsic_load_sample_pos: {
5566       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
5567       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
5568       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5569                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
5570                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
5571       break;
5572    }
5573    case nir_intrinsic_load_interpolated_input:
5574       visit_load_interpolated_input(ctx, instr);
5575       break;
5576    case nir_intrinsic_store_output:
5577       visit_store_output(ctx, instr);
5578       break;
5579    case nir_intrinsic_load_input:
5580       visit_load_input(ctx, instr);
5581       break;
5582    case nir_intrinsic_load_ubo:
5583       visit_load_ubo(ctx, instr);
5584       break;
5585    case nir_intrinsic_load_push_constant:
5586       visit_load_push_constant(ctx, instr);
5587       break;
5588    case nir_intrinsic_load_constant:
5589       visit_load_constant(ctx, instr);
5590       break;
5591    case nir_intrinsic_vulkan_resource_index:
5592       visit_load_resource(ctx, instr);
5593       break;
5594    case nir_intrinsic_discard:
5595       visit_discard(ctx, instr);
5596       break;
5597    case nir_intrinsic_discard_if:
5598       visit_discard_if(ctx, instr);
5599       break;
5600    case nir_intrinsic_load_shared:
5601       visit_load_shared(ctx, instr);
5602       break;
5603    case nir_intrinsic_store_shared:
5604       visit_store_shared(ctx, instr);
5605       break;
5606    case nir_intrinsic_shared_atomic_add:
5607    case nir_intrinsic_shared_atomic_imin:
5608    case nir_intrinsic_shared_atomic_umin:
5609    case nir_intrinsic_shared_atomic_imax:
5610    case nir_intrinsic_shared_atomic_umax:
5611    case nir_intrinsic_shared_atomic_and:
5612    case nir_intrinsic_shared_atomic_or:
5613    case nir_intrinsic_shared_atomic_xor:
5614    case nir_intrinsic_shared_atomic_exchange:
5615    case nir_intrinsic_shared_atomic_comp_swap:
5616       visit_shared_atomic(ctx, instr);
5617       break;
5618    case nir_intrinsic_image_deref_load:
5619       visit_image_load(ctx, instr);
5620       break;
5621    case nir_intrinsic_image_deref_store:
5622       visit_image_store(ctx, instr);
5623       break;
5624    case nir_intrinsic_image_deref_atomic_add:
5625    case nir_intrinsic_image_deref_atomic_umin:
5626    case nir_intrinsic_image_deref_atomic_imin:
5627    case nir_intrinsic_image_deref_atomic_umax:
5628    case nir_intrinsic_image_deref_atomic_imax:
5629    case nir_intrinsic_image_deref_atomic_and:
5630    case nir_intrinsic_image_deref_atomic_or:
5631    case nir_intrinsic_image_deref_atomic_xor:
5632    case nir_intrinsic_image_deref_atomic_exchange:
5633    case nir_intrinsic_image_deref_atomic_comp_swap:
5634       visit_image_atomic(ctx, instr);
5635       break;
5636    case nir_intrinsic_image_deref_size:
5637       visit_image_size(ctx, instr);
5638       break;
5639    case nir_intrinsic_load_ssbo:
5640       visit_load_ssbo(ctx, instr);
5641       break;
5642    case nir_intrinsic_store_ssbo:
5643       visit_store_ssbo(ctx, instr);
5644       break;
5645    case nir_intrinsic_load_global:
5646       visit_load_global(ctx, instr);
5647       break;
5648    case nir_intrinsic_store_global:
5649       visit_store_global(ctx, instr);
5650       break;
5651    case nir_intrinsic_global_atomic_add:
5652    case nir_intrinsic_global_atomic_imin:
5653    case nir_intrinsic_global_atomic_umin:
5654    case nir_intrinsic_global_atomic_imax:
5655    case nir_intrinsic_global_atomic_umax:
5656    case nir_intrinsic_global_atomic_and:
5657    case nir_intrinsic_global_atomic_or:
5658    case nir_intrinsic_global_atomic_xor:
5659    case nir_intrinsic_global_atomic_exchange:
5660    case nir_intrinsic_global_atomic_comp_swap:
5661       visit_global_atomic(ctx, instr);
5662       break;
5663    case nir_intrinsic_ssbo_atomic_add:
5664    case nir_intrinsic_ssbo_atomic_imin:
5665    case nir_intrinsic_ssbo_atomic_umin:
5666    case nir_intrinsic_ssbo_atomic_imax:
5667    case nir_intrinsic_ssbo_atomic_umax:
5668    case nir_intrinsic_ssbo_atomic_and:
5669    case nir_intrinsic_ssbo_atomic_or:
5670    case nir_intrinsic_ssbo_atomic_xor:
5671    case nir_intrinsic_ssbo_atomic_exchange:
5672    case nir_intrinsic_ssbo_atomic_comp_swap:
5673       visit_atomic_ssbo(ctx, instr);
5674       break;
5675    case nir_intrinsic_load_scratch:
5676       visit_load_scratch(ctx, instr);
5677       break;
5678    case nir_intrinsic_store_scratch:
5679       visit_store_scratch(ctx, instr);
5680       break;
5681    case nir_intrinsic_get_buffer_size:
5682       visit_get_buffer_size(ctx, instr);
5683       break;
5684    case nir_intrinsic_barrier: {
5685       unsigned* bsize = ctx->program->info->cs.block_size;
5686       unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
5687       if (workgroup_size > ctx->program->wave_size)
5688          bld.sopp(aco_opcode::s_barrier);
5689       break;
5690    }
5691    case nir_intrinsic_group_memory_barrier:
5692    case nir_intrinsic_memory_barrier:
5693    case nir_intrinsic_memory_barrier_atomic_counter:
5694    case nir_intrinsic_memory_barrier_buffer:
5695    case nir_intrinsic_memory_barrier_image:
5696    case nir_intrinsic_memory_barrier_shared:
5697       emit_memory_barrier(ctx, instr);
5698       break;
5699    case nir_intrinsic_load_num_work_groups: {
5700       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5701       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
5702       emit_split_vector(ctx, dst, 3);
5703       break;
5704    }
5705    case nir_intrinsic_load_local_invocation_id: {
5706       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5707       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
5708       emit_split_vector(ctx, dst, 3);
5709       break;
5710    }
5711    case nir_intrinsic_load_work_group_id: {
5712       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5713       struct ac_arg *args = ctx->args->ac.workgroup_ids;
5714       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5715                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
5716                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
5717                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
5718       emit_split_vector(ctx, dst, 3);
5719       break;
5720    }
5721    case nir_intrinsic_load_local_invocation_index: {
5722       Temp id = emit_mbcnt(ctx, bld.def(v1));
5723
5724       /* The tg_size bits [6:11] contain the subgroup id,
5725        * we need this multiplied by the wave size, and then OR the thread id to it.
5726        */
5727       if (ctx->program->wave_size == 64) {
5728          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
5729          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
5730                                 get_arg(ctx, ctx->args->ac.tg_size));
5731          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
5732       } else {
5733          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
5734          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
5735                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5736          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
5737       }
5738       break;
5739    }
5740    case nir_intrinsic_load_subgroup_id: {
5741       if (ctx->stage == compute_cs) {
5742          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
5743                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5744       } else {
5745          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
5746       }
5747       break;
5748    }
5749    case nir_intrinsic_load_subgroup_invocation: {
5750       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
5751       break;
5752    }
5753    case nir_intrinsic_load_num_subgroups: {
5754       if (ctx->stage == compute_cs)
5755          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
5756                   get_arg(ctx, ctx->args->ac.tg_size));
5757       else
5758          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
5759       break;
5760    }
5761    case nir_intrinsic_ballot: {
5762       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5763       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5764       Definition tmp = bld.def(dst.regClass());
5765       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
5766       if (instr->src[0].ssa->bit_size == 1) {
5767          assert(src.regClass() == bld.lm);
5768          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
5769       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
5770          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
5771       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
5772          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
5773       } else {
5774          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5775          nir_print_instr(&instr->instr, stderr);
5776          fprintf(stderr, "\n");
5777       }
5778       if (dst.size() != bld.lm.size()) {
5779          /* Wave32 with ballot size set to 64 */
5780          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
5781       }
5782       emit_wqm(ctx, tmp.getTemp(), dst);
5783       break;
5784    }
5785    case nir_intrinsic_shuffle:
5786    case nir_intrinsic_read_invocation: {
5787       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5788       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
5789          emit_uniform_subgroup(ctx, instr, src);
5790       } else {
5791          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
5792          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
5793             tid = bld.as_uniform(tid);
5794          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5795          if (src.regClass() == v1) {
5796             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
5797          } else if (src.regClass() == v2) {
5798             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5799             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5800             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
5801             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
5802             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5803             emit_split_vector(ctx, dst, 2);
5804          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
5805             assert(src.regClass() == bld.lm);
5806             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
5807             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5808          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
5809             assert(src.regClass() == bld.lm);
5810             Temp tmp;
5811             if (ctx->program->chip_class <= GFX7)
5812                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
5813             else if (ctx->program->wave_size == 64)
5814                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
5815             else
5816                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
5817             tmp = emit_extract_vector(ctx, tmp, 0, v1);
5818             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
5819             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
5820          } else {
5821             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5822             nir_print_instr(&instr->instr, stderr);
5823             fprintf(stderr, "\n");
5824          }
5825       }
5826       break;
5827    }
5828    case nir_intrinsic_load_sample_id: {
5829       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5830                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5831       break;
5832    }
5833    case nir_intrinsic_load_sample_mask_in: {
5834       visit_load_sample_mask_in(ctx, instr);
5835       break;
5836    }
5837    case nir_intrinsic_read_first_invocation: {
5838       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5839       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5840       if (src.regClass() == v1) {
5841          emit_wqm(ctx,
5842                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
5843                   dst);
5844       } else if (src.regClass() == v2) {
5845          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5846          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5847          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
5848          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
5849          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5850          emit_split_vector(ctx, dst, 2);
5851       } else if (instr->dest.ssa.bit_size == 1) {
5852          assert(src.regClass() == bld.lm);
5853          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
5854                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
5855          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5856       } else if (src.regClass() == s1) {
5857          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5858       } else if (src.regClass() == s2) {
5859          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5860       } else {
5861          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5862          nir_print_instr(&instr->instr, stderr);
5863          fprintf(stderr, "\n");
5864       }
5865       break;
5866    }
5867    case nir_intrinsic_vote_all: {
5868       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5869       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5870       assert(src.regClass() == bld.lm);
5871       assert(dst.regClass() == bld.lm);
5872
5873       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5874       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5875       emit_wqm(ctx, val, dst);
5876       break;
5877    }
5878    case nir_intrinsic_vote_any: {
5879       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5880       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5881       assert(src.regClass() == bld.lm);
5882       assert(dst.regClass() == bld.lm);
5883
5884       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5885       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(-1u), Operand(0u), bld.scc(tmp));
5886       emit_wqm(ctx, val, dst);
5887       break;
5888    }
5889    case nir_intrinsic_reduce:
5890    case nir_intrinsic_inclusive_scan:
5891    case nir_intrinsic_exclusive_scan: {
5892       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5893       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5894       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
5895       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
5896          nir_intrinsic_cluster_size(instr) : 0;
5897       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
5898
5899       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
5900          emit_uniform_subgroup(ctx, instr, src);
5901       } else if (instr->dest.ssa.bit_size == 1) {
5902          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
5903             op = nir_op_iand;
5904          else if (op == nir_op_iadd)
5905             op = nir_op_ixor;
5906          else if (op == nir_op_umax || op == nir_op_imax)
5907             op = nir_op_ior;
5908          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
5909
5910          switch (instr->intrinsic) {
5911          case nir_intrinsic_reduce:
5912             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
5913             break;
5914          case nir_intrinsic_exclusive_scan:
5915             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
5916             break;
5917          case nir_intrinsic_inclusive_scan:
5918             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
5919             break;
5920          default:
5921             assert(false);
5922          }
5923       } else if (cluster_size == 1) {
5924          bld.copy(Definition(dst), src);
5925       } else {
5926          src = as_vgpr(ctx, src);
5927
5928          ReduceOp reduce_op;
5929          switch (op) {
5930          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5931             CASE(iadd)
5932             CASE(imul)
5933             CASE(fadd)
5934             CASE(fmul)
5935             CASE(imin)
5936             CASE(umin)
5937             CASE(fmin)
5938             CASE(imax)
5939             CASE(umax)
5940             CASE(fmax)
5941             CASE(iand)
5942             CASE(ior)
5943             CASE(ixor)
5944             default:
5945                unreachable("unknown reduction op");
5946          #undef CASE
5947          }
5948
5949          aco_opcode aco_op;
5950          switch (instr->intrinsic) {
5951             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
5952             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
5953             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
5954             default:
5955                unreachable("unknown reduce intrinsic");
5956          }
5957
5958          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
5959          reduce->operands[0] = Operand(src);
5960          // filled in by aco_reduce_assign.cpp, used internally as part of the
5961          // reduce sequence
5962          assert(dst.size() == 1 || dst.size() == 2);
5963          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
5964          reduce->operands[2] = Operand(v1.as_linear());
5965
5966          Temp tmp_dst = bld.tmp(dst.regClass());
5967          reduce->definitions[0] = Definition(tmp_dst);
5968          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
5969          reduce->definitions[2] = Definition();
5970          reduce->definitions[3] = Definition(scc, s1);
5971          reduce->definitions[4] = Definition();
5972          reduce->reduce_op = reduce_op;
5973          reduce->cluster_size = cluster_size;
5974          ctx->block->instructions.emplace_back(std::move(reduce));
5975
5976          emit_wqm(ctx, tmp_dst, dst);
5977       }
5978       break;
5979    }
5980    case nir_intrinsic_quad_broadcast: {
5981       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5982       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5983          emit_uniform_subgroup(ctx, instr, src);
5984       } else {
5985          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5986          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
5987          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
5988
5989          if (instr->dest.ssa.bit_size == 1) {
5990             assert(src.regClass() == bld.lm);
5991             assert(dst.regClass() == bld.lm);
5992             uint32_t half_mask = 0x11111111u << lane;
5993             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
5994             Temp tmp = bld.tmp(bld.lm);
5995             bld.sop1(Builder::s_wqm, Definition(tmp),
5996                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
5997                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
5998             emit_wqm(ctx, tmp, dst);
5999          } else if (instr->dest.ssa.bit_size == 32) {
6000             if (ctx->program->chip_class >= GFX8)
6001                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6002             else
6003                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6004          } else if (instr->dest.ssa.bit_size == 64) {
6005             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6006             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6007             if (ctx->program->chip_class >= GFX8) {
6008                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6009                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6010             } else {
6011                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6012                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6013             }
6014             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6015             emit_split_vector(ctx, dst, 2);
6016          } else {
6017             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6018             nir_print_instr(&instr->instr, stderr);
6019             fprintf(stderr, "\n");
6020          }
6021       }
6022       break;
6023    }
6024    case nir_intrinsic_quad_swap_horizontal:
6025    case nir_intrinsic_quad_swap_vertical:
6026    case nir_intrinsic_quad_swap_diagonal:
6027    case nir_intrinsic_quad_swizzle_amd: {
6028       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6029       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6030          emit_uniform_subgroup(ctx, instr, src);
6031          break;
6032       }
6033       uint16_t dpp_ctrl = 0;
6034       switch (instr->intrinsic) {
6035       case nir_intrinsic_quad_swap_horizontal:
6036          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6037          break;
6038       case nir_intrinsic_quad_swap_vertical:
6039          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6040          break;
6041       case nir_intrinsic_quad_swap_diagonal:
6042          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6043          break;
6044       case nir_intrinsic_quad_swizzle_amd:
6045          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6046          break;
6047       default:
6048          break;
6049       }
6050       if (ctx->program->chip_class < GFX8)
6051          dpp_ctrl |= (1 << 15);
6052
6053       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6054       if (instr->dest.ssa.bit_size == 1) {
6055          assert(src.regClass() == bld.lm);
6056          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6057          if (ctx->program->chip_class >= GFX8)
6058             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6059          else
6060             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6061          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6062          emit_wqm(ctx, tmp, dst);
6063       } else if (instr->dest.ssa.bit_size == 32) {
6064          Temp tmp;
6065          if (ctx->program->chip_class >= GFX8)
6066             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6067          else
6068             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6069          emit_wqm(ctx, tmp, dst);
6070       } else if (instr->dest.ssa.bit_size == 64) {
6071          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6072          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6073          if (ctx->program->chip_class >= GFX8) {
6074             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6075             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6076          } else {
6077             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6078             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6079          }
6080          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6081          emit_split_vector(ctx, dst, 2);
6082       } else {
6083          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6084          nir_print_instr(&instr->instr, stderr);
6085          fprintf(stderr, "\n");
6086       }
6087       break;
6088    }
6089    case nir_intrinsic_masked_swizzle_amd: {
6090       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6091       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6092          emit_uniform_subgroup(ctx, instr, src);
6093          break;
6094       }
6095       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6096       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6097       if (dst.regClass() == v1) {
6098          emit_wqm(ctx,
6099                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6100                   dst);
6101       } else if (dst.regClass() == v2) {
6102          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6103          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6104          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6105          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6106          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6107          emit_split_vector(ctx, dst, 2);
6108       } else {
6109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6110          nir_print_instr(&instr->instr, stderr);
6111          fprintf(stderr, "\n");
6112       }
6113       break;
6114    }
6115    case nir_intrinsic_write_invocation_amd: {
6116       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6117       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
6118       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
6119       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6120       if (dst.regClass() == v1) {
6121          /* src2 is ignored for writelane. RA assigns the same reg for dst */
6122          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
6123       } else if (dst.regClass() == v2) {
6124          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
6125          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
6126          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
6127          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
6128          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
6129          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
6130          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6131          emit_split_vector(ctx, dst, 2);
6132       } else {
6133          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6134          nir_print_instr(&instr->instr, stderr);
6135          fprintf(stderr, "\n");
6136       }
6137       break;
6138    }
6139    case nir_intrinsic_mbcnt_amd: {
6140       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6141       RegClass rc = RegClass(src.type(), 1);
6142       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
6143       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
6144       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6145       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
6146       emit_wqm(ctx, wqm_tmp, dst);
6147       break;
6148    }
6149    case nir_intrinsic_load_helper_invocation: {
6150       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6151       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
6152       ctx->block->kind |= block_kind_needs_lowering;
6153       ctx->program->needs_exact = true;
6154       break;
6155    }
6156    case nir_intrinsic_is_helper_invocation: {
6157       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6158       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
6159       ctx->block->kind |= block_kind_needs_lowering;
6160       ctx->program->needs_exact = true;
6161       break;
6162    }
6163    case nir_intrinsic_demote:
6164       bld.pseudo(aco_opcode::p_demote_to_helper);
6165       ctx->block->kind |= block_kind_uses_demote;
6166       ctx->program->needs_exact = true;
6167       break;
6168    case nir_intrinsic_demote_if: {
6169       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6170       assert(src.regClass() == bld.lm);
6171       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6172       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
6173       ctx->block->kind |= block_kind_uses_demote;
6174       ctx->program->needs_exact = true;
6175       break;
6176    }
6177    case nir_intrinsic_first_invocation: {
6178       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
6179                get_ssa_temp(ctx, &instr->dest.ssa));
6180       break;
6181    }
6182    case nir_intrinsic_shader_clock:
6183       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
6184       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
6185       break;
6186    case nir_intrinsic_load_vertex_id_zero_base: {
6187       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6188       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
6189       break;
6190    }
6191    case nir_intrinsic_load_first_vertex: {
6192       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6193       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
6194       break;
6195    }
6196    case nir_intrinsic_load_base_instance: {
6197       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6198       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
6199       break;
6200    }
6201    case nir_intrinsic_load_instance_id: {
6202       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6203       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
6204       break;
6205    }
6206    case nir_intrinsic_load_draw_id: {
6207       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6208       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
6209       break;
6210    }
6211    default:
6212       fprintf(stderr, "Unimplemented intrinsic instr: ");
6213       nir_print_instr(&instr->instr, stderr);
6214       fprintf(stderr, "\n");
6215       abort();
6216
6217       break;
6218    }
6219 }
6220
6221
6222 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
6223                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
6224                     enum glsl_base_type *stype)
6225 {
6226    nir_deref_instr *texture_deref_instr = NULL;
6227    nir_deref_instr *sampler_deref_instr = NULL;
6228    int plane = -1;
6229
6230    for (unsigned i = 0; i < instr->num_srcs; i++) {
6231       switch (instr->src[i].src_type) {
6232       case nir_tex_src_texture_deref:
6233          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
6234          break;
6235       case nir_tex_src_sampler_deref:
6236          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
6237          break;
6238       case nir_tex_src_plane:
6239          plane = nir_src_as_int(instr->src[i].src);
6240          break;
6241       default:
6242          break;
6243       }
6244    }
6245
6246    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
6247
6248    if (!sampler_deref_instr)
6249       sampler_deref_instr = texture_deref_instr;
6250
6251    if (plane >= 0) {
6252       assert(instr->op != nir_texop_txf_ms &&
6253              instr->op != nir_texop_samples_identical);
6254       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6255       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6256    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6257       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6258    } else {
6259       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6260    }
6261    if (samp_ptr) {
6262       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6263
6264       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6265          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6266          Builder bld(ctx->program, ctx->block);
6267
6268          /* to avoid unnecessary moves, we split and recombine sampler and image */
6269          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
6270                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6271          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6272          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
6273                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
6274                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
6275          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
6276                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
6277
6278          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
6279          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
6280                                img[0], img[1], img[2], img[3],
6281                                img[4], img[5], img[6], img[7]);
6282          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6283                                 samp[0], samp[1], samp[2], samp[3]);
6284       }
6285    }
6286    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
6287                      instr->op == nir_texop_samples_identical))
6288       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6289 }
6290
6291 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
6292                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
6293 {
6294    Builder bld(ctx->program, ctx->block);
6295
6296    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
6297    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
6298    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
6299
6300    Operand neg_one(0xbf800000u);
6301    Operand one(0x3f800000u);
6302    Operand two(0x40000000u);
6303    Operand four(0x40800000u);
6304
6305    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
6306    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
6307    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
6308
6309    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
6310    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(s2), two, id);
6311    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
6312    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
6313
6314    // select sc
6315    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
6316    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
6317                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
6318                        one, is_ma_y);
6319    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6320
6321    // select tc
6322    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
6323    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
6324    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6325
6326    // select ma
6327    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6328                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
6329                   deriv_z, is_ma_z);
6330    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
6331    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
6332 }
6333
6334 void prepare_cube_coords(isel_context *ctx, Temp* coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
6335 {
6336    Builder bld(ctx->program, ctx->block);
6337    Temp coord_args[4], ma, tc, sc, id;
6338    for (unsigned i = 0; i < (is_array ? 4 : 3); i++)
6339       coord_args[i] = emit_extract_vector(ctx, *coords, i, v1);
6340
6341    if (is_array) {
6342       coord_args[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_args[3]);
6343
6344       // see comment in ac_prepare_cube_coords()
6345       if (ctx->options->chip_class <= GFX8)
6346          coord_args[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coord_args[3]);
6347    }
6348
6349    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6350
6351    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
6352    vop3a->operands[0] = Operand(ma);
6353    vop3a->abs[0] = true;
6354    Temp invma = bld.tmp(v1);
6355    vop3a->definitions[0] = Definition(invma);
6356    ctx->block->instructions.emplace_back(std::move(vop3a));
6357
6358    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6359    if (!is_deriv)
6360       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
6361
6362    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6363    if (!is_deriv)
6364       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
6365
6366    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6367
6368    if (is_deriv) {
6369       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
6370       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
6371
6372       for (unsigned i = 0; i < 2; i++) {
6373          // see comment in ac_prepare_cube_coords()
6374          Temp deriv_ma;
6375          Temp deriv_sc, deriv_tc;
6376          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
6377                            &deriv_ma, &deriv_sc, &deriv_tc);
6378
6379          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
6380
6381          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6382                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
6383                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
6384          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6385                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
6386                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
6387          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
6388       }
6389
6390       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
6391       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
6392    }
6393
6394    if (is_array)
6395       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coord_args[3], id, Operand(0x41000000u/*8.0*/));
6396    *coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), sc, tc, id);
6397
6398 }
6399
6400 Temp apply_round_slice(isel_context *ctx, Temp coords, unsigned idx)
6401 {
6402    Temp coord_vec[3];
6403    for (unsigned i = 0; i < coords.size(); i++)
6404       coord_vec[i] = emit_extract_vector(ctx, coords, i, v1);
6405
6406    Builder bld(ctx->program, ctx->block);
6407    coord_vec[idx] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_vec[idx]);
6408
6409    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6410    for (unsigned i = 0; i < coords.size(); i++)
6411       vec->operands[i] = Operand(coord_vec[i]);
6412    Temp res = bld.tmp(RegType::vgpr, coords.size());
6413    vec->definitions[0] = Definition(res);
6414    ctx->block->instructions.emplace_back(std::move(vec));
6415    return res;
6416 }
6417
6418 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
6419 {
6420    if (vec->parent_instr->type != nir_instr_type_alu)
6421       return;
6422    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
6423    if (vec_instr->op != nir_op_vec(vec->num_components))
6424       return;
6425
6426    for (unsigned i = 0; i < vec->num_components; i++) {
6427       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
6428               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
6429    }
6430 }
6431
6432 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
6433 {
6434    Builder bld(ctx->program, ctx->block);
6435    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
6436         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
6437    Temp resource, sampler, fmask_ptr, bias = Temp(), coords, compare = Temp(), sample_index = Temp(),
6438         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp(), derivs = Temp();
6439    nir_const_value *sample_index_cv = NULL;
6440    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
6441    enum glsl_base_type stype;
6442    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
6443
6444    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
6445                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
6446    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
6447                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
6448
6449    for (unsigned i = 0; i < instr->num_srcs; i++) {
6450       switch (instr->src[i].src_type) {
6451       case nir_tex_src_coord:
6452          coords = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[i].src.ssa));
6453          break;
6454       case nir_tex_src_bias:
6455          if (instr->op == nir_texop_txb) {
6456             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
6457             has_bias = true;
6458          }
6459          break;
6460       case nir_tex_src_lod: {
6461          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
6462
6463          if (val && val->f32 <= 0.0) {
6464             level_zero = true;
6465          } else {
6466             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
6467             has_lod = true;
6468          }
6469          break;
6470       }
6471       case nir_tex_src_comparator:
6472          if (instr->is_shadow) {
6473             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
6474             has_compare = true;
6475          }
6476          break;
6477       case nir_tex_src_offset:
6478          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
6479          get_const_vec(instr->src[i].src.ssa, const_offset);
6480          has_offset = true;
6481          break;
6482       case nir_tex_src_ddx:
6483          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
6484          has_ddx = true;
6485          break;
6486       case nir_tex_src_ddy:
6487          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
6488          has_ddy = true;
6489          break;
6490       case nir_tex_src_ms_index:
6491          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
6492          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
6493          has_sample_index = true;
6494          break;
6495       case nir_tex_src_texture_offset:
6496       case nir_tex_src_sampler_offset:
6497       default:
6498          break;
6499       }
6500    }
6501 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6502    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
6503       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
6504
6505    if (instr->op == nir_texop_texture_samples) {
6506       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
6507
6508       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
6509       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
6510       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6511       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
6512
6513       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6514                samples, Operand(1u), bld.scc(is_msaa));
6515       return;
6516    }
6517
6518    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
6519       aco_ptr<Instruction> tmp_instr;
6520       Temp acc, pack = Temp();
6521
6522       uint32_t pack_const = 0;
6523       for (unsigned i = 0; i < offset.size(); i++) {
6524          if (!const_offset[i])
6525             continue;
6526          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
6527       }
6528
6529       if (offset.type() == RegType::sgpr) {
6530          for (unsigned i = 0; i < offset.size(); i++) {
6531             if (const_offset[i])
6532                continue;
6533
6534             acc = emit_extract_vector(ctx, offset, i, s1);
6535             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
6536
6537             if (i) {
6538                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
6539             }
6540
6541             if (pack == Temp()) {
6542                pack = acc;
6543             } else {
6544                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
6545             }
6546          }
6547
6548          if (pack_const && pack != Temp())
6549             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
6550       } else {
6551          for (unsigned i = 0; i < offset.size(); i++) {
6552             if (const_offset[i])
6553                continue;
6554
6555             acc = emit_extract_vector(ctx, offset, i, v1);
6556             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
6557
6558             if (i) {
6559                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
6560             }
6561
6562             if (pack == Temp()) {
6563                pack = acc;
6564             } else {
6565                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
6566             }
6567          }
6568
6569          if (pack_const && pack != Temp())
6570             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
6571       }
6572       if (pack_const && pack == Temp())
6573          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
6574       else if (pack == Temp())
6575          has_offset = false;
6576       else
6577          offset = pack;
6578    }
6579
6580    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
6581       prepare_cube_coords(ctx, &coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
6582
6583    /* pack derivatives */
6584    if (has_ddx || has_ddy) {
6585       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
6586          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(v4),
6587                              ddx, Operand(0u), ddy, Operand(0u));
6588       } else {
6589          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, ddx.size() + ddy.size()), ddx, ddy);
6590       }
6591       has_derivs = true;
6592    }
6593
6594    if (instr->coord_components > 1 &&
6595        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6596        instr->is_array &&
6597        instr->op != nir_texop_txf)
6598       coords = apply_round_slice(ctx, coords, 1);
6599
6600    if (instr->coord_components > 2 &&
6601       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
6602        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6603        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
6604        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6605        instr->is_array &&
6606        instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms)
6607       coords = apply_round_slice(ctx, coords, 2);
6608
6609    if (ctx->options->chip_class == GFX9 &&
6610        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6611        instr->op != nir_texop_lod && instr->coord_components) {
6612       assert(coords.size() > 0 && coords.size() < 3);
6613
6614       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size() + 1, 1)};
6615       vec->operands[0] = Operand(emit_extract_vector(ctx, coords, 0, v1));
6616       vec->operands[1] = instr->op == nir_texop_txf ? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6617       if (coords.size() > 1)
6618          vec->operands[2] = Operand(emit_extract_vector(ctx, coords, 1, v1));
6619       coords = bld.tmp(RegType::vgpr, coords.size() + 1);
6620       vec->definitions[0] = Definition(coords);
6621       ctx->block->instructions.emplace_back(std::move(vec));
6622    }
6623
6624    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
6625
6626    if (instr->op == nir_texop_samples_identical)
6627       resource = fmask_ptr;
6628
6629    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6630              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6631             instr->op != nir_texop_txs) {
6632       assert(has_sample_index);
6633       Operand op(sample_index);
6634       if (sample_index_cv)
6635          op = Operand(sample_index_cv->u32);
6636       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
6637    }
6638
6639    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
6640       Temp split_coords[coords.size()];
6641       emit_split_vector(ctx, coords, coords.size());
6642       for (unsigned i = 0; i < coords.size(); i++)
6643          split_coords[i] = emit_extract_vector(ctx, coords, i, v1);
6644
6645       unsigned i = 0;
6646       for (; i < std::min(offset.size(), instr->coord_components); i++) {
6647          Temp off = emit_extract_vector(ctx, offset, i, v1);
6648          split_coords[i] = bld.vadd32(bld.def(v1), split_coords[i], off);
6649       }
6650
6651       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6652       for (unsigned i = 0; i < coords.size(); i++)
6653          vec->operands[i] = Operand(split_coords[i]);
6654       coords = bld.tmp(coords.regClass());
6655       vec->definitions[0] = Definition(coords);
6656       ctx->block->instructions.emplace_back(std::move(vec));
6657
6658       has_offset = false;
6659    }
6660
6661    /* Build tex instruction */
6662    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
6663    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
6664                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
6665                   : 0;
6666    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6667    Temp tmp_dst = dst;
6668
6669    /* gather4 selects the component by dmask and always returns vec4 */
6670    if (instr->op == nir_texop_tg4) {
6671       assert(instr->dest.ssa.num_components == 4);
6672       if (instr->is_shadow)
6673          dmask = 1;
6674       else
6675          dmask = 1 << instr->component;
6676       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
6677          tmp_dst = bld.tmp(v4);
6678    } else if (instr->op == nir_texop_samples_identical) {
6679       tmp_dst = bld.tmp(v1);
6680    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
6681       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
6682    }
6683
6684    aco_ptr<MIMG_instruction> tex;
6685    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
6686       if (!has_lod)
6687          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6688
6689       bool div_by_6 = instr->op == nir_texop_txs &&
6690                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
6691                       instr->is_array &&
6692                       (dmask & (1 << 2));
6693       if (tmp_dst.id() == dst.id() && div_by_6)
6694          tmp_dst = bld.tmp(tmp_dst.regClass());
6695
6696       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6697       tex->operands[0] = Operand(as_vgpr(ctx,lod));
6698       tex->operands[1] = Operand(resource);
6699       if (ctx->options->chip_class == GFX9 &&
6700           instr->op == nir_texop_txs &&
6701           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6702           instr->is_array) {
6703          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
6704       } else if (instr->op == nir_texop_query_levels) {
6705          tex->dmask = 1 << 3;
6706       } else {
6707          tex->dmask = dmask;
6708       }
6709       tex->da = da;
6710       tex->definitions[0] = Definition(tmp_dst);
6711       tex->dim = dim;
6712       tex->can_reorder = true;
6713       ctx->block->instructions.emplace_back(std::move(tex));
6714
6715       if (div_by_6) {
6716          /* divide 3rd value by 6 by multiplying with magic number */
6717          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6718          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
6719          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
6720          assert(instr->dest.ssa.num_components == 3);
6721          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
6722          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6723                               emit_extract_vector(ctx, tmp_dst, 0, v1),
6724                               emit_extract_vector(ctx, tmp_dst, 1, v1),
6725                               by_6);
6726
6727       }
6728
6729       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6730       return;
6731    }
6732
6733    Temp tg4_compare_cube_wa64 = Temp();
6734
6735    if (tg4_integer_workarounds) {
6736       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6737       tex->operands[0] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6738       tex->operands[1] = Operand(resource);
6739       tex->dim = dim;
6740       tex->dmask = 0x3;
6741       tex->da = da;
6742       Temp size = bld.tmp(v2);
6743       tex->definitions[0] = Definition(size);
6744       tex->can_reorder = true;
6745       ctx->block->instructions.emplace_back(std::move(tex));
6746       emit_split_vector(ctx, size, size.size());
6747
6748       Temp half_texel[2];
6749       for (unsigned i = 0; i < 2; i++) {
6750          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
6751          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
6752          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
6753          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
6754       }
6755
6756       Temp orig_coords[2] = {
6757          emit_extract_vector(ctx, coords, 0, v1),
6758          emit_extract_vector(ctx, coords, 1, v1)};
6759       Temp new_coords[2] = {
6760          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[0], half_texel[0]),
6761          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[1], half_texel[1])
6762       };
6763
6764       if (tg4_integer_cube_workaround) {
6765          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6766          Temp desc[resource.size()];
6767          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
6768                                                                            Format::PSEUDO, 1, resource.size())};
6769          split->operands[0] = Operand(resource);
6770          for (unsigned i = 0; i < resource.size(); i++) {
6771             desc[i] = bld.tmp(s1);
6772             split->definitions[i] = Definition(desc[i]);
6773          }
6774          ctx->block->instructions.emplace_back(std::move(split));
6775
6776          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
6777          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
6778                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
6779
6780          Temp nfmt;
6781          if (stype == GLSL_TYPE_UINT) {
6782             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6783                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
6784                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
6785                             bld.scc(compare_cube_wa));
6786          } else {
6787             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6788                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
6789                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
6790                             bld.scc(compare_cube_wa));
6791          }
6792          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
6793          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
6794
6795          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
6796
6797          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
6798                             Operand((uint32_t)C_008F14_NUM_FORMAT));
6799          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
6800
6801          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6802                                                                          Format::PSEUDO, resource.size(), 1)};
6803          for (unsigned i = 0; i < resource.size(); i++)
6804             vec->operands[i] = Operand(desc[i]);
6805          resource = bld.tmp(resource.regClass());
6806          vec->definitions[0] = Definition(resource);
6807          ctx->block->instructions.emplace_back(std::move(vec));
6808
6809          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6810                                   new_coords[0], orig_coords[0], tg4_compare_cube_wa64);
6811          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6812                                   new_coords[1], orig_coords[1], tg4_compare_cube_wa64);
6813       }
6814
6815       if (coords.size() == 3) {
6816          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3),
6817                              new_coords[0], new_coords[1],
6818                              emit_extract_vector(ctx, coords, 2, v1));
6819       } else {
6820          assert(coords.size() == 2);
6821          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2),
6822                              new_coords[0], new_coords[1]);
6823       }
6824    }
6825
6826    std::vector<Operand> args;
6827    if (has_offset)
6828       args.emplace_back(Operand(offset));
6829    if (has_bias)
6830       args.emplace_back(Operand(bias));
6831    if (has_compare)
6832       args.emplace_back(Operand(compare));
6833    if (has_derivs)
6834       args.emplace_back(Operand(derivs));
6835    args.emplace_back(Operand(coords));
6836    if (has_sample_index)
6837       args.emplace_back(Operand(sample_index));
6838    if (has_lod)
6839       args.emplace_back(lod);
6840
6841    Temp arg;
6842    if (args.size() > 1) {
6843       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
6844       unsigned size = 0;
6845       for (unsigned i = 0; i < args.size(); i++) {
6846          size += args[i].size();
6847          vec->operands[i] = args[i];
6848       }
6849       RegClass rc = RegClass(RegType::vgpr, size);
6850       Temp tmp = bld.tmp(rc);
6851       vec->definitions[0] = Definition(tmp);
6852       ctx->block->instructions.emplace_back(std::move(vec));
6853       arg = tmp;
6854    } else {
6855       assert(args[0].isTemp());
6856       arg = as_vgpr(ctx, args[0].getTemp());
6857    }
6858
6859    /* we don't need the bias, sample index, compare value or offset to be
6860     * computed in WQM but if the p_create_vector copies the coordinates, then it
6861     * needs to be in WQM */
6862    if (!(has_ddx && has_ddy) && !has_lod && !level_zero &&
6863        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
6864        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
6865       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
6866
6867    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
6868       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6869
6870       assert(coords.size() == 1);
6871       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
6872       aco_opcode op;
6873       switch (last_bit) {
6874       case 1:
6875          op = aco_opcode::buffer_load_format_x; break;
6876       case 2:
6877          op = aco_opcode::buffer_load_format_xy; break;
6878       case 3:
6879          op = aco_opcode::buffer_load_format_xyz; break;
6880       case 4:
6881          op = aco_opcode::buffer_load_format_xyzw; break;
6882       default:
6883          unreachable("Tex instruction loads more than 4 components.");
6884       }
6885
6886       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6887       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
6888          tmp_dst = dst;
6889       else
6890          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
6891
6892       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
6893       mubuf->operands[0] = Operand(coords);
6894       mubuf->operands[1] = Operand(resource);
6895       mubuf->operands[2] = Operand((uint32_t) 0);
6896       mubuf->definitions[0] = Definition(tmp_dst);
6897       mubuf->idxen = true;
6898       mubuf->can_reorder = true;
6899       ctx->block->instructions.emplace_back(std::move(mubuf));
6900
6901       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
6902       return;
6903    }
6904
6905
6906    if (instr->op == nir_texop_txf ||
6907        instr->op == nir_texop_txf_ms ||
6908        instr->op == nir_texop_samples_identical) {
6909       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
6910       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 2, 1));
6911       tex->operands[0] = Operand(arg);
6912       tex->operands[1] = Operand(resource);
6913       tex->dim = dim;
6914       tex->dmask = dmask;
6915       tex->unrm = true;
6916       tex->da = da;
6917       tex->definitions[0] = Definition(tmp_dst);
6918       tex->can_reorder = true;
6919       ctx->block->instructions.emplace_back(std::move(tex));
6920
6921       if (instr->op == nir_texop_samples_identical) {
6922          assert(dmask == 1 && dst.regClass() == v1);
6923          assert(dst.id() != tmp_dst.id());
6924
6925          Temp tmp = bld.tmp(bld.lm);
6926          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
6927          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
6928
6929       } else {
6930          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6931       }
6932       return;
6933    }
6934
6935    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6936    aco_opcode opcode = aco_opcode::image_sample;
6937    if (has_offset) { /* image_sample_*_o */
6938       if (has_compare) {
6939          opcode = aco_opcode::image_sample_c_o;
6940          if (has_derivs)
6941             opcode = aco_opcode::image_sample_c_d_o;
6942          if (has_bias)
6943             opcode = aco_opcode::image_sample_c_b_o;
6944          if (level_zero)
6945             opcode = aco_opcode::image_sample_c_lz_o;
6946          if (has_lod)
6947             opcode = aco_opcode::image_sample_c_l_o;
6948       } else {
6949          opcode = aco_opcode::image_sample_o;
6950          if (has_derivs)
6951             opcode = aco_opcode::image_sample_d_o;
6952          if (has_bias)
6953             opcode = aco_opcode::image_sample_b_o;
6954          if (level_zero)
6955             opcode = aco_opcode::image_sample_lz_o;
6956          if (has_lod)
6957             opcode = aco_opcode::image_sample_l_o;
6958       }
6959    } else { /* no offset */
6960       if (has_compare) {
6961          opcode = aco_opcode::image_sample_c;
6962          if (has_derivs)
6963             opcode = aco_opcode::image_sample_c_d;
6964          if (has_bias)
6965             opcode = aco_opcode::image_sample_c_b;
6966          if (level_zero)
6967             opcode = aco_opcode::image_sample_c_lz;
6968          if (has_lod)
6969             opcode = aco_opcode::image_sample_c_l;
6970       } else {
6971          opcode = aco_opcode::image_sample;
6972          if (has_derivs)
6973             opcode = aco_opcode::image_sample_d;
6974          if (has_bias)
6975             opcode = aco_opcode::image_sample_b;
6976          if (level_zero)
6977             opcode = aco_opcode::image_sample_lz;
6978          if (has_lod)
6979             opcode = aco_opcode::image_sample_l;
6980       }
6981    }
6982
6983    if (instr->op == nir_texop_tg4) {
6984       if (has_offset) {
6985          opcode = aco_opcode::image_gather4_lz_o;
6986          if (has_compare)
6987             opcode = aco_opcode::image_gather4_c_lz_o;
6988       } else {
6989          opcode = aco_opcode::image_gather4_lz;
6990          if (has_compare)
6991             opcode = aco_opcode::image_gather4_c_lz;
6992       }
6993    } else if (instr->op == nir_texop_lod) {
6994       opcode = aco_opcode::image_get_lod;
6995    }
6996
6997    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
6998    tex->operands[0] = Operand(arg);
6999    tex->operands[1] = Operand(resource);
7000    tex->operands[2] = Operand(sampler);
7001    tex->dim = dim;
7002    tex->dmask = dmask;
7003    tex->da = da;
7004    tex->definitions[0] = Definition(tmp_dst);
7005    tex->can_reorder = true;
7006    ctx->block->instructions.emplace_back(std::move(tex));
7007
7008    if (tg4_integer_cube_workaround) {
7009       assert(tmp_dst.id() != dst.id());
7010       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7011
7012       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7013       Temp val[4];
7014       for (unsigned i = 0; i < dst.size(); i++) {
7015          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7016          Temp cvt_val;
7017          if (stype == GLSL_TYPE_UINT)
7018             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7019          else
7020             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7021          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7022       }
7023       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7024       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7025                            val[0], val[1], val[2], val[3]);
7026    }
7027    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7028    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7029
7030 }
7031
7032
7033 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7034 {
7035    Temp tmp = get_ssa_temp(ctx, ssa);
7036    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7037       return Operand(tmp.regClass());
7038    else
7039       return Operand(tmp);
7040 }
7041
7042 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7043 {
7044    aco_ptr<Pseudo_instruction> phi;
7045    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7046    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7047
7048    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7049    logical |= ctx->block->kind & block_kind_merge;
7050    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7051
7052    /* we want a sorted list of sources, since the predecessor list is also sorted */
7053    std::map<unsigned, nir_ssa_def*> phi_src;
7054    nir_foreach_phi_src(src, instr)
7055       phi_src[src->pred->index] = src->src.ssa;
7056
7057    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7058    unsigned num_operands = 0;
7059    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
7060    unsigned num_defined = 0;
7061    unsigned cur_pred_idx = 0;
7062    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
7063       if (cur_pred_idx < preds.size()) {
7064          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7065          unsigned block = ctx->cf_info.nir_to_aco[src.first];
7066          unsigned skipped = 0;
7067          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
7068             skipped++;
7069          if (cur_pred_idx + skipped < preds.size()) {
7070             for (unsigned i = 0; i < skipped; i++)
7071                operands[num_operands++] = Operand(dst.regClass());
7072             cur_pred_idx += skipped;
7073          } else {
7074             continue;
7075          }
7076       }
7077       cur_pred_idx++;
7078       Operand op = get_phi_operand(ctx, src.second);
7079       operands[num_operands++] = op;
7080       num_defined += !op.isUndefined();
7081    }
7082    /* handle block_kind_continue_or_break at loop exit blocks */
7083    while (cur_pred_idx++ < preds.size())
7084       operands[num_operands++] = Operand(dst.regClass());
7085
7086    if (num_defined == 0) {
7087       Builder bld(ctx->program, ctx->block);
7088       if (dst.regClass() == s1) {
7089          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
7090       } else if (dst.regClass() == v1) {
7091          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
7092       } else {
7093          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7094          for (unsigned i = 0; i < dst.size(); i++)
7095             vec->operands[i] = Operand(0u);
7096          vec->definitions[0] = Definition(dst);
7097          ctx->block->instructions.emplace_back(std::move(vec));
7098       }
7099       return;
7100    }
7101
7102    /* we can use a linear phi in some cases if one src is undef */
7103    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
7104       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
7105
7106       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
7107       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
7108       assert(invert->kind & block_kind_invert);
7109
7110       unsigned then_block = invert->linear_preds[0];
7111
7112       Block* insert_block = NULL;
7113       for (unsigned i = 0; i < num_operands; i++) {
7114          Operand op = operands[i];
7115          if (op.isUndefined())
7116             continue;
7117          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
7118          phi->operands[0] = op;
7119          break;
7120       }
7121       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
7122       phi->operands[1] = Operand(dst.regClass());
7123       phi->definitions[0] = Definition(dst);
7124       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
7125       return;
7126    }
7127
7128    /* try to scalarize vector phis */
7129    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
7130       // TODO: scalarize linear phis on divergent ifs
7131       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
7132       std::array<Temp, 4> new_vec;
7133       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
7134          Operand src = operands[i];
7135          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
7136             can_scalarize = false;
7137       }
7138       if (can_scalarize) {
7139          unsigned num_components = instr->dest.ssa.num_components;
7140          assert(dst.size() % num_components == 0);
7141          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
7142
7143          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
7144          for (unsigned k = 0; k < num_components; k++) {
7145             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7146             for (unsigned i = 0; i < num_operands; i++) {
7147                Operand src = operands[i];
7148                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
7149             }
7150             Temp phi_dst = {ctx->program->allocateId(), rc};
7151             phi->definitions[0] = Definition(phi_dst);
7152             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7153             new_vec[k] = phi_dst;
7154             vec->operands[k] = Operand(phi_dst);
7155          }
7156          vec->definitions[0] = Definition(dst);
7157          ctx->block->instructions.emplace_back(std::move(vec));
7158          ctx->allocated_vec.emplace(dst.id(), new_vec);
7159          return;
7160       }
7161    }
7162
7163    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7164    for (unsigned i = 0; i < num_operands; i++)
7165       phi->operands[i] = operands[i];
7166    phi->definitions[0] = Definition(dst);
7167    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7168 }
7169
7170
7171 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
7172 {
7173    Temp dst = get_ssa_temp(ctx, &instr->def);
7174
7175    assert(dst.type() == RegType::sgpr);
7176
7177    if (dst.size() == 1) {
7178       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
7179    } else {
7180       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7181       for (unsigned i = 0; i < dst.size(); i++)
7182          vec->operands[i] = Operand(0u);
7183       vec->definitions[0] = Definition(dst);
7184       ctx->block->instructions.emplace_back(std::move(vec));
7185    }
7186 }
7187
7188 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
7189 {
7190    Builder bld(ctx->program, ctx->block);
7191    Block *logical_target;
7192    append_logical_end(ctx->block);
7193    unsigned idx = ctx->block->index;
7194
7195    switch (instr->type) {
7196    case nir_jump_break:
7197       logical_target = ctx->cf_info.parent_loop.exit;
7198       add_logical_edge(idx, logical_target);
7199       ctx->block->kind |= block_kind_break;
7200
7201       if (!ctx->cf_info.parent_if.is_divergent &&
7202           !ctx->cf_info.parent_loop.has_divergent_continue) {
7203          /* uniform break - directly jump out of the loop */
7204          ctx->block->kind |= block_kind_uniform;
7205          ctx->cf_info.has_branch = true;
7206          bld.branch(aco_opcode::p_branch);
7207          add_linear_edge(idx, logical_target);
7208          return;
7209       }
7210       ctx->cf_info.parent_loop.has_divergent_branch = true;
7211       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7212       break;
7213    case nir_jump_continue:
7214       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7215       add_logical_edge(idx, logical_target);
7216       ctx->block->kind |= block_kind_continue;
7217
7218       if (ctx->cf_info.parent_if.is_divergent) {
7219          /* for potential uniform breaks after this continue,
7220             we must ensure that they are handled correctly */
7221          ctx->cf_info.parent_loop.has_divergent_continue = true;
7222          ctx->cf_info.parent_loop.has_divergent_branch = true;
7223          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7224       } else {
7225          /* uniform continue - directly jump to the loop header */
7226          ctx->block->kind |= block_kind_uniform;
7227          ctx->cf_info.has_branch = true;
7228          bld.branch(aco_opcode::p_branch);
7229          add_linear_edge(idx, logical_target);
7230          return;
7231       }
7232       break;
7233    default:
7234       fprintf(stderr, "Unknown NIR jump instr: ");
7235       nir_print_instr(&instr->instr, stderr);
7236       fprintf(stderr, "\n");
7237       abort();
7238    }
7239
7240    /* remove critical edges from linear CFG */
7241    bld.branch(aco_opcode::p_branch);
7242    Block* break_block = ctx->program->create_and_insert_block();
7243    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7244    break_block->kind |= block_kind_uniform;
7245    add_linear_edge(idx, break_block);
7246    /* the loop_header pointer might be invalidated by this point */
7247    if (instr->type == nir_jump_continue)
7248       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7249    add_linear_edge(break_block->index, logical_target);
7250    bld.reset(break_block);
7251    bld.branch(aco_opcode::p_branch);
7252
7253    Block* continue_block = ctx->program->create_and_insert_block();
7254    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7255    add_linear_edge(idx, continue_block);
7256    append_logical_start(continue_block);
7257    ctx->block = continue_block;
7258    return;
7259 }
7260
7261 void visit_block(isel_context *ctx, nir_block *block)
7262 {
7263    nir_foreach_instr(instr, block) {
7264       switch (instr->type) {
7265       case nir_instr_type_alu:
7266          visit_alu_instr(ctx, nir_instr_as_alu(instr));
7267          break;
7268       case nir_instr_type_load_const:
7269          visit_load_const(ctx, nir_instr_as_load_const(instr));
7270          break;
7271       case nir_instr_type_intrinsic:
7272          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
7273          break;
7274       case nir_instr_type_tex:
7275          visit_tex(ctx, nir_instr_as_tex(instr));
7276          break;
7277       case nir_instr_type_phi:
7278          visit_phi(ctx, nir_instr_as_phi(instr));
7279          break;
7280       case nir_instr_type_ssa_undef:
7281          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
7282          break;
7283       case nir_instr_type_deref:
7284          break;
7285       case nir_instr_type_jump:
7286          visit_jump(ctx, nir_instr_as_jump(instr));
7287          break;
7288       default:
7289          fprintf(stderr, "Unknown NIR instr type: ");
7290          nir_print_instr(instr, stderr);
7291          fprintf(stderr, "\n");
7292          //abort();
7293       }
7294    }
7295
7296    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7297       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
7298 }
7299
7300
7301
7302 static void visit_loop(isel_context *ctx, nir_loop *loop)
7303 {
7304    append_logical_end(ctx->block);
7305    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7306    Builder bld(ctx->program, ctx->block);
7307    bld.branch(aco_opcode::p_branch);
7308    unsigned loop_preheader_idx = ctx->block->index;
7309
7310    Block loop_exit = Block();
7311    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7312    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
7313
7314    Block* loop_header = ctx->program->create_and_insert_block();
7315    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
7316    loop_header->kind |= block_kind_loop_header;
7317    add_edge(loop_preheader_idx, loop_header);
7318    ctx->block = loop_header;
7319
7320    /* emit loop body */
7321    unsigned loop_header_idx = loop_header->index;
7322    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
7323    append_logical_start(ctx->block);
7324    visit_cf_list(ctx, &loop->body);
7325
7326    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7327    if (!ctx->cf_info.has_branch) {
7328       append_logical_end(ctx->block);
7329       if (ctx->cf_info.exec_potentially_empty) {
7330          /* Discards can result in code running with an empty exec mask.
7331           * This would result in divergent breaks not ever being taken. As a
7332           * workaround, break the loop when the loop mask is empty instead of
7333           * always continuing. */
7334          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
7335          unsigned block_idx = ctx->block->index;
7336
7337          /* create helper blocks to avoid critical edges */
7338          Block *break_block = ctx->program->create_and_insert_block();
7339          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7340          break_block->kind = block_kind_uniform;
7341          bld.reset(break_block);
7342          bld.branch(aco_opcode::p_branch);
7343          add_linear_edge(block_idx, break_block);
7344          add_linear_edge(break_block->index, &loop_exit);
7345
7346          Block *continue_block = ctx->program->create_and_insert_block();
7347          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7348          continue_block->kind = block_kind_uniform;
7349          bld.reset(continue_block);
7350          bld.branch(aco_opcode::p_branch);
7351          add_linear_edge(block_idx, continue_block);
7352          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
7353
7354          add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
7355          ctx->block = &ctx->program->blocks[block_idx];
7356       } else {
7357          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
7358          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7359             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7360          else
7361             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7362       }
7363
7364       bld.reset(ctx->block);
7365       bld.branch(aco_opcode::p_branch);
7366    }
7367
7368    /* fixup phis in loop header from unreachable blocks */
7369    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
7370       bool linear = ctx->cf_info.has_branch;
7371       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
7372       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
7373          if ((logical && instr->opcode == aco_opcode::p_phi) ||
7374              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
7375             /* the last operand should be the one that needs to be removed */
7376             instr->operands.pop_back();
7377          } else if (!is_phi(instr)) {
7378             break;
7379          }
7380       }
7381    }
7382
7383    ctx->cf_info.has_branch = false;
7384
7385    // TODO: if the loop has not a single exit, we must add one °°
7386    /* emit loop successor block */
7387    ctx->block = ctx->program->insert_block(std::move(loop_exit));
7388    append_logical_start(ctx->block);
7389
7390    #if 0
7391    // TODO: check if it is beneficial to not branch on continues
7392    /* trim linear phis in loop header */
7393    for (auto&& instr : loop_entry->instructions) {
7394       if (instr->opcode == aco_opcode::p_linear_phi) {
7395          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
7396          new_phi->definitions[0] = instr->definitions[0];
7397          for (unsigned i = 0; i < new_phi->operands.size(); i++)
7398             new_phi->operands[i] = instr->operands[i];
7399          /* check that the remaining operands are all the same */
7400          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
7401             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
7402          instr.swap(new_phi);
7403       } else if (instr->opcode == aco_opcode::p_phi) {
7404          continue;
7405       } else {
7406          break;
7407       }
7408    }
7409    #endif
7410 }
7411
7412 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
7413 {
7414    ic->cond = cond;
7415
7416    append_logical_end(ctx->block);
7417    ctx->block->kind |= block_kind_branch;
7418
7419    /* branch to linear then block */
7420    assert(cond.regClass() == ctx->program->lane_mask);
7421    aco_ptr<Pseudo_branch_instruction> branch;
7422    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7423    branch->operands[0] = Operand(cond);
7424    ctx->block->instructions.push_back(std::move(branch));
7425
7426    ic->BB_if_idx = ctx->block->index;
7427    ic->BB_invert = Block();
7428    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7429    /* Invert blocks are intentionally not marked as top level because they
7430     * are not part of the logical cfg. */
7431    ic->BB_invert.kind |= block_kind_invert;
7432    ic->BB_endif = Block();
7433    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7434    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
7435
7436    ic->exec_potentially_empty_old = ctx->cf_info.exec_potentially_empty;
7437    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
7438    ctx->cf_info.parent_if.is_divergent = true;
7439    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7440
7441    /** emit logical then block */
7442    Block* BB_then_logical = ctx->program->create_and_insert_block();
7443    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7444    add_edge(ic->BB_if_idx, BB_then_logical);
7445    ctx->block = BB_then_logical;
7446    append_logical_start(BB_then_logical);
7447 }
7448
7449 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
7450 {
7451    Block *BB_then_logical = ctx->block;
7452    append_logical_end(BB_then_logical);
7453     /* branch from logical then block to invert block */
7454    aco_ptr<Pseudo_branch_instruction> branch;
7455    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7456    BB_then_logical->instructions.emplace_back(std::move(branch));
7457    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
7458    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7459       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
7460    BB_then_logical->kind |= block_kind_uniform;
7461    assert(!ctx->cf_info.has_branch);
7462    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7463    ctx->cf_info.parent_loop.has_divergent_branch = false;
7464
7465    /** emit linear then block */
7466    Block* BB_then_linear = ctx->program->create_and_insert_block();
7467    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7468    BB_then_linear->kind |= block_kind_uniform;
7469    add_linear_edge(ic->BB_if_idx, BB_then_linear);
7470    /* branch from linear then block to invert block */
7471    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7472    BB_then_linear->instructions.emplace_back(std::move(branch));
7473    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
7474
7475    /** emit invert merge block */
7476    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
7477    ic->invert_idx = ctx->block->index;
7478
7479    /* branch to linear else block (skip else) */
7480    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
7481    branch->operands[0] = Operand(ic->cond);
7482    ctx->block->instructions.push_back(std::move(branch));
7483
7484    ic->exec_potentially_empty_old |= ctx->cf_info.exec_potentially_empty;
7485    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7486
7487    /** emit logical else block */
7488    Block* BB_else_logical = ctx->program->create_and_insert_block();
7489    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7490    add_logical_edge(ic->BB_if_idx, BB_else_logical);
7491    add_linear_edge(ic->invert_idx, BB_else_logical);
7492    ctx->block = BB_else_logical;
7493    append_logical_start(BB_else_logical);
7494 }
7495
7496 static void end_divergent_if(isel_context *ctx, if_context *ic)
7497 {
7498    Block *BB_else_logical = ctx->block;
7499    append_logical_end(BB_else_logical);
7500
7501    /* branch from logical else block to endif block */
7502    aco_ptr<Pseudo_branch_instruction> branch;
7503    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7504    BB_else_logical->instructions.emplace_back(std::move(branch));
7505    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
7506    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7507       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
7508    BB_else_logical->kind |= block_kind_uniform;
7509
7510    assert(!ctx->cf_info.has_branch);
7511    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
7512
7513
7514    /** emit linear else block */
7515    Block* BB_else_linear = ctx->program->create_and_insert_block();
7516    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7517    BB_else_linear->kind |= block_kind_uniform;
7518    add_linear_edge(ic->invert_idx, BB_else_linear);
7519
7520    /* branch from linear else block to endif block */
7521    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7522    BB_else_linear->instructions.emplace_back(std::move(branch));
7523    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
7524
7525
7526    /** emit endif merge block */
7527    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
7528    append_logical_start(ctx->block);
7529
7530
7531    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
7532    ctx->cf_info.exec_potentially_empty |= ic->exec_potentially_empty_old;
7533    /* uniform control flow never has an empty exec-mask */
7534    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
7535       ctx->cf_info.exec_potentially_empty = false;
7536 }
7537
7538 static void visit_if(isel_context *ctx, nir_if *if_stmt)
7539 {
7540    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
7541    Builder bld(ctx->program, ctx->block);
7542    aco_ptr<Pseudo_branch_instruction> branch;
7543
7544    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
7545       /**
7546        * Uniform conditionals are represented in the following way*) :
7547        *
7548        * The linear and logical CFG:
7549        *                        BB_IF
7550        *                        /    \
7551        *       BB_THEN (logical)      BB_ELSE (logical)
7552        *                        \    /
7553        *                        BB_ENDIF
7554        *
7555        * *) Exceptions may be due to break and continue statements within loops
7556        *    If a break/continue happens within uniform control flow, it branches
7557        *    to the loop exit/entry block. Otherwise, it branches to the next
7558        *    merge block.
7559        **/
7560       append_logical_end(ctx->block);
7561       ctx->block->kind |= block_kind_uniform;
7562
7563       /* emit branch */
7564       assert(cond.regClass() == bld.lm);
7565       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7566       cond = bool_to_scalar_condition(ctx, cond);
7567
7568       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7569       branch->operands[0] = Operand(cond);
7570       branch->operands[0].setFixed(scc);
7571       ctx->block->instructions.emplace_back(std::move(branch));
7572
7573       unsigned BB_if_idx = ctx->block->index;
7574       Block BB_endif = Block();
7575       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7576       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
7577
7578       /** emit then block */
7579       Block* BB_then = ctx->program->create_and_insert_block();
7580       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7581       add_edge(BB_if_idx, BB_then);
7582       append_logical_start(BB_then);
7583       ctx->block = BB_then;
7584       visit_cf_list(ctx, &if_stmt->then_list);
7585       BB_then = ctx->block;
7586       bool then_branch = ctx->cf_info.has_branch;
7587       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7588
7589       if (!then_branch) {
7590          append_logical_end(BB_then);
7591          /* branch from then block to endif block */
7592          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7593          BB_then->instructions.emplace_back(std::move(branch));
7594          add_linear_edge(BB_then->index, &BB_endif);
7595          if (!then_branch_divergent)
7596             add_logical_edge(BB_then->index, &BB_endif);
7597          BB_then->kind |= block_kind_uniform;
7598       }
7599
7600       ctx->cf_info.has_branch = false;
7601       ctx->cf_info.parent_loop.has_divergent_branch = false;
7602
7603       /** emit else block */
7604       Block* BB_else = ctx->program->create_and_insert_block();
7605       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7606       add_edge(BB_if_idx, BB_else);
7607       append_logical_start(BB_else);
7608       ctx->block = BB_else;
7609       visit_cf_list(ctx, &if_stmt->else_list);
7610       BB_else = ctx->block;
7611
7612       if (!ctx->cf_info.has_branch) {
7613          append_logical_end(BB_else);
7614          /* branch from then block to endif block */
7615          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7616          BB_else->instructions.emplace_back(std::move(branch));
7617          add_linear_edge(BB_else->index, &BB_endif);
7618          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7619             add_logical_edge(BB_else->index, &BB_endif);
7620          BB_else->kind |= block_kind_uniform;
7621       }
7622
7623       ctx->cf_info.has_branch &= then_branch;
7624       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
7625
7626       /** emit endif merge block */
7627       if (!ctx->cf_info.has_branch) {
7628          ctx->block = ctx->program->insert_block(std::move(BB_endif));
7629          append_logical_start(ctx->block);
7630       }
7631    } else { /* non-uniform condition */
7632       /**
7633        * To maintain a logical and linear CFG without critical edges,
7634        * non-uniform conditionals are represented in the following way*) :
7635        *
7636        * The linear CFG:
7637        *                        BB_IF
7638        *                        /    \
7639        *       BB_THEN (logical)      BB_THEN (linear)
7640        *                        \    /
7641        *                        BB_INVERT (linear)
7642        *                        /    \
7643        *       BB_ELSE (logical)      BB_ELSE (linear)
7644        *                        \    /
7645        *                        BB_ENDIF
7646        *
7647        * The logical CFG:
7648        *                        BB_IF
7649        *                        /    \
7650        *       BB_THEN (logical)      BB_ELSE (logical)
7651        *                        \    /
7652        *                        BB_ENDIF
7653        *
7654        * *) Exceptions may be due to break and continue statements within loops
7655        **/
7656
7657       if_context ic;
7658
7659       begin_divergent_if_then(ctx, &ic, cond);
7660       visit_cf_list(ctx, &if_stmt->then_list);
7661
7662       begin_divergent_if_else(ctx, &ic);
7663       visit_cf_list(ctx, &if_stmt->else_list);
7664
7665       end_divergent_if(ctx, &ic);
7666    }
7667 }
7668
7669 static void visit_cf_list(isel_context *ctx,
7670                           struct exec_list *list)
7671 {
7672    foreach_list_typed(nir_cf_node, node, node, list) {
7673       switch (node->type) {
7674       case nir_cf_node_block:
7675          visit_block(ctx, nir_cf_node_as_block(node));
7676          break;
7677       case nir_cf_node_if:
7678          visit_if(ctx, nir_cf_node_as_if(node));
7679          break;
7680       case nir_cf_node_loop:
7681          visit_loop(ctx, nir_cf_node_as_loop(node));
7682          break;
7683       default:
7684          unreachable("unimplemented cf list type");
7685       }
7686    }
7687 }
7688
7689 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
7690 {
7691    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
7692    uint64_t mask = ctx->vs_output.mask[slot];
7693    if (!is_pos && !mask)
7694       return;
7695    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
7696       return;
7697    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7698    exp->enabled_mask = mask;
7699    for (unsigned i = 0; i < 4; ++i) {
7700       if (mask & (1 << i))
7701          exp->operands[i] = Operand(ctx->vs_output.outputs[slot][i]);
7702       else
7703          exp->operands[i] = Operand(v1);
7704    }
7705    exp->valid_mask = false;
7706    exp->done = false;
7707    exp->compressed = false;
7708    if (is_pos)
7709       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7710    else
7711       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
7712    ctx->block->instructions.emplace_back(std::move(exp));
7713 }
7714
7715 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
7716 {
7717    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7718    exp->enabled_mask = 0;
7719    for (unsigned i = 0; i < 4; ++i)
7720       exp->operands[i] = Operand(v1);
7721    if (ctx->vs_output.mask[VARYING_SLOT_PSIZ]) {
7722       exp->operands[0] = Operand(ctx->vs_output.outputs[VARYING_SLOT_PSIZ][0]);
7723       exp->enabled_mask |= 0x1;
7724    }
7725    if (ctx->vs_output.mask[VARYING_SLOT_LAYER]) {
7726       exp->operands[2] = Operand(ctx->vs_output.outputs[VARYING_SLOT_LAYER][0]);
7727       exp->enabled_mask |= 0x4;
7728    }
7729    if (ctx->vs_output.mask[VARYING_SLOT_VIEWPORT]) {
7730       if (ctx->options->chip_class < GFX9) {
7731          exp->operands[3] = Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]);
7732          exp->enabled_mask |= 0x8;
7733       } else {
7734          Builder bld(ctx->program, ctx->block);
7735
7736          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
7737                              Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]));
7738          if (exp->operands[2].isTemp())
7739             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
7740
7741          exp->operands[2] = Operand(out);
7742          exp->enabled_mask |= 0x4;
7743       }
7744    }
7745    exp->valid_mask = false;
7746    exp->done = false;
7747    exp->compressed = false;
7748    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7749    ctx->block->instructions.emplace_back(std::move(exp));
7750 }
7751
7752 static void create_vs_exports(isel_context *ctx)
7753 {
7754    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
7755
7756    if (outinfo->export_prim_id) {
7757       ctx->vs_output.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
7758       ctx->vs_output.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
7759    }
7760
7761    if (ctx->options->key.has_multiview_view_index) {
7762       ctx->vs_output.mask[VARYING_SLOT_LAYER] |= 0x1;
7763       ctx->vs_output.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
7764    }
7765
7766    /* the order these position exports are created is important */
7767    int next_pos = 0;
7768    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
7769    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
7770       export_vs_psiz_layer_viewport(ctx, &next_pos);
7771    }
7772    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7773       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
7774    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7775       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
7776
7777    if (ctx->options->key.vs_common_out.export_clip_dists) {
7778       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7779          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
7780       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7781          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
7782    }
7783
7784    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
7785       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
7786           i != VARYING_SLOT_PRIMITIVE_ID)
7787          continue;
7788
7789       export_vs_varying(ctx, i, false, NULL);
7790    }
7791 }
7792
7793 static void emit_stream_output(isel_context *ctx,
7794                                Temp const *so_buffers,
7795                                Temp const *so_write_offset,
7796                                const struct radv_stream_output *output)
7797 {
7798    unsigned num_comps = util_bitcount(output->component_mask);
7799    unsigned loc = output->location;
7800    unsigned buf = output->buffer;
7801    unsigned offset = output->offset;
7802
7803    assert(num_comps && num_comps <= 4);
7804    if (!num_comps || num_comps > 4)
7805       return;
7806
7807    unsigned start = ffs(output->component_mask) - 1;
7808
7809    Temp out[4];
7810    bool all_undef = true;
7811    assert(ctx->stage == vertex_vs);
7812    for (unsigned i = 0; i < num_comps; i++) {
7813       out[i] = ctx->vs_output.outputs[loc][start + i];
7814       all_undef = all_undef && !out[i].id();
7815    }
7816    if (all_undef)
7817       return;
7818
7819    Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_comps)};
7820    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_comps, 1)};
7821    for (unsigned i = 0; i < num_comps; ++i)
7822       vec->operands[i] = (ctx->vs_output.mask[loc] & 1 << i) ? Operand(out[i]) : Operand(0u);
7823    vec->definitions[0] = Definition(write_data);
7824    ctx->block->instructions.emplace_back(std::move(vec));
7825
7826    aco_opcode opcode;
7827    switch (num_comps) {
7828    case 1:
7829       opcode = aco_opcode::buffer_store_dword;
7830       break;
7831    case 2:
7832       opcode = aco_opcode::buffer_store_dwordx2;
7833       break;
7834    case 3:
7835       opcode = aco_opcode::buffer_store_dwordx3;
7836       break;
7837    case 4:
7838       opcode = aco_opcode::buffer_store_dwordx4;
7839       break;
7840    }
7841
7842    aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
7843    store->operands[0] = Operand(so_write_offset[buf]);
7844    store->operands[1] = Operand(so_buffers[buf]);
7845    store->operands[2] = Operand((uint32_t) 0);
7846    store->operands[3] = Operand(write_data);
7847    if (offset > 4095) {
7848       /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7849       Builder bld(ctx->program, ctx->block);
7850       store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
7851    } else {
7852       store->offset = offset;
7853    }
7854    store->offen = true;
7855    store->glc = true;
7856    store->dlc = false;
7857    store->slc = true;
7858    store->can_reorder = true;
7859    ctx->block->instructions.emplace_back(std::move(store));
7860 }
7861
7862 static void emit_streamout(isel_context *ctx, unsigned stream)
7863 {
7864    Builder bld(ctx->program, ctx->block);
7865
7866    Temp so_buffers[4];
7867    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
7868    for (unsigned i = 0; i < 4; i++) {
7869       unsigned stride = ctx->program->info->so.strides[i];
7870       if (!stride)
7871          continue;
7872
7873       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, Operand(i * 16u));
7874    }
7875
7876    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
7877                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
7878
7879    Temp tid = emit_mbcnt(ctx, bld.def(v1));
7880
7881    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(s2), so_vtx_count, tid);
7882
7883    if_context ic;
7884    begin_divergent_if_then(ctx, &ic, can_emit);
7885
7886    bld.reset(ctx->block);
7887
7888    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
7889
7890    Temp so_write_offset[4];
7891
7892    for (unsigned i = 0; i < 4; i++) {
7893       unsigned stride = ctx->program->info->so.strides[i];
7894       if (!stride)
7895          continue;
7896
7897       if (stride == 1) {
7898          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
7899                                 get_arg(ctx, ctx->args->streamout_write_idx),
7900                                 get_arg(ctx, ctx->args->streamout_offset[i]));
7901          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
7902
7903          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
7904       } else {
7905          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
7906          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
7907                                  get_arg(ctx, ctx->args->streamout_offset[i]));
7908          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
7909       }
7910    }
7911
7912    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
7913       struct radv_stream_output *output =
7914          &ctx->program->info->so.outputs[i];
7915       if (stream != output->stream)
7916          continue;
7917
7918       emit_stream_output(ctx, so_buffers, so_write_offset, output);
7919    }
7920
7921    begin_divergent_if_else(ctx, &ic);
7922    end_divergent_if(ctx, &ic);
7923 }
7924
7925 } /* end namespace */
7926
7927 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
7928 {
7929    /* Split all arguments except for the first (ring_offsets) and the last
7930     * (exec) so that the dead channels don't stay live throughout the program.
7931     */
7932    for (unsigned i = 1; i < startpgm->definitions.size() - 1; i++) {
7933       if (startpgm->definitions[i].regClass().size() > 1) {
7934          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
7935                            startpgm->definitions[i].regClass().size());
7936       }
7937    }
7938 }
7939
7940 void handle_bc_optimize(isel_context *ctx)
7941 {
7942    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7943    Builder bld(ctx->program, ctx->block);
7944    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
7945    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
7946    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
7947    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
7948    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
7949    if (uses_center && uses_centroid) {
7950       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
7951                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
7952
7953       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
7954          Temp new_coord[2];
7955          for (unsigned i = 0; i < 2; i++) {
7956             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
7957             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
7958             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7959                                     persp_centroid, persp_center, sel);
7960          }
7961          ctx->persp_centroid = bld.tmp(v2);
7962          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
7963                     Operand(new_coord[0]), Operand(new_coord[1]));
7964          emit_split_vector(ctx, ctx->persp_centroid, 2);
7965       }
7966
7967       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
7968          Temp new_coord[2];
7969          for (unsigned i = 0; i < 2; i++) {
7970             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
7971             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
7972             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7973                                     linear_centroid, linear_center, sel);
7974          }
7975          ctx->linear_centroid = bld.tmp(v2);
7976          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
7977                     Operand(new_coord[0]), Operand(new_coord[1]));
7978          emit_split_vector(ctx, ctx->linear_centroid, 2);
7979       }
7980    }
7981 }
7982
7983 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
7984 {
7985    Program *program = ctx->program;
7986
7987    unsigned float_controls = shader->info.float_controls_execution_mode;
7988
7989    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
7990       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
7991    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
7992       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
7993                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
7994
7995    program->next_fp_mode.must_flush_denorms32 =
7996       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
7997    program->next_fp_mode.must_flush_denorms16_64 =
7998       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
7999                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
8000
8001    program->next_fp_mode.care_about_round32 =
8002       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
8003
8004    program->next_fp_mode.care_about_round16_64 =
8005       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
8006                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
8007
8008    /* default to preserving fp16 and fp64 denorms, since it's free */
8009    if (program->next_fp_mode.must_flush_denorms16_64)
8010       program->next_fp_mode.denorm16_64 = 0;
8011    else
8012       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
8013
8014    /* preserving fp32 denorms is expensive, so only do it if asked */
8015    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
8016       program->next_fp_mode.denorm32 = fp_denorm_keep;
8017    else
8018       program->next_fp_mode.denorm32 = 0;
8019
8020    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
8021       program->next_fp_mode.round32 = fp_round_tz;
8022    else
8023       program->next_fp_mode.round32 = fp_round_ne;
8024
8025    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
8026       program->next_fp_mode.round16_64 = fp_round_tz;
8027    else
8028       program->next_fp_mode.round16_64 = fp_round_ne;
8029
8030    ctx->block->fp_mode = program->next_fp_mode;
8031 }
8032
8033 void select_program(Program *program,
8034                     unsigned shader_count,
8035                     struct nir_shader *const *shaders,
8036                     ac_shader_config* config,
8037                     struct radv_shader_args *args)
8038 {
8039    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args);
8040
8041    for (unsigned i = 0; i < shader_count; i++) {
8042       nir_shader *nir = shaders[i];
8043       init_context(&ctx, nir);
8044
8045       setup_fp_mode(&ctx, nir);
8046
8047       if (!i) {
8048          /* needs to be after init_context() for FS */
8049          Pseudo_instruction *startpgm = add_startpgm(&ctx);
8050          append_logical_start(ctx.block);
8051          split_arguments(&ctx, startpgm);
8052       }
8053
8054       if_context ic;
8055       if (shader_count >= 2) {
8056          Builder bld(ctx.program, ctx.block);
8057          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), ctx.merged_wave_info, Operand((8u << 16) | (i * 8u)));
8058          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
8059          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
8060
8061          begin_divergent_if_then(&ctx, &ic, cond);
8062       }
8063
8064       if (i) {
8065          Builder bld(ctx.program, ctx.block);
8066          bld.barrier(aco_opcode::p_memory_barrier_shared); //TODO: different barriers are needed for different stages
8067          bld.sopp(aco_opcode::s_barrier);
8068       }
8069
8070       if (ctx.stage == fragment_fs)
8071          handle_bc_optimize(&ctx);
8072
8073       nir_function_impl *func = nir_shader_get_entrypoint(nir);
8074       visit_cf_list(&ctx, &func->body);
8075
8076       if (ctx.program->info->so.num_outputs/*&& !ctx->is_gs_copy_shader */)
8077          emit_streamout(&ctx, 0);
8078
8079       if (ctx.stage == vertex_vs)
8080          create_vs_exports(&ctx);
8081
8082       if (shader_count >= 2) {
8083          begin_divergent_if_else(&ctx, &ic);
8084          end_divergent_if(&ctx, &ic);
8085       }
8086
8087       ralloc_free(ctx.divergent_vals);
8088    }
8089
8090    program->config->float_mode = program->blocks[0].fp_mode.val;
8091
8092    append_logical_end(ctx.block);
8093    ctx.block->kind |= block_kind_uniform;
8094    Builder bld(ctx.program, ctx.block);
8095    if (ctx.program->wb_smem_l1_on_end)
8096       bld.smem(aco_opcode::s_dcache_wb, false);
8097    bld.sopp(aco_opcode::s_endpgm);
8098
8099    /* cleanup CFG */
8100    for (Block& BB : program->blocks) {
8101       for (unsigned idx : BB.linear_preds)
8102          program->blocks[idx].linear_succs.emplace_back(BB.index);
8103       for (unsigned idx : BB.logical_preds)
8104          program->blocks[idx].logical_succs.emplace_back(BB.index);
8105    }
8106 }
8107 }