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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
594 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
595 if (src1
.type() == RegType::sgpr
) {
596 if (commutative
&& src0
.type() == RegType::vgpr
) {
601 src1
= as_vgpr(ctx
, src1
);
605 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
606 assert(dst
.size() == 1);
607 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
608 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
610 bld
.vop2(op
, Definition(dst
), src0
, src1
);
614 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
615 bool flush_denorms
= false)
617 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
618 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
619 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
621 /* ensure that the instruction has at most 1 sgpr operand
622 * The optimizer will inline constants for us */
623 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
624 src0
= as_vgpr(ctx
, src0
);
625 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
626 src1
= as_vgpr(ctx
, src1
);
627 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
628 src2
= as_vgpr(ctx
, src2
);
630 Builder
bld(ctx
->program
, ctx
->block
);
631 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
632 assert(dst
.size() == 1);
633 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
634 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
636 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
640 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
642 Builder
bld(ctx
->program
, ctx
->block
);
643 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
646 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
648 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
649 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
650 assert(src0
.size() == src1
.size());
652 aco_ptr
<Instruction
> vopc
;
653 if (src1
.type() == RegType::sgpr
) {
654 if (src0
.type() == RegType::vgpr
) {
655 /* to swap the operands, we might also have to change the opcode */
657 case aco_opcode::v_cmp_lt_f16
:
658 op
= aco_opcode::v_cmp_gt_f16
;
660 case aco_opcode::v_cmp_ge_f16
:
661 op
= aco_opcode::v_cmp_le_f16
;
663 case aco_opcode::v_cmp_lt_i16
:
664 op
= aco_opcode::v_cmp_gt_i16
;
666 case aco_opcode::v_cmp_ge_i16
:
667 op
= aco_opcode::v_cmp_le_i16
;
669 case aco_opcode::v_cmp_lt_u16
:
670 op
= aco_opcode::v_cmp_gt_u16
;
672 case aco_opcode::v_cmp_ge_u16
:
673 op
= aco_opcode::v_cmp_le_u16
;
675 case aco_opcode::v_cmp_lt_f32
:
676 op
= aco_opcode::v_cmp_gt_f32
;
678 case aco_opcode::v_cmp_ge_f32
:
679 op
= aco_opcode::v_cmp_le_f32
;
681 case aco_opcode::v_cmp_lt_i32
:
682 op
= aco_opcode::v_cmp_gt_i32
;
684 case aco_opcode::v_cmp_ge_i32
:
685 op
= aco_opcode::v_cmp_le_i32
;
687 case aco_opcode::v_cmp_lt_u32
:
688 op
= aco_opcode::v_cmp_gt_u32
;
690 case aco_opcode::v_cmp_ge_u32
:
691 op
= aco_opcode::v_cmp_le_u32
;
693 case aco_opcode::v_cmp_lt_f64
:
694 op
= aco_opcode::v_cmp_gt_f64
;
696 case aco_opcode::v_cmp_ge_f64
:
697 op
= aco_opcode::v_cmp_le_f64
;
699 case aco_opcode::v_cmp_lt_i64
:
700 op
= aco_opcode::v_cmp_gt_i64
;
702 case aco_opcode::v_cmp_ge_i64
:
703 op
= aco_opcode::v_cmp_le_i64
;
705 case aco_opcode::v_cmp_lt_u64
:
706 op
= aco_opcode::v_cmp_gt_u64
;
708 case aco_opcode::v_cmp_ge_u64
:
709 op
= aco_opcode::v_cmp_le_u64
;
711 default: /* eq and ne are commutative */
718 src1
= as_vgpr(ctx
, src1
);
722 Builder
bld(ctx
->program
, ctx
->block
);
723 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
726 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
728 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
729 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
730 Builder
bld(ctx
->program
, ctx
->block
);
732 assert(dst
.regClass() == bld
.lm
);
733 assert(src0
.type() == RegType::sgpr
);
734 assert(src1
.type() == RegType::sgpr
);
735 assert(src0
.regClass() == src1
.regClass());
737 /* Emit the SALU comparison instruction */
738 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
739 /* Turn the result into a per-lane bool */
740 bool_to_vector_condition(ctx
, cmp
, dst
);
743 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
744 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
746 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
747 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
748 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
749 nir_dest_is_divergent(instr
->dest
.dest
) ||
750 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
751 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
752 aco_opcode op
= use_valu
? v_op
: s_op
;
753 assert(op
!= aco_opcode::num_opcodes
);
754 assert(dst
.regClass() == ctx
->program
->lane_mask
);
757 emit_vopc_instruction(ctx
, instr
, op
, dst
);
759 emit_sopc_instruction(ctx
, instr
, op
, dst
);
762 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
764 Builder
bld(ctx
->program
, ctx
->block
);
765 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
766 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
768 assert(dst
.regClass() == bld
.lm
);
769 assert(src0
.regClass() == bld
.lm
);
770 assert(src1
.regClass() == bld
.lm
);
772 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
775 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
777 Builder
bld(ctx
->program
, ctx
->block
);
778 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
779 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
780 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
782 assert(cond
.regClass() == bld
.lm
);
784 if (dst
.type() == RegType::vgpr
) {
785 aco_ptr
<Instruction
> bcsel
;
786 if (dst
.size() == 1) {
787 then
= as_vgpr(ctx
, then
);
788 els
= as_vgpr(ctx
, els
);
790 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
791 } else if (dst
.size() == 2) {
792 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
793 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
794 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
797 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
798 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
800 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
802 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
803 nir_print_instr(&instr
->instr
, stderr
);
804 fprintf(stderr
, "\n");
809 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
810 assert(dst
.regClass() == bld
.lm
);
811 assert(then
.regClass() == bld
.lm
);
812 assert(els
.regClass() == bld
.lm
);
815 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
816 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
817 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
818 assert(dst
.size() == then
.size());
819 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
820 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
822 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
823 nir_print_instr(&instr
->instr
, stderr
);
824 fprintf(stderr
, "\n");
829 /* divergent boolean bcsel
830 * this implements bcsel on bools: dst = s0 ? s1 : s2
831 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
832 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
834 if (cond
.id() != then
.id())
835 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
837 if (cond
.id() == els
.id())
838 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
840 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
841 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
844 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
845 aco_opcode op
, uint32_t undo
)
847 /* multiply by 16777216 to handle denormals */
848 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
849 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
850 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
851 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
852 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
854 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
856 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
859 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
861 if (ctx
->block
->fp_mode
.denorm32
== 0) {
862 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
866 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
869 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
871 if (ctx
->block
->fp_mode
.denorm32
== 0) {
872 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
876 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
879 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
881 if (ctx
->block
->fp_mode
.denorm32
== 0) {
882 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
886 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
889 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
891 if (ctx
->block
->fp_mode
.denorm32
== 0) {
892 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
896 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
899 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
901 if (ctx
->options
->chip_class
>= GFX7
)
902 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
904 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
905 /* TODO: create more efficient code! */
906 if (val
.type() == RegType::sgpr
)
907 val
= as_vgpr(ctx
, val
);
909 /* Split the input value. */
910 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
911 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
913 /* Extract the exponent and compute the unbiased value. */
914 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
915 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
917 /* Extract the fractional part. */
918 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
919 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
921 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
924 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
925 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
926 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
927 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
928 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
930 /* Get the sign bit. */
931 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
933 /* Decide the operation to apply depending on the unbiased exponent. */
934 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
935 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
936 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
937 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
938 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
939 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
941 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
944 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
946 if (ctx
->options
->chip_class
>= GFX7
)
947 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
949 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
950 Temp src0
= as_vgpr(ctx
, val
);
952 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
953 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
955 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
956 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
957 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
959 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
960 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
961 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
964 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
965 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
967 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
969 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
970 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
972 return add
->definitions
[0].getTemp();
975 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
977 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
978 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
980 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
983 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
984 return bld
.copy(Definition(dst
), src
);
985 else if (dst
.bytes() < src
.bytes())
986 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
990 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
993 } else if (src
.regClass() == s1
) {
995 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
997 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
998 } else if (ctx
->options
->chip_class
>= GFX8
) {
999 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1000 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1001 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1002 sdwa
->operands
[0] = Operand(src
);
1003 sdwa
->definitions
[0] = Definition(tmp
);
1005 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1007 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1008 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1009 bld
.insert(std::move(sdwa
));
1011 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1012 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1013 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1016 if (dst_bits
== 64) {
1017 if (is_signed
&& dst
.regClass() == s2
) {
1018 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1019 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1020 } else if (is_signed
&& dst
.regClass() == v2
) {
1021 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1022 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1024 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1031 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1033 if (!instr
->dest
.dest
.is_ssa
) {
1034 fprintf(stderr
, "nir alu dst not in ssa: ");
1035 nir_print_instr(&instr
->instr
, stderr
);
1036 fprintf(stderr
, "\n");
1039 Builder
bld(ctx
->program
, ctx
->block
);
1040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1045 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1046 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1047 for (unsigned i
= 0; i
< num
; ++i
)
1048 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1050 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1051 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1052 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1053 for (unsigned i
= 0; i
< num
; ++i
) {
1054 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1055 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1057 vec
->operands
[i
] = Operand
{elems
[i
]};
1059 vec
->definitions
[0] = Definition(dst
);
1060 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1061 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1063 // TODO: that is a bit suboptimal..
1064 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1065 for (unsigned i
= 0; i
< num
- 1; ++i
)
1066 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1067 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1068 for (unsigned i
= 0; i
< num
; ++i
) {
1069 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1070 if (bit
% 32 == 0) {
1071 elems
[bit
/ 32] = elems
[i
];
1073 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1074 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1075 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1078 if (dst
.size() == 1)
1079 bld
.copy(Definition(dst
), elems
[0]);
1081 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1086 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1087 aco_ptr
<Instruction
> mov
;
1088 if (dst
.type() == RegType::sgpr
) {
1089 if (src
.type() == RegType::vgpr
)
1090 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1091 else if (src
.regClass() == s1
)
1092 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1093 else if (src
.regClass() == s2
)
1094 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1096 unreachable("wrong src register class for nir_op_imov");
1098 if (dst
.regClass() == v1
)
1099 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1100 else if (dst
.regClass() == v1b
||
1101 dst
.regClass() == v2b
||
1102 dst
.regClass() == v2
)
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1105 unreachable("wrong src register class for nir_op_imov");
1110 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1111 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1112 assert(src
.regClass() == bld
.lm
);
1113 assert(dst
.regClass() == bld
.lm
);
1114 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1115 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1116 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1117 } else if (dst
.regClass() == v1
) {
1118 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1119 } else if (dst
.type() == RegType::sgpr
) {
1120 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1121 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1124 nir_print_instr(&instr
->instr
, stderr
);
1125 fprintf(stderr
, "\n");
1130 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1131 if (dst
.regClass() == v1
) {
1132 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1133 } else if (dst
.regClass() == s1
) {
1134 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1135 } else if (dst
.size() == 2) {
1136 Temp src0
= bld
.tmp(dst
.type(), 1);
1137 Temp src1
= bld
.tmp(dst
.type(), 1);
1138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1140 if (dst
.regClass() == s2
) {
1141 Temp carry
= bld
.tmp(s1
);
1142 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1143 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1144 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1146 Temp lower
= bld
.tmp(v1
);
1147 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1148 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1149 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1152 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1153 nir_print_instr(&instr
->instr
, stderr
);
1154 fprintf(stderr
, "\n");
1159 if (dst
.regClass() == s1
) {
1160 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1161 } else if (dst
.regClass() == v1
) {
1162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1163 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1166 nir_print_instr(&instr
->instr
, stderr
);
1167 fprintf(stderr
, "\n");
1171 case nir_op_isign
: {
1172 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1173 if (dst
.regClass() == s1
) {
1174 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1175 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1176 } else if (dst
.regClass() == s2
) {
1177 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1179 if (ctx
->program
->chip_class
>= GFX8
)
1180 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1182 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1183 /* SCC gets zero-extended to 64 bit */
1184 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1185 } else if (dst
.regClass() == v1
) {
1186 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1187 } else if (dst
.regClass() == v2
) {
1188 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1189 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1190 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1191 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1192 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1193 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1195 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1196 nir_print_instr(&instr
->instr
, stderr
);
1197 fprintf(stderr
, "\n");
1202 if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1207 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1208 nir_print_instr(&instr
->instr
, stderr
);
1209 fprintf(stderr
, "\n");
1214 if (dst
.regClass() == v1
) {
1215 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1216 } else if (dst
.regClass() == s1
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1219 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1220 nir_print_instr(&instr
->instr
, stderr
);
1221 fprintf(stderr
, "\n");
1226 if (dst
.regClass() == v1
) {
1227 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1228 } else if (dst
.regClass() == s1
) {
1229 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (dst
.regClass() == v1
) {
1239 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1243 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1244 nir_print_instr(&instr
->instr
, stderr
);
1245 fprintf(stderr
, "\n");
1250 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1251 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1252 } else if (dst
.regClass() == v1
) {
1253 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1254 } else if (dst
.regClass() == s1
) {
1255 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1256 } else if (dst
.regClass() == s2
) {
1257 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1260 nir_print_instr(&instr
->instr
, stderr
);
1261 fprintf(stderr
, "\n");
1266 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1267 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1268 } else if (dst
.regClass() == v1
) {
1269 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1270 } else if (dst
.regClass() == s1
) {
1271 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1272 } else if (dst
.regClass() == s2
) {
1273 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1275 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1276 nir_print_instr(&instr
->instr
, stderr
);
1277 fprintf(stderr
, "\n");
1282 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1283 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1284 } else if (dst
.regClass() == v1
) {
1285 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1286 } else if (dst
.regClass() == s1
) {
1287 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1288 } else if (dst
.regClass() == s2
) {
1289 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1291 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1292 nir_print_instr(&instr
->instr
, stderr
);
1293 fprintf(stderr
, "\n");
1298 if (dst
.regClass() == v1
) {
1299 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1300 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1301 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1302 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1303 } else if (dst
.regClass() == v2
) {
1304 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1305 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1306 } else if (dst
.regClass() == s2
) {
1307 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1308 } else if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1318 if (dst
.regClass() == v1
) {
1319 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1320 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1321 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1322 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1323 } else if (dst
.regClass() == v2
) {
1324 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1325 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1326 } else if (dst
.regClass() == s1
) {
1327 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1328 } else if (dst
.regClass() == s2
) {
1329 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1331 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1332 nir_print_instr(&instr
->instr
, stderr
);
1333 fprintf(stderr
, "\n");
1338 if (dst
.regClass() == v1
) {
1339 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1340 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1341 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1342 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1343 } else if (dst
.regClass() == v2
) {
1344 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1345 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1346 } else if (dst
.regClass() == s1
) {
1347 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1348 } else if (dst
.regClass() == s2
) {
1349 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1351 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1352 nir_print_instr(&instr
->instr
, stderr
);
1353 fprintf(stderr
, "\n");
1357 case nir_op_find_lsb
: {
1358 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1359 if (src
.regClass() == s1
) {
1360 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1361 } else if (src
.regClass() == v1
) {
1362 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1363 } else if (src
.regClass() == s2
) {
1364 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1372 case nir_op_ufind_msb
:
1373 case nir_op_ifind_msb
: {
1374 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1375 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1376 aco_opcode op
= src
.regClass() == s2
?
1377 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1378 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1379 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1381 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1382 Operand(src
.size() * 32u - 1u), msb_rev
);
1383 Temp msb
= sub
.def(0).getTemp();
1384 Temp carry
= sub
.def(1).getTemp();
1386 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1387 } else if (src
.regClass() == v1
) {
1388 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1389 Temp msb_rev
= bld
.tmp(v1
);
1390 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1391 Temp msb
= bld
.tmp(v1
);
1392 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1393 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1395 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1396 nir_print_instr(&instr
->instr
, stderr
);
1397 fprintf(stderr
, "\n");
1401 case nir_op_bitfield_reverse
: {
1402 if (dst
.regClass() == s1
) {
1403 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1404 } else if (dst
.regClass() == v1
) {
1405 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1407 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1408 nir_print_instr(&instr
->instr
, stderr
);
1409 fprintf(stderr
, "\n");
1414 if (dst
.regClass() == s1
) {
1415 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1419 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1420 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1421 if (dst
.regClass() == v1
) {
1422 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1426 assert(src0
.size() == 2 && src1
.size() == 2);
1427 Temp src00
= bld
.tmp(src0
.type(), 1);
1428 Temp src01
= bld
.tmp(dst
.type(), 1);
1429 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1430 Temp src10
= bld
.tmp(src1
.type(), 1);
1431 Temp src11
= bld
.tmp(dst
.type(), 1);
1432 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1434 if (dst
.regClass() == s2
) {
1435 Temp carry
= bld
.tmp(s1
);
1436 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1437 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1438 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1439 } else if (dst
.regClass() == v2
) {
1440 Temp dst0
= bld
.tmp(v1
);
1441 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1442 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1443 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1445 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1446 nir_print_instr(&instr
->instr
, stderr
);
1447 fprintf(stderr
, "\n");
1451 case nir_op_uadd_sat
: {
1452 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1453 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1454 if (dst
.regClass() == s1
) {
1455 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1456 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1458 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1459 } else if (dst
.regClass() == v1
) {
1460 if (ctx
->options
->chip_class
>= GFX9
) {
1461 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1462 add
->operands
[0] = Operand(src0
);
1463 add
->operands
[1] = Operand(src1
);
1464 add
->definitions
[0] = Definition(dst
);
1466 ctx
->block
->instructions
.emplace_back(std::move(add
));
1468 if (src1
.regClass() != v1
)
1469 std::swap(src0
, src1
);
1470 assert(src1
.regClass() == v1
);
1471 Temp tmp
= bld
.tmp(v1
);
1472 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1473 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1476 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1477 nir_print_instr(&instr
->instr
, stderr
);
1478 fprintf(stderr
, "\n");
1482 case nir_op_uadd_carry
: {
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == s1
) {
1486 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1489 if (dst
.regClass() == v1
) {
1490 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1491 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1495 Temp src00
= bld
.tmp(src0
.type(), 1);
1496 Temp src01
= bld
.tmp(dst
.type(), 1);
1497 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1498 Temp src10
= bld
.tmp(src1
.type(), 1);
1499 Temp src11
= bld
.tmp(dst
.type(), 1);
1500 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1501 if (dst
.regClass() == s2
) {
1502 Temp carry
= bld
.tmp(s1
);
1503 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1504 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1506 } else if (dst
.regClass() == v2
) {
1507 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1508 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1509 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1512 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1513 nir_print_instr(&instr
->instr
, stderr
);
1514 fprintf(stderr
, "\n");
1519 if (dst
.regClass() == s1
) {
1520 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1524 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1525 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1526 if (dst
.regClass() == v1
) {
1527 bld
.vsub32(Definition(dst
), src0
, src1
);
1531 Temp src00
= bld
.tmp(src0
.type(), 1);
1532 Temp src01
= bld
.tmp(dst
.type(), 1);
1533 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1534 Temp src10
= bld
.tmp(src1
.type(), 1);
1535 Temp src11
= bld
.tmp(dst
.type(), 1);
1536 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1537 if (dst
.regClass() == s2
) {
1538 Temp carry
= bld
.tmp(s1
);
1539 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1540 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1542 } else if (dst
.regClass() == v2
) {
1543 Temp lower
= bld
.tmp(v1
);
1544 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1545 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1546 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1554 case nir_op_usub_borrow
: {
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.regClass() == s1
) {
1558 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1560 } else if (dst
.regClass() == v1
) {
1561 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1562 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1566 Temp src00
= bld
.tmp(src0
.type(), 1);
1567 Temp src01
= bld
.tmp(dst
.type(), 1);
1568 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1569 Temp src10
= bld
.tmp(src1
.type(), 1);
1570 Temp src11
= bld
.tmp(dst
.type(), 1);
1571 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1572 if (dst
.regClass() == s2
) {
1573 Temp borrow
= bld
.tmp(s1
);
1574 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1575 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1576 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1577 } else if (dst
.regClass() == v2
) {
1578 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1579 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1580 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1581 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1583 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1584 nir_print_instr(&instr
->instr
, stderr
);
1585 fprintf(stderr
, "\n");
1590 if (dst
.regClass() == v1
) {
1591 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1592 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1593 } else if (dst
.regClass() == s1
) {
1594 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1596 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1597 nir_print_instr(&instr
->instr
, stderr
);
1598 fprintf(stderr
, "\n");
1602 case nir_op_umul_high
: {
1603 if (dst
.regClass() == v1
) {
1604 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1605 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1606 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1607 } else if (dst
.regClass() == s1
) {
1608 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1609 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1610 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1613 nir_print_instr(&instr
->instr
, stderr
);
1614 fprintf(stderr
, "\n");
1618 case nir_op_imul_high
: {
1619 if (dst
.regClass() == v1
) {
1620 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1621 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1622 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1623 } else if (dst
.regClass() == s1
) {
1624 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1625 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1626 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1629 nir_print_instr(&instr
->instr
, stderr
);
1630 fprintf(stderr
, "\n");
1635 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1636 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1637 if (dst
.regClass() == v2b
) {
1638 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1639 } else if (dst
.regClass() == v1
) {
1640 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1641 } else if (dst
.regClass() == v2
) {
1642 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1644 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1645 nir_print_instr(&instr
->instr
, stderr
);
1646 fprintf(stderr
, "\n");
1651 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1652 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1653 if (dst
.regClass() == v2b
) {
1654 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1655 } else if (dst
.regClass() == v1
) {
1656 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1657 } else if (dst
.regClass() == v2
) {
1658 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1660 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1661 nir_print_instr(&instr
->instr
, stderr
);
1662 fprintf(stderr
, "\n");
1667 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1668 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1669 if (dst
.regClass() == v2b
) {
1670 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1671 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1673 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1674 } else if (dst
.regClass() == v1
) {
1675 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1676 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1678 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1679 } else if (dst
.regClass() == v2
) {
1680 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1681 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1682 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1693 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1694 if (dst
.regClass() == v2b
) {
1695 // TODO: check fp_mode.must_flush_denorms16_64
1696 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1697 } else if (dst
.regClass() == v1
) {
1698 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 } else if (dst
.regClass() == v2
) {
1700 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1701 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1702 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1704 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1715 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1716 if (dst
.regClass() == v2b
) {
1717 // TODO: check fp_mode.must_flush_denorms16_64
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1719 } else if (dst
.regClass() == v1
) {
1720 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1721 } else if (dst
.regClass() == v2
) {
1722 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1723 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1724 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1726 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_fmax3
: {
1736 if (dst
.regClass() == v2b
) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1742 nir_print_instr(&instr
->instr
, stderr
);
1743 fprintf(stderr
, "\n");
1747 case nir_op_fmin3
: {
1748 if (dst
.regClass() == v2b
) {
1749 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1750 } else if (dst
.regClass() == v1
) {
1751 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1754 nir_print_instr(&instr
->instr
, stderr
);
1755 fprintf(stderr
, "\n");
1759 case nir_op_fmed3
: {
1760 if (dst
.regClass() == v2b
) {
1761 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1771 case nir_op_umax3
: {
1772 if (dst
.size() == 1) {
1773 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_umin3
: {
1782 if (dst
.size() == 1) {
1783 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1785 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1786 nir_print_instr(&instr
->instr
, stderr
);
1787 fprintf(stderr
, "\n");
1791 case nir_op_umed3
: {
1792 if (dst
.size() == 1) {
1793 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1801 case nir_op_imax3
: {
1802 if (dst
.size() == 1) {
1803 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1805 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1806 nir_print_instr(&instr
->instr
, stderr
);
1807 fprintf(stderr
, "\n");
1811 case nir_op_imin3
: {
1812 if (dst
.size() == 1) {
1813 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1815 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1816 nir_print_instr(&instr
->instr
, stderr
);
1817 fprintf(stderr
, "\n");
1821 case nir_op_imed3
: {
1822 if (dst
.size() == 1) {
1823 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1825 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1826 nir_print_instr(&instr
->instr
, stderr
);
1827 fprintf(stderr
, "\n");
1831 case nir_op_cube_face_coord
: {
1832 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1833 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1834 emit_extract_vector(ctx
, in
, 1, v1
),
1835 emit_extract_vector(ctx
, in
, 2, v1
) };
1836 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1837 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1838 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1839 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1840 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1841 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1842 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1845 case nir_op_cube_face_index
: {
1846 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1847 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1848 emit_extract_vector(ctx
, in
, 1, v1
),
1849 emit_extract_vector(ctx
, in
, 2, v1
) };
1850 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1853 case nir_op_bcsel
: {
1854 emit_bcsel(ctx
, instr
, dst
);
1858 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1859 if (dst
.regClass() == v2b
) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1861 } else if (dst
.regClass() == v1
) {
1862 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1863 } else if (dst
.regClass() == v2
) {
1864 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1866 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1867 nir_print_instr(&instr
->instr
, stderr
);
1868 fprintf(stderr
, "\n");
1873 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1874 if (dst
.regClass() == v2b
) {
1875 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1898 } else if (dst
.regClass() == v1
) {
1899 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1900 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1901 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1902 } else if (dst
.regClass() == v2
) {
1903 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1904 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1905 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1906 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1907 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1908 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1911 nir_print_instr(&instr
->instr
, stderr
);
1912 fprintf(stderr
, "\n");
1917 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1918 if (dst
.regClass() == v2b
) {
1919 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1920 } else if (dst
.regClass() == v1
) {
1921 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1922 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1923 // TODO: confirm that this holds under any circumstances
1924 } else if (dst
.regClass() == v2
) {
1925 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1926 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1935 case nir_op_flog2
: {
1936 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1937 if (dst
.regClass() == v2b
) {
1938 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1939 } else if (dst
.regClass() == v1
) {
1940 emit_log2(ctx
, bld
, Definition(dst
), src
);
1942 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1943 nir_print_instr(&instr
->instr
, stderr
);
1944 fprintf(stderr
, "\n");
1949 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1950 if (dst
.regClass() == v2b
) {
1951 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1952 } else if (dst
.regClass() == v1
) {
1953 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1954 } else if (dst
.regClass() == v2
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1958 nir_print_instr(&instr
->instr
, stderr
);
1959 fprintf(stderr
, "\n");
1963 case nir_op_fexp2
: {
1964 if (dst
.regClass() == v2b
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1966 } else if (dst
.regClass() == v1
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1969 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1970 nir_print_instr(&instr
->instr
, stderr
);
1971 fprintf(stderr
, "\n");
1975 case nir_op_fsqrt
: {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 if (dst
.regClass() == v2b
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffract
: {
1991 if (dst
.regClass() == v2b
) {
1992 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1993 } else if (dst
.regClass() == v1
) {
1994 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1995 } else if (dst
.regClass() == v2
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1998 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1999 nir_print_instr(&instr
->instr
, stderr
);
2000 fprintf(stderr
, "\n");
2004 case nir_op_ffloor
: {
2005 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2006 if (dst
.regClass() == v2b
) {
2007 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2008 } else if (dst
.regClass() == v1
) {
2009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2010 } else if (dst
.regClass() == v2
) {
2011 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2013 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2014 nir_print_instr(&instr
->instr
, stderr
);
2015 fprintf(stderr
, "\n");
2019 case nir_op_fceil
: {
2020 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2021 if (dst
.regClass() == v2b
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2023 } else if (dst
.regClass() == v1
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2025 } else if (dst
.regClass() == v2
) {
2026 if (ctx
->options
->chip_class
>= GFX7
) {
2027 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2029 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2030 /* trunc = trunc(src0)
2031 * if (src0 > 0.0 && src0 != trunc)
2034 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2035 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2036 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2037 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2038 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2039 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2040 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2044 nir_print_instr(&instr
->instr
, stderr
);
2045 fprintf(stderr
, "\n");
2049 case nir_op_ftrunc
: {
2050 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2051 if (dst
.regClass() == v2b
) {
2052 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2053 } else if (dst
.regClass() == v1
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2055 } else if (dst
.regClass() == v2
) {
2056 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_fround_even
: {
2065 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (dst
.regClass() == v2b
) {
2067 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2068 } else if (dst
.regClass() == v1
) {
2069 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2070 } else if (dst
.regClass() == v2
) {
2071 if (ctx
->options
->chip_class
>= GFX7
) {
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2074 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2075 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2078 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2079 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2080 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2081 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2082 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2083 tmp
= sub
->definitions
[0].getTemp();
2085 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2086 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2087 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2088 Temp cond
= vop3
->definitions
[0].getTemp();
2090 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2091 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2092 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2093 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2095 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2098 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2099 nir_print_instr(&instr
->instr
, stderr
);
2100 fprintf(stderr
, "\n");
2106 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2107 aco_ptr
<Instruction
> norm
;
2108 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2109 if (dst
.regClass() == v2b
) {
2110 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2113 } else if (dst
.regClass() == v1
) {
2114 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2116 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2117 if (ctx
->options
->chip_class
< GFX9
)
2118 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2120 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2121 bld
.vop1(opcode
, Definition(dst
), tmp
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_ldexp
: {
2130 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2131 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2132 if (dst
.regClass() == v2b
) {
2133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2134 } else if (dst
.regClass() == v1
) {
2135 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2136 } else if (dst
.regClass() == v2
) {
2137 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2139 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2140 nir_print_instr(&instr
->instr
, stderr
);
2141 fprintf(stderr
, "\n");
2145 case nir_op_frexp_sig
: {
2146 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2147 if (dst
.regClass() == v2b
) {
2148 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2149 } else if (dst
.regClass() == v1
) {
2150 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2151 } else if (dst
.regClass() == v2
) {
2152 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2155 nir_print_instr(&instr
->instr
, stderr
);
2156 fprintf(stderr
, "\n");
2160 case nir_op_frexp_exp
: {
2161 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2162 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2163 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2164 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2165 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2166 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2167 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2168 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2169 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2171 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2172 nir_print_instr(&instr
->instr
, stderr
);
2173 fprintf(stderr
, "\n");
2177 case nir_op_fsign
: {
2178 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2179 if (dst
.regClass() == v2b
) {
2180 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2181 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2186 } else if (dst
.regClass() == v1
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2189 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2190 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2191 } else if (dst
.regClass() == v2
) {
2192 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2193 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2194 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2196 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2197 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2198 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2200 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2203 nir_print_instr(&instr
->instr
, stderr
);
2204 fprintf(stderr
, "\n");
2209 case nir_op_f2f16_rtne
: {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2212 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2213 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2216 case nir_op_f2f16_rtz
: {
2217 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2218 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2219 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2220 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2223 case nir_op_f2f32
: {
2224 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2225 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2226 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2230 nir_print_instr(&instr
->instr
, stderr
);
2231 fprintf(stderr
, "\n");
2235 case nir_op_f2f64
: {
2236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2237 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2238 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2239 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2242 case nir_op_i2f16
: {
2243 assert(dst
.regClass() == v2b
);
2244 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2245 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2246 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2247 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2248 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2249 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2252 case nir_op_i2f32
: {
2253 assert(dst
.size() == 1);
2254 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2255 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2256 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2257 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2260 case nir_op_i2f64
: {
2261 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2262 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2263 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2264 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2265 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2266 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2267 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2268 RegClass rc
= RegClass(src
.type(), 1);
2269 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2271 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2272 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2273 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2274 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2277 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2278 nir_print_instr(&instr
->instr
, stderr
);
2279 fprintf(stderr
, "\n");
2283 case nir_op_u2f16
: {
2284 assert(dst
.regClass() == v2b
);
2285 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2286 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2287 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2288 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2289 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2290 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2293 case nir_op_u2f32
: {
2294 assert(dst
.size() == 1);
2295 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2296 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2297 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2299 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2300 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2301 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2305 case nir_op_u2f64
: {
2306 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2307 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2308 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2309 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2310 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2311 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2312 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2313 RegClass rc
= RegClass(src
.type(), 1);
2314 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2315 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2316 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2317 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2318 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2319 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2321 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2322 nir_print_instr(&instr
->instr
, stderr
);
2323 fprintf(stderr
, "\n");
2328 case nir_op_f2i16
: {
2329 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2330 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2331 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2332 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2333 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2335 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2337 if (dst
.type() == RegType::vgpr
)
2338 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2340 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2344 case nir_op_f2u16
: {
2345 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2346 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2347 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2348 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2349 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2351 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2353 if (dst
.type() == RegType::vgpr
)
2354 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2356 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2359 case nir_op_f2i32
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2362 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2363 if (dst
.type() == RegType::vgpr
) {
2364 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2366 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2369 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2370 if (dst
.type() == RegType::vgpr
)
2371 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2373 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2374 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2376 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2377 if (dst
.type() == RegType::vgpr
)
2378 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2380 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2381 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2384 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2385 nir_print_instr(&instr
->instr
, stderr
);
2386 fprintf(stderr
, "\n");
2390 case nir_op_f2u32
: {
2391 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2392 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2393 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2394 if (dst
.type() == RegType::vgpr
) {
2395 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2397 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2400 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2401 if (dst
.type() == RegType::vgpr
)
2402 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2404 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2405 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2407 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2408 if (dst
.type() == RegType::vgpr
)
2409 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2411 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2412 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2415 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2416 nir_print_instr(&instr
->instr
, stderr
);
2417 fprintf(stderr
, "\n");
2421 case nir_op_f2i64
: {
2422 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2423 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2424 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2426 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2427 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2428 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2429 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2430 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2431 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2432 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2433 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2434 Temp new_exponent
= bld
.tmp(v1
);
2435 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2436 if (ctx
->program
->chip_class
>= GFX8
)
2437 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2439 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2440 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2441 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2442 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2443 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2444 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2445 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2446 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2447 Temp new_lower
= bld
.tmp(v1
);
2448 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2449 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2450 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2452 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2453 if (src
.type() == RegType::vgpr
)
2454 src
= bld
.as_uniform(src
);
2455 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2456 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2457 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2458 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2459 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2460 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2461 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2462 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2463 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2464 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2465 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2466 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2467 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2468 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2469 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2470 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2471 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2472 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2473 Temp borrow
= bld
.tmp(s1
);
2474 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2475 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2476 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2478 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2479 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2480 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2481 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2482 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2483 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2484 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2485 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2486 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2487 if (dst
.type() == RegType::sgpr
) {
2488 lower
= bld
.as_uniform(lower
);
2489 upper
= bld
.as_uniform(upper
);
2491 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2494 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2495 nir_print_instr(&instr
->instr
, stderr
);
2496 fprintf(stderr
, "\n");
2500 case nir_op_f2u64
: {
2501 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2502 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2503 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2505 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2506 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2507 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2508 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2509 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2510 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2511 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2512 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2513 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2514 Temp new_exponent
= bld
.tmp(v1
);
2515 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2516 if (ctx
->program
->chip_class
>= GFX8
)
2517 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2519 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2520 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2521 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2522 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2523 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2524 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2525 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2526 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2528 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2529 if (src
.type() == RegType::vgpr
)
2530 src
= bld
.as_uniform(src
);
2531 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2532 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2533 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2534 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2535 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2536 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2537 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2538 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2539 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2540 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2541 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2542 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2543 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2544 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2545 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2546 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2547 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2550 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2551 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2552 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2553 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2554 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2555 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2556 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2557 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2558 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2559 if (dst
.type() == RegType::sgpr
) {
2560 lower
= bld
.as_uniform(lower
);
2561 upper
= bld
.as_uniform(upper
);
2563 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2566 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2567 nir_print_instr(&instr
->instr
, stderr
);
2568 fprintf(stderr
, "\n");
2572 case nir_op_b2f16
: {
2573 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2574 assert(src
.regClass() == bld
.lm
);
2576 if (dst
.regClass() == s1
) {
2577 src
= bool_to_scalar_condition(ctx
, src
);
2578 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2579 } else if (dst
.regClass() == v2b
) {
2580 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2581 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2583 unreachable("Wrong destination register class for nir_op_b2f16.");
2587 case nir_op_b2f32
: {
2588 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2589 assert(src
.regClass() == bld
.lm
);
2591 if (dst
.regClass() == s1
) {
2592 src
= bool_to_scalar_condition(ctx
, src
);
2593 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2594 } else if (dst
.regClass() == v1
) {
2595 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2597 unreachable("Wrong destination register class for nir_op_b2f32.");
2601 case nir_op_b2f64
: {
2602 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2603 assert(src
.regClass() == bld
.lm
);
2605 if (dst
.regClass() == s2
) {
2606 src
= bool_to_scalar_condition(ctx
, src
);
2607 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2608 } else if (dst
.regClass() == v2
) {
2609 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2610 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2611 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2613 unreachable("Wrong destination register class for nir_op_b2f64.");
2620 case nir_op_i2i64
: {
2621 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2622 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2628 case nir_op_u2u64
: {
2629 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2630 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2634 case nir_op_b2i32
: {
2635 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2636 assert(src
.regClass() == bld
.lm
);
2638 if (dst
.regClass() == s1
) {
2639 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2640 bool_to_scalar_condition(ctx
, src
, dst
);
2641 } else if (dst
.regClass() == v1
) {
2642 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2644 unreachable("Invalid register class for b2i32");
2650 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2651 assert(dst
.regClass() == bld
.lm
);
2653 if (src
.type() == RegType::vgpr
) {
2654 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2655 assert(dst
.regClass() == bld
.lm
);
2656 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2657 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2659 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2661 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2662 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2664 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2665 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2667 bool_to_vector_condition(ctx
, tmp
, dst
);
2671 case nir_op_pack_64_2x32_split
: {
2672 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2673 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2675 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2678 case nir_op_unpack_64_2x32_split_x
:
2679 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2681 case nir_op_unpack_64_2x32_split_y
:
2682 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2684 case nir_op_unpack_32_2x16_split_x
:
2685 if (dst
.type() == RegType::vgpr
) {
2686 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2688 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2691 case nir_op_unpack_32_2x16_split_y
:
2692 if (dst
.type() == RegType::vgpr
) {
2693 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2695 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2698 case nir_op_pack_32_2x16_split
: {
2699 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2700 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2701 if (dst
.regClass() == v1
) {
2702 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2703 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2704 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2706 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2707 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2708 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2712 case nir_op_pack_half_2x16
: {
2713 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2715 if (dst
.regClass() == v1
) {
2716 Temp src0
= bld
.tmp(v1
);
2717 Temp src1
= bld
.tmp(v1
);
2718 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2719 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2720 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2722 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2723 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2724 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2727 nir_print_instr(&instr
->instr
, stderr
);
2728 fprintf(stderr
, "\n");
2732 case nir_op_unpack_half_2x16_split_x
: {
2733 if (dst
.regClass() == v1
) {
2734 Builder
bld(ctx
->program
, ctx
->block
);
2735 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2737 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2738 nir_print_instr(&instr
->instr
, stderr
);
2739 fprintf(stderr
, "\n");
2743 case nir_op_unpack_half_2x16_split_y
: {
2744 if (dst
.regClass() == v1
) {
2745 Builder
bld(ctx
->program
, ctx
->block
);
2746 /* TODO: use SDWA here */
2747 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2748 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2751 nir_print_instr(&instr
->instr
, stderr
);
2752 fprintf(stderr
, "\n");
2756 case nir_op_fquantize2f16
: {
2757 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2758 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2761 if (ctx
->program
->chip_class
>= GFX8
) {
2762 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2763 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2764 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2766 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2767 * so compare the result and flush to 0 if it's smaller.
2769 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2770 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2771 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2772 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2773 cmp_res
= vop3
->definitions
[0].getTemp();
2776 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2777 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2778 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2780 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2785 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2786 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2788 if (dst
.regClass() == s1
) {
2789 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2790 } else if (dst
.regClass() == v1
) {
2791 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2793 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2794 nir_print_instr(&instr
->instr
, stderr
);
2795 fprintf(stderr
, "\n");
2799 case nir_op_bitfield_select
: {
2800 /* (mask & insert) | (~mask & base) */
2801 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2802 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2803 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2805 /* dst = (insert & bitmask) | (base & ~bitmask) */
2806 if (dst
.regClass() == s1
) {
2807 aco_ptr
<Instruction
> sop2
;
2808 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2809 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2811 if (const_insert
&& const_bitmask
) {
2812 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2814 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2815 lhs
= Operand(insert
);
2819 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2820 if (const_base
&& const_bitmask
) {
2821 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2823 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2824 rhs
= Operand(base
);
2827 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2829 } else if (dst
.regClass() == v1
) {
2830 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2831 base
= as_vgpr(ctx
, base
);
2832 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2833 insert
= as_vgpr(ctx
, insert
);
2835 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2838 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2839 nir_print_instr(&instr
->instr
, stderr
);
2840 fprintf(stderr
, "\n");
2846 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2847 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2848 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2850 if (dst
.type() == RegType::sgpr
) {
2852 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2853 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2854 if (const_offset
&& const_bits
) {
2855 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2856 extract
= Operand(const_extract
);
2860 width
= Operand(const_bits
->u32
<< 16);
2862 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2864 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2868 if (dst
.regClass() == s1
) {
2869 if (instr
->op
== nir_op_ubfe
)
2870 opcode
= aco_opcode::s_bfe_u32
;
2872 opcode
= aco_opcode::s_bfe_i32
;
2873 } else if (dst
.regClass() == s2
) {
2874 if (instr
->op
== nir_op_ubfe
)
2875 opcode
= aco_opcode::s_bfe_u64
;
2877 opcode
= aco_opcode::s_bfe_i64
;
2879 unreachable("Unsupported BFE bit size");
2882 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2886 if (dst
.regClass() == v1
) {
2887 if (instr
->op
== nir_op_ubfe
)
2888 opcode
= aco_opcode::v_bfe_u32
;
2890 opcode
= aco_opcode::v_bfe_i32
;
2892 unreachable("Unsupported BFE bit size");
2895 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2899 case nir_op_bit_count
: {
2900 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2901 if (src
.regClass() == s1
) {
2902 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2903 } else if (src
.regClass() == v1
) {
2904 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2905 } else if (src
.regClass() == v2
) {
2906 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2907 emit_extract_vector(ctx
, src
, 1, v1
),
2908 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2909 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2910 } else if (src
.regClass() == s2
) {
2911 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2913 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2914 nir_print_instr(&instr
->instr
, stderr
);
2915 fprintf(stderr
, "\n");
2920 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2928 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2932 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2936 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2940 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2944 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2945 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2947 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2948 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2952 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2953 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2955 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2956 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2960 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2964 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2969 case nir_op_fddx_fine
:
2970 case nir_op_fddy_fine
:
2971 case nir_op_fddx_coarse
:
2972 case nir_op_fddy_coarse
: {
2973 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2974 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2975 if (instr
->op
== nir_op_fddx_fine
) {
2976 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2977 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2978 } else if (instr
->op
== nir_op_fddy_fine
) {
2979 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2980 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2982 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2983 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2984 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2986 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2990 if (ctx
->program
->chip_class
>= GFX8
) {
2991 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2992 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2994 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2995 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2996 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2998 emit_wqm(ctx
, tmp
, dst
, true);
3002 fprintf(stderr
, "Unknown NIR ALU instr: ");
3003 nir_print_instr(&instr
->instr
, stderr
);
3004 fprintf(stderr
, "\n");
3008 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3010 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3012 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3013 // which get truncated the lsb if double and msb if int
3014 // for now, we only use s_mov_b64 with 64bit inline constants
3015 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3016 assert(dst
.type() == RegType::sgpr
);
3018 Builder
bld(ctx
->program
, ctx
->block
);
3020 if (instr
->def
.bit_size
== 1) {
3021 assert(dst
.regClass() == bld
.lm
);
3022 int val
= instr
->value
[0].b
? -1 : 0;
3023 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3024 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3025 } else if (instr
->def
.bit_size
== 8) {
3026 /* ensure that the value is correctly represented in the low byte of the register */
3027 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3028 } else if (instr
->def
.bit_size
== 16) {
3029 /* ensure that the value is correctly represented in the low half of the register */
3030 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3031 } else if (dst
.size() == 1) {
3032 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3034 assert(dst
.size() != 1);
3035 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3036 if (instr
->def
.bit_size
== 64)
3037 for (unsigned i
= 0; i
< dst
.size(); i
++)
3038 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3040 for (unsigned i
= 0; i
< dst
.size(); i
++)
3041 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3043 vec
->definitions
[0] = Definition(dst
);
3044 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3048 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3050 uint32_t new_mask
= 0;
3051 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3052 if (mask
& (1u << i
))
3053 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3057 struct LoadEmitInfo
{
3060 unsigned num_components
;
3061 unsigned component_size
;
3062 Temp resource
= Temp(0, s1
);
3063 unsigned component_stride
= 0;
3064 unsigned const_offset
= 0;
3065 unsigned align_mul
= 0;
3066 unsigned align_offset
= 0;
3069 unsigned swizzle_component_size
= 0;
3070 barrier_interaction barrier
= barrier_none
;
3071 bool can_reorder
= true;
3072 Temp soffset
= Temp(0, s1
);
3075 using LoadCallback
= Temp(*)(
3076 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3077 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3079 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3080 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3082 unsigned load_size
= info
->num_components
* info
->component_size
;
3083 unsigned component_size
= info
->component_size
;
3085 unsigned num_vals
= 0;
3086 Temp vals
[info
->dst
.bytes()];
3088 unsigned const_offset
= info
->const_offset
;
3090 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3091 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3093 unsigned bytes_read
= 0;
3094 while (bytes_read
< load_size
) {
3095 unsigned bytes_needed
= load_size
- bytes_read
;
3097 /* add buffer for unaligned loads */
3098 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3101 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3102 if (info
->component_stride
) {
3103 assert(supports_8bit_16bit_loads
&& "unimplemented");
3107 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3108 bytes_needed
= align(bytes_needed
, 4);
3115 if (info
->swizzle_component_size
)
3116 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3117 if (info
->component_stride
)
3118 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3120 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3122 /* reduce constant offset */
3123 Operand offset
= info
->offset
;
3124 unsigned reduced_const_offset
= const_offset
;
3125 bool remove_const_offset_completely
= need_to_align_offset
;
3126 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3127 unsigned to_add
= const_offset
;
3128 if (remove_const_offset_completely
) {
3129 reduced_const_offset
= 0;
3131 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3132 reduced_const_offset
%= max_const_offset_plus_one
;
3134 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3135 if (offset
.isConstant()) {
3136 offset
= Operand(offset
.constantValue() + to_add
);
3137 } else if (offset_tmp
.regClass() == s1
) {
3138 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3139 offset_tmp
, Operand(to_add
));
3140 } else if (offset_tmp
.regClass() == v1
) {
3141 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3143 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3144 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3145 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3147 if (offset_tmp
.regClass() == s2
) {
3148 Temp carry
= bld
.tmp(s1
);
3149 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3150 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3151 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3153 Temp new_lo
= bld
.tmp(v1
);
3154 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3155 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3156 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3161 /* align offset down if needed */
3162 Operand aligned_offset
= offset
;
3163 if (need_to_align_offset
) {
3164 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3165 if (offset
.isConstant()) {
3166 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3167 } else if (offset_tmp
.regClass() == s1
) {
3168 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3169 } else if (offset_tmp
.regClass() == s2
) {
3170 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3171 } else if (offset_tmp
.regClass() == v1
) {
3172 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3173 } else if (offset_tmp
.regClass() == v2
) {
3174 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3175 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3176 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3177 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3180 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3181 bld
.copy(bld
.def(s1
), aligned_offset
);
3183 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3184 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3185 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3187 /* the callback wrote directly to dst */
3188 if (val
== info
->dst
) {
3189 assert(num_vals
== 0);
3190 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3194 /* shift result right if needed */
3195 if (info
->component_size
< 4 && byte_align_loads
) {
3196 Operand
align((uint32_t)byte_align
);
3197 if (byte_align
== -1) {
3198 if (offset
.isConstant())
3199 align
= Operand(offset
.constantValue() % 4u);
3200 else if (offset
.size() == 2)
3201 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3206 assert(val
.bytes() >= load_size
&& "unimplemented");
3207 if (val
.type() == RegType::sgpr
)
3208 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3210 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3214 /* add result to list and advance */
3215 if (info
->component_stride
) {
3216 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3217 const_offset
+= info
->component_stride
;
3218 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3220 const_offset
+= val
.bytes();
3221 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3223 bytes_read
+= val
.bytes();
3224 vals
[num_vals
++] = val
;
3227 /* create array of components */
3228 unsigned components_split
= 0;
3229 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3230 bool has_vgprs
= false;
3231 for (unsigned i
= 0; i
< num_vals
;) {
3233 unsigned num_tmps
= 0;
3234 unsigned tmp_size
= 0;
3235 RegType reg_type
= RegType::sgpr
;
3236 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3237 if (vals
[i
].type() == RegType::vgpr
)
3238 reg_type
= RegType::vgpr
;
3239 tmp_size
+= vals
[i
].bytes();
3240 tmp
[num_tmps
++] = vals
[i
++];
3243 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3244 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3245 for (unsigned i
= 0; i
< num_vals
; i
++)
3246 vec
->operands
[i
] = Operand(tmp
[i
]);
3247 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3248 vec
->definitions
[0] = Definition(tmp
[0]);
3249 bld
.insert(std::move(vec
));
3252 if (tmp
[0].bytes() % component_size
) {
3254 assert(i
== num_vals
);
3255 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3256 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3259 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3261 unsigned start
= components_split
;
3263 if (tmp_size
== elem_rc
.bytes()) {
3264 allocated_vec
[components_split
++] = tmp
[0];
3266 assert(tmp_size
% elem_rc
.bytes() == 0);
3267 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3268 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3269 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3270 Temp component
= bld
.tmp(elem_rc
);
3271 allocated_vec
[components_split
++] = component
;
3272 split
->definitions
[i
] = Definition(component
);
3274 split
->operands
[0] = Operand(tmp
[0]);
3275 bld
.insert(std::move(split
));
3278 /* try to p_as_uniform early so we can create more optimizable code and
3279 * also update allocated_vec */
3280 for (unsigned j
= start
; j
< components_split
; j
++) {
3281 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3282 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3283 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3287 /* concatenate components and p_as_uniform() result if needed */
3288 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3289 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3291 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3293 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3294 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3295 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3296 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3298 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3299 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3300 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3301 vec
->definitions
[0] = Definition(tmp
);
3302 bld
.insert(std::move(vec
));
3303 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3305 vec
->definitions
[0] = Definition(info
->dst
);
3306 bld
.insert(std::move(vec
));
3310 Operand
load_lds_size_m0(Builder
& bld
)
3312 /* TODO: m0 does not need to be initialized on GFX9+ */
3313 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3316 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3317 Temp offset
, unsigned bytes_needed
,
3318 unsigned align
, unsigned const_offset
,
3321 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3323 Operand m
= load_lds_size_m0(bld
);
3325 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3326 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3331 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3332 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3334 op
= aco_opcode::ds_read_b128
;
3335 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3338 op
= aco_opcode::ds_read2_b64
;
3339 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3341 op
= aco_opcode::ds_read_b96
;
3342 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3344 op
= aco_opcode::ds_read_b64
;
3345 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3348 op
= aco_opcode::ds_read2_b32
;
3349 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3351 op
= aco_opcode::ds_read_b32
;
3352 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3354 op
= aco_opcode::ds_read_u16
;
3357 op
= aco_opcode::ds_read_u8
;
3360 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3361 if (const_offset
>= max_offset_plus_one
) {
3362 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3363 const_offset
%= max_offset_plus_one
;
3367 const_offset
/= (size
/ 2u);
3369 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3370 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3372 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3374 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3377 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3382 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3384 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3385 Temp offset
, unsigned bytes_needed
,
3386 unsigned align
, unsigned const_offset
,
3391 if (bytes_needed
<= 4) {
3393 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3394 } else if (bytes_needed
<= 8) {
3396 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3397 } else if (bytes_needed
<= 16) {
3399 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3400 } else if (bytes_needed
<= 32) {
3402 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3405 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3407 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3408 if (info
->resource
.id()) {
3409 load
->operands
[0] = Operand(info
->resource
);
3410 load
->operands
[1] = Operand(offset
);
3412 load
->operands
[0] = Operand(offset
);
3413 load
->operands
[1] = Operand(0u);
3415 RegClass
rc(RegType::sgpr
, size
);
3416 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3417 load
->definitions
[0] = Definition(val
);
3418 load
->glc
= info
->glc
;
3419 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3420 load
->barrier
= info
->barrier
;
3421 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3422 bld
.insert(std::move(load
));
3426 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3428 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3429 Temp offset
, unsigned bytes_needed
,
3430 unsigned align_
, unsigned const_offset
,
3433 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3434 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3436 if (info
->soffset
.id()) {
3437 if (soffset
.isTemp())
3438 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3439 soffset
= Operand(info
->soffset
);
3442 unsigned bytes_size
= 0;
3444 if (bytes_needed
== 1) {
3446 op
= aco_opcode::buffer_load_ubyte
;
3447 } else if (bytes_needed
== 2) {
3449 op
= aco_opcode::buffer_load_ushort
;
3450 } else if (bytes_needed
<= 4) {
3452 op
= aco_opcode::buffer_load_dword
;
3453 } else if (bytes_needed
<= 8) {
3455 op
= aco_opcode::buffer_load_dwordx2
;
3456 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3458 op
= aco_opcode::buffer_load_dwordx3
;
3461 op
= aco_opcode::buffer_load_dwordx4
;
3463 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3464 mubuf
->operands
[0] = Operand(info
->resource
);
3465 mubuf
->operands
[1] = vaddr
;
3466 mubuf
->operands
[2] = soffset
;
3467 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3468 mubuf
->glc
= info
->glc
;
3469 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3470 mubuf
->barrier
= info
->barrier
;
3471 mubuf
->can_reorder
= info
->can_reorder
;
3472 mubuf
->offset
= const_offset
;
3473 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3474 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3475 mubuf
->definitions
[0] = Definition(val
);
3476 bld
.insert(std::move(mubuf
));
3481 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3483 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3485 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3486 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3488 if (addr
.type() == RegType::vgpr
)
3489 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3490 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3493 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3494 Temp offset
, unsigned bytes_needed
,
3495 unsigned align_
, unsigned const_offset
,
3498 unsigned bytes_size
= 0;
3499 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3500 bool global
= bld
.program
->chip_class
>= GFX9
;
3502 if (bytes_needed
== 1) {
3504 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3505 } else if (bytes_needed
== 2) {
3507 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3508 } else if (bytes_needed
<= 4) {
3510 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3511 } else if (bytes_needed
<= 8) {
3513 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3514 } else if (bytes_needed
<= 12 && !mubuf
) {
3516 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3519 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3521 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3522 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3524 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3525 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3526 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3527 mubuf
->operands
[2] = Operand(0u);
3528 mubuf
->glc
= info
->glc
;
3531 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3532 mubuf
->disable_wqm
= false;
3533 mubuf
->barrier
= info
->barrier
;
3534 mubuf
->definitions
[0] = Definition(val
);
3535 bld
.insert(std::move(mubuf
));
3537 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3539 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3540 flat
->operands
[0] = Operand(offset
);
3541 flat
->operands
[1] = Operand(s1
);
3542 flat
->glc
= info
->glc
;
3543 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3544 flat
->barrier
= info
->barrier
;
3546 flat
->definitions
[0] = Definition(val
);
3547 bld
.insert(std::move(flat
));
3553 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3555 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3556 Temp address
, unsigned base_offset
, unsigned align
)
3558 assert(util_is_power_of_two_nonzero(align
));
3560 Builder
bld(ctx
->program
, ctx
->block
);
3562 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3563 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3564 info
.align_mul
= align
;
3565 info
.align_offset
= 0;
3566 info
.barrier
= barrier_shared
;
3567 info
.can_reorder
= false;
3568 info
.const_offset
= base_offset
;
3569 emit_lds_load(ctx
, bld
, &info
);
3574 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3579 Builder
bld(ctx
->program
, ctx
->block
);
3581 ASSERTED
bool is_subdword
= false;
3582 for (unsigned i
= 0; i
< count
; i
++)
3583 is_subdword
|= offsets
[i
] % 4;
3584 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3585 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3587 /* count == 1 fast path */
3589 if (dst_type
== RegType::sgpr
)
3590 dst
[0] = bld
.as_uniform(src
);
3592 dst
[0] = as_vgpr(ctx
, src
);
3596 for (unsigned i
= 0; i
< count
- 1; i
++)
3597 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3598 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3600 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3601 src
= as_vgpr(ctx
, src
);
3603 /* use allocated_vec if possible */
3604 auto it
= ctx
->allocated_vec
.find(src
.id());
3605 if (it
!= ctx
->allocated_vec
.end()) {
3606 unsigned total_size
= 0;
3607 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3608 total_size
+= it
->second
[i
].bytes();
3609 if (total_size
!= src
.bytes())
3612 unsigned elem_size
= it
->second
[0].bytes();
3614 for (unsigned i
= 0; i
< count
; i
++) {
3615 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3619 for (unsigned i
= 0; i
< count
; i
++) {
3620 unsigned start_idx
= offsets
[i
] / elem_size
;
3621 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3622 if (op_count
== 1) {
3623 if (dst_type
== RegType::sgpr
)
3624 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3626 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3630 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3631 for (unsigned j
= 0; j
< op_count
; j
++) {
3632 Temp tmp
= it
->second
[start_idx
+ j
];
3633 if (dst_type
== RegType::sgpr
)
3634 tmp
= bld
.as_uniform(tmp
);
3635 vec
->operands
[j
] = Operand(tmp
);
3637 vec
->definitions
[0] = Definition(dst
[i
]);
3638 bld
.insert(std::move(vec
));
3644 if (dst_type
== RegType::sgpr
)
3645 src
= bld
.as_uniform(src
);
3649 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3650 split
->operands
[0] = Operand(src
);
3651 for (unsigned i
= 0; i
< count
; i
++)
3652 split
->definitions
[i
] = Definition(dst
[i
]);
3653 bld
.insert(std::move(split
));
3656 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3657 int *start
, int *count
)
3659 unsigned start_elem
= ffs(todo_mask
) - 1;
3660 bool skip
= !(mask
& (1 << start_elem
));
3662 mask
= ~mask
& todo_mask
;
3666 u_bit_scan_consecutive_range(&mask
, start
, count
);
3671 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3673 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3676 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3677 Temp address
, unsigned base_offset
, unsigned align
)
3679 assert(util_is_power_of_two_nonzero(align
));
3680 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3682 Builder
bld(ctx
->program
, ctx
->block
);
3683 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3684 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3686 unsigned write_count
= 0;
3687 Temp write_datas
[32];
3688 unsigned offsets
[32];
3689 aco_opcode opcodes
[32];
3691 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3693 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3696 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3697 offsets
[write_count
] = offset
;
3698 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3700 advance_write_mask(&todo
, offset
, bytes
);
3704 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3705 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3706 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3707 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3709 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3710 aco_opcode op
= aco_opcode::num_opcodes
;
3711 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3712 op
= aco_opcode::ds_write_b128
;
3714 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3715 op
= aco_opcode::ds_write_b96
;
3717 } else if (bytes
>= 8 && aligned8
) {
3718 op
= aco_opcode::ds_write_b64
;
3720 } else if (bytes
>= 4 && aligned4
) {
3721 op
= aco_opcode::ds_write_b32
;
3723 } else if (bytes
>= 2 && aligned2
) {
3724 op
= aco_opcode::ds_write_b16
;
3726 } else if (bytes
>= 1) {
3727 op
= aco_opcode::ds_write_b8
;
3733 offsets
[write_count
] = offset
;
3734 opcodes
[write_count
] = op
;
3736 advance_write_mask(&todo
, offset
, bytes
);
3739 Operand m
= load_lds_size_m0(bld
);
3741 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3743 for (unsigned i
= 0; i
< write_count
; i
++) {
3744 aco_opcode op
= opcodes
[i
];
3745 if (op
== aco_opcode::num_opcodes
)
3748 Temp data
= write_datas
[i
];
3750 unsigned second
= write_count
;
3751 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3752 for (second
= i
+ 1; second
< write_count
; second
++) {
3753 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3754 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3755 opcodes
[second
] = aco_opcode::num_opcodes
;
3761 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3762 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3764 unsigned inline_offset
= base_offset
+ offsets
[i
];
3765 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3766 Temp address_offset
= address
;
3767 if (inline_offset
> max_offset
) {
3768 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3769 inline_offset
= offsets
[i
];
3771 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3774 Temp second_data
= write_datas
[second
];
3775 inline_offset
/= data
.bytes();
3776 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3778 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3783 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3785 unsigned align
= 16;
3787 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3793 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3798 return aco_opcode::buffer_store_byte
;
3801 return aco_opcode::buffer_store_short
;
3803 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3805 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3808 return aco_opcode::buffer_store_dwordx3
;
3810 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3812 unreachable("Unexpected store size");
3813 return aco_opcode::num_opcodes
;
3816 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3817 Temp data
, unsigned writemask
, int swizzle_element_size
,
3818 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3820 unsigned write_count_with_skips
= 0;
3823 /* determine how to split the data */
3824 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3827 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3828 offsets
[write_count_with_skips
] = offset
;
3829 if (skips
[write_count_with_skips
]) {
3830 advance_write_mask(&todo
, offset
, bytes
);
3831 write_count_with_skips
++;
3835 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3836 * larger than swizzle_element_size */
3837 bytes
= MIN2(bytes
, swizzle_element_size
);
3839 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3841 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3842 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3845 /* dword or larger stores have to be dword-aligned */
3846 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3847 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3848 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3849 if (bytes
>= 4 && !dword_aligned
)
3850 bytes
= MIN2(bytes
, 2);
3852 advance_write_mask(&todo
, offset
, bytes
);
3853 write_count_with_skips
++;
3856 /* actually split data */
3857 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3860 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3863 write_datas
[*write_count
] = write_datas
[i
];
3864 offsets
[*write_count
] = offsets
[i
];
3869 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3870 unsigned split_cnt
= 0u, Temp dst
= Temp())
3872 Builder
bld(ctx
->program
, ctx
->block
);
3873 unsigned dword_size
= elem_size_bytes
/ 4;
3876 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3878 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3879 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3880 instr
->definitions
[0] = Definition(dst
);
3882 for (unsigned i
= 0; i
< cnt
; ++i
) {
3884 assert(arr
[i
].size() == dword_size
);
3885 allocated_vec
[i
] = arr
[i
];
3886 instr
->operands
[i
] = Operand(arr
[i
]);
3888 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3889 allocated_vec
[i
] = zero
;
3890 instr
->operands
[i
] = Operand(zero
);
3894 bld
.insert(std::move(instr
));
3897 emit_split_vector(ctx
, dst
, split_cnt
);
3899 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3904 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3906 if (const_offset
>= 4096) {
3907 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3908 const_offset
%= 4096u;
3911 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3912 else if (unlikely(voffset
.regClass() == s1
))
3913 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3914 else if (likely(voffset
.regClass() == v1
))
3915 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3917 unreachable("Unsupported register class of voffset");
3920 return const_offset
;
3923 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3924 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3927 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3928 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3930 Builder
bld(ctx
->program
, ctx
->block
);
3931 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3932 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3934 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3935 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3936 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3937 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3938 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3940 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3943 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3944 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3945 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3947 Builder
bld(ctx
->program
, ctx
->block
);
3948 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3950 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3952 unsigned write_count
= 0;
3953 Temp write_datas
[32];
3954 unsigned offsets
[32];
3955 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3956 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3958 for (unsigned i
= 0; i
< write_count
; i
++) {
3959 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3960 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3964 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3965 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3966 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3968 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3969 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3970 assert(!!stride
!= allow_combining
);
3972 Builder
bld(ctx
->program
, ctx
->block
);
3974 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3975 info
.component_stride
= allow_combining
? 0 : stride
;
3977 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3978 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3979 info
.align_offset
= 0;
3980 info
.soffset
= soffset
;
3981 info
.const_offset
= base_const_offset
;
3982 emit_mubuf_load(ctx
, bld
, &info
);
3985 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3987 Builder
bld(ctx
->program
, ctx
->block
);
3988 Temp offset
= base_offset
.first
;
3989 unsigned const_offset
= base_offset
.second
;
3991 if (!nir_src_is_const(*off_src
)) {
3992 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3995 /* Calculate indirect offset with stride */
3996 if (likely(indirect_offset_arg
.regClass() == v1
))
3997 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3998 else if (indirect_offset_arg
.regClass() == s1
)
3999 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4001 unreachable("Unsupported register class of indirect offset");
4003 /* Add to the supplied base offset */
4004 if (offset
.id() == 0)
4005 offset
= with_stride
;
4006 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4007 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4008 else if (offset
.size() == 1 && with_stride
.size() == 1)
4009 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4011 unreachable("Unsupported register class of indirect offset");
4013 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4014 const_offset
+= const_offset_arg
* stride
;
4017 return std::make_pair(offset
, const_offset
);
4020 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4022 Builder
bld(ctx
->program
, ctx
->block
);
4025 if (off1
.first
.id() && off2
.first
.id()) {
4026 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4027 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4028 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4029 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4031 unreachable("Unsupported register class of indirect offset");
4033 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4036 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4039 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4041 Builder
bld(ctx
->program
, ctx
->block
);
4042 unsigned const_offset
= offs
.second
* multiplier
;
4044 if (!offs
.first
.id())
4045 return std::make_pair(offs
.first
, const_offset
);
4047 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4048 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4049 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4051 return std::make_pair(offset
, const_offset
);
4054 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4056 Builder
bld(ctx
->program
, ctx
->block
);
4058 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4059 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4060 /* component is in bytes */
4061 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4063 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4064 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4065 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4068 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4070 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4073 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4075 Builder
bld(ctx
->program
, ctx
->block
);
4077 switch (ctx
->shader
->info
.stage
) {
4078 case MESA_SHADER_TESS_CTRL
:
4079 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4080 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4081 case MESA_SHADER_TESS_EVAL
:
4082 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4084 unreachable("Unsupported stage in get_tess_rel_patch_id");
4088 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4090 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4091 Builder
bld(ctx
->program
, ctx
->block
);
4093 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4094 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4096 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4098 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4099 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4101 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4102 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4103 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4105 return offset_mul(ctx
, offs
, 4u);
4108 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4110 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4111 Builder
bld(ctx
->program
, ctx
->block
);
4113 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4114 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4115 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4116 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4118 std::pair
<Temp
, unsigned> offs
= instr
4119 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4120 : std::make_pair(Temp(), 0u);
4122 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4123 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4128 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4129 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4131 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4132 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4134 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4135 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4141 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4143 Builder
bld(ctx
->program
, ctx
->block
);
4145 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4146 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4148 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4150 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4151 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4152 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4154 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4155 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4160 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4162 Builder
bld(ctx
->program
, ctx
->block
);
4164 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4165 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4166 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4167 unsigned attr_stride
= ctx
->tcs_num_patches
;
4169 std::pair
<Temp
, unsigned> offs
= instr
4170 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4171 : std::make_pair(Temp(), 0u);
4173 if (const_base_offset
)
4174 offs
.second
+= const_base_offset
* attr_stride
;
4176 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4177 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4178 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4183 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4185 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4190 unsigned drv_loc
= nir_intrinsic_base(instr
);
4191 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4193 if (!nir_src_is_const(*off_src
)) {
4199 uint64_t slot
= per_vertex
4200 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4201 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4202 return (((uint64_t) 1) << slot
) & mask
;
4205 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4207 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4208 unsigned component
= nir_intrinsic_component(instr
);
4209 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4211 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4212 if (off_instr
->type
!= nir_instr_type_load_const
)
4215 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4216 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4218 if (instr
->src
[0].ssa
->bit_size
== 64)
4219 write_mask
= widen_mask(write_mask
, 2);
4221 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4223 for (unsigned i
= 0; i
< 8; ++i
) {
4224 if (write_mask
& (1 << i
)) {
4225 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4226 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4234 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4236 /* Only TCS per-vertex inputs are supported by this function.
4237 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4239 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4242 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4243 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4244 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4245 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4246 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4247 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4252 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4253 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4254 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4259 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4261 Builder
bld(ctx
->program
, ctx
->block
);
4263 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4264 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4265 bool indirect_write
;
4266 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4267 if (temp_only_input
&& !indirect_write
)
4271 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4272 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4273 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4274 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4276 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4277 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4278 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4279 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4280 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4284 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4285 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4286 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4287 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4288 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4289 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4290 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4291 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4292 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4293 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4294 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4295 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4296 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4298 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4299 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4301 unreachable("Invalid LS or ES stage");
4304 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4305 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4306 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4310 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4315 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4316 return off
== ctx
->tcs_tess_lvl_out_loc
||
4317 off
== ctx
->tcs_tess_lvl_in_loc
;
4321 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4323 uint64_t mask
= per_vertex
4324 ? ctx
->program
->info
->tcs
.tes_inputs_read
4325 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4327 bool indirect_write
= false;
4328 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4329 return indirect_write
|| output_read_by_tes
;
4332 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4334 uint64_t mask
= per_vertex
4335 ? ctx
->shader
->info
.outputs_read
4336 : ctx
->shader
->info
.patch_outputs_read
;
4338 bool indirect_write
= false;
4339 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4340 return indirect_write
|| output_read
;
4343 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4345 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4346 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4348 Builder
bld(ctx
->program
, ctx
->block
);
4350 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4351 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4352 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4354 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4355 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4356 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4358 if (write_to_vmem
) {
4359 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4360 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4361 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4363 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4364 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4365 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4369 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4370 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4371 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4375 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4377 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4378 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4380 Builder
bld(ctx
->program
, ctx
->block
);
4382 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4383 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4384 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4385 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4387 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4390 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4392 if (ctx
->stage
== vertex_vs
||
4393 ctx
->stage
== tess_eval_vs
||
4394 ctx
->stage
== fragment_fs
||
4395 ctx
->stage
== ngg_vertex_gs
||
4396 ctx
->stage
== ngg_tess_eval_gs
||
4397 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4398 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4399 if (!stored_to_temps
) {
4400 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4401 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4402 fprintf(stderr
, "\n");
4405 } else if (ctx
->stage
== vertex_es
||
4406 ctx
->stage
== vertex_ls
||
4407 ctx
->stage
== tess_eval_es
||
4408 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4409 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4410 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4411 visit_store_ls_or_es_output(ctx
, instr
);
4412 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4413 visit_store_tcs_output(ctx
, instr
, false);
4415 unreachable("Shader stage not implemented");
4419 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4421 visit_load_tcs_output(ctx
, instr
, false);
4424 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4426 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4427 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4429 Builder
bld(ctx
->program
, ctx
->block
);
4431 if (dst
.regClass() == v2b
) {
4432 if (ctx
->program
->has_16bank_lds
) {
4433 assert(ctx
->options
->chip_class
<= GFX8
);
4434 Builder::Result interp_p1
=
4435 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4436 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4437 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4438 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4439 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4440 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4442 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4444 if (ctx
->options
->chip_class
== GFX8
)
4445 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4447 Builder::Result interp_p1
=
4448 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4449 coord1
, bld
.m0(prim_mask
), idx
, component
);
4450 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4451 interp_p1
, idx
, component
);
4454 Builder::Result interp_p1
=
4455 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4456 bld
.m0(prim_mask
), idx
, component
);
4458 if (ctx
->program
->has_16bank_lds
)
4459 interp_p1
.instr
->operands
[0].setLateKill(true);
4461 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4462 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4466 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4468 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4469 for (unsigned i
= 0; i
< num_components
; i
++)
4470 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4471 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4472 assert(num_components
== 4);
4473 Builder
bld(ctx
->program
, ctx
->block
);
4474 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4477 for (Operand
& op
: vec
->operands
)
4478 op
= op
.isUndefined() ? Operand(0u) : op
;
4480 vec
->definitions
[0] = Definition(dst
);
4481 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4482 emit_split_vector(ctx
, dst
, num_components
);
4486 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4488 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4489 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4490 unsigned idx
= nir_intrinsic_base(instr
);
4491 unsigned component
= nir_intrinsic_component(instr
);
4492 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4494 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4496 assert(offset
->u32
== 0);
4498 /* the lower 15bit of the prim_mask contain the offset into LDS
4499 * while the upper bits contain the number of prims */
4500 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4501 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4502 Builder
bld(ctx
->program
, ctx
->block
);
4503 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4504 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4505 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4506 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4507 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4510 if (instr
->dest
.ssa
.num_components
== 1) {
4511 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4513 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4514 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4516 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4517 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4518 vec
->operands
[i
] = Operand(tmp
);
4520 vec
->definitions
[0] = Definition(dst
);
4521 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4525 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4526 unsigned offset
, unsigned stride
, unsigned channels
)
4528 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4529 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4531 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4532 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4535 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4536 unsigned offset
, unsigned stride
, unsigned *channels
)
4538 if (!vtx_info
->chan_byte_size
) {
4539 *channels
= vtx_info
->num_channels
;
4540 return vtx_info
->chan_format
;
4543 unsigned num_channels
= *channels
;
4544 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4545 unsigned new_channels
= num_channels
+ 1;
4546 /* first, assume more loads is worse and try using a larger data format */
4547 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4549 /* don't make the attribute potentially out-of-bounds */
4550 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4554 if (new_channels
== 5) {
4555 /* then try decreasing load size (at the cost of more loads) */
4556 new_channels
= *channels
;
4557 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4561 if (new_channels
< *channels
)
4562 *channels
= new_channels
;
4563 num_channels
= new_channels
;
4566 switch (vtx_info
->chan_format
) {
4567 case V_008F0C_BUF_DATA_FORMAT_8
:
4568 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4569 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4570 case V_008F0C_BUF_DATA_FORMAT_16
:
4571 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4572 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4573 case V_008F0C_BUF_DATA_FORMAT_32
:
4574 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4575 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4577 unreachable("shouldn't reach here");
4578 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4581 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4582 * so we may need to fix it up. */
4583 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4585 Builder
bld(ctx
->program
, ctx
->block
);
4587 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4588 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4590 /* For the integer-like cases, do a natural sign extension.
4592 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4593 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4596 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4597 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4599 /* Convert back to the right type. */
4600 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4601 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4602 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4603 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4604 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4605 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4611 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4613 Builder
bld(ctx
->program
, ctx
->block
);
4614 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4615 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4617 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4618 if (off_instr
->type
!= nir_instr_type_load_const
) {
4619 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4620 nir_print_instr(off_instr
, stderr
);
4621 fprintf(stderr
, "\n");
4623 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4625 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4627 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4628 unsigned component
= nir_intrinsic_component(instr
);
4629 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4630 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4631 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4632 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4633 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4635 unsigned dfmt
= attrib_format
& 0xf;
4636 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4637 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4639 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4640 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4641 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4642 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4644 num_channels
= MAX2(num_channels
, 3);
4646 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4647 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4650 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4651 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4652 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4654 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4656 Temp divided
= bld
.tmp(v1
);
4657 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4658 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4660 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4663 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4666 index
= bld
.vadd32(bld
.def(v1
),
4667 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4668 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4671 Temp channels
[num_channels
];
4672 unsigned channel_start
= 0;
4673 bool direct_fetch
= false;
4675 /* skip unused channels at the start */
4676 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4677 channel_start
= ffs(mask
) - 1;
4678 for (unsigned i
= 0; i
< channel_start
; i
++)
4679 channels
[i
] = Temp(0, s1
);
4680 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4681 num_channels
= 3 - (ffs(mask
) - 1);
4685 while (channel_start
< num_channels
) {
4686 unsigned fetch_component
= num_channels
- channel_start
;
4687 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4688 bool expanded
= false;
4690 /* use MUBUF when possible to avoid possible alignment issues */
4691 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4692 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4693 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4694 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4695 vtx_info
->chan_byte_size
== 4;
4696 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4698 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4700 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4701 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4702 fetch_component
= 4;
4707 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4709 Temp fetch_index
= index
;
4710 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4711 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4712 fetch_offset
= fetch_offset
% attrib_stride
;
4715 Operand
soffset(0u);
4716 if (fetch_offset
>= 4096) {
4717 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4718 fetch_offset
%= 4096;
4722 switch (fetch_bytes
) {
4724 assert(!use_mubuf
&& bitsize
== 16);
4725 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4728 if (bitsize
== 16) {
4730 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4732 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4736 assert(!use_mubuf
&& bitsize
== 16);
4737 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4740 if (bitsize
== 16) {
4742 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4744 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4748 assert(ctx
->options
->chip_class
>= GFX7
||
4749 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4750 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4753 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4756 unreachable("Unimplemented load_input vector size");
4760 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4761 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4762 num_channels
<= 3)) {
4763 direct_fetch
= true;
4766 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4770 Instruction
*mubuf
= bld
.mubuf(opcode
,
4771 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4772 fetch_offset
, false, true).instr
;
4773 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4775 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4776 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4777 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4778 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4781 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4783 if (fetch_component
== 1) {
4784 channels
[channel_start
] = fetch_dst
;
4786 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4787 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4788 bitsize
== 16 ? v2b
: v1
);
4791 channel_start
+= fetch_component
;
4794 if (!direct_fetch
) {
4795 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4796 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4798 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4799 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4800 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4802 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4803 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4804 unsigned num_temp
= 0;
4805 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4806 unsigned idx
= i
+ component
;
4807 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4808 Temp channel
= channels
[swizzle
[idx
]];
4809 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4810 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4811 vec
->operands
[i
] = Operand(channel
);
4815 } else if (is_float
&& idx
== 3) {
4816 vec
->operands
[i
] = Operand(0x3f800000u
);
4817 } else if (!is_float
&& idx
== 3) {
4818 vec
->operands
[i
] = Operand(1u);
4820 vec
->operands
[i
] = Operand(0u);
4823 vec
->definitions
[0] = Definition(dst
);
4824 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4825 emit_split_vector(ctx
, dst
, dst
.size());
4827 if (num_temp
== dst
.size())
4828 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4830 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4831 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4832 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4833 if (off_instr
->type
!= nir_instr_type_load_const
||
4834 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4835 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4836 nir_print_instr(off_instr
, stderr
);
4837 fprintf(stderr
, "\n");
4840 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4841 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4843 assert(offset
->u32
== 0);
4845 /* the lower 15bit of the prim_mask contain the offset into LDS
4846 * while the upper bits contain the number of prims */
4847 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4848 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4849 Builder
bld(ctx
->program
, ctx
->block
);
4850 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4851 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4852 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4853 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4854 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4857 unsigned idx
= nir_intrinsic_base(instr
);
4858 unsigned component
= nir_intrinsic_component(instr
);
4859 unsigned vertex_id
= 2; /* P0 */
4861 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4862 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4863 switch (src0
->u32
) {
4865 vertex_id
= 2; /* P0 */
4868 vertex_id
= 0; /* P10 */
4871 vertex_id
= 1; /* P20 */
4874 unreachable("invalid vertex index");
4878 if (dst
.size() == 1) {
4879 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4881 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4882 for (unsigned i
= 0; i
< dst
.size(); i
++)
4883 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4884 vec
->definitions
[0] = Definition(dst
);
4885 bld
.insert(std::move(vec
));
4888 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4889 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4890 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4891 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4892 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4894 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4896 unreachable("Shader stage not implemented");
4900 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4902 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4904 Builder
bld(ctx
->program
, ctx
->block
);
4905 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4908 if (!nir_src_is_const(*vertex_src
)) {
4909 /* better code could be created, but this case probably doesn't happen
4910 * much in practice */
4911 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4912 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4915 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4916 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4918 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4920 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4923 if (vertex_offset
.id()) {
4924 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4925 Operand(i
), indirect_vertex
);
4926 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4928 vertex_offset
= elem
;
4932 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4933 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4935 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4936 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4937 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4938 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4939 Operand((vertex
% 2u) * 16u), Operand(16u));
4941 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4944 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4945 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4946 return offset_mul(ctx
, offs
, 4u);
4949 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4951 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4953 Builder
bld(ctx
->program
, ctx
->block
);
4954 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4955 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4957 if (ctx
->stage
== geometry_gs
) {
4958 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4959 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4960 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4961 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4962 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4963 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4964 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4966 unreachable("Unsupported GS stage.");
4970 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4972 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4974 Builder
bld(ctx
->program
, ctx
->block
);
4975 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4977 if (load_input_from_temps(ctx
, instr
, dst
))
4980 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4981 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4982 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4984 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4987 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4989 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4991 Builder
bld(ctx
->program
, ctx
->block
);
4993 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4994 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4997 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4998 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5000 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5003 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5005 switch (ctx
->shader
->info
.stage
) {
5006 case MESA_SHADER_GEOMETRY
:
5007 visit_load_gs_per_vertex_input(ctx
, instr
);
5009 case MESA_SHADER_TESS_CTRL
:
5010 visit_load_tcs_per_vertex_input(ctx
, instr
);
5012 case MESA_SHADER_TESS_EVAL
:
5013 visit_load_tes_per_vertex_input(ctx
, instr
);
5016 unreachable("Unimplemented shader stage");
5020 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5022 visit_load_tcs_output(ctx
, instr
, true);
5025 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5027 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5028 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5030 visit_store_tcs_output(ctx
, instr
, true);
5033 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5035 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5037 Builder
bld(ctx
->program
, ctx
->block
);
5038 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5040 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5041 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5044 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5045 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5046 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5047 tes_w
= Operand(tmp
);
5050 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5051 emit_split_vector(ctx
, tess_coord
, 3);
5054 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5056 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5057 Builder
bld(ctx
->program
, ctx
->block
);
5058 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5059 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5060 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5063 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5067 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5069 Builder
bld(ctx
->program
, ctx
->block
);
5070 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5071 if (!nir_dest_is_divergent(instr
->dest
))
5072 index
= bld
.as_uniform(index
);
5073 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5074 unsigned binding
= nir_intrinsic_binding(instr
);
5077 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5078 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5079 unsigned offset
= layout
->binding
[binding
].offset
;
5081 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5082 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5083 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5084 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5085 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5088 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5089 stride
= layout
->binding
[binding
].size
;
5092 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5093 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5095 if (nir_const_index
) {
5096 const_index
= const_index
* stride
;
5097 } else if (index
.type() == RegType::vgpr
) {
5098 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5099 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5101 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5105 if (nir_const_index
) {
5106 const_index
= const_index
+ offset
;
5107 } else if (index
.type() == RegType::vgpr
) {
5108 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5110 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5114 if (nir_const_index
&& const_index
== 0) {
5116 } else if (index
.type() == RegType::vgpr
) {
5117 index
= bld
.vadd32(bld
.def(v1
),
5118 nir_const_index
? Operand(const_index
) : Operand(index
),
5121 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5122 nir_const_index
? Operand(const_index
) : Operand(index
),
5126 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5129 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5130 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5131 bool glc
=false, bool readonly
=true)
5133 Builder
bld(ctx
->program
, ctx
->block
);
5135 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5137 offset
= bld
.as_uniform(offset
);
5139 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5141 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5142 info
.can_reorder
= readonly
;
5143 info
.align_mul
= align_mul
;
5144 info
.align_offset
= align_offset
;
5146 emit_smem_load(ctx
, bld
, &info
);
5148 emit_mubuf_load(ctx
, bld
, &info
);
5151 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5153 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5154 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5156 Builder
bld(ctx
->program
, ctx
->block
);
5158 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5159 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5160 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5161 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5163 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5164 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5165 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5166 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5167 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5168 if (ctx
->options
->chip_class
>= GFX10
) {
5169 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5170 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5171 S_008F0C_RESOURCE_LEVEL(1);
5173 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5174 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5176 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5177 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5178 Operand(0xFFFFFFFFu
),
5179 Operand(desc_type
));
5180 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5181 rsrc
, upper_dwords
);
5183 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5184 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5186 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5187 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5188 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5191 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5193 Builder
bld(ctx
->program
, ctx
->block
);
5194 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5195 unsigned offset
= nir_intrinsic_base(instr
);
5196 unsigned count
= instr
->dest
.ssa
.num_components
;
5197 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5199 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5200 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5201 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5202 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5203 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5204 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5205 for (unsigned i
= 0; i
< count
; ++i
) {
5206 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5207 vec
->operands
[i
] = Operand
{elems
[i
]};
5209 vec
->definitions
[0] = Definition(dst
);
5210 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5211 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5216 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5217 if (offset
!= 0) // TODO check if index != 0 as well
5218 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5219 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5222 bool aligned
= true;
5224 if (instr
->dest
.ssa
.bit_size
== 8) {
5225 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5226 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5228 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5229 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5230 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5232 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5237 switch (vec
.size()) {
5239 op
= aco_opcode::s_load_dword
;
5242 op
= aco_opcode::s_load_dwordx2
;
5248 op
= aco_opcode::s_load_dwordx4
;
5254 op
= aco_opcode::s_load_dwordx8
;
5257 unreachable("unimplemented or forbidden load_push_constant.");
5260 bld
.smem(op
, Definition(vec
), ptr
, index
);
5263 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5264 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5269 emit_split_vector(ctx
, vec
, 4);
5270 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5271 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5272 emit_extract_vector(ctx
, vec
, 0, rc
),
5273 emit_extract_vector(ctx
, vec
, 1, rc
),
5274 emit_extract_vector(ctx
, vec
, 2, rc
));
5277 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5280 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5282 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5284 Builder
bld(ctx
->program
, ctx
->block
);
5286 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5287 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5288 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5289 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5290 if (ctx
->options
->chip_class
>= GFX10
) {
5291 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5292 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5293 S_008F0C_RESOURCE_LEVEL(1);
5295 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5296 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5299 unsigned base
= nir_intrinsic_base(instr
);
5300 unsigned range
= nir_intrinsic_range(instr
);
5302 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5303 if (base
&& offset
.type() == RegType::sgpr
)
5304 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5305 else if (base
&& offset
.type() == RegType::vgpr
)
5306 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5308 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5309 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5310 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5311 Operand(desc_type
));
5312 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5313 // TODO: get alignment information for subdword constants
5314 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5317 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5319 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5320 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5322 ctx
->program
->needs_exact
= true;
5324 // TODO: optimize uniform conditions
5325 Builder
bld(ctx
->program
, ctx
->block
);
5326 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5327 assert(src
.regClass() == bld
.lm
);
5328 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5329 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5330 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5334 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5336 Builder
bld(ctx
->program
, ctx
->block
);
5338 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5339 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5341 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5342 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5344 if (ctx
->block
->loop_nest_depth
&&
5345 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5346 /* we handle discards the same way as jump instructions */
5347 append_logical_end(ctx
->block
);
5349 /* in loops, discard behaves like break */
5350 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5351 ctx
->block
->kind
|= block_kind_discard
;
5354 /* uniform discard - loop ends here */
5355 assert(nir_instr_is_last(&instr
->instr
));
5356 ctx
->block
->kind
|= block_kind_uniform
;
5357 ctx
->cf_info
.has_branch
= true;
5358 bld
.branch(aco_opcode::p_branch
);
5359 add_linear_edge(ctx
->block
->index
, linear_target
);
5363 /* we add a break right behind the discard() instructions */
5364 ctx
->block
->kind
|= block_kind_break
;
5365 unsigned idx
= ctx
->block
->index
;
5367 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5368 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5370 /* remove critical edges from linear CFG */
5371 bld
.branch(aco_opcode::p_branch
);
5372 Block
* break_block
= ctx
->program
->create_and_insert_block();
5373 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5374 break_block
->kind
|= block_kind_uniform
;
5375 add_linear_edge(idx
, break_block
);
5376 add_linear_edge(break_block
->index
, linear_target
);
5377 bld
.reset(break_block
);
5378 bld
.branch(aco_opcode::p_branch
);
5380 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5381 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5382 add_linear_edge(idx
, continue_block
);
5383 append_logical_start(continue_block
);
5384 ctx
->block
= continue_block
;
5389 /* it can currently happen that NIR doesn't remove the unreachable code */
5390 if (!nir_instr_is_last(&instr
->instr
)) {
5391 ctx
->program
->needs_exact
= true;
5392 /* save exec somewhere temporarily so that it doesn't get
5393 * overwritten before the discard from outer exec masks */
5394 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5395 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5396 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5400 /* This condition is incorrect for uniformly branched discards in a loop
5401 * predicated by a divergent condition, but the above code catches that case
5402 * and the discard would end up turning into a discard_if.
5412 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5413 /* program just ends here */
5414 ctx
->block
->kind
|= block_kind_uniform
;
5415 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5416 0 /* enabled mask */, 9 /* dest */,
5417 false /* compressed */, true/* done */, true /* valid mask */);
5418 bld
.sopp(aco_opcode::s_endpgm
);
5419 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5421 ctx
->block
->kind
|= block_kind_discard
;
5422 /* branch and linear edge is added by visit_if() */
5426 enum aco_descriptor_type
{
5437 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5438 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5440 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5441 return dim
== ac_image_cube
||
5442 dim
== ac_image_1darray
||
5443 dim
== ac_image_2darray
||
5444 dim
== ac_image_2darraymsaa
;
5447 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5448 enum aco_descriptor_type desc_type
,
5449 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5451 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5452 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5453 if (it != ctx->tex_desc.end())
5456 Temp index
= Temp();
5457 bool index_set
= false;
5458 unsigned constant_index
= 0;
5459 unsigned descriptor_set
;
5460 unsigned base_index
;
5461 Builder
bld(ctx
->program
, ctx
->block
);
5464 assert(tex_instr
&& !image
);
5466 base_index
= tex_instr
->sampler_index
;
5468 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5469 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5473 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5474 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5476 constant_index
+= array_size
* const_value
->u32
;
5478 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5479 if (indirect
.type() == RegType::vgpr
)
5480 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5482 if (array_size
!= 1)
5483 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5489 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5493 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5495 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5496 base_index
= deref_instr
->var
->data
.binding
;
5499 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5500 list
= convert_pointer_to_64_bit(ctx
, list
);
5502 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5503 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5504 unsigned offset
= binding
->offset
;
5505 unsigned stride
= binding
->size
;
5509 assert(base_index
< layout
->binding_count
);
5511 switch (desc_type
) {
5512 case ACO_DESC_IMAGE
:
5514 opcode
= aco_opcode::s_load_dwordx8
;
5516 case ACO_DESC_FMASK
:
5518 opcode
= aco_opcode::s_load_dwordx8
;
5521 case ACO_DESC_SAMPLER
:
5523 opcode
= aco_opcode::s_load_dwordx4
;
5524 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5525 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5527 case ACO_DESC_BUFFER
:
5529 opcode
= aco_opcode::s_load_dwordx4
;
5531 case ACO_DESC_PLANE_0
:
5532 case ACO_DESC_PLANE_1
:
5534 opcode
= aco_opcode::s_load_dwordx8
;
5535 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5537 case ACO_DESC_PLANE_2
:
5539 opcode
= aco_opcode::s_load_dwordx4
;
5543 unreachable("invalid desc_type\n");
5546 offset
+= constant_index
* stride
;
5548 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5549 (!index_set
|| binding
->immutable_samplers_equal
)) {
5550 if (binding
->immutable_samplers_equal
)
5553 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5554 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5555 Operand(samplers
[constant_index
* 4 + 0]),
5556 Operand(samplers
[constant_index
* 4 + 1]),
5557 Operand(samplers
[constant_index
* 4 + 2]),
5558 Operand(samplers
[constant_index
* 4 + 3]));
5563 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5565 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5566 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5569 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5571 if (desc_type
== ACO_DESC_PLANE_2
) {
5573 for (unsigned i
= 0; i
< 8; i
++)
5574 components
[i
] = bld
.tmp(s1
);
5575 bld
.pseudo(aco_opcode::p_split_vector
,
5576 Definition(components
[0]),
5577 Definition(components
[1]),
5578 Definition(components
[2]),
5579 Definition(components
[3]),
5582 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5583 bld
.pseudo(aco_opcode::p_split_vector
,
5584 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5585 Definition(components
[4]),
5586 Definition(components
[5]),
5587 Definition(components
[6]),
5588 Definition(components
[7]),
5591 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5592 components
[0], components
[1], components
[2], components
[3],
5593 components
[4], components
[5], components
[6], components
[7]);
5599 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5602 case GLSL_SAMPLER_DIM_BUF
:
5604 case GLSL_SAMPLER_DIM_1D
:
5605 return array
? 2 : 1;
5606 case GLSL_SAMPLER_DIM_2D
:
5607 return array
? 3 : 2;
5608 case GLSL_SAMPLER_DIM_MS
:
5609 return array
? 4 : 3;
5610 case GLSL_SAMPLER_DIM_3D
:
5611 case GLSL_SAMPLER_DIM_CUBE
:
5613 case GLSL_SAMPLER_DIM_RECT
:
5614 case GLSL_SAMPLER_DIM_SUBPASS
:
5616 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5625 /* Adjust the sample index according to FMASK.
5627 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5628 * which is the identity mapping. Each nibble says which physical sample
5629 * should be fetched to get that sample.
5631 * For example, 0x11111100 means there are only 2 samples stored and
5632 * the second sample covers 3/4 of the pixel. When reading samples 0
5633 * and 1, return physical sample 0 (determined by the first two 0s
5634 * in FMASK), otherwise return physical sample 1.
5636 * The sample index should be adjusted as follows:
5637 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5639 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5641 Builder
bld(ctx
->program
, ctx
->block
);
5642 Temp fmask
= bld
.tmp(v1
);
5643 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5644 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5647 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5648 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5649 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5650 load
->operands
[0] = Operand(fmask_desc_ptr
);
5651 load
->operands
[1] = Operand(s4
); /* no sampler */
5652 load
->operands
[2] = Operand(coord
);
5653 load
->definitions
[0] = Definition(fmask
);
5660 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5661 ctx
->block
->instructions
.emplace_back(std::move(load
));
5663 Operand sample_index4
;
5664 if (sample_index
.isConstant()) {
5665 if (sample_index
.constantValue() < 16) {
5666 sample_index4
= Operand(sample_index
.constantValue() << 2);
5668 sample_index4
= Operand(0u);
5670 } else if (sample_index
.regClass() == s1
) {
5671 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5673 assert(sample_index
.regClass() == v1
);
5674 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5678 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5679 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5680 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5681 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5683 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5685 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5686 * resource descriptor is 0 (invalid),
5688 Temp compare
= bld
.tmp(bld
.lm
);
5689 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5690 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5692 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5694 /* Replace the MSAA sample index. */
5695 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5698 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5701 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5702 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5703 bool is_array
= glsl_sampler_type_is_array(type
);
5704 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5705 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5706 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5707 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5708 int count
= image_type_to_components_count(dim
, is_array
);
5709 std::vector
<Temp
> coords(count
);
5710 Builder
bld(ctx
->program
, ctx
->block
);
5714 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5715 /* get sample index */
5716 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5717 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5718 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5719 std::vector
<Temp
> fmask_load_address
;
5720 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5721 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5723 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5724 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5726 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5731 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5732 coords
.resize(coords
.size() + 1);
5733 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5735 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5737 for (int i
= 0; i
< count
; i
++)
5738 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5741 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5742 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5743 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5744 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5747 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5750 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5751 for (unsigned i
= 0; i
< coords
.size(); i
++)
5752 vec
->operands
[i
] = Operand(coords
[i
]);
5753 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5754 vec
->definitions
[0] = Definition(res
);
5755 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5760 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5762 Builder
bld(ctx
->program
, ctx
->block
);
5763 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5764 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5765 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5766 bool is_array
= glsl_sampler_type_is_array(type
);
5767 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5769 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5770 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5771 unsigned num_channels
= util_last_bit(mask
);
5772 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5773 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5776 switch (num_channels
) {
5778 opcode
= aco_opcode::buffer_load_format_x
;
5781 opcode
= aco_opcode::buffer_load_format_xy
;
5784 opcode
= aco_opcode::buffer_load_format_xyz
;
5787 opcode
= aco_opcode::buffer_load_format_xyzw
;
5790 unreachable(">4 channel buffer image load");
5792 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5793 load
->operands
[0] = Operand(rsrc
);
5794 load
->operands
[1] = Operand(vindex
);
5795 load
->operands
[2] = Operand((uint32_t) 0);
5797 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5800 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5801 load
->definitions
[0] = Definition(tmp
);
5803 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5804 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5805 load
->barrier
= barrier_image
;
5806 ctx
->block
->instructions
.emplace_back(std::move(load
));
5808 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5812 Temp coords
= get_image_coords(ctx
, instr
, type
);
5813 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5815 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5816 unsigned num_components
= util_bitcount(dmask
);
5818 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5821 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5823 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5824 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5826 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5827 load
->operands
[0] = Operand(resource
);
5828 load
->operands
[1] = Operand(s4
); /* no sampler */
5829 load
->operands
[2] = Operand(coords
);
5830 load
->definitions
[0] = Definition(tmp
);
5831 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5832 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5833 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5834 load
->dmask
= dmask
;
5836 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5837 load
->barrier
= barrier_image
;
5838 ctx
->block
->instructions
.emplace_back(std::move(load
));
5840 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5844 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5846 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5847 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5848 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5849 bool is_array
= glsl_sampler_type_is_array(type
);
5850 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5852 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5854 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5855 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5856 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5858 switch (data
.size()) {
5860 opcode
= aco_opcode::buffer_store_format_x
;
5863 opcode
= aco_opcode::buffer_store_format_xy
;
5866 opcode
= aco_opcode::buffer_store_format_xyz
;
5869 opcode
= aco_opcode::buffer_store_format_xyzw
;
5872 unreachable(">4 channel buffer image store");
5874 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5875 store
->operands
[0] = Operand(rsrc
);
5876 store
->operands
[1] = Operand(vindex
);
5877 store
->operands
[2] = Operand((uint32_t) 0);
5878 store
->operands
[3] = Operand(data
);
5879 store
->idxen
= true;
5882 store
->disable_wqm
= true;
5883 store
->barrier
= barrier_image
;
5884 ctx
->program
->needs_exact
= true;
5885 ctx
->block
->instructions
.emplace_back(std::move(store
));
5889 assert(data
.type() == RegType::vgpr
);
5890 Temp coords
= get_image_coords(ctx
, instr
, type
);
5891 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5893 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5894 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5896 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5897 store
->operands
[0] = Operand(resource
);
5898 store
->operands
[1] = Operand(data
);
5899 store
->operands
[2] = Operand(coords
);
5902 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5903 store
->dmask
= (1 << data
.size()) - 1;
5905 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5906 store
->disable_wqm
= true;
5907 store
->barrier
= barrier_image
;
5908 ctx
->program
->needs_exact
= true;
5909 ctx
->block
->instructions
.emplace_back(std::move(store
));
5913 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5915 /* return the previous value if dest is ever used */
5916 bool return_previous
= false;
5917 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5918 return_previous
= true;
5921 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5922 return_previous
= true;
5926 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5927 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5928 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5929 bool is_array
= glsl_sampler_type_is_array(type
);
5930 Builder
bld(ctx
->program
, ctx
->block
);
5932 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5933 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5935 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5936 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5938 aco_opcode buf_op
, image_op
;
5939 switch (instr
->intrinsic
) {
5940 case nir_intrinsic_image_deref_atomic_add
:
5941 buf_op
= aco_opcode::buffer_atomic_add
;
5942 image_op
= aco_opcode::image_atomic_add
;
5944 case nir_intrinsic_image_deref_atomic_umin
:
5945 buf_op
= aco_opcode::buffer_atomic_umin
;
5946 image_op
= aco_opcode::image_atomic_umin
;
5948 case nir_intrinsic_image_deref_atomic_imin
:
5949 buf_op
= aco_opcode::buffer_atomic_smin
;
5950 image_op
= aco_opcode::image_atomic_smin
;
5952 case nir_intrinsic_image_deref_atomic_umax
:
5953 buf_op
= aco_opcode::buffer_atomic_umax
;
5954 image_op
= aco_opcode::image_atomic_umax
;
5956 case nir_intrinsic_image_deref_atomic_imax
:
5957 buf_op
= aco_opcode::buffer_atomic_smax
;
5958 image_op
= aco_opcode::image_atomic_smax
;
5960 case nir_intrinsic_image_deref_atomic_and
:
5961 buf_op
= aco_opcode::buffer_atomic_and
;
5962 image_op
= aco_opcode::image_atomic_and
;
5964 case nir_intrinsic_image_deref_atomic_or
:
5965 buf_op
= aco_opcode::buffer_atomic_or
;
5966 image_op
= aco_opcode::image_atomic_or
;
5968 case nir_intrinsic_image_deref_atomic_xor
:
5969 buf_op
= aco_opcode::buffer_atomic_xor
;
5970 image_op
= aco_opcode::image_atomic_xor
;
5972 case nir_intrinsic_image_deref_atomic_exchange
:
5973 buf_op
= aco_opcode::buffer_atomic_swap
;
5974 image_op
= aco_opcode::image_atomic_swap
;
5976 case nir_intrinsic_image_deref_atomic_comp_swap
:
5977 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5978 image_op
= aco_opcode::image_atomic_cmpswap
;
5981 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5984 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5986 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5987 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5988 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5989 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5990 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5991 mubuf
->operands
[0] = Operand(resource
);
5992 mubuf
->operands
[1] = Operand(vindex
);
5993 mubuf
->operands
[2] = Operand((uint32_t)0);
5994 mubuf
->operands
[3] = Operand(data
);
5995 if (return_previous
)
5996 mubuf
->definitions
[0] = Definition(dst
);
5998 mubuf
->idxen
= true;
5999 mubuf
->glc
= return_previous
;
6000 mubuf
->dlc
= false; /* Not needed for atomics */
6001 mubuf
->disable_wqm
= true;
6002 mubuf
->barrier
= barrier_image
;
6003 ctx
->program
->needs_exact
= true;
6004 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6008 Temp coords
= get_image_coords(ctx
, instr
, type
);
6009 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6010 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6011 mimg
->operands
[0] = Operand(resource
);
6012 mimg
->operands
[1] = Operand(data
);
6013 mimg
->operands
[2] = Operand(coords
);
6014 if (return_previous
)
6015 mimg
->definitions
[0] = Definition(dst
);
6016 mimg
->glc
= return_previous
;
6017 mimg
->dlc
= false; /* Not needed for atomics */
6018 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6019 mimg
->dmask
= (1 << data
.size()) - 1;
6021 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6022 mimg
->disable_wqm
= true;
6023 mimg
->barrier
= barrier_image
;
6024 ctx
->program
->needs_exact
= true;
6025 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6029 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6031 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6032 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6033 Builder
bld(ctx
->program
, ctx
->block
);
6035 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6037 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6038 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6040 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6041 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6043 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6044 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6046 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6047 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6048 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6049 if (dst
.type() == RegType::vgpr
)
6050 bld
.copy(Definition(dst
), shr_dst
);
6052 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6054 emit_extract_vector(ctx
, desc
, 2, dst
);
6058 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6060 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6061 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6062 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6063 bool is_array
= glsl_sampler_type_is_array(type
);
6064 Builder
bld(ctx
->program
, ctx
->block
);
6066 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6067 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6068 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6072 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6075 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6077 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6079 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6080 mimg
->operands
[0] = Operand(resource
);
6081 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6082 mimg
->operands
[2] = Operand(lod
);
6083 uint8_t& dmask
= mimg
->dmask
;
6084 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6085 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6086 mimg
->da
= glsl_sampler_type_is_array(type
);
6087 mimg
->can_reorder
= true;
6088 Definition
& def
= mimg
->definitions
[0];
6089 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6091 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6092 glsl_sampler_type_is_array(type
)) {
6094 assert(instr
->dest
.ssa
.num_components
== 3);
6095 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6096 def
= Definition(tmp
);
6097 emit_split_vector(ctx
, tmp
, 3);
6099 /* divide 3rd value by 6 by multiplying with magic number */
6100 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6101 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6104 emit_extract_vector(ctx
, tmp
, 0, v1
),
6105 emit_extract_vector(ctx
, tmp
, 1, v1
),
6108 } else if (ctx
->options
->chip_class
== GFX9
&&
6109 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6110 glsl_sampler_type_is_array(type
)) {
6111 assert(instr
->dest
.ssa
.num_components
== 2);
6112 def
= Definition(dst
);
6115 def
= Definition(dst
);
6118 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6121 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6123 Builder
bld(ctx
->program
, ctx
->block
);
6124 unsigned num_components
= instr
->num_components
;
6126 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6127 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6128 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6130 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6131 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6132 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6133 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6136 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6138 Builder
bld(ctx
->program
, ctx
->block
);
6139 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6140 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6141 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6142 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6144 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6145 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6147 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6148 ctx
->options
->chip_class
>= GFX8
&&
6149 elem_size_bytes
>= 4;
6151 offset
= bld
.as_uniform(offset
);
6152 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6154 unsigned write_count
= 0;
6155 Temp write_datas
[32];
6156 unsigned offsets
[32];
6157 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6158 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6160 for (unsigned i
= 0; i
< write_count
; i
++) {
6161 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6162 if (smem
&& ctx
->stage
== fragment_fs
)
6163 op
= aco_opcode::p_fs_buffer_store_smem
;
6166 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6167 store
->operands
[0] = Operand(rsrc
);
6169 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6170 offset
, Operand(offsets
[i
]));
6171 store
->operands
[1] = Operand(off
);
6173 store
->operands
[1] = Operand(offset
);
6175 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6176 store
->operands
[1].setFixed(m0
);
6177 store
->operands
[2] = Operand(write_datas
[i
]);
6178 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6180 store
->disable_wqm
= true;
6181 store
->barrier
= barrier_buffer
;
6182 ctx
->block
->instructions
.emplace_back(std::move(store
));
6183 ctx
->program
->wb_smem_l1_on_end
= true;
6184 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6185 ctx
->block
->kind
|= block_kind_needs_lowering
;
6186 ctx
->program
->needs_exact
= true;
6189 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6190 store
->operands
[0] = Operand(rsrc
);
6191 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6192 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6193 store
->operands
[3] = Operand(write_datas
[i
]);
6194 store
->offset
= offsets
[i
];
6195 store
->offen
= (offset
.type() == RegType::vgpr
);
6196 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6198 store
->disable_wqm
= true;
6199 store
->barrier
= barrier_buffer
;
6200 ctx
->program
->needs_exact
= true;
6201 ctx
->block
->instructions
.emplace_back(std::move(store
));
6206 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6208 /* return the previous value if dest is ever used */
6209 bool return_previous
= false;
6210 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6211 return_previous
= true;
6214 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6215 return_previous
= true;
6219 Builder
bld(ctx
->program
, ctx
->block
);
6220 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6222 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6223 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6224 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6226 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6227 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6228 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6230 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6232 aco_opcode op32
, op64
;
6233 switch (instr
->intrinsic
) {
6234 case nir_intrinsic_ssbo_atomic_add
:
6235 op32
= aco_opcode::buffer_atomic_add
;
6236 op64
= aco_opcode::buffer_atomic_add_x2
;
6238 case nir_intrinsic_ssbo_atomic_imin
:
6239 op32
= aco_opcode::buffer_atomic_smin
;
6240 op64
= aco_opcode::buffer_atomic_smin_x2
;
6242 case nir_intrinsic_ssbo_atomic_umin
:
6243 op32
= aco_opcode::buffer_atomic_umin
;
6244 op64
= aco_opcode::buffer_atomic_umin_x2
;
6246 case nir_intrinsic_ssbo_atomic_imax
:
6247 op32
= aco_opcode::buffer_atomic_smax
;
6248 op64
= aco_opcode::buffer_atomic_smax_x2
;
6250 case nir_intrinsic_ssbo_atomic_umax
:
6251 op32
= aco_opcode::buffer_atomic_umax
;
6252 op64
= aco_opcode::buffer_atomic_umax_x2
;
6254 case nir_intrinsic_ssbo_atomic_and
:
6255 op32
= aco_opcode::buffer_atomic_and
;
6256 op64
= aco_opcode::buffer_atomic_and_x2
;
6258 case nir_intrinsic_ssbo_atomic_or
:
6259 op32
= aco_opcode::buffer_atomic_or
;
6260 op64
= aco_opcode::buffer_atomic_or_x2
;
6262 case nir_intrinsic_ssbo_atomic_xor
:
6263 op32
= aco_opcode::buffer_atomic_xor
;
6264 op64
= aco_opcode::buffer_atomic_xor_x2
;
6266 case nir_intrinsic_ssbo_atomic_exchange
:
6267 op32
= aco_opcode::buffer_atomic_swap
;
6268 op64
= aco_opcode::buffer_atomic_swap_x2
;
6270 case nir_intrinsic_ssbo_atomic_comp_swap
:
6271 op32
= aco_opcode::buffer_atomic_cmpswap
;
6272 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6275 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6277 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6278 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6279 mubuf
->operands
[0] = Operand(rsrc
);
6280 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6281 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6282 mubuf
->operands
[3] = Operand(data
);
6283 if (return_previous
)
6284 mubuf
->definitions
[0] = Definition(dst
);
6286 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6287 mubuf
->glc
= return_previous
;
6288 mubuf
->dlc
= false; /* Not needed for atomics */
6289 mubuf
->disable_wqm
= true;
6290 mubuf
->barrier
= barrier_buffer
;
6291 ctx
->program
->needs_exact
= true;
6292 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6295 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6297 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6298 Builder
bld(ctx
->program
, ctx
->block
);
6299 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6300 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6303 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6305 Builder
bld(ctx
->program
, ctx
->block
);
6306 unsigned num_components
= instr
->num_components
;
6307 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6309 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6310 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6311 num_components
, component_size
};
6312 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6313 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6314 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6315 info
.barrier
= barrier_buffer
;
6316 info
.can_reorder
= false;
6317 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6318 * it's safe to use SMEM */
6319 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6320 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6321 emit_global_load(ctx
, bld
, &info
);
6323 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6324 emit_smem_load(ctx
, bld
, &info
);
6328 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6330 Builder
bld(ctx
->program
, ctx
->block
);
6331 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6332 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6334 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6335 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6336 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6338 if (ctx
->options
->chip_class
>= GFX7
)
6339 addr
= as_vgpr(ctx
, addr
);
6341 unsigned write_count
= 0;
6342 Temp write_datas
[32];
6343 unsigned offsets
[32];
6344 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6345 16, &write_count
, write_datas
, offsets
);
6347 for (unsigned i
= 0; i
< write_count
; i
++) {
6348 if (ctx
->options
->chip_class
>= GFX7
) {
6349 unsigned offset
= offsets
[i
];
6350 Temp store_addr
= addr
;
6351 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6352 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6353 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6354 Temp carry
= bld
.tmp(bld
.lm
);
6355 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6357 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6358 Operand(offset
), addr0
);
6359 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6361 carry
).def(1).setHint(vcc
);
6363 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6368 bool global
= ctx
->options
->chip_class
>= GFX9
;
6370 switch (write_datas
[i
].bytes()) {
6372 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6375 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6378 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6381 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6384 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6387 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6390 unreachable("store_global not implemented for this size.");
6393 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6394 flat
->operands
[0] = Operand(store_addr
);
6395 flat
->operands
[1] = Operand(s1
);
6396 flat
->operands
[2] = Operand(write_datas
[i
]);
6399 flat
->offset
= offset
;
6400 flat
->disable_wqm
= true;
6401 flat
->barrier
= barrier_buffer
;
6402 ctx
->program
->needs_exact
= true;
6403 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6405 assert(ctx
->options
->chip_class
== GFX6
);
6407 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6409 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6411 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6412 mubuf
->operands
[0] = Operand(rsrc
);
6413 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6414 mubuf
->operands
[2] = Operand(0u);
6415 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6418 mubuf
->offset
= offsets
[i
];
6419 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6420 mubuf
->disable_wqm
= true;
6421 mubuf
->barrier
= barrier_buffer
;
6422 ctx
->program
->needs_exact
= true;
6423 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6428 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6430 /* return the previous value if dest is ever used */
6431 bool return_previous
= false;
6432 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6433 return_previous
= true;
6436 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6437 return_previous
= true;
6441 Builder
bld(ctx
->program
, ctx
->block
);
6442 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6443 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6445 if (ctx
->options
->chip_class
>= GFX7
)
6446 addr
= as_vgpr(ctx
, addr
);
6448 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6449 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6450 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6452 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6454 aco_opcode op32
, op64
;
6456 if (ctx
->options
->chip_class
>= GFX7
) {
6457 bool global
= ctx
->options
->chip_class
>= GFX9
;
6458 switch (instr
->intrinsic
) {
6459 case nir_intrinsic_global_atomic_add
:
6460 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6461 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6463 case nir_intrinsic_global_atomic_imin
:
6464 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6465 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6467 case nir_intrinsic_global_atomic_umin
:
6468 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6469 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6471 case nir_intrinsic_global_atomic_imax
:
6472 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6473 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6475 case nir_intrinsic_global_atomic_umax
:
6476 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6477 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6479 case nir_intrinsic_global_atomic_and
:
6480 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6481 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6483 case nir_intrinsic_global_atomic_or
:
6484 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6485 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6487 case nir_intrinsic_global_atomic_xor
:
6488 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6489 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6491 case nir_intrinsic_global_atomic_exchange
:
6492 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6493 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6495 case nir_intrinsic_global_atomic_comp_swap
:
6496 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6497 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6500 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6503 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6504 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6505 flat
->operands
[0] = Operand(addr
);
6506 flat
->operands
[1] = Operand(s1
);
6507 flat
->operands
[2] = Operand(data
);
6508 if (return_previous
)
6509 flat
->definitions
[0] = Definition(dst
);
6510 flat
->glc
= return_previous
;
6511 flat
->dlc
= false; /* Not needed for atomics */
6513 flat
->disable_wqm
= true;
6514 flat
->barrier
= barrier_buffer
;
6515 ctx
->program
->needs_exact
= true;
6516 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6518 assert(ctx
->options
->chip_class
== GFX6
);
6520 switch (instr
->intrinsic
) {
6521 case nir_intrinsic_global_atomic_add
:
6522 op32
= aco_opcode::buffer_atomic_add
;
6523 op64
= aco_opcode::buffer_atomic_add_x2
;
6525 case nir_intrinsic_global_atomic_imin
:
6526 op32
= aco_opcode::buffer_atomic_smin
;
6527 op64
= aco_opcode::buffer_atomic_smin_x2
;
6529 case nir_intrinsic_global_atomic_umin
:
6530 op32
= aco_opcode::buffer_atomic_umin
;
6531 op64
= aco_opcode::buffer_atomic_umin_x2
;
6533 case nir_intrinsic_global_atomic_imax
:
6534 op32
= aco_opcode::buffer_atomic_smax
;
6535 op64
= aco_opcode::buffer_atomic_smax_x2
;
6537 case nir_intrinsic_global_atomic_umax
:
6538 op32
= aco_opcode::buffer_atomic_umax
;
6539 op64
= aco_opcode::buffer_atomic_umax_x2
;
6541 case nir_intrinsic_global_atomic_and
:
6542 op32
= aco_opcode::buffer_atomic_and
;
6543 op64
= aco_opcode::buffer_atomic_and_x2
;
6545 case nir_intrinsic_global_atomic_or
:
6546 op32
= aco_opcode::buffer_atomic_or
;
6547 op64
= aco_opcode::buffer_atomic_or_x2
;
6549 case nir_intrinsic_global_atomic_xor
:
6550 op32
= aco_opcode::buffer_atomic_xor
;
6551 op64
= aco_opcode::buffer_atomic_xor_x2
;
6553 case nir_intrinsic_global_atomic_exchange
:
6554 op32
= aco_opcode::buffer_atomic_swap
;
6555 op64
= aco_opcode::buffer_atomic_swap_x2
;
6557 case nir_intrinsic_global_atomic_comp_swap
:
6558 op32
= aco_opcode::buffer_atomic_cmpswap
;
6559 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6562 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6565 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6567 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6569 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6570 mubuf
->operands
[0] = Operand(rsrc
);
6571 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6572 mubuf
->operands
[2] = Operand(0u);
6573 mubuf
->operands
[3] = Operand(data
);
6574 if (return_previous
)
6575 mubuf
->definitions
[0] = Definition(dst
);
6576 mubuf
->glc
= return_previous
;
6579 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6580 mubuf
->disable_wqm
= true;
6581 mubuf
->barrier
= barrier_buffer
;
6582 ctx
->program
->needs_exact
= true;
6583 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6587 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6588 Builder
bld(ctx
->program
, ctx
->block
);
6589 switch(instr
->intrinsic
) {
6590 case nir_intrinsic_group_memory_barrier
:
6591 case nir_intrinsic_memory_barrier
:
6592 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6594 case nir_intrinsic_memory_barrier_buffer
:
6595 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6597 case nir_intrinsic_memory_barrier_image
:
6598 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6600 case nir_intrinsic_memory_barrier_tcs_patch
:
6601 case nir_intrinsic_memory_barrier_shared
:
6602 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6605 unreachable("Unimplemented memory barrier intrinsic");
6610 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6612 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6613 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6614 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6615 Builder
bld(ctx
->program
, ctx
->block
);
6617 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6618 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6619 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6622 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6624 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6625 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6626 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6627 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6629 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6630 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6633 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6635 unsigned offset
= nir_intrinsic_base(instr
);
6636 Builder
bld(ctx
->program
, ctx
->block
);
6637 Operand m
= load_lds_size_m0(bld
);
6638 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6639 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6641 unsigned num_operands
= 3;
6642 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6643 switch(instr
->intrinsic
) {
6644 case nir_intrinsic_shared_atomic_add
:
6645 op32
= aco_opcode::ds_add_u32
;
6646 op64
= aco_opcode::ds_add_u64
;
6647 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6648 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6650 case nir_intrinsic_shared_atomic_imin
:
6651 op32
= aco_opcode::ds_min_i32
;
6652 op64
= aco_opcode::ds_min_i64
;
6653 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6654 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6656 case nir_intrinsic_shared_atomic_umin
:
6657 op32
= aco_opcode::ds_min_u32
;
6658 op64
= aco_opcode::ds_min_u64
;
6659 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6660 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6662 case nir_intrinsic_shared_atomic_imax
:
6663 op32
= aco_opcode::ds_max_i32
;
6664 op64
= aco_opcode::ds_max_i64
;
6665 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6666 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6668 case nir_intrinsic_shared_atomic_umax
:
6669 op32
= aco_opcode::ds_max_u32
;
6670 op64
= aco_opcode::ds_max_u64
;
6671 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6672 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6674 case nir_intrinsic_shared_atomic_and
:
6675 op32
= aco_opcode::ds_and_b32
;
6676 op64
= aco_opcode::ds_and_b64
;
6677 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6678 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6680 case nir_intrinsic_shared_atomic_or
:
6681 op32
= aco_opcode::ds_or_b32
;
6682 op64
= aco_opcode::ds_or_b64
;
6683 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6684 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6686 case nir_intrinsic_shared_atomic_xor
:
6687 op32
= aco_opcode::ds_xor_b32
;
6688 op64
= aco_opcode::ds_xor_b64
;
6689 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6690 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6692 case nir_intrinsic_shared_atomic_exchange
:
6693 op32
= aco_opcode::ds_write_b32
;
6694 op64
= aco_opcode::ds_write_b64
;
6695 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6696 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6698 case nir_intrinsic_shared_atomic_comp_swap
:
6699 op32
= aco_opcode::ds_cmpst_b32
;
6700 op64
= aco_opcode::ds_cmpst_b64
;
6701 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6702 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6706 unreachable("Unhandled shared atomic intrinsic");
6709 /* return the previous value if dest is ever used */
6710 bool return_previous
= false;
6711 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6712 return_previous
= true;
6715 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6716 return_previous
= true;
6721 if (data
.size() == 1) {
6722 assert(instr
->dest
.ssa
.bit_size
== 32);
6723 op
= return_previous
? op32_rtn
: op32
;
6725 assert(instr
->dest
.ssa
.bit_size
== 64);
6726 op
= return_previous
? op64_rtn
: op64
;
6729 if (offset
> 65535) {
6730 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6734 aco_ptr
<DS_instruction
> ds
;
6735 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6736 ds
->operands
[0] = Operand(address
);
6737 ds
->operands
[1] = Operand(data
);
6738 if (num_operands
== 4)
6739 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6740 ds
->operands
[num_operands
- 1] = m
;
6741 ds
->offset0
= offset
;
6742 if (return_previous
)
6743 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6744 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6747 Temp
get_scratch_resource(isel_context
*ctx
)
6749 Builder
bld(ctx
->program
, ctx
->block
);
6750 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6751 if (ctx
->stage
!= compute_cs
)
6752 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6754 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6755 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6757 if (ctx
->program
->chip_class
>= GFX10
) {
6758 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6759 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6760 S_008F0C_RESOURCE_LEVEL(1);
6761 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6762 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6763 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6766 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6767 if (ctx
->program
->chip_class
<= GFX8
)
6768 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6770 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6773 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6774 Builder
bld(ctx
->program
, ctx
->block
);
6775 Temp rsrc
= get_scratch_resource(ctx
);
6776 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6777 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6779 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6780 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6781 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6782 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6783 info
.swizzle_component_size
= 16;
6784 info
.can_reorder
= false;
6785 info
.soffset
= ctx
->program
->scratch_offset
;
6786 emit_mubuf_load(ctx
, bld
, &info
);
6789 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6790 Builder
bld(ctx
->program
, ctx
->block
);
6791 Temp rsrc
= get_scratch_resource(ctx
);
6792 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6793 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6795 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6796 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6798 unsigned write_count
= 0;
6799 Temp write_datas
[32];
6800 unsigned offsets
[32];
6801 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6802 16, &write_count
, write_datas
, offsets
);
6804 for (unsigned i
= 0; i
< write_count
; i
++) {
6805 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6806 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6810 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6811 uint8_t log2_ps_iter_samples
;
6812 if (ctx
->program
->info
->ps
.force_persample
) {
6813 log2_ps_iter_samples
=
6814 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6816 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6819 /* The bit pattern matches that used by fixed function fragment
6821 static const unsigned ps_iter_masks
[] = {
6822 0xffff, /* not used */
6828 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6830 Builder
bld(ctx
->program
, ctx
->block
);
6832 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6833 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6834 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6835 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6836 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6837 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6840 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6841 Builder
bld(ctx
->program
, ctx
->block
);
6843 unsigned stream
= nir_intrinsic_stream_id(instr
);
6844 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6845 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6846 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6849 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6851 unsigned num_components
=
6852 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6853 assert(num_components
);
6855 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6856 unsigned stream_offset
= 0;
6857 for (unsigned i
= 0; i
< stream
; i
++) {
6858 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6859 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6862 /* Limit on the stride field for <= GFX7. */
6863 assert(stride
< (1 << 14));
6865 Temp gsvs_dwords
[4];
6866 for (unsigned i
= 0; i
< 4; i
++)
6867 gsvs_dwords
[i
] = bld
.tmp(s1
);
6868 bld
.pseudo(aco_opcode::p_split_vector
,
6869 Definition(gsvs_dwords
[0]),
6870 Definition(gsvs_dwords
[1]),
6871 Definition(gsvs_dwords
[2]),
6872 Definition(gsvs_dwords
[3]),
6875 if (stream_offset
) {
6876 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6878 Temp carry
= bld
.tmp(s1
);
6879 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6880 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6883 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6884 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6886 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6887 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6889 unsigned offset
= 0;
6890 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6891 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6894 for (unsigned j
= 0; j
< 4; j
++) {
6895 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6898 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6899 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6900 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6901 if (const_offset
>= 4096u) {
6902 if (vaddr_offset
.isUndefined())
6903 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6905 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6906 const_offset
%= 4096u;
6909 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6910 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6911 mtbuf
->operands
[1] = vaddr_offset
;
6912 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6913 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6914 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6915 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6916 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6917 mtbuf
->offset
= const_offset
;
6920 mtbuf
->barrier
= barrier_gs_data
;
6921 mtbuf
->can_reorder
= true;
6922 bld
.insert(std::move(mtbuf
));
6925 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6928 /* outputs for the next vertex are undefined and keeping them around can
6929 * create invalid IR with control flow */
6930 ctx
->outputs
.mask
[i
] = 0;
6933 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6936 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6938 Builder
bld(ctx
->program
, ctx
->block
);
6940 if (cluster_size
== 1) {
6942 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6943 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6944 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6945 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6946 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6947 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6948 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6949 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6950 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6951 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6952 //subgroupAnd(val) -> (exec & ~val) == 0
6953 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6954 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6955 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6956 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6957 //subgroupOr(val) -> (val & exec) != 0
6958 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6959 return bool_to_vector_condition(ctx
, tmp
);
6960 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6961 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6962 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6963 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6964 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6965 return bool_to_vector_condition(ctx
, tmp
);
6967 //subgroupClustered{And,Or,Xor}(val, n) ->
6968 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6969 //cluster_offset = ~(n - 1) & lane_id
6970 //cluster_mask = ((1 << n) - 1)
6971 //subgroupClusteredAnd():
6972 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6973 //subgroupClusteredOr():
6974 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6975 //subgroupClusteredXor():
6976 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6977 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6978 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6981 if (op
== nir_op_iand
)
6982 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6984 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6986 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6988 if (ctx
->program
->chip_class
<= GFX7
)
6989 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6990 else if (ctx
->program
->wave_size
== 64)
6991 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6993 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6994 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6995 if (cluster_mask
!= 0xffffffff)
6996 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6998 Definition cmp_def
= Definition();
6999 if (op
== nir_op_iand
) {
7000 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7001 } else if (op
== nir_op_ior
) {
7002 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7003 } else if (op
== nir_op_ixor
) {
7004 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7005 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7006 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7008 cmp_def
.setHint(vcc
);
7009 return cmp_def
.getTemp();
7013 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7015 Builder
bld(ctx
->program
, ctx
->block
);
7017 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7018 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7019 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7021 if (op
== nir_op_iand
)
7022 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7024 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7026 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7027 Temp lo
= lohi
.def(0).getTemp();
7028 Temp hi
= lohi
.def(1).getTemp();
7029 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7031 Definition cmp_def
= Definition();
7032 if (op
== nir_op_iand
)
7033 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7034 else if (op
== nir_op_ior
)
7035 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7036 else if (op
== nir_op_ixor
)
7037 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7038 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7039 cmp_def
.setHint(vcc
);
7040 return cmp_def
.getTemp();
7043 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7045 Builder
bld(ctx
->program
, ctx
->block
);
7047 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7048 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7049 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7050 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7051 if (op
== nir_op_iand
)
7052 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7053 else if (op
== nir_op_ior
)
7054 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7055 else if (op
== nir_op_ixor
)
7056 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7062 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7064 Builder
bld(ctx
->program
, ctx
->block
);
7065 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7066 if (src
.regClass().type() == RegType::vgpr
) {
7067 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7068 } else if (src
.regClass() == s1
) {
7069 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7070 } else if (src
.regClass() == s2
) {
7071 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7074 nir_print_instr(&instr
->instr
, stderr
);
7075 fprintf(stderr
, "\n");
7079 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7081 Builder
bld(ctx
->program
, ctx
->block
);
7082 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7083 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7084 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7086 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7087 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7088 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7089 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7092 if (ctx
->program
->chip_class
>= GFX8
) {
7093 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7094 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7095 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7096 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7097 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7098 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7100 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7101 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7102 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7103 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7104 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7105 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7106 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7107 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7108 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7109 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7112 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7113 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7114 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7115 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7116 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7117 Temp wqm1
= bld
.tmp(v1
);
7118 emit_wqm(ctx
, tmp1
, wqm1
, true);
7119 Temp wqm2
= bld
.tmp(v1
);
7120 emit_wqm(ctx
, tmp2
, wqm2
, true);
7121 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7125 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7127 Builder
bld(ctx
->program
, ctx
->block
);
7128 switch(instr
->intrinsic
) {
7129 case nir_intrinsic_load_barycentric_sample
:
7130 case nir_intrinsic_load_barycentric_pixel
:
7131 case nir_intrinsic_load_barycentric_centroid
: {
7132 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7133 Temp bary
= Temp(0, s2
);
7135 case INTERP_MODE_SMOOTH
:
7136 case INTERP_MODE_NONE
:
7137 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7138 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7139 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7140 bary
= ctx
->persp_centroid
;
7141 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7142 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7144 case INTERP_MODE_NOPERSPECTIVE
:
7145 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7146 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7147 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7148 bary
= ctx
->linear_centroid
;
7149 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7150 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7155 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7156 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7157 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7159 Operand(p1
), Operand(p2
));
7160 emit_split_vector(ctx
, dst
, 2);
7163 case nir_intrinsic_load_barycentric_model
: {
7164 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7166 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7167 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7168 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7169 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7170 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7171 Operand(p1
), Operand(p2
), Operand(p3
));
7172 emit_split_vector(ctx
, dst
, 3);
7175 case nir_intrinsic_load_barycentric_at_sample
: {
7176 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7177 switch (ctx
->options
->key
.fs
.num_samples
) {
7178 case 2: sample_pos_offset
+= 1 << 3; break;
7179 case 4: sample_pos_offset
+= 3 << 3; break;
7180 case 8: sample_pos_offset
+= 7 << 3; break;
7184 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7185 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7186 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7187 if (addr
.type() == RegType::sgpr
) {
7190 sample_pos_offset
+= const_addr
->u32
<< 3;
7191 offset
= Operand(sample_pos_offset
);
7192 } else if (ctx
->options
->chip_class
>= GFX9
) {
7193 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7195 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7196 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7199 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7200 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7202 } else if (ctx
->options
->chip_class
>= GFX9
) {
7203 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7204 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7205 } else if (ctx
->options
->chip_class
>= GFX7
) {
7206 /* addr += private_segment_buffer + sample_pos_offset */
7207 Temp tmp0
= bld
.tmp(s1
);
7208 Temp tmp1
= bld
.tmp(s1
);
7209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7210 Definition scc_tmp
= bld
.def(s1
, scc
);
7211 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7212 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7213 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7214 Temp pck0
= bld
.tmp(v1
);
7215 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7216 tmp1
= as_vgpr(ctx
, tmp1
);
7217 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7218 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7220 /* sample_pos = flat_load_dwordx2 addr */
7221 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7223 assert(ctx
->options
->chip_class
== GFX6
);
7225 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7227 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7229 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7230 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7232 sample_pos
= bld
.tmp(v2
);
7234 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7235 load
->definitions
[0] = Definition(sample_pos
);
7236 load
->operands
[0] = Operand(rsrc
);
7237 load
->operands
[1] = Operand(addr
);
7238 load
->operands
[2] = Operand(0u);
7239 load
->offset
= sample_pos_offset
;
7241 load
->addr64
= true;
7244 load
->disable_wqm
= false;
7245 load
->barrier
= barrier_none
;
7246 load
->can_reorder
= true;
7247 ctx
->block
->instructions
.emplace_back(std::move(load
));
7250 /* sample_pos -= 0.5 */
7251 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7252 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7253 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7254 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7255 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7257 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7260 case nir_intrinsic_load_barycentric_at_offset
: {
7261 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7262 RegClass rc
= RegClass(offset
.type(), 1);
7263 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7264 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7265 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7268 case nir_intrinsic_load_front_face
: {
7269 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7270 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7273 case nir_intrinsic_load_view_index
: {
7274 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7275 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7276 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7282 case nir_intrinsic_load_layer_id
: {
7283 unsigned idx
= nir_intrinsic_base(instr
);
7284 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7285 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7288 case nir_intrinsic_load_frag_coord
: {
7289 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7292 case nir_intrinsic_load_sample_pos
: {
7293 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7294 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7295 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7296 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7297 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7300 case nir_intrinsic_load_tess_coord
:
7301 visit_load_tess_coord(ctx
, instr
);
7303 case nir_intrinsic_load_interpolated_input
:
7304 visit_load_interpolated_input(ctx
, instr
);
7306 case nir_intrinsic_store_output
:
7307 visit_store_output(ctx
, instr
);
7309 case nir_intrinsic_load_input
:
7310 case nir_intrinsic_load_input_vertex
:
7311 visit_load_input(ctx
, instr
);
7313 case nir_intrinsic_load_output
:
7314 visit_load_output(ctx
, instr
);
7316 case nir_intrinsic_load_per_vertex_input
:
7317 visit_load_per_vertex_input(ctx
, instr
);
7319 case nir_intrinsic_load_per_vertex_output
:
7320 visit_load_per_vertex_output(ctx
, instr
);
7322 case nir_intrinsic_store_per_vertex_output
:
7323 visit_store_per_vertex_output(ctx
, instr
);
7325 case nir_intrinsic_load_ubo
:
7326 visit_load_ubo(ctx
, instr
);
7328 case nir_intrinsic_load_push_constant
:
7329 visit_load_push_constant(ctx
, instr
);
7331 case nir_intrinsic_load_constant
:
7332 visit_load_constant(ctx
, instr
);
7334 case nir_intrinsic_vulkan_resource_index
:
7335 visit_load_resource(ctx
, instr
);
7337 case nir_intrinsic_discard
:
7338 visit_discard(ctx
, instr
);
7340 case nir_intrinsic_discard_if
:
7341 visit_discard_if(ctx
, instr
);
7343 case nir_intrinsic_load_shared
:
7344 visit_load_shared(ctx
, instr
);
7346 case nir_intrinsic_store_shared
:
7347 visit_store_shared(ctx
, instr
);
7349 case nir_intrinsic_shared_atomic_add
:
7350 case nir_intrinsic_shared_atomic_imin
:
7351 case nir_intrinsic_shared_atomic_umin
:
7352 case nir_intrinsic_shared_atomic_imax
:
7353 case nir_intrinsic_shared_atomic_umax
:
7354 case nir_intrinsic_shared_atomic_and
:
7355 case nir_intrinsic_shared_atomic_or
:
7356 case nir_intrinsic_shared_atomic_xor
:
7357 case nir_intrinsic_shared_atomic_exchange
:
7358 case nir_intrinsic_shared_atomic_comp_swap
:
7359 visit_shared_atomic(ctx
, instr
);
7361 case nir_intrinsic_image_deref_load
:
7362 visit_image_load(ctx
, instr
);
7364 case nir_intrinsic_image_deref_store
:
7365 visit_image_store(ctx
, instr
);
7367 case nir_intrinsic_image_deref_atomic_add
:
7368 case nir_intrinsic_image_deref_atomic_umin
:
7369 case nir_intrinsic_image_deref_atomic_imin
:
7370 case nir_intrinsic_image_deref_atomic_umax
:
7371 case nir_intrinsic_image_deref_atomic_imax
:
7372 case nir_intrinsic_image_deref_atomic_and
:
7373 case nir_intrinsic_image_deref_atomic_or
:
7374 case nir_intrinsic_image_deref_atomic_xor
:
7375 case nir_intrinsic_image_deref_atomic_exchange
:
7376 case nir_intrinsic_image_deref_atomic_comp_swap
:
7377 visit_image_atomic(ctx
, instr
);
7379 case nir_intrinsic_image_deref_size
:
7380 visit_image_size(ctx
, instr
);
7382 case nir_intrinsic_load_ssbo
:
7383 visit_load_ssbo(ctx
, instr
);
7385 case nir_intrinsic_store_ssbo
:
7386 visit_store_ssbo(ctx
, instr
);
7388 case nir_intrinsic_load_global
:
7389 visit_load_global(ctx
, instr
);
7391 case nir_intrinsic_store_global
:
7392 visit_store_global(ctx
, instr
);
7394 case nir_intrinsic_global_atomic_add
:
7395 case nir_intrinsic_global_atomic_imin
:
7396 case nir_intrinsic_global_atomic_umin
:
7397 case nir_intrinsic_global_atomic_imax
:
7398 case nir_intrinsic_global_atomic_umax
:
7399 case nir_intrinsic_global_atomic_and
:
7400 case nir_intrinsic_global_atomic_or
:
7401 case nir_intrinsic_global_atomic_xor
:
7402 case nir_intrinsic_global_atomic_exchange
:
7403 case nir_intrinsic_global_atomic_comp_swap
:
7404 visit_global_atomic(ctx
, instr
);
7406 case nir_intrinsic_ssbo_atomic_add
:
7407 case nir_intrinsic_ssbo_atomic_imin
:
7408 case nir_intrinsic_ssbo_atomic_umin
:
7409 case nir_intrinsic_ssbo_atomic_imax
:
7410 case nir_intrinsic_ssbo_atomic_umax
:
7411 case nir_intrinsic_ssbo_atomic_and
:
7412 case nir_intrinsic_ssbo_atomic_or
:
7413 case nir_intrinsic_ssbo_atomic_xor
:
7414 case nir_intrinsic_ssbo_atomic_exchange
:
7415 case nir_intrinsic_ssbo_atomic_comp_swap
:
7416 visit_atomic_ssbo(ctx
, instr
);
7418 case nir_intrinsic_load_scratch
:
7419 visit_load_scratch(ctx
, instr
);
7421 case nir_intrinsic_store_scratch
:
7422 visit_store_scratch(ctx
, instr
);
7424 case nir_intrinsic_get_buffer_size
:
7425 visit_get_buffer_size(ctx
, instr
);
7427 case nir_intrinsic_control_barrier
: {
7428 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7429 /* GFX6 only (thanks to a hw bug workaround):
7430 * The real barrier instruction isn’t needed, because an entire patch
7431 * always fits into a single wave.
7436 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7437 bld
.sopp(aco_opcode::s_barrier
);
7441 case nir_intrinsic_memory_barrier_tcs_patch
:
7442 case nir_intrinsic_group_memory_barrier
:
7443 case nir_intrinsic_memory_barrier
:
7444 case nir_intrinsic_memory_barrier_buffer
:
7445 case nir_intrinsic_memory_barrier_image
:
7446 case nir_intrinsic_memory_barrier_shared
:
7447 emit_memory_barrier(ctx
, instr
);
7449 case nir_intrinsic_load_num_work_groups
: {
7450 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7451 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7452 emit_split_vector(ctx
, dst
, 3);
7455 case nir_intrinsic_load_local_invocation_id
: {
7456 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7457 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7458 emit_split_vector(ctx
, dst
, 3);
7461 case nir_intrinsic_load_work_group_id
: {
7462 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7463 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7465 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7466 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7467 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7468 emit_split_vector(ctx
, dst
, 3);
7471 case nir_intrinsic_load_local_invocation_index
: {
7472 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7474 /* The tg_size bits [6:11] contain the subgroup id,
7475 * we need this multiplied by the wave size, and then OR the thread id to it.
7477 if (ctx
->program
->wave_size
== 64) {
7478 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7479 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7480 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7481 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7483 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7484 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7485 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7486 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7490 case nir_intrinsic_load_subgroup_id
: {
7491 if (ctx
->stage
== compute_cs
) {
7492 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7493 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7495 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7499 case nir_intrinsic_load_subgroup_invocation
: {
7500 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7503 case nir_intrinsic_load_num_subgroups
: {
7504 if (ctx
->stage
== compute_cs
)
7505 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7506 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7508 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7511 case nir_intrinsic_ballot
: {
7512 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7513 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7514 Definition tmp
= bld
.def(dst
.regClass());
7515 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7516 if (instr
->src
[0].ssa
->bit_size
== 1) {
7517 assert(src
.regClass() == bld
.lm
);
7518 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7519 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7520 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7521 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7522 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7524 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7525 nir_print_instr(&instr
->instr
, stderr
);
7526 fprintf(stderr
, "\n");
7528 if (dst
.size() != bld
.lm
.size()) {
7529 /* Wave32 with ballot size set to 64 */
7530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7532 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7535 case nir_intrinsic_shuffle
:
7536 case nir_intrinsic_read_invocation
: {
7537 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7538 if (!nir_src_is_divergent(instr
->src
[0])) {
7539 emit_uniform_subgroup(ctx
, instr
, src
);
7541 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7542 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7543 tid
= bld
.as_uniform(tid
);
7544 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7545 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7546 Temp tmp
= bld
.tmp(v1
);
7547 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7548 if (dst
.type() == RegType::vgpr
)
7549 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7551 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7552 } else if (src
.regClass() == v1
) {
7553 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7554 } else if (src
.regClass() == v2
) {
7555 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7556 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7557 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7558 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7560 emit_split_vector(ctx
, dst
, 2);
7561 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7562 assert(src
.regClass() == bld
.lm
);
7563 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7564 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7565 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7566 assert(src
.regClass() == bld
.lm
);
7568 if (ctx
->program
->chip_class
<= GFX7
)
7569 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7570 else if (ctx
->program
->wave_size
== 64)
7571 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7573 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7574 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7575 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7576 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7578 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7579 nir_print_instr(&instr
->instr
, stderr
);
7580 fprintf(stderr
, "\n");
7585 case nir_intrinsic_load_sample_id
: {
7586 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7587 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7590 case nir_intrinsic_load_sample_mask_in
: {
7591 visit_load_sample_mask_in(ctx
, instr
);
7594 case nir_intrinsic_read_first_invocation
: {
7595 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7596 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7597 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7599 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7601 } else if (src
.regClass() == v2
) {
7602 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7603 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7604 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7605 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7606 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7607 emit_split_vector(ctx
, dst
, 2);
7608 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7609 assert(src
.regClass() == bld
.lm
);
7610 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7611 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7612 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7613 } else if (src
.regClass() == s1
) {
7614 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7615 } else if (src
.regClass() == s2
) {
7616 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7618 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7619 nir_print_instr(&instr
->instr
, stderr
);
7620 fprintf(stderr
, "\n");
7624 case nir_intrinsic_vote_all
: {
7625 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7626 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7627 assert(src
.regClass() == bld
.lm
);
7628 assert(dst
.regClass() == bld
.lm
);
7630 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7631 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7632 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7635 case nir_intrinsic_vote_any
: {
7636 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7638 assert(src
.regClass() == bld
.lm
);
7639 assert(dst
.regClass() == bld
.lm
);
7641 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7642 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7645 case nir_intrinsic_reduce
:
7646 case nir_intrinsic_inclusive_scan
:
7647 case nir_intrinsic_exclusive_scan
: {
7648 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7649 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7650 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7651 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7652 nir_intrinsic_cluster_size(instr
) : 0;
7653 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7655 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7656 emit_uniform_subgroup(ctx
, instr
, src
);
7657 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7658 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7660 else if (op
== nir_op_iadd
)
7662 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7664 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7666 switch (instr
->intrinsic
) {
7667 case nir_intrinsic_reduce
:
7668 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7670 case nir_intrinsic_exclusive_scan
:
7671 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7673 case nir_intrinsic_inclusive_scan
:
7674 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7679 } else if (cluster_size
== 1) {
7680 bld
.copy(Definition(dst
), src
);
7682 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7684 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7688 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7689 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7704 unreachable("unknown reduction op");
7710 switch (instr
->intrinsic
) {
7711 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7712 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7713 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7715 unreachable("unknown reduce intrinsic");
7718 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7719 reduce
->operands
[0] = Operand(src
);
7720 // filled in by aco_reduce_assign.cpp, used internally as part of the
7722 assert(dst
.size() == 1 || dst
.size() == 2);
7723 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7724 reduce
->operands
[2] = Operand(v1
.as_linear());
7726 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7727 reduce
->definitions
[0] = Definition(tmp_dst
);
7728 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7729 reduce
->definitions
[2] = Definition();
7730 reduce
->definitions
[3] = Definition(scc
, s1
);
7731 reduce
->definitions
[4] = Definition();
7732 reduce
->reduce_op
= reduce_op
;
7733 reduce
->cluster_size
= cluster_size
;
7734 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7736 emit_wqm(ctx
, tmp_dst
, dst
);
7740 case nir_intrinsic_quad_broadcast
: {
7741 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7742 if (!nir_dest_is_divergent(instr
->dest
)) {
7743 emit_uniform_subgroup(ctx
, instr
, src
);
7745 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7746 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7747 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7749 if (instr
->dest
.ssa
.bit_size
== 1) {
7750 assert(src
.regClass() == bld
.lm
);
7751 assert(dst
.regClass() == bld
.lm
);
7752 uint32_t half_mask
= 0x11111111u
<< lane
;
7753 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7754 Temp tmp
= bld
.tmp(bld
.lm
);
7755 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7756 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7757 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7758 emit_wqm(ctx
, tmp
, dst
);
7759 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7760 Temp tmp
= bld
.tmp(v1
);
7761 if (ctx
->program
->chip_class
>= GFX8
)
7762 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7764 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7766 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7767 Temp tmp
= bld
.tmp(v1
);
7768 if (ctx
->program
->chip_class
>= GFX8
)
7769 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7771 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7773 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7774 if (ctx
->program
->chip_class
>= GFX8
)
7775 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7777 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7778 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7779 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7780 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7781 if (ctx
->program
->chip_class
>= GFX8
) {
7782 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7783 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7785 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7786 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7788 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7789 emit_split_vector(ctx
, dst
, 2);
7791 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7792 nir_print_instr(&instr
->instr
, stderr
);
7793 fprintf(stderr
, "\n");
7798 case nir_intrinsic_quad_swap_horizontal
:
7799 case nir_intrinsic_quad_swap_vertical
:
7800 case nir_intrinsic_quad_swap_diagonal
:
7801 case nir_intrinsic_quad_swizzle_amd
: {
7802 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7803 if (!nir_dest_is_divergent(instr
->dest
)) {
7804 emit_uniform_subgroup(ctx
, instr
, src
);
7807 uint16_t dpp_ctrl
= 0;
7808 switch (instr
->intrinsic
) {
7809 case nir_intrinsic_quad_swap_horizontal
:
7810 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7812 case nir_intrinsic_quad_swap_vertical
:
7813 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7815 case nir_intrinsic_quad_swap_diagonal
:
7816 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7818 case nir_intrinsic_quad_swizzle_amd
:
7819 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7824 if (ctx
->program
->chip_class
< GFX8
)
7825 dpp_ctrl
|= (1 << 15);
7827 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7828 if (instr
->dest
.ssa
.bit_size
== 1) {
7829 assert(src
.regClass() == bld
.lm
);
7830 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7831 if (ctx
->program
->chip_class
>= GFX8
)
7832 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7834 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7835 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7836 emit_wqm(ctx
, tmp
, dst
);
7837 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7838 Temp tmp
= bld
.tmp(v1
);
7839 if (ctx
->program
->chip_class
>= GFX8
)
7840 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7842 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7843 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7844 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7845 Temp tmp
= bld
.tmp(v1
);
7846 if (ctx
->program
->chip_class
>= GFX8
)
7847 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7849 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7850 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7851 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7853 if (ctx
->program
->chip_class
>= GFX8
)
7854 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7856 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7857 emit_wqm(ctx
, tmp
, dst
);
7858 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7859 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7860 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7861 if (ctx
->program
->chip_class
>= GFX8
) {
7862 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7863 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7865 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7866 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7868 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7869 emit_split_vector(ctx
, dst
, 2);
7871 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7872 nir_print_instr(&instr
->instr
, stderr
);
7873 fprintf(stderr
, "\n");
7877 case nir_intrinsic_masked_swizzle_amd
: {
7878 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7879 if (!nir_dest_is_divergent(instr
->dest
)) {
7880 emit_uniform_subgroup(ctx
, instr
, src
);
7883 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7884 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7885 if (dst
.regClass() == v1
) {
7887 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7889 } else if (dst
.regClass() == v2
) {
7890 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7891 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7892 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7893 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7894 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7895 emit_split_vector(ctx
, dst
, 2);
7897 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7898 nir_print_instr(&instr
->instr
, stderr
);
7899 fprintf(stderr
, "\n");
7903 case nir_intrinsic_write_invocation_amd
: {
7904 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7905 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7906 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7907 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7908 if (dst
.regClass() == v1
) {
7909 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7910 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7911 } else if (dst
.regClass() == v2
) {
7912 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7913 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7916 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7917 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7918 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7919 emit_split_vector(ctx
, dst
, 2);
7921 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7922 nir_print_instr(&instr
->instr
, stderr
);
7923 fprintf(stderr
, "\n");
7927 case nir_intrinsic_mbcnt_amd
: {
7928 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7929 RegClass rc
= RegClass(src
.type(), 1);
7930 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7931 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7932 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7933 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7934 emit_wqm(ctx
, wqm_tmp
, dst
);
7937 case nir_intrinsic_load_helper_invocation
: {
7938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7939 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7940 ctx
->block
->kind
|= block_kind_needs_lowering
;
7941 ctx
->program
->needs_exact
= true;
7944 case nir_intrinsic_is_helper_invocation
: {
7945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7946 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7947 ctx
->block
->kind
|= block_kind_needs_lowering
;
7948 ctx
->program
->needs_exact
= true;
7951 case nir_intrinsic_demote
:
7952 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7954 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7955 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7956 ctx
->block
->kind
|= block_kind_uses_demote
;
7957 ctx
->program
->needs_exact
= true;
7959 case nir_intrinsic_demote_if
: {
7960 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7961 assert(src
.regClass() == bld
.lm
);
7962 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7963 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7965 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7966 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7967 ctx
->block
->kind
|= block_kind_uses_demote
;
7968 ctx
->program
->needs_exact
= true;
7971 case nir_intrinsic_first_invocation
: {
7972 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7973 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7976 case nir_intrinsic_shader_clock
: {
7978 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7979 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7980 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7981 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7984 case nir_intrinsic_load_vertex_id_zero_base
: {
7985 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7986 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7989 case nir_intrinsic_load_first_vertex
: {
7990 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7991 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7994 case nir_intrinsic_load_base_instance
: {
7995 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7996 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7999 case nir_intrinsic_load_instance_id
: {
8000 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8001 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8004 case nir_intrinsic_load_draw_id
: {
8005 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8006 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8009 case nir_intrinsic_load_invocation_id
: {
8010 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8012 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8013 if (ctx
->options
->chip_class
>= GFX10
)
8014 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8016 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8017 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8018 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8019 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8021 unreachable("Unsupported stage for load_invocation_id");
8026 case nir_intrinsic_load_primitive_id
: {
8027 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8029 switch (ctx
->shader
->info
.stage
) {
8030 case MESA_SHADER_GEOMETRY
:
8031 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8033 case MESA_SHADER_TESS_CTRL
:
8034 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8036 case MESA_SHADER_TESS_EVAL
:
8037 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8040 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8045 case nir_intrinsic_load_patch_vertices_in
: {
8046 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8047 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8049 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8050 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8053 case nir_intrinsic_emit_vertex_with_counter
: {
8054 visit_emit_vertex_with_counter(ctx
, instr
);
8057 case nir_intrinsic_end_primitive_with_counter
: {
8058 unsigned stream
= nir_intrinsic_stream_id(instr
);
8059 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8062 case nir_intrinsic_set_vertex_count
: {
8063 /* unused, the HW keeps track of this for us */
8067 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8068 nir_print_instr(&instr
->instr
, stderr
);
8069 fprintf(stderr
, "\n");
8077 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8078 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8079 enum glsl_base_type
*stype
)
8081 nir_deref_instr
*texture_deref_instr
= NULL
;
8082 nir_deref_instr
*sampler_deref_instr
= NULL
;
8085 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8086 switch (instr
->src
[i
].src_type
) {
8087 case nir_tex_src_texture_deref
:
8088 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8090 case nir_tex_src_sampler_deref
:
8091 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8093 case nir_tex_src_plane
:
8094 plane
= nir_src_as_int(instr
->src
[i
].src
);
8101 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8103 if (!sampler_deref_instr
)
8104 sampler_deref_instr
= texture_deref_instr
;
8107 assert(instr
->op
!= nir_texop_txf_ms
&&
8108 instr
->op
!= nir_texop_samples_identical
);
8109 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8110 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8111 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8112 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8113 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8114 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8116 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8119 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8121 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8122 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8123 Builder
bld(ctx
->program
, ctx
->block
);
8125 /* to avoid unnecessary moves, we split and recombine sampler and image */
8126 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8127 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8128 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8129 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8130 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8131 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8132 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8133 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8135 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8136 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8137 img
[0], img
[1], img
[2], img
[3],
8138 img
[4], img
[5], img
[6], img
[7]);
8139 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8140 samp
[0], samp
[1], samp
[2], samp
[3]);
8143 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8144 instr
->op
== nir_texop_samples_identical
))
8145 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8148 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8149 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8151 Builder
bld(ctx
->program
, ctx
->block
);
8153 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8154 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8155 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8157 Operand
neg_one(0xbf800000u
);
8158 Operand
one(0x3f800000u
);
8159 Operand
two(0x40000000u
);
8160 Operand
four(0x40800000u
);
8162 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8163 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8164 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8166 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8167 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8168 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8169 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8172 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8173 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8174 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8176 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8179 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8180 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8181 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8184 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8185 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8187 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8188 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8191 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8193 Builder
bld(ctx
->program
, ctx
->block
);
8194 Temp ma
, tc
, sc
, id
;
8197 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8199 // see comment in ac_prepare_cube_coords()
8200 if (ctx
->options
->chip_class
<= GFX8
)
8201 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8204 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8206 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8207 vop3a
->operands
[0] = Operand(ma
);
8208 vop3a
->abs
[0] = true;
8209 Temp invma
= bld
.tmp(v1
);
8210 vop3a
->definitions
[0] = Definition(invma
);
8211 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8213 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8215 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8217 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8219 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8221 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8224 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8225 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8227 for (unsigned i
= 0; i
< 2; i
++) {
8228 // see comment in ac_prepare_cube_coords()
8230 Temp deriv_sc
, deriv_tc
;
8231 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8232 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8234 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8236 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8237 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8238 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8239 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8240 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8241 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8242 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8245 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8246 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8250 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8257 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8259 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8261 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8262 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8265 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8266 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8267 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8271 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8273 Builder
bld(ctx
->program
, ctx
->block
);
8274 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8275 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8276 has_clamped_lod
= false;
8277 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8278 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8279 clamped_lod
= Temp();
8280 std::vector
<Temp
> coords
;
8281 std::vector
<Temp
> derivs
;
8282 nir_const_value
*sample_index_cv
= NULL
;
8283 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8284 enum glsl_base_type stype
;
8285 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8287 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8288 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8289 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8290 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8292 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8293 switch (instr
->src
[i
].src_type
) {
8294 case nir_tex_src_coord
: {
8295 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8296 for (unsigned i
= 0; i
< coord
.size(); i
++)
8297 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8300 case nir_tex_src_bias
:
8301 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8304 case nir_tex_src_lod
: {
8305 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8307 if (val
&& val
->f32
<= 0.0) {
8310 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8315 case nir_tex_src_min_lod
:
8316 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8317 has_clamped_lod
= true;
8319 case nir_tex_src_comparator
:
8320 if (instr
->is_shadow
) {
8321 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8325 case nir_tex_src_offset
:
8326 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8327 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8330 case nir_tex_src_ddx
:
8331 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8334 case nir_tex_src_ddy
:
8335 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8338 case nir_tex_src_ms_index
:
8339 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8340 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8341 has_sample_index
= true;
8343 case nir_tex_src_texture_offset
:
8344 case nir_tex_src_sampler_offset
:
8350 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8351 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8353 if (instr
->op
== nir_texop_texture_samples
) {
8354 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8356 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8357 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8358 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8360 Operand default_sample
= Operand(1u);
8361 if (ctx
->options
->robust_buffer_access
) {
8362 /* Extract the second dword of the descriptor, if it's
8363 * all zero, then it's a null descriptor.
8365 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8366 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8367 default_sample
= Operand(is_non_null_descriptor
);
8370 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8371 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8372 samples
, default_sample
, bld
.scc(is_msaa
));
8376 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8377 aco_ptr
<Instruction
> tmp_instr
;
8378 Temp acc
, pack
= Temp();
8380 uint32_t pack_const
= 0;
8381 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8382 if (!const_offset
[i
])
8384 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8387 if (offset
.type() == RegType::sgpr
) {
8388 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8389 if (const_offset
[i
])
8392 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8393 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8396 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8399 if (pack
== Temp()) {
8402 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8406 if (pack_const
&& pack
!= Temp())
8407 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8409 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8410 if (const_offset
[i
])
8413 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8414 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8417 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8420 if (pack
== Temp()) {
8423 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8427 if (pack_const
&& pack
!= Temp())
8428 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8430 if (pack_const
&& pack
== Temp())
8431 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8432 else if (pack
== Temp())
8438 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8439 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8441 /* pack derivatives */
8442 if (has_ddx
|| has_ddy
) {
8443 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8444 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8445 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8446 derivs
= {ddx
, zero
, ddy
, zero
};
8448 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8449 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8450 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8451 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8456 if (instr
->coord_components
> 1 &&
8457 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8459 instr
->op
!= nir_texop_txf
)
8460 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8462 if (instr
->coord_components
> 2 &&
8463 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8464 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8465 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8466 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8468 instr
->op
!= nir_texop_txf
&&
8469 instr
->op
!= nir_texop_txf_ms
&&
8470 instr
->op
!= nir_texop_fragment_fetch
&&
8471 instr
->op
!= nir_texop_fragment_mask_fetch
)
8472 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8474 if (ctx
->options
->chip_class
== GFX9
&&
8475 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8476 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8477 assert(coords
.size() > 0 && coords
.size() < 3);
8479 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8480 Operand((uint32_t) 0) :
8481 Operand((uint32_t) 0x3f000000)));
8484 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8486 if (instr
->op
== nir_texop_samples_identical
)
8487 resource
= fmask_ptr
;
8489 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8490 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8491 instr
->op
!= nir_texop_txs
&&
8492 instr
->op
!= nir_texop_fragment_fetch
&&
8493 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8494 assert(has_sample_index
);
8495 Operand
op(sample_index
);
8496 if (sample_index_cv
)
8497 op
= Operand(sample_index_cv
->u32
);
8498 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8501 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8502 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8503 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8504 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8509 /* Build tex instruction */
8510 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8511 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8512 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8514 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8517 /* gather4 selects the component by dmask and always returns vec4 */
8518 if (instr
->op
== nir_texop_tg4
) {
8519 assert(instr
->dest
.ssa
.num_components
== 4);
8520 if (instr
->is_shadow
)
8523 dmask
= 1 << instr
->component
;
8524 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8525 tmp_dst
= bld
.tmp(v4
);
8526 } else if (instr
->op
== nir_texop_samples_identical
) {
8527 tmp_dst
= bld
.tmp(v1
);
8528 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8529 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8532 aco_ptr
<MIMG_instruction
> tex
;
8533 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8535 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8537 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8538 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8541 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8542 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8544 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8545 tex
->operands
[0] = Operand(resource
);
8546 tex
->operands
[1] = Operand(s4
); /* no sampler */
8547 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8548 if (ctx
->options
->chip_class
== GFX9
&&
8549 instr
->op
== nir_texop_txs
&&
8550 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8552 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8553 } else if (instr
->op
== nir_texop_query_levels
) {
8554 tex
->dmask
= 1 << 3;
8559 tex
->definitions
[0] = Definition(tmp_dst
);
8561 tex
->can_reorder
= true;
8562 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8565 /* divide 3rd value by 6 by multiplying with magic number */
8566 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8567 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8568 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8569 assert(instr
->dest
.ssa
.num_components
== 3);
8570 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8571 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8572 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8573 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8578 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8582 Temp tg4_compare_cube_wa64
= Temp();
8584 if (tg4_integer_workarounds
) {
8585 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8586 tex
->operands
[0] = Operand(resource
);
8587 tex
->operands
[1] = Operand(s4
); /* no sampler */
8588 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8592 Temp size
= bld
.tmp(v2
);
8593 tex
->definitions
[0] = Definition(size
);
8594 tex
->can_reorder
= true;
8595 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8596 emit_split_vector(ctx
, size
, size
.size());
8599 for (unsigned i
= 0; i
< 2; i
++) {
8600 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8601 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8602 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8603 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8606 Temp new_coords
[2] = {
8607 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8608 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8611 if (tg4_integer_cube_workaround
) {
8612 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8613 Temp desc
[resource
.size()];
8614 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8615 Format::PSEUDO
, 1, resource
.size())};
8616 split
->operands
[0] = Operand(resource
);
8617 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8618 desc
[i
] = bld
.tmp(s1
);
8619 split
->definitions
[i
] = Definition(desc
[i
]);
8621 ctx
->block
->instructions
.emplace_back(std::move(split
));
8623 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8624 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8625 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8628 if (stype
== GLSL_TYPE_UINT
) {
8629 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8630 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8631 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8632 bld
.scc(compare_cube_wa
));
8634 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8635 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8636 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8637 bld
.scc(compare_cube_wa
));
8639 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8640 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8642 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8644 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8645 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8646 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8648 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8649 Format::PSEUDO
, resource
.size(), 1)};
8650 for (unsigned i
= 0; i
< resource
.size(); i
++)
8651 vec
->operands
[i
] = Operand(desc
[i
]);
8652 resource
= bld
.tmp(resource
.regClass());
8653 vec
->definitions
[0] = Definition(resource
);
8654 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8656 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8657 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8658 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8659 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8661 coords
[0] = new_coords
[0];
8662 coords
[1] = new_coords
[1];
8665 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8666 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8668 assert(coords
.size() == 1);
8669 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8673 op
= aco_opcode::buffer_load_format_x
; break;
8675 op
= aco_opcode::buffer_load_format_xy
; break;
8677 op
= aco_opcode::buffer_load_format_xyz
; break;
8679 op
= aco_opcode::buffer_load_format_xyzw
; break;
8681 unreachable("Tex instruction loads more than 4 components.");
8684 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8685 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8688 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8690 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8691 mubuf
->operands
[0] = Operand(resource
);
8692 mubuf
->operands
[1] = Operand(coords
[0]);
8693 mubuf
->operands
[2] = Operand((uint32_t) 0);
8694 mubuf
->definitions
[0] = Definition(tmp_dst
);
8695 mubuf
->idxen
= true;
8696 mubuf
->can_reorder
= true;
8697 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8699 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8703 /* gather MIMG address components */
8704 std::vector
<Temp
> args
;
8706 args
.emplace_back(offset
);
8708 args
.emplace_back(bias
);
8710 args
.emplace_back(compare
);
8712 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8714 args
.insert(args
.end(), coords
.begin(), coords
.end());
8715 if (has_sample_index
)
8716 args
.emplace_back(sample_index
);
8718 args
.emplace_back(lod
);
8719 if (has_clamped_lod
)
8720 args
.emplace_back(clamped_lod
);
8722 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8723 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8724 vec
->definitions
[0] = Definition(arg
);
8725 for (unsigned i
= 0; i
< args
.size(); i
++)
8726 vec
->operands
[i
] = Operand(args
[i
]);
8727 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8730 if (instr
->op
== nir_texop_txf
||
8731 instr
->op
== nir_texop_txf_ms
||
8732 instr
->op
== nir_texop_samples_identical
||
8733 instr
->op
== nir_texop_fragment_fetch
||
8734 instr
->op
== nir_texop_fragment_mask_fetch
) {
8735 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8736 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8737 tex
->operands
[0] = Operand(resource
);
8738 tex
->operands
[1] = Operand(s4
); /* no sampler */
8739 tex
->operands
[2] = Operand(arg
);
8744 tex
->definitions
[0] = Definition(tmp_dst
);
8745 tex
->can_reorder
= true;
8746 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8748 if (instr
->op
== nir_texop_samples_identical
) {
8749 assert(dmask
== 1 && dst
.regClass() == v1
);
8750 assert(dst
.id() != tmp_dst
.id());
8752 Temp tmp
= bld
.tmp(bld
.lm
);
8753 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8754 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8757 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8762 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8763 aco_opcode opcode
= aco_opcode::image_sample
;
8764 if (has_offset
) { /* image_sample_*_o */
8765 if (has_clamped_lod
) {
8767 opcode
= aco_opcode::image_sample_c_cl_o
;
8769 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8771 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8773 opcode
= aco_opcode::image_sample_cl_o
;
8775 opcode
= aco_opcode::image_sample_d_cl_o
;
8777 opcode
= aco_opcode::image_sample_b_cl_o
;
8779 } else if (has_compare
) {
8780 opcode
= aco_opcode::image_sample_c_o
;
8782 opcode
= aco_opcode::image_sample_c_d_o
;
8784 opcode
= aco_opcode::image_sample_c_b_o
;
8786 opcode
= aco_opcode::image_sample_c_lz_o
;
8788 opcode
= aco_opcode::image_sample_c_l_o
;
8790 opcode
= aco_opcode::image_sample_o
;
8792 opcode
= aco_opcode::image_sample_d_o
;
8794 opcode
= aco_opcode::image_sample_b_o
;
8796 opcode
= aco_opcode::image_sample_lz_o
;
8798 opcode
= aco_opcode::image_sample_l_o
;
8800 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8802 opcode
= aco_opcode::image_sample_c_cl
;
8804 opcode
= aco_opcode::image_sample_c_d_cl
;
8806 opcode
= aco_opcode::image_sample_c_b_cl
;
8808 opcode
= aco_opcode::image_sample_cl
;
8810 opcode
= aco_opcode::image_sample_d_cl
;
8812 opcode
= aco_opcode::image_sample_b_cl
;
8814 } else { /* no offset */
8816 opcode
= aco_opcode::image_sample_c
;
8818 opcode
= aco_opcode::image_sample_c_d
;
8820 opcode
= aco_opcode::image_sample_c_b
;
8822 opcode
= aco_opcode::image_sample_c_lz
;
8824 opcode
= aco_opcode::image_sample_c_l
;
8826 opcode
= aco_opcode::image_sample
;
8828 opcode
= aco_opcode::image_sample_d
;
8830 opcode
= aco_opcode::image_sample_b
;
8832 opcode
= aco_opcode::image_sample_lz
;
8834 opcode
= aco_opcode::image_sample_l
;
8838 if (instr
->op
== nir_texop_tg4
) {
8839 if (has_offset
) { /* image_gather4_*_o */
8841 opcode
= aco_opcode::image_gather4_c_lz_o
;
8843 opcode
= aco_opcode::image_gather4_c_l_o
;
8845 opcode
= aco_opcode::image_gather4_c_b_o
;
8847 opcode
= aco_opcode::image_gather4_lz_o
;
8849 opcode
= aco_opcode::image_gather4_l_o
;
8851 opcode
= aco_opcode::image_gather4_b_o
;
8855 opcode
= aco_opcode::image_gather4_c_lz
;
8857 opcode
= aco_opcode::image_gather4_c_l
;
8859 opcode
= aco_opcode::image_gather4_c_b
;
8861 opcode
= aco_opcode::image_gather4_lz
;
8863 opcode
= aco_opcode::image_gather4_l
;
8865 opcode
= aco_opcode::image_gather4_b
;
8868 } else if (instr
->op
== nir_texop_lod
) {
8869 opcode
= aco_opcode::image_get_lod
;
8872 /* we don't need the bias, sample index, compare value or offset to be
8873 * computed in WQM but if the p_create_vector copies the coordinates, then it
8874 * needs to be in WQM */
8875 if (ctx
->stage
== fragment_fs
&&
8876 !has_derivs
&& !has_lod
&& !level_zero
&&
8877 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8878 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8879 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8881 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8882 tex
->operands
[0] = Operand(resource
);
8883 tex
->operands
[1] = Operand(sampler
);
8884 tex
->operands
[2] = Operand(arg
);
8888 tex
->definitions
[0] = Definition(tmp_dst
);
8889 tex
->can_reorder
= true;
8890 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8892 if (tg4_integer_cube_workaround
) {
8893 assert(tmp_dst
.id() != dst
.id());
8894 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8896 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8898 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8899 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8901 if (stype
== GLSL_TYPE_UINT
)
8902 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8904 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8905 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8907 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8908 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8909 val
[0], val
[1], val
[2], val
[3]);
8911 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8912 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8917 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8919 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8920 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8921 return Operand(tmp
.regClass());
8923 return Operand(tmp
);
8926 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8928 aco_ptr
<Pseudo_instruction
> phi
;
8929 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8930 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8932 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8933 logical
|= ctx
->block
->kind
& block_kind_merge
;
8934 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8936 /* we want a sorted list of sources, since the predecessor list is also sorted */
8937 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8938 nir_foreach_phi_src(src
, instr
)
8939 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8941 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8942 unsigned num_operands
= 0;
8943 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8944 unsigned num_defined
= 0;
8945 unsigned cur_pred_idx
= 0;
8946 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8947 if (cur_pred_idx
< preds
.size()) {
8948 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8949 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8950 unsigned skipped
= 0;
8951 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8953 if (cur_pred_idx
+ skipped
< preds
.size()) {
8954 for (unsigned i
= 0; i
< skipped
; i
++)
8955 operands
[num_operands
++] = Operand(dst
.regClass());
8956 cur_pred_idx
+= skipped
;
8961 /* Handle missing predecessors at the end. This shouldn't happen with loop
8962 * headers and we can't ignore these sources for loop header phis. */
8963 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8966 Operand op
= get_phi_operand(ctx
, src
.second
);
8967 operands
[num_operands
++] = op
;
8968 num_defined
+= !op
.isUndefined();
8970 /* handle block_kind_continue_or_break at loop exit blocks */
8971 while (cur_pred_idx
++ < preds
.size())
8972 operands
[num_operands
++] = Operand(dst
.regClass());
8974 /* If the loop ends with a break, still add a linear continue edge in case
8975 * that break is divergent or continue_or_break is used. We'll either remove
8976 * this operand later in visit_loop() if it's not necessary or replace the
8977 * undef with something correct. */
8978 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8979 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8980 nir_block
*last
= nir_loop_last_block(loop
);
8981 if (last
->successors
[0] != instr
->instr
.block
)
8982 operands
[num_operands
++] = Operand(RegClass());
8985 if (num_defined
== 0) {
8986 Builder
bld(ctx
->program
, ctx
->block
);
8987 if (dst
.regClass() == s1
) {
8988 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8989 } else if (dst
.regClass() == v1
) {
8990 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8992 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8993 for (unsigned i
= 0; i
< dst
.size(); i
++)
8994 vec
->operands
[i
] = Operand(0u);
8995 vec
->definitions
[0] = Definition(dst
);
8996 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9001 /* we can use a linear phi in some cases if one src is undef */
9002 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9003 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9005 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9006 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9007 assert(invert
->kind
& block_kind_invert
);
9009 unsigned then_block
= invert
->linear_preds
[0];
9011 Block
* insert_block
= NULL
;
9012 for (unsigned i
= 0; i
< num_operands
; i
++) {
9013 Operand op
= operands
[i
];
9014 if (op
.isUndefined())
9016 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9017 phi
->operands
[0] = op
;
9020 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9021 phi
->operands
[1] = Operand(dst
.regClass());
9022 phi
->definitions
[0] = Definition(dst
);
9023 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9027 /* try to scalarize vector phis */
9028 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9029 // TODO: scalarize linear phis on divergent ifs
9030 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9031 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9032 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9033 Operand src
= operands
[i
];
9034 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9035 can_scalarize
= false;
9037 if (can_scalarize
) {
9038 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9039 assert(dst
.size() % num_components
== 0);
9040 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9042 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9043 for (unsigned k
= 0; k
< num_components
; k
++) {
9044 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9045 for (unsigned i
= 0; i
< num_operands
; i
++) {
9046 Operand src
= operands
[i
];
9047 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9049 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9050 phi
->definitions
[0] = Definition(phi_dst
);
9051 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9052 new_vec
[k
] = phi_dst
;
9053 vec
->operands
[k
] = Operand(phi_dst
);
9055 vec
->definitions
[0] = Definition(dst
);
9056 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9057 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9062 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9063 for (unsigned i
= 0; i
< num_operands
; i
++)
9064 phi
->operands
[i
] = operands
[i
];
9065 phi
->definitions
[0] = Definition(dst
);
9066 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9070 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9072 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9074 assert(dst
.type() == RegType::sgpr
);
9076 if (dst
.size() == 1) {
9077 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9079 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9080 for (unsigned i
= 0; i
< dst
.size(); i
++)
9081 vec
->operands
[i
] = Operand(0u);
9082 vec
->definitions
[0] = Definition(dst
);
9083 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9087 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9089 Builder
bld(ctx
->program
, ctx
->block
);
9090 Block
*logical_target
;
9091 append_logical_end(ctx
->block
);
9092 unsigned idx
= ctx
->block
->index
;
9094 switch (instr
->type
) {
9095 case nir_jump_break
:
9096 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9097 add_logical_edge(idx
, logical_target
);
9098 ctx
->block
->kind
|= block_kind_break
;
9100 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9101 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9102 /* uniform break - directly jump out of the loop */
9103 ctx
->block
->kind
|= block_kind_uniform
;
9104 ctx
->cf_info
.has_branch
= true;
9105 bld
.branch(aco_opcode::p_branch
);
9106 add_linear_edge(idx
, logical_target
);
9109 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9110 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9112 case nir_jump_continue
:
9113 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9114 add_logical_edge(idx
, logical_target
);
9115 ctx
->block
->kind
|= block_kind_continue
;
9117 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9118 /* for potential uniform breaks after this continue,
9119 we must ensure that they are handled correctly */
9120 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9121 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9122 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9124 /* uniform continue - directly jump to the loop header */
9125 ctx
->block
->kind
|= block_kind_uniform
;
9126 ctx
->cf_info
.has_branch
= true;
9127 bld
.branch(aco_opcode::p_branch
);
9128 add_linear_edge(idx
, logical_target
);
9133 fprintf(stderr
, "Unknown NIR jump instr: ");
9134 nir_print_instr(&instr
->instr
, stderr
);
9135 fprintf(stderr
, "\n");
9139 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9140 ctx
->cf_info
.exec_potentially_empty_break
= true;
9141 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9144 /* remove critical edges from linear CFG */
9145 bld
.branch(aco_opcode::p_branch
);
9146 Block
* break_block
= ctx
->program
->create_and_insert_block();
9147 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9148 break_block
->kind
|= block_kind_uniform
;
9149 add_linear_edge(idx
, break_block
);
9150 /* the loop_header pointer might be invalidated by this point */
9151 if (instr
->type
== nir_jump_continue
)
9152 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9153 add_linear_edge(break_block
->index
, logical_target
);
9154 bld
.reset(break_block
);
9155 bld
.branch(aco_opcode::p_branch
);
9157 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9158 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9159 add_linear_edge(idx
, continue_block
);
9160 append_logical_start(continue_block
);
9161 ctx
->block
= continue_block
;
9165 void visit_block(isel_context
*ctx
, nir_block
*block
)
9167 nir_foreach_instr(instr
, block
) {
9168 switch (instr
->type
) {
9169 case nir_instr_type_alu
:
9170 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9172 case nir_instr_type_load_const
:
9173 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9175 case nir_instr_type_intrinsic
:
9176 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9178 case nir_instr_type_tex
:
9179 visit_tex(ctx
, nir_instr_as_tex(instr
));
9181 case nir_instr_type_phi
:
9182 visit_phi(ctx
, nir_instr_as_phi(instr
));
9184 case nir_instr_type_ssa_undef
:
9185 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9187 case nir_instr_type_deref
:
9189 case nir_instr_type_jump
:
9190 visit_jump(ctx
, nir_instr_as_jump(instr
));
9193 fprintf(stderr
, "Unknown NIR instr type: ");
9194 nir_print_instr(instr
, stderr
);
9195 fprintf(stderr
, "\n");
9200 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9201 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9206 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9207 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9209 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9210 RegClass rc
= vals
[0].regClass();
9212 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9214 unsigned next_pred
= 1;
9216 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9217 Block
& block
= ctx
->program
->blocks
[idx
];
9218 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9219 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9223 if (block
.kind
& block_kind_continue
) {
9224 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9229 bool all_same
= true;
9230 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9231 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9235 val
= vals
[block
.linear_preds
[0] - first
];
9237 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9238 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9239 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9240 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9241 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9242 phi
->definitions
[0] = Definition(val
.getTemp());
9243 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9245 vals
[idx
- first
] = val
;
9248 return vals
[last
- first
];
9251 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9253 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9254 append_logical_end(ctx
->block
);
9255 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9256 Builder
bld(ctx
->program
, ctx
->block
);
9257 bld
.branch(aco_opcode::p_branch
);
9258 unsigned loop_preheader_idx
= ctx
->block
->index
;
9260 Block loop_exit
= Block();
9261 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9262 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9264 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9265 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9266 loop_header
->kind
|= block_kind_loop_header
;
9267 add_edge(loop_preheader_idx
, loop_header
);
9268 ctx
->block
= loop_header
;
9270 /* emit loop body */
9271 unsigned loop_header_idx
= loop_header
->index
;
9272 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9273 append_logical_start(ctx
->block
);
9274 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9276 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9277 if (!ctx
->cf_info
.has_branch
) {
9278 append_logical_end(ctx
->block
);
9279 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9280 /* Discards can result in code running with an empty exec mask.
9281 * This would result in divergent breaks not ever being taken. As a
9282 * workaround, break the loop when the loop mask is empty instead of
9283 * always continuing. */
9284 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9285 unsigned block_idx
= ctx
->block
->index
;
9287 /* create helper blocks to avoid critical edges */
9288 Block
*break_block
= ctx
->program
->create_and_insert_block();
9289 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9290 break_block
->kind
= block_kind_uniform
;
9291 bld
.reset(break_block
);
9292 bld
.branch(aco_opcode::p_branch
);
9293 add_linear_edge(block_idx
, break_block
);
9294 add_linear_edge(break_block
->index
, &loop_exit
);
9296 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9297 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9298 continue_block
->kind
= block_kind_uniform
;
9299 bld
.reset(continue_block
);
9300 bld
.branch(aco_opcode::p_branch
);
9301 add_linear_edge(block_idx
, continue_block
);
9302 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9304 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9305 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9306 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9308 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9309 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9310 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9312 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9315 bld
.reset(ctx
->block
);
9316 bld
.branch(aco_opcode::p_branch
);
9319 /* Fixup phis in loop header from unreachable blocks.
9320 * has_branch/has_divergent_branch also indicates if the loop ends with a
9321 * break/continue instruction, but we don't emit those if unreachable=true */
9323 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9324 bool linear
= ctx
->cf_info
.has_branch
;
9325 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9326 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9327 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9328 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9329 /* the last operand should be the one that needs to be removed */
9330 instr
->operands
.pop_back();
9331 } else if (!is_phi(instr
)) {
9337 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9338 * and the previous one shouldn't both happen at once because a break in the
9339 * merge block would get CSE'd */
9340 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9341 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9342 Operand vals
[num_vals
];
9343 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9344 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9345 if (ctx
->cf_info
.has_branch
)
9346 instr
->operands
.pop_back();
9348 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9349 } else if (!is_phi(instr
)) {
9355 ctx
->cf_info
.has_branch
= false;
9357 // TODO: if the loop has not a single exit, we must add one °°
9358 /* emit loop successor block */
9359 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9360 append_logical_start(ctx
->block
);
9363 // TODO: check if it is beneficial to not branch on continues
9364 /* trim linear phis in loop header */
9365 for (auto&& instr
: loop_entry
->instructions
) {
9366 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9367 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9368 new_phi
->definitions
[0] = instr
->definitions
[0];
9369 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9370 new_phi
->operands
[i
] = instr
->operands
[i
];
9371 /* check that the remaining operands are all the same */
9372 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9373 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9374 instr
.swap(new_phi
);
9375 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9384 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9388 append_logical_end(ctx
->block
);
9389 ctx
->block
->kind
|= block_kind_branch
;
9391 /* branch to linear then block */
9392 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9393 aco_ptr
<Pseudo_branch_instruction
> branch
;
9394 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9395 branch
->operands
[0] = Operand(cond
);
9396 ctx
->block
->instructions
.push_back(std::move(branch
));
9398 ic
->BB_if_idx
= ctx
->block
->index
;
9399 ic
->BB_invert
= Block();
9400 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9401 /* Invert blocks are intentionally not marked as top level because they
9402 * are not part of the logical cfg. */
9403 ic
->BB_invert
.kind
|= block_kind_invert
;
9404 ic
->BB_endif
= Block();
9405 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9406 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9408 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9409 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9410 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9411 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9412 ctx
->cf_info
.parent_if
.is_divergent
= true;
9414 /* divergent branches use cbranch_execz */
9415 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9416 ctx
->cf_info
.exec_potentially_empty_break
= false;
9417 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9419 /** emit logical then block */
9420 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9421 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9422 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9423 ctx
->block
= BB_then_logical
;
9424 append_logical_start(BB_then_logical
);
9427 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9429 Block
*BB_then_logical
= ctx
->block
;
9430 append_logical_end(BB_then_logical
);
9431 /* branch from logical then block to invert block */
9432 aco_ptr
<Pseudo_branch_instruction
> branch
;
9433 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9434 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9435 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9436 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9437 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9438 BB_then_logical
->kind
|= block_kind_uniform
;
9439 assert(!ctx
->cf_info
.has_branch
);
9440 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9441 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9443 /** emit linear then block */
9444 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9445 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9446 BB_then_linear
->kind
|= block_kind_uniform
;
9447 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9448 /* branch from linear then block to invert block */
9449 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9450 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9451 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9453 /** emit invert merge block */
9454 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9455 ic
->invert_idx
= ctx
->block
->index
;
9457 /* branch to linear else block (skip else) */
9458 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9459 branch
->operands
[0] = Operand(ic
->cond
);
9460 ctx
->block
->instructions
.push_back(std::move(branch
));
9462 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9463 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9464 ic
->exec_potentially_empty_break_depth_old
=
9465 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9466 /* divergent branches use cbranch_execz */
9467 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9468 ctx
->cf_info
.exec_potentially_empty_break
= false;
9469 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9471 /** emit logical else block */
9472 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9473 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9474 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9475 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9476 ctx
->block
= BB_else_logical
;
9477 append_logical_start(BB_else_logical
);
9480 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9482 Block
*BB_else_logical
= ctx
->block
;
9483 append_logical_end(BB_else_logical
);
9485 /* branch from logical else block to endif block */
9486 aco_ptr
<Pseudo_branch_instruction
> branch
;
9487 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9488 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9489 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9490 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9491 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9492 BB_else_logical
->kind
|= block_kind_uniform
;
9494 assert(!ctx
->cf_info
.has_branch
);
9495 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9498 /** emit linear else block */
9499 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9500 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9501 BB_else_linear
->kind
|= block_kind_uniform
;
9502 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9504 /* branch from linear else block to endif block */
9505 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9506 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9507 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9510 /** emit endif merge block */
9511 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9512 append_logical_start(ctx
->block
);
9515 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9516 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9517 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9518 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9519 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9520 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9521 !ctx
->cf_info
.parent_if
.is_divergent
) {
9522 ctx
->cf_info
.exec_potentially_empty_break
= false;
9523 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9525 /* uniform control flow never has an empty exec-mask */
9526 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9527 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9528 ctx
->cf_info
.exec_potentially_empty_break
= false;
9529 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9533 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9535 assert(cond
.regClass() == s1
);
9537 append_logical_end(ctx
->block
);
9538 ctx
->block
->kind
|= block_kind_uniform
;
9540 aco_ptr
<Pseudo_branch_instruction
> branch
;
9541 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9542 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9543 branch
->operands
[0] = Operand(cond
);
9544 branch
->operands
[0].setFixed(scc
);
9545 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9547 ic
->BB_if_idx
= ctx
->block
->index
;
9548 ic
->BB_endif
= Block();
9549 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9550 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9552 ctx
->cf_info
.has_branch
= false;
9553 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9555 /** emit then block */
9556 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9557 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9558 add_edge(ic
->BB_if_idx
, BB_then
);
9559 append_logical_start(BB_then
);
9560 ctx
->block
= BB_then
;
9563 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9565 Block
*BB_then
= ctx
->block
;
9567 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9568 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9570 if (!ic
->uniform_has_then_branch
) {
9571 append_logical_end(BB_then
);
9572 /* branch from then block to endif block */
9573 aco_ptr
<Pseudo_branch_instruction
> branch
;
9574 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9575 BB_then
->instructions
.emplace_back(std::move(branch
));
9576 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9577 if (!ic
->then_branch_divergent
)
9578 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9579 BB_then
->kind
|= block_kind_uniform
;
9582 ctx
->cf_info
.has_branch
= false;
9583 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9585 /** emit else block */
9586 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9587 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9588 add_edge(ic
->BB_if_idx
, BB_else
);
9589 append_logical_start(BB_else
);
9590 ctx
->block
= BB_else
;
9593 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9595 Block
*BB_else
= ctx
->block
;
9597 if (!ctx
->cf_info
.has_branch
) {
9598 append_logical_end(BB_else
);
9599 /* branch from then block to endif block */
9600 aco_ptr
<Pseudo_branch_instruction
> branch
;
9601 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9602 BB_else
->instructions
.emplace_back(std::move(branch
));
9603 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9604 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9605 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9606 BB_else
->kind
|= block_kind_uniform
;
9609 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9610 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9612 /** emit endif merge block */
9613 if (!ctx
->cf_info
.has_branch
) {
9614 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9615 append_logical_start(ctx
->block
);
9619 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9621 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9622 Builder
bld(ctx
->program
, ctx
->block
);
9623 aco_ptr
<Pseudo_branch_instruction
> branch
;
9626 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9628 * Uniform conditionals are represented in the following way*) :
9630 * The linear and logical CFG:
9633 * BB_THEN (logical) BB_ELSE (logical)
9637 * *) Exceptions may be due to break and continue statements within loops
9638 * If a break/continue happens within uniform control flow, it branches
9639 * to the loop exit/entry block. Otherwise, it branches to the next
9643 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9644 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9645 cond
= bool_to_scalar_condition(ctx
, cond
);
9647 begin_uniform_if_then(ctx
, &ic
, cond
);
9648 visit_cf_list(ctx
, &if_stmt
->then_list
);
9650 begin_uniform_if_else(ctx
, &ic
);
9651 visit_cf_list(ctx
, &if_stmt
->else_list
);
9653 end_uniform_if(ctx
, &ic
);
9654 } else { /* non-uniform condition */
9656 * To maintain a logical and linear CFG without critical edges,
9657 * non-uniform conditionals are represented in the following way*) :
9662 * BB_THEN (logical) BB_THEN (linear)
9664 * BB_INVERT (linear)
9666 * BB_ELSE (logical) BB_ELSE (linear)
9673 * BB_THEN (logical) BB_ELSE (logical)
9677 * *) Exceptions may be due to break and continue statements within loops
9680 begin_divergent_if_then(ctx
, &ic
, cond
);
9681 visit_cf_list(ctx
, &if_stmt
->then_list
);
9683 begin_divergent_if_else(ctx
, &ic
);
9684 visit_cf_list(ctx
, &if_stmt
->else_list
);
9686 end_divergent_if(ctx
, &ic
);
9689 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9692 static bool visit_cf_list(isel_context
*ctx
,
9693 struct exec_list
*list
)
9695 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9696 switch (node
->type
) {
9697 case nir_cf_node_block
:
9698 visit_block(ctx
, nir_cf_node_as_block(node
));
9700 case nir_cf_node_if
:
9701 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9704 case nir_cf_node_loop
:
9705 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9708 unreachable("unimplemented cf list type");
9714 static void create_null_export(isel_context
*ctx
)
9716 /* Some shader stages always need to have exports.
9717 * So when there is none, we need to add a null export.
9720 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9721 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9722 Builder
bld(ctx
->program
, ctx
->block
);
9723 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9724 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9727 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9729 assert(ctx
->stage
== vertex_vs
||
9730 ctx
->stage
== tess_eval_vs
||
9731 ctx
->stage
== gs_copy_vs
||
9732 ctx
->stage
== ngg_vertex_gs
||
9733 ctx
->stage
== ngg_tess_eval_gs
);
9735 int offset
= (ctx
->stage
& sw_tes
)
9736 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9737 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9738 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9739 if (!is_pos
&& !mask
)
9741 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9743 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9744 exp
->enabled_mask
= mask
;
9745 for (unsigned i
= 0; i
< 4; ++i
) {
9746 if (mask
& (1 << i
))
9747 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9749 exp
->operands
[i
] = Operand(v1
);
9751 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9752 * Setting valid_mask=1 prevents it and has no other effect.
9754 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9756 exp
->compressed
= false;
9758 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9760 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9761 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9766 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9768 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9769 exp
->enabled_mask
= 0;
9770 for (unsigned i
= 0; i
< 4; ++i
)
9771 exp
->operands
[i
] = Operand(v1
);
9772 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9773 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9774 exp
->enabled_mask
|= 0x1;
9776 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9777 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9778 exp
->enabled_mask
|= 0x4;
9780 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9781 if (ctx
->options
->chip_class
< GFX9
) {
9782 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9783 exp
->enabled_mask
|= 0x8;
9785 Builder
bld(ctx
->program
, ctx
->block
);
9787 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9788 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9789 if (exp
->operands
[2].isTemp())
9790 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9792 exp
->operands
[2] = Operand(out
);
9793 exp
->enabled_mask
|= 0x4;
9796 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9798 exp
->compressed
= false;
9799 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9800 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9803 static void create_export_phis(isel_context
*ctx
)
9805 /* Used when exports are needed, but the output temps are defined in a preceding block.
9806 * This function will set up phis in order to access the outputs in the next block.
9809 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9810 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9811 ctx
->block
->instructions
.pop_back();
9813 Builder
bld(ctx
->program
, ctx
->block
);
9815 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9816 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9817 for (unsigned i
= 0; i
< 4; ++i
) {
9818 if (!(mask
& (1 << i
)))
9821 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9822 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9823 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9827 bld
.insert(std::move(logical_start
));
9830 static void create_vs_exports(isel_context
*ctx
)
9832 assert(ctx
->stage
== vertex_vs
||
9833 ctx
->stage
== tess_eval_vs
||
9834 ctx
->stage
== gs_copy_vs
||
9835 ctx
->stage
== ngg_vertex_gs
||
9836 ctx
->stage
== ngg_tess_eval_gs
);
9838 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9839 ? &ctx
->program
->info
->tes
.outinfo
9840 : &ctx
->program
->info
->vs
.outinfo
;
9842 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9843 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9844 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9847 if (ctx
->options
->key
.has_multiview_view_index
) {
9848 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9849 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9852 /* the order these position exports are created is important */
9854 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9855 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9856 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9857 exported_pos
= true;
9859 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9860 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9861 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9862 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9864 if (ctx
->export_clip_dists
) {
9865 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9866 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9867 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9868 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9871 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9872 if (i
< VARYING_SLOT_VAR0
&&
9873 i
!= VARYING_SLOT_LAYER
&&
9874 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9875 i
!= VARYING_SLOT_VIEWPORT
)
9878 export_vs_varying(ctx
, i
, false, NULL
);
9882 create_null_export(ctx
);
9885 static bool export_fs_mrt_z(isel_context
*ctx
)
9887 Builder
bld(ctx
->program
, ctx
->block
);
9888 unsigned enabled_channels
= 0;
9892 for (unsigned i
= 0; i
< 4; ++i
) {
9893 values
[i
] = Operand(v1
);
9896 /* Both stencil and sample mask only need 16-bits. */
9897 if (!ctx
->program
->info
->ps
.writes_z
&&
9898 (ctx
->program
->info
->ps
.writes_stencil
||
9899 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9900 compr
= true; /* COMPR flag */
9902 if (ctx
->program
->info
->ps
.writes_stencil
) {
9903 /* Stencil should be in X[23:16]. */
9904 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9905 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9906 enabled_channels
|= 0x3;
9909 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9910 /* SampleMask should be in Y[15:0]. */
9911 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9912 enabled_channels
|= 0xc;
9915 if (ctx
->program
->info
->ps
.writes_z
) {
9916 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9917 enabled_channels
|= 0x1;
9920 if (ctx
->program
->info
->ps
.writes_stencil
) {
9921 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9922 enabled_channels
|= 0x2;
9925 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9926 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9927 enabled_channels
|= 0x4;
9931 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9932 * writemask component.
9934 if (ctx
->options
->chip_class
== GFX6
&&
9935 ctx
->options
->family
!= CHIP_OLAND
&&
9936 ctx
->options
->family
!= CHIP_HAINAN
) {
9937 enabled_channels
|= 0x1;
9940 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9941 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9946 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9948 Builder
bld(ctx
->program
, ctx
->block
);
9949 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9952 for (unsigned i
= 0; i
< 4; ++i
) {
9953 if (write_mask
& (1 << i
)) {
9954 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9956 values
[i
] = Operand(v1
);
9960 unsigned target
, col_format
;
9961 unsigned enabled_channels
= 0;
9962 aco_opcode compr_op
= (aco_opcode
)0;
9964 slot
-= FRAG_RESULT_DATA0
;
9965 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9966 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9968 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9969 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9970 bool is_16bit
= values
[0].regClass() == v2b
;
9974 case V_028714_SPI_SHADER_ZERO
:
9975 enabled_channels
= 0; /* writemask */
9976 target
= V_008DFC_SQ_EXP_NULL
;
9979 case V_028714_SPI_SHADER_32_R
:
9980 enabled_channels
= 1;
9983 case V_028714_SPI_SHADER_32_GR
:
9984 enabled_channels
= 0x3;
9987 case V_028714_SPI_SHADER_32_AR
:
9988 if (ctx
->options
->chip_class
>= GFX10
) {
9989 /* Special case: on GFX10, the outputs are different for 32_AR */
9990 enabled_channels
= 0x3;
9991 values
[1] = values
[3];
9992 values
[3] = Operand(v1
);
9994 enabled_channels
= 0x9;
9998 case V_028714_SPI_SHADER_FP16_ABGR
:
9999 enabled_channels
= 0x5;
10000 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10002 if (ctx
->options
->chip_class
>= GFX9
) {
10003 /* Pack the FP16 values together instead of converting them to
10004 * FP32 and back to FP16.
10005 * TODO: use p_create_vector and let the compiler optimizes.
10007 compr_op
= aco_opcode::v_pack_b32_f16
;
10009 for (unsigned i
= 0; i
< 4; i
++) {
10010 if ((write_mask
>> i
) & 1)
10011 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10017 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10018 enabled_channels
= 0x5;
10019 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10020 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10022 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10026 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10027 enabled_channels
= 0x5;
10028 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10029 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10031 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10035 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10036 enabled_channels
= 0x5;
10037 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10038 if (is_int8
|| is_int10
) {
10040 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10041 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10043 for (unsigned i
= 0; i
< 4; i
++) {
10044 if ((write_mask
>> i
) & 1) {
10045 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10046 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10050 } else if (is_16bit
) {
10051 for (unsigned i
= 0; i
< 4; i
++) {
10052 if ((write_mask
>> i
) & 1) {
10053 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10054 values
[i
] = Operand(tmp
);
10061 case V_028714_SPI_SHADER_SINT16_ABGR
:
10062 enabled_channels
= 0x5;
10063 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10064 if (is_int8
|| is_int10
) {
10066 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10067 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10068 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10069 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10071 for (unsigned i
= 0; i
< 4; i
++) {
10072 if ((write_mask
>> i
) & 1) {
10073 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10074 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10076 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10077 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10081 } else if (is_16bit
) {
10082 for (unsigned i
= 0; i
< 4; i
++) {
10083 if ((write_mask
>> i
) & 1) {
10084 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10085 values
[i
] = Operand(tmp
);
10091 case V_028714_SPI_SHADER_32_ABGR
:
10092 enabled_channels
= 0xF;
10099 if (target
== V_008DFC_SQ_EXP_NULL
)
10102 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10103 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10105 (col_format
== V_028714_SPI_SHADER_32_R
||
10106 col_format
== V_028714_SPI_SHADER_32_GR
||
10107 col_format
== V_028714_SPI_SHADER_32_AR
||
10108 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10109 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10110 for (int i
= 0; i
< 4; i
++) {
10111 if (!(write_mask
& (1 << i
)))
10114 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10115 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10116 bld
.copy(bld
.def(v1
), Operand(3u)));
10117 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10118 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10122 if ((bool) compr_op
) {
10123 for (int i
= 0; i
< 2; i
++) {
10124 /* check if at least one of the values to be compressed is enabled */
10125 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10127 enabled_channels
|= enabled
<< (i
*2);
10128 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10129 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10130 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10132 values
[i
] = Operand(v1
);
10135 values
[2] = Operand(v1
);
10136 values
[3] = Operand(v1
);
10138 for (int i
= 0; i
< 4; i
++)
10139 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10142 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10143 enabled_channels
, target
, (bool) compr_op
);
10147 static void create_fs_exports(isel_context
*ctx
)
10149 bool exported
= false;
10151 /* Export depth, stencil and sample mask. */
10152 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10153 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10154 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10155 exported
|= export_fs_mrt_z(ctx
);
10157 /* Export all color render targets. */
10158 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10159 if (ctx
->outputs
.mask
[i
])
10160 exported
|= export_fs_mrt_color(ctx
, i
);
10163 create_null_export(ctx
);
10166 static void write_tcs_tess_factors(isel_context
*ctx
)
10168 unsigned outer_comps
;
10169 unsigned inner_comps
;
10171 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10188 Builder
bld(ctx
->program
, ctx
->block
);
10190 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10191 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10192 bld
.sopp(aco_opcode::s_barrier
);
10194 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10195 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10197 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10198 if_context ic_invocation_id_is_zero
;
10199 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10200 bld
.reset(ctx
->block
);
10202 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10204 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10205 unsigned stride
= inner_comps
+ outer_comps
;
10206 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10210 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10212 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10214 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10215 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10216 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10218 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10219 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10221 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10222 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10223 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10224 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10227 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10228 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10229 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10230 unsigned tf_const_offset
= 0;
10232 if (ctx
->program
->chip_class
<= GFX8
) {
10233 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10234 if_context ic_rel_patch_id_is_zero
;
10235 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10236 bld
.reset(ctx
->block
);
10238 /* Store the dynamic HS control word. */
10239 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10240 bld
.mubuf(aco_opcode::buffer_store_dword
,
10241 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10242 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10243 /* disable_wqm */ false, /* glc */ true);
10244 tf_const_offset
+= 4;
10246 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10247 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10248 bld
.reset(ctx
->block
);
10251 assert(stride
== 2 || stride
== 4 || stride
== 6);
10252 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10253 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10255 /* Store to offchip for TES to read - only if TES reads them */
10256 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10257 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10258 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10260 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10261 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10263 if (likely(inner_comps
)) {
10264 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10265 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10269 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10270 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10273 static void emit_stream_output(isel_context
*ctx
,
10274 Temp
const *so_buffers
,
10275 Temp
const *so_write_offset
,
10276 const struct radv_stream_output
*output
)
10278 unsigned num_comps
= util_bitcount(output
->component_mask
);
10279 unsigned writemask
= (1 << num_comps
) - 1;
10280 unsigned loc
= output
->location
;
10281 unsigned buf
= output
->buffer
;
10283 assert(num_comps
&& num_comps
<= 4);
10284 if (!num_comps
|| num_comps
> 4)
10287 unsigned start
= ffs(output
->component_mask
) - 1;
10290 bool all_undef
= true;
10291 assert(ctx
->stage
& hw_vs
);
10292 for (unsigned i
= 0; i
< num_comps
; i
++) {
10293 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10294 all_undef
= all_undef
&& !out
[i
].id();
10299 while (writemask
) {
10301 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10302 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10303 /* GFX6 doesn't support storing vec3, split it. */
10304 writemask
|= 1u << (start
+ 2);
10308 unsigned offset
= output
->offset
+ start
* 4;
10310 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10311 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10312 for (int i
= 0; i
< count
; ++i
)
10313 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10314 vec
->definitions
[0] = Definition(write_data
);
10315 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10320 opcode
= aco_opcode::buffer_store_dword
;
10323 opcode
= aco_opcode::buffer_store_dwordx2
;
10326 opcode
= aco_opcode::buffer_store_dwordx3
;
10329 opcode
= aco_opcode::buffer_store_dwordx4
;
10332 unreachable("Unsupported dword count.");
10335 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10336 store
->operands
[0] = Operand(so_buffers
[buf
]);
10337 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10338 store
->operands
[2] = Operand((uint32_t) 0);
10339 store
->operands
[3] = Operand(write_data
);
10340 if (offset
> 4095) {
10341 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10342 Builder
bld(ctx
->program
, ctx
->block
);
10343 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10345 store
->offset
= offset
;
10347 store
->offen
= true;
10349 store
->dlc
= false;
10351 store
->can_reorder
= true;
10352 ctx
->block
->instructions
.emplace_back(std::move(store
));
10356 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10358 Builder
bld(ctx
->program
, ctx
->block
);
10360 Temp so_buffers
[4];
10361 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10362 for (unsigned i
= 0; i
< 4; i
++) {
10363 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10367 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10368 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10371 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10372 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10374 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10376 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10379 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10381 bld
.reset(ctx
->block
);
10383 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10385 Temp so_write_offset
[4];
10387 for (unsigned i
= 0; i
< 4; i
++) {
10388 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10393 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10394 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10395 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10396 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10398 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10400 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10401 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10402 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10403 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10407 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10408 struct radv_stream_output
*output
=
10409 &ctx
->program
->info
->so
.outputs
[i
];
10410 if (stream
!= output
->stream
)
10413 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10416 begin_divergent_if_else(ctx
, &ic
);
10417 end_divergent_if(ctx
, &ic
);
10420 } /* end namespace */
10422 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10424 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10425 Builder
bld(ctx
->program
, ctx
->block
);
10426 constexpr unsigned hs_idx
= 1u;
10427 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10428 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10429 Operand((8u << 16) | (hs_idx
* 8u)));
10430 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10432 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10434 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10435 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10436 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10437 ls_has_nonzero_hs_threads
);
10438 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10439 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10440 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10441 ls_has_nonzero_hs_threads
);
10442 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10443 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10444 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10445 ls_has_nonzero_hs_threads
);
10447 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10448 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10449 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10452 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10454 /* Split all arguments except for the first (ring_offsets) and the last
10455 * (exec) so that the dead channels don't stay live throughout the program.
10457 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10458 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10459 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10460 startpgm
->definitions
[i
].regClass().size());
10465 void handle_bc_optimize(isel_context
*ctx
)
10467 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10468 Builder
bld(ctx
->program
, ctx
->block
);
10469 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10470 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10471 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10472 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10473 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10474 if (uses_center
&& uses_centroid
) {
10475 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10476 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10478 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10480 for (unsigned i
= 0; i
< 2; i
++) {
10481 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10482 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10483 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10484 persp_centroid
, persp_center
, sel
);
10486 ctx
->persp_centroid
= bld
.tmp(v2
);
10487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10488 Operand(new_coord
[0]), Operand(new_coord
[1]));
10489 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10492 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10494 for (unsigned i
= 0; i
< 2; i
++) {
10495 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10496 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10497 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10498 linear_centroid
, linear_center
, sel
);
10500 ctx
->linear_centroid
= bld
.tmp(v2
);
10501 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10502 Operand(new_coord
[0]), Operand(new_coord
[1]));
10503 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10508 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10510 Program
*program
= ctx
->program
;
10512 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10514 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10515 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10516 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10517 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10518 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10520 program
->next_fp_mode
.must_flush_denorms32
=
10521 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10522 program
->next_fp_mode
.must_flush_denorms16_64
=
10523 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10524 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10526 program
->next_fp_mode
.care_about_round32
=
10527 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10529 program
->next_fp_mode
.care_about_round16_64
=
10530 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10531 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10533 /* default to preserving fp16 and fp64 denorms, since it's free */
10534 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10535 program
->next_fp_mode
.denorm16_64
= 0;
10537 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10539 /* preserving fp32 denorms is expensive, so only do it if asked */
10540 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10541 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10543 program
->next_fp_mode
.denorm32
= 0;
10545 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10546 program
->next_fp_mode
.round32
= fp_round_tz
;
10548 program
->next_fp_mode
.round32
= fp_round_ne
;
10550 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10551 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10553 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10555 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10558 void cleanup_cfg(Program
*program
)
10560 /* create linear_succs/logical_succs */
10561 for (Block
& BB
: program
->blocks
) {
10562 for (unsigned idx
: BB
.linear_preds
)
10563 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10564 for (unsigned idx
: BB
.logical_preds
)
10565 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10569 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10571 Builder
bld(ctx
->program
, ctx
->block
);
10573 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10574 Temp count
= i
== 0
10575 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10576 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10577 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10579 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10582 if (ctx
->program
->wave_size
== 64) {
10583 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10584 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10585 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10587 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10588 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10594 bool ngg_early_prim_export(isel_context
*ctx
)
10596 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10600 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10602 Builder
bld(ctx
->program
, ctx
->block
);
10604 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10605 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10607 /* Get the id of the current wave within the threadgroup (workgroup) */
10608 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10609 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10611 /* Execute the following code only on the first wave (wave id 0),
10612 * use the SCC def to tell if the wave id is zero or not.
10614 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10616 begin_uniform_if_then(ctx
, &ic
, cond
);
10617 begin_uniform_if_else(ctx
, &ic
);
10618 bld
.reset(ctx
->block
);
10620 /* Number of vertices output by VS/TES */
10621 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10622 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10623 /* Number of primitives output by VS/TES */
10624 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10625 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10627 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10628 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10629 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10631 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10632 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10634 end_uniform_if(ctx
, &ic
);
10636 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10637 bld
.reset(ctx
->block
);
10638 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10641 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10643 Builder
bld(ctx
->program
, ctx
->block
);
10645 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10646 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10649 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10652 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10653 assert(vtxindex
[i
].id());
10656 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10660 /* The initial edge flag is always false in tess eval shaders. */
10661 if (ctx
->stage
== ngg_vertex_gs
) {
10662 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10663 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10667 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10672 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10674 Builder
bld(ctx
->program
, ctx
->block
);
10675 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10677 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10678 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10679 false /* compressed */, true/* done */, false /* valid mask */);
10682 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10684 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10685 * These must always come before VS exports.
10687 * It is recommended to do these as early as possible. They can be at the beginning when
10688 * there is no SW GS and the shader doesn't write edge flags.
10692 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10693 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10695 Builder
bld(ctx
->program
, ctx
->block
);
10696 constexpr unsigned max_vertices_per_primitive
= 3;
10697 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10699 if (ctx
->stage
== ngg_vertex_gs
) {
10700 /* TODO: optimize for points & lines */
10701 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10702 if (ctx
->shader
->info
.tess
.point_mode
)
10703 num_vertices_per_primitive
= 1;
10704 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10705 num_vertices_per_primitive
= 2;
10707 unreachable("Unsupported NGG shader stage");
10710 Temp vtxindex
[max_vertices_per_primitive
];
10711 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10712 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10713 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10714 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10715 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10716 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10717 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10718 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10720 /* Export primitive data to the index buffer. */
10721 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10723 /* Export primitive ID. */
10724 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10725 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10726 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10727 Temp provoking_vtx_index
= vtxindex
[0];
10728 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10730 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10733 begin_divergent_if_else(ctx
, &ic
);
10734 end_divergent_if(ctx
, &ic
);
10737 void ngg_emit_nogs_output(isel_context
*ctx
)
10739 /* Emits NGG GS output, for stages that don't have SW GS. */
10742 Builder
bld(ctx
->program
, ctx
->block
);
10743 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10745 /* NGG streamout is currently disabled by default. */
10746 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10748 if (late_prim_export
) {
10749 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10750 create_export_phis(ctx
);
10751 /* Do what we need to do in the GS threads. */
10752 ngg_emit_nogs_gsthreads(ctx
);
10754 /* What comes next should be executed on ES threads. */
10755 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10756 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10757 bld
.reset(ctx
->block
);
10760 /* Export VS outputs */
10761 ctx
->block
->kind
|= block_kind_export_end
;
10762 create_vs_exports(ctx
);
10764 /* Export primitive ID */
10765 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10768 if (ctx
->stage
== ngg_vertex_gs
) {
10769 /* Wait for GS threads to store primitive ID in LDS. */
10770 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10771 bld
.sopp(aco_opcode::s_barrier
);
10773 /* Calculate LDS address where the GS threads stored the primitive ID. */
10774 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10775 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10776 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10777 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10778 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10779 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10781 /* Load primitive ID from LDS. */
10782 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10783 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10784 /* TES: Just use the patch ID as the primitive ID. */
10785 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10787 unreachable("unsupported NGG shader stage.");
10790 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10791 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10793 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10796 if (late_prim_export
) {
10797 begin_divergent_if_else(ctx
, &ic
);
10798 end_divergent_if(ctx
, &ic
);
10799 bld
.reset(ctx
->block
);
10803 void select_program(Program
*program
,
10804 unsigned shader_count
,
10805 struct nir_shader
*const *shaders
,
10806 ac_shader_config
* config
,
10807 struct radv_shader_args
*args
)
10809 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10810 if_context ic_merged_wave_info
;
10811 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10813 for (unsigned i
= 0; i
< shader_count
; i
++) {
10814 nir_shader
*nir
= shaders
[i
];
10815 init_context(&ctx
, nir
);
10817 setup_fp_mode(&ctx
, nir
);
10820 /* needs to be after init_context() for FS */
10821 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10822 append_logical_start(ctx
.block
);
10824 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10825 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10827 split_arguments(&ctx
, startpgm
);
10831 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10833 if (ngg_early_prim_export(&ctx
))
10834 ngg_emit_nogs_gsthreads(&ctx
);
10837 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10838 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10839 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10840 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10841 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10842 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10843 ctx
.stage
== tess_eval_geometry_gs
));
10845 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10846 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10847 if (check_merged_wave_info
) {
10848 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10849 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10853 Builder
bld(ctx
.program
, ctx
.block
);
10855 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10856 bld
.sopp(aco_opcode::s_barrier
);
10858 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10859 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10861 } else if (ctx
.stage
== geometry_gs
)
10862 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10864 if (ctx
.stage
== fragment_fs
)
10865 handle_bc_optimize(&ctx
);
10867 visit_cf_list(&ctx
, &func
->body
);
10869 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10870 emit_streamout(&ctx
, 0);
10872 if (ctx
.stage
& hw_vs
) {
10873 create_vs_exports(&ctx
);
10874 ctx
.block
->kind
|= block_kind_export_end
;
10875 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10876 ngg_emit_nogs_output(&ctx
);
10877 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10878 Builder
bld(ctx
.program
, ctx
.block
);
10879 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10880 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10881 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10882 write_tcs_tess_factors(&ctx
);
10885 if (ctx
.stage
== fragment_fs
) {
10886 create_fs_exports(&ctx
);
10887 ctx
.block
->kind
|= block_kind_export_end
;
10890 if (endif_merged_wave_info
) {
10891 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10892 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10895 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10896 ngg_emit_nogs_output(&ctx
);
10898 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10899 /* Outputs of the previous stage are inputs to the next stage */
10900 ctx
.inputs
= ctx
.outputs
;
10901 ctx
.outputs
= shader_io_state();
10905 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10907 append_logical_end(ctx
.block
);
10908 ctx
.block
->kind
|= block_kind_uniform
;
10909 Builder
bld(ctx
.program
, ctx
.block
);
10910 if (ctx
.program
->wb_smem_l1_on_end
)
10911 bld
.smem(aco_opcode::s_dcache_wb
, false);
10912 bld
.sopp(aco_opcode::s_endpgm
);
10914 cleanup_cfg(program
);
10917 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10918 ac_shader_config
* config
,
10919 struct radv_shader_args
*args
)
10921 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10923 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10924 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10925 program
->next_fp_mode
.must_flush_denorms32
= false;
10926 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10927 program
->next_fp_mode
.care_about_round32
= false;
10928 program
->next_fp_mode
.care_about_round16_64
= false;
10929 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10930 program
->next_fp_mode
.denorm32
= 0;
10931 program
->next_fp_mode
.round32
= fp_round_ne
;
10932 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10933 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10935 add_startpgm(&ctx
);
10936 append_logical_start(ctx
.block
);
10938 Builder
bld(ctx
.program
, ctx
.block
);
10940 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10942 Operand
stream_id(0u);
10943 if (args
->shader_info
->so
.num_outputs
)
10944 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10945 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10947 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10949 std::stack
<Block
> endif_blocks
;
10951 for (unsigned stream
= 0; stream
< 4; stream
++) {
10952 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10955 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10956 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10959 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10961 unsigned BB_if_idx
= ctx
.block
->index
;
10962 Block BB_endif
= Block();
10963 if (!stream_id
.isConstant()) {
10965 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10966 append_logical_end(ctx
.block
);
10967 ctx
.block
->kind
|= block_kind_uniform
;
10968 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10970 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10972 ctx
.block
= ctx
.program
->create_and_insert_block();
10973 add_edge(BB_if_idx
, ctx
.block
);
10974 bld
.reset(ctx
.block
);
10975 append_logical_start(ctx
.block
);
10978 unsigned offset
= 0;
10979 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10980 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10983 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10984 unsigned length
= util_last_bit(output_usage_mask
);
10985 for (unsigned j
= 0; j
< length
; ++j
) {
10986 if (!(output_usage_mask
& (1 << j
)))
10989 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10990 Temp voffset
= vtx_offset
;
10991 if (const_offset
>= 4096u) {
10992 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10993 const_offset
%= 4096u;
10996 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10997 mubuf
->definitions
[0] = bld
.def(v1
);
10998 mubuf
->operands
[0] = Operand(gsvs_ring
);
10999 mubuf
->operands
[1] = Operand(voffset
);
11000 mubuf
->operands
[2] = Operand(0u);
11001 mubuf
->offen
= true;
11002 mubuf
->offset
= const_offset
;
11005 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11006 mubuf
->barrier
= barrier_none
;
11007 mubuf
->can_reorder
= true;
11009 ctx
.outputs
.mask
[i
] |= 1 << j
;
11010 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11012 bld
.insert(std::move(mubuf
));
11018 if (args
->shader_info
->so
.num_outputs
) {
11019 emit_streamout(&ctx
, stream
);
11020 bld
.reset(ctx
.block
);
11024 create_vs_exports(&ctx
);
11025 ctx
.block
->kind
|= block_kind_export_end
;
11028 if (!stream_id
.isConstant()) {
11029 append_logical_end(ctx
.block
);
11031 /* branch from then block to endif block */
11032 bld
.branch(aco_opcode::p_branch
);
11033 add_edge(ctx
.block
->index
, &BB_endif
);
11034 ctx
.block
->kind
|= block_kind_uniform
;
11036 /* emit else block */
11037 ctx
.block
= ctx
.program
->create_and_insert_block();
11038 add_edge(BB_if_idx
, ctx
.block
);
11039 bld
.reset(ctx
.block
);
11040 append_logical_start(ctx
.block
);
11042 endif_blocks
.push(std::move(BB_endif
));
11046 while (!endif_blocks
.empty()) {
11047 Block BB_endif
= std::move(endif_blocks
.top());
11048 endif_blocks
.pop();
11050 Block
*BB_else
= ctx
.block
;
11052 append_logical_end(BB_else
);
11053 /* branch from else block to endif block */
11054 bld
.branch(aco_opcode::p_branch
);
11055 add_edge(BB_else
->index
, &BB_endif
);
11056 BB_else
->kind
|= block_kind_uniform
;
11058 /** emit endif merge block */
11059 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11060 bld
.reset(ctx
.block
);
11061 append_logical_start(ctx
.block
);
11064 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11066 append_logical_end(ctx
.block
);
11067 ctx
.block
->kind
|= block_kind_uniform
;
11068 bld
.sopp(aco_opcode::s_endpgm
);
11070 cleanup_cfg(program
);