src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <map>
  29
  30 #include "ac_shader_util.h"
  31 #include "aco_ir.h"
  32 #include "aco_builder.h"
  33 #include "aco_interface.h"
  34 #include "aco_instruction_selection_setup.cpp"
  35 #include "util/fast_idiv_by_const.h"
  36
  37 namespace aco {
  38 namespace {
  39
  40 class loop_info_RAII {
  41    isel_context* ctx;
  42    unsigned header_idx_old;
  43    Block* exit_old;
  44    bool divergent_cont_old;
  45    bool divergent_branch_old;
  46    bool divergent_if_old;
  47
  48 public:
  49    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  50       : ctx(ctx),
  51         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  52         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  53         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  54         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  55    {
  56       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  57       ctx->cf_info.parent_loop.exit = loop_exit;
  58       ctx->cf_info.parent_loop.has_divergent_continue = false;
  59       ctx->cf_info.parent_loop.has_divergent_branch = false;
  60       ctx->cf_info.parent_if.is_divergent = false;
  61       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  62    }
  63
  64    ~loop_info_RAII()
  65    {
  66       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  67       ctx->cf_info.parent_loop.exit = exit_old;
  68       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  69       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  70       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  71       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  72       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  73          ctx->cf_info.exec_potentially_empty = false;
  74    }
  75 };
  76
  77 struct if_context {
  78    Temp cond;
  79
  80    bool divergent_old;
  81    bool exec_potentially_empty_old;
  82
  83    unsigned BB_if_idx;
  84    unsigned invert_idx;
  85    bool then_branch_divergent;
  86    Block BB_invert;
  87    Block BB_endif;
  88 };
  89
  90 static void visit_cf_list(struct isel_context *ctx,
  91                           struct exec_list *list);
  92
  93 static void add_logical_edge(unsigned pred_idx, Block *succ)
  94 {
  95    succ->logical_preds.emplace_back(pred_idx);
  96 }
  97
  98
  99 static void add_linear_edge(unsigned pred_idx, Block *succ)
 100 {
 101    succ->linear_preds.emplace_back(pred_idx);
 102 }
 103
 104 static void add_edge(unsigned pred_idx, Block *succ)
 105 {
 106    add_logical_edge(pred_idx, succ);
 107    add_linear_edge(pred_idx, succ);
 108 }
 109
 110 static void append_logical_start(Block *b)
 111 {
 112    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 113 }
 114
 115 static void append_logical_end(Block *b)
 116 {
 117    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 118 }
 119
 120 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 121 {
 122    assert(ctx->allocated[def->index].id());
 123    return ctx->allocated[def->index];
 124 }
 125
 126 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 127                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 128 {
 129    Builder bld(ctx->program, ctx->block);
 130    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 131    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 132
 133    if (ctx->program->wave_size == 32) {
 134       return thread_id_lo;
 135    } else {
 136       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 137       return thread_id_hi;
 138    }
 139 }
 140
 141 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 142 {
 143    Builder bld(ctx->program, ctx->block);
 144
 145    if (!dst.id())
 146       dst = bld.tmp(src.regClass());
 147
 148    assert(src.size() == dst.size());
 149
 150    if (ctx->stage != fragment_fs) {
 151       if (!dst.id())
 152          return src;
 153
 154       bld.copy(Definition(dst), src);
 155       return dst;
 156    }
 157
 158    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 159    ctx->program->needs_wqm |= program_needs_wqm;
 160    return dst;
 161 }
 162
 163 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 164 {
 165    if (index.regClass() == s1)
 166       return bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), data, index);
 167
 168    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 169
 170    /* Currently not implemented on GFX6-7 */
 171    assert(ctx->options->chip_class >= GFX8);
 172
 173    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 174       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 175    }
 176
 177    /* GFX10, wave64 mode:
 178     * The bpermute instruction is limited to half-wave operation, which means that it can't
 179     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 180     * emulate it here.
 181     */
 182    if (!ctx->has_gfx10_wave64_bpermute) {
 183       ctx->has_gfx10_wave64_bpermute = true;
 184       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 185       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 186    }
 187
 188    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 189    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 190    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 191    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2, vcc), lane_is_hi, index_is_hi);
 192
 193    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 194                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 195 }
 196
 197 Temp as_vgpr(isel_context *ctx, Temp val)
 198 {
 199    if (val.type() == RegType::sgpr) {
 200       Builder bld(ctx->program, ctx->block);
 201       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 202    }
 203    assert(val.type() == RegType::vgpr);
 204    return val;
 205 }
 206
 207 //assumes a != 0xffffffff
 208 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 209 {
 210    assert(b != 0);
 211    Builder bld(ctx->program, ctx->block);
 212
 213    if (util_is_power_of_two_or_zero(b)) {
 214       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 215       return;
 216    }
 217
 218    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 219
 220    assert(info.multiplier <= 0xffffffff);
 221
 222    bool pre_shift = info.pre_shift != 0;
 223    bool increment = info.increment != 0;
 224    bool multiply = true;
 225    bool post_shift = info.post_shift != 0;
 226
 227    if (!pre_shift && !increment && !multiply && !post_shift) {
 228       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 229       return;
 230    }
 231
 232    Temp pre_shift_dst = a;
 233    if (pre_shift) {
 234       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 235       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 236    }
 237
 238    Temp increment_dst = pre_shift_dst;
 239    if (increment) {
 240       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 241       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 242    }
 243
 244    Temp multiply_dst = increment_dst;
 245    if (multiply) {
 246       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 247       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 248                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 249    }
 250
 251    if (post_shift) {
 252       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 253    }
 254 }
 255
 256 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 257 {
 258    Builder bld(ctx->program, ctx->block);
 259    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 260 }
 261
 262
 263 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 264 {
 265    /* no need to extract the whole vector */
 266    if (src.regClass() == dst_rc) {
 267       assert(idx == 0);
 268       return src;
 269    }
 270    assert(src.size() > idx);
 271    Builder bld(ctx->program, ctx->block);
 272    auto it = ctx->allocated_vec.find(src.id());
 273    /* the size check needs to be early because elements other than 0 may be garbage */
 274    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 275       if (it->second[idx].regClass() == dst_rc) {
 276          return it->second[idx];
 277       } else {
 278          assert(dst_rc.size() == it->second[idx].regClass().size());
 279          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 280          return bld.copy(bld.def(dst_rc), it->second[idx]);
 281       }
 282    }
 283
 284    if (src.size() == dst_rc.size()) {
 285       assert(idx == 0);
 286       return bld.copy(bld.def(dst_rc), src);
 287    } else {
 288       Temp dst = bld.tmp(dst_rc);
 289       emit_extract_vector(ctx, src, idx, dst);
 290       return dst;
 291    }
 292 }
 293
 294 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 295 {
 296    if (num_components == 1)
 297       return;
 298    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 299       return;
 300    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 301    split->operands[0] = Operand(vec_src);
 302    std::array<Temp,4> elems;
 303    for (unsigned i = 0; i < num_components; i++) {
 304       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 305       split->definitions[i] = Definition(elems[i]);
 306    }
 307    ctx->block->instructions.emplace_back(std::move(split));
 308    ctx->allocated_vec.emplace(vec_src.id(), elems);
 309 }
 310
 311 /* This vector expansion uses a mask to determine which elements in the new vector
 312  * come from the original vector. The other elements are undefined. */
 313 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 314 {
 315    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 316
 317    if (vec_src == dst)
 318       return;
 319
 320    Builder bld(ctx->program, ctx->block);
 321    if (num_components == 1) {
 322       if (dst.type() == RegType::sgpr)
 323          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 324       else
 325          bld.copy(Definition(dst), vec_src);
 326       return;
 327    }
 328
 329    unsigned component_size = dst.size() / num_components;
 330    std::array<Temp,4> elems;
 331
 332    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 333    vec->definitions[0] = Definition(dst);
 334    unsigned k = 0;
 335    for (unsigned i = 0; i < num_components; i++) {
 336       if (mask & (1 << i)) {
 337          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 338          if (dst.type() == RegType::sgpr)
 339             src = bld.as_uniform(src);
 340          vec->operands[i] = Operand(src);
 341       } else {
 342          vec->operands[i] = Operand(0u);
 343       }
 344       elems[i] = vec->operands[i].getTemp();
 345    }
 346    ctx->block->instructions.emplace_back(std::move(vec));
 347    ctx->allocated_vec.emplace(dst.id(), elems);
 348 }
 349
 350 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 351 {
 352    Builder bld(ctx->program, ctx->block);
 353    if (!dst.id())
 354       dst = bld.tmp(bld.lm);
 355
 356    assert(val.regClass() == s1);
 357    assert(dst.regClass() == bld.lm);
 358
 359    return bld.sop2(Builder::s_cselect, bld.hint_vcc(Definition(dst)), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 360 }
 361
 362 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 363 {
 364    Builder bld(ctx->program, ctx->block);
 365    if (!dst.id())
 366       dst = bld.tmp(s1);
 367
 368    assert(val.regClass() == bld.lm);
 369    assert(dst.regClass() == s1);
 370
 371    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 372    Temp tmp = bld.tmp(s1);
 373    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 374    return emit_wqm(ctx, tmp, dst);
 375 }
 376
 377 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 378 {
 379    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 380       return get_ssa_temp(ctx, src.src.ssa);
 381
 382    if (src.src.ssa->num_components == size) {
 383       bool identity_swizzle = true;
 384       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 385          if (src.swizzle[i] != i)
 386             identity_swizzle = false;
 387       }
 388       if (identity_swizzle)
 389          return get_ssa_temp(ctx, src.src.ssa);
 390    }
 391
 392    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 393    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 394    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 395    assert(vec.size() % elem_size == 0);
 396
 397    RegClass elem_rc = RegClass(vec.type(), elem_size);
 398    if (size == 1) {
 399       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 400    } else {
 401       assert(size <= 4);
 402       std::array<Temp,4> elems;
 403       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 404       for (unsigned i = 0; i < size; ++i) {
 405          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 406          vec_instr->operands[i] = Operand{elems[i]};
 407       }
 408       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 409       vec_instr->definitions[0] = Definition(dst);
 410       ctx->block->instructions.emplace_back(std::move(vec_instr));
 411       ctx->allocated_vec.emplace(dst.id(), elems);
 412       return dst;
 413    }
 414 }
 415
 416 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 417 {
 418    if (ptr.size() == 2)
 419       return ptr;
 420    Builder bld(ctx->program, ctx->block);
 421    if (ptr.type() == RegType::vgpr)
 422       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 423    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 424                      ptr, Operand((unsigned)ctx->options->address32_hi));
 425 }
 426
 427 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 428 {
 429    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 430    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 431    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 432    sop2->definitions[0] = Definition(dst);
 433    if (writes_scc)
 434       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 435    ctx->block->instructions.emplace_back(std::move(sop2));
 436 }
 437
 438 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool commutative, bool swap_srcs=false)
 439 {
 440    Builder bld(ctx->program, ctx->block);
 441    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 442    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 443    if (src1.type() == RegType::sgpr) {
 444       if (commutative && src0.type() == RegType::vgpr) {
 445          Temp t = src0;
 446          src0 = src1;
 447          src1 = t;
 448       } else if (src0.type() == RegType::vgpr &&
 449                  op != aco_opcode::v_madmk_f32 &&
 450                  op != aco_opcode::v_madak_f32 &&
 451                  op != aco_opcode::v_madmk_f16 &&
 452                  op != aco_opcode::v_madak_f16) {
 453          /* If the instruction is not commutative, we emit a VOP3A instruction */
 454          bld.vop2_e64(op, Definition(dst), src0, src1);
 455          return;
 456       } else {
 457          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 458       }
 459    }
 460    bld.vop2(op, Definition(dst), src0, src1);
 461 }
 462
 463 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 464 {
 465    Temp src0 = get_alu_src(ctx, instr->src[0]);
 466    Temp src1 = get_alu_src(ctx, instr->src[1]);
 467    Temp src2 = get_alu_src(ctx, instr->src[2]);
 468
 469    /* ensure that the instruction has at most 1 sgpr operand
 470     * The optimizer will inline constants for us */
 471    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 472       src0 = as_vgpr(ctx, src0);
 473    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 474       src1 = as_vgpr(ctx, src1);
 475    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 476       src2 = as_vgpr(ctx, src2);
 477
 478    Builder bld(ctx->program, ctx->block);
 479    bld.vop3(op, Definition(dst), src0, src1, src2);
 480 }
 481
 482 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 483 {
 484    Builder bld(ctx->program, ctx->block);
 485    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 486 }
 487
 488 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 489 {
 490    Temp src0 = get_alu_src(ctx, instr->src[0]);
 491    Temp src1 = get_alu_src(ctx, instr->src[1]);
 492    assert(src0.size() == src1.size());
 493
 494    aco_ptr<Instruction> vopc;
 495    if (src1.type() == RegType::sgpr) {
 496       if (src0.type() == RegType::vgpr) {
 497          /* to swap the operands, we might also have to change the opcode */
 498          switch (op) {
 499             case aco_opcode::v_cmp_lt_f32:
 500                op = aco_opcode::v_cmp_gt_f32;
 501                break;
 502             case aco_opcode::v_cmp_ge_f32:
 503                op = aco_opcode::v_cmp_le_f32;
 504                break;
 505             case aco_opcode::v_cmp_lt_i32:
 506                op = aco_opcode::v_cmp_gt_i32;
 507                break;
 508             case aco_opcode::v_cmp_ge_i32:
 509                op = aco_opcode::v_cmp_le_i32;
 510                break;
 511             case aco_opcode::v_cmp_lt_u32:
 512                op = aco_opcode::v_cmp_gt_u32;
 513                break;
 514             case aco_opcode::v_cmp_ge_u32:
 515                op = aco_opcode::v_cmp_le_u32;
 516                break;
 517             case aco_opcode::v_cmp_lt_f64:
 518                op = aco_opcode::v_cmp_gt_f64;
 519                break;
 520             case aco_opcode::v_cmp_ge_f64:
 521                op = aco_opcode::v_cmp_le_f64;
 522                break;
 523             case aco_opcode::v_cmp_lt_i64:
 524                op = aco_opcode::v_cmp_gt_i64;
 525                break;
 526             case aco_opcode::v_cmp_ge_i64:
 527                op = aco_opcode::v_cmp_le_i64;
 528                break;
 529             case aco_opcode::v_cmp_lt_u64:
 530                op = aco_opcode::v_cmp_gt_u64;
 531                break;
 532             case aco_opcode::v_cmp_ge_u64:
 533                op = aco_opcode::v_cmp_le_u64;
 534                break;
 535             default: /* eq and ne are commutative */
 536                break;
 537          }
 538          Temp t = src0;
 539          src0 = src1;
 540          src1 = t;
 541       } else {
 542          src1 = as_vgpr(ctx, src1);
 543       }
 544    }
 545
 546    Builder bld(ctx->program, ctx->block);
 547    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 548 }
 549
 550 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 551 {
 552    Temp src0 = get_alu_src(ctx, instr->src[0]);
 553    Temp src1 = get_alu_src(ctx, instr->src[1]);
 554    Builder bld(ctx->program, ctx->block);
 555
 556    assert(dst.regClass() == bld.lm);
 557    assert(src0.type() == RegType::sgpr);
 558    assert(src1.type() == RegType::sgpr);
 559    assert(src0.regClass() == src1.regClass());
 560
 561    /* Emit the SALU comparison instruction */
 562    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 563    /* Turn the result into a per-lane bool */
 564    bool_to_vector_condition(ctx, cmp, dst);
 565 }
 566
 567 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 568                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::last_opcode, aco_opcode s64_op = aco_opcode::last_opcode)
 569 {
 570    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 571    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 572    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 573    bool use_valu = s_op == aco_opcode::last_opcode ||
 574                    divergent_vals ||
 575                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 576                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 577    aco_opcode op = use_valu ? v_op : s_op;
 578    assert(op != aco_opcode::last_opcode);
 579
 580    if (use_valu)
 581       emit_vopc_instruction(ctx, instr, op, dst);
 582    else
 583       emit_sopc_instruction(ctx, instr, op, dst);
 584 }
 585
 586 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 587 {
 588    Builder bld(ctx->program, ctx->block);
 589    Temp src0 = get_alu_src(ctx, instr->src[0]);
 590    Temp src1 = get_alu_src(ctx, instr->src[1]);
 591
 592    assert(dst.regClass() == bld.lm);
 593    assert(src0.regClass() == bld.lm);
 594    assert(src1.regClass() == bld.lm);
 595
 596    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 597 }
 598
 599 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 600 {
 601    Builder bld(ctx->program, ctx->block);
 602    Temp cond = get_alu_src(ctx, instr->src[0]);
 603    Temp then = get_alu_src(ctx, instr->src[1]);
 604    Temp els = get_alu_src(ctx, instr->src[2]);
 605
 606    assert(cond.regClass() == bld.lm);
 607
 608    if (dst.type() == RegType::vgpr) {
 609       aco_ptr<Instruction> bcsel;
 610       if (dst.size() == 1) {
 611          then = as_vgpr(ctx, then);
 612          els = as_vgpr(ctx, els);
 613
 614          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 615       } else if (dst.size() == 2) {
 616          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 617          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 618          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 619          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 620
 621          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 622          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 623
 624          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 625       } else {
 626          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 627          nir_print_instr(&instr->instr, stderr);
 628          fprintf(stderr, "\n");
 629       }
 630       return;
 631    }
 632
 633    if (instr->dest.dest.ssa.bit_size == 1) {
 634       assert(dst.regClass() == bld.lm);
 635       assert(then.regClass() == bld.lm);
 636       assert(els.regClass() == bld.lm);
 637    }
 638
 639    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 640       if (dst.regClass() == s1 || dst.regClass() == s2) {
 641          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 642          assert(dst.size() == then.size());
 643          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 644          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 645       } else {
 646          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 647          nir_print_instr(&instr->instr, stderr);
 648          fprintf(stderr, "\n");
 649       }
 650       return;
 651    }
 652
 653    /* divergent boolean bcsel
 654     * this implements bcsel on bools: dst = s0 ? s1 : s2
 655     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 656    assert(instr->dest.dest.ssa.bit_size == 1);
 657
 658    if (cond.id() != then.id())
 659       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 660
 661    if (cond.id() == els.id())
 662       bld.sop1(Builder::s_mov, Definition(dst), then);
 663    else
 664       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 665                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 666 }
 667
 668 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 669                     aco_opcode op, uint32_t undo)
 670 {
 671    /* multiply by 16777216 to handle denormals */
 672    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 673                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 674    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 675    scaled = bld.vop1(op, bld.def(v1), scaled);
 676    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 677
 678    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 679
 680    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 681 }
 682
 683 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 684 {
 685    if (ctx->block->fp_mode.denorm32 == 0) {
 686       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 687       return;
 688    }
 689
 690    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 691 }
 692
 693 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 694 {
 695    if (ctx->block->fp_mode.denorm32 == 0) {
 696       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 697       return;
 698    }
 699
 700    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 701 }
 702
 703 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 704 {
 705    if (ctx->block->fp_mode.denorm32 == 0) {
 706       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 707       return;
 708    }
 709
 710    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 711 }
 712
 713 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 714 {
 715    if (ctx->block->fp_mode.denorm32 == 0) {
 716       bld.vop1(aco_opcode::v_log_f32, dst, val);
 717       return;
 718    }
 719
 720    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 721 }
 722
 723 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 724 {
 725    if (!instr->dest.dest.is_ssa) {
 726       fprintf(stderr, "nir alu dst not in ssa: ");
 727       nir_print_instr(&instr->instr, stderr);
 728       fprintf(stderr, "\n");
 729       abort();
 730    }
 731    Builder bld(ctx->program, ctx->block);
 732    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 733    switch(instr->op) {
 734    case nir_op_vec2:
 735    case nir_op_vec3:
 736    case nir_op_vec4: {
 737       std::array<Temp,4> elems;
 738       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 739       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 740          elems[i] = get_alu_src(ctx, instr->src[i]);
 741          vec->operands[i] = Operand{elems[i]};
 742       }
 743       vec->definitions[0] = Definition(dst);
 744       ctx->block->instructions.emplace_back(std::move(vec));
 745       ctx->allocated_vec.emplace(dst.id(), elems);
 746       break;
 747    }
 748    case nir_op_mov: {
 749       Temp src = get_alu_src(ctx, instr->src[0]);
 750       aco_ptr<Instruction> mov;
 751       if (dst.type() == RegType::sgpr) {
 752          if (src.type() == RegType::vgpr)
 753             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 754          else if (src.regClass() == s1)
 755             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 756          else if (src.regClass() == s2)
 757             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 758          else
 759             unreachable("wrong src register class for nir_op_imov");
 760       } else if (dst.regClass() == v1) {
 761          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 762       } else if (dst.regClass() == v2) {
 763          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 764       } else {
 765          nir_print_instr(&instr->instr, stderr);
 766          unreachable("Should have been lowered to scalar.");
 767       }
 768       break;
 769    }
 770    case nir_op_inot: {
 771       Temp src = get_alu_src(ctx, instr->src[0]);
 772       if (instr->dest.dest.ssa.bit_size == 1) {
 773          assert(src.regClass() == bld.lm);
 774          assert(dst.regClass() == bld.lm);
 775          bld.sop2(Builder::s_andn2, Definition(dst), bld.def(s1, scc), Operand(exec, bld.lm), src);
 776       } else if (dst.regClass() == v1) {
 777          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 778       } else if (dst.type() == RegType::sgpr) {
 779          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 780          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 781       } else {
 782          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 783          nir_print_instr(&instr->instr, stderr);
 784          fprintf(stderr, "\n");
 785       }
 786       break;
 787    }
 788    case nir_op_ineg: {
 789       Temp src = get_alu_src(ctx, instr->src[0]);
 790       if (dst.regClass() == v1) {
 791          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 792       } else if (dst.regClass() == s1) {
 793          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 794       } else if (dst.size() == 2) {
 795          Temp src0 = bld.tmp(dst.type(), 1);
 796          Temp src1 = bld.tmp(dst.type(), 1);
 797          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 798
 799          if (dst.regClass() == s2) {
 800             Temp carry = bld.tmp(s1);
 801             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 802             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 803             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 804          } else {
 805             Temp lower = bld.tmp(v1);
 806             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 807             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 808             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 809          }
 810       } else {
 811          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 812          nir_print_instr(&instr->instr, stderr);
 813          fprintf(stderr, "\n");
 814       }
 815       break;
 816    }
 817    case nir_op_iabs: {
 818       if (dst.regClass() == s1) {
 819          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 820       } else if (dst.regClass() == v1) {
 821          Temp src = get_alu_src(ctx, instr->src[0]);
 822          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 823       } else {
 824          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 825          nir_print_instr(&instr->instr, stderr);
 826          fprintf(stderr, "\n");
 827       }
 828       break;
 829    }
 830    case nir_op_isign: {
 831       Temp src = get_alu_src(ctx, instr->src[0]);
 832       if (dst.regClass() == s1) {
 833          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 834          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 835          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 836       } else if (dst.regClass() == s2) {
 837          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 838          Temp neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 839          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, neqz);
 840       } else if (dst.regClass() == v1) {
 841          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 842          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 843          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 844       } else if (dst.regClass() == v2) {
 845          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 846          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 847          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 848          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 849          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 850          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 851       } else {
 852          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 853          nir_print_instr(&instr->instr, stderr);
 854          fprintf(stderr, "\n");
 855       }
 856       break;
 857    }
 858    case nir_op_imax: {
 859       if (dst.regClass() == v1) {
 860          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 861       } else if (dst.regClass() == s1) {
 862          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 863       } else {
 864          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 865          nir_print_instr(&instr->instr, stderr);
 866          fprintf(stderr, "\n");
 867       }
 868       break;
 869    }
 870    case nir_op_umax: {
 871       if (dst.regClass() == v1) {
 872          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 873       } else if (dst.regClass() == s1) {
 874          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 875       } else {
 876          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 877          nir_print_instr(&instr->instr, stderr);
 878          fprintf(stderr, "\n");
 879       }
 880       break;
 881    }
 882    case nir_op_imin: {
 883       if (dst.regClass() == v1) {
 884          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 885       } else if (dst.regClass() == s1) {
 886          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 887       } else {
 888          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 889          nir_print_instr(&instr->instr, stderr);
 890          fprintf(stderr, "\n");
 891       }
 892       break;
 893    }
 894    case nir_op_umin: {
 895       if (dst.regClass() == v1) {
 896          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 897       } else if (dst.regClass() == s1) {
 898          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
 899       } else {
 900          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 901          nir_print_instr(&instr->instr, stderr);
 902          fprintf(stderr, "\n");
 903       }
 904       break;
 905    }
 906    case nir_op_ior: {
 907       if (instr->dest.dest.ssa.bit_size == 1) {
 908          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
 909       } else if (dst.regClass() == v1) {
 910          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
 911       } else if (dst.regClass() == s1) {
 912          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
 913       } else if (dst.regClass() == s2) {
 914          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
 915       } else {
 916          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 917          nir_print_instr(&instr->instr, stderr);
 918          fprintf(stderr, "\n");
 919       }
 920       break;
 921    }
 922    case nir_op_iand: {
 923       if (instr->dest.dest.ssa.bit_size == 1) {
 924          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
 925       } else if (dst.regClass() == v1) {
 926          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
 927       } else if (dst.regClass() == s1) {
 928          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
 929       } else if (dst.regClass() == s2) {
 930          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
 931       } else {
 932          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 933          nir_print_instr(&instr->instr, stderr);
 934          fprintf(stderr, "\n");
 935       }
 936       break;
 937    }
 938    case nir_op_ixor: {
 939       if (instr->dest.dest.ssa.bit_size == 1) {
 940          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
 941       } else if (dst.regClass() == v1) {
 942          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
 943       } else if (dst.regClass() == s1) {
 944          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
 945       } else if (dst.regClass() == s2) {
 946          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
 947       } else {
 948          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 949          nir_print_instr(&instr->instr, stderr);
 950          fprintf(stderr, "\n");
 951       }
 952       break;
 953    }
 954    case nir_op_ushr: {
 955       if (dst.regClass() == v1) {
 956          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
 957       } else if (dst.regClass() == v2) {
 958          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
 959                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 960       } else if (dst.regClass() == s2) {
 961          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_ishl: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
 974       } else if (dst.regClass() == v2) {
 975          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
 976                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 977       } else if (dst.regClass() == s1) {
 978          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
 979       } else if (dst.regClass() == s2) {
 980          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
 981       } else {
 982          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 983          nir_print_instr(&instr->instr, stderr);
 984          fprintf(stderr, "\n");
 985       }
 986       break;
 987    }
 988    case nir_op_ishr: {
 989       if (dst.regClass() == v1) {
 990          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
 991       } else if (dst.regClass() == v2) {
 992          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
 993                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 994       } else if (dst.regClass() == s1) {
 995          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
 996       } else if (dst.regClass() == s2) {
 997          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
 998       } else {
 999          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1000          nir_print_instr(&instr->instr, stderr);
1001          fprintf(stderr, "\n");
1002       }
1003       break;
1004    }
1005    case nir_op_find_lsb: {
1006       Temp src = get_alu_src(ctx, instr->src[0]);
1007       if (src.regClass() == s1) {
1008          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1009       } else if (src.regClass() == v1) {
1010          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1011       } else if (src.regClass() == s2) {
1012          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1013       } else {
1014          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1015          nir_print_instr(&instr->instr, stderr);
1016          fprintf(stderr, "\n");
1017       }
1018       break;
1019    }
1020    case nir_op_ufind_msb:
1021    case nir_op_ifind_msb: {
1022       Temp src = get_alu_src(ctx, instr->src[0]);
1023       if (src.regClass() == s1 || src.regClass() == s2) {
1024          aco_opcode op = src.regClass() == s2 ?
1025                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1026                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1027          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1028
1029          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1030                                         Operand(src.size() * 32u - 1u), msb_rev);
1031          Temp msb = sub.def(0).getTemp();
1032          Temp carry = sub.def(1).getTemp();
1033
1034          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, carry);
1035       } else if (src.regClass() == v1) {
1036          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1037          Temp msb_rev = bld.tmp(v1);
1038          emit_vop1_instruction(ctx, instr, op, msb_rev);
1039          Temp msb = bld.tmp(v1);
1040          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1041          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1042       } else {
1043          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1044          nir_print_instr(&instr->instr, stderr);
1045          fprintf(stderr, "\n");
1046       }
1047       break;
1048    }
1049    case nir_op_bitfield_reverse: {
1050       if (dst.regClass() == s1) {
1051          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1052       } else if (dst.regClass() == v1) {
1053          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1054       } else {
1055          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1056          nir_print_instr(&instr->instr, stderr);
1057          fprintf(stderr, "\n");
1058       }
1059       break;
1060    }
1061    case nir_op_iadd: {
1062       if (dst.regClass() == s1) {
1063          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1064          break;
1065       }
1066
1067       Temp src0 = get_alu_src(ctx, instr->src[0]);
1068       Temp src1 = get_alu_src(ctx, instr->src[1]);
1069       if (dst.regClass() == v1) {
1070          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1071          break;
1072       }
1073
1074       assert(src0.size() == 2 && src1.size() == 2);
1075       Temp src00 = bld.tmp(src0.type(), 1);
1076       Temp src01 = bld.tmp(dst.type(), 1);
1077       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1078       Temp src10 = bld.tmp(src1.type(), 1);
1079       Temp src11 = bld.tmp(dst.type(), 1);
1080       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1081
1082       if (dst.regClass() == s2) {
1083          Temp carry = bld.tmp(s1);
1084          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1085          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1086          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1087       } else if (dst.regClass() == v2) {
1088          Temp dst0 = bld.tmp(v1);
1089          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1090          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1091          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1092       } else {
1093          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1094          nir_print_instr(&instr->instr, stderr);
1095          fprintf(stderr, "\n");
1096       }
1097       break;
1098    }
1099    case nir_op_uadd_sat: {
1100       Temp src0 = get_alu_src(ctx, instr->src[0]);
1101       Temp src1 = get_alu_src(ctx, instr->src[1]);
1102       if (dst.regClass() == s1) {
1103          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1104          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1105                   src0, src1);
1106          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1107       } else if (dst.regClass() == v1) {
1108          if (ctx->options->chip_class >= GFX9) {
1109             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1110             add->operands[0] = Operand(src0);
1111             add->operands[1] = Operand(src1);
1112             add->definitions[0] = Definition(dst);
1113             add->clamp = 1;
1114             ctx->block->instructions.emplace_back(std::move(add));
1115          } else {
1116             if (src1.regClass() != v1)
1117                std::swap(src0, src1);
1118             assert(src1.regClass() == v1);
1119             Temp tmp = bld.tmp(v1);
1120             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1121             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1122          }
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_uadd_carry: {
1131       Temp src0 = get_alu_src(ctx, instr->src[0]);
1132       Temp src1 = get_alu_src(ctx, instr->src[1]);
1133       if (dst.regClass() == s1) {
1134          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1135          break;
1136       }
1137       if (dst.regClass() == v1) {
1138          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1139          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1140          break;
1141       }
1142
1143       Temp src00 = bld.tmp(src0.type(), 1);
1144       Temp src01 = bld.tmp(dst.type(), 1);
1145       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1146       Temp src10 = bld.tmp(src1.type(), 1);
1147       Temp src11 = bld.tmp(dst.type(), 1);
1148       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1149       if (dst.regClass() == s2) {
1150          Temp carry = bld.tmp(s1);
1151          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1152          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1153          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1154       } else if (dst.regClass() == v2) {
1155          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1156          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1157          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1158          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1159       } else {
1160          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1161          nir_print_instr(&instr->instr, stderr);
1162          fprintf(stderr, "\n");
1163       }
1164       break;
1165    }
1166    case nir_op_isub: {
1167       if (dst.regClass() == s1) {
1168          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1169          break;
1170       }
1171
1172       Temp src0 = get_alu_src(ctx, instr->src[0]);
1173       Temp src1 = get_alu_src(ctx, instr->src[1]);
1174       if (dst.regClass() == v1) {
1175          bld.vsub32(Definition(dst), src0, src1);
1176          break;
1177       }
1178
1179       Temp src00 = bld.tmp(src0.type(), 1);
1180       Temp src01 = bld.tmp(dst.type(), 1);
1181       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1182       Temp src10 = bld.tmp(src1.type(), 1);
1183       Temp src11 = bld.tmp(dst.type(), 1);
1184       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1185       if (dst.regClass() == s2) {
1186          Temp carry = bld.tmp(s1);
1187          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1188          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1189          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1190       } else if (dst.regClass() == v2) {
1191          Temp lower = bld.tmp(v1);
1192          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1193          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1194          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1195       } else {
1196          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1197          nir_print_instr(&instr->instr, stderr);
1198          fprintf(stderr, "\n");
1199       }
1200       break;
1201    }
1202    case nir_op_usub_borrow: {
1203       Temp src0 = get_alu_src(ctx, instr->src[0]);
1204       Temp src1 = get_alu_src(ctx, instr->src[1]);
1205       if (dst.regClass() == s1) {
1206          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1207          break;
1208       } else if (dst.regClass() == v1) {
1209          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1210          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1211          break;
1212       }
1213
1214       Temp src00 = bld.tmp(src0.type(), 1);
1215       Temp src01 = bld.tmp(dst.type(), 1);
1216       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1217       Temp src10 = bld.tmp(src1.type(), 1);
1218       Temp src11 = bld.tmp(dst.type(), 1);
1219       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1220       if (dst.regClass() == s2) {
1221          Temp borrow = bld.tmp(s1);
1222          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1223          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1224          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1225       } else if (dst.regClass() == v2) {
1226          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1227          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1228          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1229          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1230       } else {
1231          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1232          nir_print_instr(&instr->instr, stderr);
1233          fprintf(stderr, "\n");
1234       }
1235       break;
1236    }
1237    case nir_op_imul: {
1238       if (dst.regClass() == v1) {
1239          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1240                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1241       } else if (dst.regClass() == s1) {
1242          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1243       } else {
1244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1245          nir_print_instr(&instr->instr, stderr);
1246          fprintf(stderr, "\n");
1247       }
1248       break;
1249    }
1250    case nir_op_umul_high: {
1251       if (dst.regClass() == v1) {
1252          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1253       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1254          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1255       } else if (dst.regClass() == s1) {
1256          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1257                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1258          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1259       } else {
1260          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1261          nir_print_instr(&instr->instr, stderr);
1262          fprintf(stderr, "\n");
1263       }
1264       break;
1265    }
1266    case nir_op_imul_high: {
1267       if (dst.regClass() == v1) {
1268          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1269       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1270          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1271       } else if (dst.regClass() == s1) {
1272          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1273                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1274          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1275       } else {
1276          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1277          nir_print_instr(&instr->instr, stderr);
1278          fprintf(stderr, "\n");
1279       }
1280       break;
1281    }
1282    case nir_op_fmul: {
1283       if (dst.size() == 1) {
1284          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1285       } else if (dst.size() == 2) {
1286          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1287                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1288       } else {
1289          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1290          nir_print_instr(&instr->instr, stderr);
1291          fprintf(stderr, "\n");
1292       }
1293       break;
1294    }
1295    case nir_op_fadd: {
1296       if (dst.size() == 1) {
1297          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1298       } else if (dst.size() == 2) {
1299          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1300                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1301       } else {
1302          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1303          nir_print_instr(&instr->instr, stderr);
1304          fprintf(stderr, "\n");
1305       }
1306       break;
1307    }
1308    case nir_op_fsub: {
1309       Temp src0 = get_alu_src(ctx, instr->src[0]);
1310       Temp src1 = get_alu_src(ctx, instr->src[1]);
1311       if (dst.size() == 1) {
1312          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1313             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1314          else
1315             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1316       } else if (dst.size() == 2) {
1317          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1318                                      get_alu_src(ctx, instr->src[0]),
1319                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1320          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1321          sub->neg[1] = true;
1322       } else {
1323          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1324          nir_print_instr(&instr->instr, stderr);
1325          fprintf(stderr, "\n");
1326       }
1327       break;
1328    }
1329    case nir_op_fmax: {
1330       if (dst.size() == 1) {
1331          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true);
1332       } else if (dst.size() == 2) {
1333          bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1334                   get_alu_src(ctx, instr->src[0]),
1335                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1336       } else {
1337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1338          nir_print_instr(&instr->instr, stderr);
1339          fprintf(stderr, "\n");
1340       }
1341       break;
1342    }
1343    case nir_op_fmin: {
1344       if (dst.size() == 1) {
1345          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true);
1346       } else if (dst.size() == 2) {
1347          bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1348                   get_alu_src(ctx, instr->src[0]),
1349                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1350       } else {
1351          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1352          nir_print_instr(&instr->instr, stderr);
1353          fprintf(stderr, "\n");
1354       }
1355       break;
1356    }
1357    case nir_op_fmax3: {
1358       if (dst.size() == 1) {
1359          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst);
1360       } else {
1361          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1362          nir_print_instr(&instr->instr, stderr);
1363          fprintf(stderr, "\n");
1364       }
1365       break;
1366    }
1367    case nir_op_fmin3: {
1368       if (dst.size() == 1) {
1369          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst);
1370       } else {
1371          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1372          nir_print_instr(&instr->instr, stderr);
1373          fprintf(stderr, "\n");
1374       }
1375       break;
1376    }
1377    case nir_op_fmed3: {
1378       if (dst.size() == 1) {
1379          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst);
1380       } else {
1381          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1382          nir_print_instr(&instr->instr, stderr);
1383          fprintf(stderr, "\n");
1384       }
1385       break;
1386    }
1387    case nir_op_umax3: {
1388       if (dst.size() == 1) {
1389          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1390       } else {
1391          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1392          nir_print_instr(&instr->instr, stderr);
1393          fprintf(stderr, "\n");
1394       }
1395       break;
1396    }
1397    case nir_op_umin3: {
1398       if (dst.size() == 1) {
1399          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1400       } else {
1401          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1402          nir_print_instr(&instr->instr, stderr);
1403          fprintf(stderr, "\n");
1404       }
1405       break;
1406    }
1407    case nir_op_umed3: {
1408       if (dst.size() == 1) {
1409          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1410       } else {
1411          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1412          nir_print_instr(&instr->instr, stderr);
1413          fprintf(stderr, "\n");
1414       }
1415       break;
1416    }
1417    case nir_op_imax3: {
1418       if (dst.size() == 1) {
1419          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1420       } else {
1421          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1422          nir_print_instr(&instr->instr, stderr);
1423          fprintf(stderr, "\n");
1424       }
1425       break;
1426    }
1427    case nir_op_imin3: {
1428       if (dst.size() == 1) {
1429          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1430       } else {
1431          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1432          nir_print_instr(&instr->instr, stderr);
1433          fprintf(stderr, "\n");
1434       }
1435       break;
1436    }
1437    case nir_op_imed3: {
1438       if (dst.size() == 1) {
1439          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1440       } else {
1441          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1442          nir_print_instr(&instr->instr, stderr);
1443          fprintf(stderr, "\n");
1444       }
1445       break;
1446    }
1447    case nir_op_cube_face_coord: {
1448       Temp in = get_alu_src(ctx, instr->src[0], 3);
1449       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1450                       emit_extract_vector(ctx, in, 1, v1),
1451                       emit_extract_vector(ctx, in, 2, v1) };
1452       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1453       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1454       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1455       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1456       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1457       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1458       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1459       break;
1460    }
1461    case nir_op_cube_face_index: {
1462       Temp in = get_alu_src(ctx, instr->src[0], 3);
1463       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1464                       emit_extract_vector(ctx, in, 1, v1),
1465                       emit_extract_vector(ctx, in, 2, v1) };
1466       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1467       break;
1468    }
1469    case nir_op_bcsel: {
1470       emit_bcsel(ctx, instr, dst);
1471       break;
1472    }
1473    case nir_op_frsq: {
1474       if (dst.size() == 1) {
1475          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1476       } else if (dst.size() == 2) {
1477          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1478       } else {
1479          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1480          nir_print_instr(&instr->instr, stderr);
1481          fprintf(stderr, "\n");
1482       }
1483       break;
1484    }
1485    case nir_op_fneg: {
1486       Temp src = get_alu_src(ctx, instr->src[0]);
1487       if (dst.size() == 1) {
1488          if (ctx->block->fp_mode.must_flush_denorms32)
1489             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1490          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1491       } else if (dst.size() == 2) {
1492          if (ctx->block->fp_mode.must_flush_denorms16_64)
1493             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1494          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1495          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1496          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1497          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1498       } else {
1499          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1500          nir_print_instr(&instr->instr, stderr);
1501          fprintf(stderr, "\n");
1502       }
1503       break;
1504    }
1505    case nir_op_fabs: {
1506       Temp src = get_alu_src(ctx, instr->src[0]);
1507       if (dst.size() == 1) {
1508          if (ctx->block->fp_mode.must_flush_denorms32)
1509             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1510          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1511       } else if (dst.size() == 2) {
1512          if (ctx->block->fp_mode.must_flush_denorms16_64)
1513             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1514          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1515          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1516          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1517          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1518       } else {
1519          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1520          nir_print_instr(&instr->instr, stderr);
1521          fprintf(stderr, "\n");
1522       }
1523       break;
1524    }
1525    case nir_op_fsat: {
1526       Temp src = get_alu_src(ctx, instr->src[0]);
1527       if (dst.size() == 1) {
1528          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1529       } else if (dst.size() == 2) {
1530          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1531          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1532          vop3->clamp = true;
1533       } else {
1534          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1535          nir_print_instr(&instr->instr, stderr);
1536          fprintf(stderr, "\n");
1537       }
1538       break;
1539    }
1540    case nir_op_flog2: {
1541       if (dst.size() == 1) {
1542          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1543       } else {
1544          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1545          nir_print_instr(&instr->instr, stderr);
1546          fprintf(stderr, "\n");
1547       }
1548       break;
1549    }
1550    case nir_op_frcp: {
1551       if (dst.size() == 1) {
1552          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1553       } else if (dst.size() == 2) {
1554          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1555       } else {
1556          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1557          nir_print_instr(&instr->instr, stderr);
1558          fprintf(stderr, "\n");
1559       }
1560       break;
1561    }
1562    case nir_op_fexp2: {
1563       if (dst.size() == 1) {
1564          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1565       } else {
1566          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1567          nir_print_instr(&instr->instr, stderr);
1568          fprintf(stderr, "\n");
1569       }
1570       break;
1571    }
1572    case nir_op_fsqrt: {
1573       if (dst.size() == 1) {
1574          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1575       } else if (dst.size() == 2) {
1576          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1577       } else {
1578          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1579          nir_print_instr(&instr->instr, stderr);
1580          fprintf(stderr, "\n");
1581       }
1582       break;
1583    }
1584    case nir_op_ffract: {
1585       if (dst.size() == 1) {
1586          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1587       } else if (dst.size() == 2) {
1588          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1589       } else {
1590          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1591          nir_print_instr(&instr->instr, stderr);
1592          fprintf(stderr, "\n");
1593       }
1594       break;
1595    }
1596    case nir_op_ffloor: {
1597       if (dst.size() == 1) {
1598          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1599       } else if (dst.size() == 2) {
1600          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst);
1601       } else {
1602          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1603          nir_print_instr(&instr->instr, stderr);
1604          fprintf(stderr, "\n");
1605       }
1606       break;
1607    }
1608    case nir_op_fceil: {
1609       if (dst.size() == 1) {
1610          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1611       } else if (dst.size() == 2) {
1612          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1613       } else {
1614          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1615          nir_print_instr(&instr->instr, stderr);
1616          fprintf(stderr, "\n");
1617       }
1618       break;
1619    }
1620    case nir_op_ftrunc: {
1621       if (dst.size() == 1) {
1622          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1623       } else if (dst.size() == 2) {
1624          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f64, dst);
1625       } else {
1626          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1627          nir_print_instr(&instr->instr, stderr);
1628          fprintf(stderr, "\n");
1629       }
1630       break;
1631    }
1632    case nir_op_fround_even: {
1633       if (dst.size() == 1) {
1634          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1635       } else if (dst.size() == 2) {
1636          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1637       } else {
1638          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1639          nir_print_instr(&instr->instr, stderr);
1640          fprintf(stderr, "\n");
1641       }
1642       break;
1643    }
1644    case nir_op_fsin:
1645    case nir_op_fcos: {
1646       Temp src = get_alu_src(ctx, instr->src[0]);
1647       aco_ptr<Instruction> norm;
1648       if (dst.size() == 1) {
1649          Temp tmp;
1650          Operand half_pi(0x3e22f983u);
1651          if (src.type() == RegType::sgpr)
1652             tmp = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1653          else
1654             tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1655
1656          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1657          if (ctx->options->chip_class < GFX9)
1658             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1659
1660          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1661          bld.vop1(opcode, Definition(dst), tmp);
1662       } else {
1663          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1664          nir_print_instr(&instr->instr, stderr);
1665          fprintf(stderr, "\n");
1666       }
1667       break;
1668    }
1669    case nir_op_ldexp: {
1670       if (dst.size() == 1) {
1671          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1672                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1673                   get_alu_src(ctx, instr->src[1]));
1674       } else if (dst.size() == 2) {
1675          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1676                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1677                   get_alu_src(ctx, instr->src[1]));
1678       } else {
1679          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1680          nir_print_instr(&instr->instr, stderr);
1681          fprintf(stderr, "\n");
1682       }
1683       break;
1684    }
1685    case nir_op_frexp_sig: {
1686       if (dst.size() == 1) {
1687          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1688                   get_alu_src(ctx, instr->src[0]));
1689       } else if (dst.size() == 2) {
1690          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1691                   get_alu_src(ctx, instr->src[0]));
1692       } else {
1693          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1694          nir_print_instr(&instr->instr, stderr);
1695          fprintf(stderr, "\n");
1696       }
1697       break;
1698    }
1699    case nir_op_frexp_exp: {
1700       if (instr->src[0].src.ssa->bit_size == 32) {
1701          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1702                   get_alu_src(ctx, instr->src[0]));
1703       } else if (instr->src[0].src.ssa->bit_size == 64) {
1704          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1705                   get_alu_src(ctx, instr->src[0]));
1706       } else {
1707          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1708          nir_print_instr(&instr->instr, stderr);
1709          fprintf(stderr, "\n");
1710       }
1711       break;
1712    }
1713    case nir_op_fsign: {
1714       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1715       if (dst.size() == 1) {
1716          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1717          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1718          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1719          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1720       } else if (dst.size() == 2) {
1721          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1722          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1723          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1724
1725          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1726          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1727          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1728
1729          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1730       } else {
1731          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1732          nir_print_instr(&instr->instr, stderr);
1733          fprintf(stderr, "\n");
1734       }
1735       break;
1736    }
1737    case nir_op_f2f32: {
1738       if (instr->src[0].src.ssa->bit_size == 64) {
1739          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1740       } else {
1741          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1742          nir_print_instr(&instr->instr, stderr);
1743          fprintf(stderr, "\n");
1744       }
1745       break;
1746    }
1747    case nir_op_f2f64: {
1748       if (instr->src[0].src.ssa->bit_size == 32) {
1749          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1750       } else {
1751          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1752          nir_print_instr(&instr->instr, stderr);
1753          fprintf(stderr, "\n");
1754       }
1755       break;
1756    }
1757    case nir_op_i2f32: {
1758       assert(dst.size() == 1);
1759       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1760       break;
1761    }
1762    case nir_op_i2f64: {
1763       if (instr->src[0].src.ssa->bit_size == 32) {
1764          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1765       } else if (instr->src[0].src.ssa->bit_size == 64) {
1766          Temp src = get_alu_src(ctx, instr->src[0]);
1767          RegClass rc = RegClass(src.type(), 1);
1768          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1769          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1770          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1771          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1772          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1773          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1774
1775       } else {
1776          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1777          nir_print_instr(&instr->instr, stderr);
1778          fprintf(stderr, "\n");
1779       }
1780       break;
1781    }
1782    case nir_op_u2f32: {
1783       assert(dst.size() == 1);
1784       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1785       break;
1786    }
1787    case nir_op_u2f64: {
1788       if (instr->src[0].src.ssa->bit_size == 32) {
1789          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1790       } else if (instr->src[0].src.ssa->bit_size == 64) {
1791          Temp src = get_alu_src(ctx, instr->src[0]);
1792          RegClass rc = RegClass(src.type(), 1);
1793          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1794          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1795          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1796          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1797          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1798          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1799       } else {
1800          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1801          nir_print_instr(&instr->instr, stderr);
1802          fprintf(stderr, "\n");
1803       }
1804       break;
1805    }
1806    case nir_op_f2i32: {
1807       Temp src = get_alu_src(ctx, instr->src[0]);
1808       if (instr->src[0].src.ssa->bit_size == 32) {
1809          if (dst.type() == RegType::vgpr)
1810             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1811          else
1812             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1813                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1814
1815       } else if (instr->src[0].src.ssa->bit_size == 64) {
1816          if (dst.type() == RegType::vgpr)
1817             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1818          else
1819             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1820                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1821
1822       } else {
1823          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1824          nir_print_instr(&instr->instr, stderr);
1825          fprintf(stderr, "\n");
1826       }
1827       break;
1828    }
1829    case nir_op_f2u32: {
1830       Temp src = get_alu_src(ctx, instr->src[0]);
1831       if (instr->src[0].src.ssa->bit_size == 32) {
1832          if (dst.type() == RegType::vgpr)
1833             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
1834          else
1835             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1836                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
1837
1838       } else if (instr->src[0].src.ssa->bit_size == 64) {
1839          if (dst.type() == RegType::vgpr)
1840             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
1841          else
1842             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1843                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
1844
1845       } else {
1846          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1847          nir_print_instr(&instr->instr, stderr);
1848          fprintf(stderr, "\n");
1849       }
1850       break;
1851    }
1852    case nir_op_f2i64: {
1853       Temp src = get_alu_src(ctx, instr->src[0]);
1854       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1855          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1856          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
1857          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1858          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
1859          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1860          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
1861          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1862          Temp new_exponent = bld.tmp(v1);
1863          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
1864          mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
1865          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
1866          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1867          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1868          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
1869          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
1870          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
1871          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
1872          Temp new_lower = bld.tmp(v1);
1873          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
1874          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
1875          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
1876
1877       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1878          if (src.type() == RegType::vgpr)
1879             src = bld.as_uniform(src);
1880          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1881          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1882          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1883          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
1884          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1885          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
1886          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1887          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
1888          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1889          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
1890          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
1891          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
1892          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
1893          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
1894          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1895          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1896          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
1897          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
1898          Temp borrow = bld.tmp(s1);
1899          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
1900          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
1901          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1902
1903       } else if (instr->src[0].src.ssa->bit_size == 64) {
1904          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1905          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1906          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1907          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1908          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1909          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1910          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1911          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
1912          if (dst.type() == RegType::sgpr) {
1913             lower = bld.as_uniform(lower);
1914             upper = bld.as_uniform(upper);
1915          }
1916          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1917
1918       } else {
1919          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1920          nir_print_instr(&instr->instr, stderr);
1921          fprintf(stderr, "\n");
1922       }
1923       break;
1924    }
1925    case nir_op_f2u64: {
1926       Temp src = get_alu_src(ctx, instr->src[0]);
1927       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1928          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1929          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
1930          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
1931          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1932          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1933          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
1934          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
1935          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1936          Temp new_exponent = bld.tmp(v1);
1937          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
1938          mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
1939          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1940          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1941          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
1942          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
1943          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
1944          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
1945          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1946
1947       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1948          if (src.type() == RegType::vgpr)
1949             src = bld.as_uniform(src);
1950          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1951          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1952          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1953          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1954          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1955          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
1956          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
1957          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1958          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
1959          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
1960          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
1961          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
1962          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1963          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1964          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
1965          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
1966          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
1967          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1968
1969       } else if (instr->src[0].src.ssa->bit_size == 64) {
1970          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1971          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1972          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1973          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1974          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1975          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1976          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1977          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
1978          if (dst.type() == RegType::sgpr) {
1979             lower = bld.as_uniform(lower);
1980             upper = bld.as_uniform(upper);
1981          }
1982          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1983
1984       } else {
1985          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1986          nir_print_instr(&instr->instr, stderr);
1987          fprintf(stderr, "\n");
1988       }
1989       break;
1990    }
1991    case nir_op_b2f32: {
1992       Temp src = get_alu_src(ctx, instr->src[0]);
1993       assert(src.regClass() == bld.lm);
1994
1995       if (dst.regClass() == s1) {
1996          src = bool_to_scalar_condition(ctx, src);
1997          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
1998       } else if (dst.regClass() == v1) {
1999          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2000       } else {
2001          unreachable("Wrong destination register class for nir_op_b2f32.");
2002       }
2003       break;
2004    }
2005    case nir_op_b2f64: {
2006       Temp src = get_alu_src(ctx, instr->src[0]);
2007       assert(src.regClass() == bld.lm);
2008
2009       if (dst.regClass() == s2) {
2010          src = bool_to_scalar_condition(ctx, src);
2011          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2012       } else if (dst.regClass() == v2) {
2013          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2014          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2015          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2016       } else {
2017          unreachable("Wrong destination register class for nir_op_b2f64.");
2018       }
2019       break;
2020    }
2021    case nir_op_i2i32: {
2022       Temp src = get_alu_src(ctx, instr->src[0]);
2023       if (instr->src[0].src.ssa->bit_size == 64) {
2024          /* we can actually just say dst = src, as it would map the lower register */
2025          emit_extract_vector(ctx, src, 0, dst);
2026       } else {
2027          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2028          nir_print_instr(&instr->instr, stderr);
2029          fprintf(stderr, "\n");
2030       }
2031       break;
2032    }
2033    case nir_op_u2u32: {
2034       Temp src = get_alu_src(ctx, instr->src[0]);
2035       if (instr->src[0].src.ssa->bit_size == 16) {
2036          if (dst.regClass() == s1) {
2037             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2038          } else {
2039             // TODO: do better with SDWA
2040             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2041          }
2042       } else if (instr->src[0].src.ssa->bit_size == 64) {
2043          /* we can actually just say dst = src, as it would map the lower register */
2044          emit_extract_vector(ctx, src, 0, dst);
2045       } else {
2046          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2047          nir_print_instr(&instr->instr, stderr);
2048          fprintf(stderr, "\n");
2049       }
2050       break;
2051    }
2052    case nir_op_i2i64: {
2053       Temp src = get_alu_src(ctx, instr->src[0]);
2054       if (src.regClass() == s1) {
2055          Temp high = bld.sopc(aco_opcode::s_ashr_i32, bld.def(s1, scc), src, Operand(31u));
2056          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2057       } else if (src.regClass() == v1) {
2058          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2059          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2060       } else {
2061          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2062          nir_print_instr(&instr->instr, stderr);
2063          fprintf(stderr, "\n");
2064       }
2065       break;
2066    }
2067    case nir_op_u2u64: {
2068       Temp src = get_alu_src(ctx, instr->src[0]);
2069       if (instr->src[0].src.ssa->bit_size == 32) {
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2071       } else {
2072          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2073          nir_print_instr(&instr->instr, stderr);
2074          fprintf(stderr, "\n");
2075       }
2076       break;
2077    }
2078    case nir_op_b2i32: {
2079       Temp src = get_alu_src(ctx, instr->src[0]);
2080       assert(src.regClass() == bld.lm);
2081
2082       if (dst.regClass() == s1) {
2083          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2084          bool_to_scalar_condition(ctx, src, dst);
2085       } else if (dst.regClass() == v1) {
2086          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2087       } else {
2088          unreachable("Invalid register class for b2i32");
2089       }
2090       break;
2091    }
2092    case nir_op_i2b1: {
2093       Temp src = get_alu_src(ctx, instr->src[0]);
2094       assert(dst.regClass() == bld.lm);
2095
2096       if (src.type() == RegType::vgpr) {
2097          assert(src.regClass() == v1 || src.regClass() == v2);
2098          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2099                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2100       } else {
2101          assert(src.regClass() == s1 || src.regClass() == s2);
2102          Temp tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2103                              bld.scc(bld.def(s1)), Operand(0u), src);
2104          bool_to_vector_condition(ctx, tmp, dst);
2105       }
2106       break;
2107    }
2108    case nir_op_pack_64_2x32_split: {
2109       Temp src0 = get_alu_src(ctx, instr->src[0]);
2110       Temp src1 = get_alu_src(ctx, instr->src[1]);
2111
2112       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2113       break;
2114    }
2115    case nir_op_unpack_64_2x32_split_x:
2116       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2117       break;
2118    case nir_op_unpack_64_2x32_split_y:
2119       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2120       break;
2121    case nir_op_pack_half_2x16: {
2122       Temp src = get_alu_src(ctx, instr->src[0], 2);
2123
2124       if (dst.regClass() == v1) {
2125          Temp src0 = bld.tmp(v1);
2126          Temp src1 = bld.tmp(v1);
2127          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2128          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2129             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2130          else
2131             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2132                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2133                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2134       } else {
2135          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2136          nir_print_instr(&instr->instr, stderr);
2137          fprintf(stderr, "\n");
2138       }
2139       break;
2140    }
2141    case nir_op_unpack_half_2x16_split_x: {
2142       if (dst.regClass() == v1) {
2143          Builder bld(ctx->program, ctx->block);
2144          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2145       } else {
2146          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2147          nir_print_instr(&instr->instr, stderr);
2148          fprintf(stderr, "\n");
2149       }
2150       break;
2151    }
2152    case nir_op_unpack_half_2x16_split_y: {
2153       if (dst.regClass() == v1) {
2154          Builder bld(ctx->program, ctx->block);
2155          /* TODO: use SDWA here */
2156          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2157                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2158       } else {
2159          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2160          nir_print_instr(&instr->instr, stderr);
2161          fprintf(stderr, "\n");
2162       }
2163       break;
2164    }
2165    case nir_op_fquantize2f16: {
2166       Temp src = get_alu_src(ctx, instr->src[0]);
2167       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2168
2169       Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2170
2171       Temp cmp_res = bld.tmp(bld.lm);
2172       bld.vopc_e64(aco_opcode::v_cmp_class_f16, Definition(cmp_res), f16, mask).def(0).setHint(vcc);
2173
2174       Temp f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2175
2176       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32) {
2177          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2178          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2179       } else {
2180          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2181       }
2182       break;
2183    }
2184    case nir_op_bfm: {
2185       Temp bits = get_alu_src(ctx, instr->src[0]);
2186       Temp offset = get_alu_src(ctx, instr->src[1]);
2187
2188       if (dst.regClass() == s1) {
2189          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2190       } else if (dst.regClass() == v1) {
2191          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2192       } else {
2193          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2194          nir_print_instr(&instr->instr, stderr);
2195          fprintf(stderr, "\n");
2196       }
2197       break;
2198    }
2199    case nir_op_bitfield_select: {
2200       /* (mask & insert) | (~mask & base) */
2201       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2202       Temp insert = get_alu_src(ctx, instr->src[1]);
2203       Temp base = get_alu_src(ctx, instr->src[2]);
2204
2205       /* dst = (insert & bitmask) | (base & ~bitmask) */
2206       if (dst.regClass() == s1) {
2207          aco_ptr<Instruction> sop2;
2208          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2209          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2210          Operand lhs;
2211          if (const_insert && const_bitmask) {
2212             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2213          } else {
2214             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2215             lhs = Operand(insert);
2216          }
2217
2218          Operand rhs;
2219          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2220          if (const_base && const_bitmask) {
2221             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2222          } else {
2223             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2224             rhs = Operand(base);
2225          }
2226
2227          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2228
2229       } else if (dst.regClass() == v1) {
2230          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2231             base = as_vgpr(ctx, base);
2232          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2233             insert = as_vgpr(ctx, insert);
2234
2235          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2236
2237       } else {
2238          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2239          nir_print_instr(&instr->instr, stderr);
2240          fprintf(stderr, "\n");
2241       }
2242       break;
2243    }
2244    case nir_op_ubfe:
2245    case nir_op_ibfe: {
2246       Temp base = get_alu_src(ctx, instr->src[0]);
2247       Temp offset = get_alu_src(ctx, instr->src[1]);
2248       Temp bits = get_alu_src(ctx, instr->src[2]);
2249
2250       if (dst.type() == RegType::sgpr) {
2251          Operand extract;
2252          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2253          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2254          if (const_offset && const_bits) {
2255             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2256             extract = Operand(const_extract);
2257          } else {
2258             Operand width;
2259             if (const_bits) {
2260                width = Operand(const_bits->u32 << 16);
2261             } else {
2262                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2263             }
2264             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2265          }
2266
2267          aco_opcode opcode;
2268          if (dst.regClass() == s1) {
2269             if (instr->op == nir_op_ubfe)
2270                opcode = aco_opcode::s_bfe_u32;
2271             else
2272                opcode = aco_opcode::s_bfe_i32;
2273          } else if (dst.regClass() == s2) {
2274             if (instr->op == nir_op_ubfe)
2275                opcode = aco_opcode::s_bfe_u64;
2276             else
2277                opcode = aco_opcode::s_bfe_i64;
2278          } else {
2279             unreachable("Unsupported BFE bit size");
2280          }
2281
2282          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2283
2284       } else {
2285          aco_opcode opcode;
2286          if (dst.regClass() == v1) {
2287             if (instr->op == nir_op_ubfe)
2288                opcode = aco_opcode::v_bfe_u32;
2289             else
2290                opcode = aco_opcode::v_bfe_i32;
2291          } else {
2292             unreachable("Unsupported BFE bit size");
2293          }
2294
2295          emit_vop3a_instruction(ctx, instr, opcode, dst);
2296       }
2297       break;
2298    }
2299    case nir_op_bit_count: {
2300       Temp src = get_alu_src(ctx, instr->src[0]);
2301       if (src.regClass() == s1) {
2302          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2303       } else if (src.regClass() == v1) {
2304          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2305       } else if (src.regClass() == v2) {
2306          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2307                   emit_extract_vector(ctx, src, 1, v1),
2308                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2309                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2310       } else if (src.regClass() == s2) {
2311          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_flt: {
2320       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2321       break;
2322    }
2323    case nir_op_fge: {
2324       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2325       break;
2326    }
2327    case nir_op_feq: {
2328       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2329       break;
2330    }
2331    case nir_op_fne: {
2332       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2333       break;
2334    }
2335    case nir_op_ilt: {
2336       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2337       break;
2338    }
2339    case nir_op_ige: {
2340       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2341       break;
2342    }
2343    case nir_op_ieq: {
2344       if (instr->src[0].src.ssa->bit_size == 1)
2345          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2346       else
2347          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32, aco_opcode::s_cmp_eq_u64);
2348       break;
2349    }
2350    case nir_op_ine: {
2351       if (instr->src[0].src.ssa->bit_size == 1)
2352          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2353       else
2354          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32, aco_opcode::s_cmp_lg_u64);
2355       break;
2356    }
2357    case nir_op_ult: {
2358       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2359       break;
2360    }
2361    case nir_op_uge: {
2362       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2363       break;
2364    }
2365    case nir_op_fddx:
2366    case nir_op_fddy:
2367    case nir_op_fddx_fine:
2368    case nir_op_fddy_fine:
2369    case nir_op_fddx_coarse:
2370    case nir_op_fddy_coarse: {
2371       Definition tl = bld.def(v1);
2372       uint16_t dpp_ctrl;
2373       if (instr->op == nir_op_fddx_fine) {
2374          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 2, 2));
2375          dpp_ctrl = dpp_quad_perm(1, 1, 3, 3);
2376       } else if (instr->op == nir_op_fddy_fine) {
2377          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 1, 0, 1));
2378          dpp_ctrl = dpp_quad_perm(2, 3, 2, 3);
2379       } else {
2380          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 0, 0));
2381          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2382             dpp_ctrl = dpp_quad_perm(1, 1, 1, 1);
2383          else
2384             dpp_ctrl = dpp_quad_perm(2, 2, 2, 2);
2385       }
2386
2387       Definition tmp = bld.def(v1);
2388       bld.vop2_dpp(aco_opcode::v_sub_f32, tmp, get_alu_src(ctx, instr->src[0]), tl.getTemp(), dpp_ctrl);
2389       emit_wqm(ctx, tmp.getTemp(), dst, true);
2390       break;
2391    }
2392    default:
2393       fprintf(stderr, "Unknown NIR ALU instr: ");
2394       nir_print_instr(&instr->instr, stderr);
2395       fprintf(stderr, "\n");
2396    }
2397 }
2398
2399 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2400 {
2401    Temp dst = get_ssa_temp(ctx, &instr->def);
2402
2403    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2404    // which get truncated the lsb if double and msb if int
2405    // for now, we only use s_mov_b64 with 64bit inline constants
2406    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2407    assert(dst.type() == RegType::sgpr);
2408
2409    Builder bld(ctx->program, ctx->block);
2410
2411    if (instr->def.bit_size == 1) {
2412       assert(dst.regClass() == bld.lm);
2413       int val = instr->value[0].b ? -1 : 0;
2414       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2415       bld.sop1(Builder::s_mov, Definition(dst), op);
2416    } else if (dst.size() == 1) {
2417       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2418    } else {
2419       assert(dst.size() != 1);
2420       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2421       if (instr->def.bit_size == 64)
2422          for (unsigned i = 0; i < dst.size(); i++)
2423             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2424       else {
2425          for (unsigned i = 0; i < dst.size(); i++)
2426             vec->operands[i] = Operand{instr->value[i].u32};
2427       }
2428       vec->definitions[0] = Definition(dst);
2429       ctx->block->instructions.emplace_back(std::move(vec));
2430    }
2431 }
2432
2433 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2434 {
2435    uint32_t new_mask = 0;
2436    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2437       if (mask & (1u << i))
2438          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2439    return new_mask;
2440 }
2441
2442 void visit_store_vs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2443 {
2444    /* This wouldn't work inside control flow or with indirect offsets but
2445     * that doesn't happen because of nir_lower_io_to_temporaries(). */
2446
2447    unsigned write_mask = nir_intrinsic_write_mask(instr);
2448    unsigned component = nir_intrinsic_component(instr);
2449    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2450    unsigned idx = nir_intrinsic_base(instr) + component;
2451
2452    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2453    if (off_instr->type != nir_instr_type_load_const) {
2454       fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2455       nir_print_instr(off_instr, stderr);
2456       fprintf(stderr, "\n");
2457    }
2458    idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2459
2460    if (instr->src[0].ssa->bit_size == 64)
2461       write_mask = widen_mask(write_mask, 2);
2462
2463    for (unsigned i = 0; i < 8; ++i) {
2464       if (write_mask & (1 << i)) {
2465          ctx->vs_output.mask[idx / 4u] |= 1 << (idx % 4u);
2466          ctx->vs_output.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2467       }
2468       idx++;
2469    }
2470 }
2471
2472 void visit_store_fs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2473 {
2474    unsigned write_mask = nir_intrinsic_write_mask(instr);
2475    Operand values[4];
2476    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2477    for (unsigned i = 0; i < 4; ++i) {
2478       if (write_mask & (1 << i)) {
2479          Temp tmp = emit_extract_vector(ctx, src, i, v1);
2480          values[i] = Operand(tmp);
2481       } else {
2482          values[i] = Operand(v1);
2483       }
2484    }
2485
2486    unsigned index = nir_intrinsic_base(instr) / 4;
2487    unsigned target, col_format;
2488    unsigned enabled_channels = 0xF;
2489    aco_opcode compr_op = (aco_opcode)0;
2490
2491    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2492    assert(offset && "Non-const offsets on exports not yet supported");
2493    index += offset->u32;
2494
2495    assert(index != FRAG_RESULT_COLOR);
2496
2497    /* Unlike vertex shader exports, it's fine to use multiple exports to
2498     * export separate channels of one target. So shaders which export both
2499     * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2500     * TODO: combine the exports in those cases and create better code
2501     */
2502
2503    if (index == FRAG_RESULT_SAMPLE_MASK) {
2504
2505       if (ctx->program->info->ps.writes_z) {
2506          target = V_008DFC_SQ_EXP_MRTZ;
2507          enabled_channels = 0x4;
2508          col_format = (unsigned) -1;
2509
2510          values[2] = values[0];
2511          values[0] = Operand(v1);
2512       } else {
2513          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2514          exp->valid_mask = false;
2515          exp->done = false;
2516          exp->compressed = true;
2517          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2518          exp->enabled_mask = 0xc;
2519          for (int i = 0; i < 4; i++)
2520             exp->operands[i] = Operand(v1);
2521          exp->operands[1] = Operand(values[0]);
2522          ctx->block->instructions.emplace_back(std::move(exp));
2523          return;
2524       }
2525
2526    } else if (index == FRAG_RESULT_DEPTH) {
2527
2528       target = V_008DFC_SQ_EXP_MRTZ;
2529       enabled_channels = 0x1;
2530       col_format = (unsigned) -1;
2531
2532    } else if (index == FRAG_RESULT_STENCIL) {
2533
2534       if (ctx->program->info->ps.writes_z) {
2535          target = V_008DFC_SQ_EXP_MRTZ;
2536          enabled_channels = 0x2;
2537          col_format = (unsigned) -1;
2538
2539          values[1] = values[0];
2540          values[0] = Operand(v1);
2541       } else {
2542          aco_ptr<Instruction> shift{create_instruction<VOP2_instruction>(aco_opcode::v_lshlrev_b32, Format::VOP2, 2, 1)};
2543          shift->operands[0] = Operand((uint32_t) 16);
2544          shift->operands[1] = values[0];
2545          Temp tmp = {ctx->program->allocateId(), v1};
2546          shift->definitions[0] = Definition(tmp);
2547          ctx->block->instructions.emplace_back(std::move(shift));
2548
2549          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2550          exp->valid_mask = false;
2551          exp->done = false;
2552          exp->compressed = true;
2553          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2554          exp->enabled_mask = 0x3;
2555          exp->operands[0] = Operand(tmp);
2556          for (int i = 1; i < 4; i++)
2557             exp->operands[i] = Operand(v1);
2558          ctx->block->instructions.emplace_back(std::move(exp));
2559          return;
2560       }
2561
2562    } else {
2563       index -= FRAG_RESULT_DATA0;
2564       target = V_008DFC_SQ_EXP_MRT + index;
2565       col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2566    }
2567    ASSERTED bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2568    ASSERTED bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2569    assert(!is_int8 && !is_int10);
2570
2571    switch (col_format)
2572    {
2573    case V_028714_SPI_SHADER_ZERO:
2574       enabled_channels = 0; /* writemask */
2575       target = V_008DFC_SQ_EXP_NULL;
2576       break;
2577
2578    case V_028714_SPI_SHADER_32_R:
2579       enabled_channels = 1;
2580       break;
2581
2582    case V_028714_SPI_SHADER_32_GR:
2583       enabled_channels = 0x3;
2584       break;
2585
2586    case V_028714_SPI_SHADER_32_AR:
2587       if (ctx->options->chip_class >= GFX10) {
2588          /* Special case: on GFX10, the outputs are different for 32_AR */
2589          enabled_channels = 0x3;
2590          values[1] = values[3];
2591       } else {
2592          enabled_channels = 0x9;
2593       }
2594       break;
2595
2596    case V_028714_SPI_SHADER_FP16_ABGR:
2597       enabled_channels = 0x5;
2598       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
2599       break;
2600
2601    case V_028714_SPI_SHADER_UNORM16_ABGR:
2602       enabled_channels = 0x5;
2603       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
2604       break;
2605
2606    case V_028714_SPI_SHADER_SNORM16_ABGR:
2607       enabled_channels = 0x5;
2608       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
2609       break;
2610
2611    case V_028714_SPI_SHADER_UINT16_ABGR:
2612       enabled_channels = 0x5;
2613       compr_op = aco_opcode::v_cvt_pk_u16_u32;
2614       break;
2615
2616    case V_028714_SPI_SHADER_SINT16_ABGR:
2617       enabled_channels = 0x5;
2618       compr_op = aco_opcode::v_cvt_pk_i16_i32;
2619       break;
2620
2621    case V_028714_SPI_SHADER_32_ABGR:
2622       enabled_channels = 0xF;
2623       break;
2624
2625    default:
2626       break;
2627    }
2628
2629    if (target == V_008DFC_SQ_EXP_NULL)
2630       return;
2631
2632    if ((bool)compr_op)
2633    {
2634       for (int i = 0; i < 2; i++)
2635       {
2636          /* check if at least one of the values to be compressed is enabled */
2637          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
2638          if (enabled) {
2639             enabled_channels |= enabled << (i*2);
2640             aco_ptr<VOP3A_instruction> compr{create_instruction<VOP3A_instruction>(compr_op, Format::VOP3A, 2, 1)};
2641             Temp tmp{ctx->program->allocateId(), v1};
2642             compr->operands[0] = values[i*2].isUndefined() ? Operand(0u) : values[i*2];
2643             compr->operands[1] = values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1];
2644             compr->definitions[0] = Definition(tmp);
2645             values[i] = Operand(tmp);
2646             ctx->block->instructions.emplace_back(std::move(compr));
2647          } else {
2648             values[i] = Operand(v1);
2649          }
2650       }
2651    }
2652
2653    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2654    exp->valid_mask = false;
2655    exp->done = false;
2656    exp->compressed = (bool) compr_op;
2657    exp->dest = target;
2658    exp->enabled_mask = enabled_channels;
2659    if ((bool) compr_op) {
2660       for (int i = 0; i < 2; i++)
2661          exp->operands[i] = enabled_channels & (3 << (i * 2)) ? values[i] : Operand(v1);
2662       exp->operands[2] = Operand(v1);
2663       exp->operands[3] = Operand(v1);
2664    } else {
2665       for (int i = 0; i < 4; i++)
2666          exp->operands[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
2667    }
2668
2669    ctx->block->instructions.emplace_back(std::move(exp));
2670 }
2671
2672 Operand load_lds_size_m0(isel_context *ctx)
2673 {
2674    /* TODO: m0 does not need to be initialized on GFX9+ */
2675    Builder bld(ctx->program, ctx->block);
2676    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2677 }
2678
2679 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2680               Temp address, unsigned base_offset, unsigned align)
2681 {
2682    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2683
2684    Builder bld(ctx->program, ctx->block);
2685
2686    Operand m = load_lds_size_m0(ctx);
2687
2688    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2689    unsigned bytes_read = 0;
2690    unsigned result_size = 0;
2691    unsigned total_bytes = num_components * elem_size_bytes;
2692    std::array<Temp, 4> result;
2693
2694    while (bytes_read < total_bytes) {
2695       unsigned todo = total_bytes - bytes_read;
2696       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2697       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2698
2699       aco_opcode op = aco_opcode::last_opcode;
2700       bool read2 = false;
2701       if (todo >= 16 && aligned16) {
2702          op = aco_opcode::ds_read_b128;
2703          todo = 16;
2704       } else if (todo >= 16 && aligned8) {
2705          op = aco_opcode::ds_read2_b64;
2706          read2 = true;
2707          todo = 16;
2708       } else if (todo >= 12 && aligned16) {
2709          op = aco_opcode::ds_read_b96;
2710          todo = 12;
2711       } else if (todo >= 8 && aligned8) {
2712          op = aco_opcode::ds_read_b64;
2713          todo = 8;
2714       } else if (todo >= 8) {
2715          op = aco_opcode::ds_read2_b32;
2716          read2 = true;
2717          todo = 8;
2718       } else if (todo >= 4) {
2719          op = aco_opcode::ds_read_b32;
2720          todo = 4;
2721       } else {
2722          assert(false);
2723       }
2724       assert(todo % elem_size_bytes == 0);
2725       unsigned num_elements = todo / elem_size_bytes;
2726       unsigned offset = base_offset + bytes_read;
2727       unsigned max_offset = read2 ? 1019 : 65535;
2728
2729       Temp address_offset = address;
2730       if (offset > max_offset) {
2731          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2732          offset = bytes_read;
2733       }
2734       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2735
2736       Temp res;
2737       if (num_components == 1 && dst.type() == RegType::vgpr)
2738          res = dst;
2739       else
2740          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2741
2742       if (read2)
2743          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2744       else
2745          res = bld.ds(op, Definition(res), address_offset, m, offset);
2746
2747       if (num_components == 1) {
2748          assert(todo == total_bytes);
2749          if (dst.type() == RegType::sgpr)
2750             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2751          return;
2752       }
2753
2754       if (dst.type() == RegType::sgpr)
2755          res = bld.as_uniform(res);
2756
2757       if (num_elements == 1) {
2758          result[result_size++] = res;
2759       } else {
2760          assert(res != dst && res.size() % num_elements == 0);
2761          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2762          split->operands[0] = Operand(res);
2763          for (unsigned i = 0; i < num_elements; i++)
2764             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2765          ctx->block->instructions.emplace_back(std::move(split));
2766       }
2767
2768       bytes_read += todo;
2769    }
2770
2771    assert(result_size == num_components && result_size > 1);
2772    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2773    for (unsigned i = 0; i < result_size; i++)
2774       vec->operands[i] = Operand(result[i]);
2775    vec->definitions[0] = Definition(dst);
2776    ctx->block->instructions.emplace_back(std::move(vec));
2777    ctx->allocated_vec.emplace(dst.id(), result);
2778 }
2779
2780 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2781 {
2782    if (start == 0 && size == data.size())
2783       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2784
2785    unsigned size_hint = 1;
2786    auto it = ctx->allocated_vec.find(data.id());
2787    if (it != ctx->allocated_vec.end())
2788       size_hint = it->second[0].size();
2789    if (size % size_hint || start % size_hint)
2790       size_hint = 1;
2791
2792    start /= size_hint;
2793    size /= size_hint;
2794
2795    Temp elems[size];
2796    for (unsigned i = 0; i < size; i++)
2797       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2798
2799    if (size == 1)
2800       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2801
2802    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2803    for (unsigned i = 0; i < size; i++)
2804       vec->operands[i] = Operand(elems[i]);
2805    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2806    vec->definitions[0] = Definition(res);
2807    ctx->block->instructions.emplace_back(std::move(vec));
2808    return res;
2809 }
2810
2811 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2812 {
2813    Builder bld(ctx->program, ctx->block);
2814    unsigned bytes_written = 0;
2815    while (bytes_written < total_size * 4) {
2816       unsigned todo = total_size * 4 - bytes_written;
2817       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2818       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2819
2820       aco_opcode op = aco_opcode::last_opcode;
2821       bool write2 = false;
2822       unsigned size = 0;
2823       if (todo >= 16 && aligned16) {
2824          op = aco_opcode::ds_write_b128;
2825          size = 4;
2826       } else if (todo >= 16 && aligned8) {
2827          op = aco_opcode::ds_write2_b64;
2828          write2 = true;
2829          size = 4;
2830       } else if (todo >= 12 && aligned16) {
2831          op = aco_opcode::ds_write_b96;
2832          size = 3;
2833       } else if (todo >= 8 && aligned8) {
2834          op = aco_opcode::ds_write_b64;
2835          size = 2;
2836       } else if (todo >= 8) {
2837          op = aco_opcode::ds_write2_b32;
2838          write2 = true;
2839          size = 2;
2840       } else if (todo >= 4) {
2841          op = aco_opcode::ds_write_b32;
2842          size = 1;
2843       } else {
2844          assert(false);
2845       }
2846
2847       unsigned offset = offset0 + offset1 + bytes_written;
2848       unsigned max_offset = write2 ? 1020 : 65535;
2849       Temp address_offset = address;
2850       if (offset > max_offset) {
2851          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2852          offset = offset1 + bytes_written;
2853       }
2854       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2855
2856       if (write2) {
2857          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2858          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2859          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2860       } else {
2861          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2862          bld.ds(op, address_offset, val, m, offset);
2863       }
2864
2865       bytes_written += size * 4;
2866    }
2867 }
2868
2869 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2870                Temp address, unsigned base_offset, unsigned align)
2871 {
2872    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2873
2874    Operand m = load_lds_size_m0(ctx);
2875
2876    /* we need at most two stores for 32bit variables */
2877    int start[2], count[2];
2878    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2879    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2880    assert(wrmask == 0);
2881
2882    /* one combined store is sufficient */
2883    if (count[0] == count[1]) {
2884       Builder bld(ctx->program, ctx->block);
2885
2886       Temp address_offset = address;
2887       if ((base_offset >> 2) + start[1] > 255) {
2888          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2889          base_offset = 0;
2890       }
2891
2892       assert(count[0] == 1);
2893       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2894       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2895       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2896       base_offset = base_offset / elem_size_bytes;
2897       bld.ds(op, address_offset, val0, val1, m,
2898              base_offset + start[0], base_offset + start[1]);
2899       return;
2900    }
2901
2902    for (unsigned i = 0; i < 2; i++) {
2903       if (count[i] == 0)
2904          continue;
2905
2906       unsigned elem_size_words = elem_size_bytes / 4;
2907       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2908                       base_offset, start[i] * elem_size_bytes, align);
2909    }
2910    return;
2911 }
2912
2913 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2914 {
2915    if (ctx->stage == vertex_vs) {
2916       visit_store_vs_output(ctx, instr);
2917    } else if (ctx->stage == fragment_fs) {
2918       visit_store_fs_output(ctx, instr);
2919    } else {
2920       unreachable("Shader stage not implemented");
2921    }
2922 }
2923
2924 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
2925 {
2926    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
2927    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
2928
2929    Builder bld(ctx->program, ctx->block);
2930    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
2931    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
2932 }
2933
2934 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
2935 {
2936    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
2937    for (unsigned i = 0; i < num_components; i++)
2938       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
2939    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
2940       assert(num_components == 4);
2941       Builder bld(ctx->program, ctx->block);
2942       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
2943    }
2944
2945    for (Operand& op : vec->operands)
2946       op = op.isUndefined() ? Operand(0u) : op;
2947
2948    vec->definitions[0] = Definition(dst);
2949    ctx->block->instructions.emplace_back(std::move(vec));
2950    emit_split_vector(ctx, dst, num_components);
2951    return;
2952 }
2953
2954 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
2955 {
2956    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2957    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
2958    unsigned idx = nir_intrinsic_base(instr);
2959    unsigned component = nir_intrinsic_component(instr);
2960    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
2961
2962    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2963    if (offset) {
2964       assert(offset->u32 == 0);
2965    } else {
2966       /* the lower 15bit of the prim_mask contain the offset into LDS
2967        * while the upper bits contain the number of prims */
2968       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
2969       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
2970       Builder bld(ctx->program, ctx->block);
2971       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
2972       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
2973       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
2974       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
2975       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
2976    }
2977
2978    if (instr->dest.ssa.num_components == 1) {
2979       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
2980    } else {
2981       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
2982       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
2983       {
2984          Temp tmp = {ctx->program->allocateId(), v1};
2985          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
2986          vec->operands[i] = Operand(tmp);
2987       }
2988       vec->definitions[0] = Definition(dst);
2989       ctx->block->instructions.emplace_back(std::move(vec));
2990    }
2991 }
2992
2993 unsigned get_num_channels_from_data_format(unsigned data_format)
2994 {
2995    switch (data_format) {
2996    case V_008F0C_BUF_DATA_FORMAT_8:
2997    case V_008F0C_BUF_DATA_FORMAT_16:
2998    case V_008F0C_BUF_DATA_FORMAT_32:
2999       return 1;
3000    case V_008F0C_BUF_DATA_FORMAT_8_8:
3001    case V_008F0C_BUF_DATA_FORMAT_16_16:
3002    case V_008F0C_BUF_DATA_FORMAT_32_32:
3003       return 2;
3004    case V_008F0C_BUF_DATA_FORMAT_10_11_11:
3005    case V_008F0C_BUF_DATA_FORMAT_11_11_10:
3006    case V_008F0C_BUF_DATA_FORMAT_32_32_32:
3007       return 3;
3008    case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
3009    case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
3010    case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
3011    case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
3012    case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
3013       return 4;
3014    default:
3015       break;
3016    }
3017
3018    return 4;
3019 }
3020
3021 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3022  * so we may need to fix it up. */
3023 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3024 {
3025    Builder bld(ctx->program, ctx->block);
3026
3027    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3028       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3029
3030    /* For the integer-like cases, do a natural sign extension.
3031     *
3032     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3033     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3034     * exponent.
3035     */
3036    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3037    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3038
3039    /* Convert back to the right type. */
3040    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3041       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3042       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3043       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3044    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3045       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3046    }
3047
3048    return alpha;
3049 }
3050
3051 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3052 {
3053    Builder bld(ctx->program, ctx->block);
3054    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3055    if (ctx->stage & sw_vs) {
3056
3057       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3058       if (off_instr->type != nir_instr_type_load_const) {
3059          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3060          nir_print_instr(off_instr, stderr);
3061          fprintf(stderr, "\n");
3062       }
3063       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3064
3065       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3066
3067       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3068       unsigned component = nir_intrinsic_component(instr);
3069       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3070       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3071       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3072       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3073
3074       unsigned dfmt = attrib_format & 0xf;
3075
3076       unsigned nfmt = (attrib_format >> 4) & 0x7;
3077       unsigned num_dfmt_channels = get_num_channels_from_data_format(dfmt);
3078       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3079       unsigned num_channels = MIN2(util_last_bit(mask), num_dfmt_channels);
3080       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3081       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3082       if (post_shuffle)
3083          num_channels = MAX2(num_channels, 3);
3084
3085       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, Operand(attrib_binding * 16u));
3086
3087       Temp index;
3088       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3089          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3090          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3091          if (divisor) {
3092             ctx->needs_instance_id = true;
3093             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3094             if (divisor != 1) {
3095                Temp divided = bld.tmp(v1);
3096                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3097                index = bld.vadd32(bld.def(v1), start_instance, divided);
3098             } else {
3099                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3100             }
3101          } else {
3102             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3103          }
3104       } else {
3105          index = bld.vadd32(bld.def(v1),
3106                             get_arg(ctx, ctx->args->ac.base_vertex),
3107                             get_arg(ctx, ctx->args->ac.vertex_id));
3108       }
3109
3110       if (attrib_stride != 0 && attrib_offset > attrib_stride) {
3111          index = bld.vadd32(bld.def(v1), Operand(attrib_offset / attrib_stride), index);
3112          attrib_offset = attrib_offset % attrib_stride;
3113       }
3114
3115       Operand soffset(0u);
3116       if (attrib_offset >= 4096) {
3117          soffset = bld.copy(bld.def(s1), Operand(attrib_offset));
3118          attrib_offset = 0;
3119       }
3120
3121       aco_opcode opcode;
3122       switch (num_channels) {
3123       case 1:
3124          opcode = aco_opcode::tbuffer_load_format_x;
3125          break;
3126       case 2:
3127          opcode = aco_opcode::tbuffer_load_format_xy;
3128          break;
3129       case 3:
3130          opcode = aco_opcode::tbuffer_load_format_xyz;
3131          break;
3132       case 4:
3133          opcode = aco_opcode::tbuffer_load_format_xyzw;
3134          break;
3135       default:
3136          unreachable("Unimplemented load_input vector size");
3137       }
3138
3139       Temp tmp = post_shuffle || num_channels != dst.size() || alpha_adjust != RADV_ALPHA_ADJUST_NONE || component ? bld.tmp(RegType::vgpr, num_channels) : dst;
3140
3141       aco_ptr<MTBUF_instruction> mubuf{create_instruction<MTBUF_instruction>(opcode, Format::MTBUF, 3, 1)};
3142       mubuf->operands[0] = Operand(index);
3143       mubuf->operands[1] = Operand(list);
3144       mubuf->operands[2] = soffset;
3145       mubuf->definitions[0] = Definition(tmp);
3146       mubuf->idxen = true;
3147       mubuf->can_reorder = true;
3148       mubuf->dfmt = dfmt;
3149       mubuf->nfmt = nfmt;
3150       assert(attrib_offset < 4096);
3151       mubuf->offset = attrib_offset;
3152       ctx->block->instructions.emplace_back(std::move(mubuf));
3153
3154       emit_split_vector(ctx, tmp, tmp.size());
3155
3156       if (tmp.id() != dst.id()) {
3157          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3158                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3159
3160          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3161          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3162          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3163
3164          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3165          for (unsigned i = 0; i < dst.size(); i++) {
3166             unsigned idx = i + component;
3167             if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE && num_channels >= 4) {
3168                Temp alpha = emit_extract_vector(ctx, tmp, swizzle[3], v1);
3169                vec->operands[3] = Operand(adjust_vertex_fetch_alpha(ctx, alpha_adjust, alpha));
3170             } else if (idx < num_channels) {
3171                vec->operands[i] = Operand(emit_extract_vector(ctx, tmp, swizzle[idx], v1));
3172             } else if (is_float && idx == 3) {
3173                vec->operands[i] = Operand(0x3f800000u);
3174             } else if (!is_float && idx == 3) {
3175                vec->operands[i] = Operand(1u);
3176             } else {
3177                vec->operands[i] = Operand(0u);
3178             }
3179          }
3180          vec->definitions[0] = Definition(dst);
3181          ctx->block->instructions.emplace_back(std::move(vec));
3182          emit_split_vector(ctx, dst, dst.size());
3183       }
3184
3185    } else if (ctx->stage == fragment_fs) {
3186       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3187       if (off_instr->type != nir_instr_type_load_const ||
3188           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3189          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3190          nir_print_instr(off_instr, stderr);
3191          fprintf(stderr, "\n");
3192       }
3193
3194       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3195       nir_const_value* offset = nir_src_as_const_value(instr->src[0]);
3196       if (offset) {
3197          assert(offset->u32 == 0);
3198       } else {
3199          /* the lower 15bit of the prim_mask contain the offset into LDS
3200           * while the upper bits contain the number of prims */
3201          Temp offset_src = get_ssa_temp(ctx, instr->src[0].ssa);
3202          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3203          Builder bld(ctx->program, ctx->block);
3204          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3205          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3206          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3207          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3208          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3209       }
3210
3211       unsigned idx = nir_intrinsic_base(instr);
3212       unsigned component = nir_intrinsic_component(instr);
3213
3214       if (dst.size() == 1) {
3215          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(2u), bld.m0(prim_mask), idx, component);
3216       } else {
3217          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3218          for (unsigned i = 0; i < dst.size(); i++)
3219             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(2u), bld.m0(prim_mask), idx, component + i);
3220          vec->definitions[0] = Definition(dst);
3221          bld.insert(std::move(vec));
3222       }
3223
3224    } else {
3225       unreachable("Shader stage not implemented");
3226    }
3227 }
3228
3229 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3230 {
3231    if (ctx->program->info->need_indirect_descriptor_sets) {
3232       Builder bld(ctx->program, ctx->block);
3233       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3234       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, Operand(desc_set << 2));//, false, false, false);
3235    }
3236
3237    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3238 }
3239
3240
3241 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3242 {
3243    Builder bld(ctx->program, ctx->block);
3244    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3245    if (!ctx->divergent_vals[instr->dest.ssa.index])
3246       index = bld.as_uniform(index);
3247    unsigned desc_set = nir_intrinsic_desc_set(instr);
3248    unsigned binding = nir_intrinsic_binding(instr);
3249
3250    Temp desc_ptr;
3251    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3252    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3253    unsigned offset = layout->binding[binding].offset;
3254    unsigned stride;
3255    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3256        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3257       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3258       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3259       offset = pipeline_layout->push_constant_size + 16 * idx;
3260       stride = 16;
3261    } else {
3262       desc_ptr = load_desc_ptr(ctx, desc_set);
3263       stride = layout->binding[binding].size;
3264    }
3265
3266    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3267    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3268    if (stride != 1) {
3269       if (nir_const_index) {
3270          const_index = const_index * stride;
3271       } else if (index.type() == RegType::vgpr) {
3272          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3273          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3274       } else {
3275          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3276       }
3277    }
3278    if (offset) {
3279       if (nir_const_index) {
3280          const_index = const_index + offset;
3281       } else if (index.type() == RegType::vgpr) {
3282          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3283       } else {
3284          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3285       }
3286    }
3287
3288    if (nir_const_index && const_index == 0) {
3289       index = desc_ptr;
3290    } else if (index.type() == RegType::vgpr) {
3291       index = bld.vadd32(bld.def(v1),
3292                          nir_const_index ? Operand(const_index) : Operand(index),
3293                          Operand(desc_ptr));
3294    } else {
3295       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3296                        nir_const_index ? Operand(const_index) : Operand(index),
3297                        Operand(desc_ptr));
3298    }
3299
3300    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3301 }
3302
3303 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3304                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3305 {
3306    Builder bld(ctx->program, ctx->block);
3307
3308    unsigned num_bytes = dst.size() * 4;
3309    bool dlc = glc && ctx->options->chip_class >= GFX10;
3310
3311    aco_opcode op;
3312    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
3313       if (ctx->options->chip_class < GFX8)
3314          offset = as_vgpr(ctx, offset);
3315
3316       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3317       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3318       unsigned const_offset = 0;
3319
3320       Temp lower = Temp();
3321       if (num_bytes > 16) {
3322          assert(num_components == 3 || num_components == 4);
3323          op = aco_opcode::buffer_load_dwordx4;
3324          lower = bld.tmp(v4);
3325          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3326          mubuf->definitions[0] = Definition(lower);
3327          mubuf->operands[0] = vaddr;
3328          mubuf->operands[1] = Operand(rsrc);
3329          mubuf->operands[2] = soffset;
3330          mubuf->offen = (offset.type() == RegType::vgpr);
3331          mubuf->glc = glc;
3332          mubuf->dlc = dlc;
3333          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3334          mubuf->can_reorder = readonly;
3335          bld.insert(std::move(mubuf));
3336          emit_split_vector(ctx, lower, 2);
3337          num_bytes -= 16;
3338          const_offset = 16;
3339       }
3340
3341       switch (num_bytes) {
3342          case 4:
3343             op = aco_opcode::buffer_load_dword;
3344             break;
3345          case 8:
3346             op = aco_opcode::buffer_load_dwordx2;
3347             break;
3348          case 12:
3349             op = aco_opcode::buffer_load_dwordx3;
3350             break;
3351          case 16:
3352             op = aco_opcode::buffer_load_dwordx4;
3353             break;
3354          default:
3355             unreachable("Load SSBO not implemented for this size.");
3356       }
3357       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3358       mubuf->operands[0] = vaddr;
3359       mubuf->operands[1] = Operand(rsrc);
3360       mubuf->operands[2] = soffset;
3361       mubuf->offen = (offset.type() == RegType::vgpr);
3362       mubuf->glc = glc;
3363       mubuf->dlc = dlc;
3364       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3365       mubuf->can_reorder = readonly;
3366       mubuf->offset = const_offset;
3367       aco_ptr<Instruction> instr = std::move(mubuf);
3368
3369       if (dst.size() > 4) {
3370          assert(lower != Temp());
3371          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3372          instr->definitions[0] = Definition(upper);
3373          bld.insert(std::move(instr));
3374          if (dst.size() == 8)
3375             emit_split_vector(ctx, upper, 2);
3376          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3377          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3378          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3379          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3380          if (dst.size() == 8)
3381             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3382       }
3383
3384       if (dst.type() == RegType::sgpr) {
3385          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3386          instr->definitions[0] = Definition(vec);
3387          bld.insert(std::move(instr));
3388          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
3389       } else {
3390          instr->definitions[0] = Definition(dst);
3391          bld.insert(std::move(instr));
3392       }
3393    } else {
3394       switch (num_bytes) {
3395          case 4:
3396             op = aco_opcode::s_buffer_load_dword;
3397             break;
3398          case 8:
3399             op = aco_opcode::s_buffer_load_dwordx2;
3400             break;
3401          case 12:
3402          case 16:
3403             op = aco_opcode::s_buffer_load_dwordx4;
3404             break;
3405          case 24:
3406          case 32:
3407             op = aco_opcode::s_buffer_load_dwordx8;
3408             break;
3409          default:
3410             unreachable("Load SSBO not implemented for this size.");
3411       }
3412       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3413       load->operands[0] = Operand(rsrc);
3414       load->operands[1] = Operand(bld.as_uniform(offset));
3415       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3416       load->definitions[0] = Definition(dst);
3417       load->glc = glc;
3418       load->dlc = dlc;
3419       load->barrier = readonly ? barrier_none : barrier_buffer;
3420       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3421       assert(ctx->options->chip_class >= GFX8 || !glc);
3422
3423       /* trim vector */
3424       if (dst.size() == 3) {
3425          Temp vec = bld.tmp(s4);
3426          load->definitions[0] = Definition(vec);
3427          bld.insert(std::move(load));
3428          emit_split_vector(ctx, vec, 4);
3429
3430          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3431                     emit_extract_vector(ctx, vec, 0, s1),
3432                     emit_extract_vector(ctx, vec, 1, s1),
3433                     emit_extract_vector(ctx, vec, 2, s1));
3434       } else if (dst.size() == 6) {
3435          Temp vec = bld.tmp(s8);
3436          load->definitions[0] = Definition(vec);
3437          bld.insert(std::move(load));
3438          emit_split_vector(ctx, vec, 4);
3439
3440          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3441                     emit_extract_vector(ctx, vec, 0, s2),
3442                     emit_extract_vector(ctx, vec, 1, s2),
3443                     emit_extract_vector(ctx, vec, 2, s2));
3444       } else {
3445          bld.insert(std::move(load));
3446       }
3447
3448    }
3449    emit_split_vector(ctx, dst, num_components);
3450 }
3451
3452 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3453 {
3454    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3455    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3456
3457    Builder bld(ctx->program, ctx->block);
3458
3459    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3460    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3461    unsigned binding = nir_intrinsic_binding(idx_instr);
3462    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3463
3464    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3465       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3466                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3467                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3468                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3469       if (ctx->options->chip_class >= GFX10) {
3470          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3471                       S_008F0C_OOB_SELECT(3) |
3472                       S_008F0C_RESOURCE_LEVEL(1);
3473       } else {
3474          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3475                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3476       }
3477       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3478                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3479                                      Operand(0xFFFFFFFFu),
3480                                      Operand(desc_type));
3481       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3482                         rsrc, upper_dwords);
3483    } else {
3484       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3485       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3486    }
3487
3488    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3489 }
3490
3491 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3492 {
3493    Builder bld(ctx->program, ctx->block);
3494    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3495
3496    unsigned offset = nir_intrinsic_base(instr);
3497    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3498    if (index_cv && instr->dest.ssa.bit_size == 32) {
3499
3500       unsigned count = instr->dest.ssa.num_components;
3501       unsigned start = (offset + index_cv->u32) / 4u;
3502       start -= ctx->args->ac.base_inline_push_consts;
3503       if (start + count <= ctx->args->ac.num_inline_push_consts) {
3504          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3505          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3506          for (unsigned i = 0; i < count; ++i) {
3507             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
3508             vec->operands[i] = Operand{elems[i]};
3509          }
3510          vec->definitions[0] = Definition(dst);
3511          ctx->block->instructions.emplace_back(std::move(vec));
3512          ctx->allocated_vec.emplace(dst.id(), elems);
3513          return;
3514       }
3515    }
3516
3517    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3518    if (offset != 0) // TODO check if index != 0 as well
3519       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3520    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
3521    Temp vec = dst;
3522    bool trim = false;
3523    aco_opcode op;
3524
3525    switch (dst.size()) {
3526    case 1:
3527       op = aco_opcode::s_load_dword;
3528       break;
3529    case 2:
3530       op = aco_opcode::s_load_dwordx2;
3531       break;
3532    case 3:
3533       vec = bld.tmp(s4);
3534       trim = true;
3535    case 4:
3536       op = aco_opcode::s_load_dwordx4;
3537       break;
3538    case 6:
3539       vec = bld.tmp(s8);
3540       trim = true;
3541    case 8:
3542       op = aco_opcode::s_load_dwordx8;
3543       break;
3544    default:
3545       unreachable("unimplemented or forbidden load_push_constant.");
3546    }
3547
3548    bld.smem(op, Definition(vec), ptr, index);
3549
3550    if (trim) {
3551       emit_split_vector(ctx, vec, 4);
3552       RegClass rc = dst.size() == 3 ? s1 : s2;
3553       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3554                  emit_extract_vector(ctx, vec, 0, rc),
3555                  emit_extract_vector(ctx, vec, 1, rc),
3556                  emit_extract_vector(ctx, vec, 2, rc));
3557
3558    }
3559    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3560 }
3561
3562 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3563 {
3564    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3565
3566    Builder bld(ctx->program, ctx->block);
3567
3568    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3569                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3570                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3571                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3572    if (ctx->options->chip_class >= GFX10) {
3573       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3574                    S_008F0C_OOB_SELECT(3) |
3575                    S_008F0C_RESOURCE_LEVEL(1);
3576    } else {
3577       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3578                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3579    }
3580
3581    unsigned base = nir_intrinsic_base(instr);
3582    unsigned range = nir_intrinsic_range(instr);
3583
3584    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3585    if (base && offset.type() == RegType::sgpr)
3586       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3587    else if (base && offset.type() == RegType::vgpr)
3588       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3589
3590    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3591                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3592                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3593                           Operand(desc_type));
3594
3595    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3596 }
3597
3598 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3599 {
3600    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3601       ctx->cf_info.exec_potentially_empty = true;
3602
3603    ctx->program->needs_exact = true;
3604
3605    // TODO: optimize uniform conditions
3606    Builder bld(ctx->program, ctx->block);
3607    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3608    assert(src.regClass() == bld.lm);
3609    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
3610    bld.pseudo(aco_opcode::p_discard_if, src);
3611    ctx->block->kind |= block_kind_uses_discard_if;
3612    return;
3613 }
3614
3615 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3616 {
3617    Builder bld(ctx->program, ctx->block);
3618
3619    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3620       ctx->cf_info.exec_potentially_empty = true;
3621
3622    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3623                     ctx->cf_info.parent_loop.has_divergent_continue;
3624
3625    if (ctx->block->loop_nest_depth &&
3626        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3627       /* we handle discards the same way as jump instructions */
3628       append_logical_end(ctx->block);
3629
3630       /* in loops, discard behaves like break */
3631       Block *linear_target = ctx->cf_info.parent_loop.exit;
3632       ctx->block->kind |= block_kind_discard;
3633
3634       if (!divergent) {
3635          /* uniform discard - loop ends here */
3636          assert(nir_instr_is_last(&instr->instr));
3637          ctx->block->kind |= block_kind_uniform;
3638          ctx->cf_info.has_branch = true;
3639          bld.branch(aco_opcode::p_branch);
3640          add_linear_edge(ctx->block->index, linear_target);
3641          return;
3642       }
3643
3644       /* we add a break right behind the discard() instructions */
3645       ctx->block->kind |= block_kind_break;
3646       unsigned idx = ctx->block->index;
3647
3648       /* remove critical edges from linear CFG */
3649       bld.branch(aco_opcode::p_branch);
3650       Block* break_block = ctx->program->create_and_insert_block();
3651       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3652       break_block->kind |= block_kind_uniform;
3653       add_linear_edge(idx, break_block);
3654       add_linear_edge(break_block->index, linear_target);
3655       bld.reset(break_block);
3656       bld.branch(aco_opcode::p_branch);
3657
3658       Block* continue_block = ctx->program->create_and_insert_block();
3659       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3660       add_linear_edge(idx, continue_block);
3661       append_logical_start(continue_block);
3662       ctx->block = continue_block;
3663
3664       return;
3665    }
3666
3667    /* it can currently happen that NIR doesn't remove the unreachable code */
3668    if (!nir_instr_is_last(&instr->instr)) {
3669       ctx->program->needs_exact = true;
3670       /* save exec somewhere temporarily so that it doesn't get
3671        * overwritten before the discard from outer exec masks */
3672       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
3673       bld.pseudo(aco_opcode::p_discard_if, cond);
3674       ctx->block->kind |= block_kind_uses_discard_if;
3675       return;
3676    }
3677
3678    /* This condition is incorrect for uniformly branched discards in a loop
3679     * predicated by a divergent condition, but the above code catches that case
3680     * and the discard would end up turning into a discard_if.
3681     * For example:
3682     * if (divergent) {
3683     *    while (...) {
3684     *       if (uniform) {
3685     *          discard;
3686     *       }
3687     *    }
3688     * }
3689     */
3690    if (!ctx->cf_info.parent_if.is_divergent) {
3691       /* program just ends here */
3692       ctx->block->kind |= block_kind_uniform;
3693       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
3694               0 /* enabled mask */, 9 /* dest */,
3695               false /* compressed */, true/* done */, true /* valid mask */);
3696       bld.sopp(aco_opcode::s_endpgm);
3697       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3698    } else {
3699       ctx->block->kind |= block_kind_discard;
3700       /* branch and linear edge is added by visit_if() */
3701    }
3702 }
3703
3704 enum aco_descriptor_type {
3705    ACO_DESC_IMAGE,
3706    ACO_DESC_FMASK,
3707    ACO_DESC_SAMPLER,
3708    ACO_DESC_BUFFER,
3709    ACO_DESC_PLANE_0,
3710    ACO_DESC_PLANE_1,
3711    ACO_DESC_PLANE_2,
3712 };
3713
3714 static bool
3715 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
3716    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
3717       return false;
3718    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
3719    return dim == ac_image_cube ||
3720           dim == ac_image_1darray ||
3721           dim == ac_image_2darray ||
3722           dim == ac_image_2darraymsaa;
3723 }
3724
3725 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
3726                       enum aco_descriptor_type desc_type,
3727                       const nir_tex_instr *tex_instr, bool image, bool write)
3728 {
3729 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3730    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3731    if (it != ctx->tex_desc.end())
3732       return it->second;
3733 */
3734    Temp index = Temp();
3735    bool index_set = false;
3736    unsigned constant_index = 0;
3737    unsigned descriptor_set;
3738    unsigned base_index;
3739    Builder bld(ctx->program, ctx->block);
3740
3741    if (!deref_instr) {
3742       assert(tex_instr && !image);
3743       descriptor_set = 0;
3744       base_index = tex_instr->sampler_index;
3745    } else {
3746       while(deref_instr->deref_type != nir_deref_type_var) {
3747          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
3748          if (!array_size)
3749             array_size = 1;
3750
3751          assert(deref_instr->deref_type == nir_deref_type_array);
3752          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
3753          if (const_value) {
3754             constant_index += array_size * const_value->u32;
3755          } else {
3756             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
3757             if (indirect.type() == RegType::vgpr)
3758                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
3759
3760             if (array_size != 1)
3761                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
3762
3763             if (!index_set) {
3764                index = indirect;
3765                index_set = true;
3766             } else {
3767                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
3768             }
3769          }
3770
3771          deref_instr = nir_src_as_deref(deref_instr->parent);
3772       }
3773       descriptor_set = deref_instr->var->data.descriptor_set;
3774       base_index = deref_instr->var->data.binding;
3775    }
3776
3777    Temp list = load_desc_ptr(ctx, descriptor_set);
3778    list = convert_pointer_to_64_bit(ctx, list);
3779
3780    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
3781    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
3782    unsigned offset = binding->offset;
3783    unsigned stride = binding->size;
3784    aco_opcode opcode;
3785    RegClass type;
3786
3787    assert(base_index < layout->binding_count);
3788
3789    switch (desc_type) {
3790    case ACO_DESC_IMAGE:
3791       type = s8;
3792       opcode = aco_opcode::s_load_dwordx8;
3793       break;
3794    case ACO_DESC_FMASK:
3795       type = s8;
3796       opcode = aco_opcode::s_load_dwordx8;
3797       offset += 32;
3798       break;
3799    case ACO_DESC_SAMPLER:
3800       type = s4;
3801       opcode = aco_opcode::s_load_dwordx4;
3802       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3803          offset += radv_combined_image_descriptor_sampler_offset(binding);
3804       break;
3805    case ACO_DESC_BUFFER:
3806       type = s4;
3807       opcode = aco_opcode::s_load_dwordx4;
3808       break;
3809    case ACO_DESC_PLANE_0:
3810    case ACO_DESC_PLANE_1:
3811       type = s8;
3812       opcode = aco_opcode::s_load_dwordx8;
3813       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
3814       break;
3815    case ACO_DESC_PLANE_2:
3816       type = s4;
3817       opcode = aco_opcode::s_load_dwordx4;
3818       offset += 64;
3819       break;
3820    default:
3821       unreachable("invalid desc_type\n");
3822    }
3823
3824    offset += constant_index * stride;
3825
3826    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
3827       (!index_set || binding->immutable_samplers_equal)) {
3828       if (binding->immutable_samplers_equal)
3829          constant_index = 0;
3830
3831       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3832       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3833                         Operand(samplers[constant_index * 4 + 0]),
3834                         Operand(samplers[constant_index * 4 + 1]),
3835                         Operand(samplers[constant_index * 4 + 2]),
3836                         Operand(samplers[constant_index * 4 + 3]));
3837    }
3838
3839    Operand off;
3840    if (!index_set) {
3841       off = Operand(offset);
3842    } else {
3843       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
3844                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
3845    }
3846
3847    Temp res = bld.smem(opcode, bld.def(type), list, off);
3848
3849    if (desc_type == ACO_DESC_PLANE_2) {
3850       Temp components[8];
3851       for (unsigned i = 0; i < 8; i++)
3852          components[i] = bld.tmp(s1);
3853       bld.pseudo(aco_opcode::p_split_vector,
3854                  Definition(components[0]),
3855                  Definition(components[1]),
3856                  Definition(components[2]),
3857                  Definition(components[3]),
3858                  res);
3859
3860       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
3861       bld.pseudo(aco_opcode::p_split_vector,
3862                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
3863                  Definition(components[4]),
3864                  Definition(components[5]),
3865                  Definition(components[6]),
3866                  Definition(components[7]),
3867                  desc2);
3868
3869       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
3870                        components[0], components[1], components[2], components[3],
3871                        components[4], components[5], components[6], components[7]);
3872    }
3873
3874    return res;
3875 }
3876
3877 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3878 {
3879    switch (dim) {
3880    case GLSL_SAMPLER_DIM_BUF:
3881       return 1;
3882    case GLSL_SAMPLER_DIM_1D:
3883       return array ? 2 : 1;
3884    case GLSL_SAMPLER_DIM_2D:
3885       return array ? 3 : 2;
3886    case GLSL_SAMPLER_DIM_MS:
3887       return array ? 4 : 3;
3888    case GLSL_SAMPLER_DIM_3D:
3889    case GLSL_SAMPLER_DIM_CUBE:
3890       return 3;
3891    case GLSL_SAMPLER_DIM_RECT:
3892    case GLSL_SAMPLER_DIM_SUBPASS:
3893       return 2;
3894    case GLSL_SAMPLER_DIM_SUBPASS_MS:
3895       return 3;
3896    default:
3897       break;
3898    }
3899    return 0;
3900 }
3901
3902
3903 /* Adjust the sample index according to FMASK.
3904  *
3905  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3906  * which is the identity mapping. Each nibble says which physical sample
3907  * should be fetched to get that sample.
3908  *
3909  * For example, 0x11111100 means there are only 2 samples stored and
3910  * the second sample covers 3/4 of the pixel. When reading samples 0
3911  * and 1, return physical sample 0 (determined by the first two 0s
3912  * in FMASK), otherwise return physical sample 1.
3913  *
3914  * The sample index should be adjusted as follows:
3915  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
3916  */
3917 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, Temp coords, Operand sample_index, Temp fmask_desc_ptr)
3918 {
3919    Builder bld(ctx->program, ctx->block);
3920    Temp fmask = bld.tmp(v1);
3921    unsigned dim = ctx->options->chip_class >= GFX10
3922                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
3923                   : 0;
3924
3925    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3926    load->operands[0] = Operand(coords);
3927    load->operands[1] = Operand(fmask_desc_ptr);
3928    load->definitions[0] = Definition(fmask);
3929    load->glc = false;
3930    load->dlc = false;
3931    load->dmask = 0x1;
3932    load->unrm = true;
3933    load->da = da;
3934    load->dim = dim;
3935    load->can_reorder = true; /* fmask images shouldn't be modified */
3936    ctx->block->instructions.emplace_back(std::move(load));
3937
3938    Operand sample_index4;
3939    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
3940       sample_index4 = Operand(sample_index.constantValue() << 2);
3941    } else if (sample_index.regClass() == s1) {
3942       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
3943    } else {
3944       assert(sample_index.regClass() == v1);
3945       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
3946    }
3947
3948    Temp final_sample;
3949    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
3950       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
3951    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
3952       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
3953    else
3954       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
3955
3956    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3957     * resource descriptor is 0 (invalid),
3958     */
3959    Temp compare = bld.tmp(bld.lm);
3960    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
3961                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
3962
3963    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
3964
3965    /* Replace the MSAA sample index. */
3966    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
3967 }
3968
3969 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
3970 {
3971
3972    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
3973    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3974    bool is_array = glsl_sampler_type_is_array(type);
3975    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3976    assert(!add_frag_pos && "Input attachments should be lowered.");
3977    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3978    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3979    int count = image_type_to_components_count(dim, is_array);
3980    std::vector<Operand> coords(count);
3981
3982    if (is_ms) {
3983       Operand sample_index;
3984       nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
3985       if (sample_cv)
3986          sample_index = Operand(sample_cv->u32);
3987       else
3988          sample_index = Operand(emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[2].ssa), 0, v1));
3989
3990       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
3991          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, is_array ? 3 : 2, 1)};
3992          for (unsigned i = 0; i < vec->operands.size(); i++)
3993             vec->operands[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
3994          Temp fmask_load_address = {ctx->program->allocateId(), is_array ? v3 : v2};
3995          vec->definitions[0] = Definition(fmask_load_address);
3996          ctx->block->instructions.emplace_back(std::move(vec));
3997
3998          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
3999          sample_index = Operand(adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr));
4000       }
4001       count--;
4002       coords[count] = sample_index;
4003    }
4004
4005    if (count == 1 && !gfx9_1d)
4006       return emit_extract_vector(ctx, src0, 0, v1);
4007
4008    if (gfx9_1d) {
4009       coords[0] = Operand(emit_extract_vector(ctx, src0, 0, v1));
4010       coords.resize(coords.size() + 1);
4011       coords[1] = Operand((uint32_t) 0);
4012       if (is_array)
4013          coords[2] = Operand(emit_extract_vector(ctx, src0, 1, v1));
4014    } else {
4015       for (int i = 0; i < count; i++)
4016          coords[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
4017    }
4018
4019    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4020    for (unsigned i = 0; i < coords.size(); i++)
4021       vec->operands[i] = coords[i];
4022    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4023    vec->definitions[0] = Definition(res);
4024    ctx->block->instructions.emplace_back(std::move(vec));
4025    return res;
4026 }
4027
4028
4029 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4030 {
4031    Builder bld(ctx->program, ctx->block);
4032    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4033    const struct glsl_type *type = glsl_without_array(var->type);
4034    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4035    bool is_array = glsl_sampler_type_is_array(type);
4036    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4037
4038    if (dim == GLSL_SAMPLER_DIM_BUF) {
4039       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4040       unsigned num_channels = util_last_bit(mask);
4041       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4042       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4043
4044       aco_opcode opcode;
4045       switch (num_channels) {
4046       case 1:
4047          opcode = aco_opcode::buffer_load_format_x;
4048          break;
4049       case 2:
4050          opcode = aco_opcode::buffer_load_format_xy;
4051          break;
4052       case 3:
4053          opcode = aco_opcode::buffer_load_format_xyz;
4054          break;
4055       case 4:
4056          opcode = aco_opcode::buffer_load_format_xyzw;
4057          break;
4058       default:
4059          unreachable(">4 channel buffer image load");
4060       }
4061       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4062       load->operands[0] = Operand(vindex);
4063       load->operands[1] = Operand(rsrc);
4064       load->operands[2] = Operand((uint32_t) 0);
4065       Temp tmp;
4066       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4067          tmp = dst;
4068       else
4069          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4070       load->definitions[0] = Definition(tmp);
4071       load->idxen = true;
4072       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4073       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4074       load->barrier = barrier_image;
4075       ctx->block->instructions.emplace_back(std::move(load));
4076
4077       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4078       return;
4079    }
4080
4081    Temp coords = get_image_coords(ctx, instr, type);
4082    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4083
4084    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4085    unsigned num_components = util_bitcount(dmask);
4086    Temp tmp;
4087    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4088       tmp = dst;
4089    else
4090       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4091
4092    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
4093    load->operands[0] = Operand(coords);
4094    load->operands[1] = Operand(resource);
4095    load->definitions[0] = Definition(tmp);
4096    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4097    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4098    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4099    load->dmask = dmask;
4100    load->unrm = true;
4101    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4102    load->barrier = barrier_image;
4103    ctx->block->instructions.emplace_back(std::move(load));
4104
4105    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4106    return;
4107 }
4108
4109 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4110 {
4111    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4112    const struct glsl_type *type = glsl_without_array(var->type);
4113    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4114    bool is_array = glsl_sampler_type_is_array(type);
4115    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4116
4117    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4118
4119    if (dim == GLSL_SAMPLER_DIM_BUF) {
4120       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4121       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4122       aco_opcode opcode;
4123       switch (data.size()) {
4124       case 1:
4125          opcode = aco_opcode::buffer_store_format_x;
4126          break;
4127       case 2:
4128          opcode = aco_opcode::buffer_store_format_xy;
4129          break;
4130       case 3:
4131          opcode = aco_opcode::buffer_store_format_xyz;
4132          break;
4133       case 4:
4134          opcode = aco_opcode::buffer_store_format_xyzw;
4135          break;
4136       default:
4137          unreachable(">4 channel buffer image store");
4138       }
4139       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4140       store->operands[0] = Operand(vindex);
4141       store->operands[1] = Operand(rsrc);
4142       store->operands[2] = Operand((uint32_t) 0);
4143       store->operands[3] = Operand(data);
4144       store->idxen = true;
4145       store->glc = glc;
4146       store->dlc = false;
4147       store->disable_wqm = true;
4148       store->barrier = barrier_image;
4149       ctx->program->needs_exact = true;
4150       ctx->block->instructions.emplace_back(std::move(store));
4151       return;
4152    }
4153
4154    assert(data.type() == RegType::vgpr);
4155    Temp coords = get_image_coords(ctx, instr, type);
4156    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4157
4158    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(aco_opcode::image_store, Format::MIMG, 4, 0)};
4159    store->operands[0] = Operand(coords);
4160    store->operands[1] = Operand(resource);
4161    store->operands[2] = Operand(s4);
4162    store->operands[3] = Operand(data);
4163    store->glc = glc;
4164    store->dlc = false;
4165    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4166    store->dmask = (1 << data.size()) - 1;
4167    store->unrm = true;
4168    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4169    store->disable_wqm = true;
4170    store->barrier = barrier_image;
4171    ctx->program->needs_exact = true;
4172    ctx->block->instructions.emplace_back(std::move(store));
4173    return;
4174 }
4175
4176 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4177 {
4178    /* return the previous value if dest is ever used */
4179    bool return_previous = false;
4180    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4181       return_previous = true;
4182       break;
4183    }
4184    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4185       return_previous = true;
4186       break;
4187    }
4188
4189    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4190    const struct glsl_type *type = glsl_without_array(var->type);
4191    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4192    bool is_array = glsl_sampler_type_is_array(type);
4193    Builder bld(ctx->program, ctx->block);
4194
4195    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4196    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4197
4198    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4199       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4200
4201    aco_opcode buf_op, image_op;
4202    switch (instr->intrinsic) {
4203       case nir_intrinsic_image_deref_atomic_add:
4204          buf_op = aco_opcode::buffer_atomic_add;
4205          image_op = aco_opcode::image_atomic_add;
4206          break;
4207       case nir_intrinsic_image_deref_atomic_umin:
4208          buf_op = aco_opcode::buffer_atomic_umin;
4209          image_op = aco_opcode::image_atomic_umin;
4210          break;
4211       case nir_intrinsic_image_deref_atomic_imin:
4212          buf_op = aco_opcode::buffer_atomic_smin;
4213          image_op = aco_opcode::image_atomic_smin;
4214          break;
4215       case nir_intrinsic_image_deref_atomic_umax:
4216          buf_op = aco_opcode::buffer_atomic_umax;
4217          image_op = aco_opcode::image_atomic_umax;
4218          break;
4219       case nir_intrinsic_image_deref_atomic_imax:
4220          buf_op = aco_opcode::buffer_atomic_smax;
4221          image_op = aco_opcode::image_atomic_smax;
4222          break;
4223       case nir_intrinsic_image_deref_atomic_and:
4224          buf_op = aco_opcode::buffer_atomic_and;
4225          image_op = aco_opcode::image_atomic_and;
4226          break;
4227       case nir_intrinsic_image_deref_atomic_or:
4228          buf_op = aco_opcode::buffer_atomic_or;
4229          image_op = aco_opcode::image_atomic_or;
4230          break;
4231       case nir_intrinsic_image_deref_atomic_xor:
4232          buf_op = aco_opcode::buffer_atomic_xor;
4233          image_op = aco_opcode::image_atomic_xor;
4234          break;
4235       case nir_intrinsic_image_deref_atomic_exchange:
4236          buf_op = aco_opcode::buffer_atomic_swap;
4237          image_op = aco_opcode::image_atomic_swap;
4238          break;
4239       case nir_intrinsic_image_deref_atomic_comp_swap:
4240          buf_op = aco_opcode::buffer_atomic_cmpswap;
4241          image_op = aco_opcode::image_atomic_cmpswap;
4242          break;
4243       default:
4244          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4245    }
4246
4247    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4248
4249    if (dim == GLSL_SAMPLER_DIM_BUF) {
4250       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4251       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4252       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4253       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4254       mubuf->operands[0] = Operand(vindex);
4255       mubuf->operands[1] = Operand(resource);
4256       mubuf->operands[2] = Operand((uint32_t)0);
4257       mubuf->operands[3] = Operand(data);
4258       if (return_previous)
4259          mubuf->definitions[0] = Definition(dst);
4260       mubuf->offset = 0;
4261       mubuf->idxen = true;
4262       mubuf->glc = return_previous;
4263       mubuf->dlc = false; /* Not needed for atomics */
4264       mubuf->disable_wqm = true;
4265       mubuf->barrier = barrier_image;
4266       ctx->program->needs_exact = true;
4267       ctx->block->instructions.emplace_back(std::move(mubuf));
4268       return;
4269    }
4270
4271    Temp coords = get_image_coords(ctx, instr, type);
4272    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4273    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 4, return_previous ? 1 : 0)};
4274    mimg->operands[0] = Operand(coords);
4275    mimg->operands[1] = Operand(resource);
4276    mimg->operands[2] = Operand(s4); /* no sampler */
4277    mimg->operands[3] = Operand(data);
4278    if (return_previous)
4279       mimg->definitions[0] = Definition(dst);
4280    mimg->glc = return_previous;
4281    mimg->dlc = false; /* Not needed for atomics */
4282    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4283    mimg->dmask = (1 << data.size()) - 1;
4284    mimg->unrm = true;
4285    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4286    mimg->disable_wqm = true;
4287    mimg->barrier = barrier_image;
4288    ctx->program->needs_exact = true;
4289    ctx->block->instructions.emplace_back(std::move(mimg));
4290    return;
4291 }
4292
4293 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4294 {
4295    if (in_elements && ctx->options->chip_class == GFX8) {
4296       Builder bld(ctx->program, ctx->block);
4297
4298       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4299       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4300       stride = bld.vop1(aco_opcode::v_cvt_f32_ubyte0, bld.def(v1), stride);
4301       stride = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), stride);
4302
4303       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4304       size = bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), size);
4305
4306       Temp res = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), size, stride);
4307       res = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), res);
4308       bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
4309
4310       // TODO: we can probably calculate this faster on the scalar unit to do: size / stride{1,2,4,8,12,16}
4311       /* idea
4312        * for 1,2,4,8,16, the result is just (stride >> S_FF1_I32_B32)
4313        * in case 12 (or 3?), we have to divide by 3:
4314        * set v_skip in case it's 12 (if we also have to take care of 3, shift first)
4315        * use v_mul_hi_u32 with magic number to divide
4316        * we need some pseudo merge opcode to overwrite the original SALU result with readfirstlane
4317        * disable v_skip
4318        * total: 6 SALU + 2 VALU instructions vs 1 SALU + 6 VALU instructions
4319        */
4320
4321    } else {
4322       emit_extract_vector(ctx, desc, 2, dst);
4323    }
4324 }
4325
4326 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4327 {
4328    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4329    const struct glsl_type *type = glsl_without_array(var->type);
4330    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4331    bool is_array = glsl_sampler_type_is_array(type);
4332    Builder bld(ctx->program, ctx->block);
4333
4334    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4335       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4336       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4337    }
4338
4339    /* LOD */
4340    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4341
4342    /* Resource */
4343    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4344
4345    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4346
4347    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1)};
4348    mimg->operands[0] = Operand(lod);
4349    mimg->operands[1] = Operand(resource);
4350    unsigned& dmask = mimg->dmask;
4351    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4352    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4353    mimg->da = glsl_sampler_type_is_array(type);
4354    mimg->can_reorder = true;
4355    Definition& def = mimg->definitions[0];
4356    ctx->block->instructions.emplace_back(std::move(mimg));
4357
4358    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4359        glsl_sampler_type_is_array(type)) {
4360
4361       assert(instr->dest.ssa.num_components == 3);
4362       Temp tmp = {ctx->program->allocateId(), v3};
4363       def = Definition(tmp);
4364       emit_split_vector(ctx, tmp, 3);
4365
4366       /* divide 3rd value by 6 by multiplying with magic number */
4367       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4368       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4369
4370       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4371                  emit_extract_vector(ctx, tmp, 0, v1),
4372                  emit_extract_vector(ctx, tmp, 1, v1),
4373                  by_6);
4374
4375    } else if (ctx->options->chip_class == GFX9 &&
4376               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4377               glsl_sampler_type_is_array(type)) {
4378       assert(instr->dest.ssa.num_components == 2);
4379       def = Definition(dst);
4380       dmask = 0x5;
4381    } else {
4382       def = Definition(dst);
4383    }
4384
4385    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4386 }
4387
4388 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4389 {
4390    Builder bld(ctx->program, ctx->block);
4391    unsigned num_components = instr->num_components;
4392
4393    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4394    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4395    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4396
4397    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4398    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4399 }
4400
4401 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4402 {
4403    Builder bld(ctx->program, ctx->block);
4404    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4405    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4406    unsigned writemask = nir_intrinsic_write_mask(instr);
4407
4408    Temp offset;
4409    if (ctx->options->chip_class < GFX8)
4410       offset = as_vgpr(ctx,get_ssa_temp(ctx, instr->src[2].ssa));
4411    else
4412       offset = get_ssa_temp(ctx, instr->src[2].ssa);
4413
4414    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4415    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4416
4417    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4418                ctx->options->chip_class >= GFX8;
4419    if (smem)
4420       offset = bld.as_uniform(offset);
4421    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4422
4423    while (writemask) {
4424       int start, count;
4425       u_bit_scan_consecutive_range(&writemask, &start, &count);
4426       if (count == 3 && smem) {
4427          writemask |= 1u << (start + 2);
4428          count = 2;
4429       }
4430       int num_bytes = count * elem_size_bytes;
4431
4432       if (num_bytes > 16) {
4433          assert(elem_size_bytes == 8);
4434          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4435          count = 2;
4436          num_bytes = 16;
4437       }
4438
4439       // TODO: check alignment of sub-dword stores
4440       // TODO: split 3 bytes. there is no store instruction for that
4441
4442       Temp write_data;
4443       if (count != instr->num_components) {
4444          emit_split_vector(ctx, data, instr->num_components);
4445          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4446          for (int i = 0; i < count; i++) {
4447             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4448             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4449          }
4450          write_data = bld.tmp(smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4451          vec->definitions[0] = Definition(write_data);
4452          ctx->block->instructions.emplace_back(std::move(vec));
4453       } else if (!smem && data.type() != RegType::vgpr) {
4454          assert(num_bytes % 4 == 0);
4455          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4456       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4457          assert(num_bytes % 4 == 0);
4458          write_data = bld.as_uniform(data);
4459       } else {
4460          write_data = data;
4461       }
4462
4463       aco_opcode vmem_op, smem_op;
4464       switch (num_bytes) {
4465          case 4:
4466             vmem_op = aco_opcode::buffer_store_dword;
4467             smem_op = aco_opcode::s_buffer_store_dword;
4468             break;
4469          case 8:
4470             vmem_op = aco_opcode::buffer_store_dwordx2;
4471             smem_op = aco_opcode::s_buffer_store_dwordx2;
4472             break;
4473          case 12:
4474             vmem_op = aco_opcode::buffer_store_dwordx3;
4475             smem_op = aco_opcode::last_opcode;
4476             assert(!smem);
4477             break;
4478          case 16:
4479             vmem_op = aco_opcode::buffer_store_dwordx4;
4480             smem_op = aco_opcode::s_buffer_store_dwordx4;
4481             break;
4482          default:
4483             unreachable("Store SSBO not implemented for this size.");
4484       }
4485       if (ctx->stage == fragment_fs)
4486          smem_op = aco_opcode::p_fs_buffer_store_smem;
4487
4488       if (smem) {
4489          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4490          store->operands[0] = Operand(rsrc);
4491          if (start) {
4492             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4493                                 offset, Operand(start * elem_size_bytes));
4494             store->operands[1] = Operand(off);
4495          } else {
4496             store->operands[1] = Operand(offset);
4497          }
4498          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4499             store->operands[1].setFixed(m0);
4500          store->operands[2] = Operand(write_data);
4501          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4502          store->dlc = false;
4503          store->disable_wqm = true;
4504          store->barrier = barrier_buffer;
4505          ctx->block->instructions.emplace_back(std::move(store));
4506          ctx->program->wb_smem_l1_on_end = true;
4507          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4508             ctx->block->kind |= block_kind_needs_lowering;
4509             ctx->program->needs_exact = true;
4510          }
4511       } else {
4512          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4513          store->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4514          store->operands[1] = Operand(rsrc);
4515          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4516          store->operands[3] = Operand(write_data);
4517          store->offset = start * elem_size_bytes;
4518          store->offen = (offset.type() == RegType::vgpr);
4519          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4520          store->dlc = false;
4521          store->disable_wqm = true;
4522          store->barrier = barrier_buffer;
4523          ctx->program->needs_exact = true;
4524          ctx->block->instructions.emplace_back(std::move(store));
4525       }
4526    }
4527 }
4528
4529 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4530 {
4531    /* return the previous value if dest is ever used */
4532    bool return_previous = false;
4533    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4534       return_previous = true;
4535       break;
4536    }
4537    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4538       return_previous = true;
4539       break;
4540    }
4541
4542    Builder bld(ctx->program, ctx->block);
4543    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4544
4545    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4546       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4547                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4548
4549    Temp offset;
4550    if (ctx->options->chip_class < GFX8)
4551       offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4552    else
4553       offset = get_ssa_temp(ctx, instr->src[1].ssa);
4554
4555    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4556    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4557
4558    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4559
4560    aco_opcode op32, op64;
4561    switch (instr->intrinsic) {
4562       case nir_intrinsic_ssbo_atomic_add:
4563          op32 = aco_opcode::buffer_atomic_add;
4564          op64 = aco_opcode::buffer_atomic_add_x2;
4565          break;
4566       case nir_intrinsic_ssbo_atomic_imin:
4567          op32 = aco_opcode::buffer_atomic_smin;
4568          op64 = aco_opcode::buffer_atomic_smin_x2;
4569          break;
4570       case nir_intrinsic_ssbo_atomic_umin:
4571          op32 = aco_opcode::buffer_atomic_umin;
4572          op64 = aco_opcode::buffer_atomic_umin_x2;
4573          break;
4574       case nir_intrinsic_ssbo_atomic_imax:
4575          op32 = aco_opcode::buffer_atomic_smax;
4576          op64 = aco_opcode::buffer_atomic_smax_x2;
4577          break;
4578       case nir_intrinsic_ssbo_atomic_umax:
4579          op32 = aco_opcode::buffer_atomic_umax;
4580          op64 = aco_opcode::buffer_atomic_umax_x2;
4581          break;
4582       case nir_intrinsic_ssbo_atomic_and:
4583          op32 = aco_opcode::buffer_atomic_and;
4584          op64 = aco_opcode::buffer_atomic_and_x2;
4585          break;
4586       case nir_intrinsic_ssbo_atomic_or:
4587          op32 = aco_opcode::buffer_atomic_or;
4588          op64 = aco_opcode::buffer_atomic_or_x2;
4589          break;
4590       case nir_intrinsic_ssbo_atomic_xor:
4591          op32 = aco_opcode::buffer_atomic_xor;
4592          op64 = aco_opcode::buffer_atomic_xor_x2;
4593          break;
4594       case nir_intrinsic_ssbo_atomic_exchange:
4595          op32 = aco_opcode::buffer_atomic_swap;
4596          op64 = aco_opcode::buffer_atomic_swap_x2;
4597          break;
4598       case nir_intrinsic_ssbo_atomic_comp_swap:
4599          op32 = aco_opcode::buffer_atomic_cmpswap;
4600          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4601          break;
4602       default:
4603          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4604    }
4605    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4606    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4607    mubuf->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4608    mubuf->operands[1] = Operand(rsrc);
4609    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4610    mubuf->operands[3] = Operand(data);
4611    if (return_previous)
4612       mubuf->definitions[0] = Definition(dst);
4613    mubuf->offset = 0;
4614    mubuf->offen = (offset.type() == RegType::vgpr);
4615    mubuf->glc = return_previous;
4616    mubuf->dlc = false; /* Not needed for atomics */
4617    mubuf->disable_wqm = true;
4618    mubuf->barrier = barrier_buffer;
4619    ctx->program->needs_exact = true;
4620    ctx->block->instructions.emplace_back(std::move(mubuf));
4621 }
4622
4623 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4624
4625    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4626    Builder bld(ctx->program, ctx->block);
4627    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4628    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4629 }
4630
4631 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4632 {
4633    Builder bld(ctx->program, ctx->block);
4634    unsigned num_components = instr->num_components;
4635    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4636
4637    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4638    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4639
4640    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4641    bool dlc = glc && ctx->options->chip_class >= GFX10;
4642    aco_opcode op;
4643    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4644       bool global = ctx->options->chip_class >= GFX9;
4645       aco_opcode op;
4646       switch (num_bytes) {
4647       case 4:
4648          op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4649          break;
4650       case 8:
4651          op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4652          break;
4653       case 12:
4654          op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4655          break;
4656       case 16:
4657          op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
4658          break;
4659       default:
4660          unreachable("load_global not implemented for this size.");
4661       }
4662       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
4663       flat->operands[0] = Operand(addr);
4664       flat->operands[1] = Operand(s1);
4665       flat->glc = glc;
4666       flat->dlc = dlc;
4667       flat->barrier = barrier_buffer;
4668
4669       if (dst.type() == RegType::sgpr) {
4670          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4671          flat->definitions[0] = Definition(vec);
4672          ctx->block->instructions.emplace_back(std::move(flat));
4673          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
4674       } else {
4675          flat->definitions[0] = Definition(dst);
4676          ctx->block->instructions.emplace_back(std::move(flat));
4677       }
4678       emit_split_vector(ctx, dst, num_components);
4679    } else {
4680       switch (num_bytes) {
4681          case 4:
4682             op = aco_opcode::s_load_dword;
4683             break;
4684          case 8:
4685             op = aco_opcode::s_load_dwordx2;
4686             break;
4687          case 12:
4688          case 16:
4689             op = aco_opcode::s_load_dwordx4;
4690             break;
4691          default:
4692             unreachable("load_global not implemented for this size.");
4693       }
4694       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4695       load->operands[0] = Operand(addr);
4696       load->operands[1] = Operand(0u);
4697       load->definitions[0] = Definition(dst);
4698       load->glc = glc;
4699       load->dlc = dlc;
4700       load->barrier = barrier_buffer;
4701       assert(ctx->options->chip_class >= GFX8 || !glc);
4702
4703       if (dst.size() == 3) {
4704          /* trim vector */
4705          Temp vec = bld.tmp(s4);
4706          load->definitions[0] = Definition(vec);
4707          ctx->block->instructions.emplace_back(std::move(load));
4708          emit_split_vector(ctx, vec, 4);
4709
4710          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4711                     emit_extract_vector(ctx, vec, 0, s1),
4712                     emit_extract_vector(ctx, vec, 1, s1),
4713                     emit_extract_vector(ctx, vec, 2, s1));
4714       } else {
4715          ctx->block->instructions.emplace_back(std::move(load));
4716       }
4717    }
4718 }
4719
4720 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
4721 {
4722    Builder bld(ctx->program, ctx->block);
4723    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4724
4725    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4726    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4727
4728    unsigned writemask = nir_intrinsic_write_mask(instr);
4729    while (writemask) {
4730       int start, count;
4731       u_bit_scan_consecutive_range(&writemask, &start, &count);
4732       unsigned num_bytes = count * elem_size_bytes;
4733
4734       Temp write_data = data;
4735       if (count != instr->num_components) {
4736          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4737          for (int i = 0; i < count; i++)
4738             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
4739          write_data = bld.tmp(RegType::vgpr, count);
4740          vec->definitions[0] = Definition(write_data);
4741          ctx->block->instructions.emplace_back(std::move(vec));
4742       }
4743
4744       unsigned offset = start * elem_size_bytes;
4745       if (offset > 0 && ctx->options->chip_class < GFX9) {
4746          Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
4747          Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
4748          Temp carry = bld.tmp(bld.lm);
4749          bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
4750
4751          bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
4752                   Operand(offset), addr0);
4753          bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
4754                   Operand(0u), addr1,
4755                   carry).def(1).setHint(vcc);
4756
4757          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
4758
4759          offset = 0;
4760       }
4761
4762       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4763       bool global = ctx->options->chip_class >= GFX9;
4764       aco_opcode op;
4765       switch (num_bytes) {
4766       case 4:
4767          op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
4768          break;
4769       case 8:
4770          op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
4771          break;
4772       case 12:
4773          op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
4774          break;
4775       case 16:
4776          op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
4777          break;
4778       default:
4779          unreachable("store_global not implemented for this size.");
4780       }
4781       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
4782       flat->operands[0] = Operand(addr);
4783       flat->operands[1] = Operand(s1);
4784       flat->operands[2] = Operand(data);
4785       flat->glc = glc;
4786       flat->dlc = false;
4787       flat->offset = offset;
4788       flat->disable_wqm = true;
4789       flat->barrier = barrier_buffer;
4790       ctx->program->needs_exact = true;
4791       ctx->block->instructions.emplace_back(std::move(flat));
4792    }
4793 }
4794
4795 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4796 {
4797    /* return the previous value if dest is ever used */
4798    bool return_previous = false;
4799    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4800       return_previous = true;
4801       break;
4802    }
4803    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4804       return_previous = true;
4805       break;
4806    }
4807
4808    Builder bld(ctx->program, ctx->block);
4809    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4810    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4811
4812    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
4813       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4814                         get_ssa_temp(ctx, instr->src[2].ssa), data);
4815
4816    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4817
4818    bool global = ctx->options->chip_class >= GFX9;
4819    aco_opcode op32, op64;
4820    switch (instr->intrinsic) {
4821       case nir_intrinsic_global_atomic_add:
4822          op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
4823          op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
4824          break;
4825       case nir_intrinsic_global_atomic_imin:
4826          op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
4827          op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
4828          break;
4829       case nir_intrinsic_global_atomic_umin:
4830          op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
4831          op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
4832          break;
4833       case nir_intrinsic_global_atomic_imax:
4834          op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
4835          op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
4836          break;
4837       case nir_intrinsic_global_atomic_umax:
4838          op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
4839          op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
4840          break;
4841       case nir_intrinsic_global_atomic_and:
4842          op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
4843          op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
4844          break;
4845       case nir_intrinsic_global_atomic_or:
4846          op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
4847          op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
4848          break;
4849       case nir_intrinsic_global_atomic_xor:
4850          op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
4851          op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
4852          break;
4853       case nir_intrinsic_global_atomic_exchange:
4854          op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
4855          op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
4856          break;
4857       case nir_intrinsic_global_atomic_comp_swap:
4858          op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
4859          op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
4860          break;
4861       default:
4862          unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
4863    }
4864    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4865    aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
4866    flat->operands[0] = Operand(addr);
4867    flat->operands[1] = Operand(s1);
4868    flat->operands[2] = Operand(data);
4869    if (return_previous)
4870       flat->definitions[0] = Definition(dst);
4871    flat->glc = return_previous;
4872    flat->dlc = false; /* Not needed for atomics */
4873    flat->offset = 0;
4874    flat->disable_wqm = true;
4875    flat->barrier = barrier_buffer;
4876    ctx->program->needs_exact = true;
4877    ctx->block->instructions.emplace_back(std::move(flat));
4878 }
4879
4880 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
4881    Builder bld(ctx->program, ctx->block);
4882    switch(instr->intrinsic) {
4883       case nir_intrinsic_group_memory_barrier:
4884       case nir_intrinsic_memory_barrier:
4885          bld.barrier(aco_opcode::p_memory_barrier_all);
4886          break;
4887       case nir_intrinsic_memory_barrier_atomic_counter:
4888          bld.barrier(aco_opcode::p_memory_barrier_atomic);
4889          break;
4890       case nir_intrinsic_memory_barrier_buffer:
4891          bld.barrier(aco_opcode::p_memory_barrier_buffer);
4892          break;
4893       case nir_intrinsic_memory_barrier_image:
4894          bld.barrier(aco_opcode::p_memory_barrier_image);
4895          break;
4896       case nir_intrinsic_memory_barrier_shared:
4897          bld.barrier(aco_opcode::p_memory_barrier_shared);
4898          break;
4899       default:
4900          unreachable("Unimplemented memory barrier intrinsic");
4901          break;
4902    }
4903 }
4904
4905 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4906 {
4907    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4908    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4909    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
4910    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4911    Builder bld(ctx->program, ctx->block);
4912
4913    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
4914    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4915    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
4916 }
4917
4918 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4919 {
4920    unsigned writemask = nir_intrinsic_write_mask(instr);
4921    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4922    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4923    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4924    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
4925
4926    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4927    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
4928 }
4929
4930 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4931 {
4932    unsigned offset = nir_intrinsic_base(instr);
4933    Operand m = load_lds_size_m0(ctx);
4934    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4935    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4936
4937    unsigned num_operands = 3;
4938    aco_opcode op32, op64, op32_rtn, op64_rtn;
4939    switch(instr->intrinsic) {
4940       case nir_intrinsic_shared_atomic_add:
4941          op32 = aco_opcode::ds_add_u32;
4942          op64 = aco_opcode::ds_add_u64;
4943          op32_rtn = aco_opcode::ds_add_rtn_u32;
4944          op64_rtn = aco_opcode::ds_add_rtn_u64;
4945          break;
4946       case nir_intrinsic_shared_atomic_imin:
4947          op32 = aco_opcode::ds_min_i32;
4948          op64 = aco_opcode::ds_min_i64;
4949          op32_rtn = aco_opcode::ds_min_rtn_i32;
4950          op64_rtn = aco_opcode::ds_min_rtn_i64;
4951          break;
4952       case nir_intrinsic_shared_atomic_umin:
4953          op32 = aco_opcode::ds_min_u32;
4954          op64 = aco_opcode::ds_min_u64;
4955          op32_rtn = aco_opcode::ds_min_rtn_u32;
4956          op64_rtn = aco_opcode::ds_min_rtn_u64;
4957          break;
4958       case nir_intrinsic_shared_atomic_imax:
4959          op32 = aco_opcode::ds_max_i32;
4960          op64 = aco_opcode::ds_max_i64;
4961          op32_rtn = aco_opcode::ds_max_rtn_i32;
4962          op64_rtn = aco_opcode::ds_max_rtn_i64;
4963          break;
4964       case nir_intrinsic_shared_atomic_umax:
4965          op32 = aco_opcode::ds_max_u32;
4966          op64 = aco_opcode::ds_max_u64;
4967          op32_rtn = aco_opcode::ds_max_rtn_u32;
4968          op64_rtn = aco_opcode::ds_max_rtn_u64;
4969          break;
4970       case nir_intrinsic_shared_atomic_and:
4971          op32 = aco_opcode::ds_and_b32;
4972          op64 = aco_opcode::ds_and_b64;
4973          op32_rtn = aco_opcode::ds_and_rtn_b32;
4974          op64_rtn = aco_opcode::ds_and_rtn_b64;
4975          break;
4976       case nir_intrinsic_shared_atomic_or:
4977          op32 = aco_opcode::ds_or_b32;
4978          op64 = aco_opcode::ds_or_b64;
4979          op32_rtn = aco_opcode::ds_or_rtn_b32;
4980          op64_rtn = aco_opcode::ds_or_rtn_b64;
4981          break;
4982       case nir_intrinsic_shared_atomic_xor:
4983          op32 = aco_opcode::ds_xor_b32;
4984          op64 = aco_opcode::ds_xor_b64;
4985          op32_rtn = aco_opcode::ds_xor_rtn_b32;
4986          op64_rtn = aco_opcode::ds_xor_rtn_b64;
4987          break;
4988       case nir_intrinsic_shared_atomic_exchange:
4989          op32 = aco_opcode::ds_write_b32;
4990          op64 = aco_opcode::ds_write_b64;
4991          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
4992          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
4993          break;
4994       case nir_intrinsic_shared_atomic_comp_swap:
4995          op32 = aco_opcode::ds_cmpst_b32;
4996          op64 = aco_opcode::ds_cmpst_b64;
4997          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
4998          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
4999          num_operands = 4;
5000          break;
5001       default:
5002          unreachable("Unhandled shared atomic intrinsic");
5003    }
5004
5005    /* return the previous value if dest is ever used */
5006    bool return_previous = false;
5007    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5008       return_previous = true;
5009       break;
5010    }
5011    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5012       return_previous = true;
5013       break;
5014    }
5015
5016    aco_opcode op;
5017    if (data.size() == 1) {
5018       assert(instr->dest.ssa.bit_size == 32);
5019       op = return_previous ? op32_rtn : op32;
5020    } else {
5021       assert(instr->dest.ssa.bit_size == 64);
5022       op = return_previous ? op64_rtn : op64;
5023    }
5024
5025    if (offset > 65535) {
5026       Builder bld(ctx->program, ctx->block);
5027       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5028       offset = 0;
5029    }
5030
5031    aco_ptr<DS_instruction> ds;
5032    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5033    ds->operands[0] = Operand(address);
5034    ds->operands[1] = Operand(data);
5035    if (num_operands == 4)
5036       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5037    ds->operands[num_operands - 1] = m;
5038    ds->offset0 = offset;
5039    if (return_previous)
5040       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5041    ctx->block->instructions.emplace_back(std::move(ds));
5042 }
5043
5044 Temp get_scratch_resource(isel_context *ctx)
5045 {
5046    Builder bld(ctx->program, ctx->block);
5047    Temp scratch_addr = ctx->program->private_segment_buffer;
5048    if (ctx->stage != compute_cs)
5049       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5050
5051    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5052                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5053
5054    if (ctx->program->chip_class >= GFX10) {
5055       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5056                    S_008F0C_OOB_SELECT(3) |
5057                    S_008F0C_RESOURCE_LEVEL(1);
5058    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5059       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5060                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5061    }
5062
5063    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5064    if (ctx->program->chip_class <= GFX8)
5065       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5066
5067    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5068 }
5069
5070 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5071    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5072    Builder bld(ctx->program, ctx->block);
5073    Temp rsrc = get_scratch_resource(ctx);
5074    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5075    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5076
5077    aco_opcode op;
5078    switch (dst.size()) {
5079       case 1:
5080          op = aco_opcode::buffer_load_dword;
5081          break;
5082       case 2:
5083          op = aco_opcode::buffer_load_dwordx2;
5084          break;
5085       case 3:
5086          op = aco_opcode::buffer_load_dwordx3;
5087          break;
5088       case 4:
5089          op = aco_opcode::buffer_load_dwordx4;
5090          break;
5091       case 6:
5092       case 8: {
5093          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5094          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5095                                 bld.def(v4), offset, rsrc,
5096                                 ctx->program->scratch_offset, 0, true);
5097          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5098                                                   aco_opcode::buffer_load_dwordx4,
5099                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5100                                 offset, rsrc, ctx->program->scratch_offset, 16, true);
5101          emit_split_vector(ctx, lower, 2);
5102          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5103          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5104          if (dst.size() == 8) {
5105             emit_split_vector(ctx, upper, 2);
5106             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5107             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5108          } else {
5109             elems[2] = upper;
5110          }
5111
5112          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5113                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5114          for (unsigned i = 0; i < dst.size() / 2; i++)
5115             vec->operands[i] = Operand(elems[i]);
5116          vec->definitions[0] = Definition(dst);
5117          bld.insert(std::move(vec));
5118          ctx->allocated_vec.emplace(dst.id(), elems);
5119          return;
5120       }
5121       default:
5122          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5123    }
5124
5125    bld.mubuf(op, Definition(dst), offset, rsrc, ctx->program->scratch_offset, 0, true);
5126    emit_split_vector(ctx, dst, instr->num_components);
5127 }
5128
5129 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5130    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5131    Builder bld(ctx->program, ctx->block);
5132    Temp rsrc = get_scratch_resource(ctx);
5133    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5134    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5135
5136    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5137    unsigned writemask = nir_intrinsic_write_mask(instr);
5138
5139    while (writemask) {
5140       int start, count;
5141       u_bit_scan_consecutive_range(&writemask, &start, &count);
5142       int num_bytes = count * elem_size_bytes;
5143
5144       if (num_bytes > 16) {
5145          assert(elem_size_bytes == 8);
5146          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5147          count = 2;
5148          num_bytes = 16;
5149       }
5150
5151       // TODO: check alignment of sub-dword stores
5152       // TODO: split 3 bytes. there is no store instruction for that
5153
5154       Temp write_data;
5155       if (count != instr->num_components) {
5156          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5157          for (int i = 0; i < count; i++) {
5158             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5159             vec->operands[i] = Operand(elem);
5160          }
5161          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5162          vec->definitions[0] = Definition(write_data);
5163          ctx->block->instructions.emplace_back(std::move(vec));
5164       } else {
5165          write_data = data;
5166       }
5167
5168       aco_opcode op;
5169       switch (num_bytes) {
5170          case 4:
5171             op = aco_opcode::buffer_store_dword;
5172             break;
5173          case 8:
5174             op = aco_opcode::buffer_store_dwordx2;
5175             break;
5176          case 12:
5177             op = aco_opcode::buffer_store_dwordx3;
5178             break;
5179          case 16:
5180             op = aco_opcode::buffer_store_dwordx4;
5181             break;
5182          default:
5183             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5184       }
5185
5186       bld.mubuf(op, offset, rsrc, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5187    }
5188 }
5189
5190 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5191    uint8_t log2_ps_iter_samples;
5192    if (ctx->program->info->ps.force_persample) {
5193       log2_ps_iter_samples =
5194          util_logbase2(ctx->options->key.fs.num_samples);
5195    } else {
5196       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5197    }
5198
5199    /* The bit pattern matches that used by fixed function fragment
5200     * processing. */
5201    static const unsigned ps_iter_masks[] = {
5202       0xffff, /* not used */
5203       0x5555,
5204       0x1111,
5205       0x0101,
5206       0x0001,
5207    };
5208    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5209
5210    Builder bld(ctx->program, ctx->block);
5211
5212    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5213                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5214    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5215    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5216    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5217    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5218 }
5219
5220 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5221 {
5222    Builder bld(ctx->program, ctx->block);
5223
5224    if (cluster_size == 1) {
5225       return src;
5226    } if (op == nir_op_iand && cluster_size == 4) {
5227       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5228       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5229       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
5230                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
5231    } else if (op == nir_op_ior && cluster_size == 4) {
5232       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5233       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
5234                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
5235    } else if (op == nir_op_iand && cluster_size == 64) {
5236       //subgroupAnd(val) -> (exec & ~val) == 0
5237       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5238       return bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5239    } else if (op == nir_op_ior && cluster_size == 64) {
5240       //subgroupOr(val) -> (val & exec) != 0
5241       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
5242       return bool_to_vector_condition(ctx, tmp);
5243    } else if (op == nir_op_ixor && cluster_size == 64) {
5244       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5245       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5246       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
5247       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5248       return bool_to_vector_condition(ctx, tmp);
5249    } else {
5250       //subgroupClustered{And,Or,Xor}(val, n) ->
5251       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
5252       //cluster_offset = ~(n - 1) & lane_id
5253       //cluster_mask = ((1 << n) - 1)
5254       //subgroupClusteredAnd():
5255       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5256       //subgroupClusteredOr():
5257       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5258       //subgroupClusteredXor():
5259       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5260       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
5261       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5262
5263       Temp tmp;
5264       if (op == nir_op_iand)
5265          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5266       else
5267          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5268
5269       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5270       if (ctx->program->wave_size == 64)
5271          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5272       else
5273          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
5274       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5275       if (cluster_mask != 0xffffffff)
5276          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5277
5278       Definition cmp_def = Definition();
5279       if (op == nir_op_iand) {
5280          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
5281       } else if (op == nir_op_ior) {
5282          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5283       } else if (op == nir_op_ixor) {
5284          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5285                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5286          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5287       }
5288       cmp_def.setHint(vcc);
5289       return cmp_def.getTemp();
5290    }
5291 }
5292
5293 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5294 {
5295    Builder bld(ctx->program, ctx->block);
5296
5297    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5298    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5299    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5300    Temp tmp;
5301    if (op == nir_op_iand)
5302       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5303    else
5304       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
5305
5306    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5307    Temp lo = lohi.def(0).getTemp();
5308    Temp hi = lohi.def(1).getTemp();
5309    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
5310
5311    Definition cmp_def = Definition();
5312    if (op == nir_op_iand)
5313       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5314    else if (op == nir_op_ior)
5315       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5316    else if (op == nir_op_ixor)
5317       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
5318                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5319    cmp_def.setHint(vcc);
5320    return cmp_def.getTemp();
5321 }
5322
5323 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5324 {
5325    Builder bld(ctx->program, ctx->block);
5326
5327    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5328    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5329    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5330    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5331    if (op == nir_op_iand)
5332       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5333    else if (op == nir_op_ior)
5334       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5335    else if (op == nir_op_ixor)
5336       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5337
5338    assert(false);
5339    return Temp();
5340 }
5341
5342 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5343 {
5344    Builder bld(ctx->program, ctx->block);
5345    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5346    if (src.regClass().type() == RegType::vgpr) {
5347       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5348    } else if (src.regClass() == s1) {
5349       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5350    } else if (src.regClass() == s2) {
5351       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5352    } else {
5353       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5354       nir_print_instr(&instr->instr, stderr);
5355       fprintf(stderr, "\n");
5356    }
5357 }
5358
5359 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5360 {
5361    Builder bld(ctx->program, ctx->block);
5362    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
5363    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
5364    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
5365
5366    /* Build DD X/Y */
5367    Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_quad_perm(0, 0, 0, 0));
5368    Temp ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(1, 1, 1, 1));
5369    Temp ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(2, 2, 2, 2));
5370    Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_quad_perm(0, 0, 0, 0));
5371    Temp ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(1, 1, 1, 1));
5372    Temp ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(2, 2, 2, 2));
5373
5374    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5375    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
5376    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
5377    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
5378    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
5379    Temp wqm1 = bld.tmp(v1);
5380    emit_wqm(ctx, tmp1, wqm1, true);
5381    Temp wqm2 = bld.tmp(v1);
5382    emit_wqm(ctx, tmp2, wqm2, true);
5383    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
5384    return;
5385 }
5386
5387 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
5388 {
5389    Builder bld(ctx->program, ctx->block);
5390    switch(instr->intrinsic) {
5391    case nir_intrinsic_load_barycentric_sample:
5392    case nir_intrinsic_load_barycentric_pixel:
5393    case nir_intrinsic_load_barycentric_centroid: {
5394       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
5395       Temp bary = Temp(0, s2);
5396       switch (mode) {
5397       case INTERP_MODE_SMOOTH:
5398       case INTERP_MODE_NONE:
5399          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5400             bary = get_arg(ctx, ctx->args->ac.persp_center);
5401          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5402             bary = ctx->persp_centroid;
5403          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5404             bary = get_arg(ctx, ctx->args->ac.persp_sample);
5405          break;
5406       case INTERP_MODE_NOPERSPECTIVE:
5407          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
5408             bary = get_arg(ctx, ctx->args->ac.linear_center);
5409          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
5410             bary = ctx->linear_centroid;
5411          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
5412             bary = get_arg(ctx, ctx->args->ac.linear_sample);
5413          break;
5414       default:
5415          break;
5416       }
5417       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5418       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
5419       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
5420       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5421                  Operand(p1), Operand(p2));
5422       emit_split_vector(ctx, dst, 2);
5423       break;
5424    }
5425    case nir_intrinsic_load_barycentric_at_sample: {
5426       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
5427       switch (ctx->options->key.fs.num_samples) {
5428          case 2: sample_pos_offset += 1 << 3; break;
5429          case 4: sample_pos_offset += 3 << 3; break;
5430          case 8: sample_pos_offset += 7 << 3; break;
5431          default: break;
5432       }
5433       Temp sample_pos;
5434       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5435       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
5436       Temp private_segment_buffer = ctx->program->private_segment_buffer;
5437       if (addr.type() == RegType::sgpr) {
5438          Operand offset;
5439          if (const_addr) {
5440             sample_pos_offset += const_addr->u32 << 3;
5441             offset = Operand(sample_pos_offset);
5442          } else if (ctx->options->chip_class >= GFX9) {
5443             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5444          } else {
5445             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
5446             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5447          }
5448          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand(offset));
5449
5450       } else if (ctx->options->chip_class >= GFX9) {
5451          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5452          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
5453       } else {
5454          /* addr += private_segment_buffer + sample_pos_offset */
5455          Temp tmp0 = bld.tmp(s1);
5456          Temp tmp1 = bld.tmp(s1);
5457          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
5458          Definition scc_tmp = bld.def(s1, scc);
5459          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
5460          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
5461          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5462          Temp pck0 = bld.tmp(v1);
5463          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
5464          tmp1 = as_vgpr(ctx, tmp1);
5465          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
5466          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
5467
5468          /* sample_pos = flat_load_dwordx2 addr */
5469          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
5470       }
5471
5472       /* sample_pos -= 0.5 */
5473       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
5474       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
5475       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
5476       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
5477       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
5478
5479       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5480       break;
5481    }
5482    case nir_intrinsic_load_barycentric_at_offset: {
5483       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
5484       RegClass rc = RegClass(offset.type(), 1);
5485       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
5486       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
5487       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5488       break;
5489    }
5490    case nir_intrinsic_load_front_face: {
5491       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5492                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
5493       break;
5494    }
5495    case nir_intrinsic_load_view_index:
5496    case nir_intrinsic_load_layer_id: {
5497       if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & sw_vs)) {
5498          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5499          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
5500          break;
5501       }
5502
5503       unsigned idx = nir_intrinsic_base(instr);
5504       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5505                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
5506       break;
5507    }
5508    case nir_intrinsic_load_frag_coord: {
5509       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
5510       break;
5511    }
5512    case nir_intrinsic_load_sample_pos: {
5513       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
5514       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
5515       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5516                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
5517                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
5518       break;
5519    }
5520    case nir_intrinsic_load_interpolated_input:
5521       visit_load_interpolated_input(ctx, instr);
5522       break;
5523    case nir_intrinsic_store_output:
5524       visit_store_output(ctx, instr);
5525       break;
5526    case nir_intrinsic_load_input:
5527       visit_load_input(ctx, instr);
5528       break;
5529    case nir_intrinsic_load_ubo:
5530       visit_load_ubo(ctx, instr);
5531       break;
5532    case nir_intrinsic_load_push_constant:
5533       visit_load_push_constant(ctx, instr);
5534       break;
5535    case nir_intrinsic_load_constant:
5536       visit_load_constant(ctx, instr);
5537       break;
5538    case nir_intrinsic_vulkan_resource_index:
5539       visit_load_resource(ctx, instr);
5540       break;
5541    case nir_intrinsic_discard:
5542       visit_discard(ctx, instr);
5543       break;
5544    case nir_intrinsic_discard_if:
5545       visit_discard_if(ctx, instr);
5546       break;
5547    case nir_intrinsic_load_shared:
5548       visit_load_shared(ctx, instr);
5549       break;
5550    case nir_intrinsic_store_shared:
5551       visit_store_shared(ctx, instr);
5552       break;
5553    case nir_intrinsic_shared_atomic_add:
5554    case nir_intrinsic_shared_atomic_imin:
5555    case nir_intrinsic_shared_atomic_umin:
5556    case nir_intrinsic_shared_atomic_imax:
5557    case nir_intrinsic_shared_atomic_umax:
5558    case nir_intrinsic_shared_atomic_and:
5559    case nir_intrinsic_shared_atomic_or:
5560    case nir_intrinsic_shared_atomic_xor:
5561    case nir_intrinsic_shared_atomic_exchange:
5562    case nir_intrinsic_shared_atomic_comp_swap:
5563       visit_shared_atomic(ctx, instr);
5564       break;
5565    case nir_intrinsic_image_deref_load:
5566       visit_image_load(ctx, instr);
5567       break;
5568    case nir_intrinsic_image_deref_store:
5569       visit_image_store(ctx, instr);
5570       break;
5571    case nir_intrinsic_image_deref_atomic_add:
5572    case nir_intrinsic_image_deref_atomic_umin:
5573    case nir_intrinsic_image_deref_atomic_imin:
5574    case nir_intrinsic_image_deref_atomic_umax:
5575    case nir_intrinsic_image_deref_atomic_imax:
5576    case nir_intrinsic_image_deref_atomic_and:
5577    case nir_intrinsic_image_deref_atomic_or:
5578    case nir_intrinsic_image_deref_atomic_xor:
5579    case nir_intrinsic_image_deref_atomic_exchange:
5580    case nir_intrinsic_image_deref_atomic_comp_swap:
5581       visit_image_atomic(ctx, instr);
5582       break;
5583    case nir_intrinsic_image_deref_size:
5584       visit_image_size(ctx, instr);
5585       break;
5586    case nir_intrinsic_load_ssbo:
5587       visit_load_ssbo(ctx, instr);
5588       break;
5589    case nir_intrinsic_store_ssbo:
5590       visit_store_ssbo(ctx, instr);
5591       break;
5592    case nir_intrinsic_load_global:
5593       visit_load_global(ctx, instr);
5594       break;
5595    case nir_intrinsic_store_global:
5596       visit_store_global(ctx, instr);
5597       break;
5598    case nir_intrinsic_global_atomic_add:
5599    case nir_intrinsic_global_atomic_imin:
5600    case nir_intrinsic_global_atomic_umin:
5601    case nir_intrinsic_global_atomic_imax:
5602    case nir_intrinsic_global_atomic_umax:
5603    case nir_intrinsic_global_atomic_and:
5604    case nir_intrinsic_global_atomic_or:
5605    case nir_intrinsic_global_atomic_xor:
5606    case nir_intrinsic_global_atomic_exchange:
5607    case nir_intrinsic_global_atomic_comp_swap:
5608       visit_global_atomic(ctx, instr);
5609       break;
5610    case nir_intrinsic_ssbo_atomic_add:
5611    case nir_intrinsic_ssbo_atomic_imin:
5612    case nir_intrinsic_ssbo_atomic_umin:
5613    case nir_intrinsic_ssbo_atomic_imax:
5614    case nir_intrinsic_ssbo_atomic_umax:
5615    case nir_intrinsic_ssbo_atomic_and:
5616    case nir_intrinsic_ssbo_atomic_or:
5617    case nir_intrinsic_ssbo_atomic_xor:
5618    case nir_intrinsic_ssbo_atomic_exchange:
5619    case nir_intrinsic_ssbo_atomic_comp_swap:
5620       visit_atomic_ssbo(ctx, instr);
5621       break;
5622    case nir_intrinsic_load_scratch:
5623       visit_load_scratch(ctx, instr);
5624       break;
5625    case nir_intrinsic_store_scratch:
5626       visit_store_scratch(ctx, instr);
5627       break;
5628    case nir_intrinsic_get_buffer_size:
5629       visit_get_buffer_size(ctx, instr);
5630       break;
5631    case nir_intrinsic_barrier: {
5632       unsigned* bsize = ctx->program->info->cs.block_size;
5633       unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
5634       if (workgroup_size > ctx->program->wave_size)
5635          bld.sopp(aco_opcode::s_barrier);
5636       break;
5637    }
5638    case nir_intrinsic_group_memory_barrier:
5639    case nir_intrinsic_memory_barrier:
5640    case nir_intrinsic_memory_barrier_atomic_counter:
5641    case nir_intrinsic_memory_barrier_buffer:
5642    case nir_intrinsic_memory_barrier_image:
5643    case nir_intrinsic_memory_barrier_shared:
5644       emit_memory_barrier(ctx, instr);
5645       break;
5646    case nir_intrinsic_load_num_work_groups: {
5647       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5648       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
5649       emit_split_vector(ctx, dst, 3);
5650       break;
5651    }
5652    case nir_intrinsic_load_local_invocation_id: {
5653       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5654       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
5655       emit_split_vector(ctx, dst, 3);
5656       break;
5657    }
5658    case nir_intrinsic_load_work_group_id: {
5659       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5660       struct ac_arg *args = ctx->args->ac.workgroup_ids;
5661       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5662                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
5663                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
5664                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
5665       emit_split_vector(ctx, dst, 3);
5666       break;
5667    }
5668    case nir_intrinsic_load_local_invocation_index: {
5669       Temp id = emit_mbcnt(ctx, bld.def(v1));
5670
5671       /* The tg_size bits [6:11] contain the subgroup id,
5672        * we need this multiplied by the wave size, and then OR the thread id to it.
5673        */
5674       if (ctx->program->wave_size == 64) {
5675          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
5676          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
5677                                 get_arg(ctx, ctx->args->ac.tg_size));
5678          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
5679       } else {
5680          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
5681          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
5682                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5683          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
5684       }
5685       break;
5686    }
5687    case nir_intrinsic_load_subgroup_id: {
5688       if (ctx->stage == compute_cs) {
5689          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
5690                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
5691       } else {
5692          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
5693       }
5694       break;
5695    }
5696    case nir_intrinsic_load_subgroup_invocation: {
5697       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
5698       break;
5699    }
5700    case nir_intrinsic_load_num_subgroups: {
5701       if (ctx->stage == compute_cs)
5702          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
5703                   get_arg(ctx, ctx->args->ac.tg_size));
5704       else
5705          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
5706       break;
5707    }
5708    case nir_intrinsic_ballot: {
5709       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5710       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5711       Definition tmp = bld.def(dst.regClass());
5712       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
5713       if (instr->src[0].ssa->bit_size == 1) {
5714          assert(src.regClass() == bld.lm);
5715          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
5716       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
5717          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
5718       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
5719          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
5720       } else {
5721          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5722          nir_print_instr(&instr->instr, stderr);
5723          fprintf(stderr, "\n");
5724       }
5725       if (dst.size() != bld.lm.size()) {
5726          /* Wave32 with ballot size set to 64 */
5727          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
5728       }
5729       emit_wqm(ctx, tmp.getTemp(), dst);
5730       break;
5731    }
5732    case nir_intrinsic_shuffle:
5733    case nir_intrinsic_read_invocation: {
5734       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5735       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
5736          emit_uniform_subgroup(ctx, instr, src);
5737       } else {
5738          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
5739          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
5740             tid = bld.as_uniform(tid);
5741          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5742          if (src.regClass() == v1) {
5743             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
5744          } else if (src.regClass() == v2) {
5745             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5746             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5747             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
5748             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
5749             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5750             emit_split_vector(ctx, dst, 2);
5751          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
5752             assert(src.regClass() == bld.lm);
5753             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
5754             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5755          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
5756             assert(src.regClass() == bld.lm);
5757             Temp tmp;
5758             if (ctx->program->wave_size == 64)
5759                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
5760             else
5761                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
5762             tmp = emit_extract_vector(ctx, tmp, 0, v1);
5763             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
5764             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
5765          } else {
5766             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5767             nir_print_instr(&instr->instr, stderr);
5768             fprintf(stderr, "\n");
5769          }
5770       }
5771       break;
5772    }
5773    case nir_intrinsic_load_sample_id: {
5774       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5775                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5776       break;
5777    }
5778    case nir_intrinsic_load_sample_mask_in: {
5779       visit_load_sample_mask_in(ctx, instr);
5780       break;
5781    }
5782    case nir_intrinsic_read_first_invocation: {
5783       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5784       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5785       if (src.regClass() == v1) {
5786          emit_wqm(ctx,
5787                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
5788                   dst);
5789       } else if (src.regClass() == v2) {
5790          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5791          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5792          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
5793          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
5794          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5795          emit_split_vector(ctx, dst, 2);
5796       } else if (instr->dest.ssa.bit_size == 1) {
5797          assert(src.regClass() == bld.lm);
5798          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
5799                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
5800          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5801       } else if (src.regClass() == s1) {
5802          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5803       } else if (src.regClass() == s2) {
5804          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5805       } else {
5806          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5807          nir_print_instr(&instr->instr, stderr);
5808          fprintf(stderr, "\n");
5809       }
5810       break;
5811    }
5812    case nir_intrinsic_vote_all: {
5813       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5814       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5815       assert(src.regClass() == bld.lm);
5816       assert(dst.regClass() == bld.lm);
5817
5818       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5819       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(0u), Operand(-1u), bld.scc(tmp));
5820       emit_wqm(ctx, val, dst);
5821       break;
5822    }
5823    case nir_intrinsic_vote_any: {
5824       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5825       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5826       assert(src.regClass() == bld.lm);
5827       assert(dst.regClass() == bld.lm);
5828
5829       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5830       Temp val = bld.sop2(Builder::s_cselect, bld.def(bld.lm), Operand(-1u), Operand(0u), bld.scc(tmp));
5831       emit_wqm(ctx, val, dst);
5832       break;
5833    }
5834    case nir_intrinsic_reduce:
5835    case nir_intrinsic_inclusive_scan:
5836    case nir_intrinsic_exclusive_scan: {
5837       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5838       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5839       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
5840       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
5841          nir_intrinsic_cluster_size(instr) : 0;
5842       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : 64, 64));
5843
5844       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
5845          emit_uniform_subgroup(ctx, instr, src);
5846       } else if (instr->dest.ssa.bit_size == 1) {
5847          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
5848             op = nir_op_iand;
5849          else if (op == nir_op_iadd)
5850             op = nir_op_ixor;
5851          else if (op == nir_op_umax || op == nir_op_imax)
5852             op = nir_op_ior;
5853          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
5854
5855          switch (instr->intrinsic) {
5856          case nir_intrinsic_reduce:
5857             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
5858             break;
5859          case nir_intrinsic_exclusive_scan:
5860             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
5861             break;
5862          case nir_intrinsic_inclusive_scan:
5863             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
5864             break;
5865          default:
5866             assert(false);
5867          }
5868       } else if (cluster_size == 1) {
5869          bld.copy(Definition(dst), src);
5870       } else {
5871          src = as_vgpr(ctx, src);
5872
5873          ReduceOp reduce_op;
5874          switch (op) {
5875          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5876             CASE(iadd)
5877             CASE(imul)
5878             CASE(fadd)
5879             CASE(fmul)
5880             CASE(imin)
5881             CASE(umin)
5882             CASE(fmin)
5883             CASE(imax)
5884             CASE(umax)
5885             CASE(fmax)
5886             CASE(iand)
5887             CASE(ior)
5888             CASE(ixor)
5889             default:
5890                unreachable("unknown reduction op");
5891          #undef CASE
5892          }
5893
5894          aco_opcode aco_op;
5895          switch (instr->intrinsic) {
5896             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
5897             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
5898             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
5899             default:
5900                unreachable("unknown reduce intrinsic");
5901          }
5902
5903          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
5904          reduce->operands[0] = Operand(src);
5905          // filled in by aco_reduce_assign.cpp, used internally as part of the
5906          // reduce sequence
5907          assert(dst.size() == 1 || dst.size() == 2);
5908          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
5909          reduce->operands[2] = Operand(v1.as_linear());
5910
5911          Temp tmp_dst = bld.tmp(dst.regClass());
5912          reduce->definitions[0] = Definition(tmp_dst);
5913          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
5914          reduce->definitions[2] = Definition();
5915          reduce->definitions[3] = Definition(scc, s1);
5916          reduce->definitions[4] = Definition();
5917          reduce->reduce_op = reduce_op;
5918          reduce->cluster_size = cluster_size;
5919          ctx->block->instructions.emplace_back(std::move(reduce));
5920
5921          emit_wqm(ctx, tmp_dst, dst);
5922       }
5923       break;
5924    }
5925    case nir_intrinsic_quad_broadcast: {
5926       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5927       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5928          emit_uniform_subgroup(ctx, instr, src);
5929       } else {
5930          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5931          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
5932          if (instr->dest.ssa.bit_size == 1) {
5933             assert(src.regClass() == bld.lm);
5934             assert(dst.regClass() == bld.lm);
5935             uint32_t half_mask = 0x11111111u << lane;
5936             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
5937             Temp tmp = bld.tmp(bld.lm);
5938             bld.sop1(Builder::s_wqm, Definition(tmp),
5939                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
5940                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
5941             emit_wqm(ctx, tmp, dst);
5942          } else if (instr->dest.ssa.bit_size == 32) {
5943             emit_wqm(ctx,
5944                      bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src,
5945                                   dpp_quad_perm(lane, lane, lane, lane)),
5946                      dst);
5947          } else if (instr->dest.ssa.bit_size == 64) {
5948             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5949             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5950             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_quad_perm(lane, lane, lane, lane)));
5951             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_quad_perm(lane, lane, lane, lane)));
5952             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5953             emit_split_vector(ctx, dst, 2);
5954          } else {
5955             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5956             nir_print_instr(&instr->instr, stderr);
5957             fprintf(stderr, "\n");
5958          }
5959       }
5960       break;
5961    }
5962    case nir_intrinsic_quad_swap_horizontal:
5963    case nir_intrinsic_quad_swap_vertical:
5964    case nir_intrinsic_quad_swap_diagonal:
5965    case nir_intrinsic_quad_swizzle_amd: {
5966       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5967       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5968          emit_uniform_subgroup(ctx, instr, src);
5969          break;
5970       }
5971       uint16_t dpp_ctrl = 0;
5972       switch (instr->intrinsic) {
5973       case nir_intrinsic_quad_swap_horizontal:
5974          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
5975          break;
5976       case nir_intrinsic_quad_swap_vertical:
5977          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
5978          break;
5979       case nir_intrinsic_quad_swap_diagonal:
5980          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
5981          break;
5982       case nir_intrinsic_quad_swizzle_amd: {
5983          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
5984          break;
5985       }
5986       default:
5987          break;
5988       }
5989
5990       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5991       if (instr->dest.ssa.bit_size == 1) {
5992          assert(src.regClass() == bld.lm);
5993          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
5994          src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5995          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
5996          emit_wqm(ctx, tmp, dst);
5997       } else if (instr->dest.ssa.bit_size == 32) {
5998          Temp tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5999          emit_wqm(ctx, tmp, dst);
6000       } else if (instr->dest.ssa.bit_size == 64) {
6001          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6002          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6003          lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6004          hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6005          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6006          emit_split_vector(ctx, dst, 2);
6007       } else {
6008          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6009          nir_print_instr(&instr->instr, stderr);
6010          fprintf(stderr, "\n");
6011       }
6012       break;
6013    }
6014    case nir_intrinsic_masked_swizzle_amd: {
6015       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6016       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6017          emit_uniform_subgroup(ctx, instr, src);
6018          break;
6019       }
6020       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6021       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6022       if (dst.regClass() == v1) {
6023          emit_wqm(ctx,
6024                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6025                   dst);
6026       } else if (dst.regClass() == v2) {
6027          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6028          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6029          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6030          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6031          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6032          emit_split_vector(ctx, dst, 2);
6033       } else {
6034          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6035          nir_print_instr(&instr->instr, stderr);
6036          fprintf(stderr, "\n");
6037       }
6038       break;
6039    }
6040    case nir_intrinsic_write_invocation_amd: {
6041       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6042       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
6043       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
6044       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6045       if (dst.regClass() == v1) {
6046          /* src2 is ignored for writelane. RA assigns the same reg for dst */
6047          emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val, lane, src), dst);
6048       } else if (dst.regClass() == v2) {
6049          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
6050          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
6051          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
6052          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
6053          Temp lo = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_lo, lane, src_hi));
6054          Temp hi = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_hi, lane, src_hi));
6055          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6056          emit_split_vector(ctx, dst, 2);
6057       } else {
6058          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6059          nir_print_instr(&instr->instr, stderr);
6060          fprintf(stderr, "\n");
6061       }
6062       break;
6063    }
6064    case nir_intrinsic_mbcnt_amd: {
6065       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6066       RegClass rc = RegClass(src.type(), 1);
6067       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
6068       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
6069       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6070       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
6071       emit_wqm(ctx, wqm_tmp, dst);
6072       break;
6073    }
6074    case nir_intrinsic_load_helper_invocation: {
6075       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6076       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
6077       ctx->block->kind |= block_kind_needs_lowering;
6078       ctx->program->needs_exact = true;
6079       break;
6080    }
6081    case nir_intrinsic_is_helper_invocation: {
6082       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6083       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
6084       ctx->block->kind |= block_kind_needs_lowering;
6085       ctx->program->needs_exact = true;
6086       break;
6087    }
6088    case nir_intrinsic_demote:
6089       bld.pseudo(aco_opcode::p_demote_to_helper);
6090       ctx->block->kind |= block_kind_uses_demote;
6091       ctx->program->needs_exact = true;
6092       break;
6093    case nir_intrinsic_demote_if: {
6094       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6095       assert(src.regClass() == bld.lm);
6096       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6097       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
6098       ctx->block->kind |= block_kind_uses_demote;
6099       ctx->program->needs_exact = true;
6100       break;
6101    }
6102    case nir_intrinsic_first_invocation: {
6103       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
6104                get_ssa_temp(ctx, &instr->dest.ssa));
6105       break;
6106    }
6107    case nir_intrinsic_shader_clock:
6108       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
6109       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
6110       break;
6111    case nir_intrinsic_load_vertex_id_zero_base: {
6112       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6113       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
6114       break;
6115    }
6116    case nir_intrinsic_load_first_vertex: {
6117       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6118       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
6119       break;
6120    }
6121    case nir_intrinsic_load_base_instance: {
6122       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6123       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
6124       break;
6125    }
6126    case nir_intrinsic_load_instance_id: {
6127       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6128       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
6129       break;
6130    }
6131    case nir_intrinsic_load_draw_id: {
6132       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6133       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
6134       break;
6135    }
6136    default:
6137       fprintf(stderr, "Unimplemented intrinsic instr: ");
6138       nir_print_instr(&instr->instr, stderr);
6139       fprintf(stderr, "\n");
6140       abort();
6141
6142       break;
6143    }
6144 }
6145
6146
6147 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
6148                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
6149                     enum glsl_base_type *stype)
6150 {
6151    nir_deref_instr *texture_deref_instr = NULL;
6152    nir_deref_instr *sampler_deref_instr = NULL;
6153    int plane = -1;
6154
6155    for (unsigned i = 0; i < instr->num_srcs; i++) {
6156       switch (instr->src[i].src_type) {
6157       case nir_tex_src_texture_deref:
6158          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
6159          break;
6160       case nir_tex_src_sampler_deref:
6161          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
6162          break;
6163       case nir_tex_src_plane:
6164          plane = nir_src_as_int(instr->src[i].src);
6165          break;
6166       default:
6167          break;
6168       }
6169    }
6170
6171    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
6172
6173    if (!sampler_deref_instr)
6174       sampler_deref_instr = texture_deref_instr;
6175
6176    if (plane >= 0) {
6177       assert(instr->op != nir_texop_txf_ms &&
6178              instr->op != nir_texop_samples_identical);
6179       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6180       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6181    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6182       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6183    } else {
6184       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6185    }
6186    if (samp_ptr) {
6187       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6188       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6189          fprintf(stderr, "Unimplemented sampler descriptor: ");
6190          nir_print_instr(&instr->instr, stderr);
6191          fprintf(stderr, "\n");
6192          abort();
6193          // TODO: build samp_ptr = and(samp_ptr, res_ptr)
6194       }
6195    }
6196    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
6197                      instr->op == nir_texop_samples_identical))
6198       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6199 }
6200
6201 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
6202                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
6203 {
6204    Builder bld(ctx->program, ctx->block);
6205
6206    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
6207    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
6208    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
6209
6210    Operand neg_one(0xbf800000u);
6211    Operand one(0x3f800000u);
6212    Operand two(0x40000000u);
6213    Operand four(0x40800000u);
6214
6215    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
6216    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
6217    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
6218
6219    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
6220    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(s2), two, id);
6221    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
6222    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
6223
6224    // select sc
6225    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
6226    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
6227                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
6228                        one, is_ma_y);
6229    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6230
6231    // select tc
6232    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
6233    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
6234    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6235
6236    // select ma
6237    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6238                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
6239                   deriv_z, is_ma_z);
6240    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
6241    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
6242 }
6243
6244 void prepare_cube_coords(isel_context *ctx, Temp* coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
6245 {
6246    Builder bld(ctx->program, ctx->block);
6247    Temp coord_args[4], ma, tc, sc, id;
6248    for (unsigned i = 0; i < (is_array ? 4 : 3); i++)
6249       coord_args[i] = emit_extract_vector(ctx, *coords, i, v1);
6250
6251    if (is_array) {
6252       coord_args[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_args[3]);
6253
6254       // see comment in ac_prepare_cube_coords()
6255       if (ctx->options->chip_class <= GFX8)
6256          coord_args[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coord_args[3]);
6257    }
6258
6259    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6260
6261    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
6262    vop3a->operands[0] = Operand(ma);
6263    vop3a->abs[0] = true;
6264    Temp invma = bld.tmp(v1);
6265    vop3a->definitions[0] = Definition(invma);
6266    ctx->block->instructions.emplace_back(std::move(vop3a));
6267
6268    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6269    if (!is_deriv)
6270       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
6271
6272    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6273    if (!is_deriv)
6274       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
6275
6276    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6277
6278    if (is_deriv) {
6279       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
6280       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
6281
6282       for (unsigned i = 0; i < 2; i++) {
6283          // see comment in ac_prepare_cube_coords()
6284          Temp deriv_ma;
6285          Temp deriv_sc, deriv_tc;
6286          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
6287                            &deriv_ma, &deriv_sc, &deriv_tc);
6288
6289          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
6290
6291          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6292                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
6293                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
6294          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6295                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
6296                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
6297          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
6298       }
6299
6300       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
6301       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
6302    }
6303
6304    if (is_array)
6305       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coord_args[3], id, Operand(0x41000000u/*8.0*/));
6306    *coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), sc, tc, id);
6307
6308 }
6309
6310 Temp apply_round_slice(isel_context *ctx, Temp coords, unsigned idx)
6311 {
6312    Temp coord_vec[3];
6313    for (unsigned i = 0; i < coords.size(); i++)
6314       coord_vec[i] = emit_extract_vector(ctx, coords, i, v1);
6315
6316    Builder bld(ctx->program, ctx->block);
6317    coord_vec[idx] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_vec[idx]);
6318
6319    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6320    for (unsigned i = 0; i < coords.size(); i++)
6321       vec->operands[i] = Operand(coord_vec[i]);
6322    Temp res = bld.tmp(RegType::vgpr, coords.size());
6323    vec->definitions[0] = Definition(res);
6324    ctx->block->instructions.emplace_back(std::move(vec));
6325    return res;
6326 }
6327
6328 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
6329 {
6330    if (vec->parent_instr->type != nir_instr_type_alu)
6331       return;
6332    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
6333    if (vec_instr->op != nir_op_vec(vec->num_components))
6334       return;
6335
6336    for (unsigned i = 0; i < vec->num_components; i++) {
6337       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
6338               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
6339    }
6340 }
6341
6342 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
6343 {
6344    Builder bld(ctx->program, ctx->block);
6345    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
6346         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
6347    Temp resource, sampler, fmask_ptr, bias = Temp(), coords, compare = Temp(), sample_index = Temp(),
6348         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp(), derivs = Temp();
6349    nir_const_value *sample_index_cv = NULL;
6350    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
6351    enum glsl_base_type stype;
6352    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
6353
6354    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
6355                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
6356    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
6357                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
6358
6359    for (unsigned i = 0; i < instr->num_srcs; i++) {
6360       switch (instr->src[i].src_type) {
6361       case nir_tex_src_coord:
6362          coords = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[i].src.ssa));
6363          break;
6364       case nir_tex_src_bias:
6365          if (instr->op == nir_texop_txb) {
6366             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
6367             has_bias = true;
6368          }
6369          break;
6370       case nir_tex_src_lod: {
6371          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
6372
6373          if (val && val->f32 <= 0.0) {
6374             level_zero = true;
6375          } else {
6376             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
6377             has_lod = true;
6378          }
6379          break;
6380       }
6381       case nir_tex_src_comparator:
6382          if (instr->is_shadow) {
6383             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
6384             has_compare = true;
6385          }
6386          break;
6387       case nir_tex_src_offset:
6388          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
6389          get_const_vec(instr->src[i].src.ssa, const_offset);
6390          has_offset = true;
6391          break;
6392       case nir_tex_src_ddx:
6393          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
6394          has_ddx = true;
6395          break;
6396       case nir_tex_src_ddy:
6397          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
6398          has_ddy = true;
6399          break;
6400       case nir_tex_src_ms_index:
6401          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
6402          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
6403          has_sample_index = true;
6404          break;
6405       case nir_tex_src_texture_offset:
6406       case nir_tex_src_sampler_offset:
6407       default:
6408          break;
6409       }
6410    }
6411 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6412    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
6413       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
6414
6415    if (instr->op == nir_texop_texture_samples) {
6416       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
6417
6418       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
6419       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
6420       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6421       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
6422
6423       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6424                samples, Operand(1u), bld.scc(is_msaa));
6425       return;
6426    }
6427
6428    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
6429       aco_ptr<Instruction> tmp_instr;
6430       Temp acc, pack = Temp();
6431
6432       uint32_t pack_const = 0;
6433       for (unsigned i = 0; i < offset.size(); i++) {
6434          if (!const_offset[i])
6435             continue;
6436          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
6437       }
6438
6439       if (offset.type() == RegType::sgpr) {
6440          for (unsigned i = 0; i < offset.size(); i++) {
6441             if (const_offset[i])
6442                continue;
6443
6444             acc = emit_extract_vector(ctx, offset, i, s1);
6445             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
6446
6447             if (i) {
6448                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
6449             }
6450
6451             if (pack == Temp()) {
6452                pack = acc;
6453             } else {
6454                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
6455             }
6456          }
6457
6458          if (pack_const && pack != Temp())
6459             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
6460       } else {
6461          for (unsigned i = 0; i < offset.size(); i++) {
6462             if (const_offset[i])
6463                continue;
6464
6465             acc = emit_extract_vector(ctx, offset, i, v1);
6466             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
6467
6468             if (i) {
6469                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
6470             }
6471
6472             if (pack == Temp()) {
6473                pack = acc;
6474             } else {
6475                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
6476             }
6477          }
6478
6479          if (pack_const && pack != Temp())
6480             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
6481       }
6482       if (pack_const && pack == Temp())
6483          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
6484       else if (pack == Temp())
6485          has_offset = false;
6486       else
6487          offset = pack;
6488    }
6489
6490    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
6491       prepare_cube_coords(ctx, &coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
6492
6493    /* pack derivatives */
6494    if (has_ddx || has_ddy) {
6495       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
6496          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(v4),
6497                              ddx, Operand(0u), ddy, Operand(0u));
6498       } else {
6499          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, ddx.size() + ddy.size()), ddx, ddy);
6500       }
6501       has_derivs = true;
6502    }
6503
6504    if (instr->coord_components > 1 &&
6505        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6506        instr->is_array &&
6507        instr->op != nir_texop_txf)
6508       coords = apply_round_slice(ctx, coords, 1);
6509
6510    if (instr->coord_components > 2 &&
6511       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
6512        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6513        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
6514        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6515        instr->is_array &&
6516        instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms)
6517       coords = apply_round_slice(ctx, coords, 2);
6518
6519    if (ctx->options->chip_class == GFX9 &&
6520        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6521        instr->op != nir_texop_lod && instr->coord_components) {
6522       assert(coords.size() > 0 && coords.size() < 3);
6523
6524       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size() + 1, 1)};
6525       vec->operands[0] = Operand(emit_extract_vector(ctx, coords, 0, v1));
6526       vec->operands[1] = instr->op == nir_texop_txf ? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6527       if (coords.size() > 1)
6528          vec->operands[2] = Operand(emit_extract_vector(ctx, coords, 1, v1));
6529       coords = bld.tmp(RegType::vgpr, coords.size() + 1);
6530       vec->definitions[0] = Definition(coords);
6531       ctx->block->instructions.emplace_back(std::move(vec));
6532    }
6533
6534    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
6535
6536    if (instr->op == nir_texop_samples_identical)
6537       resource = fmask_ptr;
6538
6539    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6540              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6541             instr->op != nir_texop_txs) {
6542       assert(has_sample_index);
6543       Operand op(sample_index);
6544       if (sample_index_cv)
6545          op = Operand(sample_index_cv->u32);
6546       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
6547    }
6548
6549    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
6550       Temp split_coords[coords.size()];
6551       emit_split_vector(ctx, coords, coords.size());
6552       for (unsigned i = 0; i < coords.size(); i++)
6553          split_coords[i] = emit_extract_vector(ctx, coords, i, v1);
6554
6555       unsigned i = 0;
6556       for (; i < std::min(offset.size(), instr->coord_components); i++) {
6557          Temp off = emit_extract_vector(ctx, offset, i, v1);
6558          split_coords[i] = bld.vadd32(bld.def(v1), split_coords[i], off);
6559       }
6560
6561       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6562       for (unsigned i = 0; i < coords.size(); i++)
6563          vec->operands[i] = Operand(split_coords[i]);
6564       coords = bld.tmp(coords.regClass());
6565       vec->definitions[0] = Definition(coords);
6566       ctx->block->instructions.emplace_back(std::move(vec));
6567
6568       has_offset = false;
6569    }
6570
6571    /* Build tex instruction */
6572    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
6573    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
6574                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
6575                   : 0;
6576    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6577    Temp tmp_dst = dst;
6578
6579    /* gather4 selects the component by dmask and always returns vec4 */
6580    if (instr->op == nir_texop_tg4) {
6581       assert(instr->dest.ssa.num_components == 4);
6582       if (instr->is_shadow)
6583          dmask = 1;
6584       else
6585          dmask = 1 << instr->component;
6586       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
6587          tmp_dst = bld.tmp(v4);
6588    } else if (instr->op == nir_texop_samples_identical) {
6589       tmp_dst = bld.tmp(v1);
6590    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
6591       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
6592    }
6593
6594    aco_ptr<MIMG_instruction> tex;
6595    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
6596       if (!has_lod)
6597          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6598
6599       bool div_by_6 = instr->op == nir_texop_txs &&
6600                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
6601                       instr->is_array &&
6602                       (dmask & (1 << 2));
6603       if (tmp_dst.id() == dst.id() && div_by_6)
6604          tmp_dst = bld.tmp(tmp_dst.regClass());
6605
6606       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6607       tex->operands[0] = Operand(as_vgpr(ctx,lod));
6608       tex->operands[1] = Operand(resource);
6609       if (ctx->options->chip_class == GFX9 &&
6610           instr->op == nir_texop_txs &&
6611           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6612           instr->is_array) {
6613          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
6614       } else if (instr->op == nir_texop_query_levels) {
6615          tex->dmask = 1 << 3;
6616       } else {
6617          tex->dmask = dmask;
6618       }
6619       tex->da = da;
6620       tex->definitions[0] = Definition(tmp_dst);
6621       tex->dim = dim;
6622       tex->can_reorder = true;
6623       ctx->block->instructions.emplace_back(std::move(tex));
6624
6625       if (div_by_6) {
6626          /* divide 3rd value by 6 by multiplying with magic number */
6627          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6628          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
6629          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
6630          assert(instr->dest.ssa.num_components == 3);
6631          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
6632          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6633                               emit_extract_vector(ctx, tmp_dst, 0, v1),
6634                               emit_extract_vector(ctx, tmp_dst, 1, v1),
6635                               by_6);
6636
6637       }
6638
6639       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6640       return;
6641    }
6642
6643    Temp tg4_compare_cube_wa64 = Temp();
6644
6645    if (tg4_integer_workarounds) {
6646       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6647       tex->operands[0] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6648       tex->operands[1] = Operand(resource);
6649       tex->dim = dim;
6650       tex->dmask = 0x3;
6651       tex->da = da;
6652       Temp size = bld.tmp(v2);
6653       tex->definitions[0] = Definition(size);
6654       tex->can_reorder = true;
6655       ctx->block->instructions.emplace_back(std::move(tex));
6656       emit_split_vector(ctx, size, size.size());
6657
6658       Temp half_texel[2];
6659       for (unsigned i = 0; i < 2; i++) {
6660          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
6661          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
6662          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
6663          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
6664       }
6665
6666       Temp orig_coords[2] = {
6667          emit_extract_vector(ctx, coords, 0, v1),
6668          emit_extract_vector(ctx, coords, 1, v1)};
6669       Temp new_coords[2] = {
6670          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[0], half_texel[0]),
6671          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[1], half_texel[1])
6672       };
6673
6674       if (tg4_integer_cube_workaround) {
6675          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6676          Temp desc[resource.size()];
6677          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
6678                                                                            Format::PSEUDO, 1, resource.size())};
6679          split->operands[0] = Operand(resource);
6680          for (unsigned i = 0; i < resource.size(); i++) {
6681             desc[i] = bld.tmp(s1);
6682             split->definitions[i] = Definition(desc[i]);
6683          }
6684          ctx->block->instructions.emplace_back(std::move(split));
6685
6686          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
6687          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
6688                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
6689
6690          Temp nfmt;
6691          if (stype == GLSL_TYPE_UINT) {
6692             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6693                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
6694                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
6695                             bld.scc(compare_cube_wa));
6696          } else {
6697             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6698                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
6699                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
6700                             bld.scc(compare_cube_wa));
6701          }
6702          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
6703          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
6704
6705          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
6706
6707          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
6708                             Operand((uint32_t)C_008F14_NUM_FORMAT));
6709          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
6710
6711          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6712                                                                          Format::PSEUDO, resource.size(), 1)};
6713          for (unsigned i = 0; i < resource.size(); i++)
6714             vec->operands[i] = Operand(desc[i]);
6715          resource = bld.tmp(resource.regClass());
6716          vec->definitions[0] = Definition(resource);
6717          ctx->block->instructions.emplace_back(std::move(vec));
6718
6719          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6720                                   new_coords[0], orig_coords[0], tg4_compare_cube_wa64);
6721          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6722                                   new_coords[1], orig_coords[1], tg4_compare_cube_wa64);
6723       }
6724
6725       if (coords.size() == 3) {
6726          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3),
6727                              new_coords[0], new_coords[1],
6728                              emit_extract_vector(ctx, coords, 2, v1));
6729       } else {
6730          assert(coords.size() == 2);
6731          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2),
6732                              new_coords[0], new_coords[1]);
6733       }
6734    }
6735
6736    std::vector<Operand> args;
6737    if (has_offset)
6738       args.emplace_back(Operand(offset));
6739    if (has_bias)
6740       args.emplace_back(Operand(bias));
6741    if (has_compare)
6742       args.emplace_back(Operand(compare));
6743    if (has_derivs)
6744       args.emplace_back(Operand(derivs));
6745    args.emplace_back(Operand(coords));
6746    if (has_sample_index)
6747       args.emplace_back(Operand(sample_index));
6748    if (has_lod)
6749       args.emplace_back(lod);
6750
6751    Temp arg;
6752    if (args.size() > 1) {
6753       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
6754       unsigned size = 0;
6755       for (unsigned i = 0; i < args.size(); i++) {
6756          size += args[i].size();
6757          vec->operands[i] = args[i];
6758       }
6759       RegClass rc = RegClass(RegType::vgpr, size);
6760       Temp tmp = bld.tmp(rc);
6761       vec->definitions[0] = Definition(tmp);
6762       ctx->block->instructions.emplace_back(std::move(vec));
6763       arg = tmp;
6764    } else {
6765       assert(args[0].isTemp());
6766       arg = as_vgpr(ctx, args[0].getTemp());
6767    }
6768
6769    /* we don't need the bias, sample index, compare value or offset to be
6770     * computed in WQM but if the p_create_vector copies the coordinates, then it
6771     * needs to be in WQM */
6772    if (!(has_ddx && has_ddy) && !has_lod && !level_zero &&
6773        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
6774        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
6775       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
6776
6777    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
6778       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6779
6780       assert(coords.size() == 1);
6781       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
6782       aco_opcode op;
6783       switch (last_bit) {
6784       case 1:
6785          op = aco_opcode::buffer_load_format_x; break;
6786       case 2:
6787          op = aco_opcode::buffer_load_format_xy; break;
6788       case 3:
6789          op = aco_opcode::buffer_load_format_xyz; break;
6790       case 4:
6791          op = aco_opcode::buffer_load_format_xyzw; break;
6792       default:
6793          unreachable("Tex instruction loads more than 4 components.");
6794       }
6795
6796       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6797       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
6798          tmp_dst = dst;
6799       else
6800          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
6801
6802       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
6803       mubuf->operands[0] = Operand(coords);
6804       mubuf->operands[1] = Operand(resource);
6805       mubuf->operands[2] = Operand((uint32_t) 0);
6806       mubuf->definitions[0] = Definition(tmp_dst);
6807       mubuf->idxen = true;
6808       mubuf->can_reorder = true;
6809       ctx->block->instructions.emplace_back(std::move(mubuf));
6810
6811       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
6812       return;
6813    }
6814
6815
6816    if (instr->op == nir_texop_txf ||
6817        instr->op == nir_texop_txf_ms ||
6818        instr->op == nir_texop_samples_identical) {
6819       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
6820       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 2, 1));
6821       tex->operands[0] = Operand(arg);
6822       tex->operands[1] = Operand(resource);
6823       tex->dim = dim;
6824       tex->dmask = dmask;
6825       tex->unrm = true;
6826       tex->da = da;
6827       tex->definitions[0] = Definition(tmp_dst);
6828       tex->can_reorder = true;
6829       ctx->block->instructions.emplace_back(std::move(tex));
6830
6831       if (instr->op == nir_texop_samples_identical) {
6832          assert(dmask == 1 && dst.regClass() == v1);
6833          assert(dst.id() != tmp_dst.id());
6834
6835          Temp tmp = bld.tmp(bld.lm);
6836          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
6837          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
6838
6839       } else {
6840          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6841       }
6842       return;
6843    }
6844
6845    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6846    aco_opcode opcode = aco_opcode::image_sample;
6847    if (has_offset) { /* image_sample_*_o */
6848       if (has_compare) {
6849          opcode = aco_opcode::image_sample_c_o;
6850          if (has_derivs)
6851             opcode = aco_opcode::image_sample_c_d_o;
6852          if (has_bias)
6853             opcode = aco_opcode::image_sample_c_b_o;
6854          if (level_zero)
6855             opcode = aco_opcode::image_sample_c_lz_o;
6856          if (has_lod)
6857             opcode = aco_opcode::image_sample_c_l_o;
6858       } else {
6859          opcode = aco_opcode::image_sample_o;
6860          if (has_derivs)
6861             opcode = aco_opcode::image_sample_d_o;
6862          if (has_bias)
6863             opcode = aco_opcode::image_sample_b_o;
6864          if (level_zero)
6865             opcode = aco_opcode::image_sample_lz_o;
6866          if (has_lod)
6867             opcode = aco_opcode::image_sample_l_o;
6868       }
6869    } else { /* no offset */
6870       if (has_compare) {
6871          opcode = aco_opcode::image_sample_c;
6872          if (has_derivs)
6873             opcode = aco_opcode::image_sample_c_d;
6874          if (has_bias)
6875             opcode = aco_opcode::image_sample_c_b;
6876          if (level_zero)
6877             opcode = aco_opcode::image_sample_c_lz;
6878          if (has_lod)
6879             opcode = aco_opcode::image_sample_c_l;
6880       } else {
6881          opcode = aco_opcode::image_sample;
6882          if (has_derivs)
6883             opcode = aco_opcode::image_sample_d;
6884          if (has_bias)
6885             opcode = aco_opcode::image_sample_b;
6886          if (level_zero)
6887             opcode = aco_opcode::image_sample_lz;
6888          if (has_lod)
6889             opcode = aco_opcode::image_sample_l;
6890       }
6891    }
6892
6893    if (instr->op == nir_texop_tg4) {
6894       if (has_offset) {
6895          opcode = aco_opcode::image_gather4_lz_o;
6896          if (has_compare)
6897             opcode = aco_opcode::image_gather4_c_lz_o;
6898       } else {
6899          opcode = aco_opcode::image_gather4_lz;
6900          if (has_compare)
6901             opcode = aco_opcode::image_gather4_c_lz;
6902       }
6903    } else if (instr->op == nir_texop_lod) {
6904       opcode = aco_opcode::image_get_lod;
6905    }
6906
6907    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
6908    tex->operands[0] = Operand(arg);
6909    tex->operands[1] = Operand(resource);
6910    tex->operands[2] = Operand(sampler);
6911    tex->dim = dim;
6912    tex->dmask = dmask;
6913    tex->da = da;
6914    tex->definitions[0] = Definition(tmp_dst);
6915    tex->can_reorder = true;
6916    ctx->block->instructions.emplace_back(std::move(tex));
6917
6918    if (tg4_integer_cube_workaround) {
6919       assert(tmp_dst.id() != dst.id());
6920       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
6921
6922       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6923       Temp val[4];
6924       for (unsigned i = 0; i < dst.size(); i++) {
6925          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
6926          Temp cvt_val;
6927          if (stype == GLSL_TYPE_UINT)
6928             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
6929          else
6930             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
6931          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
6932       }
6933       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
6934       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6935                            val[0], val[1], val[2], val[3]);
6936    }
6937    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
6938    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
6939
6940 }
6941
6942
6943 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
6944 {
6945    Temp tmp = get_ssa_temp(ctx, ssa);
6946    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
6947       return Operand(tmp.regClass());
6948    else
6949       return Operand(tmp);
6950 }
6951
6952 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
6953 {
6954    aco_ptr<Pseudo_instruction> phi;
6955    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6956    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
6957
6958    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
6959    logical |= ctx->block->kind & block_kind_merge;
6960    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
6961
6962    /* we want a sorted list of sources, since the predecessor list is also sorted */
6963    std::map<unsigned, nir_ssa_def*> phi_src;
6964    nir_foreach_phi_src(src, instr)
6965       phi_src[src->pred->index] = src->src.ssa;
6966
6967    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
6968    unsigned num_operands = 0;
6969    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
6970    unsigned num_defined = 0;
6971    unsigned cur_pred_idx = 0;
6972    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
6973       if (cur_pred_idx < preds.size()) {
6974          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
6975          unsigned block = ctx->cf_info.nir_to_aco[src.first];
6976          unsigned skipped = 0;
6977          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
6978             skipped++;
6979          if (cur_pred_idx + skipped < preds.size()) {
6980             for (unsigned i = 0; i < skipped; i++)
6981                operands[num_operands++] = Operand(dst.regClass());
6982             cur_pred_idx += skipped;
6983          } else {
6984             continue;
6985          }
6986       }
6987       cur_pred_idx++;
6988       Operand op = get_phi_operand(ctx, src.second);
6989       operands[num_operands++] = op;
6990       num_defined += !op.isUndefined();
6991    }
6992    /* handle block_kind_continue_or_break at loop exit blocks */
6993    while (cur_pred_idx++ < preds.size())
6994       operands[num_operands++] = Operand(dst.regClass());
6995
6996    if (num_defined == 0) {
6997       Builder bld(ctx->program, ctx->block);
6998       if (dst.regClass() == s1) {
6999          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
7000       } else if (dst.regClass() == v1) {
7001          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
7002       } else {
7003          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7004          for (unsigned i = 0; i < dst.size(); i++)
7005             vec->operands[i] = Operand(0u);
7006          vec->definitions[0] = Definition(dst);
7007          ctx->block->instructions.emplace_back(std::move(vec));
7008       }
7009       return;
7010    }
7011
7012    /* we can use a linear phi in some cases if one src is undef */
7013    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
7014       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
7015
7016       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
7017       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
7018       assert(invert->kind & block_kind_invert);
7019
7020       unsigned then_block = invert->linear_preds[0];
7021
7022       Block* insert_block = NULL;
7023       for (unsigned i = 0; i < num_operands; i++) {
7024          Operand op = operands[i];
7025          if (op.isUndefined())
7026             continue;
7027          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
7028          phi->operands[0] = op;
7029          break;
7030       }
7031       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
7032       phi->operands[1] = Operand(dst.regClass());
7033       phi->definitions[0] = Definition(dst);
7034       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
7035       return;
7036    }
7037
7038    /* try to scalarize vector phis */
7039    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
7040       // TODO: scalarize linear phis on divergent ifs
7041       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
7042       std::array<Temp, 4> new_vec;
7043       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
7044          Operand src = operands[i];
7045          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
7046             can_scalarize = false;
7047       }
7048       if (can_scalarize) {
7049          unsigned num_components = instr->dest.ssa.num_components;
7050          assert(dst.size() % num_components == 0);
7051          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
7052
7053          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
7054          for (unsigned k = 0; k < num_components; k++) {
7055             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7056             for (unsigned i = 0; i < num_operands; i++) {
7057                Operand src = operands[i];
7058                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
7059             }
7060             Temp phi_dst = {ctx->program->allocateId(), rc};
7061             phi->definitions[0] = Definition(phi_dst);
7062             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7063             new_vec[k] = phi_dst;
7064             vec->operands[k] = Operand(phi_dst);
7065          }
7066          vec->definitions[0] = Definition(dst);
7067          ctx->block->instructions.emplace_back(std::move(vec));
7068          ctx->allocated_vec.emplace(dst.id(), new_vec);
7069          return;
7070       }
7071    }
7072
7073    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7074    for (unsigned i = 0; i < num_operands; i++)
7075       phi->operands[i] = operands[i];
7076    phi->definitions[0] = Definition(dst);
7077    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7078 }
7079
7080
7081 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
7082 {
7083    Temp dst = get_ssa_temp(ctx, &instr->def);
7084
7085    assert(dst.type() == RegType::sgpr);
7086
7087    if (dst.size() == 1) {
7088       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
7089    } else {
7090       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7091       for (unsigned i = 0; i < dst.size(); i++)
7092          vec->operands[i] = Operand(0u);
7093       vec->definitions[0] = Definition(dst);
7094       ctx->block->instructions.emplace_back(std::move(vec));
7095    }
7096 }
7097
7098 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
7099 {
7100    Builder bld(ctx->program, ctx->block);
7101    Block *logical_target;
7102    append_logical_end(ctx->block);
7103    unsigned idx = ctx->block->index;
7104
7105    switch (instr->type) {
7106    case nir_jump_break:
7107       logical_target = ctx->cf_info.parent_loop.exit;
7108       add_logical_edge(idx, logical_target);
7109       ctx->block->kind |= block_kind_break;
7110
7111       if (!ctx->cf_info.parent_if.is_divergent &&
7112           !ctx->cf_info.parent_loop.has_divergent_continue) {
7113          /* uniform break - directly jump out of the loop */
7114          ctx->block->kind |= block_kind_uniform;
7115          ctx->cf_info.has_branch = true;
7116          bld.branch(aco_opcode::p_branch);
7117          add_linear_edge(idx, logical_target);
7118          return;
7119       }
7120       ctx->cf_info.parent_loop.has_divergent_branch = true;
7121       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7122       break;
7123    case nir_jump_continue:
7124       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7125       add_logical_edge(idx, logical_target);
7126       ctx->block->kind |= block_kind_continue;
7127
7128       if (ctx->cf_info.parent_if.is_divergent) {
7129          /* for potential uniform breaks after this continue,
7130             we must ensure that they are handled correctly */
7131          ctx->cf_info.parent_loop.has_divergent_continue = true;
7132          ctx->cf_info.parent_loop.has_divergent_branch = true;
7133          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7134       } else {
7135          /* uniform continue - directly jump to the loop header */
7136          ctx->block->kind |= block_kind_uniform;
7137          ctx->cf_info.has_branch = true;
7138          bld.branch(aco_opcode::p_branch);
7139          add_linear_edge(idx, logical_target);
7140          return;
7141       }
7142       break;
7143    default:
7144       fprintf(stderr, "Unknown NIR jump instr: ");
7145       nir_print_instr(&instr->instr, stderr);
7146       fprintf(stderr, "\n");
7147       abort();
7148    }
7149
7150    /* remove critical edges from linear CFG */
7151    bld.branch(aco_opcode::p_branch);
7152    Block* break_block = ctx->program->create_and_insert_block();
7153    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7154    break_block->kind |= block_kind_uniform;
7155    add_linear_edge(idx, break_block);
7156    /* the loop_header pointer might be invalidated by this point */
7157    if (instr->type == nir_jump_continue)
7158       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7159    add_linear_edge(break_block->index, logical_target);
7160    bld.reset(break_block);
7161    bld.branch(aco_opcode::p_branch);
7162
7163    Block* continue_block = ctx->program->create_and_insert_block();
7164    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7165    add_linear_edge(idx, continue_block);
7166    append_logical_start(continue_block);
7167    ctx->block = continue_block;
7168    return;
7169 }
7170
7171 void visit_block(isel_context *ctx, nir_block *block)
7172 {
7173    nir_foreach_instr(instr, block) {
7174       switch (instr->type) {
7175       case nir_instr_type_alu:
7176          visit_alu_instr(ctx, nir_instr_as_alu(instr));
7177          break;
7178       case nir_instr_type_load_const:
7179          visit_load_const(ctx, nir_instr_as_load_const(instr));
7180          break;
7181       case nir_instr_type_intrinsic:
7182          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
7183          break;
7184       case nir_instr_type_tex:
7185          visit_tex(ctx, nir_instr_as_tex(instr));
7186          break;
7187       case nir_instr_type_phi:
7188          visit_phi(ctx, nir_instr_as_phi(instr));
7189          break;
7190       case nir_instr_type_ssa_undef:
7191          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
7192          break;
7193       case nir_instr_type_deref:
7194          break;
7195       case nir_instr_type_jump:
7196          visit_jump(ctx, nir_instr_as_jump(instr));
7197          break;
7198       default:
7199          fprintf(stderr, "Unknown NIR instr type: ");
7200          nir_print_instr(instr, stderr);
7201          fprintf(stderr, "\n");
7202          //abort();
7203       }
7204    }
7205
7206    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7207       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
7208 }
7209
7210
7211
7212 static void visit_loop(isel_context *ctx, nir_loop *loop)
7213 {
7214    append_logical_end(ctx->block);
7215    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7216    Builder bld(ctx->program, ctx->block);
7217    bld.branch(aco_opcode::p_branch);
7218    unsigned loop_preheader_idx = ctx->block->index;
7219
7220    Block loop_exit = Block();
7221    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7222    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
7223
7224    Block* loop_header = ctx->program->create_and_insert_block();
7225    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
7226    loop_header->kind |= block_kind_loop_header;
7227    add_edge(loop_preheader_idx, loop_header);
7228    ctx->block = loop_header;
7229
7230    /* emit loop body */
7231    unsigned loop_header_idx = loop_header->index;
7232    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
7233    append_logical_start(ctx->block);
7234    visit_cf_list(ctx, &loop->body);
7235
7236    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7237    if (!ctx->cf_info.has_branch) {
7238       append_logical_end(ctx->block);
7239       if (ctx->cf_info.exec_potentially_empty) {
7240          /* Discards can result in code running with an empty exec mask.
7241           * This would result in divergent breaks not ever being taken. As a
7242           * workaround, break the loop when the loop mask is empty instead of
7243           * always continuing. */
7244          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
7245          unsigned block_idx = ctx->block->index;
7246
7247          /* create helper blocks to avoid critical edges */
7248          Block *break_block = ctx->program->create_and_insert_block();
7249          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7250          break_block->kind = block_kind_uniform;
7251          bld.reset(break_block);
7252          bld.branch(aco_opcode::p_branch);
7253          add_linear_edge(block_idx, break_block);
7254          add_linear_edge(break_block->index, &loop_exit);
7255
7256          Block *continue_block = ctx->program->create_and_insert_block();
7257          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7258          continue_block->kind = block_kind_uniform;
7259          bld.reset(continue_block);
7260          bld.branch(aco_opcode::p_branch);
7261          add_linear_edge(block_idx, continue_block);
7262          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
7263
7264          add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
7265          ctx->block = &ctx->program->blocks[block_idx];
7266       } else {
7267          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
7268          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7269             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7270          else
7271             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7272       }
7273
7274       bld.reset(ctx->block);
7275       bld.branch(aco_opcode::p_branch);
7276    }
7277
7278    /* fixup phis in loop header from unreachable blocks */
7279    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
7280       bool linear = ctx->cf_info.has_branch;
7281       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
7282       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
7283          if ((logical && instr->opcode == aco_opcode::p_phi) ||
7284              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
7285             /* the last operand should be the one that needs to be removed */
7286             instr->operands.pop_back();
7287          } else if (!is_phi(instr)) {
7288             break;
7289          }
7290       }
7291    }
7292
7293    ctx->cf_info.has_branch = false;
7294
7295    // TODO: if the loop has not a single exit, we must add one °°
7296    /* emit loop successor block */
7297    ctx->block = ctx->program->insert_block(std::move(loop_exit));
7298    append_logical_start(ctx->block);
7299
7300    #if 0
7301    // TODO: check if it is beneficial to not branch on continues
7302    /* trim linear phis in loop header */
7303    for (auto&& instr : loop_entry->instructions) {
7304       if (instr->opcode == aco_opcode::p_linear_phi) {
7305          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
7306          new_phi->definitions[0] = instr->definitions[0];
7307          for (unsigned i = 0; i < new_phi->operands.size(); i++)
7308             new_phi->operands[i] = instr->operands[i];
7309          /* check that the remaining operands are all the same */
7310          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
7311             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
7312          instr.swap(new_phi);
7313       } else if (instr->opcode == aco_opcode::p_phi) {
7314          continue;
7315       } else {
7316          break;
7317       }
7318    }
7319    #endif
7320 }
7321
7322 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
7323 {
7324    ic->cond = cond;
7325
7326    append_logical_end(ctx->block);
7327    ctx->block->kind |= block_kind_branch;
7328
7329    /* branch to linear then block */
7330    assert(cond.regClass() == ctx->program->lane_mask);
7331    aco_ptr<Pseudo_branch_instruction> branch;
7332    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7333    branch->operands[0] = Operand(cond);
7334    ctx->block->instructions.push_back(std::move(branch));
7335
7336    ic->BB_if_idx = ctx->block->index;
7337    ic->BB_invert = Block();
7338    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7339    /* Invert blocks are intentionally not marked as top level because they
7340     * are not part of the logical cfg. */
7341    ic->BB_invert.kind |= block_kind_invert;
7342    ic->BB_endif = Block();
7343    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7344    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
7345
7346    ic->exec_potentially_empty_old = ctx->cf_info.exec_potentially_empty;
7347    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
7348    ctx->cf_info.parent_if.is_divergent = true;
7349    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7350
7351    /** emit logical then block */
7352    Block* BB_then_logical = ctx->program->create_and_insert_block();
7353    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7354    add_edge(ic->BB_if_idx, BB_then_logical);
7355    ctx->block = BB_then_logical;
7356    append_logical_start(BB_then_logical);
7357 }
7358
7359 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
7360 {
7361    Block *BB_then_logical = ctx->block;
7362    append_logical_end(BB_then_logical);
7363     /* branch from logical then block to invert block */
7364    aco_ptr<Pseudo_branch_instruction> branch;
7365    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7366    BB_then_logical->instructions.emplace_back(std::move(branch));
7367    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
7368    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7369       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
7370    BB_then_logical->kind |= block_kind_uniform;
7371    assert(!ctx->cf_info.has_branch);
7372    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7373    ctx->cf_info.parent_loop.has_divergent_branch = false;
7374
7375    /** emit linear then block */
7376    Block* BB_then_linear = ctx->program->create_and_insert_block();
7377    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7378    BB_then_linear->kind |= block_kind_uniform;
7379    add_linear_edge(ic->BB_if_idx, BB_then_linear);
7380    /* branch from linear then block to invert block */
7381    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7382    BB_then_linear->instructions.emplace_back(std::move(branch));
7383    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
7384
7385    /** emit invert merge block */
7386    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
7387    ic->invert_idx = ctx->block->index;
7388
7389    /* branch to linear else block (skip else) */
7390    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
7391    branch->operands[0] = Operand(ic->cond);
7392    ctx->block->instructions.push_back(std::move(branch));
7393
7394    ic->exec_potentially_empty_old |= ctx->cf_info.exec_potentially_empty;
7395    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7396
7397    /** emit logical else block */
7398    Block* BB_else_logical = ctx->program->create_and_insert_block();
7399    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7400    add_logical_edge(ic->BB_if_idx, BB_else_logical);
7401    add_linear_edge(ic->invert_idx, BB_else_logical);
7402    ctx->block = BB_else_logical;
7403    append_logical_start(BB_else_logical);
7404 }
7405
7406 static void end_divergent_if(isel_context *ctx, if_context *ic)
7407 {
7408    Block *BB_else_logical = ctx->block;
7409    append_logical_end(BB_else_logical);
7410
7411    /* branch from logical else block to endif block */
7412    aco_ptr<Pseudo_branch_instruction> branch;
7413    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7414    BB_else_logical->instructions.emplace_back(std::move(branch));
7415    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
7416    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7417       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
7418    BB_else_logical->kind |= block_kind_uniform;
7419
7420    assert(!ctx->cf_info.has_branch);
7421    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
7422
7423
7424    /** emit linear else block */
7425    Block* BB_else_linear = ctx->program->create_and_insert_block();
7426    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7427    BB_else_linear->kind |= block_kind_uniform;
7428    add_linear_edge(ic->invert_idx, BB_else_linear);
7429
7430    /* branch from linear else block to endif block */
7431    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7432    BB_else_linear->instructions.emplace_back(std::move(branch));
7433    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
7434
7435
7436    /** emit endif merge block */
7437    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
7438    append_logical_start(ctx->block);
7439
7440
7441    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
7442    ctx->cf_info.exec_potentially_empty |= ic->exec_potentially_empty_old;
7443    /* uniform control flow never has an empty exec-mask */
7444    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
7445       ctx->cf_info.exec_potentially_empty = false;
7446 }
7447
7448 static void visit_if(isel_context *ctx, nir_if *if_stmt)
7449 {
7450    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
7451    Builder bld(ctx->program, ctx->block);
7452    aco_ptr<Pseudo_branch_instruction> branch;
7453
7454    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
7455       /**
7456        * Uniform conditionals are represented in the following way*) :
7457        *
7458        * The linear and logical CFG:
7459        *                        BB_IF
7460        *                        /    \
7461        *       BB_THEN (logical)      BB_ELSE (logical)
7462        *                        \    /
7463        *                        BB_ENDIF
7464        *
7465        * *) Exceptions may be due to break and continue statements within loops
7466        *    If a break/continue happens within uniform control flow, it branches
7467        *    to the loop exit/entry block. Otherwise, it branches to the next
7468        *    merge block.
7469        **/
7470       append_logical_end(ctx->block);
7471       ctx->block->kind |= block_kind_uniform;
7472
7473       /* emit branch */
7474       assert(cond.regClass() == bld.lm);
7475       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7476       cond = bool_to_scalar_condition(ctx, cond);
7477
7478       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7479       branch->operands[0] = Operand(cond);
7480       branch->operands[0].setFixed(scc);
7481       ctx->block->instructions.emplace_back(std::move(branch));
7482
7483       unsigned BB_if_idx = ctx->block->index;
7484       Block BB_endif = Block();
7485       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7486       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
7487
7488       /** emit then block */
7489       Block* BB_then = ctx->program->create_and_insert_block();
7490       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7491       add_edge(BB_if_idx, BB_then);
7492       append_logical_start(BB_then);
7493       ctx->block = BB_then;
7494       visit_cf_list(ctx, &if_stmt->then_list);
7495       BB_then = ctx->block;
7496       bool then_branch = ctx->cf_info.has_branch;
7497       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7498
7499       if (!then_branch) {
7500          append_logical_end(BB_then);
7501          /* branch from then block to endif block */
7502          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7503          BB_then->instructions.emplace_back(std::move(branch));
7504          add_linear_edge(BB_then->index, &BB_endif);
7505          if (!then_branch_divergent)
7506             add_logical_edge(BB_then->index, &BB_endif);
7507          BB_then->kind |= block_kind_uniform;
7508       }
7509
7510       ctx->cf_info.has_branch = false;
7511       ctx->cf_info.parent_loop.has_divergent_branch = false;
7512
7513       /** emit else block */
7514       Block* BB_else = ctx->program->create_and_insert_block();
7515       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7516       add_edge(BB_if_idx, BB_else);
7517       append_logical_start(BB_else);
7518       ctx->block = BB_else;
7519       visit_cf_list(ctx, &if_stmt->else_list);
7520       BB_else = ctx->block;
7521
7522       if (!ctx->cf_info.has_branch) {
7523          append_logical_end(BB_else);
7524          /* branch from then block to endif block */
7525          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7526          BB_else->instructions.emplace_back(std::move(branch));
7527          add_linear_edge(BB_else->index, &BB_endif);
7528          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7529             add_logical_edge(BB_else->index, &BB_endif);
7530          BB_else->kind |= block_kind_uniform;
7531       }
7532
7533       ctx->cf_info.has_branch &= then_branch;
7534       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
7535
7536       /** emit endif merge block */
7537       if (!ctx->cf_info.has_branch) {
7538          ctx->block = ctx->program->insert_block(std::move(BB_endif));
7539          append_logical_start(ctx->block);
7540       }
7541    } else { /* non-uniform condition */
7542       /**
7543        * To maintain a logical and linear CFG without critical edges,
7544        * non-uniform conditionals are represented in the following way*) :
7545        *
7546        * The linear CFG:
7547        *                        BB_IF
7548        *                        /    \
7549        *       BB_THEN (logical)      BB_THEN (linear)
7550        *                        \    /
7551        *                        BB_INVERT (linear)
7552        *                        /    \
7553        *       BB_ELSE (logical)      BB_ELSE (linear)
7554        *                        \    /
7555        *                        BB_ENDIF
7556        *
7557        * The logical CFG:
7558        *                        BB_IF
7559        *                        /    \
7560        *       BB_THEN (logical)      BB_ELSE (logical)
7561        *                        \    /
7562        *                        BB_ENDIF
7563        *
7564        * *) Exceptions may be due to break and continue statements within loops
7565        **/
7566
7567       if_context ic;
7568
7569       begin_divergent_if_then(ctx, &ic, cond);
7570       visit_cf_list(ctx, &if_stmt->then_list);
7571
7572       begin_divergent_if_else(ctx, &ic);
7573       visit_cf_list(ctx, &if_stmt->else_list);
7574
7575       end_divergent_if(ctx, &ic);
7576    }
7577 }
7578
7579 static void visit_cf_list(isel_context *ctx,
7580                           struct exec_list *list)
7581 {
7582    foreach_list_typed(nir_cf_node, node, node, list) {
7583       switch (node->type) {
7584       case nir_cf_node_block:
7585          visit_block(ctx, nir_cf_node_as_block(node));
7586          break;
7587       case nir_cf_node_if:
7588          visit_if(ctx, nir_cf_node_as_if(node));
7589          break;
7590       case nir_cf_node_loop:
7591          visit_loop(ctx, nir_cf_node_as_loop(node));
7592          break;
7593       default:
7594          unreachable("unimplemented cf list type");
7595       }
7596    }
7597 }
7598
7599 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
7600 {
7601    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
7602    uint64_t mask = ctx->vs_output.mask[slot];
7603    if (!is_pos && !mask)
7604       return;
7605    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
7606       return;
7607    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7608    exp->enabled_mask = mask;
7609    for (unsigned i = 0; i < 4; ++i) {
7610       if (mask & (1 << i))
7611          exp->operands[i] = Operand(ctx->vs_output.outputs[slot][i]);
7612       else
7613          exp->operands[i] = Operand(v1);
7614    }
7615    exp->valid_mask = false;
7616    exp->done = false;
7617    exp->compressed = false;
7618    if (is_pos)
7619       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7620    else
7621       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
7622    ctx->block->instructions.emplace_back(std::move(exp));
7623 }
7624
7625 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
7626 {
7627    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7628    exp->enabled_mask = 0;
7629    for (unsigned i = 0; i < 4; ++i)
7630       exp->operands[i] = Operand(v1);
7631    if (ctx->vs_output.mask[VARYING_SLOT_PSIZ]) {
7632       exp->operands[0] = Operand(ctx->vs_output.outputs[VARYING_SLOT_PSIZ][0]);
7633       exp->enabled_mask |= 0x1;
7634    }
7635    if (ctx->vs_output.mask[VARYING_SLOT_LAYER]) {
7636       exp->operands[2] = Operand(ctx->vs_output.outputs[VARYING_SLOT_LAYER][0]);
7637       exp->enabled_mask |= 0x4;
7638    }
7639    if (ctx->vs_output.mask[VARYING_SLOT_VIEWPORT]) {
7640       if (ctx->options->chip_class < GFX9) {
7641          exp->operands[3] = Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]);
7642          exp->enabled_mask |= 0x8;
7643       } else {
7644          Builder bld(ctx->program, ctx->block);
7645
7646          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
7647                              Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]));
7648          if (exp->operands[2].isTemp())
7649             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
7650
7651          exp->operands[2] = Operand(out);
7652          exp->enabled_mask |= 0x4;
7653       }
7654    }
7655    exp->valid_mask = false;
7656    exp->done = false;
7657    exp->compressed = false;
7658    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7659    ctx->block->instructions.emplace_back(std::move(exp));
7660 }
7661
7662 static void create_vs_exports(isel_context *ctx)
7663 {
7664    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
7665
7666    if (outinfo->export_prim_id) {
7667       ctx->vs_output.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
7668       ctx->vs_output.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
7669    }
7670
7671    if (ctx->options->key.has_multiview_view_index) {
7672       ctx->vs_output.mask[VARYING_SLOT_LAYER] |= 0x1;
7673       ctx->vs_output.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
7674    }
7675
7676    /* the order these position exports are created is important */
7677    int next_pos = 0;
7678    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
7679    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
7680       export_vs_psiz_layer_viewport(ctx, &next_pos);
7681    }
7682    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7683       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
7684    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7685       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
7686
7687    if (ctx->options->key.vs_common_out.export_clip_dists) {
7688       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7689          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
7690       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7691          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
7692    }
7693
7694    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
7695       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
7696           i != VARYING_SLOT_PRIMITIVE_ID)
7697          continue;
7698
7699       export_vs_varying(ctx, i, false, NULL);
7700    }
7701 }
7702
7703 static void emit_stream_output(isel_context *ctx,
7704                                Temp const *so_buffers,
7705                                Temp const *so_write_offset,
7706                                const struct radv_stream_output *output)
7707 {
7708    unsigned num_comps = util_bitcount(output->component_mask);
7709    unsigned loc = output->location;
7710    unsigned buf = output->buffer;
7711    unsigned offset = output->offset;
7712
7713    assert(num_comps && num_comps <= 4);
7714    if (!num_comps || num_comps > 4)
7715       return;
7716
7717    unsigned start = ffs(output->component_mask) - 1;
7718
7719    Temp out[4];
7720    bool all_undef = true;
7721    assert(ctx->stage == vertex_vs);
7722    for (unsigned i = 0; i < num_comps; i++) {
7723       out[i] = ctx->vs_output.outputs[loc][start + i];
7724       all_undef = all_undef && !out[i].id();
7725    }
7726    if (all_undef)
7727       return;
7728
7729    Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_comps)};
7730    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_comps, 1)};
7731    for (unsigned i = 0; i < num_comps; ++i)
7732       vec->operands[i] = (ctx->vs_output.mask[loc] & 1 << i) ? Operand(out[i]) : Operand(0u);
7733    vec->definitions[0] = Definition(write_data);
7734    ctx->block->instructions.emplace_back(std::move(vec));
7735
7736    aco_opcode opcode;
7737    switch (num_comps) {
7738    case 1:
7739       opcode = aco_opcode::buffer_store_dword;
7740       break;
7741    case 2:
7742       opcode = aco_opcode::buffer_store_dwordx2;
7743       break;
7744    case 3:
7745       opcode = aco_opcode::buffer_store_dwordx3;
7746       break;
7747    case 4:
7748       opcode = aco_opcode::buffer_store_dwordx4;
7749       break;
7750    }
7751
7752    aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
7753    store->operands[0] = Operand(so_write_offset[buf]);
7754    store->operands[1] = Operand(so_buffers[buf]);
7755    store->operands[2] = Operand((uint32_t) 0);
7756    store->operands[3] = Operand(write_data);
7757    if (offset > 4095) {
7758       /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7759       Builder bld(ctx->program, ctx->block);
7760       store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
7761    } else {
7762       store->offset = offset;
7763    }
7764    store->offen = true;
7765    store->glc = true;
7766    store->dlc = false;
7767    store->slc = true;
7768    store->can_reorder = true;
7769    ctx->block->instructions.emplace_back(std::move(store));
7770 }
7771
7772 static void emit_streamout(isel_context *ctx, unsigned stream)
7773 {
7774    Builder bld(ctx->program, ctx->block);
7775
7776    Temp so_buffers[4];
7777    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
7778    for (unsigned i = 0; i < 4; i++) {
7779       unsigned stride = ctx->program->info->so.strides[i];
7780       if (!stride)
7781          continue;
7782
7783       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, Operand(i * 16u));
7784    }
7785
7786    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
7787                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
7788
7789    Temp tid = emit_mbcnt(ctx, bld.def(v1));
7790
7791    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(s2), so_vtx_count, tid);
7792
7793    if_context ic;
7794    begin_divergent_if_then(ctx, &ic, can_emit);
7795
7796    bld.reset(ctx->block);
7797
7798    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
7799
7800    Temp so_write_offset[4];
7801
7802    for (unsigned i = 0; i < 4; i++) {
7803       unsigned stride = ctx->program->info->so.strides[i];
7804       if (!stride)
7805          continue;
7806
7807       if (stride == 1) {
7808          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
7809                                 get_arg(ctx, ctx->args->streamout_write_idx),
7810                                 get_arg(ctx, ctx->args->streamout_offset[i]));
7811          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
7812
7813          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
7814       } else {
7815          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
7816          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
7817                                  get_arg(ctx, ctx->args->streamout_offset[i]));
7818          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
7819       }
7820    }
7821
7822    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
7823       struct radv_stream_output *output =
7824          &ctx->program->info->so.outputs[i];
7825       if (stream != output->stream)
7826          continue;
7827
7828       emit_stream_output(ctx, so_buffers, so_write_offset, output);
7829    }
7830
7831    begin_divergent_if_else(ctx, &ic);
7832    end_divergent_if(ctx, &ic);
7833 }
7834
7835 } /* end namespace */
7836
7837 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
7838 {
7839    /* Split all arguments except for the first (ring_offsets) and the last
7840     * (exec) so that the dead channels don't stay live throughout the program.
7841     */
7842    for (unsigned i = 1; i < startpgm->definitions.size() - 1; i++) {
7843       if (startpgm->definitions[i].regClass().size() > 1) {
7844          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
7845                            startpgm->definitions[i].regClass().size());
7846       }
7847    }
7848 }
7849
7850 void handle_bc_optimize(isel_context *ctx)
7851 {
7852    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7853    Builder bld(ctx->program, ctx->block);
7854    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
7855    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
7856    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
7857    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
7858    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
7859    if (uses_center && uses_centroid) {
7860       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
7861                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
7862
7863       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
7864          Temp new_coord[2];
7865          for (unsigned i = 0; i < 2; i++) {
7866             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
7867             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
7868             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7869                                     persp_centroid, persp_center, sel);
7870          }
7871          ctx->persp_centroid = bld.tmp(v2);
7872          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
7873                     Operand(new_coord[0]), Operand(new_coord[1]));
7874          emit_split_vector(ctx, ctx->persp_centroid, 2);
7875       }
7876
7877       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
7878          Temp new_coord[2];
7879          for (unsigned i = 0; i < 2; i++) {
7880             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
7881             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
7882             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7883                                     linear_centroid, linear_center, sel);
7884          }
7885          ctx->linear_centroid = bld.tmp(v2);
7886          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
7887                     Operand(new_coord[0]), Operand(new_coord[1]));
7888          emit_split_vector(ctx, ctx->linear_centroid, 2);
7889       }
7890    }
7891 }
7892
7893 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
7894 {
7895    Program *program = ctx->program;
7896
7897    unsigned float_controls = shader->info.float_controls_execution_mode;
7898
7899    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
7900       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
7901    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
7902       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
7903                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
7904
7905    program->next_fp_mode.must_flush_denorms32 =
7906       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
7907    program->next_fp_mode.must_flush_denorms16_64 =
7908       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
7909                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
7910
7911    program->next_fp_mode.care_about_round32 =
7912       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
7913
7914    program->next_fp_mode.care_about_round16_64 =
7915       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
7916                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
7917
7918    /* default to preserving fp16 and fp64 denorms, since it's free */
7919    if (program->next_fp_mode.must_flush_denorms16_64)
7920       program->next_fp_mode.denorm16_64 = 0;
7921    else
7922       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
7923
7924    /* preserving fp32 denorms is expensive, so only do it if asked */
7925    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
7926       program->next_fp_mode.denorm32 = fp_denorm_keep;
7927    else
7928       program->next_fp_mode.denorm32 = 0;
7929
7930    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
7931       program->next_fp_mode.round32 = fp_round_tz;
7932    else
7933       program->next_fp_mode.round32 = fp_round_ne;
7934
7935    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
7936       program->next_fp_mode.round16_64 = fp_round_tz;
7937    else
7938       program->next_fp_mode.round16_64 = fp_round_ne;
7939
7940    ctx->block->fp_mode = program->next_fp_mode;
7941 }
7942
7943 void select_program(Program *program,
7944                     unsigned shader_count,
7945                     struct nir_shader *const *shaders,
7946                     ac_shader_config* config,
7947                     struct radv_shader_args *args)
7948 {
7949    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args);
7950
7951    for (unsigned i = 0; i < shader_count; i++) {
7952       nir_shader *nir = shaders[i];
7953       init_context(&ctx, nir);
7954
7955       setup_fp_mode(&ctx, nir);
7956
7957       if (!i) {
7958          /* needs to be after init_context() for FS */
7959          Pseudo_instruction *startpgm = add_startpgm(&ctx);
7960          append_logical_start(ctx.block);
7961          split_arguments(&ctx, startpgm);
7962       }
7963
7964       if_context ic;
7965       if (shader_count >= 2) {
7966          Builder bld(ctx.program, ctx.block);
7967          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), ctx.merged_wave_info, Operand((8u << 16) | (i * 8u)));
7968          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
7969          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
7970
7971          begin_divergent_if_then(&ctx, &ic, cond);
7972       }
7973
7974       if (i) {
7975          Builder bld(ctx.program, ctx.block);
7976          bld.barrier(aco_opcode::p_memory_barrier_shared); //TODO: different barriers are needed for different stages
7977          bld.sopp(aco_opcode::s_barrier);
7978       }
7979
7980       if (ctx.stage == fragment_fs)
7981          handle_bc_optimize(&ctx);
7982
7983       nir_function_impl *func = nir_shader_get_entrypoint(nir);
7984       visit_cf_list(&ctx, &func->body);
7985
7986       if (ctx.program->info->so.num_outputs/*&& !ctx->is_gs_copy_shader */)
7987          emit_streamout(&ctx, 0);
7988
7989       if (ctx.stage == vertex_vs)
7990          create_vs_exports(&ctx);
7991
7992       if (shader_count >= 2) {
7993          begin_divergent_if_else(&ctx, &ic);
7994          end_divergent_if(&ctx, &ic);
7995       }
7996
7997       ralloc_free(ctx.divergent_vals);
7998    }
7999
8000    program->config->float_mode = program->blocks[0].fp_mode.val;
8001
8002    append_logical_end(ctx.block);
8003    ctx.block->kind |= block_kind_uniform;
8004    Builder bld(ctx.program, ctx.block);
8005    if (ctx.program->wb_smem_l1_on_end)
8006       bld.smem(aco_opcode::s_dcache_wb, false);
8007    bld.sopp(aco_opcode::s_endpgm);
8008
8009    /* cleanup CFG */
8010    for (Block& BB : program->blocks) {
8011       for (unsigned idx : BB.linear_preds)
8012          program->blocks[idx].linear_succs.emplace_back(BB.index);
8013       for (unsigned idx : BB.logical_preds)
8014          program->blocks[idx].logical_succs.emplace_back(BB.index);
8015    }
8016 }
8017 }