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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
139 } else if (ctx
->program
->chip_class
<= GFX7
) {
140 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
143 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
148 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
150 Builder
bld(ctx
->program
, ctx
->block
);
153 dst
= bld
.tmp(src
.regClass());
155 assert(src
.size() == dst
.size());
157 if (ctx
->stage
!= fragment_fs
) {
161 bld
.copy(Definition(dst
), src
);
165 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
166 ctx
->program
->needs_wqm
|= program_needs_wqm
;
170 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
172 if (index
.regClass() == s1
)
173 return bld
.readlane(bld
.def(s1
), data
, index
);
175 if (ctx
->options
->chip_class
<= GFX7
) {
176 /* GFX6-7: there is no bpermute instruction */
177 Operand
index_op(index
);
178 Operand
input_data(data
);
179 index_op
.setLateKill(true);
180 input_data
.setLateKill(true);
182 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
183 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
184 /* GFX10 wave64 mode: emulate full-wave bpermute */
185 if (!ctx
->has_gfx10_wave64_bpermute
) {
186 ctx
->has_gfx10_wave64_bpermute
= true;
187 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
188 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
191 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
192 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
193 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
194 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
195 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
196 Operand
input_data(data
);
198 index_x4
.setLateKill(true);
199 input_data
.setLateKill(true);
200 same_half
.setLateKill(true);
202 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
204 /* GFX8-9 or GFX10 wave32: bpermute works normally */
205 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
206 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
210 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
212 if (ctx
->options
->chip_class
>= GFX8
) {
213 unsigned and_mask
= mask
& 0x1f;
214 unsigned or_mask
= (mask
>> 5) & 0x1f;
215 unsigned xor_mask
= (mask
>> 10) & 0x1f;
217 uint16_t dpp_ctrl
= 0xffff;
219 // TODO: we could use DPP8 for some swizzles
220 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
221 unsigned res
[4] = {0, 1, 2, 3};
222 for (unsigned i
= 0; i
< 4; i
++)
223 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
224 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
225 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
226 dpp_ctrl
= dpp_row_rr(8);
227 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
228 dpp_ctrl
= dpp_row_mirror
;
229 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
230 dpp_ctrl
= dpp_row_half_mirror
;
233 if (dpp_ctrl
!= 0xffff)
234 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
237 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
240 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
242 if (val
.type() == RegType::sgpr
) {
243 Builder
bld(ctx
->program
, ctx
->block
);
244 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
246 assert(val
.type() == RegType::vgpr
);
250 //assumes a != 0xffffffff
251 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
254 Builder
bld(ctx
->program
, ctx
->block
);
256 if (util_is_power_of_two_or_zero(b
)) {
257 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
261 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
263 assert(info
.multiplier
<= 0xffffffff);
265 bool pre_shift
= info
.pre_shift
!= 0;
266 bool increment
= info
.increment
!= 0;
267 bool multiply
= true;
268 bool post_shift
= info
.post_shift
!= 0;
270 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
271 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
275 Temp pre_shift_dst
= a
;
277 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
278 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
281 Temp increment_dst
= pre_shift_dst
;
283 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
284 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
287 Temp multiply_dst
= increment_dst
;
289 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
290 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
291 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
299 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
301 Builder
bld(ctx
->program
, ctx
->block
);
302 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
306 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
308 /* no need to extract the whole vector */
309 if (src
.regClass() == dst_rc
) {
314 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
315 Builder
bld(ctx
->program
, ctx
->block
);
316 auto it
= ctx
->allocated_vec
.find(src
.id());
317 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
318 if (it
->second
[idx
].regClass() == dst_rc
) {
319 return it
->second
[idx
];
321 assert(!dst_rc
.is_subdword());
322 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
323 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
327 if (dst_rc
.is_subdword())
328 src
= as_vgpr(ctx
, src
);
330 if (src
.bytes() == dst_rc
.bytes()) {
332 return bld
.copy(bld
.def(dst_rc
), src
);
334 Temp dst
= bld
.tmp(dst_rc
);
335 emit_extract_vector(ctx
, src
, idx
, dst
);
340 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
342 if (num_components
== 1)
344 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
347 if (num_components
> vec_src
.size()) {
348 if (vec_src
.type() == RegType::sgpr
) {
349 /* should still help get_alu_src() */
350 emit_split_vector(ctx
, vec_src
, vec_src
.size());
353 /* sub-dword split */
354 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
356 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
358 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
359 split
->operands
[0] = Operand(vec_src
);
360 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
361 for (unsigned i
= 0; i
< num_components
; i
++) {
362 elems
[i
] = {ctx
->program
->allocateId(), rc
};
363 split
->definitions
[i
] = Definition(elems
[i
]);
365 ctx
->block
->instructions
.emplace_back(std::move(split
));
366 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
369 /* This vector expansion uses a mask to determine which elements in the new vector
370 * come from the original vector. The other elements are undefined. */
371 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
373 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
378 Builder
bld(ctx
->program
, ctx
->block
);
379 if (num_components
== 1) {
380 if (dst
.type() == RegType::sgpr
)
381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
383 bld
.copy(Definition(dst
), vec_src
);
387 unsigned component_size
= dst
.size() / num_components
;
388 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
390 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
391 vec
->definitions
[0] = Definition(dst
);
393 for (unsigned i
= 0; i
< num_components
; i
++) {
394 if (mask
& (1 << i
)) {
395 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
396 if (dst
.type() == RegType::sgpr
)
397 src
= bld
.as_uniform(src
);
398 vec
->operands
[i
] = Operand(src
);
400 vec
->operands
[i
] = Operand(0u);
402 elems
[i
] = vec
->operands
[i
].getTemp();
404 ctx
->block
->instructions
.emplace_back(std::move(vec
));
405 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
408 /* adjust misaligned small bit size loads */
409 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
411 Builder
bld(ctx
->program
, ctx
->block
);
413 Temp select
= Temp();
414 if (offset
.isConstant()) {
415 assert(offset
.constantValue() && offset
.constantValue() < 4);
416 shift
= Operand(offset
.constantValue() * 8);
418 /* bit_offset = 8 * (offset & 0x3) */
419 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
420 select
= bld
.tmp(s1
);
421 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
424 if (vec
.size() == 1) {
425 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
426 } else if (vec
.size() == 2) {
427 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
428 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
430 emit_split_vector(ctx
, dst
, 2);
432 emit_extract_vector(ctx
, tmp
, 0, dst
);
433 } else if (vec
.size() == 4) {
434 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
435 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
436 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
437 if (select
!= Temp())
438 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
439 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
440 Temp mid
= bld
.tmp(s1
);
441 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
442 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
443 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
444 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
445 emit_split_vector(ctx
, dst
, 2);
449 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
451 Builder
bld(ctx
->program
, ctx
->block
);
452 if (offset
.isTemp()) {
453 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
455 if (vec
.size() == 4) {
456 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
458 } else if (vec
.size() == 3) {
459 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
460 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
461 } else if (vec
.size() == 2) {
462 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
463 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
465 for (unsigned i
= 0; i
< dst
.size(); i
++)
466 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
470 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
472 offset
= Operand(0u);
475 unsigned num_components
= vec
.bytes() / component_size
;
476 if (vec
.regClass() == dst
.regClass()) {
477 assert(offset
.constantValue() == 0);
478 bld
.copy(Definition(dst
), vec
);
479 emit_split_vector(ctx
, dst
, num_components
);
483 emit_split_vector(ctx
, vec
, num_components
);
484 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
485 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
487 assert(offset
.constantValue() % component_size
== 0);
488 unsigned skip
= offset
.constantValue() / component_size
;
489 for (unsigned i
= skip
; i
< num_components
; i
++)
490 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
492 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
493 if (dst
.type() == RegType::vgpr
) {
494 num_components
= dst
.bytes() / component_size
;
495 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
496 for (unsigned i
= 0; i
< num_components
; i
++)
497 create_vec
->operands
[i
] = Operand(elems
[i
]);
498 create_vec
->definitions
[0] = Definition(dst
);
499 bld
.insert(std::move(create_vec
));
501 /* if dst is sgpr - split the src, but move the original to sgpr. */
503 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
504 byte_align_scalar(ctx
, vec
, offset
, dst
);
506 assert(dst
.size() == vec
.size());
507 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
510 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
513 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
515 Builder
bld(ctx
->program
, ctx
->block
);
517 dst
= bld
.tmp(bld
.lm
);
519 assert(val
.regClass() == s1
);
520 assert(dst
.regClass() == bld
.lm
);
522 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
525 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
527 Builder
bld(ctx
->program
, ctx
->block
);
531 assert(val
.regClass() == bld
.lm
);
532 assert(dst
.regClass() == s1
);
534 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
535 Temp tmp
= bld
.tmp(s1
);
536 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
537 return emit_wqm(ctx
, tmp
, dst
);
540 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
543 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
544 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
546 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
549 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
550 return bld
.copy(Definition(dst
), src
);
551 else if (dst
.bytes() < src
.bytes())
552 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
556 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
559 } else if (src
.regClass() == s1
) {
561 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
563 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
564 } else if (ctx
->options
->chip_class
>= GFX8
) {
565 assert(src_bits
!= 8 || src
.regClass() == v1b
);
566 assert(src_bits
!= 16 || src
.regClass() == v2b
);
567 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
568 sdwa
->operands
[0] = Operand(src
);
569 sdwa
->definitions
[0] = Definition(tmp
);
571 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
573 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
574 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
575 bld
.insert(std::move(sdwa
));
577 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
578 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
579 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
582 if (dst_bits
== 64) {
583 if (is_signed
&& dst
.regClass() == s2
) {
584 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
585 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
586 } else if (is_signed
&& dst
.regClass() == v2
) {
587 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
590 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
597 enum sgpr_extract_mode
{
603 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
605 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
606 unsigned src_size
= src
->src
.ssa
->bit_size
;
607 unsigned swizzle
= src
->swizzle
[0];
609 if (vec
.size() > 1) {
610 assert(src_size
== 16);
611 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
612 swizzle
= swizzle
& 1;
615 Builder
bld(ctx
->program
, ctx
->block
);
616 unsigned offset
= src_size
* swizzle
;
617 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
619 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
620 bld
.copy(Definition(tmp
), vec
);
621 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
622 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
623 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
624 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
625 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
626 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
628 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
629 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
632 if (dst
.regClass() == s2
)
633 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
638 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
640 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
641 return get_ssa_temp(ctx
, src
.src
.ssa
);
643 if (src
.src
.ssa
->num_components
== size
) {
644 bool identity_swizzle
= true;
645 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
646 if (src
.swizzle
[i
] != i
)
647 identity_swizzle
= false;
649 if (identity_swizzle
)
650 return get_ssa_temp(ctx
, src
.src
.ssa
);
653 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
654 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
655 assert(elem_size
> 0);
656 assert(vec
.bytes() % elem_size
== 0);
658 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
659 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
661 return extract_8_16_bit_sgpr_element(
662 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
665 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
667 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
670 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
671 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
672 for (unsigned i
= 0; i
< size
; ++i
) {
673 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
674 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
676 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
677 vec_instr
->definitions
[0] = Definition(dst
);
678 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
679 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
684 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
688 Builder
bld(ctx
->program
, ctx
->block
);
689 if (ptr
.type() == RegType::vgpr
)
690 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
691 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
692 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
695 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
697 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
698 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
699 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
700 sop2
->definitions
[0] = Definition(dst
);
701 if (instr
->no_unsigned_wrap
)
702 sop2
->definitions
[0].setNUW(true);
704 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
705 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
708 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
709 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
711 Builder
bld(ctx
->program
, ctx
->block
);
712 bld
.is_precise
= instr
->exact
;
714 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
715 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
716 if (src1
.type() == RegType::sgpr
) {
717 if (commutative
&& src0
.type() == RegType::vgpr
) {
722 src1
= as_vgpr(ctx
, src1
);
726 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
727 assert(dst
.size() == 1);
728 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
729 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
731 bld
.vop2(op
, Definition(dst
), src0
, src1
);
735 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
736 aco_opcode op
, Temp dst
)
738 Builder
bld(ctx
->program
, ctx
->block
);
739 bld
.is_precise
= instr
->exact
;
741 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
742 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
744 if (src1
.type() == RegType::sgpr
) {
745 assert(src0
.type() == RegType::vgpr
);
746 std::swap(src0
, src1
);
749 Temp src00
= bld
.tmp(src0
.type(), 1);
750 Temp src01
= bld
.tmp(src0
.type(), 1);
751 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
752 Temp src10
= bld
.tmp(v1
);
753 Temp src11
= bld
.tmp(v1
);
754 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
755 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
756 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
760 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
761 bool flush_denorms
= false)
763 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
764 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
765 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
767 /* ensure that the instruction has at most 1 sgpr operand
768 * The optimizer will inline constants for us */
769 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
770 src0
= as_vgpr(ctx
, src0
);
771 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
772 src1
= as_vgpr(ctx
, src1
);
773 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
774 src2
= as_vgpr(ctx
, src2
);
776 Builder
bld(ctx
->program
, ctx
->block
);
777 bld
.is_precise
= instr
->exact
;
778 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
779 assert(dst
.size() == 1);
780 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
781 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
783 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
787 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
789 Builder
bld(ctx
->program
, ctx
->block
);
790 bld
.is_precise
= instr
->exact
;
791 if (dst
.type() == RegType::sgpr
)
792 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
793 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
795 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
798 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
800 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
801 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
802 assert(src0
.size() == src1
.size());
804 aco_ptr
<Instruction
> vopc
;
805 if (src1
.type() == RegType::sgpr
) {
806 if (src0
.type() == RegType::vgpr
) {
807 /* to swap the operands, we might also have to change the opcode */
809 case aco_opcode::v_cmp_lt_f16
:
810 op
= aco_opcode::v_cmp_gt_f16
;
812 case aco_opcode::v_cmp_ge_f16
:
813 op
= aco_opcode::v_cmp_le_f16
;
815 case aco_opcode::v_cmp_lt_i16
:
816 op
= aco_opcode::v_cmp_gt_i16
;
818 case aco_opcode::v_cmp_ge_i16
:
819 op
= aco_opcode::v_cmp_le_i16
;
821 case aco_opcode::v_cmp_lt_u16
:
822 op
= aco_opcode::v_cmp_gt_u16
;
824 case aco_opcode::v_cmp_ge_u16
:
825 op
= aco_opcode::v_cmp_le_u16
;
827 case aco_opcode::v_cmp_lt_f32
:
828 op
= aco_opcode::v_cmp_gt_f32
;
830 case aco_opcode::v_cmp_ge_f32
:
831 op
= aco_opcode::v_cmp_le_f32
;
833 case aco_opcode::v_cmp_lt_i32
:
834 op
= aco_opcode::v_cmp_gt_i32
;
836 case aco_opcode::v_cmp_ge_i32
:
837 op
= aco_opcode::v_cmp_le_i32
;
839 case aco_opcode::v_cmp_lt_u32
:
840 op
= aco_opcode::v_cmp_gt_u32
;
842 case aco_opcode::v_cmp_ge_u32
:
843 op
= aco_opcode::v_cmp_le_u32
;
845 case aco_opcode::v_cmp_lt_f64
:
846 op
= aco_opcode::v_cmp_gt_f64
;
848 case aco_opcode::v_cmp_ge_f64
:
849 op
= aco_opcode::v_cmp_le_f64
;
851 case aco_opcode::v_cmp_lt_i64
:
852 op
= aco_opcode::v_cmp_gt_i64
;
854 case aco_opcode::v_cmp_ge_i64
:
855 op
= aco_opcode::v_cmp_le_i64
;
857 case aco_opcode::v_cmp_lt_u64
:
858 op
= aco_opcode::v_cmp_gt_u64
;
860 case aco_opcode::v_cmp_ge_u64
:
861 op
= aco_opcode::v_cmp_le_u64
;
863 default: /* eq and ne are commutative */
870 src1
= as_vgpr(ctx
, src1
);
874 Builder
bld(ctx
->program
, ctx
->block
);
875 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
878 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
880 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
881 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
882 Builder
bld(ctx
->program
, ctx
->block
);
884 assert(dst
.regClass() == bld
.lm
);
885 assert(src0
.type() == RegType::sgpr
);
886 assert(src1
.type() == RegType::sgpr
);
887 assert(src0
.regClass() == src1
.regClass());
889 /* Emit the SALU comparison instruction */
890 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
891 /* Turn the result into a per-lane bool */
892 bool_to_vector_condition(ctx
, cmp
, dst
);
895 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
896 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
898 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
899 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
900 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
901 nir_dest_is_divergent(instr
->dest
.dest
) ||
902 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
903 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
904 aco_opcode op
= use_valu
? v_op
: s_op
;
905 assert(op
!= aco_opcode::num_opcodes
);
906 assert(dst
.regClass() == ctx
->program
->lane_mask
);
909 emit_vopc_instruction(ctx
, instr
, op
, dst
);
911 emit_sopc_instruction(ctx
, instr
, op
, dst
);
914 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
916 Builder
bld(ctx
->program
, ctx
->block
);
917 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
918 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
920 assert(dst
.regClass() == bld
.lm
);
921 assert(src0
.regClass() == bld
.lm
);
922 assert(src1
.regClass() == bld
.lm
);
924 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
927 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
929 Builder
bld(ctx
->program
, ctx
->block
);
930 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
931 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
932 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
934 assert(cond
.regClass() == bld
.lm
);
936 if (dst
.type() == RegType::vgpr
) {
937 aco_ptr
<Instruction
> bcsel
;
938 if (dst
.size() == 1) {
939 then
= as_vgpr(ctx
, then
);
940 els
= as_vgpr(ctx
, els
);
942 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
943 } else if (dst
.size() == 2) {
944 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
945 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
946 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
947 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
949 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
950 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
952 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
954 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
955 nir_print_instr(&instr
->instr
, stderr
);
956 fprintf(stderr
, "\n");
961 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
962 assert(dst
.regClass() == bld
.lm
);
963 assert(then
.regClass() == bld
.lm
);
964 assert(els
.regClass() == bld
.lm
);
967 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
968 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
969 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
970 assert(dst
.size() == then
.size());
971 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
972 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
974 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
975 nir_print_instr(&instr
->instr
, stderr
);
976 fprintf(stderr
, "\n");
981 /* divergent boolean bcsel
982 * this implements bcsel on bools: dst = s0 ? s1 : s2
983 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
984 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
986 if (cond
.id() != then
.id())
987 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
989 if (cond
.id() == els
.id())
990 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
992 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
993 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
996 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
997 aco_opcode op
, uint32_t undo
)
999 /* multiply by 16777216 to handle denormals */
1000 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1001 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1002 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1003 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1004 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1006 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1008 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1011 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1013 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1014 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1018 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1021 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1023 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1024 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1028 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1031 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1033 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1034 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1038 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1041 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1043 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1044 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1048 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1051 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1053 if (ctx
->options
->chip_class
>= GFX7
)
1054 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1056 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1057 /* TODO: create more efficient code! */
1058 if (val
.type() == RegType::sgpr
)
1059 val
= as_vgpr(ctx
, val
);
1061 /* Split the input value. */
1062 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1065 /* Extract the exponent and compute the unbiased value. */
1066 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1067 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1069 /* Extract the fractional part. */
1070 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1071 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1073 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1074 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1076 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1077 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1078 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1079 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1080 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1082 /* Get the sign bit. */
1083 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1085 /* Decide the operation to apply depending on the unbiased exponent. */
1086 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1087 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1088 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1089 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1090 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1091 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1093 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1096 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1098 if (ctx
->options
->chip_class
>= GFX7
)
1099 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1101 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1102 * lowered at NIR level for precision reasons). */
1103 Temp src0
= as_vgpr(ctx
, val
);
1105 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1106 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1108 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1109 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1110 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1112 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1113 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1114 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1115 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1117 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1118 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1120 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1122 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1123 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1125 return add
->definitions
[0].getTemp();
1128 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1130 if (!instr
->dest
.dest
.is_ssa
) {
1131 fprintf(stderr
, "nir alu dst not in ssa: ");
1132 nir_print_instr(&instr
->instr
, stderr
);
1133 fprintf(stderr
, "\n");
1136 Builder
bld(ctx
->program
, ctx
->block
);
1137 bld
.is_precise
= instr
->exact
;
1138 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1143 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1144 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1145 for (unsigned i
= 0; i
< num
; ++i
)
1146 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1148 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1149 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1150 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1151 for (unsigned i
= 0; i
< num
; ++i
) {
1152 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1153 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1155 vec
->operands
[i
] = Operand
{elems
[i
]};
1157 vec
->definitions
[0] = Definition(dst
);
1158 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1159 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1161 // TODO: that is a bit suboptimal..
1162 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1163 for (unsigned i
= 0; i
< num
- 1; ++i
)
1164 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1165 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1166 for (unsigned i
= 0; i
< num
; ++i
) {
1167 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1168 if (bit
% 32 == 0) {
1169 elems
[bit
/ 32] = elems
[i
];
1171 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1172 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1173 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1176 if (dst
.size() == 1)
1177 bld
.copy(Definition(dst
), elems
[0]);
1179 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1184 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1185 aco_ptr
<Instruction
> mov
;
1186 if (dst
.type() == RegType::sgpr
) {
1187 if (src
.type() == RegType::vgpr
)
1188 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1189 else if (src
.regClass() == s1
)
1190 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1191 else if (src
.regClass() == s2
)
1192 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1194 unreachable("wrong src register class for nir_op_imov");
1196 if (dst
.regClass() == v1
)
1197 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1198 else if (dst
.regClass() == v1b
||
1199 dst
.regClass() == v2b
||
1200 dst
.regClass() == v2
)
1201 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1203 unreachable("wrong src register class for nir_op_imov");
1208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 assert(src
.regClass() == bld
.lm
);
1211 assert(dst
.regClass() == bld
.lm
);
1212 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1213 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1214 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1215 } else if (dst
.regClass() == v1
) {
1216 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1217 } else if (dst
.regClass() == v2
) {
1218 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1219 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1220 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1221 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1222 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1223 } else if (dst
.type() == RegType::sgpr
) {
1224 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1225 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1227 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1228 nir_print_instr(&instr
->instr
, stderr
);
1229 fprintf(stderr
, "\n");
1234 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1235 if (dst
.regClass() == v1
) {
1236 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1237 } else if (dst
.regClass() == s1
) {
1238 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1239 } else if (dst
.size() == 2) {
1240 Temp src0
= bld
.tmp(dst
.type(), 1);
1241 Temp src1
= bld
.tmp(dst
.type(), 1);
1242 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1244 if (dst
.regClass() == s2
) {
1245 Temp carry
= bld
.tmp(s1
);
1246 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1247 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1248 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1250 Temp lower
= bld
.tmp(v1
);
1251 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1252 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1253 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1256 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1257 nir_print_instr(&instr
->instr
, stderr
);
1258 fprintf(stderr
, "\n");
1263 if (dst
.regClass() == s1
) {
1264 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1265 } else if (dst
.regClass() == v1
) {
1266 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1267 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1269 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1270 nir_print_instr(&instr
->instr
, stderr
);
1271 fprintf(stderr
, "\n");
1275 case nir_op_isign
: {
1276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1277 if (dst
.regClass() == s1
) {
1278 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1279 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1280 } else if (dst
.regClass() == s2
) {
1281 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1283 if (ctx
->program
->chip_class
>= GFX8
)
1284 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1286 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1287 /* SCC gets zero-extended to 64 bit */
1288 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1289 } else if (dst
.regClass() == v1
) {
1290 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1291 } else if (dst
.regClass() == v2
) {
1292 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1293 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1294 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1295 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1296 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1297 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1299 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1300 nir_print_instr(&instr
->instr
, stderr
);
1301 fprintf(stderr
, "\n");
1306 if (dst
.regClass() == v1
) {
1307 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1308 } else if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1318 if (dst
.regClass() == v1
) {
1319 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1320 } else if (dst
.regClass() == s1
) {
1321 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1324 nir_print_instr(&instr
->instr
, stderr
);
1325 fprintf(stderr
, "\n");
1330 if (dst
.regClass() == v1
) {
1331 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1332 } else if (dst
.regClass() == s1
) {
1333 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1335 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1336 nir_print_instr(&instr
->instr
, stderr
);
1337 fprintf(stderr
, "\n");
1342 if (dst
.regClass() == v1
) {
1343 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1344 } else if (dst
.regClass() == s1
) {
1345 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1347 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1348 nir_print_instr(&instr
->instr
, stderr
);
1349 fprintf(stderr
, "\n");
1354 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1355 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1356 } else if (dst
.regClass() == v1
) {
1357 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1358 } else if (dst
.regClass() == v2
) {
1359 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1360 } else if (dst
.regClass() == s1
) {
1361 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1362 } else if (dst
.regClass() == s2
) {
1363 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1365 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1366 nir_print_instr(&instr
->instr
, stderr
);
1367 fprintf(stderr
, "\n");
1372 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1373 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1374 } else if (dst
.regClass() == v1
) {
1375 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1376 } else if (dst
.regClass() == v2
) {
1377 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1378 } else if (dst
.regClass() == s1
) {
1379 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1380 } else if (dst
.regClass() == s2
) {
1381 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1383 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1384 nir_print_instr(&instr
->instr
, stderr
);
1385 fprintf(stderr
, "\n");
1390 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1391 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1392 } else if (dst
.regClass() == v1
) {
1393 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1394 } else if (dst
.regClass() == v2
) {
1395 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1396 } else if (dst
.regClass() == s1
) {
1397 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1398 } else if (dst
.regClass() == s2
) {
1399 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1401 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1402 nir_print_instr(&instr
->instr
, stderr
);
1403 fprintf(stderr
, "\n");
1408 if (dst
.regClass() == v1
) {
1409 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1410 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1411 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1412 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1413 } else if (dst
.regClass() == v2
) {
1414 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1415 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1416 } else if (dst
.regClass() == s2
) {
1417 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1418 } else if (dst
.regClass() == s1
) {
1419 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1421 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1422 nir_print_instr(&instr
->instr
, stderr
);
1423 fprintf(stderr
, "\n");
1428 if (dst
.regClass() == v1
) {
1429 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1430 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1431 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1432 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1433 } else if (dst
.regClass() == v2
) {
1434 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1435 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1436 } else if (dst
.regClass() == s1
) {
1437 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1438 } else if (dst
.regClass() == s2
) {
1439 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1441 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1442 nir_print_instr(&instr
->instr
, stderr
);
1443 fprintf(stderr
, "\n");
1448 if (dst
.regClass() == v1
) {
1449 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1450 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1451 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1452 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1453 } else if (dst
.regClass() == v2
) {
1454 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1455 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1456 } else if (dst
.regClass() == s1
) {
1457 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1458 } else if (dst
.regClass() == s2
) {
1459 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1461 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1462 nir_print_instr(&instr
->instr
, stderr
);
1463 fprintf(stderr
, "\n");
1467 case nir_op_find_lsb
: {
1468 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1469 if (src
.regClass() == s1
) {
1470 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1471 } else if (src
.regClass() == v1
) {
1472 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1473 } else if (src
.regClass() == s2
) {
1474 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1476 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1477 nir_print_instr(&instr
->instr
, stderr
);
1478 fprintf(stderr
, "\n");
1482 case nir_op_ufind_msb
:
1483 case nir_op_ifind_msb
: {
1484 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1485 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1486 aco_opcode op
= src
.regClass() == s2
?
1487 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1488 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1489 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1491 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1492 Operand(src
.size() * 32u - 1u), msb_rev
);
1493 Temp msb
= sub
.def(0).getTemp();
1494 Temp carry
= sub
.def(1).getTemp();
1496 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1497 } else if (src
.regClass() == v1
) {
1498 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1499 Temp msb_rev
= bld
.tmp(v1
);
1500 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1501 Temp msb
= bld
.tmp(v1
);
1502 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1503 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1505 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1506 nir_print_instr(&instr
->instr
, stderr
);
1507 fprintf(stderr
, "\n");
1511 case nir_op_bitfield_reverse
: {
1512 if (dst
.regClass() == s1
) {
1513 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1514 } else if (dst
.regClass() == v1
) {
1515 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1517 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1518 nir_print_instr(&instr
->instr
, stderr
);
1519 fprintf(stderr
, "\n");
1524 if (dst
.regClass() == s1
) {
1525 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1529 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1530 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1531 if (dst
.regClass() == v1
) {
1532 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1536 assert(src0
.size() == 2 && src1
.size() == 2);
1537 Temp src00
= bld
.tmp(src0
.type(), 1);
1538 Temp src01
= bld
.tmp(dst
.type(), 1);
1539 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1540 Temp src10
= bld
.tmp(src1
.type(), 1);
1541 Temp src11
= bld
.tmp(dst
.type(), 1);
1542 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1544 if (dst
.regClass() == s2
) {
1545 Temp carry
= bld
.tmp(s1
);
1546 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1547 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1549 } else if (dst
.regClass() == v2
) {
1550 Temp dst0
= bld
.tmp(v1
);
1551 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1552 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_uadd_sat
: {
1562 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1563 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1564 if (dst
.regClass() == s1
) {
1565 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1566 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1568 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1569 } else if (dst
.regClass() == v1
) {
1570 if (ctx
->options
->chip_class
>= GFX9
) {
1571 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1572 add
->operands
[0] = Operand(src0
);
1573 add
->operands
[1] = Operand(src1
);
1574 add
->definitions
[0] = Definition(dst
);
1576 ctx
->block
->instructions
.emplace_back(std::move(add
));
1578 if (src1
.regClass() != v1
)
1579 std::swap(src0
, src1
);
1580 assert(src1
.regClass() == v1
);
1581 Temp tmp
= bld
.tmp(v1
);
1582 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1583 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1586 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1587 nir_print_instr(&instr
->instr
, stderr
);
1588 fprintf(stderr
, "\n");
1592 case nir_op_uadd_carry
: {
1593 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1594 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1595 if (dst
.regClass() == s1
) {
1596 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1599 if (dst
.regClass() == v1
) {
1600 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1601 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1605 Temp src00
= bld
.tmp(src0
.type(), 1);
1606 Temp src01
= bld
.tmp(dst
.type(), 1);
1607 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1608 Temp src10
= bld
.tmp(src1
.type(), 1);
1609 Temp src11
= bld
.tmp(dst
.type(), 1);
1610 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1611 if (dst
.regClass() == s2
) {
1612 Temp carry
= bld
.tmp(s1
);
1613 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1614 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1615 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1616 } else if (dst
.regClass() == v2
) {
1617 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1618 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1619 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1620 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1623 nir_print_instr(&instr
->instr
, stderr
);
1624 fprintf(stderr
, "\n");
1629 if (dst
.regClass() == s1
) {
1630 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == v1
) {
1637 bld
.vsub32(Definition(dst
), src0
, src1
);
1641 Temp src00
= bld
.tmp(src0
.type(), 1);
1642 Temp src01
= bld
.tmp(dst
.type(), 1);
1643 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1644 Temp src10
= bld
.tmp(src1
.type(), 1);
1645 Temp src11
= bld
.tmp(dst
.type(), 1);
1646 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1647 if (dst
.regClass() == s2
) {
1648 Temp carry
= bld
.tmp(s1
);
1649 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1650 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1651 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1652 } else if (dst
.regClass() == v2
) {
1653 Temp lower
= bld
.tmp(v1
);
1654 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1655 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1656 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1659 nir_print_instr(&instr
->instr
, stderr
);
1660 fprintf(stderr
, "\n");
1664 case nir_op_usub_borrow
: {
1665 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1666 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1667 if (dst
.regClass() == s1
) {
1668 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1670 } else if (dst
.regClass() == v1
) {
1671 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1672 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1676 Temp src00
= bld
.tmp(src0
.type(), 1);
1677 Temp src01
= bld
.tmp(dst
.type(), 1);
1678 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1679 Temp src10
= bld
.tmp(src1
.type(), 1);
1680 Temp src11
= bld
.tmp(dst
.type(), 1);
1681 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1682 if (dst
.regClass() == s2
) {
1683 Temp borrow
= bld
.tmp(s1
);
1684 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1685 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1686 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1687 } else if (dst
.regClass() == v2
) {
1688 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1689 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1690 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1691 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1694 nir_print_instr(&instr
->instr
, stderr
);
1695 fprintf(stderr
, "\n");
1700 if (dst
.regClass() == v1
) {
1701 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1702 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1703 } else if (dst
.regClass() == s1
) {
1704 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1707 nir_print_instr(&instr
->instr
, stderr
);
1708 fprintf(stderr
, "\n");
1712 case nir_op_umul_high
: {
1713 if (dst
.regClass() == v1
) {
1714 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1715 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1716 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1717 } else if (dst
.regClass() == s1
) {
1718 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1719 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1720 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1722 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1723 nir_print_instr(&instr
->instr
, stderr
);
1724 fprintf(stderr
, "\n");
1728 case nir_op_imul_high
: {
1729 if (dst
.regClass() == v1
) {
1730 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1731 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1732 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1733 } else if (dst
.regClass() == s1
) {
1734 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1735 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1736 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1739 nir_print_instr(&instr
->instr
, stderr
);
1740 fprintf(stderr
, "\n");
1745 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1746 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1747 if (dst
.regClass() == v2b
) {
1748 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1749 } else if (dst
.regClass() == v1
) {
1750 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1751 } else if (dst
.regClass() == v2
) {
1752 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1755 nir_print_instr(&instr
->instr
, stderr
);
1756 fprintf(stderr
, "\n");
1761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1762 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1763 if (dst
.regClass() == v2b
) {
1764 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1765 } else if (dst
.regClass() == v1
) {
1766 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1767 } else if (dst
.regClass() == v2
) {
1768 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1779 if (dst
.regClass() == v2b
) {
1780 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1784 } else if (dst
.regClass() == v1
) {
1785 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1786 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1788 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1789 } else if (dst
.regClass() == v2
) {
1790 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1791 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1792 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1802 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1803 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1804 if (dst
.regClass() == v2b
) {
1805 // TODO: check fp_mode.must_flush_denorms16_64
1806 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1807 } else if (dst
.regClass() == v1
) {
1808 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1809 } else if (dst
.regClass() == v2
) {
1810 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1811 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1812 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1814 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1817 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1818 nir_print_instr(&instr
->instr
, stderr
);
1819 fprintf(stderr
, "\n");
1824 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1825 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1826 if (dst
.regClass() == v2b
) {
1827 // TODO: check fp_mode.must_flush_denorms16_64
1828 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1829 } else if (dst
.regClass() == v1
) {
1830 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1831 } else if (dst
.regClass() == v2
) {
1832 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1833 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1834 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1836 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1839 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1840 nir_print_instr(&instr
->instr
, stderr
);
1841 fprintf(stderr
, "\n");
1845 case nir_op_fmax3
: {
1846 if (dst
.regClass() == v2b
) {
1847 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1848 } else if (dst
.regClass() == v1
) {
1849 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1851 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1852 nir_print_instr(&instr
->instr
, stderr
);
1853 fprintf(stderr
, "\n");
1857 case nir_op_fmin3
: {
1858 if (dst
.regClass() == v2b
) {
1859 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1860 } else if (dst
.regClass() == v1
) {
1861 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1863 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1864 nir_print_instr(&instr
->instr
, stderr
);
1865 fprintf(stderr
, "\n");
1869 case nir_op_fmed3
: {
1870 if (dst
.regClass() == v2b
) {
1871 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1872 } else if (dst
.regClass() == v1
) {
1873 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1875 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1876 nir_print_instr(&instr
->instr
, stderr
);
1877 fprintf(stderr
, "\n");
1881 case nir_op_umax3
: {
1882 if (dst
.size() == 1) {
1883 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1885 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1886 nir_print_instr(&instr
->instr
, stderr
);
1887 fprintf(stderr
, "\n");
1891 case nir_op_umin3
: {
1892 if (dst
.size() == 1) {
1893 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1895 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1896 nir_print_instr(&instr
->instr
, stderr
);
1897 fprintf(stderr
, "\n");
1901 case nir_op_umed3
: {
1902 if (dst
.size() == 1) {
1903 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_imax3
: {
1912 if (dst
.size() == 1) {
1913 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1915 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1916 nir_print_instr(&instr
->instr
, stderr
);
1917 fprintf(stderr
, "\n");
1921 case nir_op_imin3
: {
1922 if (dst
.size() == 1) {
1923 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1925 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1926 nir_print_instr(&instr
->instr
, stderr
);
1927 fprintf(stderr
, "\n");
1931 case nir_op_imed3
: {
1932 if (dst
.size() == 1) {
1933 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1936 nir_print_instr(&instr
->instr
, stderr
);
1937 fprintf(stderr
, "\n");
1941 case nir_op_cube_face_coord
: {
1942 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1943 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1944 emit_extract_vector(ctx
, in
, 1, v1
),
1945 emit_extract_vector(ctx
, in
, 2, v1
) };
1946 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1947 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1948 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1949 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1950 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1951 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1952 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1955 case nir_op_cube_face_index
: {
1956 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1957 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1958 emit_extract_vector(ctx
, in
, 1, v1
),
1959 emit_extract_vector(ctx
, in
, 2, v1
) };
1960 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1963 case nir_op_bcsel
: {
1964 emit_bcsel(ctx
, instr
, dst
);
1968 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1969 if (dst
.regClass() == v2b
) {
1970 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1971 } else if (dst
.regClass() == v1
) {
1972 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1973 } else if (dst
.regClass() == v2
) {
1974 /* Lowered at NIR level for precision reasons. */
1975 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1978 nir_print_instr(&instr
->instr
, stderr
);
1979 fprintf(stderr
, "\n");
1984 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1985 if (dst
.regClass() == v2b
) {
1986 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1987 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1988 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1989 } else if (dst
.regClass() == v1
) {
1990 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1991 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1992 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1993 } else if (dst
.regClass() == v2
) {
1994 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1995 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1996 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1997 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1998 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1999 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2001 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2002 nir_print_instr(&instr
->instr
, stderr
);
2003 fprintf(stderr
, "\n");
2008 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2009 if (dst
.regClass() == v2b
) {
2010 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
2011 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
2012 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
2013 } else if (dst
.regClass() == v1
) {
2014 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
2015 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
2016 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
2017 } else if (dst
.regClass() == v2
) {
2018 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
2019 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
2020 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
2021 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2022 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
2023 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2025 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2026 nir_print_instr(&instr
->instr
, stderr
);
2027 fprintf(stderr
, "\n");
2032 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2033 if (dst
.regClass() == v2b
) {
2034 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
2035 } else if (dst
.regClass() == v1
) {
2036 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2037 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
2038 // TODO: confirm that this holds under any circumstances
2039 } else if (dst
.regClass() == v2
) {
2040 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
2041 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
2044 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2045 nir_print_instr(&instr
->instr
, stderr
);
2046 fprintf(stderr
, "\n");
2050 case nir_op_flog2
: {
2051 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2052 if (dst
.regClass() == v2b
) {
2053 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
2054 } else if (dst
.regClass() == v1
) {
2055 emit_log2(ctx
, bld
, Definition(dst
), src
);
2057 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2058 nir_print_instr(&instr
->instr
, stderr
);
2059 fprintf(stderr
, "\n");
2064 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2065 if (dst
.regClass() == v2b
) {
2066 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2067 } else if (dst
.regClass() == v1
) {
2068 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2069 } else if (dst
.regClass() == v2
) {
2070 /* Lowered at NIR level for precision reasons. */
2071 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2073 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2074 nir_print_instr(&instr
->instr
, stderr
);
2075 fprintf(stderr
, "\n");
2079 case nir_op_fexp2
: {
2080 if (dst
.regClass() == v2b
) {
2081 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2082 } else if (dst
.regClass() == v1
) {
2083 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2085 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2086 nir_print_instr(&instr
->instr
, stderr
);
2087 fprintf(stderr
, "\n");
2091 case nir_op_fsqrt
: {
2092 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2093 if (dst
.regClass() == v2b
) {
2094 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2095 } else if (dst
.regClass() == v1
) {
2096 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2097 } else if (dst
.regClass() == v2
) {
2098 /* Lowered at NIR level for precision reasons. */
2099 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2102 nir_print_instr(&instr
->instr
, stderr
);
2103 fprintf(stderr
, "\n");
2107 case nir_op_ffract
: {
2108 if (dst
.regClass() == v2b
) {
2109 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2110 } else if (dst
.regClass() == v1
) {
2111 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2112 } else if (dst
.regClass() == v2
) {
2113 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2115 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2116 nir_print_instr(&instr
->instr
, stderr
);
2117 fprintf(stderr
, "\n");
2121 case nir_op_ffloor
: {
2122 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2123 if (dst
.regClass() == v2b
) {
2124 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2125 } else if (dst
.regClass() == v1
) {
2126 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2127 } else if (dst
.regClass() == v2
) {
2128 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2130 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2131 nir_print_instr(&instr
->instr
, stderr
);
2132 fprintf(stderr
, "\n");
2136 case nir_op_fceil
: {
2137 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2138 if (dst
.regClass() == v2b
) {
2139 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2140 } else if (dst
.regClass() == v1
) {
2141 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2142 } else if (dst
.regClass() == v2
) {
2143 if (ctx
->options
->chip_class
>= GFX7
) {
2144 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2146 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2147 /* trunc = trunc(src0)
2148 * if (src0 > 0.0 && src0 != trunc)
2151 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2152 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2153 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2154 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2155 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2156 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2157 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2160 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2161 nir_print_instr(&instr
->instr
, stderr
);
2162 fprintf(stderr
, "\n");
2166 case nir_op_ftrunc
: {
2167 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2168 if (dst
.regClass() == v2b
) {
2169 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2170 } else if (dst
.regClass() == v1
) {
2171 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2172 } else if (dst
.regClass() == v2
) {
2173 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2175 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2176 nir_print_instr(&instr
->instr
, stderr
);
2177 fprintf(stderr
, "\n");
2181 case nir_op_fround_even
: {
2182 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (dst
.regClass() == v2b
) {
2184 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2185 } else if (dst
.regClass() == v1
) {
2186 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2187 } else if (dst
.regClass() == v2
) {
2188 if (ctx
->options
->chip_class
>= GFX7
) {
2189 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2191 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2192 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2193 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2195 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2196 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2197 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2198 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2199 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2200 tmp
= sub
->definitions
[0].getTemp();
2202 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2203 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2204 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2205 Temp cond
= vop3
->definitions
[0].getTemp();
2207 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2208 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2209 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2210 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2215 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2216 nir_print_instr(&instr
->instr
, stderr
);
2217 fprintf(stderr
, "\n");
2223 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2224 aco_ptr
<Instruction
> norm
;
2225 if (dst
.regClass() == v2b
) {
2226 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2227 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2228 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2229 bld
.vop1(opcode
, Definition(dst
), tmp
);
2230 } else if (dst
.regClass() == v1
) {
2231 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2232 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2234 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2235 if (ctx
->options
->chip_class
< GFX9
)
2236 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2238 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2239 bld
.vop1(opcode
, Definition(dst
), tmp
);
2241 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2242 nir_print_instr(&instr
->instr
, stderr
);
2243 fprintf(stderr
, "\n");
2247 case nir_op_ldexp
: {
2248 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2249 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2250 if (dst
.regClass() == v2b
) {
2251 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2252 } else if (dst
.regClass() == v1
) {
2253 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2254 } else if (dst
.regClass() == v2
) {
2255 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2257 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2258 nir_print_instr(&instr
->instr
, stderr
);
2259 fprintf(stderr
, "\n");
2263 case nir_op_frexp_sig
: {
2264 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2265 if (dst
.regClass() == v2b
) {
2266 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2267 } else if (dst
.regClass() == v1
) {
2268 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2269 } else if (dst
.regClass() == v2
) {
2270 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2273 nir_print_instr(&instr
->instr
, stderr
);
2274 fprintf(stderr
, "\n");
2278 case nir_op_frexp_exp
: {
2279 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2280 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2281 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2282 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2283 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2284 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2285 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2286 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2287 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2290 nir_print_instr(&instr
->instr
, stderr
);
2291 fprintf(stderr
, "\n");
2295 case nir_op_fsign
: {
2296 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2297 if (dst
.regClass() == v2b
) {
2298 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2299 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2300 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2301 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2302 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2303 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2304 } else if (dst
.regClass() == v1
) {
2305 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2306 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2307 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2308 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2309 } else if (dst
.regClass() == v2
) {
2310 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2311 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2312 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2314 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2315 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2316 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2318 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2321 nir_print_instr(&instr
->instr
, stderr
);
2322 fprintf(stderr
, "\n");
2327 case nir_op_f2f16_rtne
: {
2328 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2329 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2330 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2331 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2332 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2333 * keep value numbering and the scheduler simpler.
2335 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2337 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2340 case nir_op_f2f16_rtz
: {
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2343 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2344 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2347 case nir_op_f2f32
: {
2348 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2349 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2350 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2351 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2354 nir_print_instr(&instr
->instr
, stderr
);
2355 fprintf(stderr
, "\n");
2359 case nir_op_f2f64
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2362 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2363 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2366 case nir_op_i2f16
: {
2367 assert(dst
.regClass() == v2b
);
2368 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2369 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2370 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2371 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2372 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2373 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2376 case nir_op_i2f32
: {
2377 assert(dst
.size() == 1);
2378 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2379 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2380 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2381 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2384 case nir_op_i2f64
: {
2385 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2388 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2389 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2390 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2391 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2392 RegClass rc
= RegClass(src
.type(), 1);
2393 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2395 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2396 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2397 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2398 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2401 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2402 nir_print_instr(&instr
->instr
, stderr
);
2403 fprintf(stderr
, "\n");
2407 case nir_op_u2f16
: {
2408 assert(dst
.regClass() == v2b
);
2409 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2410 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2411 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2412 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2413 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2414 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2417 case nir_op_u2f32
: {
2418 assert(dst
.size() == 1);
2419 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2420 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2421 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2423 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2424 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2425 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2429 case nir_op_u2f64
: {
2430 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2431 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2432 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2433 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2434 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2435 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2436 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2437 RegClass rc
= RegClass(src
.type(), 1);
2438 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2439 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2440 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2441 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2442 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2443 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2445 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2446 nir_print_instr(&instr
->instr
, stderr
);
2447 fprintf(stderr
, "\n");
2452 case nir_op_f2i16
: {
2453 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2454 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2455 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2456 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2458 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2462 case nir_op_f2u16
: {
2463 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2464 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2465 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2466 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2468 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2471 case nir_op_f2i32
: {
2472 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2473 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2474 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2475 if (dst
.type() == RegType::vgpr
) {
2476 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2478 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2479 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2481 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2482 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2483 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2484 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2486 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2487 nir_print_instr(&instr
->instr
, stderr
);
2488 fprintf(stderr
, "\n");
2492 case nir_op_f2u32
: {
2493 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2494 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2495 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2496 if (dst
.type() == RegType::vgpr
) {
2497 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2499 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2500 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2502 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2503 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2504 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2505 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2507 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2508 nir_print_instr(&instr
->instr
, stderr
);
2509 fprintf(stderr
, "\n");
2513 case nir_op_f2i64
: {
2514 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2515 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2516 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2518 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2519 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2520 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2521 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2522 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2523 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2524 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2525 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2526 Temp new_exponent
= bld
.tmp(v1
);
2527 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2528 if (ctx
->program
->chip_class
>= GFX8
)
2529 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2531 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2532 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2533 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2534 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2535 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2536 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2537 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2538 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2539 Temp new_lower
= bld
.tmp(v1
);
2540 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2541 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2544 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2545 if (src
.type() == RegType::vgpr
)
2546 src
= bld
.as_uniform(src
);
2547 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2548 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2549 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2550 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2551 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2552 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2553 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2554 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2555 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2556 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2557 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2558 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2559 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2560 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2561 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2562 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2563 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2564 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2565 Temp borrow
= bld
.tmp(s1
);
2566 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2567 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2568 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2570 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2571 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2572 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2573 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2574 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2575 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2576 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2577 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2578 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2579 if (dst
.type() == RegType::sgpr
) {
2580 lower
= bld
.as_uniform(lower
);
2581 upper
= bld
.as_uniform(upper
);
2583 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2586 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2587 nir_print_instr(&instr
->instr
, stderr
);
2588 fprintf(stderr
, "\n");
2592 case nir_op_f2u64
: {
2593 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2594 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2595 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2597 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2598 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2599 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2600 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2601 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2602 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2603 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2604 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2605 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2606 Temp new_exponent
= bld
.tmp(v1
);
2607 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2608 if (ctx
->program
->chip_class
>= GFX8
)
2609 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2611 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2612 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2613 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2614 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2615 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2616 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2617 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2618 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2620 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2621 if (src
.type() == RegType::vgpr
)
2622 src
= bld
.as_uniform(src
);
2623 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2624 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2625 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2626 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2627 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2628 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2629 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2630 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2631 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2632 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2633 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2634 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2635 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2636 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2637 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2638 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2639 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2640 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2642 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2643 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2644 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2645 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2646 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2647 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2648 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2649 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2650 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2651 if (dst
.type() == RegType::sgpr
) {
2652 lower
= bld
.as_uniform(lower
);
2653 upper
= bld
.as_uniform(upper
);
2655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2658 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2659 nir_print_instr(&instr
->instr
, stderr
);
2660 fprintf(stderr
, "\n");
2664 case nir_op_b2f16
: {
2665 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2666 assert(src
.regClass() == bld
.lm
);
2668 if (dst
.regClass() == s1
) {
2669 src
= bool_to_scalar_condition(ctx
, src
);
2670 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2671 } else if (dst
.regClass() == v2b
) {
2672 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2673 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2675 unreachable("Wrong destination register class for nir_op_b2f16.");
2679 case nir_op_b2f32
: {
2680 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2681 assert(src
.regClass() == bld
.lm
);
2683 if (dst
.regClass() == s1
) {
2684 src
= bool_to_scalar_condition(ctx
, src
);
2685 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2686 } else if (dst
.regClass() == v1
) {
2687 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2689 unreachable("Wrong destination register class for nir_op_b2f32.");
2693 case nir_op_b2f64
: {
2694 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2695 assert(src
.regClass() == bld
.lm
);
2697 if (dst
.regClass() == s2
) {
2698 src
= bool_to_scalar_condition(ctx
, src
);
2699 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2700 } else if (dst
.regClass() == v2
) {
2701 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2702 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2703 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2705 unreachable("Wrong destination register class for nir_op_b2f64.");
2712 case nir_op_i2i64
: {
2713 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2714 /* no need to do the extract in get_alu_src() */
2715 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2716 sgpr_extract_sext
: sgpr_extract_undef
;
2717 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2719 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2720 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2727 case nir_op_u2u64
: {
2728 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2729 /* no need to do the extract in get_alu_src() */
2730 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2731 sgpr_extract_zext
: sgpr_extract_undef
;
2732 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2734 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2735 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2743 case nir_op_b2i64
: {
2744 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2745 assert(src
.regClass() == bld
.lm
);
2747 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2748 if (tmp
.regClass() == s1
) {
2749 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2750 bool_to_scalar_condition(ctx
, src
, tmp
);
2751 } else if (tmp
.type() == RegType::vgpr
) {
2752 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2754 unreachable("Invalid register class for b2i32");
2758 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2763 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2764 assert(dst
.regClass() == bld
.lm
);
2766 if (src
.type() == RegType::vgpr
) {
2767 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2768 assert(dst
.regClass() == bld
.lm
);
2769 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2770 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2772 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2774 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2775 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2777 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2778 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2780 bool_to_vector_condition(ctx
, tmp
, dst
);
2784 case nir_op_pack_64_2x32_split
: {
2785 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2786 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2788 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2791 case nir_op_unpack_64_2x32_split_x
:
2792 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2794 case nir_op_unpack_64_2x32_split_y
:
2795 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2797 case nir_op_unpack_32_2x16_split_x
:
2798 if (dst
.type() == RegType::vgpr
) {
2799 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2801 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2804 case nir_op_unpack_32_2x16_split_y
:
2805 if (dst
.type() == RegType::vgpr
) {
2806 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2808 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2811 case nir_op_pack_32_2x16_split
: {
2812 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2813 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2814 if (dst
.regClass() == v1
) {
2815 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2816 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2819 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2820 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2821 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2825 case nir_op_pack_half_2x16
: {
2826 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2828 if (dst
.regClass() == v1
) {
2829 Temp src0
= bld
.tmp(v1
);
2830 Temp src1
= bld
.tmp(v1
);
2831 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2832 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2833 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2835 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2836 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2837 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2839 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2840 nir_print_instr(&instr
->instr
, stderr
);
2841 fprintf(stderr
, "\n");
2845 case nir_op_unpack_half_2x16_split_x
: {
2846 if (dst
.regClass() == v1
) {
2847 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2849 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2850 nir_print_instr(&instr
->instr
, stderr
);
2851 fprintf(stderr
, "\n");
2855 case nir_op_unpack_half_2x16_split_y
: {
2856 if (dst
.regClass() == v1
) {
2857 /* TODO: use SDWA here */
2858 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2859 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2861 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2862 nir_print_instr(&instr
->instr
, stderr
);
2863 fprintf(stderr
, "\n");
2867 case nir_op_fquantize2f16
: {
2868 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2869 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2872 if (ctx
->program
->chip_class
>= GFX8
) {
2873 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2874 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2875 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2877 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2878 * so compare the result and flush to 0 if it's smaller.
2880 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2881 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2882 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2883 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2884 cmp_res
= vop3
->definitions
[0].getTemp();
2887 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2888 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2889 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2891 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2896 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2897 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2899 if (dst
.regClass() == s1
) {
2900 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2901 } else if (dst
.regClass() == v1
) {
2902 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2904 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2905 nir_print_instr(&instr
->instr
, stderr
);
2906 fprintf(stderr
, "\n");
2910 case nir_op_bitfield_select
: {
2911 /* (mask & insert) | (~mask & base) */
2912 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2913 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2914 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2916 /* dst = (insert & bitmask) | (base & ~bitmask) */
2917 if (dst
.regClass() == s1
) {
2918 aco_ptr
<Instruction
> sop2
;
2919 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2920 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2922 if (const_insert
&& const_bitmask
) {
2923 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2925 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2926 lhs
= Operand(insert
);
2930 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2931 if (const_base
&& const_bitmask
) {
2932 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2934 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2935 rhs
= Operand(base
);
2938 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2940 } else if (dst
.regClass() == v1
) {
2941 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2942 base
= as_vgpr(ctx
, base
);
2943 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2944 insert
= as_vgpr(ctx
, insert
);
2946 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2949 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2950 nir_print_instr(&instr
->instr
, stderr
);
2951 fprintf(stderr
, "\n");
2957 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2958 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2959 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2961 if (dst
.type() == RegType::sgpr
) {
2963 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2964 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2965 if (const_offset
&& const_bits
) {
2966 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2967 extract
= Operand(const_extract
);
2971 width
= Operand(const_bits
->u32
<< 16);
2973 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2975 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2979 if (dst
.regClass() == s1
) {
2980 if (instr
->op
== nir_op_ubfe
)
2981 opcode
= aco_opcode::s_bfe_u32
;
2983 opcode
= aco_opcode::s_bfe_i32
;
2984 } else if (dst
.regClass() == s2
) {
2985 if (instr
->op
== nir_op_ubfe
)
2986 opcode
= aco_opcode::s_bfe_u64
;
2988 opcode
= aco_opcode::s_bfe_i64
;
2990 unreachable("Unsupported BFE bit size");
2993 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2997 if (dst
.regClass() == v1
) {
2998 if (instr
->op
== nir_op_ubfe
)
2999 opcode
= aco_opcode::v_bfe_u32
;
3001 opcode
= aco_opcode::v_bfe_i32
;
3003 unreachable("Unsupported BFE bit size");
3006 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
3010 case nir_op_bit_count
: {
3011 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3012 if (src
.regClass() == s1
) {
3013 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
3014 } else if (src
.regClass() == v1
) {
3015 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
3016 } else if (src
.regClass() == v2
) {
3017 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
3018 emit_extract_vector(ctx
, src
, 1, v1
),
3019 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
3020 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
3021 } else if (src
.regClass() == s2
) {
3022 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
3024 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
3025 nir_print_instr(&instr
->instr
, stderr
);
3026 fprintf(stderr
, "\n");
3031 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
3035 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
3039 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
3043 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
3047 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
3051 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
3055 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3056 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
3058 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
3059 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
3063 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
3064 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
3066 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
3067 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
3071 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
3075 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
3080 case nir_op_fddx_fine
:
3081 case nir_op_fddy_fine
:
3082 case nir_op_fddx_coarse
:
3083 case nir_op_fddy_coarse
: {
3084 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
3085 uint16_t dpp_ctrl1
, dpp_ctrl2
;
3086 if (instr
->op
== nir_op_fddx_fine
) {
3087 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
3088 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
3089 } else if (instr
->op
== nir_op_fddy_fine
) {
3090 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
3091 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
3093 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3094 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3095 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3097 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3101 if (ctx
->program
->chip_class
>= GFX8
) {
3102 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3103 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3105 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3106 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3107 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3109 emit_wqm(ctx
, tmp
, dst
, true);
3113 fprintf(stderr
, "Unknown NIR ALU instr: ");
3114 nir_print_instr(&instr
->instr
, stderr
);
3115 fprintf(stderr
, "\n");
3119 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3121 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3123 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3124 // which get truncated the lsb if double and msb if int
3125 // for now, we only use s_mov_b64 with 64bit inline constants
3126 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3127 assert(dst
.type() == RegType::sgpr
);
3129 Builder
bld(ctx
->program
, ctx
->block
);
3131 if (instr
->def
.bit_size
== 1) {
3132 assert(dst
.regClass() == bld
.lm
);
3133 int val
= instr
->value
[0].b
? -1 : 0;
3134 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3135 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3136 } else if (instr
->def
.bit_size
== 8) {
3137 /* ensure that the value is correctly represented in the low byte of the register */
3138 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3139 } else if (instr
->def
.bit_size
== 16) {
3140 /* ensure that the value is correctly represented in the low half of the register */
3141 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3142 } else if (dst
.size() == 1) {
3143 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3145 assert(dst
.size() != 1);
3146 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3147 if (instr
->def
.bit_size
== 64)
3148 for (unsigned i
= 0; i
< dst
.size(); i
++)
3149 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3151 for (unsigned i
= 0; i
< dst
.size(); i
++)
3152 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3154 vec
->definitions
[0] = Definition(dst
);
3155 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3159 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3161 uint32_t new_mask
= 0;
3162 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3163 if (mask
& (1u << i
))
3164 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3168 struct LoadEmitInfo
{
3171 unsigned num_components
;
3172 unsigned component_size
;
3173 Temp resource
= Temp(0, s1
);
3174 unsigned component_stride
= 0;
3175 unsigned const_offset
= 0;
3176 unsigned align_mul
= 0;
3177 unsigned align_offset
= 0;
3180 unsigned swizzle_component_size
= 0;
3181 memory_sync_info sync
;
3182 Temp soffset
= Temp(0, s1
);
3185 using LoadCallback
= Temp(*)(
3186 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3187 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3189 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3190 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3192 unsigned load_size
= info
->num_components
* info
->component_size
;
3193 unsigned component_size
= info
->component_size
;
3195 unsigned num_vals
= 0;
3196 Temp vals
[info
->dst
.bytes()];
3198 unsigned const_offset
= info
->const_offset
;
3200 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3201 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3203 unsigned bytes_read
= 0;
3204 while (bytes_read
< load_size
) {
3205 unsigned bytes_needed
= load_size
- bytes_read
;
3207 /* add buffer for unaligned loads */
3208 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3211 if ((bytes_needed
> 2 ||
3212 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3213 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3214 if (info
->component_stride
) {
3215 assert(supports_8bit_16bit_loads
&& "unimplemented");
3219 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3220 bytes_needed
= align(bytes_needed
, 4);
3227 if (info
->swizzle_component_size
)
3228 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3229 if (info
->component_stride
)
3230 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3232 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3234 /* reduce constant offset */
3235 Operand offset
= info
->offset
;
3236 unsigned reduced_const_offset
= const_offset
;
3237 bool remove_const_offset_completely
= need_to_align_offset
;
3238 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3239 unsigned to_add
= const_offset
;
3240 if (remove_const_offset_completely
) {
3241 reduced_const_offset
= 0;
3243 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3244 reduced_const_offset
%= max_const_offset_plus_one
;
3246 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3247 if (offset
.isConstant()) {
3248 offset
= Operand(offset
.constantValue() + to_add
);
3249 } else if (offset_tmp
.regClass() == s1
) {
3250 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3251 offset_tmp
, Operand(to_add
));
3252 } else if (offset_tmp
.regClass() == v1
) {
3253 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3255 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3256 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3257 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3259 if (offset_tmp
.regClass() == s2
) {
3260 Temp carry
= bld
.tmp(s1
);
3261 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3262 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3263 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3265 Temp new_lo
= bld
.tmp(v1
);
3266 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3267 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3268 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3273 /* align offset down if needed */
3274 Operand aligned_offset
= offset
;
3275 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3276 if (need_to_align_offset
) {
3278 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3279 if (offset
.isConstant()) {
3280 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3281 } else if (offset_tmp
.regClass() == s1
) {
3282 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3283 } else if (offset_tmp
.regClass() == s2
) {
3284 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3285 } else if (offset_tmp
.regClass() == v1
) {
3286 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3287 } else if (offset_tmp
.regClass() == v2
) {
3288 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3289 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3290 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3291 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3294 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3295 bld
.copy(bld
.def(s1
), aligned_offset
);
3297 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3298 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3300 /* the callback wrote directly to dst */
3301 if (val
== info
->dst
) {
3302 assert(num_vals
== 0);
3303 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3307 /* shift result right if needed */
3308 if (info
->component_size
< 4 && byte_align_loads
) {
3309 Operand
align((uint32_t)byte_align
);
3310 if (byte_align
== -1) {
3311 if (offset
.isConstant())
3312 align
= Operand(offset
.constantValue() % 4u);
3313 else if (offset
.size() == 2)
3314 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3319 assert(val
.bytes() >= load_size
&& "unimplemented");
3320 if (val
.type() == RegType::sgpr
)
3321 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3323 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3327 /* add result to list and advance */
3328 if (info
->component_stride
) {
3329 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3330 const_offset
+= info
->component_stride
;
3331 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3333 const_offset
+= val
.bytes();
3334 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3336 bytes_read
+= val
.bytes();
3337 vals
[num_vals
++] = val
;
3340 /* create array of components */
3341 unsigned components_split
= 0;
3342 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3343 bool has_vgprs
= false;
3344 for (unsigned i
= 0; i
< num_vals
;) {
3346 unsigned num_tmps
= 0;
3347 unsigned tmp_size
= 0;
3348 RegType reg_type
= RegType::sgpr
;
3349 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3350 if (vals
[i
].type() == RegType::vgpr
)
3351 reg_type
= RegType::vgpr
;
3352 tmp_size
+= vals
[i
].bytes();
3353 tmp
[num_tmps
++] = vals
[i
++];
3356 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3357 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3358 for (unsigned i
= 0; i
< num_tmps
; i
++)
3359 vec
->operands
[i
] = Operand(tmp
[i
]);
3360 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3361 vec
->definitions
[0] = Definition(tmp
[0]);
3362 bld
.insert(std::move(vec
));
3365 if (tmp
[0].bytes() % component_size
) {
3367 assert(i
== num_vals
);
3368 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3369 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3372 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3374 unsigned start
= components_split
;
3376 if (tmp_size
== elem_rc
.bytes()) {
3377 allocated_vec
[components_split
++] = tmp
[0];
3379 assert(tmp_size
% elem_rc
.bytes() == 0);
3380 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3381 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3382 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3383 Temp component
= bld
.tmp(elem_rc
);
3384 allocated_vec
[components_split
++] = component
;
3385 split
->definitions
[i
] = Definition(component
);
3387 split
->operands
[0] = Operand(tmp
[0]);
3388 bld
.insert(std::move(split
));
3391 /* try to p_as_uniform early so we can create more optimizable code and
3392 * also update allocated_vec */
3393 for (unsigned j
= start
; j
< components_split
; j
++) {
3394 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3395 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3396 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3400 /* concatenate components and p_as_uniform() result if needed */
3401 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3402 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3404 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3406 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3407 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3408 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3409 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3411 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3412 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3413 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3414 vec
->definitions
[0] = Definition(tmp
);
3415 bld
.insert(std::move(vec
));
3416 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3418 vec
->definitions
[0] = Definition(info
->dst
);
3419 bld
.insert(std::move(vec
));
3423 Operand
load_lds_size_m0(Builder
& bld
)
3425 /* TODO: m0 does not need to be initialized on GFX9+ */
3426 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3429 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3430 Temp offset
, unsigned bytes_needed
,
3431 unsigned align
, unsigned const_offset
,
3434 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3436 Operand m
= load_lds_size_m0(bld
);
3438 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3439 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3444 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3445 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3447 op
= aco_opcode::ds_read_b128
;
3448 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3451 op
= aco_opcode::ds_read2_b64
;
3452 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3454 op
= aco_opcode::ds_read_b96
;
3455 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3457 op
= aco_opcode::ds_read_b64
;
3458 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3461 op
= aco_opcode::ds_read2_b32
;
3462 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3464 op
= aco_opcode::ds_read_b32
;
3465 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3467 op
= aco_opcode::ds_read_u16
;
3470 op
= aco_opcode::ds_read_u8
;
3473 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3474 if (const_offset
>= max_offset_plus_one
) {
3475 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3476 const_offset
%= max_offset_plus_one
;
3480 const_offset
/= (size
/ 2u);
3482 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3483 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3486 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3488 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3489 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3492 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3497 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3499 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3500 Temp offset
, unsigned bytes_needed
,
3501 unsigned align
, unsigned const_offset
,
3506 if (bytes_needed
<= 4) {
3508 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3509 } else if (bytes_needed
<= 8) {
3511 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3512 } else if (bytes_needed
<= 16) {
3514 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3515 } else if (bytes_needed
<= 32) {
3517 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3520 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3522 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3523 if (info
->resource
.id()) {
3524 load
->operands
[0] = Operand(info
->resource
);
3525 load
->operands
[1] = Operand(offset
);
3527 load
->operands
[0] = Operand(offset
);
3528 load
->operands
[1] = Operand(0u);
3530 RegClass
rc(RegType::sgpr
, size
);
3531 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3532 load
->definitions
[0] = Definition(val
);
3533 load
->glc
= info
->glc
;
3534 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3535 load
->sync
= info
->sync
;
3536 bld
.insert(std::move(load
));
3540 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3542 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3543 Temp offset
, unsigned bytes_needed
,
3544 unsigned align_
, unsigned const_offset
,
3547 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3548 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3550 if (info
->soffset
.id()) {
3551 if (soffset
.isTemp())
3552 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3553 soffset
= Operand(info
->soffset
);
3556 unsigned bytes_size
= 0;
3558 if (bytes_needed
== 1 || align_
% 2) {
3560 op
= aco_opcode::buffer_load_ubyte
;
3561 } else if (bytes_needed
== 2 || align_
% 4) {
3563 op
= aco_opcode::buffer_load_ushort
;
3564 } else if (bytes_needed
<= 4) {
3566 op
= aco_opcode::buffer_load_dword
;
3567 } else if (bytes_needed
<= 8) {
3569 op
= aco_opcode::buffer_load_dwordx2
;
3570 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3572 op
= aco_opcode::buffer_load_dwordx3
;
3575 op
= aco_opcode::buffer_load_dwordx4
;
3577 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3578 mubuf
->operands
[0] = Operand(info
->resource
);
3579 mubuf
->operands
[1] = vaddr
;
3580 mubuf
->operands
[2] = soffset
;
3581 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3582 mubuf
->glc
= info
->glc
;
3583 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3584 mubuf
->sync
= info
->sync
;
3585 mubuf
->offset
= const_offset
;
3586 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3587 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3588 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3589 mubuf
->definitions
[0] = Definition(val
);
3590 bld
.insert(std::move(mubuf
));
3595 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3596 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3598 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3600 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3601 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3603 if (addr
.type() == RegType::vgpr
)
3604 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3605 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3608 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3609 Temp offset
, unsigned bytes_needed
,
3610 unsigned align_
, unsigned const_offset
,
3613 unsigned bytes_size
= 0;
3614 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3615 bool global
= bld
.program
->chip_class
>= GFX9
;
3617 if (bytes_needed
== 1) {
3619 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3620 } else if (bytes_needed
== 2) {
3622 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3623 } else if (bytes_needed
<= 4) {
3625 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3626 } else if (bytes_needed
<= 8) {
3628 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3629 } else if (bytes_needed
<= 12 && !mubuf
) {
3631 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3634 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3636 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3637 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3639 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3640 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3641 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3642 mubuf
->operands
[2] = Operand(0u);
3643 mubuf
->glc
= info
->glc
;
3646 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3647 mubuf
->disable_wqm
= false;
3648 mubuf
->sync
= info
->sync
;
3649 mubuf
->definitions
[0] = Definition(val
);
3650 bld
.insert(std::move(mubuf
));
3652 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3654 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3655 flat
->operands
[0] = Operand(offset
);
3656 flat
->operands
[1] = Operand(s1
);
3657 flat
->glc
= info
->glc
;
3658 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3659 flat
->sync
= info
->sync
;
3661 flat
->definitions
[0] = Definition(val
);
3662 bld
.insert(std::move(flat
));
3668 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3670 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3671 Temp address
, unsigned base_offset
, unsigned align
)
3673 assert(util_is_power_of_two_nonzero(align
));
3675 Builder
bld(ctx
->program
, ctx
->block
);
3677 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3678 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3679 info
.align_mul
= align
;
3680 info
.align_offset
= 0;
3681 info
.sync
= memory_sync_info(storage_shared
);
3682 info
.const_offset
= base_offset
;
3683 emit_lds_load(ctx
, bld
, &info
);
3688 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3693 Builder
bld(ctx
->program
, ctx
->block
);
3695 ASSERTED
bool is_subdword
= false;
3696 for (unsigned i
= 0; i
< count
; i
++)
3697 is_subdword
|= offsets
[i
] % 4;
3698 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3699 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3701 /* count == 1 fast path */
3703 if (dst_type
== RegType::sgpr
)
3704 dst
[0] = bld
.as_uniform(src
);
3706 dst
[0] = as_vgpr(ctx
, src
);
3710 for (unsigned i
= 0; i
< count
- 1; i
++)
3711 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3712 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3714 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3715 src
= as_vgpr(ctx
, src
);
3717 /* use allocated_vec if possible */
3718 auto it
= ctx
->allocated_vec
.find(src
.id());
3719 if (it
!= ctx
->allocated_vec
.end()) {
3720 if (!it
->second
[0].id())
3722 unsigned elem_size
= it
->second
[0].bytes();
3723 assert(src
.bytes() % elem_size
== 0);
3725 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3726 if (!it
->second
[i
].id())
3730 for (unsigned i
= 0; i
< count
; i
++) {
3731 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3735 for (unsigned i
= 0; i
< count
; i
++) {
3736 unsigned start_idx
= offsets
[i
] / elem_size
;
3737 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3738 if (op_count
== 1) {
3739 if (dst_type
== RegType::sgpr
)
3740 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3742 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3746 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3747 for (unsigned j
= 0; j
< op_count
; j
++) {
3748 Temp tmp
= it
->second
[start_idx
+ j
];
3749 if (dst_type
== RegType::sgpr
)
3750 tmp
= bld
.as_uniform(tmp
);
3751 vec
->operands
[j
] = Operand(tmp
);
3753 vec
->definitions
[0] = Definition(dst
[i
]);
3754 bld
.insert(std::move(vec
));
3762 if (dst_type
== RegType::sgpr
)
3763 src
= bld
.as_uniform(src
);
3766 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3767 split
->operands
[0] = Operand(src
);
3768 for (unsigned i
= 0; i
< count
; i
++)
3769 split
->definitions
[i
] = Definition(dst
[i
]);
3770 bld
.insert(std::move(split
));
3773 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3774 int *start
, int *count
)
3776 unsigned start_elem
= ffs(todo_mask
) - 1;
3777 bool skip
= !(mask
& (1 << start_elem
));
3779 mask
= ~mask
& todo_mask
;
3783 u_bit_scan_consecutive_range(&mask
, start
, count
);
3788 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3790 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3793 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3794 Temp address
, unsigned base_offset
, unsigned align
)
3796 assert(util_is_power_of_two_nonzero(align
));
3797 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3799 Builder
bld(ctx
->program
, ctx
->block
);
3800 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3801 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3803 unsigned write_count
= 0;
3804 Temp write_datas
[32];
3805 unsigned offsets
[32];
3806 aco_opcode opcodes
[32];
3808 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3810 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3813 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3814 offsets
[write_count
] = offset
;
3815 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3817 advance_write_mask(&todo
, offset
, bytes
);
3821 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3822 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3823 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3824 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3826 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3827 aco_opcode op
= aco_opcode::num_opcodes
;
3828 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3829 op
= aco_opcode::ds_write_b128
;
3831 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3832 op
= aco_opcode::ds_write_b96
;
3834 } else if (bytes
>= 8 && aligned8
) {
3835 op
= aco_opcode::ds_write_b64
;
3837 } else if (bytes
>= 4 && aligned4
) {
3838 op
= aco_opcode::ds_write_b32
;
3840 } else if (bytes
>= 2 && aligned2
) {
3841 op
= aco_opcode::ds_write_b16
;
3843 } else if (bytes
>= 1) {
3844 op
= aco_opcode::ds_write_b8
;
3850 offsets
[write_count
] = offset
;
3851 opcodes
[write_count
] = op
;
3853 advance_write_mask(&todo
, offset
, bytes
);
3856 Operand m
= load_lds_size_m0(bld
);
3858 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3860 for (unsigned i
= 0; i
< write_count
; i
++) {
3861 aco_opcode op
= opcodes
[i
];
3862 if (op
== aco_opcode::num_opcodes
)
3865 Temp data
= write_datas
[i
];
3867 unsigned second
= write_count
;
3868 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3869 for (second
= i
+ 1; second
< write_count
; second
++) {
3870 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3871 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3872 opcodes
[second
] = aco_opcode::num_opcodes
;
3878 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3879 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3881 unsigned inline_offset
= base_offset
+ offsets
[i
];
3882 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3883 Temp address_offset
= address
;
3884 if (inline_offset
> max_offset
) {
3885 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3886 inline_offset
= offsets
[i
];
3888 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3892 Temp second_data
= write_datas
[second
];
3893 inline_offset
/= data
.bytes();
3894 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3896 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3898 static_cast<DS_instruction
*>(instr
)->sync
=
3899 memory_sync_info(storage_shared
);
3903 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3905 unsigned align
= 16;
3907 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3913 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3918 return aco_opcode::buffer_store_byte
;
3921 return aco_opcode::buffer_store_short
;
3923 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3925 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3928 return aco_opcode::buffer_store_dwordx3
;
3930 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3932 unreachable("Unexpected store size");
3933 return aco_opcode::num_opcodes
;
3936 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3937 Temp data
, unsigned writemask
, int swizzle_element_size
,
3938 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3940 unsigned write_count_with_skips
= 0;
3943 /* determine how to split the data */
3944 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3947 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3948 offsets
[write_count_with_skips
] = offset
;
3949 if (skips
[write_count_with_skips
]) {
3950 advance_write_mask(&todo
, offset
, bytes
);
3951 write_count_with_skips
++;
3955 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3956 * larger than swizzle_element_size */
3957 bytes
= MIN2(bytes
, swizzle_element_size
);
3959 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3961 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3962 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3965 /* dword or larger stores have to be dword-aligned */
3966 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3967 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3968 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3970 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3972 advance_write_mask(&todo
, offset
, bytes
);
3973 write_count_with_skips
++;
3976 /* actually split data */
3977 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3980 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3983 write_datas
[*write_count
] = write_datas
[i
];
3984 offsets
[*write_count
] = offsets
[i
];
3989 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3990 unsigned split_cnt
= 0u, Temp dst
= Temp())
3992 Builder
bld(ctx
->program
, ctx
->block
);
3993 unsigned dword_size
= elem_size_bytes
/ 4;
3996 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3998 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3999 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
4000 instr
->definitions
[0] = Definition(dst
);
4002 for (unsigned i
= 0; i
< cnt
; ++i
) {
4004 assert(arr
[i
].size() == dword_size
);
4005 allocated_vec
[i
] = arr
[i
];
4006 instr
->operands
[i
] = Operand(arr
[i
]);
4008 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
4009 allocated_vec
[i
] = zero
;
4010 instr
->operands
[i
] = Operand(zero
);
4014 bld
.insert(std::move(instr
));
4017 emit_split_vector(ctx
, dst
, split_cnt
);
4019 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
4024 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
4026 if (const_offset
>= 4096) {
4027 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
4028 const_offset
%= 4096u;
4031 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
4032 else if (unlikely(voffset
.regClass() == s1
))
4033 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
4034 else if (likely(voffset
.regClass() == v1
))
4035 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
4037 unreachable("Unsupported register class of voffset");
4040 return const_offset
;
4043 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
4044 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
4045 bool slc
= false, bool swizzled
= false)
4048 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
4049 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
4051 Builder
bld(ctx
->program
, ctx
->block
);
4052 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
4053 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
4055 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
4056 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
4057 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
4058 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
4059 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
4060 /* dlc*/ false, /* slc */ slc
);
4062 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
4065 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
4066 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
4067 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
4069 Builder
bld(ctx
->program
, ctx
->block
);
4070 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4072 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
4074 unsigned write_count
= 0;
4075 Temp write_datas
[32];
4076 unsigned offsets
[32];
4077 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
4078 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
4080 for (unsigned i
= 0; i
< write_count
; i
++) {
4081 unsigned const_offset
= offsets
[i
] + base_const_offset
;
4082 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
4086 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
4087 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
4088 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
4090 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
4091 assert((num_components
* elem_size_bytes
) == dst
.bytes());
4092 assert(!!stride
!= allow_combining
);
4094 Builder
bld(ctx
->program
, ctx
->block
);
4096 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
4097 info
.component_stride
= allow_combining
? 0 : stride
;
4099 info
.swizzle_component_size
= allow_combining
? 0 : 4;
4100 info
.align_mul
= MIN2(elem_size_bytes
, 4);
4101 info
.align_offset
= 0;
4102 info
.soffset
= soffset
;
4103 info
.const_offset
= base_const_offset
;
4104 emit_mubuf_load(ctx
, bld
, &info
);
4107 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4109 Builder
bld(ctx
->program
, ctx
->block
);
4110 Temp offset
= base_offset
.first
;
4111 unsigned const_offset
= base_offset
.second
;
4113 if (!nir_src_is_const(*off_src
)) {
4114 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4117 /* Calculate indirect offset with stride */
4118 if (likely(indirect_offset_arg
.regClass() == v1
))
4119 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4120 else if (indirect_offset_arg
.regClass() == s1
)
4121 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4123 unreachable("Unsupported register class of indirect offset");
4125 /* Add to the supplied base offset */
4126 if (offset
.id() == 0)
4127 offset
= with_stride
;
4128 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4129 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4130 else if (offset
.size() == 1 && with_stride
.size() == 1)
4131 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4133 unreachable("Unsupported register class of indirect offset");
4135 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4136 const_offset
+= const_offset_arg
* stride
;
4139 return std::make_pair(offset
, const_offset
);
4142 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4144 Builder
bld(ctx
->program
, ctx
->block
);
4147 if (off1
.first
.id() && off2
.first
.id()) {
4148 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4149 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4150 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4151 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4153 unreachable("Unsupported register class of indirect offset");
4155 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4158 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4161 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4163 Builder
bld(ctx
->program
, ctx
->block
);
4164 unsigned const_offset
= offs
.second
* multiplier
;
4166 if (!offs
.first
.id())
4167 return std::make_pair(offs
.first
, const_offset
);
4169 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4170 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4171 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4173 return std::make_pair(offset
, const_offset
);
4176 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4178 Builder
bld(ctx
->program
, ctx
->block
);
4180 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4181 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4182 /* component is in bytes */
4183 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4185 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4186 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4187 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4190 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4192 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4195 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4197 Builder
bld(ctx
->program
, ctx
->block
);
4199 switch (ctx
->shader
->info
.stage
) {
4200 case MESA_SHADER_TESS_CTRL
:
4201 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4202 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4203 case MESA_SHADER_TESS_EVAL
:
4204 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4206 unreachable("Unsupported stage in get_tess_rel_patch_id");
4210 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4212 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4213 Builder
bld(ctx
->program
, ctx
->block
);
4215 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4216 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4218 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4220 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4221 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4223 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4224 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4225 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4227 return offset_mul(ctx
, offs
, 4u);
4230 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4232 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4233 Builder
bld(ctx
->program
, ctx
->block
);
4235 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4236 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4237 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4238 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4240 std::pair
<Temp
, unsigned> offs
= instr
4241 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4242 : std::make_pair(Temp(), 0u);
4244 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4245 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4250 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4251 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4253 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4254 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4256 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4257 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4263 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4265 Builder
bld(ctx
->program
, ctx
->block
);
4267 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4268 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4270 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4272 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4273 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4274 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4276 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4277 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4282 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4284 Builder
bld(ctx
->program
, ctx
->block
);
4286 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4287 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4288 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4289 unsigned attr_stride
= ctx
->tcs_num_patches
;
4291 std::pair
<Temp
, unsigned> offs
= instr
4292 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4293 : std::make_pair(Temp(), 0u);
4295 if (const_base_offset
)
4296 offs
.second
+= const_base_offset
* attr_stride
;
4298 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4299 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4300 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4305 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4307 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4312 unsigned drv_loc
= nir_intrinsic_base(instr
);
4313 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4315 if (!nir_src_is_const(*off_src
)) {
4321 uint64_t slot
= per_vertex
4322 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4323 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4324 return (((uint64_t) 1) << slot
) & mask
;
4327 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4329 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4330 unsigned component
= nir_intrinsic_component(instr
);
4331 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4333 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4334 if (off_instr
->type
!= nir_instr_type_load_const
)
4337 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4338 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4340 if (instr
->src
[0].ssa
->bit_size
== 64)
4341 write_mask
= widen_mask(write_mask
, 2);
4343 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4345 for (unsigned i
= 0; i
< 8; ++i
) {
4346 if (write_mask
& (1 << i
)) {
4347 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4348 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4356 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4358 /* Only TCS per-vertex inputs are supported by this function.
4359 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4361 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4364 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4365 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4366 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4367 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4368 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4369 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4374 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4375 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4376 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4381 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4383 Builder
bld(ctx
->program
, ctx
->block
);
4385 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4386 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4387 bool indirect_write
;
4388 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4389 if (temp_only_input
&& !indirect_write
)
4393 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4394 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4395 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4396 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4398 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4399 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4400 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4401 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4402 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4406 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4407 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4408 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4409 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4410 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4411 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4412 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4413 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4414 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4415 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4416 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4417 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4418 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4420 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4421 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4423 unreachable("Invalid LS or ES stage");
4426 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4427 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4428 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4432 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4437 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4438 return off
== ctx
->tcs_tess_lvl_out_loc
||
4439 off
== ctx
->tcs_tess_lvl_in_loc
;
4443 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4445 uint64_t mask
= per_vertex
4446 ? ctx
->program
->info
->tcs
.tes_inputs_read
4447 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4449 bool indirect_write
= false;
4450 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4451 return indirect_write
|| output_read_by_tes
;
4454 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4456 uint64_t mask
= per_vertex
4457 ? ctx
->shader
->info
.outputs_read
4458 : ctx
->shader
->info
.patch_outputs_read
;
4460 bool indirect_write
= false;
4461 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4462 return indirect_write
|| output_read
;
4465 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4467 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4468 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4470 Builder
bld(ctx
->program
, ctx
->block
);
4472 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4473 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4474 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4476 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4477 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4478 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4480 if (write_to_vmem
) {
4481 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4482 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4483 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4485 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4486 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4487 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4491 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4492 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4493 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4497 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4499 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4500 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4502 Builder
bld(ctx
->program
, ctx
->block
);
4504 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4505 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4506 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4507 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4509 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4512 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4514 if (ctx
->stage
== vertex_vs
||
4515 ctx
->stage
== tess_eval_vs
||
4516 ctx
->stage
== fragment_fs
||
4517 ctx
->stage
== ngg_vertex_gs
||
4518 ctx
->stage
== ngg_tess_eval_gs
||
4519 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4520 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4521 if (!stored_to_temps
) {
4522 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4523 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4524 fprintf(stderr
, "\n");
4527 } else if (ctx
->stage
== vertex_es
||
4528 ctx
->stage
== vertex_ls
||
4529 ctx
->stage
== tess_eval_es
||
4530 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4531 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4532 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4533 visit_store_ls_or_es_output(ctx
, instr
);
4534 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4535 visit_store_tcs_output(ctx
, instr
, false);
4537 unreachable("Shader stage not implemented");
4541 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4543 visit_load_tcs_output(ctx
, instr
, false);
4546 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4548 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4549 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4551 Builder
bld(ctx
->program
, ctx
->block
);
4553 if (dst
.regClass() == v2b
) {
4554 if (ctx
->program
->has_16bank_lds
) {
4555 assert(ctx
->options
->chip_class
<= GFX8
);
4556 Builder::Result interp_p1
=
4557 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4558 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4559 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4560 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4561 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4562 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4564 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4566 if (ctx
->options
->chip_class
== GFX8
)
4567 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4569 Builder::Result interp_p1
=
4570 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4571 coord1
, bld
.m0(prim_mask
), idx
, component
);
4572 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4573 interp_p1
, idx
, component
);
4576 Builder::Result interp_p1
=
4577 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4578 bld
.m0(prim_mask
), idx
, component
);
4580 if (ctx
->program
->has_16bank_lds
)
4581 interp_p1
.instr
->operands
[0].setLateKill(true);
4583 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4584 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4588 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4590 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4591 for (unsigned i
= 0; i
< num_components
; i
++)
4592 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4593 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4594 assert(num_components
== 4);
4595 Builder
bld(ctx
->program
, ctx
->block
);
4596 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4599 for (Operand
& op
: vec
->operands
)
4600 op
= op
.isUndefined() ? Operand(0u) : op
;
4602 vec
->definitions
[0] = Definition(dst
);
4603 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4604 emit_split_vector(ctx
, dst
, num_components
);
4608 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4610 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4611 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4612 unsigned idx
= nir_intrinsic_base(instr
);
4613 unsigned component
= nir_intrinsic_component(instr
);
4614 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4616 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4618 assert(offset
->u32
== 0);
4620 /* the lower 15bit of the prim_mask contain the offset into LDS
4621 * while the upper bits contain the number of prims */
4622 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4623 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4624 Builder
bld(ctx
->program
, ctx
->block
);
4625 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4626 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4627 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4628 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4629 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4632 if (instr
->dest
.ssa
.num_components
== 1) {
4633 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4635 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4636 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4638 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4639 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4640 vec
->operands
[i
] = Operand(tmp
);
4642 vec
->definitions
[0] = Definition(dst
);
4643 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4647 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4648 unsigned offset
, unsigned stride
, unsigned channels
)
4650 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4651 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4653 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4654 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4657 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4658 unsigned offset
, unsigned stride
, unsigned *channels
)
4660 if (!vtx_info
->chan_byte_size
) {
4661 *channels
= vtx_info
->num_channels
;
4662 return vtx_info
->chan_format
;
4665 unsigned num_channels
= *channels
;
4666 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4667 unsigned new_channels
= num_channels
+ 1;
4668 /* first, assume more loads is worse and try using a larger data format */
4669 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4671 /* don't make the attribute potentially out-of-bounds */
4672 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4676 if (new_channels
== 5) {
4677 /* then try decreasing load size (at the cost of more loads) */
4678 new_channels
= *channels
;
4679 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4683 if (new_channels
< *channels
)
4684 *channels
= new_channels
;
4685 num_channels
= new_channels
;
4688 switch (vtx_info
->chan_format
) {
4689 case V_008F0C_BUF_DATA_FORMAT_8
:
4690 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4691 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4692 case V_008F0C_BUF_DATA_FORMAT_16
:
4693 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4694 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4695 case V_008F0C_BUF_DATA_FORMAT_32
:
4696 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4697 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4699 unreachable("shouldn't reach here");
4700 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4703 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4704 * so we may need to fix it up. */
4705 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4707 Builder
bld(ctx
->program
, ctx
->block
);
4709 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4710 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4712 /* For the integer-like cases, do a natural sign extension.
4714 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4715 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4718 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4719 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4721 /* Convert back to the right type. */
4722 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4723 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4724 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4725 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4726 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4727 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4733 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4735 Builder
bld(ctx
->program
, ctx
->block
);
4736 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4737 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4739 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4740 if (off_instr
->type
!= nir_instr_type_load_const
) {
4741 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4742 nir_print_instr(off_instr
, stderr
);
4743 fprintf(stderr
, "\n");
4745 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4747 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4749 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4750 unsigned component
= nir_intrinsic_component(instr
);
4751 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4752 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4753 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4754 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4755 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4757 unsigned dfmt
= attrib_format
& 0xf;
4758 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4759 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4761 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4762 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4763 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4764 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4766 num_channels
= MAX2(num_channels
, 3);
4768 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4769 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4772 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4773 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4774 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4776 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4778 Temp divided
= bld
.tmp(v1
);
4779 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4780 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4782 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4785 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4788 index
= bld
.vadd32(bld
.def(v1
),
4789 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4790 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4793 Temp channels
[num_channels
];
4794 unsigned channel_start
= 0;
4795 bool direct_fetch
= false;
4797 /* skip unused channels at the start */
4798 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4799 channel_start
= ffs(mask
) - 1;
4800 for (unsigned i
= 0; i
< channel_start
; i
++)
4801 channels
[i
] = Temp(0, s1
);
4802 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4803 num_channels
= 3 - (ffs(mask
) - 1);
4807 while (channel_start
< num_channels
) {
4808 unsigned fetch_component
= num_channels
- channel_start
;
4809 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4810 bool expanded
= false;
4812 /* use MUBUF when possible to avoid possible alignment issues */
4813 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4814 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4815 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4816 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4817 vtx_info
->chan_byte_size
== 4;
4818 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4820 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4822 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4823 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4824 fetch_component
= 4;
4829 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4831 Temp fetch_index
= index
;
4832 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4833 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4834 fetch_offset
= fetch_offset
% attrib_stride
;
4837 Operand
soffset(0u);
4838 if (fetch_offset
>= 4096) {
4839 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4840 fetch_offset
%= 4096;
4844 switch (fetch_bytes
) {
4846 assert(!use_mubuf
&& bitsize
== 16);
4847 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4850 if (bitsize
== 16) {
4852 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4854 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4858 assert(!use_mubuf
&& bitsize
== 16);
4859 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4862 if (bitsize
== 16) {
4864 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4866 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4870 assert(ctx
->options
->chip_class
>= GFX7
||
4871 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4872 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4875 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4878 unreachable("Unimplemented load_input vector size");
4882 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4883 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4884 num_channels
<= 3)) {
4885 direct_fetch
= true;
4888 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4893 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4894 fetch_offset
, false, false, true).instr
;
4897 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4898 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4901 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4903 if (fetch_component
== 1) {
4904 channels
[channel_start
] = fetch_dst
;
4906 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4907 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4908 bitsize
== 16 ? v2b
: v1
);
4911 channel_start
+= fetch_component
;
4914 if (!direct_fetch
) {
4915 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4916 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4918 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4919 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4920 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4922 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4923 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4924 unsigned num_temp
= 0;
4925 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4926 unsigned idx
= i
+ component
;
4927 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4928 Temp channel
= channels
[swizzle
[idx
]];
4929 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4930 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4931 vec
->operands
[i
] = Operand(channel
);
4935 } else if (is_float
&& idx
== 3) {
4936 vec
->operands
[i
] = Operand(0x3f800000u
);
4937 } else if (!is_float
&& idx
== 3) {
4938 vec
->operands
[i
] = Operand(1u);
4940 vec
->operands
[i
] = Operand(0u);
4943 vec
->definitions
[0] = Definition(dst
);
4944 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4945 emit_split_vector(ctx
, dst
, dst
.size());
4947 if (num_temp
== dst
.size())
4948 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4950 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4951 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4952 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4953 if (off_instr
->type
!= nir_instr_type_load_const
||
4954 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4955 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4956 nir_print_instr(off_instr
, stderr
);
4957 fprintf(stderr
, "\n");
4960 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4961 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4963 assert(offset
->u32
== 0);
4965 /* the lower 15bit of the prim_mask contain the offset into LDS
4966 * while the upper bits contain the number of prims */
4967 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4968 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4969 Builder
bld(ctx
->program
, ctx
->block
);
4970 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4971 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4972 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4973 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4974 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4977 unsigned idx
= nir_intrinsic_base(instr
);
4978 unsigned component
= nir_intrinsic_component(instr
);
4979 unsigned vertex_id
= 2; /* P0 */
4981 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4982 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4983 switch (src0
->u32
) {
4985 vertex_id
= 2; /* P0 */
4988 vertex_id
= 0; /* P10 */
4991 vertex_id
= 1; /* P20 */
4994 unreachable("invalid vertex index");
4998 if (dst
.size() == 1) {
4999 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
5001 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
5002 for (unsigned i
= 0; i
< dst
.size(); i
++)
5003 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
5004 vec
->definitions
[0] = Definition(dst
);
5005 bld
.insert(std::move(vec
));
5008 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
5009 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5010 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
5011 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
5012 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
5014 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
5016 unreachable("Shader stage not implemented");
5020 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
5022 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5024 Builder
bld(ctx
->program
, ctx
->block
);
5025 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
5028 if (!nir_src_is_const(*vertex_src
)) {
5029 /* better code could be created, but this case probably doesn't happen
5030 * much in practice */
5031 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
5032 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
5035 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5036 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
5038 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
5040 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
5043 if (vertex_offset
.id()) {
5044 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
5045 Operand(i
), indirect_vertex
);
5046 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
5048 vertex_offset
= elem
;
5052 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5053 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
5055 unsigned vertex
= nir_src_as_uint(*vertex_src
);
5056 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
5057 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5058 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
5059 Operand((vertex
% 2u) * 16u), Operand(16u));
5061 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
5064 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
5065 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
5066 return offset_mul(ctx
, offs
, 4u);
5069 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5071 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
5073 Builder
bld(ctx
->program
, ctx
->block
);
5074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5075 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5077 if (ctx
->stage
== geometry_gs
) {
5078 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
5079 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
5080 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
5081 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
5082 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
5083 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5084 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5086 unreachable("Unsupported GS stage.");
5090 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5092 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5094 Builder
bld(ctx
->program
, ctx
->block
);
5095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5097 if (load_input_from_temps(ctx
, instr
, dst
))
5100 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5101 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5102 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5104 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5107 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5109 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5111 Builder
bld(ctx
->program
, ctx
->block
);
5113 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5114 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5115 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5117 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5118 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5120 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5123 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5125 switch (ctx
->shader
->info
.stage
) {
5126 case MESA_SHADER_GEOMETRY
:
5127 visit_load_gs_per_vertex_input(ctx
, instr
);
5129 case MESA_SHADER_TESS_CTRL
:
5130 visit_load_tcs_per_vertex_input(ctx
, instr
);
5132 case MESA_SHADER_TESS_EVAL
:
5133 visit_load_tes_per_vertex_input(ctx
, instr
);
5136 unreachable("Unimplemented shader stage");
5140 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5142 visit_load_tcs_output(ctx
, instr
, true);
5145 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5147 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5148 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5150 visit_store_tcs_output(ctx
, instr
, true);
5153 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5155 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5157 Builder
bld(ctx
->program
, ctx
->block
);
5158 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5160 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5161 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5164 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5165 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5166 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5167 tes_w
= Operand(tmp
);
5170 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5171 emit_split_vector(ctx
, tess_coord
, 3);
5174 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5176 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5177 Builder
bld(ctx
->program
, ctx
->block
);
5178 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5179 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5180 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5183 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5187 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5189 Builder
bld(ctx
->program
, ctx
->block
);
5190 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5191 if (!nir_dest_is_divergent(instr
->dest
))
5192 index
= bld
.as_uniform(index
);
5193 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5194 unsigned binding
= nir_intrinsic_binding(instr
);
5197 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5198 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5199 unsigned offset
= layout
->binding
[binding
].offset
;
5201 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5202 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5203 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5204 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5205 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5208 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5209 stride
= layout
->binding
[binding
].size
;
5212 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5213 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5215 if (nir_const_index
) {
5216 const_index
= const_index
* stride
;
5217 } else if (index
.type() == RegType::vgpr
) {
5218 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5219 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5221 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5225 if (nir_const_index
) {
5226 const_index
= const_index
+ offset
;
5227 } else if (index
.type() == RegType::vgpr
) {
5228 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5230 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5234 if (nir_const_index
&& const_index
== 0) {
5236 } else if (index
.type() == RegType::vgpr
) {
5237 index
= bld
.vadd32(bld
.def(v1
),
5238 nir_const_index
? Operand(const_index
) : Operand(index
),
5241 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5242 nir_const_index
? Operand(const_index
) : Operand(index
),
5246 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5249 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5250 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5251 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5253 Builder
bld(ctx
->program
, ctx
->block
);
5255 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5257 offset
= bld
.as_uniform(offset
);
5259 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5262 info
.align_mul
= align_mul
;
5263 info
.align_offset
= align_offset
;
5265 emit_smem_load(ctx
, bld
, &info
);
5267 emit_mubuf_load(ctx
, bld
, &info
);
5270 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5272 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5273 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5275 Builder
bld(ctx
->program
, ctx
->block
);
5277 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5278 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5279 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5280 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5282 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5283 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5287 if (ctx
->options
->chip_class
>= GFX10
) {
5288 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5289 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5290 S_008F0C_RESOURCE_LEVEL(1);
5292 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5293 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5295 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5296 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5297 Operand(0xFFFFFFFFu
),
5298 Operand(desc_type
));
5299 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5300 rsrc
, upper_dwords
);
5302 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5303 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5305 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5306 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5307 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5310 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5312 Builder
bld(ctx
->program
, ctx
->block
);
5313 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5314 unsigned offset
= nir_intrinsic_base(instr
);
5315 unsigned count
= instr
->dest
.ssa
.num_components
;
5316 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5318 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5319 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5320 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5321 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5322 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5323 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5324 for (unsigned i
= 0; i
< count
; ++i
) {
5325 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5326 vec
->operands
[i
] = Operand
{elems
[i
]};
5328 vec
->definitions
[0] = Definition(dst
);
5329 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5330 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5335 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5336 if (offset
!= 0) // TODO check if index != 0 as well
5337 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5338 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5341 bool aligned
= true;
5343 if (instr
->dest
.ssa
.bit_size
== 8) {
5344 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5345 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5347 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5348 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5349 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5351 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5356 switch (vec
.size()) {
5358 op
= aco_opcode::s_load_dword
;
5361 op
= aco_opcode::s_load_dwordx2
;
5367 op
= aco_opcode::s_load_dwordx4
;
5373 op
= aco_opcode::s_load_dwordx8
;
5376 unreachable("unimplemented or forbidden load_push_constant.");
5379 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5382 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5383 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5388 emit_split_vector(ctx
, vec
, 4);
5389 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5390 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5391 emit_extract_vector(ctx
, vec
, 0, rc
),
5392 emit_extract_vector(ctx
, vec
, 1, rc
),
5393 emit_extract_vector(ctx
, vec
, 2, rc
));
5396 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5399 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5401 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5403 Builder
bld(ctx
->program
, ctx
->block
);
5405 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5406 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5407 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5408 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5409 if (ctx
->options
->chip_class
>= GFX10
) {
5410 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5411 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5412 S_008F0C_RESOURCE_LEVEL(1);
5414 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5415 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5418 unsigned base
= nir_intrinsic_base(instr
);
5419 unsigned range
= nir_intrinsic_range(instr
);
5421 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5422 if (base
&& offset
.type() == RegType::sgpr
)
5423 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5424 else if (base
&& offset
.type() == RegType::vgpr
)
5425 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5427 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5428 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5429 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5430 Operand(desc_type
));
5431 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5432 // TODO: get alignment information for subdword constants
5433 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5436 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5438 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5439 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5441 ctx
->program
->needs_exact
= true;
5443 // TODO: optimize uniform conditions
5444 Builder
bld(ctx
->program
, ctx
->block
);
5445 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5446 assert(src
.regClass() == bld
.lm
);
5447 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5448 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5449 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5453 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5455 Builder
bld(ctx
->program
, ctx
->block
);
5457 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5458 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5460 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5461 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5463 if (ctx
->block
->loop_nest_depth
&&
5464 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5465 /* we handle discards the same way as jump instructions */
5466 append_logical_end(ctx
->block
);
5468 /* in loops, discard behaves like break */
5469 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5470 ctx
->block
->kind
|= block_kind_discard
;
5473 /* uniform discard - loop ends here */
5474 assert(nir_instr_is_last(&instr
->instr
));
5475 ctx
->block
->kind
|= block_kind_uniform
;
5476 ctx
->cf_info
.has_branch
= true;
5477 bld
.branch(aco_opcode::p_branch
);
5478 add_linear_edge(ctx
->block
->index
, linear_target
);
5482 /* we add a break right behind the discard() instructions */
5483 ctx
->block
->kind
|= block_kind_break
;
5484 unsigned idx
= ctx
->block
->index
;
5486 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5487 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5489 /* remove critical edges from linear CFG */
5490 bld
.branch(aco_opcode::p_branch
);
5491 Block
* break_block
= ctx
->program
->create_and_insert_block();
5492 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5493 break_block
->kind
|= block_kind_uniform
;
5494 add_linear_edge(idx
, break_block
);
5495 add_linear_edge(break_block
->index
, linear_target
);
5496 bld
.reset(break_block
);
5497 bld
.branch(aco_opcode::p_branch
);
5499 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5500 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5501 add_linear_edge(idx
, continue_block
);
5502 append_logical_start(continue_block
);
5503 ctx
->block
= continue_block
;
5508 /* it can currently happen that NIR doesn't remove the unreachable code */
5509 if (!nir_instr_is_last(&instr
->instr
)) {
5510 ctx
->program
->needs_exact
= true;
5511 /* save exec somewhere temporarily so that it doesn't get
5512 * overwritten before the discard from outer exec masks */
5513 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5514 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5515 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5519 /* This condition is incorrect for uniformly branched discards in a loop
5520 * predicated by a divergent condition, but the above code catches that case
5521 * and the discard would end up turning into a discard_if.
5531 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5532 /* program just ends here */
5533 ctx
->block
->kind
|= block_kind_uniform
;
5534 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5535 0 /* enabled mask */, 9 /* dest */,
5536 false /* compressed */, true/* done */, true /* valid mask */);
5537 bld
.sopp(aco_opcode::s_endpgm
);
5538 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5540 ctx
->block
->kind
|= block_kind_discard
;
5541 /* branch and linear edge is added by visit_if() */
5545 enum aco_descriptor_type
{
5556 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5557 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5559 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5560 return dim
== ac_image_cube
||
5561 dim
== ac_image_1darray
||
5562 dim
== ac_image_2darray
||
5563 dim
== ac_image_2darraymsaa
;
5566 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5567 enum aco_descriptor_type desc_type
,
5568 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5570 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5571 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5572 if (it != ctx->tex_desc.end())
5575 Temp index
= Temp();
5576 bool index_set
= false;
5577 unsigned constant_index
= 0;
5578 unsigned descriptor_set
;
5579 unsigned base_index
;
5580 Builder
bld(ctx
->program
, ctx
->block
);
5583 assert(tex_instr
&& !image
);
5585 base_index
= tex_instr
->sampler_index
;
5587 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5588 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5592 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5593 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5595 constant_index
+= array_size
* const_value
->u32
;
5597 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5598 if (indirect
.type() == RegType::vgpr
)
5599 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5601 if (array_size
!= 1)
5602 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5608 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5612 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5614 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5615 base_index
= deref_instr
->var
->data
.binding
;
5618 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5619 list
= convert_pointer_to_64_bit(ctx
, list
);
5621 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5622 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5623 unsigned offset
= binding
->offset
;
5624 unsigned stride
= binding
->size
;
5628 assert(base_index
< layout
->binding_count
);
5630 switch (desc_type
) {
5631 case ACO_DESC_IMAGE
:
5633 opcode
= aco_opcode::s_load_dwordx8
;
5635 case ACO_DESC_FMASK
:
5637 opcode
= aco_opcode::s_load_dwordx8
;
5640 case ACO_DESC_SAMPLER
:
5642 opcode
= aco_opcode::s_load_dwordx4
;
5643 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5644 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5646 case ACO_DESC_BUFFER
:
5648 opcode
= aco_opcode::s_load_dwordx4
;
5650 case ACO_DESC_PLANE_0
:
5651 case ACO_DESC_PLANE_1
:
5653 opcode
= aco_opcode::s_load_dwordx8
;
5654 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5656 case ACO_DESC_PLANE_2
:
5658 opcode
= aco_opcode::s_load_dwordx4
;
5662 unreachable("invalid desc_type\n");
5665 offset
+= constant_index
* stride
;
5667 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5668 (!index_set
|| binding
->immutable_samplers_equal
)) {
5669 if (binding
->immutable_samplers_equal
)
5672 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5673 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5674 Operand(samplers
[constant_index
* 4 + 0]),
5675 Operand(samplers
[constant_index
* 4 + 1]),
5676 Operand(samplers
[constant_index
* 4 + 2]),
5677 Operand(samplers
[constant_index
* 4 + 3]));
5682 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5684 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5685 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5688 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5690 if (desc_type
== ACO_DESC_PLANE_2
) {
5692 for (unsigned i
= 0; i
< 8; i
++)
5693 components
[i
] = bld
.tmp(s1
);
5694 bld
.pseudo(aco_opcode::p_split_vector
,
5695 Definition(components
[0]),
5696 Definition(components
[1]),
5697 Definition(components
[2]),
5698 Definition(components
[3]),
5701 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5702 bld
.pseudo(aco_opcode::p_split_vector
,
5703 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5704 Definition(components
[4]),
5705 Definition(components
[5]),
5706 Definition(components
[6]),
5707 Definition(components
[7]),
5710 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5711 components
[0], components
[1], components
[2], components
[3],
5712 components
[4], components
[5], components
[6], components
[7]);
5718 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5721 case GLSL_SAMPLER_DIM_BUF
:
5723 case GLSL_SAMPLER_DIM_1D
:
5724 return array
? 2 : 1;
5725 case GLSL_SAMPLER_DIM_2D
:
5726 return array
? 3 : 2;
5727 case GLSL_SAMPLER_DIM_MS
:
5728 return array
? 4 : 3;
5729 case GLSL_SAMPLER_DIM_3D
:
5730 case GLSL_SAMPLER_DIM_CUBE
:
5732 case GLSL_SAMPLER_DIM_RECT
:
5733 case GLSL_SAMPLER_DIM_SUBPASS
:
5735 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5744 /* Adjust the sample index according to FMASK.
5746 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5747 * which is the identity mapping. Each nibble says which physical sample
5748 * should be fetched to get that sample.
5750 * For example, 0x11111100 means there are only 2 samples stored and
5751 * the second sample covers 3/4 of the pixel. When reading samples 0
5752 * and 1, return physical sample 0 (determined by the first two 0s
5753 * in FMASK), otherwise return physical sample 1.
5755 * The sample index should be adjusted as follows:
5756 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5758 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5760 Builder
bld(ctx
->program
, ctx
->block
);
5761 Temp fmask
= bld
.tmp(v1
);
5762 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5763 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5766 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5767 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5768 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5769 load
->operands
[0] = Operand(fmask_desc_ptr
);
5770 load
->operands
[1] = Operand(s4
); /* no sampler */
5771 load
->operands
[2] = Operand(coord
);
5772 load
->definitions
[0] = Definition(fmask
);
5779 ctx
->block
->instructions
.emplace_back(std::move(load
));
5781 Operand sample_index4
;
5782 if (sample_index
.isConstant()) {
5783 if (sample_index
.constantValue() < 16) {
5784 sample_index4
= Operand(sample_index
.constantValue() << 2);
5786 sample_index4
= Operand(0u);
5788 } else if (sample_index
.regClass() == s1
) {
5789 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5791 assert(sample_index
.regClass() == v1
);
5792 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5796 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5797 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5798 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5799 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5801 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5803 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5804 * resource descriptor is 0 (invalid),
5806 Temp compare
= bld
.tmp(bld
.lm
);
5807 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5808 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5810 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5812 /* Replace the MSAA sample index. */
5813 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5816 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5819 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5820 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5821 bool is_array
= glsl_sampler_type_is_array(type
);
5822 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5823 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5824 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5825 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5826 int count
= image_type_to_components_count(dim
, is_array
);
5827 std::vector
<Temp
> coords(count
);
5828 Builder
bld(ctx
->program
, ctx
->block
);
5832 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5833 /* get sample index */
5834 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5835 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5836 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5837 std::vector
<Temp
> fmask_load_address
;
5838 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5839 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5841 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5842 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5844 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5849 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5850 coords
.resize(coords
.size() + 1);
5851 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5853 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5855 for (int i
= 0; i
< count
; i
++)
5856 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5859 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5860 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5861 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5862 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5865 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5868 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5869 for (unsigned i
= 0; i
< coords
.size(); i
++)
5870 vec
->operands
[i
] = Operand(coords
[i
]);
5871 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5872 vec
->definitions
[0] = Definition(res
);
5873 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5878 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5880 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5881 if (semantics
& semantic_atomicrmw
)
5882 return memory_sync_info(storage
, semantics
);
5884 unsigned access
= nir_intrinsic_access(instr
);
5886 if (access
& ACCESS_VOLATILE
)
5887 semantics
|= semantic_volatile
;
5888 if (access
& ACCESS_CAN_REORDER
)
5889 semantics
|= semantic_can_reorder
| semantic_private
;
5891 return memory_sync_info(storage
, semantics
);
5894 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5896 Builder
bld(ctx
->program
, ctx
->block
);
5897 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5898 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5899 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5900 bool is_array
= glsl_sampler_type_is_array(type
);
5901 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5903 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5904 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5906 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5907 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5908 unsigned num_channels
= util_last_bit(mask
);
5909 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5910 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5913 switch (num_channels
) {
5915 opcode
= aco_opcode::buffer_load_format_x
;
5918 opcode
= aco_opcode::buffer_load_format_xy
;
5921 opcode
= aco_opcode::buffer_load_format_xyz
;
5924 opcode
= aco_opcode::buffer_load_format_xyzw
;
5927 unreachable(">4 channel buffer image load");
5929 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5930 load
->operands
[0] = Operand(rsrc
);
5931 load
->operands
[1] = Operand(vindex
);
5932 load
->operands
[2] = Operand((uint32_t) 0);
5934 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5937 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5938 load
->definitions
[0] = Definition(tmp
);
5940 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5941 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5943 ctx
->block
->instructions
.emplace_back(std::move(load
));
5945 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5949 Temp coords
= get_image_coords(ctx
, instr
, type
);
5950 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5952 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5953 unsigned num_components
= util_bitcount(dmask
);
5955 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5958 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5960 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5961 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5963 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5964 load
->operands
[0] = Operand(resource
);
5965 load
->operands
[1] = Operand(s4
); /* no sampler */
5966 load
->operands
[2] = Operand(coords
);
5967 load
->definitions
[0] = Definition(tmp
);
5968 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5969 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5970 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5971 load
->dmask
= dmask
;
5973 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5975 ctx
->block
->instructions
.emplace_back(std::move(load
));
5977 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5981 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5983 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5984 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5985 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5986 bool is_array
= glsl_sampler_type_is_array(type
);
5987 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5989 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5990 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5991 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5993 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5994 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5995 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5997 switch (data
.size()) {
5999 opcode
= aco_opcode::buffer_store_format_x
;
6002 opcode
= aco_opcode::buffer_store_format_xy
;
6005 opcode
= aco_opcode::buffer_store_format_xyz
;
6008 opcode
= aco_opcode::buffer_store_format_xyzw
;
6011 unreachable(">4 channel buffer image store");
6013 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
6014 store
->operands
[0] = Operand(rsrc
);
6015 store
->operands
[1] = Operand(vindex
);
6016 store
->operands
[2] = Operand((uint32_t) 0);
6017 store
->operands
[3] = Operand(data
);
6018 store
->idxen
= true;
6021 store
->disable_wqm
= true;
6023 ctx
->program
->needs_exact
= true;
6024 ctx
->block
->instructions
.emplace_back(std::move(store
));
6028 assert(data
.type() == RegType::vgpr
);
6029 Temp coords
= get_image_coords(ctx
, instr
, type
);
6030 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6032 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
6033 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
6035 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
6036 store
->operands
[0] = Operand(resource
);
6037 store
->operands
[1] = Operand(data
);
6038 store
->operands
[2] = Operand(coords
);
6041 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6042 store
->dmask
= (1 << data
.size()) - 1;
6044 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6045 store
->disable_wqm
= true;
6047 ctx
->program
->needs_exact
= true;
6048 ctx
->block
->instructions
.emplace_back(std::move(store
));
6052 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6054 /* return the previous value if dest is ever used */
6055 bool return_previous
= false;
6056 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6057 return_previous
= true;
6060 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6061 return_previous
= true;
6065 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6066 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6067 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6068 bool is_array
= glsl_sampler_type_is_array(type
);
6069 Builder
bld(ctx
->program
, ctx
->block
);
6071 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
6072 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
6074 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
6075 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
6077 aco_opcode buf_op
, image_op
;
6078 switch (instr
->intrinsic
) {
6079 case nir_intrinsic_image_deref_atomic_add
:
6080 buf_op
= aco_opcode::buffer_atomic_add
;
6081 image_op
= aco_opcode::image_atomic_add
;
6083 case nir_intrinsic_image_deref_atomic_umin
:
6084 buf_op
= aco_opcode::buffer_atomic_umin
;
6085 image_op
= aco_opcode::image_atomic_umin
;
6087 case nir_intrinsic_image_deref_atomic_imin
:
6088 buf_op
= aco_opcode::buffer_atomic_smin
;
6089 image_op
= aco_opcode::image_atomic_smin
;
6091 case nir_intrinsic_image_deref_atomic_umax
:
6092 buf_op
= aco_opcode::buffer_atomic_umax
;
6093 image_op
= aco_opcode::image_atomic_umax
;
6095 case nir_intrinsic_image_deref_atomic_imax
:
6096 buf_op
= aco_opcode::buffer_atomic_smax
;
6097 image_op
= aco_opcode::image_atomic_smax
;
6099 case nir_intrinsic_image_deref_atomic_and
:
6100 buf_op
= aco_opcode::buffer_atomic_and
;
6101 image_op
= aco_opcode::image_atomic_and
;
6103 case nir_intrinsic_image_deref_atomic_or
:
6104 buf_op
= aco_opcode::buffer_atomic_or
;
6105 image_op
= aco_opcode::image_atomic_or
;
6107 case nir_intrinsic_image_deref_atomic_xor
:
6108 buf_op
= aco_opcode::buffer_atomic_xor
;
6109 image_op
= aco_opcode::image_atomic_xor
;
6111 case nir_intrinsic_image_deref_atomic_exchange
:
6112 buf_op
= aco_opcode::buffer_atomic_swap
;
6113 image_op
= aco_opcode::image_atomic_swap
;
6115 case nir_intrinsic_image_deref_atomic_comp_swap
:
6116 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
6117 image_op
= aco_opcode::image_atomic_cmpswap
;
6120 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6124 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
6126 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6127 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6128 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6129 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6130 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6131 mubuf
->operands
[0] = Operand(resource
);
6132 mubuf
->operands
[1] = Operand(vindex
);
6133 mubuf
->operands
[2] = Operand((uint32_t)0);
6134 mubuf
->operands
[3] = Operand(data
);
6135 if (return_previous
)
6136 mubuf
->definitions
[0] = Definition(dst
);
6138 mubuf
->idxen
= true;
6139 mubuf
->glc
= return_previous
;
6140 mubuf
->dlc
= false; /* Not needed for atomics */
6141 mubuf
->disable_wqm
= true;
6143 ctx
->program
->needs_exact
= true;
6144 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6148 Temp coords
= get_image_coords(ctx
, instr
, type
);
6149 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6150 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6151 mimg
->operands
[0] = Operand(resource
);
6152 mimg
->operands
[1] = Operand(data
);
6153 mimg
->operands
[2] = Operand(coords
);
6154 if (return_previous
)
6155 mimg
->definitions
[0] = Definition(dst
);
6156 mimg
->glc
= return_previous
;
6157 mimg
->dlc
= false; /* Not needed for atomics */
6158 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6159 mimg
->dmask
= (1 << data
.size()) - 1;
6161 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6162 mimg
->disable_wqm
= true;
6164 ctx
->program
->needs_exact
= true;
6165 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6169 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6171 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6172 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6173 Builder
bld(ctx
->program
, ctx
->block
);
6175 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6177 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6178 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6180 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6181 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6183 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6184 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6186 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6187 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6188 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6189 if (dst
.type() == RegType::vgpr
)
6190 bld
.copy(Definition(dst
), shr_dst
);
6192 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6194 emit_extract_vector(ctx
, desc
, 2, dst
);
6198 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6200 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6201 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6202 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6203 bool is_array
= glsl_sampler_type_is_array(type
);
6204 Builder
bld(ctx
->program
, ctx
->block
);
6206 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6207 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6208 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6212 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6215 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6217 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6219 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6220 mimg
->operands
[0] = Operand(resource
);
6221 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6222 mimg
->operands
[2] = Operand(lod
);
6223 uint8_t& dmask
= mimg
->dmask
;
6224 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6225 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6226 mimg
->da
= glsl_sampler_type_is_array(type
);
6227 Definition
& def
= mimg
->definitions
[0];
6228 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6230 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6231 glsl_sampler_type_is_array(type
)) {
6233 assert(instr
->dest
.ssa
.num_components
== 3);
6234 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6235 def
= Definition(tmp
);
6236 emit_split_vector(ctx
, tmp
, 3);
6238 /* divide 3rd value by 6 by multiplying with magic number */
6239 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6240 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6242 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6243 emit_extract_vector(ctx
, tmp
, 0, v1
),
6244 emit_extract_vector(ctx
, tmp
, 1, v1
),
6247 } else if (ctx
->options
->chip_class
== GFX9
&&
6248 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6249 glsl_sampler_type_is_array(type
)) {
6250 assert(instr
->dest
.ssa
.num_components
== 2);
6251 def
= Definition(dst
);
6254 def
= Definition(dst
);
6257 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6260 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6262 Builder
bld(ctx
->program
, ctx
->block
);
6263 unsigned num_components
= instr
->num_components
;
6265 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6266 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6267 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6269 unsigned access
= nir_intrinsic_access(instr
);
6270 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6271 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6273 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6274 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6275 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6277 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6278 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6280 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6281 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6282 get_memory_sync_info(instr
, storage_buffer
, 0));
6285 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6287 Builder
bld(ctx
->program
, ctx
->block
);
6288 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6289 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6290 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6291 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6293 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6294 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6296 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6297 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6298 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6299 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6300 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6302 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6304 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6305 ctx
->options
->chip_class
>= GFX8
&&
6306 ctx
->options
->chip_class
< GFX10_3
&&
6307 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6310 offset
= bld
.as_uniform(offset
);
6311 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6313 unsigned write_count
= 0;
6314 Temp write_datas
[32];
6315 unsigned offsets
[32];
6316 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6317 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6319 for (unsigned i
= 0; i
< write_count
; i
++) {
6320 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6321 if (smem
&& ctx
->stage
== fragment_fs
)
6322 op
= aco_opcode::p_fs_buffer_store_smem
;
6325 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6326 store
->operands
[0] = Operand(rsrc
);
6328 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6329 offset
, Operand(offsets
[i
]));
6330 store
->operands
[1] = Operand(off
);
6332 store
->operands
[1] = Operand(offset
);
6334 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6335 store
->operands
[1].setFixed(m0
);
6336 store
->operands
[2] = Operand(write_datas
[i
]);
6339 store
->disable_wqm
= true;
6341 ctx
->block
->instructions
.emplace_back(std::move(store
));
6342 ctx
->program
->wb_smem_l1_on_end
= true;
6343 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6344 ctx
->block
->kind
|= block_kind_needs_lowering
;
6345 ctx
->program
->needs_exact
= true;
6348 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6349 store
->operands
[0] = Operand(rsrc
);
6350 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6351 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6352 store
->operands
[3] = Operand(write_datas
[i
]);
6353 store
->offset
= offsets
[i
];
6354 store
->offen
= (offset
.type() == RegType::vgpr
);
6357 store
->disable_wqm
= true;
6359 ctx
->program
->needs_exact
= true;
6360 ctx
->block
->instructions
.emplace_back(std::move(store
));
6365 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6367 /* return the previous value if dest is ever used */
6368 bool return_previous
= false;
6369 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6370 return_previous
= true;
6373 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6374 return_previous
= true;
6378 Builder
bld(ctx
->program
, ctx
->block
);
6379 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6381 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6382 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6383 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6385 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6386 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6387 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6389 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6391 aco_opcode op32
, op64
;
6392 switch (instr
->intrinsic
) {
6393 case nir_intrinsic_ssbo_atomic_add
:
6394 op32
= aco_opcode::buffer_atomic_add
;
6395 op64
= aco_opcode::buffer_atomic_add_x2
;
6397 case nir_intrinsic_ssbo_atomic_imin
:
6398 op32
= aco_opcode::buffer_atomic_smin
;
6399 op64
= aco_opcode::buffer_atomic_smin_x2
;
6401 case nir_intrinsic_ssbo_atomic_umin
:
6402 op32
= aco_opcode::buffer_atomic_umin
;
6403 op64
= aco_opcode::buffer_atomic_umin_x2
;
6405 case nir_intrinsic_ssbo_atomic_imax
:
6406 op32
= aco_opcode::buffer_atomic_smax
;
6407 op64
= aco_opcode::buffer_atomic_smax_x2
;
6409 case nir_intrinsic_ssbo_atomic_umax
:
6410 op32
= aco_opcode::buffer_atomic_umax
;
6411 op64
= aco_opcode::buffer_atomic_umax_x2
;
6413 case nir_intrinsic_ssbo_atomic_and
:
6414 op32
= aco_opcode::buffer_atomic_and
;
6415 op64
= aco_opcode::buffer_atomic_and_x2
;
6417 case nir_intrinsic_ssbo_atomic_or
:
6418 op32
= aco_opcode::buffer_atomic_or
;
6419 op64
= aco_opcode::buffer_atomic_or_x2
;
6421 case nir_intrinsic_ssbo_atomic_xor
:
6422 op32
= aco_opcode::buffer_atomic_xor
;
6423 op64
= aco_opcode::buffer_atomic_xor_x2
;
6425 case nir_intrinsic_ssbo_atomic_exchange
:
6426 op32
= aco_opcode::buffer_atomic_swap
;
6427 op64
= aco_opcode::buffer_atomic_swap_x2
;
6429 case nir_intrinsic_ssbo_atomic_comp_swap
:
6430 op32
= aco_opcode::buffer_atomic_cmpswap
;
6431 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6434 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6436 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6437 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6438 mubuf
->operands
[0] = Operand(rsrc
);
6439 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6440 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6441 mubuf
->operands
[3] = Operand(data
);
6442 if (return_previous
)
6443 mubuf
->definitions
[0] = Definition(dst
);
6445 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6446 mubuf
->glc
= return_previous
;
6447 mubuf
->dlc
= false; /* Not needed for atomics */
6448 mubuf
->disable_wqm
= true;
6449 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6450 ctx
->program
->needs_exact
= true;
6451 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6454 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6456 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6457 Builder
bld(ctx
->program
, ctx
->block
);
6458 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6459 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6462 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6464 Builder
bld(ctx
->program
, ctx
->block
);
6465 unsigned num_components
= instr
->num_components
;
6466 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6468 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6469 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6470 num_components
, component_size
};
6471 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6472 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6473 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6474 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6475 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6476 * it's safe to use SMEM */
6477 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6478 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6479 emit_global_load(ctx
, bld
, &info
);
6481 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6482 emit_smem_load(ctx
, bld
, &info
);
6486 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6488 Builder
bld(ctx
->program
, ctx
->block
);
6489 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6490 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6492 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6493 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6494 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6495 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6497 if (ctx
->options
->chip_class
>= GFX7
)
6498 addr
= as_vgpr(ctx
, addr
);
6500 unsigned write_count
= 0;
6501 Temp write_datas
[32];
6502 unsigned offsets
[32];
6503 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6504 16, &write_count
, write_datas
, offsets
);
6506 for (unsigned i
= 0; i
< write_count
; i
++) {
6507 if (ctx
->options
->chip_class
>= GFX7
) {
6508 unsigned offset
= offsets
[i
];
6509 Temp store_addr
= addr
;
6510 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6511 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6512 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6513 Temp carry
= bld
.tmp(bld
.lm
);
6514 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6516 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6517 Operand(offset
), addr0
);
6518 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6520 carry
).def(1).setHint(vcc
);
6522 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6527 bool global
= ctx
->options
->chip_class
>= GFX9
;
6529 switch (write_datas
[i
].bytes()) {
6531 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6534 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6537 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6540 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6543 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6546 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6549 unreachable("store_global not implemented for this size.");
6552 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6553 flat
->operands
[0] = Operand(store_addr
);
6554 flat
->operands
[1] = Operand(s1
);
6555 flat
->operands
[2] = Operand(write_datas
[i
]);
6558 flat
->offset
= offset
;
6559 flat
->disable_wqm
= true;
6561 ctx
->program
->needs_exact
= true;
6562 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6564 assert(ctx
->options
->chip_class
== GFX6
);
6566 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6568 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6570 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6571 mubuf
->operands
[0] = Operand(rsrc
);
6572 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6573 mubuf
->operands
[2] = Operand(0u);
6574 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6577 mubuf
->offset
= offsets
[i
];
6578 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6579 mubuf
->disable_wqm
= true;
6581 ctx
->program
->needs_exact
= true;
6582 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6587 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6589 /* return the previous value if dest is ever used */
6590 bool return_previous
= false;
6591 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6592 return_previous
= true;
6595 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6596 return_previous
= true;
6600 Builder
bld(ctx
->program
, ctx
->block
);
6601 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6602 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6604 if (ctx
->options
->chip_class
>= GFX7
)
6605 addr
= as_vgpr(ctx
, addr
);
6607 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6608 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6609 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6611 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6613 aco_opcode op32
, op64
;
6615 if (ctx
->options
->chip_class
>= GFX7
) {
6616 bool global
= ctx
->options
->chip_class
>= GFX9
;
6617 switch (instr
->intrinsic
) {
6618 case nir_intrinsic_global_atomic_add
:
6619 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6620 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6622 case nir_intrinsic_global_atomic_imin
:
6623 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6624 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6626 case nir_intrinsic_global_atomic_umin
:
6627 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6628 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6630 case nir_intrinsic_global_atomic_imax
:
6631 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6632 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6634 case nir_intrinsic_global_atomic_umax
:
6635 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6636 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6638 case nir_intrinsic_global_atomic_and
:
6639 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6640 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6642 case nir_intrinsic_global_atomic_or
:
6643 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6644 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6646 case nir_intrinsic_global_atomic_xor
:
6647 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6648 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6650 case nir_intrinsic_global_atomic_exchange
:
6651 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6652 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6654 case nir_intrinsic_global_atomic_comp_swap
:
6655 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6656 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6659 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6662 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6663 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6664 flat
->operands
[0] = Operand(addr
);
6665 flat
->operands
[1] = Operand(s1
);
6666 flat
->operands
[2] = Operand(data
);
6667 if (return_previous
)
6668 flat
->definitions
[0] = Definition(dst
);
6669 flat
->glc
= return_previous
;
6670 flat
->dlc
= false; /* Not needed for atomics */
6672 flat
->disable_wqm
= true;
6673 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6674 ctx
->program
->needs_exact
= true;
6675 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6677 assert(ctx
->options
->chip_class
== GFX6
);
6679 switch (instr
->intrinsic
) {
6680 case nir_intrinsic_global_atomic_add
:
6681 op32
= aco_opcode::buffer_atomic_add
;
6682 op64
= aco_opcode::buffer_atomic_add_x2
;
6684 case nir_intrinsic_global_atomic_imin
:
6685 op32
= aco_opcode::buffer_atomic_smin
;
6686 op64
= aco_opcode::buffer_atomic_smin_x2
;
6688 case nir_intrinsic_global_atomic_umin
:
6689 op32
= aco_opcode::buffer_atomic_umin
;
6690 op64
= aco_opcode::buffer_atomic_umin_x2
;
6692 case nir_intrinsic_global_atomic_imax
:
6693 op32
= aco_opcode::buffer_atomic_smax
;
6694 op64
= aco_opcode::buffer_atomic_smax_x2
;
6696 case nir_intrinsic_global_atomic_umax
:
6697 op32
= aco_opcode::buffer_atomic_umax
;
6698 op64
= aco_opcode::buffer_atomic_umax_x2
;
6700 case nir_intrinsic_global_atomic_and
:
6701 op32
= aco_opcode::buffer_atomic_and
;
6702 op64
= aco_opcode::buffer_atomic_and_x2
;
6704 case nir_intrinsic_global_atomic_or
:
6705 op32
= aco_opcode::buffer_atomic_or
;
6706 op64
= aco_opcode::buffer_atomic_or_x2
;
6708 case nir_intrinsic_global_atomic_xor
:
6709 op32
= aco_opcode::buffer_atomic_xor
;
6710 op64
= aco_opcode::buffer_atomic_xor_x2
;
6712 case nir_intrinsic_global_atomic_exchange
:
6713 op32
= aco_opcode::buffer_atomic_swap
;
6714 op64
= aco_opcode::buffer_atomic_swap_x2
;
6716 case nir_intrinsic_global_atomic_comp_swap
:
6717 op32
= aco_opcode::buffer_atomic_cmpswap
;
6718 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6721 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6724 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6726 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6728 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6729 mubuf
->operands
[0] = Operand(rsrc
);
6730 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6731 mubuf
->operands
[2] = Operand(0u);
6732 mubuf
->operands
[3] = Operand(data
);
6733 if (return_previous
)
6734 mubuf
->definitions
[0] = Definition(dst
);
6735 mubuf
->glc
= return_previous
;
6738 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6739 mubuf
->disable_wqm
= true;
6740 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6741 ctx
->program
->needs_exact
= true;
6742 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6746 sync_scope
translate_nir_scope(nir_scope scope
)
6749 case NIR_SCOPE_NONE
:
6750 case NIR_SCOPE_INVOCATION
:
6751 return scope_invocation
;
6752 case NIR_SCOPE_SUBGROUP
:
6753 return scope_subgroup
;
6754 case NIR_SCOPE_WORKGROUP
:
6755 return scope_workgroup
;
6756 case NIR_SCOPE_QUEUE_FAMILY
:
6757 return scope_queuefamily
;
6758 case NIR_SCOPE_DEVICE
:
6759 return scope_device
;
6761 unreachable("invalid scope");
6764 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6765 Builder
bld(ctx
->program
, ctx
->block
);
6767 unsigned semantics
= 0;
6768 unsigned storage
= 0;
6769 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6770 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6772 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6773 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6774 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6775 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6776 storage
|= storage_shared
;
6777 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6778 storage
|= storage_shared
;
6780 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6781 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6782 semantics
|= semantic_acquire
| semantic_release
;
6783 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6784 semantics
|= semantic_acquire
| semantic_release
;
6786 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6788 bld
.barrier(aco_opcode::p_barrier
,
6789 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6793 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6795 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6796 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6797 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6798 Builder
bld(ctx
->program
, ctx
->block
);
6800 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6801 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6802 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6805 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6807 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6808 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6809 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6810 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6812 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6813 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6816 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6818 unsigned offset
= nir_intrinsic_base(instr
);
6819 Builder
bld(ctx
->program
, ctx
->block
);
6820 Operand m
= load_lds_size_m0(bld
);
6821 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6822 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6824 unsigned num_operands
= 3;
6825 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6826 switch(instr
->intrinsic
) {
6827 case nir_intrinsic_shared_atomic_add
:
6828 op32
= aco_opcode::ds_add_u32
;
6829 op64
= aco_opcode::ds_add_u64
;
6830 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6831 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6833 case nir_intrinsic_shared_atomic_imin
:
6834 op32
= aco_opcode::ds_min_i32
;
6835 op64
= aco_opcode::ds_min_i64
;
6836 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6837 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6839 case nir_intrinsic_shared_atomic_umin
:
6840 op32
= aco_opcode::ds_min_u32
;
6841 op64
= aco_opcode::ds_min_u64
;
6842 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6843 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6845 case nir_intrinsic_shared_atomic_imax
:
6846 op32
= aco_opcode::ds_max_i32
;
6847 op64
= aco_opcode::ds_max_i64
;
6848 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6849 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6851 case nir_intrinsic_shared_atomic_umax
:
6852 op32
= aco_opcode::ds_max_u32
;
6853 op64
= aco_opcode::ds_max_u64
;
6854 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6855 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6857 case nir_intrinsic_shared_atomic_and
:
6858 op32
= aco_opcode::ds_and_b32
;
6859 op64
= aco_opcode::ds_and_b64
;
6860 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6861 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6863 case nir_intrinsic_shared_atomic_or
:
6864 op32
= aco_opcode::ds_or_b32
;
6865 op64
= aco_opcode::ds_or_b64
;
6866 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6867 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6869 case nir_intrinsic_shared_atomic_xor
:
6870 op32
= aco_opcode::ds_xor_b32
;
6871 op64
= aco_opcode::ds_xor_b64
;
6872 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6873 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6875 case nir_intrinsic_shared_atomic_exchange
:
6876 op32
= aco_opcode::ds_write_b32
;
6877 op64
= aco_opcode::ds_write_b64
;
6878 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6879 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6881 case nir_intrinsic_shared_atomic_comp_swap
:
6882 op32
= aco_opcode::ds_cmpst_b32
;
6883 op64
= aco_opcode::ds_cmpst_b64
;
6884 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6885 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6888 case nir_intrinsic_shared_atomic_fadd
:
6889 op32
= aco_opcode::ds_add_f32
;
6890 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6891 op64
= aco_opcode::num_opcodes
;
6892 op64_rtn
= aco_opcode::num_opcodes
;
6895 unreachable("Unhandled shared atomic intrinsic");
6898 /* return the previous value if dest is ever used */
6899 bool return_previous
= false;
6900 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6901 return_previous
= true;
6904 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6905 return_previous
= true;
6910 if (data
.size() == 1) {
6911 assert(instr
->dest
.ssa
.bit_size
== 32);
6912 op
= return_previous
? op32_rtn
: op32
;
6914 assert(instr
->dest
.ssa
.bit_size
== 64);
6915 op
= return_previous
? op64_rtn
: op64
;
6918 if (offset
> 65535) {
6919 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6923 aco_ptr
<DS_instruction
> ds
;
6924 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6925 ds
->operands
[0] = Operand(address
);
6926 ds
->operands
[1] = Operand(data
);
6927 if (num_operands
== 4)
6928 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6929 ds
->operands
[num_operands
- 1] = m
;
6930 ds
->offset0
= offset
;
6931 if (return_previous
)
6932 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6933 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6934 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6937 Temp
get_scratch_resource(isel_context
*ctx
)
6939 Builder
bld(ctx
->program
, ctx
->block
);
6940 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6941 if (ctx
->stage
!= compute_cs
)
6942 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6944 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6945 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6947 if (ctx
->program
->chip_class
>= GFX10
) {
6948 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6949 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6950 S_008F0C_RESOURCE_LEVEL(1);
6951 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6952 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6953 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6956 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6957 if (ctx
->program
->chip_class
<= GFX8
)
6958 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6960 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6963 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6964 Builder
bld(ctx
->program
, ctx
->block
);
6965 Temp rsrc
= get_scratch_resource(ctx
);
6966 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6967 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6969 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6970 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6971 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6972 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6973 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6974 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6975 info
.soffset
= ctx
->program
->scratch_offset
;
6976 emit_scratch_load(ctx
, bld
, &info
);
6979 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6980 Builder
bld(ctx
->program
, ctx
->block
);
6981 Temp rsrc
= get_scratch_resource(ctx
);
6982 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6983 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6985 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6986 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6988 unsigned write_count
= 0;
6989 Temp write_datas
[32];
6990 unsigned offsets
[32];
6991 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6992 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6993 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6995 for (unsigned i
= 0; i
< write_count
; i
++) {
6996 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6997 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6998 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
7002 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7003 uint8_t log2_ps_iter_samples
;
7004 if (ctx
->program
->info
->ps
.force_persample
) {
7005 log2_ps_iter_samples
=
7006 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
7008 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
7011 /* The bit pattern matches that used by fixed function fragment
7013 static const unsigned ps_iter_masks
[] = {
7014 0xffff, /* not used */
7020 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
7022 Builder
bld(ctx
->program
, ctx
->block
);
7024 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
7025 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7026 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
7027 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
7028 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7029 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
7032 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
7033 Builder
bld(ctx
->program
, ctx
->block
);
7035 unsigned stream
= nir_intrinsic_stream_id(instr
);
7036 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7037 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
7038 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
7041 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
7043 unsigned num_components
=
7044 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
7045 assert(num_components
);
7047 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
7048 unsigned stream_offset
= 0;
7049 for (unsigned i
= 0; i
< stream
; i
++) {
7050 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
7051 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
7054 /* Limit on the stride field for <= GFX7. */
7055 assert(stride
< (1 << 14));
7057 Temp gsvs_dwords
[4];
7058 for (unsigned i
= 0; i
< 4; i
++)
7059 gsvs_dwords
[i
] = bld
.tmp(s1
);
7060 bld
.pseudo(aco_opcode::p_split_vector
,
7061 Definition(gsvs_dwords
[0]),
7062 Definition(gsvs_dwords
[1]),
7063 Definition(gsvs_dwords
[2]),
7064 Definition(gsvs_dwords
[3]),
7067 if (stream_offset
) {
7068 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
7070 Temp carry
= bld
.tmp(s1
);
7071 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
7072 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
7075 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
7076 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
7078 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7079 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
7081 unsigned offset
= 0;
7082 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
7083 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
7086 for (unsigned j
= 0; j
< 4; j
++) {
7087 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7090 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7091 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7092 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7093 if (const_offset
>= 4096u) {
7094 if (vaddr_offset
.isUndefined())
7095 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7097 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7098 const_offset
%= 4096u;
7101 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7102 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7103 mtbuf
->operands
[1] = vaddr_offset
;
7104 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7105 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7106 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7107 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7108 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7109 mtbuf
->offset
= const_offset
;
7112 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
7113 bld
.insert(std::move(mtbuf
));
7116 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7119 /* outputs for the next vertex are undefined and keeping them around can
7120 * create invalid IR with control flow */
7121 ctx
->outputs
.mask
[i
] = 0;
7124 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7127 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7129 Builder
bld(ctx
->program
, ctx
->block
);
7131 if (cluster_size
== 1) {
7133 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7134 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7135 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7136 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7137 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7138 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7139 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7140 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7141 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7142 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7143 //subgroupAnd(val) -> (exec & ~val) == 0
7144 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7145 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7146 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7147 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7148 //subgroupOr(val) -> (val & exec) != 0
7149 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7150 return bool_to_vector_condition(ctx
, tmp
);
7151 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7152 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7153 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7154 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7155 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7156 return bool_to_vector_condition(ctx
, tmp
);
7158 //subgroupClustered{And,Or,Xor}(val, n) ->
7159 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7160 //cluster_offset = ~(n - 1) & lane_id
7161 //cluster_mask = ((1 << n) - 1)
7162 //subgroupClusteredAnd():
7163 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7164 //subgroupClusteredOr():
7165 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7166 //subgroupClusteredXor():
7167 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7168 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7169 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7172 if (op
== nir_op_iand
)
7173 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7175 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7177 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7179 if (ctx
->program
->chip_class
<= GFX7
)
7180 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7181 else if (ctx
->program
->wave_size
== 64)
7182 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7184 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7185 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7186 if (cluster_mask
!= 0xffffffff)
7187 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7189 Definition cmp_def
= Definition();
7190 if (op
== nir_op_iand
) {
7191 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7192 } else if (op
== nir_op_ior
) {
7193 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7194 } else if (op
== nir_op_ixor
) {
7195 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7196 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7197 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7199 cmp_def
.setHint(vcc
);
7200 return cmp_def
.getTemp();
7204 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7206 Builder
bld(ctx
->program
, ctx
->block
);
7208 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7209 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7210 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7212 if (op
== nir_op_iand
)
7213 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7215 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7217 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7218 Temp lo
= lohi
.def(0).getTemp();
7219 Temp hi
= lohi
.def(1).getTemp();
7220 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7222 Definition cmp_def
= Definition();
7223 if (op
== nir_op_iand
)
7224 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7225 else if (op
== nir_op_ior
)
7226 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7227 else if (op
== nir_op_ixor
)
7228 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7229 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7230 cmp_def
.setHint(vcc
);
7231 return cmp_def
.getTemp();
7234 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7236 Builder
bld(ctx
->program
, ctx
->block
);
7238 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7239 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7240 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7241 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7242 if (op
== nir_op_iand
)
7243 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7244 else if (op
== nir_op_ior
)
7245 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7246 else if (op
== nir_op_ixor
)
7247 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7253 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7255 Builder
bld(ctx
->program
, ctx
->block
);
7256 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7257 if (src
.regClass().type() == RegType::vgpr
) {
7258 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7259 } else if (src
.regClass() == s1
) {
7260 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7261 } else if (src
.regClass() == s2
) {
7262 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7264 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7265 nir_print_instr(&instr
->instr
, stderr
);
7266 fprintf(stderr
, "\n");
7270 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7272 Builder
bld(ctx
->program
, ctx
->block
);
7273 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7274 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7275 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7277 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7278 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7279 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7280 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7283 if (ctx
->program
->chip_class
>= GFX8
) {
7284 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7285 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7286 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7287 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7288 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7289 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7291 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7292 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7293 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7294 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7295 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7296 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7297 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7298 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7299 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7300 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7303 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7304 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7305 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7306 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7307 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7308 Temp wqm1
= bld
.tmp(v1
);
7309 emit_wqm(ctx
, tmp1
, wqm1
, true);
7310 Temp wqm2
= bld
.tmp(v1
);
7311 emit_wqm(ctx
, tmp2
, wqm2
, true);
7312 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7316 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7318 Builder
bld(ctx
->program
, ctx
->block
);
7319 switch(instr
->intrinsic
) {
7320 case nir_intrinsic_load_barycentric_sample
:
7321 case nir_intrinsic_load_barycentric_pixel
:
7322 case nir_intrinsic_load_barycentric_centroid
: {
7323 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7324 Temp bary
= Temp(0, s2
);
7326 case INTERP_MODE_SMOOTH
:
7327 case INTERP_MODE_NONE
:
7328 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7329 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7330 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7331 bary
= ctx
->persp_centroid
;
7332 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7333 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7335 case INTERP_MODE_NOPERSPECTIVE
:
7336 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7337 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7338 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7339 bary
= ctx
->linear_centroid
;
7340 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7341 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7346 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7347 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7348 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7349 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7350 Operand(p1
), Operand(p2
));
7351 emit_split_vector(ctx
, dst
, 2);
7354 case nir_intrinsic_load_barycentric_model
: {
7355 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7357 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7358 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7359 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7360 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7361 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7362 Operand(p1
), Operand(p2
), Operand(p3
));
7363 emit_split_vector(ctx
, dst
, 3);
7366 case nir_intrinsic_load_barycentric_at_sample
: {
7367 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7368 switch (ctx
->options
->key
.fs
.num_samples
) {
7369 case 2: sample_pos_offset
+= 1 << 3; break;
7370 case 4: sample_pos_offset
+= 3 << 3; break;
7371 case 8: sample_pos_offset
+= 7 << 3; break;
7375 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7376 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7377 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7378 //TODO: bounds checking?
7379 if (addr
.type() == RegType::sgpr
) {
7382 sample_pos_offset
+= const_addr
->u32
<< 3;
7383 offset
= Operand(sample_pos_offset
);
7384 } else if (ctx
->options
->chip_class
>= GFX9
) {
7385 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7387 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7388 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7391 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7392 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7394 } else if (ctx
->options
->chip_class
>= GFX9
) {
7395 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7396 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7397 } else if (ctx
->options
->chip_class
>= GFX7
) {
7398 /* addr += private_segment_buffer + sample_pos_offset */
7399 Temp tmp0
= bld
.tmp(s1
);
7400 Temp tmp1
= bld
.tmp(s1
);
7401 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7402 Definition scc_tmp
= bld
.def(s1
, scc
);
7403 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7404 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7405 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7406 Temp pck0
= bld
.tmp(v1
);
7407 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7408 tmp1
= as_vgpr(ctx
, tmp1
);
7409 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7410 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7412 /* sample_pos = flat_load_dwordx2 addr */
7413 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7415 assert(ctx
->options
->chip_class
== GFX6
);
7417 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7418 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7419 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7421 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7422 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7424 sample_pos
= bld
.tmp(v2
);
7426 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7427 load
->definitions
[0] = Definition(sample_pos
);
7428 load
->operands
[0] = Operand(rsrc
);
7429 load
->operands
[1] = Operand(addr
);
7430 load
->operands
[2] = Operand(0u);
7431 load
->offset
= sample_pos_offset
;
7433 load
->addr64
= true;
7436 load
->disable_wqm
= false;
7437 ctx
->block
->instructions
.emplace_back(std::move(load
));
7440 /* sample_pos -= 0.5 */
7441 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7442 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7443 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7444 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7445 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7447 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7450 case nir_intrinsic_load_barycentric_at_offset
: {
7451 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7452 RegClass rc
= RegClass(offset
.type(), 1);
7453 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7454 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7455 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7458 case nir_intrinsic_load_front_face
: {
7459 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7460 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7463 case nir_intrinsic_load_view_index
: {
7464 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7465 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7466 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7472 case nir_intrinsic_load_layer_id
: {
7473 unsigned idx
= nir_intrinsic_base(instr
);
7474 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7475 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7478 case nir_intrinsic_load_frag_coord
: {
7479 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7482 case nir_intrinsic_load_sample_pos
: {
7483 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7484 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7485 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7486 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7487 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7490 case nir_intrinsic_load_tess_coord
:
7491 visit_load_tess_coord(ctx
, instr
);
7493 case nir_intrinsic_load_interpolated_input
:
7494 visit_load_interpolated_input(ctx
, instr
);
7496 case nir_intrinsic_store_output
:
7497 visit_store_output(ctx
, instr
);
7499 case nir_intrinsic_load_input
:
7500 case nir_intrinsic_load_input_vertex
:
7501 visit_load_input(ctx
, instr
);
7503 case nir_intrinsic_load_output
:
7504 visit_load_output(ctx
, instr
);
7506 case nir_intrinsic_load_per_vertex_input
:
7507 visit_load_per_vertex_input(ctx
, instr
);
7509 case nir_intrinsic_load_per_vertex_output
:
7510 visit_load_per_vertex_output(ctx
, instr
);
7512 case nir_intrinsic_store_per_vertex_output
:
7513 visit_store_per_vertex_output(ctx
, instr
);
7515 case nir_intrinsic_load_ubo
:
7516 visit_load_ubo(ctx
, instr
);
7518 case nir_intrinsic_load_push_constant
:
7519 visit_load_push_constant(ctx
, instr
);
7521 case nir_intrinsic_load_constant
:
7522 visit_load_constant(ctx
, instr
);
7524 case nir_intrinsic_vulkan_resource_index
:
7525 visit_load_resource(ctx
, instr
);
7527 case nir_intrinsic_discard
:
7528 visit_discard(ctx
, instr
);
7530 case nir_intrinsic_discard_if
:
7531 visit_discard_if(ctx
, instr
);
7533 case nir_intrinsic_load_shared
:
7534 visit_load_shared(ctx
, instr
);
7536 case nir_intrinsic_store_shared
:
7537 visit_store_shared(ctx
, instr
);
7539 case nir_intrinsic_shared_atomic_add
:
7540 case nir_intrinsic_shared_atomic_imin
:
7541 case nir_intrinsic_shared_atomic_umin
:
7542 case nir_intrinsic_shared_atomic_imax
:
7543 case nir_intrinsic_shared_atomic_umax
:
7544 case nir_intrinsic_shared_atomic_and
:
7545 case nir_intrinsic_shared_atomic_or
:
7546 case nir_intrinsic_shared_atomic_xor
:
7547 case nir_intrinsic_shared_atomic_exchange
:
7548 case nir_intrinsic_shared_atomic_comp_swap
:
7549 case nir_intrinsic_shared_atomic_fadd
:
7550 visit_shared_atomic(ctx
, instr
);
7552 case nir_intrinsic_image_deref_load
:
7553 visit_image_load(ctx
, instr
);
7555 case nir_intrinsic_image_deref_store
:
7556 visit_image_store(ctx
, instr
);
7558 case nir_intrinsic_image_deref_atomic_add
:
7559 case nir_intrinsic_image_deref_atomic_umin
:
7560 case nir_intrinsic_image_deref_atomic_imin
:
7561 case nir_intrinsic_image_deref_atomic_umax
:
7562 case nir_intrinsic_image_deref_atomic_imax
:
7563 case nir_intrinsic_image_deref_atomic_and
:
7564 case nir_intrinsic_image_deref_atomic_or
:
7565 case nir_intrinsic_image_deref_atomic_xor
:
7566 case nir_intrinsic_image_deref_atomic_exchange
:
7567 case nir_intrinsic_image_deref_atomic_comp_swap
:
7568 visit_image_atomic(ctx
, instr
);
7570 case nir_intrinsic_image_deref_size
:
7571 visit_image_size(ctx
, instr
);
7573 case nir_intrinsic_load_ssbo
:
7574 visit_load_ssbo(ctx
, instr
);
7576 case nir_intrinsic_store_ssbo
:
7577 visit_store_ssbo(ctx
, instr
);
7579 case nir_intrinsic_load_global
:
7580 visit_load_global(ctx
, instr
);
7582 case nir_intrinsic_store_global
:
7583 visit_store_global(ctx
, instr
);
7585 case nir_intrinsic_global_atomic_add
:
7586 case nir_intrinsic_global_atomic_imin
:
7587 case nir_intrinsic_global_atomic_umin
:
7588 case nir_intrinsic_global_atomic_imax
:
7589 case nir_intrinsic_global_atomic_umax
:
7590 case nir_intrinsic_global_atomic_and
:
7591 case nir_intrinsic_global_atomic_or
:
7592 case nir_intrinsic_global_atomic_xor
:
7593 case nir_intrinsic_global_atomic_exchange
:
7594 case nir_intrinsic_global_atomic_comp_swap
:
7595 visit_global_atomic(ctx
, instr
);
7597 case nir_intrinsic_ssbo_atomic_add
:
7598 case nir_intrinsic_ssbo_atomic_imin
:
7599 case nir_intrinsic_ssbo_atomic_umin
:
7600 case nir_intrinsic_ssbo_atomic_imax
:
7601 case nir_intrinsic_ssbo_atomic_umax
:
7602 case nir_intrinsic_ssbo_atomic_and
:
7603 case nir_intrinsic_ssbo_atomic_or
:
7604 case nir_intrinsic_ssbo_atomic_xor
:
7605 case nir_intrinsic_ssbo_atomic_exchange
:
7606 case nir_intrinsic_ssbo_atomic_comp_swap
:
7607 visit_atomic_ssbo(ctx
, instr
);
7609 case nir_intrinsic_load_scratch
:
7610 visit_load_scratch(ctx
, instr
);
7612 case nir_intrinsic_store_scratch
:
7613 visit_store_scratch(ctx
, instr
);
7615 case nir_intrinsic_get_buffer_size
:
7616 visit_get_buffer_size(ctx
, instr
);
7618 case nir_intrinsic_scoped_barrier
:
7619 emit_scoped_barrier(ctx
, instr
);
7621 case nir_intrinsic_load_num_work_groups
: {
7622 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7623 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7624 emit_split_vector(ctx
, dst
, 3);
7627 case nir_intrinsic_load_local_invocation_id
: {
7628 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7629 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7630 emit_split_vector(ctx
, dst
, 3);
7633 case nir_intrinsic_load_work_group_id
: {
7634 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7635 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7636 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7637 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7638 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7639 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7640 emit_split_vector(ctx
, dst
, 3);
7643 case nir_intrinsic_load_local_invocation_index
: {
7644 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7646 /* The tg_size bits [6:11] contain the subgroup id,
7647 * we need this multiplied by the wave size, and then OR the thread id to it.
7649 if (ctx
->program
->wave_size
== 64) {
7650 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7651 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7652 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7653 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7655 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7656 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7657 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7658 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7662 case nir_intrinsic_load_subgroup_id
: {
7663 if (ctx
->stage
== compute_cs
) {
7664 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7665 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7667 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7671 case nir_intrinsic_load_subgroup_invocation
: {
7672 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7675 case nir_intrinsic_load_num_subgroups
: {
7676 if (ctx
->stage
== compute_cs
)
7677 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7678 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7680 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7683 case nir_intrinsic_ballot
: {
7684 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7685 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7686 Definition tmp
= bld
.def(dst
.regClass());
7687 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7688 if (instr
->src
[0].ssa
->bit_size
== 1) {
7689 assert(src
.regClass() == bld
.lm
);
7690 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7691 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7692 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7693 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7694 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7696 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7697 nir_print_instr(&instr
->instr
, stderr
);
7698 fprintf(stderr
, "\n");
7700 if (dst
.size() != bld
.lm
.size()) {
7701 /* Wave32 with ballot size set to 64 */
7702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7704 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7707 case nir_intrinsic_shuffle
:
7708 case nir_intrinsic_read_invocation
: {
7709 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7710 if (!nir_src_is_divergent(instr
->src
[0])) {
7711 emit_uniform_subgroup(ctx
, instr
, src
);
7713 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7714 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7715 tid
= bld
.as_uniform(tid
);
7716 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7717 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7718 Temp tmp
= bld
.tmp(v1
);
7719 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7720 if (dst
.type() == RegType::vgpr
)
7721 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7723 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7724 } else if (src
.regClass() == v1
) {
7725 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7726 } else if (src
.regClass() == v2
) {
7727 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7728 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7729 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7730 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7731 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7732 emit_split_vector(ctx
, dst
, 2);
7733 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7734 assert(src
.regClass() == bld
.lm
);
7735 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7736 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7737 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7738 assert(src
.regClass() == bld
.lm
);
7740 if (ctx
->program
->chip_class
<= GFX7
)
7741 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7742 else if (ctx
->program
->wave_size
== 64)
7743 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7745 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7746 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7747 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7748 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7751 nir_print_instr(&instr
->instr
, stderr
);
7752 fprintf(stderr
, "\n");
7757 case nir_intrinsic_load_sample_id
: {
7758 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7759 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7762 case nir_intrinsic_load_sample_mask_in
: {
7763 visit_load_sample_mask_in(ctx
, instr
);
7766 case nir_intrinsic_read_first_invocation
: {
7767 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7768 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7769 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7771 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7773 } else if (src
.regClass() == v2
) {
7774 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7776 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7777 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7778 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7779 emit_split_vector(ctx
, dst
, 2);
7780 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7781 assert(src
.regClass() == bld
.lm
);
7782 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7783 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7784 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7785 } else if (src
.regClass() == s1
) {
7786 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7787 } else if (src
.regClass() == s2
) {
7788 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7791 nir_print_instr(&instr
->instr
, stderr
);
7792 fprintf(stderr
, "\n");
7796 case nir_intrinsic_vote_all
: {
7797 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7798 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7799 assert(src
.regClass() == bld
.lm
);
7800 assert(dst
.regClass() == bld
.lm
);
7802 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7803 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7804 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7807 case nir_intrinsic_vote_any
: {
7808 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7809 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7810 assert(src
.regClass() == bld
.lm
);
7811 assert(dst
.regClass() == bld
.lm
);
7813 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7814 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7817 case nir_intrinsic_reduce
:
7818 case nir_intrinsic_inclusive_scan
:
7819 case nir_intrinsic_exclusive_scan
: {
7820 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7821 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7822 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7823 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7824 nir_intrinsic_cluster_size(instr
) : 0;
7825 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7827 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7828 emit_uniform_subgroup(ctx
, instr
, src
);
7829 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7830 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7832 else if (op
== nir_op_iadd
)
7834 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7836 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7838 switch (instr
->intrinsic
) {
7839 case nir_intrinsic_reduce
:
7840 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7842 case nir_intrinsic_exclusive_scan
:
7843 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7845 case nir_intrinsic_inclusive_scan
:
7846 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7851 } else if (cluster_size
== 1) {
7852 bld
.copy(Definition(dst
), src
);
7854 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7856 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7860 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7861 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7876 unreachable("unknown reduction op");
7882 switch (instr
->intrinsic
) {
7883 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7884 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7885 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7887 unreachable("unknown reduce intrinsic");
7890 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7891 reduce
->operands
[0] = Operand(src
);
7892 // filled in by aco_reduce_assign.cpp, used internally as part of the
7894 assert(dst
.size() == 1 || dst
.size() == 2);
7895 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7896 reduce
->operands
[2] = Operand(v1
.as_linear());
7898 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7899 reduce
->definitions
[0] = Definition(tmp_dst
);
7900 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7901 reduce
->definitions
[2] = Definition();
7902 reduce
->definitions
[3] = Definition(scc
, s1
);
7903 reduce
->definitions
[4] = Definition();
7904 reduce
->reduce_op
= reduce_op
;
7905 reduce
->cluster_size
= cluster_size
;
7906 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7908 emit_wqm(ctx
, tmp_dst
, dst
);
7912 case nir_intrinsic_quad_broadcast
: {
7913 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7914 if (!nir_dest_is_divergent(instr
->dest
)) {
7915 emit_uniform_subgroup(ctx
, instr
, src
);
7917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7918 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7919 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7921 if (instr
->dest
.ssa
.bit_size
== 1) {
7922 assert(src
.regClass() == bld
.lm
);
7923 assert(dst
.regClass() == bld
.lm
);
7924 uint32_t half_mask
= 0x11111111u
<< lane
;
7925 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7926 Temp tmp
= bld
.tmp(bld
.lm
);
7927 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7928 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7929 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7930 emit_wqm(ctx
, tmp
, dst
);
7931 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7932 Temp tmp
= bld
.tmp(v1
);
7933 if (ctx
->program
->chip_class
>= GFX8
)
7934 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7936 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7938 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7939 Temp tmp
= bld
.tmp(v1
);
7940 if (ctx
->program
->chip_class
>= GFX8
)
7941 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7943 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7944 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7945 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7946 if (ctx
->program
->chip_class
>= GFX8
)
7947 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7949 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7950 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7951 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7952 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7953 if (ctx
->program
->chip_class
>= GFX8
) {
7954 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7955 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7957 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7958 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7960 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7961 emit_split_vector(ctx
, dst
, 2);
7963 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7964 nir_print_instr(&instr
->instr
, stderr
);
7965 fprintf(stderr
, "\n");
7970 case nir_intrinsic_quad_swap_horizontal
:
7971 case nir_intrinsic_quad_swap_vertical
:
7972 case nir_intrinsic_quad_swap_diagonal
:
7973 case nir_intrinsic_quad_swizzle_amd
: {
7974 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7975 if (!nir_dest_is_divergent(instr
->dest
)) {
7976 emit_uniform_subgroup(ctx
, instr
, src
);
7979 uint16_t dpp_ctrl
= 0;
7980 switch (instr
->intrinsic
) {
7981 case nir_intrinsic_quad_swap_horizontal
:
7982 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7984 case nir_intrinsic_quad_swap_vertical
:
7985 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7987 case nir_intrinsic_quad_swap_diagonal
:
7988 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7990 case nir_intrinsic_quad_swizzle_amd
:
7991 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7996 if (ctx
->program
->chip_class
< GFX8
)
7997 dpp_ctrl
|= (1 << 15);
7999 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8000 if (instr
->dest
.ssa
.bit_size
== 1) {
8001 assert(src
.regClass() == bld
.lm
);
8002 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8003 if (ctx
->program
->chip_class
>= GFX8
)
8004 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8006 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8007 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8008 emit_wqm(ctx
, tmp
, dst
);
8009 } else if (instr
->dest
.ssa
.bit_size
== 8) {
8010 Temp tmp
= bld
.tmp(v1
);
8011 if (ctx
->program
->chip_class
>= GFX8
)
8012 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8014 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8015 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
8016 } else if (instr
->dest
.ssa
.bit_size
== 16) {
8017 Temp tmp
= bld
.tmp(v1
);
8018 if (ctx
->program
->chip_class
>= GFX8
)
8019 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8021 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
8022 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
8023 } else if (instr
->dest
.ssa
.bit_size
== 32) {
8025 if (ctx
->program
->chip_class
>= GFX8
)
8026 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8028 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
8029 emit_wqm(ctx
, tmp
, dst
);
8030 } else if (instr
->dest
.ssa
.bit_size
== 64) {
8031 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8032 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8033 if (ctx
->program
->chip_class
>= GFX8
) {
8034 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8035 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8037 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
8038 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
8040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8041 emit_split_vector(ctx
, dst
, 2);
8043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8044 nir_print_instr(&instr
->instr
, stderr
);
8045 fprintf(stderr
, "\n");
8049 case nir_intrinsic_masked_swizzle_amd
: {
8050 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8051 if (!nir_dest_is_divergent(instr
->dest
)) {
8052 emit_uniform_subgroup(ctx
, instr
, src
);
8055 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8056 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
8057 if (instr
->dest
.ssa
.bit_size
== 1) {
8058 assert(src
.regClass() == bld
.lm
);
8059 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
8060 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
8061 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
8062 emit_wqm(ctx
, tmp
, dst
);
8063 } else if (dst
.regClass() == v1b
) {
8064 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8065 emit_extract_vector(ctx
, tmp
, 0, dst
);
8066 } else if (dst
.regClass() == v2b
) {
8067 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
8068 emit_extract_vector(ctx
, tmp
, 0, dst
);
8069 } else if (dst
.regClass() == v1
) {
8070 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
8071 } else if (dst
.regClass() == v2
) {
8072 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
8073 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
8074 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
8075 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
8076 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8077 emit_split_vector(ctx
, dst
, 2);
8079 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8080 nir_print_instr(&instr
->instr
, stderr
);
8081 fprintf(stderr
, "\n");
8085 case nir_intrinsic_write_invocation_amd
: {
8086 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
8087 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
8088 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
8089 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8090 if (dst
.regClass() == v1
) {
8091 /* src2 is ignored for writelane. RA assigns the same reg for dst */
8092 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
8093 } else if (dst
.regClass() == v2
) {
8094 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
8095 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
8096 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
8097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
8098 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
8099 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
8100 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
8101 emit_split_vector(ctx
, dst
, 2);
8103 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
8104 nir_print_instr(&instr
->instr
, stderr
);
8105 fprintf(stderr
, "\n");
8109 case nir_intrinsic_mbcnt_amd
: {
8110 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8111 RegClass rc
= RegClass(src
.type(), 1);
8112 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
8113 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
8114 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8115 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
8116 emit_wqm(ctx
, wqm_tmp
, dst
);
8119 case nir_intrinsic_load_helper_invocation
: {
8120 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8121 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8122 ctx
->block
->kind
|= block_kind_needs_lowering
;
8123 ctx
->program
->needs_exact
= true;
8126 case nir_intrinsic_is_helper_invocation
: {
8127 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8128 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8129 ctx
->block
->kind
|= block_kind_needs_lowering
;
8130 ctx
->program
->needs_exact
= true;
8133 case nir_intrinsic_demote
:
8134 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8136 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8137 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8138 ctx
->block
->kind
|= block_kind_uses_demote
;
8139 ctx
->program
->needs_exact
= true;
8141 case nir_intrinsic_demote_if
: {
8142 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8143 assert(src
.regClass() == bld
.lm
);
8144 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8145 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8147 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8148 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8149 ctx
->block
->kind
|= block_kind_uses_demote
;
8150 ctx
->program
->needs_exact
= true;
8153 case nir_intrinsic_first_invocation
: {
8154 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8155 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8158 case nir_intrinsic_shader_clock
: {
8159 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8160 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
8161 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
8162 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
8163 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
8166 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8167 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8168 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
8170 emit_split_vector(ctx
, dst
, 2);
8173 case nir_intrinsic_load_vertex_id_zero_base
: {
8174 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8175 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8178 case nir_intrinsic_load_first_vertex
: {
8179 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8180 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8183 case nir_intrinsic_load_base_instance
: {
8184 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8185 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8188 case nir_intrinsic_load_instance_id
: {
8189 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8190 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8193 case nir_intrinsic_load_draw_id
: {
8194 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8195 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8198 case nir_intrinsic_load_invocation_id
: {
8199 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8201 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8202 if (ctx
->options
->chip_class
>= GFX10
)
8203 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8205 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8206 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8207 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8208 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8210 unreachable("Unsupported stage for load_invocation_id");
8215 case nir_intrinsic_load_primitive_id
: {
8216 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8218 switch (ctx
->shader
->info
.stage
) {
8219 case MESA_SHADER_GEOMETRY
:
8220 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8222 case MESA_SHADER_TESS_CTRL
:
8223 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8225 case MESA_SHADER_TESS_EVAL
:
8226 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8229 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8234 case nir_intrinsic_load_patch_vertices_in
: {
8235 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8236 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8238 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8239 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8242 case nir_intrinsic_emit_vertex_with_counter
: {
8243 visit_emit_vertex_with_counter(ctx
, instr
);
8246 case nir_intrinsic_end_primitive_with_counter
: {
8247 unsigned stream
= nir_intrinsic_stream_id(instr
);
8248 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8251 case nir_intrinsic_set_vertex_count
: {
8252 /* unused, the HW keeps track of this for us */
8256 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8257 nir_print_instr(&instr
->instr
, stderr
);
8258 fprintf(stderr
, "\n");
8266 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8267 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8268 enum glsl_base_type
*stype
)
8270 nir_deref_instr
*texture_deref_instr
= NULL
;
8271 nir_deref_instr
*sampler_deref_instr
= NULL
;
8274 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8275 switch (instr
->src
[i
].src_type
) {
8276 case nir_tex_src_texture_deref
:
8277 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8279 case nir_tex_src_sampler_deref
:
8280 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8282 case nir_tex_src_plane
:
8283 plane
= nir_src_as_int(instr
->src
[i
].src
);
8290 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8292 if (!sampler_deref_instr
)
8293 sampler_deref_instr
= texture_deref_instr
;
8296 assert(instr
->op
!= nir_texop_txf_ms
&&
8297 instr
->op
!= nir_texop_samples_identical
);
8298 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8299 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8300 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8301 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8302 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8303 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8305 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8308 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8310 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8311 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8312 Builder
bld(ctx
->program
, ctx
->block
);
8314 /* to avoid unnecessary moves, we split and recombine sampler and image */
8315 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8316 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8317 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8318 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8319 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8320 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8322 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8324 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8325 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8326 img
[0], img
[1], img
[2], img
[3],
8327 img
[4], img
[5], img
[6], img
[7]);
8328 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8329 samp
[0], samp
[1], samp
[2], samp
[3]);
8332 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8333 instr
->op
== nir_texop_samples_identical
))
8334 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8337 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8338 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8340 Builder
bld(ctx
->program
, ctx
->block
);
8342 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8343 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8344 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8346 Operand
neg_one(0xbf800000u
);
8347 Operand
one(0x3f800000u
);
8348 Operand
two(0x40000000u
);
8349 Operand
four(0x40800000u
);
8351 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8352 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8353 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8355 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8356 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8357 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8358 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8361 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8362 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8363 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8365 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8368 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8369 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8370 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8373 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8374 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8376 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8377 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8380 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8382 Builder
bld(ctx
->program
, ctx
->block
);
8383 Temp ma
, tc
, sc
, id
;
8386 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8388 // see comment in ac_prepare_cube_coords()
8389 if (ctx
->options
->chip_class
<= GFX8
)
8390 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8393 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8395 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8396 vop3a
->operands
[0] = Operand(ma
);
8397 vop3a
->abs
[0] = true;
8398 Temp invma
= bld
.tmp(v1
);
8399 vop3a
->definitions
[0] = Definition(invma
);
8400 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8402 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8404 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8406 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8408 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8410 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8413 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8414 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8416 for (unsigned i
= 0; i
< 2; i
++) {
8417 // see comment in ac_prepare_cube_coords()
8419 Temp deriv_sc
, deriv_tc
;
8420 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8421 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8423 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8425 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8426 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8427 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8428 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8429 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8430 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8431 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8434 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8435 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8439 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8446 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8448 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8450 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8451 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8454 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8455 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8456 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8460 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8462 Builder
bld(ctx
->program
, ctx
->block
);
8463 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8464 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8465 has_clamped_lod
= false;
8466 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8467 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8468 clamped_lod
= Temp();
8469 std::vector
<Temp
> coords
;
8470 std::vector
<Temp
> derivs
;
8471 nir_const_value
*sample_index_cv
= NULL
;
8472 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8473 enum glsl_base_type stype
;
8474 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8476 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8477 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8478 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8479 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8481 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8482 switch (instr
->src
[i
].src_type
) {
8483 case nir_tex_src_coord
: {
8484 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8485 for (unsigned i
= 0; i
< coord
.size(); i
++)
8486 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8489 case nir_tex_src_bias
:
8490 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8493 case nir_tex_src_lod
: {
8494 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8496 if (val
&& val
->f32
<= 0.0) {
8499 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8504 case nir_tex_src_min_lod
:
8505 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8506 has_clamped_lod
= true;
8508 case nir_tex_src_comparator
:
8509 if (instr
->is_shadow
) {
8510 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8514 case nir_tex_src_offset
:
8515 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8516 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8519 case nir_tex_src_ddx
:
8520 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8523 case nir_tex_src_ddy
:
8524 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8527 case nir_tex_src_ms_index
:
8528 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8529 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8530 has_sample_index
= true;
8532 case nir_tex_src_texture_offset
:
8533 case nir_tex_src_sampler_offset
:
8539 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8540 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8542 if (instr
->op
== nir_texop_texture_samples
) {
8543 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8545 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8546 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8547 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8549 Operand default_sample
= Operand(1u);
8550 if (ctx
->options
->robust_buffer_access
) {
8551 /* Extract the second dword of the descriptor, if it's
8552 * all zero, then it's a null descriptor.
8554 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8555 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8556 default_sample
= Operand(is_non_null_descriptor
);
8559 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8560 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8561 samples
, default_sample
, bld
.scc(is_msaa
));
8565 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8566 aco_ptr
<Instruction
> tmp_instr
;
8567 Temp acc
, pack
= Temp();
8569 uint32_t pack_const
= 0;
8570 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8571 if (!const_offset
[i
])
8573 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8576 if (offset
.type() == RegType::sgpr
) {
8577 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8578 if (const_offset
[i
])
8581 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8582 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8585 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8588 if (pack
== Temp()) {
8591 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8595 if (pack_const
&& pack
!= Temp())
8596 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8598 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8599 if (const_offset
[i
])
8602 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8603 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8606 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8609 if (pack
== Temp()) {
8612 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8616 if (pack_const
&& pack
!= Temp())
8617 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8619 if (pack_const
&& pack
== Temp())
8620 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8621 else if (pack
== Temp())
8627 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8628 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8630 /* pack derivatives */
8631 if (has_ddx
|| has_ddy
) {
8632 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8633 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8634 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8635 derivs
= {ddx
, zero
, ddy
, zero
};
8637 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8638 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8639 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8640 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8645 if (instr
->coord_components
> 1 &&
8646 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8648 instr
->op
!= nir_texop_txf
)
8649 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8651 if (instr
->coord_components
> 2 &&
8652 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8653 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8654 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8655 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8657 instr
->op
!= nir_texop_txf
&&
8658 instr
->op
!= nir_texop_txf_ms
&&
8659 instr
->op
!= nir_texop_fragment_fetch
&&
8660 instr
->op
!= nir_texop_fragment_mask_fetch
)
8661 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8663 if (ctx
->options
->chip_class
== GFX9
&&
8664 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8665 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8666 assert(coords
.size() > 0 && coords
.size() < 3);
8668 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8669 Operand((uint32_t) 0) :
8670 Operand((uint32_t) 0x3f000000)));
8673 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8675 if (instr
->op
== nir_texop_samples_identical
)
8676 resource
= fmask_ptr
;
8678 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8679 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8680 instr
->op
!= nir_texop_txs
&&
8681 instr
->op
!= nir_texop_fragment_fetch
&&
8682 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8683 assert(has_sample_index
);
8684 Operand
op(sample_index
);
8685 if (sample_index_cv
)
8686 op
= Operand(sample_index_cv
->u32
);
8687 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8690 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8691 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8692 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8693 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8698 /* Build tex instruction */
8699 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8700 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8701 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8703 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8706 /* gather4 selects the component by dmask and always returns vec4 */
8707 if (instr
->op
== nir_texop_tg4
) {
8708 assert(instr
->dest
.ssa
.num_components
== 4);
8709 if (instr
->is_shadow
)
8712 dmask
= 1 << instr
->component
;
8713 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8714 tmp_dst
= bld
.tmp(v4
);
8715 } else if (instr
->op
== nir_texop_samples_identical
) {
8716 tmp_dst
= bld
.tmp(v1
);
8717 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8718 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8721 aco_ptr
<MIMG_instruction
> tex
;
8722 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8724 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8726 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8727 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8730 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8731 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8733 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8734 tex
->operands
[0] = Operand(resource
);
8735 tex
->operands
[1] = Operand(s4
); /* no sampler */
8736 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8737 if (ctx
->options
->chip_class
== GFX9
&&
8738 instr
->op
== nir_texop_txs
&&
8739 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8741 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8742 } else if (instr
->op
== nir_texop_query_levels
) {
8743 tex
->dmask
= 1 << 3;
8748 tex
->definitions
[0] = Definition(tmp_dst
);
8750 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8753 /* divide 3rd value by 6 by multiplying with magic number */
8754 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8755 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8756 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8757 assert(instr
->dest
.ssa
.num_components
== 3);
8758 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8759 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8760 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8761 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8766 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8770 Temp tg4_compare_cube_wa64
= Temp();
8772 if (tg4_integer_workarounds
) {
8773 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8774 tex
->operands
[0] = Operand(resource
);
8775 tex
->operands
[1] = Operand(s4
); /* no sampler */
8776 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8780 Temp size
= bld
.tmp(v2
);
8781 tex
->definitions
[0] = Definition(size
);
8782 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8783 emit_split_vector(ctx
, size
, size
.size());
8786 for (unsigned i
= 0; i
< 2; i
++) {
8787 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8788 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8789 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8790 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8793 Temp new_coords
[2] = {
8794 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8795 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8798 if (tg4_integer_cube_workaround
) {
8799 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8800 Temp desc
[resource
.size()];
8801 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8802 Format::PSEUDO
, 1, resource
.size())};
8803 split
->operands
[0] = Operand(resource
);
8804 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8805 desc
[i
] = bld
.tmp(s1
);
8806 split
->definitions
[i
] = Definition(desc
[i
]);
8808 ctx
->block
->instructions
.emplace_back(std::move(split
));
8810 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8811 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8812 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8815 if (stype
== GLSL_TYPE_UINT
) {
8816 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8817 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8818 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8819 bld
.scc(compare_cube_wa
));
8821 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8822 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8823 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8824 bld
.scc(compare_cube_wa
));
8826 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8827 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8829 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8831 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8832 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8833 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8835 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8836 Format::PSEUDO
, resource
.size(), 1)};
8837 for (unsigned i
= 0; i
< resource
.size(); i
++)
8838 vec
->operands
[i
] = Operand(desc
[i
]);
8839 resource
= bld
.tmp(resource
.regClass());
8840 vec
->definitions
[0] = Definition(resource
);
8841 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8843 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8844 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8845 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8846 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8848 coords
[0] = new_coords
[0];
8849 coords
[1] = new_coords
[1];
8852 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8853 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8855 assert(coords
.size() == 1);
8856 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8860 op
= aco_opcode::buffer_load_format_x
; break;
8862 op
= aco_opcode::buffer_load_format_xy
; break;
8864 op
= aco_opcode::buffer_load_format_xyz
; break;
8866 op
= aco_opcode::buffer_load_format_xyzw
; break;
8868 unreachable("Tex instruction loads more than 4 components.");
8871 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8872 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8875 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8877 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8878 mubuf
->operands
[0] = Operand(resource
);
8879 mubuf
->operands
[1] = Operand(coords
[0]);
8880 mubuf
->operands
[2] = Operand((uint32_t) 0);
8881 mubuf
->definitions
[0] = Definition(tmp_dst
);
8882 mubuf
->idxen
= true;
8883 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8885 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8889 /* gather MIMG address components */
8890 std::vector
<Temp
> args
;
8892 args
.emplace_back(offset
);
8894 args
.emplace_back(bias
);
8896 args
.emplace_back(compare
);
8898 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8900 args
.insert(args
.end(), coords
.begin(), coords
.end());
8901 if (has_sample_index
)
8902 args
.emplace_back(sample_index
);
8904 args
.emplace_back(lod
);
8905 if (has_clamped_lod
)
8906 args
.emplace_back(clamped_lod
);
8908 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8909 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8910 vec
->definitions
[0] = Definition(arg
);
8911 for (unsigned i
= 0; i
< args
.size(); i
++)
8912 vec
->operands
[i
] = Operand(args
[i
]);
8913 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8916 if (instr
->op
== nir_texop_txf
||
8917 instr
->op
== nir_texop_txf_ms
||
8918 instr
->op
== nir_texop_samples_identical
||
8919 instr
->op
== nir_texop_fragment_fetch
||
8920 instr
->op
== nir_texop_fragment_mask_fetch
) {
8921 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8922 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8923 tex
->operands
[0] = Operand(resource
);
8924 tex
->operands
[1] = Operand(s4
); /* no sampler */
8925 tex
->operands
[2] = Operand(arg
);
8930 tex
->definitions
[0] = Definition(tmp_dst
);
8931 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8933 if (instr
->op
== nir_texop_samples_identical
) {
8934 assert(dmask
== 1 && dst
.regClass() == v1
);
8935 assert(dst
.id() != tmp_dst
.id());
8937 Temp tmp
= bld
.tmp(bld
.lm
);
8938 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8939 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8942 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8947 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8948 aco_opcode opcode
= aco_opcode::image_sample
;
8949 if (has_offset
) { /* image_sample_*_o */
8950 if (has_clamped_lod
) {
8952 opcode
= aco_opcode::image_sample_c_cl_o
;
8954 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8956 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8958 opcode
= aco_opcode::image_sample_cl_o
;
8960 opcode
= aco_opcode::image_sample_d_cl_o
;
8962 opcode
= aco_opcode::image_sample_b_cl_o
;
8964 } else if (has_compare
) {
8965 opcode
= aco_opcode::image_sample_c_o
;
8967 opcode
= aco_opcode::image_sample_c_d_o
;
8969 opcode
= aco_opcode::image_sample_c_b_o
;
8971 opcode
= aco_opcode::image_sample_c_lz_o
;
8973 opcode
= aco_opcode::image_sample_c_l_o
;
8975 opcode
= aco_opcode::image_sample_o
;
8977 opcode
= aco_opcode::image_sample_d_o
;
8979 opcode
= aco_opcode::image_sample_b_o
;
8981 opcode
= aco_opcode::image_sample_lz_o
;
8983 opcode
= aco_opcode::image_sample_l_o
;
8985 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8987 opcode
= aco_opcode::image_sample_c_cl
;
8989 opcode
= aco_opcode::image_sample_c_d_cl
;
8991 opcode
= aco_opcode::image_sample_c_b_cl
;
8993 opcode
= aco_opcode::image_sample_cl
;
8995 opcode
= aco_opcode::image_sample_d_cl
;
8997 opcode
= aco_opcode::image_sample_b_cl
;
8999 } else { /* no offset */
9001 opcode
= aco_opcode::image_sample_c
;
9003 opcode
= aco_opcode::image_sample_c_d
;
9005 opcode
= aco_opcode::image_sample_c_b
;
9007 opcode
= aco_opcode::image_sample_c_lz
;
9009 opcode
= aco_opcode::image_sample_c_l
;
9011 opcode
= aco_opcode::image_sample
;
9013 opcode
= aco_opcode::image_sample_d
;
9015 opcode
= aco_opcode::image_sample_b
;
9017 opcode
= aco_opcode::image_sample_lz
;
9019 opcode
= aco_opcode::image_sample_l
;
9023 if (instr
->op
== nir_texop_tg4
) {
9024 if (has_offset
) { /* image_gather4_*_o */
9026 opcode
= aco_opcode::image_gather4_c_lz_o
;
9028 opcode
= aco_opcode::image_gather4_c_l_o
;
9030 opcode
= aco_opcode::image_gather4_c_b_o
;
9032 opcode
= aco_opcode::image_gather4_lz_o
;
9034 opcode
= aco_opcode::image_gather4_l_o
;
9036 opcode
= aco_opcode::image_gather4_b_o
;
9040 opcode
= aco_opcode::image_gather4_c_lz
;
9042 opcode
= aco_opcode::image_gather4_c_l
;
9044 opcode
= aco_opcode::image_gather4_c_b
;
9046 opcode
= aco_opcode::image_gather4_lz
;
9048 opcode
= aco_opcode::image_gather4_l
;
9050 opcode
= aco_opcode::image_gather4_b
;
9053 } else if (instr
->op
== nir_texop_lod
) {
9054 opcode
= aco_opcode::image_get_lod
;
9057 /* we don't need the bias, sample index, compare value or offset to be
9058 * computed in WQM but if the p_create_vector copies the coordinates, then it
9059 * needs to be in WQM */
9060 if (ctx
->stage
== fragment_fs
&&
9061 !has_derivs
&& !has_lod
&& !level_zero
&&
9062 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
9063 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
9064 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
9066 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
9067 tex
->operands
[0] = Operand(resource
);
9068 tex
->operands
[1] = Operand(sampler
);
9069 tex
->operands
[2] = Operand(arg
);
9073 tex
->definitions
[0] = Definition(tmp_dst
);
9074 ctx
->block
->instructions
.emplace_back(std::move(tex
));
9076 if (tg4_integer_cube_workaround
) {
9077 assert(tmp_dst
.id() != dst
.id());
9078 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
9080 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
9082 for (unsigned i
= 0; i
< dst
.size(); i
++) {
9083 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
9085 if (stype
== GLSL_TYPE_UINT
)
9086 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
9088 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
9089 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
9091 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
9092 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
9093 val
[0], val
[1], val
[2], val
[3]);
9095 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
9096 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
9101 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
9103 Temp tmp
= get_ssa_temp(ctx
, ssa
);
9104 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
9106 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
9107 if (ctx
->program
->wave_size
== 64)
9108 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
9110 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
9112 return Operand(tmp
);
9116 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
9118 aco_ptr
<Pseudo_instruction
> phi
;
9119 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
9120 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
9122 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
9123 logical
|= ctx
->block
->kind
& block_kind_merge
;
9124 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
9126 /* we want a sorted list of sources, since the predecessor list is also sorted */
9127 std::map
<unsigned, nir_ssa_def
*> phi_src
;
9128 nir_foreach_phi_src(src
, instr
)
9129 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
9131 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
9132 unsigned num_operands
= 0;
9133 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
9134 unsigned num_defined
= 0;
9135 unsigned cur_pred_idx
= 0;
9136 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
9137 if (cur_pred_idx
< preds
.size()) {
9138 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
9139 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
9140 unsigned skipped
= 0;
9141 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9143 if (cur_pred_idx
+ skipped
< preds
.size()) {
9144 for (unsigned i
= 0; i
< skipped
; i
++)
9145 operands
[num_operands
++] = Operand(dst
.regClass());
9146 cur_pred_idx
+= skipped
;
9151 /* Handle missing predecessors at the end. This shouldn't happen with loop
9152 * headers and we can't ignore these sources for loop header phis. */
9153 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9156 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9157 operands
[num_operands
++] = op
;
9158 num_defined
+= !op
.isUndefined();
9160 /* handle block_kind_continue_or_break at loop exit blocks */
9161 while (cur_pred_idx
++ < preds
.size())
9162 operands
[num_operands
++] = Operand(dst
.regClass());
9164 /* If the loop ends with a break, still add a linear continue edge in case
9165 * that break is divergent or continue_or_break is used. We'll either remove
9166 * this operand later in visit_loop() if it's not necessary or replace the
9167 * undef with something correct. */
9168 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9169 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9170 nir_block
*last
= nir_loop_last_block(loop
);
9171 if (last
->successors
[0] != instr
->instr
.block
)
9172 operands
[num_operands
++] = Operand(RegClass());
9175 if (num_defined
== 0) {
9176 Builder
bld(ctx
->program
, ctx
->block
);
9177 if (dst
.regClass() == s1
) {
9178 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9179 } else if (dst
.regClass() == v1
) {
9180 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9182 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9183 for (unsigned i
= 0; i
< dst
.size(); i
++)
9184 vec
->operands
[i
] = Operand(0u);
9185 vec
->definitions
[0] = Definition(dst
);
9186 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9191 /* we can use a linear phi in some cases if one src is undef */
9192 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9193 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9195 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9196 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9197 assert(invert
->kind
& block_kind_invert
);
9199 unsigned then_block
= invert
->linear_preds
[0];
9201 Block
* insert_block
= NULL
;
9202 for (unsigned i
= 0; i
< num_operands
; i
++) {
9203 Operand op
= operands
[i
];
9204 if (op
.isUndefined())
9206 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9207 phi
->operands
[0] = op
;
9210 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9211 phi
->operands
[1] = Operand(dst
.regClass());
9212 phi
->definitions
[0] = Definition(dst
);
9213 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9217 /* try to scalarize vector phis */
9218 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9219 // TODO: scalarize linear phis on divergent ifs
9220 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9221 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9222 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9223 Operand src
= operands
[i
];
9224 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9225 can_scalarize
= false;
9227 if (can_scalarize
) {
9228 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9229 assert(dst
.size() % num_components
== 0);
9230 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9232 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9233 for (unsigned k
= 0; k
< num_components
; k
++) {
9234 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9235 for (unsigned i
= 0; i
< num_operands
; i
++) {
9236 Operand src
= operands
[i
];
9237 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9239 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9240 phi
->definitions
[0] = Definition(phi_dst
);
9241 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9242 new_vec
[k
] = phi_dst
;
9243 vec
->operands
[k
] = Operand(phi_dst
);
9245 vec
->definitions
[0] = Definition(dst
);
9246 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9247 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9252 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9253 for (unsigned i
= 0; i
< num_operands
; i
++)
9254 phi
->operands
[i
] = operands
[i
];
9255 phi
->definitions
[0] = Definition(dst
);
9256 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9260 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9262 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9264 assert(dst
.type() == RegType::sgpr
);
9266 if (dst
.size() == 1) {
9267 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9269 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9270 for (unsigned i
= 0; i
< dst
.size(); i
++)
9271 vec
->operands
[i
] = Operand(0u);
9272 vec
->definitions
[0] = Definition(dst
);
9273 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9277 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9279 Builder
bld(ctx
->program
, ctx
->block
);
9280 Block
*logical_target
;
9281 append_logical_end(ctx
->block
);
9282 unsigned idx
= ctx
->block
->index
;
9284 switch (instr
->type
) {
9285 case nir_jump_break
:
9286 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9287 add_logical_edge(idx
, logical_target
);
9288 ctx
->block
->kind
|= block_kind_break
;
9290 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9291 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9292 /* uniform break - directly jump out of the loop */
9293 ctx
->block
->kind
|= block_kind_uniform
;
9294 ctx
->cf_info
.has_branch
= true;
9295 bld
.branch(aco_opcode::p_branch
);
9296 add_linear_edge(idx
, logical_target
);
9299 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9300 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9302 case nir_jump_continue
:
9303 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9304 add_logical_edge(idx
, logical_target
);
9305 ctx
->block
->kind
|= block_kind_continue
;
9307 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9308 /* for potential uniform breaks after this continue,
9309 we must ensure that they are handled correctly */
9310 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9311 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9312 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9314 /* uniform continue - directly jump to the loop header */
9315 ctx
->block
->kind
|= block_kind_uniform
;
9316 ctx
->cf_info
.has_branch
= true;
9317 bld
.branch(aco_opcode::p_branch
);
9318 add_linear_edge(idx
, logical_target
);
9323 fprintf(stderr
, "Unknown NIR jump instr: ");
9324 nir_print_instr(&instr
->instr
, stderr
);
9325 fprintf(stderr
, "\n");
9329 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9330 ctx
->cf_info
.exec_potentially_empty_break
= true;
9331 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9334 /* remove critical edges from linear CFG */
9335 bld
.branch(aco_opcode::p_branch
);
9336 Block
* break_block
= ctx
->program
->create_and_insert_block();
9337 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9338 break_block
->kind
|= block_kind_uniform
;
9339 add_linear_edge(idx
, break_block
);
9340 /* the loop_header pointer might be invalidated by this point */
9341 if (instr
->type
== nir_jump_continue
)
9342 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9343 add_linear_edge(break_block
->index
, logical_target
);
9344 bld
.reset(break_block
);
9345 bld
.branch(aco_opcode::p_branch
);
9347 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9348 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9349 add_linear_edge(idx
, continue_block
);
9350 append_logical_start(continue_block
);
9351 ctx
->block
= continue_block
;
9355 void visit_block(isel_context
*ctx
, nir_block
*block
)
9357 nir_foreach_instr(instr
, block
) {
9358 switch (instr
->type
) {
9359 case nir_instr_type_alu
:
9360 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9362 case nir_instr_type_load_const
:
9363 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9365 case nir_instr_type_intrinsic
:
9366 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9368 case nir_instr_type_tex
:
9369 visit_tex(ctx
, nir_instr_as_tex(instr
));
9371 case nir_instr_type_phi
:
9372 visit_phi(ctx
, nir_instr_as_phi(instr
));
9374 case nir_instr_type_ssa_undef
:
9375 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9377 case nir_instr_type_deref
:
9379 case nir_instr_type_jump
:
9380 visit_jump(ctx
, nir_instr_as_jump(instr
));
9383 fprintf(stderr
, "Unknown NIR instr type: ");
9384 nir_print_instr(instr
, stderr
);
9385 fprintf(stderr
, "\n");
9390 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9391 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9396 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9397 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9399 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9400 RegClass rc
= vals
[0].regClass();
9402 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9404 unsigned next_pred
= 1;
9406 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9407 Block
& block
= ctx
->program
->blocks
[idx
];
9408 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9409 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9413 if (block
.kind
& block_kind_continue
) {
9414 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9419 bool all_same
= true;
9420 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9421 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9425 val
= vals
[block
.linear_preds
[0] - first
];
9427 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9428 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9429 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9430 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9431 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9432 phi
->definitions
[0] = Definition(val
.getTemp());
9433 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9435 vals
[idx
- first
] = val
;
9438 return vals
[last
- first
];
9441 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9443 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9444 append_logical_end(ctx
->block
);
9445 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9446 Builder
bld(ctx
->program
, ctx
->block
);
9447 bld
.branch(aco_opcode::p_branch
);
9448 unsigned loop_preheader_idx
= ctx
->block
->index
;
9450 Block loop_exit
= Block();
9451 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9452 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9454 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9455 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9456 loop_header
->kind
|= block_kind_loop_header
;
9457 add_edge(loop_preheader_idx
, loop_header
);
9458 ctx
->block
= loop_header
;
9460 /* emit loop body */
9461 unsigned loop_header_idx
= loop_header
->index
;
9462 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9463 append_logical_start(ctx
->block
);
9464 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9466 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9467 if (!ctx
->cf_info
.has_branch
) {
9468 append_logical_end(ctx
->block
);
9469 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9470 /* Discards can result in code running with an empty exec mask.
9471 * This would result in divergent breaks not ever being taken. As a
9472 * workaround, break the loop when the loop mask is empty instead of
9473 * always continuing. */
9474 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9475 unsigned block_idx
= ctx
->block
->index
;
9477 /* create helper blocks to avoid critical edges */
9478 Block
*break_block
= ctx
->program
->create_and_insert_block();
9479 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9480 break_block
->kind
= block_kind_uniform
;
9481 bld
.reset(break_block
);
9482 bld
.branch(aco_opcode::p_branch
);
9483 add_linear_edge(block_idx
, break_block
);
9484 add_linear_edge(break_block
->index
, &loop_exit
);
9486 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9487 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9488 continue_block
->kind
= block_kind_uniform
;
9489 bld
.reset(continue_block
);
9490 bld
.branch(aco_opcode::p_branch
);
9491 add_linear_edge(block_idx
, continue_block
);
9492 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9494 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9495 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9496 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9498 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9499 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9500 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9502 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9505 bld
.reset(ctx
->block
);
9506 bld
.branch(aco_opcode::p_branch
);
9509 /* Fixup phis in loop header from unreachable blocks.
9510 * has_branch/has_divergent_branch also indicates if the loop ends with a
9511 * break/continue instruction, but we don't emit those if unreachable=true */
9513 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9514 bool linear
= ctx
->cf_info
.has_branch
;
9515 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9516 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9517 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9518 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9519 /* the last operand should be the one that needs to be removed */
9520 instr
->operands
.pop_back();
9521 } else if (!is_phi(instr
)) {
9527 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9528 * and the previous one shouldn't both happen at once because a break in the
9529 * merge block would get CSE'd */
9530 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9531 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9532 Operand vals
[num_vals
];
9533 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9534 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9535 if (ctx
->cf_info
.has_branch
)
9536 instr
->operands
.pop_back();
9538 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9539 } else if (!is_phi(instr
)) {
9545 ctx
->cf_info
.has_branch
= false;
9547 // TODO: if the loop has not a single exit, we must add one °°
9548 /* emit loop successor block */
9549 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9550 append_logical_start(ctx
->block
);
9553 // TODO: check if it is beneficial to not branch on continues
9554 /* trim linear phis in loop header */
9555 for (auto&& instr
: loop_entry
->instructions
) {
9556 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9557 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9558 new_phi
->definitions
[0] = instr
->definitions
[0];
9559 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9560 new_phi
->operands
[i
] = instr
->operands
[i
];
9561 /* check that the remaining operands are all the same */
9562 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9563 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9564 instr
.swap(new_phi
);
9565 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9574 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9578 append_logical_end(ctx
->block
);
9579 ctx
->block
->kind
|= block_kind_branch
;
9581 /* branch to linear then block */
9582 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9583 aco_ptr
<Pseudo_branch_instruction
> branch
;
9584 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9585 branch
->operands
[0] = Operand(cond
);
9586 ctx
->block
->instructions
.push_back(std::move(branch
));
9588 ic
->BB_if_idx
= ctx
->block
->index
;
9589 ic
->BB_invert
= Block();
9590 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9591 /* Invert blocks are intentionally not marked as top level because they
9592 * are not part of the logical cfg. */
9593 ic
->BB_invert
.kind
|= block_kind_invert
;
9594 ic
->BB_endif
= Block();
9595 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9596 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9598 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9599 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9600 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9601 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9602 ctx
->cf_info
.parent_if
.is_divergent
= true;
9604 /* divergent branches use cbranch_execz */
9605 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9606 ctx
->cf_info
.exec_potentially_empty_break
= false;
9607 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9609 /** emit logical then block */
9610 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9611 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9612 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9613 ctx
->block
= BB_then_logical
;
9614 append_logical_start(BB_then_logical
);
9617 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9619 Block
*BB_then_logical
= ctx
->block
;
9620 append_logical_end(BB_then_logical
);
9621 /* branch from logical then block to invert block */
9622 aco_ptr
<Pseudo_branch_instruction
> branch
;
9623 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9624 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9625 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9626 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9627 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9628 BB_then_logical
->kind
|= block_kind_uniform
;
9629 assert(!ctx
->cf_info
.has_branch
);
9630 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9631 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9633 /** emit linear then block */
9634 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9635 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9636 BB_then_linear
->kind
|= block_kind_uniform
;
9637 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9638 /* branch from linear then block to invert block */
9639 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9640 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9641 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9643 /** emit invert merge block */
9644 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9645 ic
->invert_idx
= ctx
->block
->index
;
9647 /* branch to linear else block (skip else) */
9648 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9649 branch
->operands
[0] = Operand(ic
->cond
);
9650 ctx
->block
->instructions
.push_back(std::move(branch
));
9652 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9653 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9654 ic
->exec_potentially_empty_break_depth_old
=
9655 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9656 /* divergent branches use cbranch_execz */
9657 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9658 ctx
->cf_info
.exec_potentially_empty_break
= false;
9659 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9661 /** emit logical else block */
9662 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9663 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9664 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9665 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9666 ctx
->block
= BB_else_logical
;
9667 append_logical_start(BB_else_logical
);
9670 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9672 Block
*BB_else_logical
= ctx
->block
;
9673 append_logical_end(BB_else_logical
);
9675 /* branch from logical else block to endif block */
9676 aco_ptr
<Pseudo_branch_instruction
> branch
;
9677 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9678 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9679 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9680 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9681 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9682 BB_else_logical
->kind
|= block_kind_uniform
;
9684 assert(!ctx
->cf_info
.has_branch
);
9685 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9688 /** emit linear else block */
9689 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9690 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9691 BB_else_linear
->kind
|= block_kind_uniform
;
9692 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9694 /* branch from linear else block to endif block */
9695 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9696 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9697 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9700 /** emit endif merge block */
9701 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9702 append_logical_start(ctx
->block
);
9705 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9706 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9707 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9708 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9709 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9710 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9711 !ctx
->cf_info
.parent_if
.is_divergent
) {
9712 ctx
->cf_info
.exec_potentially_empty_break
= false;
9713 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9715 /* uniform control flow never has an empty exec-mask */
9716 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9717 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9718 ctx
->cf_info
.exec_potentially_empty_break
= false;
9719 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9723 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9725 assert(cond
.regClass() == s1
);
9727 append_logical_end(ctx
->block
);
9728 ctx
->block
->kind
|= block_kind_uniform
;
9730 aco_ptr
<Pseudo_branch_instruction
> branch
;
9731 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9732 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9733 branch
->operands
[0] = Operand(cond
);
9734 branch
->operands
[0].setFixed(scc
);
9735 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9737 ic
->BB_if_idx
= ctx
->block
->index
;
9738 ic
->BB_endif
= Block();
9739 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9740 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9742 ctx
->cf_info
.has_branch
= false;
9743 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9745 /** emit then block */
9746 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9747 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9748 add_edge(ic
->BB_if_idx
, BB_then
);
9749 append_logical_start(BB_then
);
9750 ctx
->block
= BB_then
;
9753 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9755 Block
*BB_then
= ctx
->block
;
9757 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9758 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9760 if (!ic
->uniform_has_then_branch
) {
9761 append_logical_end(BB_then
);
9762 /* branch from then block to endif block */
9763 aco_ptr
<Pseudo_branch_instruction
> branch
;
9764 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9765 BB_then
->instructions
.emplace_back(std::move(branch
));
9766 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9767 if (!ic
->then_branch_divergent
)
9768 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9769 BB_then
->kind
|= block_kind_uniform
;
9772 ctx
->cf_info
.has_branch
= false;
9773 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9775 /** emit else block */
9776 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9777 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9778 add_edge(ic
->BB_if_idx
, BB_else
);
9779 append_logical_start(BB_else
);
9780 ctx
->block
= BB_else
;
9783 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9785 Block
*BB_else
= ctx
->block
;
9787 if (!ctx
->cf_info
.has_branch
) {
9788 append_logical_end(BB_else
);
9789 /* branch from then block to endif block */
9790 aco_ptr
<Pseudo_branch_instruction
> branch
;
9791 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9792 BB_else
->instructions
.emplace_back(std::move(branch
));
9793 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9794 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9795 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9796 BB_else
->kind
|= block_kind_uniform
;
9799 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9800 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9802 /** emit endif merge block */
9803 if (!ctx
->cf_info
.has_branch
) {
9804 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9805 append_logical_start(ctx
->block
);
9809 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9811 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9812 Builder
bld(ctx
->program
, ctx
->block
);
9813 aco_ptr
<Pseudo_branch_instruction
> branch
;
9816 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9818 * Uniform conditionals are represented in the following way*) :
9820 * The linear and logical CFG:
9823 * BB_THEN (logical) BB_ELSE (logical)
9827 * *) Exceptions may be due to break and continue statements within loops
9828 * If a break/continue happens within uniform control flow, it branches
9829 * to the loop exit/entry block. Otherwise, it branches to the next
9833 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9834 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9835 cond
= bool_to_scalar_condition(ctx
, cond
);
9837 begin_uniform_if_then(ctx
, &ic
, cond
);
9838 visit_cf_list(ctx
, &if_stmt
->then_list
);
9840 begin_uniform_if_else(ctx
, &ic
);
9841 visit_cf_list(ctx
, &if_stmt
->else_list
);
9843 end_uniform_if(ctx
, &ic
);
9844 } else { /* non-uniform condition */
9846 * To maintain a logical and linear CFG without critical edges,
9847 * non-uniform conditionals are represented in the following way*) :
9852 * BB_THEN (logical) BB_THEN (linear)
9854 * BB_INVERT (linear)
9856 * BB_ELSE (logical) BB_ELSE (linear)
9863 * BB_THEN (logical) BB_ELSE (logical)
9867 * *) Exceptions may be due to break and continue statements within loops
9870 begin_divergent_if_then(ctx
, &ic
, cond
);
9871 visit_cf_list(ctx
, &if_stmt
->then_list
);
9873 begin_divergent_if_else(ctx
, &ic
);
9874 visit_cf_list(ctx
, &if_stmt
->else_list
);
9876 end_divergent_if(ctx
, &ic
);
9879 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9882 static bool visit_cf_list(isel_context
*ctx
,
9883 struct exec_list
*list
)
9885 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9886 switch (node
->type
) {
9887 case nir_cf_node_block
:
9888 visit_block(ctx
, nir_cf_node_as_block(node
));
9890 case nir_cf_node_if
:
9891 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9894 case nir_cf_node_loop
:
9895 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9898 unreachable("unimplemented cf list type");
9904 static void create_null_export(isel_context
*ctx
)
9906 /* Some shader stages always need to have exports.
9907 * So when there is none, we need to add a null export.
9910 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9911 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9912 Builder
bld(ctx
->program
, ctx
->block
);
9913 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9914 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9917 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9919 assert(ctx
->stage
== vertex_vs
||
9920 ctx
->stage
== tess_eval_vs
||
9921 ctx
->stage
== gs_copy_vs
||
9922 ctx
->stage
== ngg_vertex_gs
||
9923 ctx
->stage
== ngg_tess_eval_gs
);
9925 int offset
= (ctx
->stage
& sw_tes
)
9926 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9927 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9928 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9929 if (!is_pos
&& !mask
)
9931 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9933 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9934 exp
->enabled_mask
= mask
;
9935 for (unsigned i
= 0; i
< 4; ++i
) {
9936 if (mask
& (1 << i
))
9937 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9939 exp
->operands
[i
] = Operand(v1
);
9941 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9942 * Setting valid_mask=1 prevents it and has no other effect.
9944 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9946 exp
->compressed
= false;
9948 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9950 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9951 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9956 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9958 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9959 exp
->enabled_mask
= 0;
9960 for (unsigned i
= 0; i
< 4; ++i
)
9961 exp
->operands
[i
] = Operand(v1
);
9962 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9963 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9964 exp
->enabled_mask
|= 0x1;
9966 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9967 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9968 exp
->enabled_mask
|= 0x4;
9970 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9971 if (ctx
->options
->chip_class
< GFX9
) {
9972 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9973 exp
->enabled_mask
|= 0x8;
9975 Builder
bld(ctx
->program
, ctx
->block
);
9977 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9978 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9979 if (exp
->operands
[2].isTemp())
9980 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9982 exp
->operands
[2] = Operand(out
);
9983 exp
->enabled_mask
|= 0x4;
9986 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9988 exp
->compressed
= false;
9989 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9990 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9993 static void create_export_phis(isel_context
*ctx
)
9995 /* Used when exports are needed, but the output temps are defined in a preceding block.
9996 * This function will set up phis in order to access the outputs in the next block.
9999 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
10000 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
10001 ctx
->block
->instructions
.pop_back();
10003 Builder
bld(ctx
->program
, ctx
->block
);
10005 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
10006 uint64_t mask
= ctx
->outputs
.mask
[slot
];
10007 for (unsigned i
= 0; i
< 4; ++i
) {
10008 if (!(mask
& (1 << i
)))
10011 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
10012 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
10013 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
10017 bld
.insert(std::move(logical_start
));
10020 static void create_vs_exports(isel_context
*ctx
)
10022 assert(ctx
->stage
== vertex_vs
||
10023 ctx
->stage
== tess_eval_vs
||
10024 ctx
->stage
== gs_copy_vs
||
10025 ctx
->stage
== ngg_vertex_gs
||
10026 ctx
->stage
== ngg_tess_eval_gs
);
10028 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
10029 ? &ctx
->program
->info
->tes
.outinfo
10030 : &ctx
->program
->info
->vs
.outinfo
;
10032 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
10033 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10034 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
10037 if (ctx
->options
->key
.has_multiview_view_index
) {
10038 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
10039 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
10042 /* the order these position exports are created is important */
10044 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
10045 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
10046 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
10047 exported_pos
= true;
10049 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10050 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
10051 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10052 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
10054 if (ctx
->export_clip_dists
) {
10055 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
10056 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
10057 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
10058 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
10061 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10062 if (i
< VARYING_SLOT_VAR0
&&
10063 i
!= VARYING_SLOT_LAYER
&&
10064 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
10065 i
!= VARYING_SLOT_VIEWPORT
)
10068 export_vs_varying(ctx
, i
, false, NULL
);
10072 create_null_export(ctx
);
10075 static bool export_fs_mrt_z(isel_context
*ctx
)
10077 Builder
bld(ctx
->program
, ctx
->block
);
10078 unsigned enabled_channels
= 0;
10079 bool compr
= false;
10082 for (unsigned i
= 0; i
< 4; ++i
) {
10083 values
[i
] = Operand(v1
);
10086 /* Both stencil and sample mask only need 16-bits. */
10087 if (!ctx
->program
->info
->ps
.writes_z
&&
10088 (ctx
->program
->info
->ps
.writes_stencil
||
10089 ctx
->program
->info
->ps
.writes_sample_mask
)) {
10090 compr
= true; /* COMPR flag */
10092 if (ctx
->program
->info
->ps
.writes_stencil
) {
10093 /* Stencil should be in X[23:16]. */
10094 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10095 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
10096 enabled_channels
|= 0x3;
10099 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10100 /* SampleMask should be in Y[15:0]. */
10101 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10102 enabled_channels
|= 0xc;
10105 if (ctx
->program
->info
->ps
.writes_z
) {
10106 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
10107 enabled_channels
|= 0x1;
10110 if (ctx
->program
->info
->ps
.writes_stencil
) {
10111 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
10112 enabled_channels
|= 0x2;
10115 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
10116 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
10117 enabled_channels
|= 0x4;
10121 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
10122 * writemask component.
10124 if (ctx
->options
->chip_class
== GFX6
&&
10125 ctx
->options
->family
!= CHIP_OLAND
&&
10126 ctx
->options
->family
!= CHIP_HAINAN
) {
10127 enabled_channels
|= 0x1;
10130 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10131 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
10136 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
10138 Builder
bld(ctx
->program
, ctx
->block
);
10139 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
10142 for (unsigned i
= 0; i
< 4; ++i
) {
10143 if (write_mask
& (1 << i
)) {
10144 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
10146 values
[i
] = Operand(v1
);
10150 unsigned target
, col_format
;
10151 unsigned enabled_channels
= 0;
10152 aco_opcode compr_op
= (aco_opcode
)0;
10154 slot
-= FRAG_RESULT_DATA0
;
10155 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10156 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10158 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10159 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10160 bool is_16bit
= values
[0].regClass() == v2b
;
10162 switch (col_format
)
10164 case V_028714_SPI_SHADER_ZERO
:
10165 enabled_channels
= 0; /* writemask */
10166 target
= V_008DFC_SQ_EXP_NULL
;
10169 case V_028714_SPI_SHADER_32_R
:
10170 enabled_channels
= 1;
10173 case V_028714_SPI_SHADER_32_GR
:
10174 enabled_channels
= 0x3;
10177 case V_028714_SPI_SHADER_32_AR
:
10178 if (ctx
->options
->chip_class
>= GFX10
) {
10179 /* Special case: on GFX10, the outputs are different for 32_AR */
10180 enabled_channels
= 0x3;
10181 values
[1] = values
[3];
10182 values
[3] = Operand(v1
);
10184 enabled_channels
= 0x9;
10188 case V_028714_SPI_SHADER_FP16_ABGR
:
10189 enabled_channels
= 0x5;
10190 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10192 if (ctx
->options
->chip_class
>= GFX9
) {
10193 /* Pack the FP16 values together instead of converting them to
10194 * FP32 and back to FP16.
10195 * TODO: use p_create_vector and let the compiler optimizes.
10197 compr_op
= aco_opcode::v_pack_b32_f16
;
10199 for (unsigned i
= 0; i
< 4; i
++) {
10200 if ((write_mask
>> i
) & 1)
10201 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10207 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10208 enabled_channels
= 0x5;
10209 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10210 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10212 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10216 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10217 enabled_channels
= 0x5;
10218 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10219 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10221 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10225 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10226 enabled_channels
= 0x5;
10227 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10228 if (is_int8
|| is_int10
) {
10230 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10231 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10233 for (unsigned i
= 0; i
< 4; i
++) {
10234 if ((write_mask
>> i
) & 1) {
10235 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10236 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10240 } else if (is_16bit
) {
10241 for (unsigned i
= 0; i
< 4; i
++) {
10242 if ((write_mask
>> i
) & 1) {
10243 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10244 values
[i
] = Operand(tmp
);
10251 case V_028714_SPI_SHADER_SINT16_ABGR
:
10252 enabled_channels
= 0x5;
10253 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10254 if (is_int8
|| is_int10
) {
10256 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10257 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10258 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10259 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10261 for (unsigned i
= 0; i
< 4; i
++) {
10262 if ((write_mask
>> i
) & 1) {
10263 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10264 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10266 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10267 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10271 } else if (is_16bit
) {
10272 for (unsigned i
= 0; i
< 4; i
++) {
10273 if ((write_mask
>> i
) & 1) {
10274 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10275 values
[i
] = Operand(tmp
);
10281 case V_028714_SPI_SHADER_32_ABGR
:
10282 enabled_channels
= 0xF;
10289 if (target
== V_008DFC_SQ_EXP_NULL
)
10292 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10293 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10295 (col_format
== V_028714_SPI_SHADER_32_R
||
10296 col_format
== V_028714_SPI_SHADER_32_GR
||
10297 col_format
== V_028714_SPI_SHADER_32_AR
||
10298 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10299 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10300 for (int i
= 0; i
< 4; i
++) {
10301 if (!(write_mask
& (1 << i
)))
10304 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10305 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10306 bld
.copy(bld
.def(v1
), Operand(3u)));
10307 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10308 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10312 if ((bool) compr_op
) {
10313 for (int i
= 0; i
< 2; i
++) {
10314 /* check if at least one of the values to be compressed is enabled */
10315 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10317 enabled_channels
|= enabled
<< (i
*2);
10318 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10319 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10320 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10322 values
[i
] = Operand(v1
);
10325 values
[2] = Operand(v1
);
10326 values
[3] = Operand(v1
);
10328 for (int i
= 0; i
< 4; i
++)
10329 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10332 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10333 enabled_channels
, target
, (bool) compr_op
);
10337 static void create_fs_exports(isel_context
*ctx
)
10339 bool exported
= false;
10341 /* Export depth, stencil and sample mask. */
10342 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10343 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10344 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10345 exported
|= export_fs_mrt_z(ctx
);
10347 /* Export all color render targets. */
10348 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10349 if (ctx
->outputs
.mask
[i
])
10350 exported
|= export_fs_mrt_color(ctx
, i
);
10353 create_null_export(ctx
);
10356 static void create_workgroup_barrier(Builder
& bld
)
10358 bld
.barrier(aco_opcode::p_barrier
,
10359 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10363 static void write_tcs_tess_factors(isel_context
*ctx
)
10365 unsigned outer_comps
;
10366 unsigned inner_comps
;
10368 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10385 Builder
bld(ctx
->program
, ctx
->block
);
10387 create_workgroup_barrier(bld
);
10389 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10390 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10392 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10393 if_context ic_invocation_id_is_zero
;
10394 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10395 bld
.reset(ctx
->block
);
10397 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10399 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10400 unsigned stride
= inner_comps
+ outer_comps
;
10401 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10405 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10407 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10409 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10410 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10411 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10413 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10414 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10416 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10417 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10418 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10419 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10422 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10423 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10424 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10425 unsigned tf_const_offset
= 0;
10427 if (ctx
->program
->chip_class
<= GFX8
) {
10428 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10429 if_context ic_rel_patch_id_is_zero
;
10430 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10431 bld
.reset(ctx
->block
);
10433 /* Store the dynamic HS control word. */
10434 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10435 bld
.mubuf(aco_opcode::buffer_store_dword
,
10436 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10437 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10438 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10439 tf_const_offset
+= 4;
10441 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10442 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10443 bld
.reset(ctx
->block
);
10446 assert(stride
== 2 || stride
== 4 || stride
== 6);
10447 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10448 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10450 /* Store to offchip for TES to read - only if TES reads them */
10451 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10452 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10453 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10455 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10456 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10458 if (likely(inner_comps
)) {
10459 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10460 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10464 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10465 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10468 static void emit_stream_output(isel_context
*ctx
,
10469 Temp
const *so_buffers
,
10470 Temp
const *so_write_offset
,
10471 const struct radv_stream_output
*output
)
10473 unsigned num_comps
= util_bitcount(output
->component_mask
);
10474 unsigned writemask
= (1 << num_comps
) - 1;
10475 unsigned loc
= output
->location
;
10476 unsigned buf
= output
->buffer
;
10478 assert(num_comps
&& num_comps
<= 4);
10479 if (!num_comps
|| num_comps
> 4)
10482 unsigned start
= ffs(output
->component_mask
) - 1;
10485 bool all_undef
= true;
10486 assert(ctx
->stage
& hw_vs
);
10487 for (unsigned i
= 0; i
< num_comps
; i
++) {
10488 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10489 all_undef
= all_undef
&& !out
[i
].id();
10494 while (writemask
) {
10496 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10497 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10498 /* GFX6 doesn't support storing vec3, split it. */
10499 writemask
|= 1u << (start
+ 2);
10503 unsigned offset
= output
->offset
+ start
* 4;
10505 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10506 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10507 for (int i
= 0; i
< count
; ++i
)
10508 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10509 vec
->definitions
[0] = Definition(write_data
);
10510 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10515 opcode
= aco_opcode::buffer_store_dword
;
10518 opcode
= aco_opcode::buffer_store_dwordx2
;
10521 opcode
= aco_opcode::buffer_store_dwordx3
;
10524 opcode
= aco_opcode::buffer_store_dwordx4
;
10527 unreachable("Unsupported dword count.");
10530 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10531 store
->operands
[0] = Operand(so_buffers
[buf
]);
10532 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10533 store
->operands
[2] = Operand((uint32_t) 0);
10534 store
->operands
[3] = Operand(write_data
);
10535 if (offset
> 4095) {
10536 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10537 Builder
bld(ctx
->program
, ctx
->block
);
10538 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10540 store
->offset
= offset
;
10542 store
->offen
= true;
10544 store
->dlc
= false;
10546 ctx
->block
->instructions
.emplace_back(std::move(store
));
10550 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10552 Builder
bld(ctx
->program
, ctx
->block
);
10554 Temp so_buffers
[4];
10555 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10556 for (unsigned i
= 0; i
< 4; i
++) {
10557 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10561 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10562 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10565 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10566 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10568 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10570 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10573 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10575 bld
.reset(ctx
->block
);
10577 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10579 Temp so_write_offset
[4];
10581 for (unsigned i
= 0; i
< 4; i
++) {
10582 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10587 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10588 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10589 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10590 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10592 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10594 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10595 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10596 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10597 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10601 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10602 struct radv_stream_output
*output
=
10603 &ctx
->program
->info
->so
.outputs
[i
];
10604 if (stream
!= output
->stream
)
10607 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10610 begin_divergent_if_else(ctx
, &ic
);
10611 end_divergent_if(ctx
, &ic
);
10614 } /* end namespace */
10616 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10618 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10619 Builder
bld(ctx
->program
, ctx
->block
);
10620 constexpr unsigned hs_idx
= 1u;
10621 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10622 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10623 Operand((8u << 16) | (hs_idx
* 8u)));
10624 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10626 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10628 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10629 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10630 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10631 ls_has_nonzero_hs_threads
);
10632 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10633 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10634 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10635 ls_has_nonzero_hs_threads
);
10636 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10637 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10638 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10639 ls_has_nonzero_hs_threads
);
10641 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10642 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10643 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10646 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10648 /* Split all arguments except for the first (ring_offsets) and the last
10649 * (exec) so that the dead channels don't stay live throughout the program.
10651 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10652 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10653 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10654 startpgm
->definitions
[i
].regClass().size());
10659 void handle_bc_optimize(isel_context
*ctx
)
10661 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10662 Builder
bld(ctx
->program
, ctx
->block
);
10663 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10664 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10665 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10666 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10667 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10668 if (uses_center
&& uses_centroid
) {
10669 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10670 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10672 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10674 for (unsigned i
= 0; i
< 2; i
++) {
10675 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10676 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10677 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10678 persp_centroid
, persp_center
, sel
);
10680 ctx
->persp_centroid
= bld
.tmp(v2
);
10681 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10682 Operand(new_coord
[0]), Operand(new_coord
[1]));
10683 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10686 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10688 for (unsigned i
= 0; i
< 2; i
++) {
10689 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10690 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10691 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10692 linear_centroid
, linear_center
, sel
);
10694 ctx
->linear_centroid
= bld
.tmp(v2
);
10695 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10696 Operand(new_coord
[0]), Operand(new_coord
[1]));
10697 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10702 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10704 Program
*program
= ctx
->program
;
10706 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10708 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10709 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10710 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10711 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10712 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10714 program
->next_fp_mode
.must_flush_denorms32
=
10715 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10716 program
->next_fp_mode
.must_flush_denorms16_64
=
10717 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10718 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10720 program
->next_fp_mode
.care_about_round32
=
10721 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10723 program
->next_fp_mode
.care_about_round16_64
=
10724 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10725 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10727 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10728 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10729 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10730 program
->next_fp_mode
.denorm16_64
= 0;
10732 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10734 /* preserving fp32 denorms is expensive, so only do it if asked */
10735 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10736 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10738 program
->next_fp_mode
.denorm32
= 0;
10740 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10741 program
->next_fp_mode
.round32
= fp_round_tz
;
10743 program
->next_fp_mode
.round32
= fp_round_ne
;
10745 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10746 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10748 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10750 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10753 void cleanup_cfg(Program
*program
)
10755 /* create linear_succs/logical_succs */
10756 for (Block
& BB
: program
->blocks
) {
10757 for (unsigned idx
: BB
.linear_preds
)
10758 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10759 for (unsigned idx
: BB
.logical_preds
)
10760 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10764 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10766 Builder
bld(ctx
->program
, ctx
->block
);
10768 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10769 Temp count
= i
== 0
10770 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10771 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10772 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10774 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10777 if (ctx
->program
->wave_size
== 64) {
10778 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10779 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10780 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10782 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10783 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10789 bool ngg_early_prim_export(isel_context
*ctx
)
10791 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10795 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10797 Builder
bld(ctx
->program
, ctx
->block
);
10799 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10800 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10802 /* Get the id of the current wave within the threadgroup (workgroup) */
10803 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10804 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10806 /* Execute the following code only on the first wave (wave id 0),
10807 * use the SCC def to tell if the wave id is zero or not.
10809 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10811 begin_uniform_if_then(ctx
, &ic
, cond
);
10812 begin_uniform_if_else(ctx
, &ic
);
10813 bld
.reset(ctx
->block
);
10815 /* Number of vertices output by VS/TES */
10816 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10817 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10818 /* Number of primitives output by VS/TES */
10819 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10820 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10822 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10823 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10824 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10826 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10827 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10829 end_uniform_if(ctx
, &ic
);
10831 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10832 bld
.reset(ctx
->block
);
10833 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10836 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10838 Builder
bld(ctx
->program
, ctx
->block
);
10840 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10841 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10844 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10847 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10848 assert(vtxindex
[i
].id());
10851 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10855 /* The initial edge flag is always false in tess eval shaders. */
10856 if (ctx
->stage
== ngg_vertex_gs
) {
10857 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10858 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10862 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10867 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10869 Builder
bld(ctx
->program
, ctx
->block
);
10870 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10872 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10873 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10874 false /* compressed */, true/* done */, false /* valid mask */);
10877 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10879 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10880 * These must always come before VS exports.
10882 * It is recommended to do these as early as possible. They can be at the beginning when
10883 * there is no SW GS and the shader doesn't write edge flags.
10887 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10888 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10890 Builder
bld(ctx
->program
, ctx
->block
);
10891 constexpr unsigned max_vertices_per_primitive
= 3;
10892 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10894 if (ctx
->stage
== ngg_vertex_gs
) {
10895 /* TODO: optimize for points & lines */
10896 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10897 if (ctx
->shader
->info
.tess
.point_mode
)
10898 num_vertices_per_primitive
= 1;
10899 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10900 num_vertices_per_primitive
= 2;
10902 unreachable("Unsupported NGG shader stage");
10905 Temp vtxindex
[max_vertices_per_primitive
];
10906 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10907 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10908 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10909 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10910 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10911 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10912 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10913 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10915 /* Export primitive data to the index buffer. */
10916 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10918 /* Export primitive ID. */
10919 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10920 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10921 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10922 Temp provoking_vtx_index
= vtxindex
[0];
10923 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10925 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10928 begin_divergent_if_else(ctx
, &ic
);
10929 end_divergent_if(ctx
, &ic
);
10932 void ngg_emit_nogs_output(isel_context
*ctx
)
10934 /* Emits NGG GS output, for stages that don't have SW GS. */
10937 Builder
bld(ctx
->program
, ctx
->block
);
10938 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10940 /* NGG streamout is currently disabled by default. */
10941 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10943 if (late_prim_export
) {
10944 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10945 create_export_phis(ctx
);
10946 /* Do what we need to do in the GS threads. */
10947 ngg_emit_nogs_gsthreads(ctx
);
10949 /* What comes next should be executed on ES threads. */
10950 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10951 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10952 bld
.reset(ctx
->block
);
10955 /* Export VS outputs */
10956 ctx
->block
->kind
|= block_kind_export_end
;
10957 create_vs_exports(ctx
);
10959 /* Export primitive ID */
10960 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10963 if (ctx
->stage
== ngg_vertex_gs
) {
10964 /* Wait for GS threads to store primitive ID in LDS. */
10965 create_workgroup_barrier(bld
);
10967 /* Calculate LDS address where the GS threads stored the primitive ID. */
10968 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10969 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10970 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10971 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10972 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10973 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10975 /* Load primitive ID from LDS. */
10976 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10977 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10978 /* TES: Just use the patch ID as the primitive ID. */
10979 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10981 unreachable("unsupported NGG shader stage.");
10984 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10985 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10987 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10990 if (late_prim_export
) {
10991 begin_divergent_if_else(ctx
, &ic
);
10992 end_divergent_if(ctx
, &ic
);
10993 bld
.reset(ctx
->block
);
10997 void select_program(Program
*program
,
10998 unsigned shader_count
,
10999 struct nir_shader
*const *shaders
,
11000 ac_shader_config
* config
,
11001 struct radv_shader_args
*args
)
11003 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
11004 if_context ic_merged_wave_info
;
11005 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
11007 for (unsigned i
= 0; i
< shader_count
; i
++) {
11008 nir_shader
*nir
= shaders
[i
];
11009 init_context(&ctx
, nir
);
11011 setup_fp_mode(&ctx
, nir
);
11014 /* needs to be after init_context() for FS */
11015 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
11016 append_logical_start(ctx
.block
);
11018 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
11019 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
11021 split_arguments(&ctx
, startpgm
);
11025 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
11027 if (ngg_early_prim_export(&ctx
))
11028 ngg_emit_nogs_gsthreads(&ctx
);
11031 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
11032 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
11033 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
11034 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
11035 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
11036 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
11037 ctx
.stage
== tess_eval_geometry_gs
));
11039 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
11040 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
11041 if (check_merged_wave_info
) {
11042 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
11043 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
11047 Builder
bld(ctx
.program
, ctx
.block
);
11049 create_workgroup_barrier(bld
);
11051 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
11052 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
11054 } else if (ctx
.stage
== geometry_gs
)
11055 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
11057 if (ctx
.stage
== fragment_fs
)
11058 handle_bc_optimize(&ctx
);
11060 visit_cf_list(&ctx
, &func
->body
);
11062 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
11063 emit_streamout(&ctx
, 0);
11065 if (ctx
.stage
& hw_vs
) {
11066 create_vs_exports(&ctx
);
11067 ctx
.block
->kind
|= block_kind_export_end
;
11068 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
11069 ngg_emit_nogs_output(&ctx
);
11070 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
11071 Builder
bld(ctx
.program
, ctx
.block
);
11072 bld
.barrier(aco_opcode::p_barrier
,
11073 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
11074 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
11075 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
11076 write_tcs_tess_factors(&ctx
);
11079 if (ctx
.stage
== fragment_fs
) {
11080 create_fs_exports(&ctx
);
11081 ctx
.block
->kind
|= block_kind_export_end
;
11084 if (endif_merged_wave_info
) {
11085 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
11086 end_divergent_if(&ctx
, &ic_merged_wave_info
);
11089 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
11090 ngg_emit_nogs_output(&ctx
);
11092 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
11093 /* Outputs of the previous stage are inputs to the next stage */
11094 ctx
.inputs
= ctx
.outputs
;
11095 ctx
.outputs
= shader_io_state();
11099 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11101 append_logical_end(ctx
.block
);
11102 ctx
.block
->kind
|= block_kind_uniform
;
11103 Builder
bld(ctx
.program
, ctx
.block
);
11104 if (ctx
.program
->wb_smem_l1_on_end
)
11105 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
11106 bld
.sopp(aco_opcode::s_endpgm
);
11108 cleanup_cfg(program
);
11111 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
11112 ac_shader_config
* config
,
11113 struct radv_shader_args
*args
)
11115 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
11117 ctx
.block
->fp_mode
= program
->next_fp_mode
;
11119 add_startpgm(&ctx
);
11120 append_logical_start(ctx
.block
);
11122 Builder
bld(ctx
.program
, ctx
.block
);
11124 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
11126 Operand
stream_id(0u);
11127 if (args
->shader_info
->so
.num_outputs
)
11128 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
11129 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
11131 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
11133 std::stack
<Block
> endif_blocks
;
11135 for (unsigned stream
= 0; stream
< 4; stream
++) {
11136 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
11139 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
11140 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
11143 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
11145 unsigned BB_if_idx
= ctx
.block
->index
;
11146 Block BB_endif
= Block();
11147 if (!stream_id
.isConstant()) {
11149 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11150 append_logical_end(ctx
.block
);
11151 ctx
.block
->kind
|= block_kind_uniform
;
11152 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11154 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11156 ctx
.block
= ctx
.program
->create_and_insert_block();
11157 add_edge(BB_if_idx
, ctx
.block
);
11158 bld
.reset(ctx
.block
);
11159 append_logical_start(ctx
.block
);
11162 unsigned offset
= 0;
11163 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11164 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11167 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11168 unsigned length
= util_last_bit(output_usage_mask
);
11169 for (unsigned j
= 0; j
< length
; ++j
) {
11170 if (!(output_usage_mask
& (1 << j
)))
11173 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11174 Temp voffset
= vtx_offset
;
11175 if (const_offset
>= 4096u) {
11176 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11177 const_offset
%= 4096u;
11180 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11181 mubuf
->definitions
[0] = bld
.def(v1
);
11182 mubuf
->operands
[0] = Operand(gsvs_ring
);
11183 mubuf
->operands
[1] = Operand(voffset
);
11184 mubuf
->operands
[2] = Operand(0u);
11185 mubuf
->offen
= true;
11186 mubuf
->offset
= const_offset
;
11189 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11191 ctx
.outputs
.mask
[i
] |= 1 << j
;
11192 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11194 bld
.insert(std::move(mubuf
));
11200 if (args
->shader_info
->so
.num_outputs
) {
11201 emit_streamout(&ctx
, stream
);
11202 bld
.reset(ctx
.block
);
11206 create_vs_exports(&ctx
);
11207 ctx
.block
->kind
|= block_kind_export_end
;
11210 if (!stream_id
.isConstant()) {
11211 append_logical_end(ctx
.block
);
11213 /* branch from then block to endif block */
11214 bld
.branch(aco_opcode::p_branch
);
11215 add_edge(ctx
.block
->index
, &BB_endif
);
11216 ctx
.block
->kind
|= block_kind_uniform
;
11218 /* emit else block */
11219 ctx
.block
= ctx
.program
->create_and_insert_block();
11220 add_edge(BB_if_idx
, ctx
.block
);
11221 bld
.reset(ctx
.block
);
11222 append_logical_start(ctx
.block
);
11224 endif_blocks
.push(std::move(BB_endif
));
11228 while (!endif_blocks
.empty()) {
11229 Block BB_endif
= std::move(endif_blocks
.top());
11230 endif_blocks
.pop();
11232 Block
*BB_else
= ctx
.block
;
11234 append_logical_end(BB_else
);
11235 /* branch from else block to endif block */
11236 bld
.branch(aco_opcode::p_branch
);
11237 add_edge(BB_else
->index
, &BB_endif
);
11238 BB_else
->kind
|= block_kind_uniform
;
11240 /** emit endif merge block */
11241 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11242 bld
.reset(ctx
.block
);
11243 append_logical_start(ctx
.block
);
11246 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11248 append_logical_end(ctx
.block
);
11249 ctx
.block
->kind
|= block_kind_uniform
;
11250 bld
.sopp(aco_opcode::s_endpgm
);
11252 cleanup_cfg(program
);