src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <map>
  29
  30 #include "ac_shader_util.h"
  31 #include "aco_ir.h"
  32 #include "aco_builder.h"
  33 #include "aco_interface.h"
  34 #include "aco_instruction_selection_setup.cpp"
  35 #include "util/fast_idiv_by_const.h"
  36
  37 namespace aco {
  38 namespace {
  39
  40 class loop_info_RAII {
  41    isel_context* ctx;
  42    unsigned header_idx_old;
  43    Block* exit_old;
  44    bool divergent_cont_old;
  45    bool divergent_branch_old;
  46    bool divergent_if_old;
  47
  48 public:
  49    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  50       : ctx(ctx),
  51         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  52         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  53         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  54         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  55    {
  56       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  57       ctx->cf_info.parent_loop.exit = loop_exit;
  58       ctx->cf_info.parent_loop.has_divergent_continue = false;
  59       ctx->cf_info.parent_loop.has_divergent_branch = false;
  60       ctx->cf_info.parent_if.is_divergent = false;
  61       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  62    }
  63
  64    ~loop_info_RAII()
  65    {
  66       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  67       ctx->cf_info.parent_loop.exit = exit_old;
  68       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  69       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  70       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  71       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  72       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  73          ctx->cf_info.exec_potentially_empty = false;
  74    }
  75 };
  76
  77 struct if_context {
  78    Temp cond;
  79
  80    bool divergent_old;
  81    bool exec_potentially_empty_old;
  82
  83    unsigned BB_if_idx;
  84    unsigned invert_idx;
  85    bool then_branch_divergent;
  86    Block BB_invert;
  87    Block BB_endif;
  88 };
  89
  90 static void visit_cf_list(struct isel_context *ctx,
  91                           struct exec_list *list);
  92
  93 static void add_logical_edge(unsigned pred_idx, Block *succ)
  94 {
  95    succ->logical_preds.emplace_back(pred_idx);
  96 }
  97
  98
  99 static void add_linear_edge(unsigned pred_idx, Block *succ)
 100 {
 101    succ->linear_preds.emplace_back(pred_idx);
 102 }
 103
 104 static void add_edge(unsigned pred_idx, Block *succ)
 105 {
 106    add_logical_edge(pred_idx, succ);
 107    add_linear_edge(pred_idx, succ);
 108 }
 109
 110 static void append_logical_start(Block *b)
 111 {
 112    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 113 }
 114
 115 static void append_logical_end(Block *b)
 116 {
 117    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 118 }
 119
 120 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 121 {
 122    assert(ctx->allocated[def->index].id());
 123    return ctx->allocated[def->index];
 124 }
 125
 126 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 127 {
 128    Builder bld(ctx->program, ctx->block);
 129
 130    if (!dst.id())
 131       dst = bld.tmp(src.regClass());
 132
 133    assert(src.size() == dst.size());
 134
 135    if (ctx->stage != fragment_fs) {
 136       if (!dst.id())
 137          return src;
 138
 139       bld.copy(Definition(dst), src);
 140       return dst;
 141    }
 142
 143    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 144    ctx->program->needs_wqm |= program_needs_wqm;
 145    return dst;
 146 }
 147
 148 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 149 {
 150    if (index.regClass() == s1)
 151       return bld.vop3(aco_opcode::v_readlane_b32, bld.def(s1), data, index);
 152
 153    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 154
 155    /* Currently not implemented on GFX6-7 */
 156    assert(ctx->options->chip_class >= GFX8);
 157
 158    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 159       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 160    }
 161
 162    /* GFX10, wave64 mode:
 163     * The bpermute instruction is limited to half-wave operation, which means that it can't
 164     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 165     * emulate it here.
 166     */
 167    if (!ctx->has_gfx10_wave64_bpermute) {
 168       ctx->has_gfx10_wave64_bpermute = true;
 169       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 170       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 171    }
 172
 173    Temp lane_id = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u));
 174    lane_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1), lane_id);
 175    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 176    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 177    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2, vcc), lane_is_hi, index_is_hi);
 178
 179    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 180                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 181 }
 182
 183 Temp as_vgpr(isel_context *ctx, Temp val)
 184 {
 185    if (val.type() == RegType::sgpr) {
 186       Builder bld(ctx->program, ctx->block);
 187       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 188    }
 189    assert(val.type() == RegType::vgpr);
 190    return val;
 191 }
 192
 193 //assumes a != 0xffffffff
 194 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 195 {
 196    assert(b != 0);
 197    Builder bld(ctx->program, ctx->block);
 198
 199    if (util_is_power_of_two_or_zero(b)) {
 200       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 201       return;
 202    }
 203
 204    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 205
 206    assert(info.multiplier <= 0xffffffff);
 207
 208    bool pre_shift = info.pre_shift != 0;
 209    bool increment = info.increment != 0;
 210    bool multiply = true;
 211    bool post_shift = info.post_shift != 0;
 212
 213    if (!pre_shift && !increment && !multiply && !post_shift) {
 214       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 215       return;
 216    }
 217
 218    Temp pre_shift_dst = a;
 219    if (pre_shift) {
 220       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 221       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 222    }
 223
 224    Temp increment_dst = pre_shift_dst;
 225    if (increment) {
 226       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 227       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 228    }
 229
 230    Temp multiply_dst = increment_dst;
 231    if (multiply) {
 232       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 233       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 234                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 235    }
 236
 237    if (post_shift) {
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 239    }
 240 }
 241
 242 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 243 {
 244    Builder bld(ctx->program, ctx->block);
 245    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 246 }
 247
 248
 249 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 250 {
 251    /* no need to extract the whole vector */
 252    if (src.regClass() == dst_rc) {
 253       assert(idx == 0);
 254       return src;
 255    }
 256    assert(src.size() > idx);
 257    Builder bld(ctx->program, ctx->block);
 258    auto it = ctx->allocated_vec.find(src.id());
 259    /* the size check needs to be early because elements other than 0 may be garbage */
 260    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 261       if (it->second[idx].regClass() == dst_rc) {
 262          return it->second[idx];
 263       } else {
 264          assert(dst_rc.size() == it->second[idx].regClass().size());
 265          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 266          return bld.copy(bld.def(dst_rc), it->second[idx]);
 267       }
 268    }
 269
 270    if (src.size() == dst_rc.size()) {
 271       assert(idx == 0);
 272       return bld.copy(bld.def(dst_rc), src);
 273    } else {
 274       Temp dst = bld.tmp(dst_rc);
 275       emit_extract_vector(ctx, src, idx, dst);
 276       return dst;
 277    }
 278 }
 279
 280 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 281 {
 282    if (num_components == 1)
 283       return;
 284    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 285       return;
 286    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 287    split->operands[0] = Operand(vec_src);
 288    std::array<Temp,4> elems;
 289    for (unsigned i = 0; i < num_components; i++) {
 290       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 291       split->definitions[i] = Definition(elems[i]);
 292    }
 293    ctx->block->instructions.emplace_back(std::move(split));
 294    ctx->allocated_vec.emplace(vec_src.id(), elems);
 295 }
 296
 297 /* This vector expansion uses a mask to determine which elements in the new vector
 298  * come from the original vector. The other elements are undefined. */
 299 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 300 {
 301    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 302
 303    if (vec_src == dst)
 304       return;
 305
 306    Builder bld(ctx->program, ctx->block);
 307    if (num_components == 1) {
 308       if (dst.type() == RegType::sgpr)
 309          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 310       else
 311          bld.copy(Definition(dst), vec_src);
 312       return;
 313    }
 314
 315    unsigned component_size = dst.size() / num_components;
 316    std::array<Temp,4> elems;
 317
 318    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 319    vec->definitions[0] = Definition(dst);
 320    unsigned k = 0;
 321    for (unsigned i = 0; i < num_components; i++) {
 322       if (mask & (1 << i)) {
 323          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 324          if (dst.type() == RegType::sgpr)
 325             src = bld.as_uniform(src);
 326          vec->operands[i] = Operand(src);
 327       } else {
 328          vec->operands[i] = Operand(0u);
 329       }
 330       elems[i] = vec->operands[i].getTemp();
 331    }
 332    ctx->block->instructions.emplace_back(std::move(vec));
 333    ctx->allocated_vec.emplace(dst.id(), elems);
 334 }
 335
 336 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 337 {
 338    Builder bld(ctx->program, ctx->block);
 339    if (!dst.id())
 340       dst = bld.tmp(s2);
 341
 342    assert(val.regClass() == s1);
 343    assert(dst.regClass() == s2);
 344
 345    return bld.sop2(aco_opcode::s_cselect_b64, bld.hint_vcc(Definition(dst)), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 346 }
 347
 348 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 349 {
 350    Builder bld(ctx->program, ctx->block);
 351    if (!dst.id())
 352       dst = bld.tmp(s1);
 353
 354    assert(val.regClass() == s2);
 355    assert(dst.regClass() == s1);
 356
 357    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 358    Temp tmp = bld.tmp(s1);
 359    bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.scc(Definition(tmp)), val, Operand(exec, s2));
 360    return emit_wqm(ctx, tmp, dst);
 361 }
 362
 363 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 364 {
 365    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 366       return get_ssa_temp(ctx, src.src.ssa);
 367
 368    if (src.src.ssa->num_components == size) {
 369       bool identity_swizzle = true;
 370       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 371          if (src.swizzle[i] != i)
 372             identity_swizzle = false;
 373       }
 374       if (identity_swizzle)
 375          return get_ssa_temp(ctx, src.src.ssa);
 376    }
 377
 378    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 379    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 380    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 381    assert(vec.size() % elem_size == 0);
 382
 383    RegClass elem_rc = RegClass(vec.type(), elem_size);
 384    if (size == 1) {
 385       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 386    } else {
 387       assert(size <= 4);
 388       std::array<Temp,4> elems;
 389       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 390       for (unsigned i = 0; i < size; ++i) {
 391          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 392          vec_instr->operands[i] = Operand{elems[i]};
 393       }
 394       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 395       vec_instr->definitions[0] = Definition(dst);
 396       ctx->block->instructions.emplace_back(std::move(vec_instr));
 397       ctx->allocated_vec.emplace(dst.id(), elems);
 398       return dst;
 399    }
 400 }
 401
 402 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 403 {
 404    if (ptr.size() == 2)
 405       return ptr;
 406    Builder bld(ctx->program, ctx->block);
 407    if (ptr.type() == RegType::vgpr)
 408       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 409    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 410                      ptr, Operand((unsigned)ctx->options->address32_hi));
 411 }
 412
 413 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 414 {
 415    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 416    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 417    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 418    sop2->definitions[0] = Definition(dst);
 419    if (writes_scc)
 420       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 421    ctx->block->instructions.emplace_back(std::move(sop2));
 422 }
 423
 424 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool commutative, bool swap_srcs=false)
 425 {
 426    Builder bld(ctx->program, ctx->block);
 427    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 428    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 429    if (src1.type() == RegType::sgpr) {
 430       if (commutative && src0.type() == RegType::vgpr) {
 431          Temp t = src0;
 432          src0 = src1;
 433          src1 = t;
 434       } else if (src0.type() == RegType::vgpr &&
 435                  op != aco_opcode::v_madmk_f32 &&
 436                  op != aco_opcode::v_madak_f32 &&
 437                  op != aco_opcode::v_madmk_f16 &&
 438                  op != aco_opcode::v_madak_f16) {
 439          /* If the instruction is not commutative, we emit a VOP3A instruction */
 440          bld.vop2_e64(op, Definition(dst), src0, src1);
 441          return;
 442       } else {
 443          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 444       }
 445    }
 446    bld.vop2(op, Definition(dst), src0, src1);
 447 }
 448
 449 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 450 {
 451    Temp src0 = get_alu_src(ctx, instr->src[0]);
 452    Temp src1 = get_alu_src(ctx, instr->src[1]);
 453    Temp src2 = get_alu_src(ctx, instr->src[2]);
 454
 455    /* ensure that the instruction has at most 1 sgpr operand
 456     * The optimizer will inline constants for us */
 457    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 458       src0 = as_vgpr(ctx, src0);
 459    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 460       src1 = as_vgpr(ctx, src1);
 461    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 462       src2 = as_vgpr(ctx, src2);
 463
 464    Builder bld(ctx->program, ctx->block);
 465    bld.vop3(op, Definition(dst), src0, src1, src2);
 466 }
 467
 468 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 469 {
 470    Builder bld(ctx->program, ctx->block);
 471    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 472 }
 473
 474 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 475 {
 476    Temp src0 = get_alu_src(ctx, instr->src[0]);
 477    Temp src1 = get_alu_src(ctx, instr->src[1]);
 478    aco_ptr<Instruction> vopc;
 479    if (src1.type() == RegType::sgpr) {
 480       if (src0.type() == RegType::vgpr) {
 481          /* to swap the operands, we might also have to change the opcode */
 482          switch (op) {
 483             case aco_opcode::v_cmp_lt_f32:
 484                op = aco_opcode::v_cmp_gt_f32;
 485                break;
 486             case aco_opcode::v_cmp_ge_f32:
 487                op = aco_opcode::v_cmp_le_f32;
 488                break;
 489             case aco_opcode::v_cmp_lt_i32:
 490                op = aco_opcode::v_cmp_gt_i32;
 491                break;
 492             case aco_opcode::v_cmp_ge_i32:
 493                op = aco_opcode::v_cmp_le_i32;
 494                break;
 495             case aco_opcode::v_cmp_lt_u32:
 496                op = aco_opcode::v_cmp_gt_u32;
 497                break;
 498             case aco_opcode::v_cmp_ge_u32:
 499                op = aco_opcode::v_cmp_le_u32;
 500                break;
 501             case aco_opcode::v_cmp_lt_f64:
 502                op = aco_opcode::v_cmp_gt_f64;
 503                break;
 504             case aco_opcode::v_cmp_ge_f64:
 505                op = aco_opcode::v_cmp_le_f64;
 506                break;
 507             case aco_opcode::v_cmp_lt_i64:
 508                op = aco_opcode::v_cmp_gt_i64;
 509                break;
 510             case aco_opcode::v_cmp_ge_i64:
 511                op = aco_opcode::v_cmp_le_i64;
 512                break;
 513             case aco_opcode::v_cmp_lt_u64:
 514                op = aco_opcode::v_cmp_gt_u64;
 515                break;
 516             case aco_opcode::v_cmp_ge_u64:
 517                op = aco_opcode::v_cmp_le_u64;
 518                break;
 519             default: /* eq and ne are commutative */
 520                break;
 521          }
 522          Temp t = src0;
 523          src0 = src1;
 524          src1 = t;
 525       } else {
 526          src1 = as_vgpr(ctx, src1);
 527       }
 528    }
 529
 530    Builder bld(ctx->program, ctx->block);
 531    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 532 }
 533
 534 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 535 {
 536    Temp src0 = get_alu_src(ctx, instr->src[0]);
 537    Temp src1 = get_alu_src(ctx, instr->src[1]);
 538
 539    assert(dst.regClass() == s2);
 540    assert(src0.type() == RegType::sgpr);
 541    assert(src1.type() == RegType::sgpr);
 542
 543    Builder bld(ctx->program, ctx->block);
 544    /* Emit the SALU comparison instruction */
 545    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 546    /* Turn the result into a per-lane bool */
 547    bool_to_vector_condition(ctx, cmp, dst);
 548 }
 549
 550 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 551                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::last_opcode, aco_opcode s64_op = aco_opcode::last_opcode)
 552 {
 553    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 554    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 555    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 556    bool use_valu = s_op == aco_opcode::last_opcode ||
 557                    divergent_vals ||
 558                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 559                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 560    aco_opcode op = use_valu ? v_op : s_op;
 561    assert(op != aco_opcode::last_opcode);
 562
 563    if (use_valu)
 564       emit_vopc_instruction(ctx, instr, op, dst);
 565    else
 566       emit_sopc_instruction(ctx, instr, op, dst);
 567 }
 568
 569 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, aco_opcode op32, aco_opcode op64, Temp dst)
 570 {
 571    Builder bld(ctx->program, ctx->block);
 572    Temp src0 = get_alu_src(ctx, instr->src[0]);
 573    Temp src1 = get_alu_src(ctx, instr->src[1]);
 574
 575    assert(dst.regClass() == s2);
 576    assert(src0.regClass() == s2);
 577    assert(src1.regClass() == s2);
 578
 579    bld.sop2(op64, Definition(dst), bld.def(s1, scc), src0, src1);
 580 }
 581
 582 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 583 {
 584    Builder bld(ctx->program, ctx->block);
 585    Temp cond = get_alu_src(ctx, instr->src[0]);
 586    Temp then = get_alu_src(ctx, instr->src[1]);
 587    Temp els = get_alu_src(ctx, instr->src[2]);
 588
 589    assert(cond.regClass() == s2);
 590
 591    if (dst.type() == RegType::vgpr) {
 592       aco_ptr<Instruction> bcsel;
 593       if (dst.size() == 1) {
 594          then = as_vgpr(ctx, then);
 595          els = as_vgpr(ctx, els);
 596
 597          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 598       } else if (dst.size() == 2) {
 599          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 600          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 601          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 602          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 603
 604          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 605          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 606
 607          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 608       } else {
 609          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 610          nir_print_instr(&instr->instr, stderr);
 611          fprintf(stderr, "\n");
 612       }
 613       return;
 614    }
 615
 616    if (instr->dest.dest.ssa.bit_size == 1) {
 617       assert(dst.regClass() == s2);
 618       assert(then.regClass() == s2);
 619       assert(els.regClass() == s2);
 620    }
 621
 622    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 623       if (dst.regClass() == s1 || dst.regClass() == s2) {
 624          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 625          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 626          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 627       } else {
 628          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 629          nir_print_instr(&instr->instr, stderr);
 630          fprintf(stderr, "\n");
 631       }
 632       return;
 633    }
 634
 635    /* divergent boolean bcsel
 636     * this implements bcsel on bools: dst = s0 ? s1 : s2
 637     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 638    assert(instr->dest.dest.ssa.bit_size == 1);
 639
 640    if (cond.id() != then.id())
 641       then = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), cond, then);
 642
 643    if (cond.id() == els.id())
 644       bld.sop1(aco_opcode::s_mov_b64, Definition(dst), then);
 645    else
 646       bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), then,
 647                bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), els, cond));
 648 }
 649
 650 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 651                     aco_opcode op, uint32_t undo)
 652 {
 653    /* multiply by 16777216 to handle denormals */
 654    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(s2)),
 655                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 656    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 657    scaled = bld.vop1(op, bld.def(v1), scaled);
 658    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 659
 660    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 661
 662    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 663 }
 664
 665 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 666 {
 667    if (ctx->block->fp_mode.denorm32 == 0) {
 668       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 669       return;
 670    }
 671
 672    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 673 }
 674
 675 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 676 {
 677    if (ctx->block->fp_mode.denorm32 == 0) {
 678       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 679       return;
 680    }
 681
 682    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 683 }
 684
 685 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 686 {
 687    if (ctx->block->fp_mode.denorm32 == 0) {
 688       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 689       return;
 690    }
 691
 692    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 693 }
 694
 695 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 696 {
 697    if (ctx->block->fp_mode.denorm32 == 0) {
 698       bld.vop1(aco_opcode::v_log_f32, dst, val);
 699       return;
 700    }
 701
 702    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 703 }
 704
 705 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 706 {
 707    if (!instr->dest.dest.is_ssa) {
 708       fprintf(stderr, "nir alu dst not in ssa: ");
 709       nir_print_instr(&instr->instr, stderr);
 710       fprintf(stderr, "\n");
 711       abort();
 712    }
 713    Builder bld(ctx->program, ctx->block);
 714    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 715    switch(instr->op) {
 716    case nir_op_vec2:
 717    case nir_op_vec3:
 718    case nir_op_vec4: {
 719       std::array<Temp,4> elems;
 720       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 721       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 722          elems[i] = get_alu_src(ctx, instr->src[i]);
 723          vec->operands[i] = Operand{elems[i]};
 724       }
 725       vec->definitions[0] = Definition(dst);
 726       ctx->block->instructions.emplace_back(std::move(vec));
 727       ctx->allocated_vec.emplace(dst.id(), elems);
 728       break;
 729    }
 730    case nir_op_mov: {
 731       Temp src = get_alu_src(ctx, instr->src[0]);
 732       aco_ptr<Instruction> mov;
 733       if (dst.type() == RegType::sgpr) {
 734          if (src.type() == RegType::vgpr)
 735             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 736          else if (src.regClass() == s1)
 737             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 738          else if (src.regClass() == s2)
 739             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 740          else
 741             unreachable("wrong src register class for nir_op_imov");
 742       } else if (dst.regClass() == v1) {
 743          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 744       } else if (dst.regClass() == v2) {
 745          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 746       } else {
 747          nir_print_instr(&instr->instr, stderr);
 748          unreachable("Should have been lowered to scalar.");
 749       }
 750       break;
 751    }
 752    case nir_op_inot: {
 753       Temp src = get_alu_src(ctx, instr->src[0]);
 754       if (instr->dest.dest.ssa.bit_size == 1) {
 755          assert(src.regClass() == s2);
 756          assert(dst.regClass() == s2);
 757          bld.sop2(aco_opcode::s_andn2_b64, Definition(dst), bld.def(s1, scc), Operand(exec, s2), src);
 758       } else if (dst.regClass() == v1) {
 759          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 760       } else if (dst.type() == RegType::sgpr) {
 761          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 762          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 763       } else {
 764          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 765          nir_print_instr(&instr->instr, stderr);
 766          fprintf(stderr, "\n");
 767       }
 768       break;
 769    }
 770    case nir_op_ineg: {
 771       Temp src = get_alu_src(ctx, instr->src[0]);
 772       if (dst.regClass() == v1) {
 773          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 774       } else if (dst.regClass() == s1) {
 775          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 776       } else if (dst.size() == 2) {
 777          Temp src0 = bld.tmp(dst.type(), 1);
 778          Temp src1 = bld.tmp(dst.type(), 1);
 779          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 780
 781          if (dst.regClass() == s2) {
 782             Temp carry = bld.tmp(s1);
 783             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 784             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 785             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 786          } else {
 787             Temp lower = bld.tmp(v1);
 788             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 789             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 790             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 791          }
 792       } else {
 793          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 794          nir_print_instr(&instr->instr, stderr);
 795          fprintf(stderr, "\n");
 796       }
 797       break;
 798    }
 799    case nir_op_iabs: {
 800       if (dst.regClass() == s1) {
 801          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 802       } else if (dst.regClass() == v1) {
 803          Temp src = get_alu_src(ctx, instr->src[0]);
 804          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 805       } else {
 806          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 807          nir_print_instr(&instr->instr, stderr);
 808          fprintf(stderr, "\n");
 809       }
 810       break;
 811    }
 812    case nir_op_isign: {
 813       Temp src = get_alu_src(ctx, instr->src[0]);
 814       if (dst.regClass() == s1) {
 815          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 816          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 817          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 818       } else if (dst.regClass() == s2) {
 819          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 820          Temp neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 821          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, neqz);
 822       } else if (dst.regClass() == v1) {
 823          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 824          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
 825          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 826       } else if (dst.regClass() == v2) {
 827          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 828          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 829          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
 830          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 831          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 832          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 833       } else {
 834          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 835          nir_print_instr(&instr->instr, stderr);
 836          fprintf(stderr, "\n");
 837       }
 838       break;
 839    }
 840    case nir_op_imax: {
 841       if (dst.regClass() == v1) {
 842          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 843       } else if (dst.regClass() == s1) {
 844          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 845       } else {
 846          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 847          nir_print_instr(&instr->instr, stderr);
 848          fprintf(stderr, "\n");
 849       }
 850       break;
 851    }
 852    case nir_op_umax: {
 853       if (dst.regClass() == v1) {
 854          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 855       } else if (dst.regClass() == s1) {
 856          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 857       } else {
 858          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 859          nir_print_instr(&instr->instr, stderr);
 860          fprintf(stderr, "\n");
 861       }
 862       break;
 863    }
 864    case nir_op_imin: {
 865       if (dst.regClass() == v1) {
 866          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 867       } else if (dst.regClass() == s1) {
 868          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 869       } else {
 870          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 871          nir_print_instr(&instr->instr, stderr);
 872          fprintf(stderr, "\n");
 873       }
 874       break;
 875    }
 876    case nir_op_umin: {
 877       if (dst.regClass() == v1) {
 878          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 879       } else if (dst.regClass() == s1) {
 880          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
 881       } else {
 882          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 883          nir_print_instr(&instr->instr, stderr);
 884          fprintf(stderr, "\n");
 885       }
 886       break;
 887    }
 888    case nir_op_ior: {
 889       if (instr->dest.dest.ssa.bit_size == 1) {
 890          emit_boolean_logic(ctx, instr, aco_opcode::s_or_b32, aco_opcode::s_or_b64, dst);
 891       } else if (dst.regClass() == v1) {
 892          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
 893       } else if (dst.regClass() == s1) {
 894          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
 895       } else if (dst.regClass() == s2) {
 896          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
 897       } else {
 898          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 899          nir_print_instr(&instr->instr, stderr);
 900          fprintf(stderr, "\n");
 901       }
 902       break;
 903    }
 904    case nir_op_iand: {
 905       if (instr->dest.dest.ssa.bit_size == 1) {
 906          emit_boolean_logic(ctx, instr, aco_opcode::s_and_b32, aco_opcode::s_and_b64, dst);
 907       } else if (dst.regClass() == v1) {
 908          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
 909       } else if (dst.regClass() == s1) {
 910          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
 911       } else if (dst.regClass() == s2) {
 912          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
 913       } else {
 914          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 915          nir_print_instr(&instr->instr, stderr);
 916          fprintf(stderr, "\n");
 917       }
 918       break;
 919    }
 920    case nir_op_ixor: {
 921       if (instr->dest.dest.ssa.bit_size == 1) {
 922          emit_boolean_logic(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::s_xor_b64, dst);
 923       } else if (dst.regClass() == v1) {
 924          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
 925       } else if (dst.regClass() == s1) {
 926          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
 927       } else if (dst.regClass() == s2) {
 928          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
 929       } else {
 930          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 931          nir_print_instr(&instr->instr, stderr);
 932          fprintf(stderr, "\n");
 933       }
 934       break;
 935    }
 936    case nir_op_ushr: {
 937       if (dst.regClass() == v1) {
 938          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
 939       } else if (dst.regClass() == v2) {
 940          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
 941                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 942       } else if (dst.regClass() == s2) {
 943          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
 944       } else if (dst.regClass() == s1) {
 945          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
 946       } else {
 947          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 948          nir_print_instr(&instr->instr, stderr);
 949          fprintf(stderr, "\n");
 950       }
 951       break;
 952    }
 953    case nir_op_ishl: {
 954       if (dst.regClass() == v1) {
 955          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
 956       } else if (dst.regClass() == v2) {
 957          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
 958                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 959       } else if (dst.regClass() == s1) {
 960          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
 961       } else if (dst.regClass() == s2) {
 962          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
 963       } else {
 964          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 965          nir_print_instr(&instr->instr, stderr);
 966          fprintf(stderr, "\n");
 967       }
 968       break;
 969    }
 970    case nir_op_ishr: {
 971       if (dst.regClass() == v1) {
 972          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
 973       } else if (dst.regClass() == v2) {
 974          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
 975                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
 976       } else if (dst.regClass() == s1) {
 977          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
 978       } else if (dst.regClass() == s2) {
 979          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
 980       } else {
 981          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 982          nir_print_instr(&instr->instr, stderr);
 983          fprintf(stderr, "\n");
 984       }
 985       break;
 986    }
 987    case nir_op_find_lsb: {
 988       Temp src = get_alu_src(ctx, instr->src[0]);
 989       if (src.regClass() == s1) {
 990          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
 991       } else if (src.regClass() == v1) {
 992          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
 993       } else if (src.regClass() == s2) {
 994          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
 995       } else {
 996          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 997          nir_print_instr(&instr->instr, stderr);
 998          fprintf(stderr, "\n");
 999       }
1000       break;
1001    }
1002    case nir_op_ufind_msb:
1003    case nir_op_ifind_msb: {
1004       Temp src = get_alu_src(ctx, instr->src[0]);
1005       if (src.regClass() == s1 || src.regClass() == s2) {
1006          aco_opcode op = src.regClass() == s2 ?
1007                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1008                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1009          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1010
1011          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1012                                         Operand(src.size() * 32u - 1u), msb_rev);
1013          Temp msb = sub.def(0).getTemp();
1014          Temp carry = sub.def(1).getTemp();
1015
1016          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, carry);
1017       } else if (src.regClass() == v1) {
1018          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1019          Temp msb_rev = bld.tmp(v1);
1020          emit_vop1_instruction(ctx, instr, op, msb_rev);
1021          Temp msb = bld.tmp(v1);
1022          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1023          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1024       } else {
1025          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1026          nir_print_instr(&instr->instr, stderr);
1027          fprintf(stderr, "\n");
1028       }
1029       break;
1030    }
1031    case nir_op_bitfield_reverse: {
1032       if (dst.regClass() == s1) {
1033          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1034       } else if (dst.regClass() == v1) {
1035          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1036       } else {
1037          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1038          nir_print_instr(&instr->instr, stderr);
1039          fprintf(stderr, "\n");
1040       }
1041       break;
1042    }
1043    case nir_op_iadd: {
1044       if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1046          break;
1047       }
1048
1049       Temp src0 = get_alu_src(ctx, instr->src[0]);
1050       Temp src1 = get_alu_src(ctx, instr->src[1]);
1051       if (dst.regClass() == v1) {
1052          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1053          break;
1054       }
1055
1056       assert(src0.size() == 2 && src1.size() == 2);
1057       Temp src00 = bld.tmp(src0.type(), 1);
1058       Temp src01 = bld.tmp(dst.type(), 1);
1059       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1060       Temp src10 = bld.tmp(src1.type(), 1);
1061       Temp src11 = bld.tmp(dst.type(), 1);
1062       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1063
1064       if (dst.regClass() == s2) {
1065          Temp carry = bld.tmp(s1);
1066          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1067          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1068          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1069       } else if (dst.regClass() == v2) {
1070          Temp dst0 = bld.tmp(v1);
1071          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1072          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1073          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1074       } else {
1075          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1076          nir_print_instr(&instr->instr, stderr);
1077          fprintf(stderr, "\n");
1078       }
1079       break;
1080    }
1081    case nir_op_uadd_sat: {
1082       Temp src0 = get_alu_src(ctx, instr->src[0]);
1083       Temp src1 = get_alu_src(ctx, instr->src[1]);
1084       if (dst.regClass() == s1) {
1085          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1086          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1087                   src0, src1);
1088          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1089       } else if (dst.regClass() == v1) {
1090          if (ctx->options->chip_class >= GFX9) {
1091             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1092             add->operands[0] = Operand(src0);
1093             add->operands[1] = Operand(src1);
1094             add->definitions[0] = Definition(dst);
1095             add->clamp = 1;
1096             ctx->block->instructions.emplace_back(std::move(add));
1097          } else {
1098             if (src1.regClass() != v1)
1099                std::swap(src0, src1);
1100             assert(src1.regClass() == v1);
1101             Temp tmp = bld.tmp(v1);
1102             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1103             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1104          }
1105       } else {
1106          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1107          nir_print_instr(&instr->instr, stderr);
1108          fprintf(stderr, "\n");
1109       }
1110       break;
1111    }
1112    case nir_op_uadd_carry: {
1113       Temp src0 = get_alu_src(ctx, instr->src[0]);
1114       Temp src1 = get_alu_src(ctx, instr->src[1]);
1115       if (dst.regClass() == s1) {
1116          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1117          break;
1118       }
1119       if (dst.regClass() == v1) {
1120          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1121          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1122          break;
1123       }
1124
1125       Temp src00 = bld.tmp(src0.type(), 1);
1126       Temp src01 = bld.tmp(dst.type(), 1);
1127       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1128       Temp src10 = bld.tmp(src1.type(), 1);
1129       Temp src11 = bld.tmp(dst.type(), 1);
1130       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1131       if (dst.regClass() == s2) {
1132          Temp carry = bld.tmp(s1);
1133          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1134          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1135          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1136       } else if (dst.regClass() == v2) {
1137          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1138          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1139          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1140          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1141       } else {
1142          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1143          nir_print_instr(&instr->instr, stderr);
1144          fprintf(stderr, "\n");
1145       }
1146       break;
1147    }
1148    case nir_op_isub: {
1149       if (dst.regClass() == s1) {
1150          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1151          break;
1152       }
1153
1154       Temp src0 = get_alu_src(ctx, instr->src[0]);
1155       Temp src1 = get_alu_src(ctx, instr->src[1]);
1156       if (dst.regClass() == v1) {
1157          bld.vsub32(Definition(dst), src0, src1);
1158          break;
1159       }
1160
1161       Temp src00 = bld.tmp(src0.type(), 1);
1162       Temp src01 = bld.tmp(dst.type(), 1);
1163       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1164       Temp src10 = bld.tmp(src1.type(), 1);
1165       Temp src11 = bld.tmp(dst.type(), 1);
1166       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1167       if (dst.regClass() == s2) {
1168          Temp carry = bld.tmp(s1);
1169          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1170          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1171          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1172       } else if (dst.regClass() == v2) {
1173          Temp lower = bld.tmp(v1);
1174          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1175          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1176          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1177       } else {
1178          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1179          nir_print_instr(&instr->instr, stderr);
1180          fprintf(stderr, "\n");
1181       }
1182       break;
1183    }
1184    case nir_op_usub_borrow: {
1185       Temp src0 = get_alu_src(ctx, instr->src[0]);
1186       Temp src1 = get_alu_src(ctx, instr->src[1]);
1187       if (dst.regClass() == s1) {
1188          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1189          break;
1190       } else if (dst.regClass() == v1) {
1191          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1192          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1193          break;
1194       }
1195
1196       Temp src00 = bld.tmp(src0.type(), 1);
1197       Temp src01 = bld.tmp(dst.type(), 1);
1198       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1199       Temp src10 = bld.tmp(src1.type(), 1);
1200       Temp src11 = bld.tmp(dst.type(), 1);
1201       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1202       if (dst.regClass() == s2) {
1203          Temp borrow = bld.tmp(s1);
1204          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1205          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1206          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1207       } else if (dst.regClass() == v2) {
1208          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1209          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1210          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1211          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1212       } else {
1213          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1214          nir_print_instr(&instr->instr, stderr);
1215          fprintf(stderr, "\n");
1216       }
1217       break;
1218    }
1219    case nir_op_imul: {
1220       if (dst.regClass() == v1) {
1221          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1222                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1223       } else if (dst.regClass() == s1) {
1224          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1225       } else {
1226          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1227          nir_print_instr(&instr->instr, stderr);
1228          fprintf(stderr, "\n");
1229       }
1230       break;
1231    }
1232    case nir_op_umul_high: {
1233       if (dst.regClass() == v1) {
1234          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1235       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1236          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1237       } else if (dst.regClass() == s1) {
1238          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1239                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1240          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1241       } else {
1242          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1243          nir_print_instr(&instr->instr, stderr);
1244          fprintf(stderr, "\n");
1245       }
1246       break;
1247    }
1248    case nir_op_imul_high: {
1249       if (dst.regClass() == v1) {
1250          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1251       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1252          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1253       } else if (dst.regClass() == s1) {
1254          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1255                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1256          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1257       } else {
1258          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1259          nir_print_instr(&instr->instr, stderr);
1260          fprintf(stderr, "\n");
1261       }
1262       break;
1263    }
1264    case nir_op_fmul: {
1265       if (dst.size() == 1) {
1266          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1267       } else if (dst.size() == 2) {
1268          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1269                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1270       } else {
1271          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1272          nir_print_instr(&instr->instr, stderr);
1273          fprintf(stderr, "\n");
1274       }
1275       break;
1276    }
1277    case nir_op_fadd: {
1278       if (dst.size() == 1) {
1279          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1280       } else if (dst.size() == 2) {
1281          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1282                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1283       } else {
1284          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1285          nir_print_instr(&instr->instr, stderr);
1286          fprintf(stderr, "\n");
1287       }
1288       break;
1289    }
1290    case nir_op_fsub: {
1291       Temp src0 = get_alu_src(ctx, instr->src[0]);
1292       Temp src1 = get_alu_src(ctx, instr->src[1]);
1293       if (dst.size() == 1) {
1294          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1295             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1296          else
1297             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1298       } else if (dst.size() == 2) {
1299          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1300                                      get_alu_src(ctx, instr->src[0]),
1301                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1302          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1303          sub->neg[1] = true;
1304       } else {
1305          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1306          nir_print_instr(&instr->instr, stderr);
1307          fprintf(stderr, "\n");
1308       }
1309       break;
1310    }
1311    case nir_op_fmax: {
1312       if (dst.size() == 1) {
1313          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true);
1314       } else if (dst.size() == 2) {
1315          bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1316                   get_alu_src(ctx, instr->src[0]),
1317                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1318       } else {
1319          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1320          nir_print_instr(&instr->instr, stderr);
1321          fprintf(stderr, "\n");
1322       }
1323       break;
1324    }
1325    case nir_op_fmin: {
1326       if (dst.size() == 1) {
1327          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true);
1328       } else if (dst.size() == 2) {
1329          bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1330                   get_alu_src(ctx, instr->src[0]),
1331                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1332       } else {
1333          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1334          nir_print_instr(&instr->instr, stderr);
1335          fprintf(stderr, "\n");
1336       }
1337       break;
1338    }
1339    case nir_op_fmax3: {
1340       if (dst.size() == 1) {
1341          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst);
1342       } else {
1343          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1344          nir_print_instr(&instr->instr, stderr);
1345          fprintf(stderr, "\n");
1346       }
1347       break;
1348    }
1349    case nir_op_fmin3: {
1350       if (dst.size() == 1) {
1351          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst);
1352       } else {
1353          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1354          nir_print_instr(&instr->instr, stderr);
1355          fprintf(stderr, "\n");
1356       }
1357       break;
1358    }
1359    case nir_op_fmed3: {
1360       if (dst.size() == 1) {
1361          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst);
1362       } else {
1363          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1364          nir_print_instr(&instr->instr, stderr);
1365          fprintf(stderr, "\n");
1366       }
1367       break;
1368    }
1369    case nir_op_umax3: {
1370       if (dst.size() == 1) {
1371          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1372       } else {
1373          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1374          nir_print_instr(&instr->instr, stderr);
1375          fprintf(stderr, "\n");
1376       }
1377       break;
1378    }
1379    case nir_op_umin3: {
1380       if (dst.size() == 1) {
1381          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1382       } else {
1383          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1384          nir_print_instr(&instr->instr, stderr);
1385          fprintf(stderr, "\n");
1386       }
1387       break;
1388    }
1389    case nir_op_umed3: {
1390       if (dst.size() == 1) {
1391          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1392       } else {
1393          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1394          nir_print_instr(&instr->instr, stderr);
1395          fprintf(stderr, "\n");
1396       }
1397       break;
1398    }
1399    case nir_op_imax3: {
1400       if (dst.size() == 1) {
1401          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1402       } else {
1403          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1404          nir_print_instr(&instr->instr, stderr);
1405          fprintf(stderr, "\n");
1406       }
1407       break;
1408    }
1409    case nir_op_imin3: {
1410       if (dst.size() == 1) {
1411          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1412       } else {
1413          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1414          nir_print_instr(&instr->instr, stderr);
1415          fprintf(stderr, "\n");
1416       }
1417       break;
1418    }
1419    case nir_op_imed3: {
1420       if (dst.size() == 1) {
1421          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1422       } else {
1423          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1424          nir_print_instr(&instr->instr, stderr);
1425          fprintf(stderr, "\n");
1426       }
1427       break;
1428    }
1429    case nir_op_cube_face_coord: {
1430       Temp in = get_alu_src(ctx, instr->src[0], 3);
1431       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1432                       emit_extract_vector(ctx, in, 1, v1),
1433                       emit_extract_vector(ctx, in, 2, v1) };
1434       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1435       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1436       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1437       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1438       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1439       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1440       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1441       break;
1442    }
1443    case nir_op_cube_face_index: {
1444       Temp in = get_alu_src(ctx, instr->src[0], 3);
1445       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1446                       emit_extract_vector(ctx, in, 1, v1),
1447                       emit_extract_vector(ctx, in, 2, v1) };
1448       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1449       break;
1450    }
1451    case nir_op_bcsel: {
1452       emit_bcsel(ctx, instr, dst);
1453       break;
1454    }
1455    case nir_op_frsq: {
1456       if (dst.size() == 1) {
1457          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1458       } else if (dst.size() == 2) {
1459          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1460       } else {
1461          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1462          nir_print_instr(&instr->instr, stderr);
1463          fprintf(stderr, "\n");
1464       }
1465       break;
1466    }
1467    case nir_op_fneg: {
1468       Temp src = get_alu_src(ctx, instr->src[0]);
1469       if (dst.size() == 1) {
1470          if (ctx->block->fp_mode.must_flush_denorms32)
1471             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1472          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1473       } else if (dst.size() == 2) {
1474          if (ctx->block->fp_mode.must_flush_denorms16_64)
1475             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1476          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1477          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1478          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1479          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1480       } else {
1481          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1482          nir_print_instr(&instr->instr, stderr);
1483          fprintf(stderr, "\n");
1484       }
1485       break;
1486    }
1487    case nir_op_fabs: {
1488       Temp src = get_alu_src(ctx, instr->src[0]);
1489       if (dst.size() == 1) {
1490          if (ctx->block->fp_mode.must_flush_denorms32)
1491             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1492          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1493       } else if (dst.size() == 2) {
1494          if (ctx->block->fp_mode.must_flush_denorms16_64)
1495             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1496          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1497          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1498          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1499          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1500       } else {
1501          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1502          nir_print_instr(&instr->instr, stderr);
1503          fprintf(stderr, "\n");
1504       }
1505       break;
1506    }
1507    case nir_op_fsat: {
1508       Temp src = get_alu_src(ctx, instr->src[0]);
1509       if (dst.size() == 1) {
1510          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1511       } else if (dst.size() == 2) {
1512          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1513          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1514          vop3->clamp = true;
1515       } else {
1516          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1517          nir_print_instr(&instr->instr, stderr);
1518          fprintf(stderr, "\n");
1519       }
1520       break;
1521    }
1522    case nir_op_flog2: {
1523       if (dst.size() == 1) {
1524          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1525       } else {
1526          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1527          nir_print_instr(&instr->instr, stderr);
1528          fprintf(stderr, "\n");
1529       }
1530       break;
1531    }
1532    case nir_op_frcp: {
1533       if (dst.size() == 1) {
1534          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1535       } else if (dst.size() == 2) {
1536          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1537       } else {
1538          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1539          nir_print_instr(&instr->instr, stderr);
1540          fprintf(stderr, "\n");
1541       }
1542       break;
1543    }
1544    case nir_op_fexp2: {
1545       if (dst.size() == 1) {
1546          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1547       } else {
1548          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1549          nir_print_instr(&instr->instr, stderr);
1550          fprintf(stderr, "\n");
1551       }
1552       break;
1553    }
1554    case nir_op_fsqrt: {
1555       if (dst.size() == 1) {
1556          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1557       } else if (dst.size() == 2) {
1558          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1559       } else {
1560          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1561          nir_print_instr(&instr->instr, stderr);
1562          fprintf(stderr, "\n");
1563       }
1564       break;
1565    }
1566    case nir_op_ffract: {
1567       if (dst.size() == 1) {
1568          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1569       } else if (dst.size() == 2) {
1570          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1571       } else {
1572          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1573          nir_print_instr(&instr->instr, stderr);
1574          fprintf(stderr, "\n");
1575       }
1576       break;
1577    }
1578    case nir_op_ffloor: {
1579       if (dst.size() == 1) {
1580          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1581       } else if (dst.size() == 2) {
1582          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f64, dst);
1583       } else {
1584          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1585          nir_print_instr(&instr->instr, stderr);
1586          fprintf(stderr, "\n");
1587       }
1588       break;
1589    }
1590    case nir_op_fceil: {
1591       if (dst.size() == 1) {
1592          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1593       } else if (dst.size() == 2) {
1594          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1595       } else {
1596          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1597          nir_print_instr(&instr->instr, stderr);
1598          fprintf(stderr, "\n");
1599       }
1600       break;
1601    }
1602    case nir_op_ftrunc: {
1603       if (dst.size() == 1) {
1604          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1605       } else if (dst.size() == 2) {
1606          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f64, dst);
1607       } else {
1608          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1609          nir_print_instr(&instr->instr, stderr);
1610          fprintf(stderr, "\n");
1611       }
1612       break;
1613    }
1614    case nir_op_fround_even: {
1615       if (dst.size() == 1) {
1616          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1617       } else if (dst.size() == 2) {
1618          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1619       } else {
1620          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1621          nir_print_instr(&instr->instr, stderr);
1622          fprintf(stderr, "\n");
1623       }
1624       break;
1625    }
1626    case nir_op_fsin:
1627    case nir_op_fcos: {
1628       Temp src = get_alu_src(ctx, instr->src[0]);
1629       aco_ptr<Instruction> norm;
1630       if (dst.size() == 1) {
1631          Temp tmp;
1632          Operand half_pi(0x3e22f983u);
1633          if (src.type() == RegType::sgpr)
1634             tmp = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1635          else
1636             tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src);
1637
1638          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1639          if (ctx->options->chip_class < GFX9)
1640             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1641
1642          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1643          bld.vop1(opcode, Definition(dst), tmp);
1644       } else {
1645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1646          nir_print_instr(&instr->instr, stderr);
1647          fprintf(stderr, "\n");
1648       }
1649       break;
1650    }
1651    case nir_op_ldexp: {
1652       if (dst.size() == 1) {
1653          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1654                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1655                   get_alu_src(ctx, instr->src[1]));
1656       } else if (dst.size() == 2) {
1657          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1658                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1659                   get_alu_src(ctx, instr->src[1]));
1660       } else {
1661          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1662          nir_print_instr(&instr->instr, stderr);
1663          fprintf(stderr, "\n");
1664       }
1665       break;
1666    }
1667    case nir_op_frexp_sig: {
1668       if (dst.size() == 1) {
1669          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1670                   get_alu_src(ctx, instr->src[0]));
1671       } else if (dst.size() == 2) {
1672          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1673                   get_alu_src(ctx, instr->src[0]));
1674       } else {
1675          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1676          nir_print_instr(&instr->instr, stderr);
1677          fprintf(stderr, "\n");
1678       }
1679       break;
1680    }
1681    case nir_op_frexp_exp: {
1682       if (instr->src[0].src.ssa->bit_size == 32) {
1683          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1684                   get_alu_src(ctx, instr->src[0]));
1685       } else if (instr->src[0].src.ssa->bit_size == 64) {
1686          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1687                   get_alu_src(ctx, instr->src[0]));
1688       } else {
1689          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1690          nir_print_instr(&instr->instr, stderr);
1691          fprintf(stderr, "\n");
1692       }
1693       break;
1694    }
1695    case nir_op_fsign: {
1696       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1697       if (dst.size() == 1) {
1698          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1699          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1700          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1701          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1702       } else if (dst.size() == 2) {
1703          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1704          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1705          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1706
1707          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(s2)), Operand(0u), src);
1708          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1709          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1710
1711          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1712       } else {
1713          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1714          nir_print_instr(&instr->instr, stderr);
1715          fprintf(stderr, "\n");
1716       }
1717       break;
1718    }
1719    case nir_op_f2f32: {
1720       if (instr->src[0].src.ssa->bit_size == 64) {
1721          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1722       } else {
1723          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1724          nir_print_instr(&instr->instr, stderr);
1725          fprintf(stderr, "\n");
1726       }
1727       break;
1728    }
1729    case nir_op_f2f64: {
1730       if (instr->src[0].src.ssa->bit_size == 32) {
1731          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1732       } else {
1733          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1734          nir_print_instr(&instr->instr, stderr);
1735          fprintf(stderr, "\n");
1736       }
1737       break;
1738    }
1739    case nir_op_i2f32: {
1740       assert(dst.size() == 1);
1741       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1742       break;
1743    }
1744    case nir_op_i2f64: {
1745       if (instr->src[0].src.ssa->bit_size == 32) {
1746          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1747       } else if (instr->src[0].src.ssa->bit_size == 64) {
1748          Temp src = get_alu_src(ctx, instr->src[0]);
1749          RegClass rc = RegClass(src.type(), 1);
1750          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1751          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1752          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1753          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1754          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1755          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1756
1757       } else {
1758          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1759          nir_print_instr(&instr->instr, stderr);
1760          fprintf(stderr, "\n");
1761       }
1762       break;
1763    }
1764    case nir_op_u2f32: {
1765       assert(dst.size() == 1);
1766       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1767       break;
1768    }
1769    case nir_op_u2f64: {
1770       if (instr->src[0].src.ssa->bit_size == 32) {
1771          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1772       } else if (instr->src[0].src.ssa->bit_size == 64) {
1773          Temp src = get_alu_src(ctx, instr->src[0]);
1774          RegClass rc = RegClass(src.type(), 1);
1775          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1776          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1777          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1778          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1779          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1780          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1781       } else {
1782          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1783          nir_print_instr(&instr->instr, stderr);
1784          fprintf(stderr, "\n");
1785       }
1786       break;
1787    }
1788    case nir_op_f2i32: {
1789       Temp src = get_alu_src(ctx, instr->src[0]);
1790       if (instr->src[0].src.ssa->bit_size == 32) {
1791          if (dst.type() == RegType::vgpr)
1792             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1793          else
1794             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1795                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1796
1797       } else if (instr->src[0].src.ssa->bit_size == 64) {
1798          if (dst.type() == RegType::vgpr)
1799             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1800          else
1801             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1802                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1803
1804       } else {
1805          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1806          nir_print_instr(&instr->instr, stderr);
1807          fprintf(stderr, "\n");
1808       }
1809       break;
1810    }
1811    case nir_op_f2u32: {
1812       Temp src = get_alu_src(ctx, instr->src[0]);
1813       if (instr->src[0].src.ssa->bit_size == 32) {
1814          if (dst.type() == RegType::vgpr)
1815             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
1816          else
1817             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1818                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
1819
1820       } else if (instr->src[0].src.ssa->bit_size == 64) {
1821          if (dst.type() == RegType::vgpr)
1822             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
1823          else
1824             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1825                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
1826
1827       } else {
1828          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1829          nir_print_instr(&instr->instr, stderr);
1830          fprintf(stderr, "\n");
1831       }
1832       break;
1833    }
1834    case nir_op_f2i64: {
1835       Temp src = get_alu_src(ctx, instr->src[0]);
1836       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1837          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1838          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
1839          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1840          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
1841          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1842          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
1843          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1844          Temp new_exponent = bld.tmp(v1);
1845          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
1846          mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
1847          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
1848          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1849          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1850          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
1851          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
1852          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
1853          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
1854          Temp new_lower = bld.tmp(v1);
1855          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
1856          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
1857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
1858
1859       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1860          if (src.type() == RegType::vgpr)
1861             src = bld.as_uniform(src);
1862          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1863          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1864          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1865          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
1866          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1867          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
1868          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1869          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
1870          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1871          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
1872          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
1873          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
1874          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
1875          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
1876          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1877          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1878          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
1879          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
1880          Temp borrow = bld.tmp(s1);
1881          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
1882          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
1883          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1884
1885       } else if (instr->src[0].src.ssa->bit_size == 64) {
1886          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1887          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1888          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1889          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1890          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1891          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1892          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1893          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
1894          if (dst.type() == RegType::sgpr) {
1895             lower = bld.as_uniform(lower);
1896             upper = bld.as_uniform(upper);
1897          }
1898          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1899
1900       } else {
1901          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1902          nir_print_instr(&instr->instr, stderr);
1903          fprintf(stderr, "\n");
1904       }
1905       break;
1906    }
1907    case nir_op_f2u64: {
1908       Temp src = get_alu_src(ctx, instr->src[0]);
1909       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
1910          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
1911          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(s2)), Operand(64u), exponent);
1912          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
1913          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
1914          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
1915          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
1916          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
1917          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
1918          Temp new_exponent = bld.tmp(v1);
1919          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
1920          mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
1921          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
1922          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1923          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
1924          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
1925          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
1926          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
1927          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1928
1929       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
1930          if (src.type() == RegType::vgpr)
1931             src = bld.as_uniform(src);
1932          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
1933          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
1934          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
1935          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
1936          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
1937          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
1938          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
1939          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
1940          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
1941          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
1942          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
1943          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
1944          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
1945          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
1946          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
1947          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
1948          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
1949          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1950
1951       } else if (instr->src[0].src.ssa->bit_size == 64) {
1952          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
1953          Temp trunc = bld.vop1(aco_opcode::v_trunc_f64, bld.def(v2), src);
1954          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
1955          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
1956          Temp floor  = bld.vop1(aco_opcode::v_floor_f64, bld.def(v2), mul);
1957          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
1958          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
1959          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
1960          if (dst.type() == RegType::sgpr) {
1961             lower = bld.as_uniform(lower);
1962             upper = bld.as_uniform(upper);
1963          }
1964          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1965
1966       } else {
1967          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1968          nir_print_instr(&instr->instr, stderr);
1969          fprintf(stderr, "\n");
1970       }
1971       break;
1972    }
1973    case nir_op_b2f32: {
1974       Temp src = get_alu_src(ctx, instr->src[0]);
1975       assert(src.regClass() == s2);
1976
1977       if (dst.regClass() == s1) {
1978          src = bool_to_scalar_condition(ctx, src);
1979          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
1980       } else if (dst.regClass() == v1) {
1981          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1982       } else {
1983          unreachable("Wrong destination register class for nir_op_b2f32.");
1984       }
1985       break;
1986    }
1987    case nir_op_b2f64: {
1988       Temp src = get_alu_src(ctx, instr->src[0]);
1989       assert(src.regClass() == s2);
1990
1991       if (dst.regClass() == s2) {
1992          src = bool_to_scalar_condition(ctx, src);
1993          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
1994       } else if (dst.regClass() == v2) {
1995          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
1996          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
1997          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1998       } else {
1999          unreachable("Wrong destination register class for nir_op_b2f64.");
2000       }
2001       break;
2002    }
2003    case nir_op_i2i32: {
2004       Temp src = get_alu_src(ctx, instr->src[0]);
2005       if (instr->src[0].src.ssa->bit_size == 64) {
2006          /* we can actually just say dst = src, as it would map the lower register */
2007          emit_extract_vector(ctx, src, 0, dst);
2008       } else {
2009          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2010          nir_print_instr(&instr->instr, stderr);
2011          fprintf(stderr, "\n");
2012       }
2013       break;
2014    }
2015    case nir_op_u2u32: {
2016       Temp src = get_alu_src(ctx, instr->src[0]);
2017       if (instr->src[0].src.ssa->bit_size == 16) {
2018          if (dst.regClass() == s1) {
2019             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2020          } else {
2021             // TODO: do better with SDWA
2022             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2023          }
2024       } else if (instr->src[0].src.ssa->bit_size == 64) {
2025          /* we can actually just say dst = src, as it would map the lower register */
2026          emit_extract_vector(ctx, src, 0, dst);
2027       } else {
2028          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2029          nir_print_instr(&instr->instr, stderr);
2030          fprintf(stderr, "\n");
2031       }
2032       break;
2033    }
2034    case nir_op_i2i64: {
2035       Temp src = get_alu_src(ctx, instr->src[0]);
2036       if (instr->src[0].src.ssa->bit_size == 32) {
2037          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2038       } else {
2039          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2040          nir_print_instr(&instr->instr, stderr);
2041          fprintf(stderr, "\n");
2042       }
2043       break;
2044    }
2045    case nir_op_u2u64: {
2046       Temp src = get_alu_src(ctx, instr->src[0]);
2047       if (instr->src[0].src.ssa->bit_size == 32) {
2048          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2049       } else {
2050          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2051          nir_print_instr(&instr->instr, stderr);
2052          fprintf(stderr, "\n");
2053       }
2054       break;
2055    }
2056    case nir_op_b2i32: {
2057       Temp src = get_alu_src(ctx, instr->src[0]);
2058       assert(src.regClass() == s2);
2059
2060       if (dst.regClass() == s1) {
2061          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2062          bool_to_scalar_condition(ctx, src, dst);
2063       } else if (dst.regClass() == v1) {
2064          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2065       } else {
2066          unreachable("Invalid register class for b2i32");
2067       }
2068       break;
2069    }
2070    case nir_op_i2b1: {
2071       Temp src = get_alu_src(ctx, instr->src[0]);
2072       assert(dst.regClass() == s2);
2073
2074       if (src.type() == RegType::vgpr) {
2075          assert(src.regClass() == v1 || src.regClass() == v2);
2076          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2077                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2078       } else {
2079          assert(src.regClass() == s1 || src.regClass() == s2);
2080          Temp tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2081                              bld.scc(bld.def(s1)), Operand(0u), src);
2082          bool_to_vector_condition(ctx, tmp, dst);
2083       }
2084       break;
2085    }
2086    case nir_op_pack_64_2x32_split: {
2087       Temp src0 = get_alu_src(ctx, instr->src[0]);
2088       Temp src1 = get_alu_src(ctx, instr->src[1]);
2089
2090       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2091       break;
2092    }
2093    case nir_op_unpack_64_2x32_split_x:
2094       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2095       break;
2096    case nir_op_unpack_64_2x32_split_y:
2097       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2098       break;
2099    case nir_op_pack_half_2x16: {
2100       Temp src = get_alu_src(ctx, instr->src[0], 2);
2101
2102       if (dst.regClass() == v1) {
2103          Temp src0 = bld.tmp(v1);
2104          Temp src1 = bld.tmp(v1);
2105          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2106          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2107             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2108          else
2109             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2110                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2111                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2112       } else {
2113          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2114          nir_print_instr(&instr->instr, stderr);
2115          fprintf(stderr, "\n");
2116       }
2117       break;
2118    }
2119    case nir_op_unpack_half_2x16_split_x: {
2120       if (dst.regClass() == v1) {
2121          Builder bld(ctx->program, ctx->block);
2122          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2123       } else {
2124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2125          nir_print_instr(&instr->instr, stderr);
2126          fprintf(stderr, "\n");
2127       }
2128       break;
2129    }
2130    case nir_op_unpack_half_2x16_split_y: {
2131       if (dst.regClass() == v1) {
2132          Builder bld(ctx->program, ctx->block);
2133          /* TODO: use SDWA here */
2134          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2135                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2136       } else {
2137          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2138          nir_print_instr(&instr->instr, stderr);
2139          fprintf(stderr, "\n");
2140       }
2141       break;
2142    }
2143    case nir_op_fquantize2f16: {
2144       Temp src = get_alu_src(ctx, instr->src[0]);
2145       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2146
2147       Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2148
2149       Temp cmp_res = bld.tmp(s2);
2150       bld.vopc_e64(aco_opcode::v_cmp_class_f16, Definition(cmp_res), f16, mask).def(0).setHint(vcc);
2151
2152       Temp f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2153
2154       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32) {
2155          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2156          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2157       } else {
2158          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2159       }
2160       break;
2161    }
2162    case nir_op_bfm: {
2163       Temp bits = get_alu_src(ctx, instr->src[0]);
2164       Temp offset = get_alu_src(ctx, instr->src[1]);
2165
2166       if (dst.regClass() == s1) {
2167          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2168       } else if (dst.regClass() == v1) {
2169          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2170       } else {
2171          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2172          nir_print_instr(&instr->instr, stderr);
2173          fprintf(stderr, "\n");
2174       }
2175       break;
2176    }
2177    case nir_op_bitfield_select: {
2178       /* (mask & insert) | (~mask & base) */
2179       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2180       Temp insert = get_alu_src(ctx, instr->src[1]);
2181       Temp base = get_alu_src(ctx, instr->src[2]);
2182
2183       /* dst = (insert & bitmask) | (base & ~bitmask) */
2184       if (dst.regClass() == s1) {
2185          aco_ptr<Instruction> sop2;
2186          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2187          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2188          Operand lhs;
2189          if (const_insert && const_bitmask) {
2190             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2191          } else {
2192             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2193             lhs = Operand(insert);
2194          }
2195
2196          Operand rhs;
2197          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2198          if (const_base && const_bitmask) {
2199             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2200          } else {
2201             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2202             rhs = Operand(base);
2203          }
2204
2205          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2206
2207       } else if (dst.regClass() == v1) {
2208          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2209             base = as_vgpr(ctx, base);
2210          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2211             insert = as_vgpr(ctx, insert);
2212
2213          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2214
2215       } else {
2216          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2217          nir_print_instr(&instr->instr, stderr);
2218          fprintf(stderr, "\n");
2219       }
2220       break;
2221    }
2222    case nir_op_ubfe:
2223    case nir_op_ibfe: {
2224       Temp base = get_alu_src(ctx, instr->src[0]);
2225       Temp offset = get_alu_src(ctx, instr->src[1]);
2226       Temp bits = get_alu_src(ctx, instr->src[2]);
2227
2228       if (dst.type() == RegType::sgpr) {
2229          Operand extract;
2230          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2231          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2232          if (const_offset && const_bits) {
2233             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2234             extract = Operand(const_extract);
2235          } else {
2236             Operand width;
2237             if (const_bits) {
2238                width = Operand(const_bits->u32 << 16);
2239             } else {
2240                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2241             }
2242             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2243          }
2244
2245          aco_opcode opcode;
2246          if (dst.regClass() == s1) {
2247             if (instr->op == nir_op_ubfe)
2248                opcode = aco_opcode::s_bfe_u32;
2249             else
2250                opcode = aco_opcode::s_bfe_i32;
2251          } else if (dst.regClass() == s2) {
2252             if (instr->op == nir_op_ubfe)
2253                opcode = aco_opcode::s_bfe_u64;
2254             else
2255                opcode = aco_opcode::s_bfe_i64;
2256          } else {
2257             unreachable("Unsupported BFE bit size");
2258          }
2259
2260          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2261
2262       } else {
2263          aco_opcode opcode;
2264          if (dst.regClass() == v1) {
2265             if (instr->op == nir_op_ubfe)
2266                opcode = aco_opcode::v_bfe_u32;
2267             else
2268                opcode = aco_opcode::v_bfe_i32;
2269          } else {
2270             unreachable("Unsupported BFE bit size");
2271          }
2272
2273          emit_vop3a_instruction(ctx, instr, opcode, dst);
2274       }
2275       break;
2276    }
2277    case nir_op_bit_count: {
2278       Temp src = get_alu_src(ctx, instr->src[0]);
2279       if (src.regClass() == s1) {
2280          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2281       } else if (src.regClass() == v1) {
2282          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2283       } else if (src.regClass() == v2) {
2284          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2285                   emit_extract_vector(ctx, src, 1, v1),
2286                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2287                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2288       } else if (src.regClass() == s2) {
2289          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2290       } else {
2291          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2292          nir_print_instr(&instr->instr, stderr);
2293          fprintf(stderr, "\n");
2294       }
2295       break;
2296    }
2297    case nir_op_flt: {
2298       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2299       break;
2300    }
2301    case nir_op_fge: {
2302       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2303       break;
2304    }
2305    case nir_op_feq: {
2306       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2307       break;
2308    }
2309    case nir_op_fne: {
2310       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2311       break;
2312    }
2313    case nir_op_ilt: {
2314       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2315       break;
2316    }
2317    case nir_op_ige: {
2318       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2319       break;
2320    }
2321    case nir_op_ieq: {
2322       if (instr->src[0].src.ssa->bit_size == 1)
2323          emit_boolean_logic(ctx, instr, aco_opcode::s_xnor_b32, aco_opcode::s_xnor_b64, dst);
2324       else
2325          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32, aco_opcode::s_cmp_eq_u64);
2326       break;
2327    }
2328    case nir_op_ine: {
2329       if (instr->src[0].src.ssa->bit_size == 1)
2330          emit_boolean_logic(ctx, instr, aco_opcode::s_xor_b32, aco_opcode::s_xor_b64, dst);
2331       else
2332          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32, aco_opcode::s_cmp_lg_u64);
2333       break;
2334    }
2335    case nir_op_ult: {
2336       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2337       break;
2338    }
2339    case nir_op_uge: {
2340       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2341       break;
2342    }
2343    case nir_op_fddx:
2344    case nir_op_fddy:
2345    case nir_op_fddx_fine:
2346    case nir_op_fddy_fine:
2347    case nir_op_fddx_coarse:
2348    case nir_op_fddy_coarse: {
2349       Definition tl = bld.def(v1);
2350       uint16_t dpp_ctrl;
2351       if (instr->op == nir_op_fddx_fine) {
2352          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 2, 2));
2353          dpp_ctrl = dpp_quad_perm(1, 1, 3, 3);
2354       } else if (instr->op == nir_op_fddy_fine) {
2355          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 1, 0, 1));
2356          dpp_ctrl = dpp_quad_perm(2, 3, 2, 3);
2357       } else {
2358          bld.vop1_dpp(aco_opcode::v_mov_b32, tl, get_alu_src(ctx, instr->src[0]), dpp_quad_perm(0, 0, 0, 0));
2359          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2360             dpp_ctrl = dpp_quad_perm(1, 1, 1, 1);
2361          else
2362             dpp_ctrl = dpp_quad_perm(2, 2, 2, 2);
2363       }
2364
2365       Definition tmp = bld.def(v1);
2366       bld.vop2_dpp(aco_opcode::v_sub_f32, tmp, get_alu_src(ctx, instr->src[0]), tl.getTemp(), dpp_ctrl);
2367       emit_wqm(ctx, tmp.getTemp(), dst, true);
2368       break;
2369    }
2370    default:
2371       fprintf(stderr, "Unknown NIR ALU instr: ");
2372       nir_print_instr(&instr->instr, stderr);
2373       fprintf(stderr, "\n");
2374    }
2375 }
2376
2377 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2378 {
2379    Temp dst = get_ssa_temp(ctx, &instr->def);
2380
2381    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2382    // which get truncated the lsb if double and msb if int
2383    // for now, we only use s_mov_b64 with 64bit inline constants
2384    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2385    assert(dst.type() == RegType::sgpr);
2386
2387    Builder bld(ctx->program, ctx->block);
2388
2389    if (instr->def.bit_size == 1) {
2390       assert(dst.regClass() == s2);
2391       bld.sop1(aco_opcode::s_mov_b64, Definition(dst), Operand((uint64_t)(instr->value[0].b ? -1 : 0)));
2392    } else if (dst.size() == 1) {
2393       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2394    } else {
2395       assert(dst.size() != 1);
2396       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2397       if (instr->def.bit_size == 64)
2398          for (unsigned i = 0; i < dst.size(); i++)
2399             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2400       else {
2401          for (unsigned i = 0; i < dst.size(); i++)
2402             vec->operands[i] = Operand{instr->value[i].u32};
2403       }
2404       vec->definitions[0] = Definition(dst);
2405       ctx->block->instructions.emplace_back(std::move(vec));
2406    }
2407 }
2408
2409 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2410 {
2411    uint32_t new_mask = 0;
2412    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2413       if (mask & (1u << i))
2414          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2415    return new_mask;
2416 }
2417
2418 void visit_store_vs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2419 {
2420    /* This wouldn't work inside control flow or with indirect offsets but
2421     * that doesn't happen because of nir_lower_io_to_temporaries(). */
2422
2423    unsigned write_mask = nir_intrinsic_write_mask(instr);
2424    unsigned component = nir_intrinsic_component(instr);
2425    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2426    unsigned idx = nir_intrinsic_base(instr) + component;
2427
2428    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2429    if (off_instr->type != nir_instr_type_load_const) {
2430       fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2431       nir_print_instr(off_instr, stderr);
2432       fprintf(stderr, "\n");
2433    }
2434    idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2435
2436    if (instr->src[0].ssa->bit_size == 64)
2437       write_mask = widen_mask(write_mask, 2);
2438
2439    for (unsigned i = 0; i < 8; ++i) {
2440       if (write_mask & (1 << i)) {
2441          ctx->vs_output.mask[idx / 4u] |= 1 << (idx % 4u);
2442          ctx->vs_output.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
2443       }
2444       idx++;
2445    }
2446 }
2447
2448 void visit_store_fs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2449 {
2450    unsigned write_mask = nir_intrinsic_write_mask(instr);
2451    Operand values[4];
2452    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2453    for (unsigned i = 0; i < 4; ++i) {
2454       if (write_mask & (1 << i)) {
2455          Temp tmp = emit_extract_vector(ctx, src, i, v1);
2456          values[i] = Operand(tmp);
2457       } else {
2458          values[i] = Operand(v1);
2459       }
2460    }
2461
2462    unsigned index = nir_intrinsic_base(instr) / 4;
2463    unsigned target, col_format;
2464    unsigned enabled_channels = 0xF;
2465    aco_opcode compr_op = (aco_opcode)0;
2466
2467    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2468    assert(offset && "Non-const offsets on exports not yet supported");
2469    index += offset->u32;
2470
2471    assert(index != FRAG_RESULT_COLOR);
2472
2473    /* Unlike vertex shader exports, it's fine to use multiple exports to
2474     * export separate channels of one target. So shaders which export both
2475     * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2476     * TODO: combine the exports in those cases and create better code
2477     */
2478
2479    if (index == FRAG_RESULT_SAMPLE_MASK) {
2480
2481       if (ctx->program->info->ps.writes_z) {
2482          target = V_008DFC_SQ_EXP_MRTZ;
2483          enabled_channels = 0x4;
2484          col_format = (unsigned) -1;
2485
2486          values[2] = values[0];
2487          values[0] = Operand(v1);
2488       } else {
2489          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2490          exp->valid_mask = false;
2491          exp->done = false;
2492          exp->compressed = true;
2493          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2494          exp->enabled_mask = 0xc;
2495          for (int i = 0; i < 4; i++)
2496             exp->operands[i] = Operand(v1);
2497          exp->operands[1] = Operand(values[0]);
2498          ctx->block->instructions.emplace_back(std::move(exp));
2499          return;
2500       }
2501
2502    } else if (index == FRAG_RESULT_DEPTH) {
2503
2504       target = V_008DFC_SQ_EXP_MRTZ;
2505       enabled_channels = 0x1;
2506       col_format = (unsigned) -1;
2507
2508    } else if (index == FRAG_RESULT_STENCIL) {
2509
2510       if (ctx->program->info->ps.writes_z) {
2511          target = V_008DFC_SQ_EXP_MRTZ;
2512          enabled_channels = 0x2;
2513          col_format = (unsigned) -1;
2514
2515          values[1] = values[0];
2516          values[0] = Operand(v1);
2517       } else {
2518          aco_ptr<Instruction> shift{create_instruction<VOP2_instruction>(aco_opcode::v_lshlrev_b32, Format::VOP2, 2, 1)};
2519          shift->operands[0] = Operand((uint32_t) 16);
2520          shift->operands[1] = values[0];
2521          Temp tmp = {ctx->program->allocateId(), v1};
2522          shift->definitions[0] = Definition(tmp);
2523          ctx->block->instructions.emplace_back(std::move(shift));
2524
2525          aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2526          exp->valid_mask = false;
2527          exp->done = false;
2528          exp->compressed = true;
2529          exp->dest = V_008DFC_SQ_EXP_MRTZ;
2530          exp->enabled_mask = 0x3;
2531          exp->operands[0] = Operand(tmp);
2532          for (int i = 1; i < 4; i++)
2533             exp->operands[i] = Operand(v1);
2534          ctx->block->instructions.emplace_back(std::move(exp));
2535          return;
2536       }
2537
2538    } else {
2539       index -= FRAG_RESULT_DATA0;
2540       target = V_008DFC_SQ_EXP_MRT + index;
2541       col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2542    }
2543    ASSERTED bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2544    ASSERTED bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2545    assert(!is_int8 && !is_int10);
2546
2547    switch (col_format)
2548    {
2549    case V_028714_SPI_SHADER_ZERO:
2550       enabled_channels = 0; /* writemask */
2551       target = V_008DFC_SQ_EXP_NULL;
2552       break;
2553
2554    case V_028714_SPI_SHADER_32_R:
2555       enabled_channels = 1;
2556       break;
2557
2558    case V_028714_SPI_SHADER_32_GR:
2559       enabled_channels = 0x3;
2560       break;
2561
2562    case V_028714_SPI_SHADER_32_AR:
2563       if (ctx->options->chip_class >= GFX10) {
2564          /* Special case: on GFX10, the outputs are different for 32_AR */
2565          enabled_channels = 0x3;
2566          values[1] = values[3];
2567       } else {
2568          enabled_channels = 0x9;
2569       }
2570       break;
2571
2572    case V_028714_SPI_SHADER_FP16_ABGR:
2573       enabled_channels = 0x5;
2574       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
2575       break;
2576
2577    case V_028714_SPI_SHADER_UNORM16_ABGR:
2578       enabled_channels = 0x5;
2579       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
2580       break;
2581
2582    case V_028714_SPI_SHADER_SNORM16_ABGR:
2583       enabled_channels = 0x5;
2584       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
2585       break;
2586
2587    case V_028714_SPI_SHADER_UINT16_ABGR:
2588       enabled_channels = 0x5;
2589       compr_op = aco_opcode::v_cvt_pk_u16_u32;
2590       break;
2591
2592    case V_028714_SPI_SHADER_SINT16_ABGR:
2593       enabled_channels = 0x5;
2594       compr_op = aco_opcode::v_cvt_pk_i16_i32;
2595       break;
2596
2597    case V_028714_SPI_SHADER_32_ABGR:
2598       enabled_channels = 0xF;
2599       break;
2600
2601    default:
2602       break;
2603    }
2604
2605    if (target == V_008DFC_SQ_EXP_NULL)
2606       return;
2607
2608    if ((bool)compr_op)
2609    {
2610       for (int i = 0; i < 2; i++)
2611       {
2612          /* check if at least one of the values to be compressed is enabled */
2613          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
2614          if (enabled) {
2615             enabled_channels |= enabled << (i*2);
2616             aco_ptr<VOP3A_instruction> compr{create_instruction<VOP3A_instruction>(compr_op, Format::VOP3A, 2, 1)};
2617             Temp tmp{ctx->program->allocateId(), v1};
2618             compr->operands[0] = values[i*2].isUndefined() ? Operand(0u) : values[i*2];
2619             compr->operands[1] = values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1];
2620             compr->definitions[0] = Definition(tmp);
2621             values[i] = Operand(tmp);
2622             ctx->block->instructions.emplace_back(std::move(compr));
2623          } else {
2624             values[i] = Operand(v1);
2625          }
2626       }
2627    }
2628
2629    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
2630    exp->valid_mask = false;
2631    exp->done = false;
2632    exp->compressed = (bool) compr_op;
2633    exp->dest = target;
2634    exp->enabled_mask = enabled_channels;
2635    if ((bool) compr_op) {
2636       for (int i = 0; i < 2; i++)
2637          exp->operands[i] = enabled_channels & (3 << (i * 2)) ? values[i] : Operand(v1);
2638       exp->operands[2] = Operand(v1);
2639       exp->operands[3] = Operand(v1);
2640    } else {
2641       for (int i = 0; i < 4; i++)
2642          exp->operands[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
2643    }
2644
2645    ctx->block->instructions.emplace_back(std::move(exp));
2646 }
2647
2648 Operand load_lds_size_m0(isel_context *ctx)
2649 {
2650    /* TODO: m0 does not need to be initialized on GFX9+ */
2651    Builder bld(ctx->program, ctx->block);
2652    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2653 }
2654
2655 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2656               Temp address, unsigned base_offset, unsigned align)
2657 {
2658    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2659
2660    Builder bld(ctx->program, ctx->block);
2661
2662    Operand m = load_lds_size_m0(ctx);
2663
2664    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2665    unsigned bytes_read = 0;
2666    unsigned result_size = 0;
2667    unsigned total_bytes = num_components * elem_size_bytes;
2668    std::array<Temp, 4> result;
2669
2670    while (bytes_read < total_bytes) {
2671       unsigned todo = total_bytes - bytes_read;
2672       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2673       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2674
2675       aco_opcode op = aco_opcode::last_opcode;
2676       bool read2 = false;
2677       if (todo >= 16 && aligned16) {
2678          op = aco_opcode::ds_read_b128;
2679          todo = 16;
2680       } else if (todo >= 16 && aligned8) {
2681          op = aco_opcode::ds_read2_b64;
2682          read2 = true;
2683          todo = 16;
2684       } else if (todo >= 12 && aligned16) {
2685          op = aco_opcode::ds_read_b96;
2686          todo = 12;
2687       } else if (todo >= 8 && aligned8) {
2688          op = aco_opcode::ds_read_b64;
2689          todo = 8;
2690       } else if (todo >= 8) {
2691          op = aco_opcode::ds_read2_b32;
2692          read2 = true;
2693          todo = 8;
2694       } else if (todo >= 4) {
2695          op = aco_opcode::ds_read_b32;
2696          todo = 4;
2697       } else {
2698          assert(false);
2699       }
2700       assert(todo % elem_size_bytes == 0);
2701       unsigned num_elements = todo / elem_size_bytes;
2702       unsigned offset = base_offset + bytes_read;
2703       unsigned max_offset = read2 ? 1019 : 65535;
2704
2705       Temp address_offset = address;
2706       if (offset > max_offset) {
2707          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2708          offset = bytes_read;
2709       }
2710       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2711
2712       Temp res;
2713       if (num_components == 1 && dst.type() == RegType::vgpr)
2714          res = dst;
2715       else
2716          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2717
2718       if (read2)
2719          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2720       else
2721          res = bld.ds(op, Definition(res), address_offset, m, offset);
2722
2723       if (num_components == 1) {
2724          assert(todo == total_bytes);
2725          if (dst.type() == RegType::sgpr)
2726             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2727          return;
2728       }
2729
2730       if (dst.type() == RegType::sgpr)
2731          res = bld.as_uniform(res);
2732
2733       if (num_elements == 1) {
2734          result[result_size++] = res;
2735       } else {
2736          assert(res != dst && res.size() % num_elements == 0);
2737          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2738          split->operands[0] = Operand(res);
2739          for (unsigned i = 0; i < num_elements; i++)
2740             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2741          ctx->block->instructions.emplace_back(std::move(split));
2742       }
2743
2744       bytes_read += todo;
2745    }
2746
2747    assert(result_size == num_components && result_size > 1);
2748    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2749    for (unsigned i = 0; i < result_size; i++)
2750       vec->operands[i] = Operand(result[i]);
2751    vec->definitions[0] = Definition(dst);
2752    ctx->block->instructions.emplace_back(std::move(vec));
2753    ctx->allocated_vec.emplace(dst.id(), result);
2754 }
2755
2756 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2757 {
2758    if (start == 0 && size == data.size())
2759       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2760
2761    unsigned size_hint = 1;
2762    auto it = ctx->allocated_vec.find(data.id());
2763    if (it != ctx->allocated_vec.end())
2764       size_hint = it->second[0].size();
2765    if (size % size_hint || start % size_hint)
2766       size_hint = 1;
2767
2768    start /= size_hint;
2769    size /= size_hint;
2770
2771    Temp elems[size];
2772    for (unsigned i = 0; i < size; i++)
2773       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2774
2775    if (size == 1)
2776       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2777
2778    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2779    for (unsigned i = 0; i < size; i++)
2780       vec->operands[i] = Operand(elems[i]);
2781    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2782    vec->definitions[0] = Definition(res);
2783    ctx->block->instructions.emplace_back(std::move(vec));
2784    return res;
2785 }
2786
2787 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2788 {
2789    Builder bld(ctx->program, ctx->block);
2790    unsigned bytes_written = 0;
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849
2850    Operand m = load_lds_size_m0(ctx);
2851
2852    /* we need at most two stores for 32bit variables */
2853    int start[2], count[2];
2854    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2855    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2856    assert(wrmask == 0);
2857
2858    /* one combined store is sufficient */
2859    if (count[0] == count[1]) {
2860       Builder bld(ctx->program, ctx->block);
2861
2862       Temp address_offset = address;
2863       if ((base_offset >> 2) + start[1] > 255) {
2864          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2865          base_offset = 0;
2866       }
2867
2868       assert(count[0] == 1);
2869       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2870       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2871       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2872       base_offset = base_offset / elem_size_bytes;
2873       bld.ds(op, address_offset, val0, val1, m,
2874              base_offset + start[0], base_offset + start[1]);
2875       return;
2876    }
2877
2878    for (unsigned i = 0; i < 2; i++) {
2879       if (count[i] == 0)
2880          continue;
2881
2882       unsigned elem_size_words = elem_size_bytes / 4;
2883       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2884                       base_offset, start[i] * elem_size_bytes, align);
2885    }
2886    return;
2887 }
2888
2889 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2890 {
2891    if (ctx->stage == vertex_vs) {
2892       visit_store_vs_output(ctx, instr);
2893    } else if (ctx->stage == fragment_fs) {
2894       visit_store_fs_output(ctx, instr);
2895    } else {
2896       unreachable("Shader stage not implemented");
2897    }
2898 }
2899
2900 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
2901 {
2902    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
2903    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
2904
2905    Builder bld(ctx->program, ctx->block);
2906    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
2907    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
2908 }
2909
2910 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
2911 {
2912    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
2913    for (unsigned i = 0; i < num_components; i++)
2914       vec->operands[i] = Operand(ctx->fs_inputs[fs_input::frag_pos_0 + i]);
2915
2916    if (ctx->fs_vgpr_args[fs_input::frag_pos_3]) {
2917       assert(num_components == 4);
2918       Builder bld(ctx->program, ctx->block);
2919       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ctx->fs_inputs[fs_input::frag_pos_3]);
2920    }
2921
2922    for (Operand& op : vec->operands)
2923       op = op.isUndefined() ? Operand(0u) : op;
2924
2925    vec->definitions[0] = Definition(dst);
2926    ctx->block->instructions.emplace_back(std::move(vec));
2927    emit_split_vector(ctx, dst, num_components);
2928    return;
2929 }
2930
2931 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
2932 {
2933    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
2934    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
2935    unsigned idx = nir_intrinsic_base(instr);
2936    unsigned component = nir_intrinsic_component(instr);
2937    Temp prim_mask = ctx->prim_mask;
2938
2939    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
2940    if (offset) {
2941       assert(offset->u32 == 0);
2942    } else {
2943       /* the lower 15bit of the prim_mask contain the offset into LDS
2944        * while the upper bits contain the number of prims */
2945       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
2946       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
2947       Builder bld(ctx->program, ctx->block);
2948       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
2949       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
2950       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
2951       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
2952       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
2953    }
2954
2955    if (instr->dest.ssa.num_components == 1) {
2956       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
2957    } else {
2958       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
2959       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
2960       {
2961          Temp tmp = {ctx->program->allocateId(), v1};
2962          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
2963          vec->operands[i] = Operand(tmp);
2964       }
2965       vec->definitions[0] = Definition(dst);
2966       ctx->block->instructions.emplace_back(std::move(vec));
2967    }
2968 }
2969
2970 unsigned get_num_channels_from_data_format(unsigned data_format)
2971 {
2972    switch (data_format) {
2973    case V_008F0C_BUF_DATA_FORMAT_8:
2974    case V_008F0C_BUF_DATA_FORMAT_16:
2975    case V_008F0C_BUF_DATA_FORMAT_32:
2976       return 1;
2977    case V_008F0C_BUF_DATA_FORMAT_8_8:
2978    case V_008F0C_BUF_DATA_FORMAT_16_16:
2979    case V_008F0C_BUF_DATA_FORMAT_32_32:
2980       return 2;
2981    case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2982    case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2983    case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2984       return 3;
2985    case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2986    case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2987    case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2988    case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2989    case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2990       return 4;
2991    default:
2992       break;
2993    }
2994
2995    return 4;
2996 }
2997
2998 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2999  * so we may need to fix it up. */
3000 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3001 {
3002    Builder bld(ctx->program, ctx->block);
3003
3004    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3005       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3006
3007    /* For the integer-like cases, do a natural sign extension.
3008     *
3009     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3010     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3011     * exponent.
3012     */
3013    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3014    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3015
3016    /* Convert back to the right type. */
3017    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3018       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3019       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0xbf800000u), alpha);
3020       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3021    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3022       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3023    }
3024
3025    return alpha;
3026 }
3027
3028 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3029 {
3030    Builder bld(ctx->program, ctx->block);
3031    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3032    if (ctx->stage & sw_vs) {
3033
3034       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3035       if (off_instr->type != nir_instr_type_load_const) {
3036          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3037          nir_print_instr(off_instr, stderr);
3038          fprintf(stderr, "\n");
3039       }
3040       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3041
3042       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, ctx->vertex_buffers);
3043
3044       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3045       unsigned component = nir_intrinsic_component(instr);
3046       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3047       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3048       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3049       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3050
3051       unsigned dfmt = attrib_format & 0xf;
3052
3053       unsigned nfmt = (attrib_format >> 4) & 0x7;
3054       unsigned num_dfmt_channels = get_num_channels_from_data_format(dfmt);
3055       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3056       unsigned num_channels = MIN2(util_last_bit(mask), num_dfmt_channels);
3057       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3058       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3059       if (post_shuffle)
3060          num_channels = MAX2(num_channels, 3);
3061
3062       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, Operand(attrib_binding * 16u));
3063
3064       Temp index;
3065       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3066          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3067          if (divisor) {
3068             ctx->needs_instance_id = true;
3069
3070             if (divisor != 1) {
3071                Temp divided = bld.tmp(v1);
3072                emit_v_div_u32(ctx, divided, as_vgpr(ctx, ctx->instance_id), divisor);
3073                index = bld.vadd32(bld.def(v1), ctx->start_instance, divided);
3074             } else {
3075                index = bld.vadd32(bld.def(v1), ctx->start_instance, ctx->instance_id);
3076             }
3077          } else {
3078             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), ctx->start_instance);
3079          }
3080       } else {
3081          index = bld.vadd32(bld.def(v1), ctx->base_vertex, ctx->vertex_id);
3082       }
3083
3084       if (attrib_stride != 0 && attrib_offset > attrib_stride) {
3085          index = bld.vadd32(bld.def(v1), Operand(attrib_offset / attrib_stride), index);
3086          attrib_offset = attrib_offset % attrib_stride;
3087       }
3088
3089       Operand soffset(0u);
3090       if (attrib_offset >= 4096) {
3091          soffset = bld.copy(bld.def(s1), Operand(attrib_offset));
3092          attrib_offset = 0;
3093       }
3094
3095       aco_opcode opcode;
3096       switch (num_channels) {
3097       case 1:
3098          opcode = aco_opcode::tbuffer_load_format_x;
3099          break;
3100       case 2:
3101          opcode = aco_opcode::tbuffer_load_format_xy;
3102          break;
3103       case 3:
3104          opcode = aco_opcode::tbuffer_load_format_xyz;
3105          break;
3106       case 4:
3107          opcode = aco_opcode::tbuffer_load_format_xyzw;
3108          break;
3109       default:
3110          unreachable("Unimplemented load_input vector size");
3111       }
3112
3113       Temp tmp = post_shuffle || num_channels != dst.size() || alpha_adjust != RADV_ALPHA_ADJUST_NONE || component ? bld.tmp(RegType::vgpr, num_channels) : dst;
3114
3115       aco_ptr<MTBUF_instruction> mubuf{create_instruction<MTBUF_instruction>(opcode, Format::MTBUF, 3, 1)};
3116       mubuf->operands[0] = Operand(index);
3117       mubuf->operands[1] = Operand(list);
3118       mubuf->operands[2] = soffset;
3119       mubuf->definitions[0] = Definition(tmp);
3120       mubuf->idxen = true;
3121       mubuf->can_reorder = true;
3122       mubuf->dfmt = dfmt;
3123       mubuf->nfmt = nfmt;
3124       assert(attrib_offset < 4096);
3125       mubuf->offset = attrib_offset;
3126       ctx->block->instructions.emplace_back(std::move(mubuf));
3127
3128       emit_split_vector(ctx, tmp, tmp.size());
3129
3130       if (tmp.id() != dst.id()) {
3131          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3132                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3133
3134          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3135          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3136          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3137
3138          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3139          for (unsigned i = 0; i < dst.size(); i++) {
3140             unsigned idx = i + component;
3141             if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE && num_channels >= 4) {
3142                Temp alpha = emit_extract_vector(ctx, tmp, swizzle[3], v1);
3143                vec->operands[3] = Operand(adjust_vertex_fetch_alpha(ctx, alpha_adjust, alpha));
3144             } else if (idx < num_channels) {
3145                vec->operands[i] = Operand(emit_extract_vector(ctx, tmp, swizzle[idx], v1));
3146             } else if (is_float && idx == 3) {
3147                vec->operands[i] = Operand(0x3f800000u);
3148             } else if (!is_float && idx == 3) {
3149                vec->operands[i] = Operand(1u);
3150             } else {
3151                vec->operands[i] = Operand(0u);
3152             }
3153          }
3154          vec->definitions[0] = Definition(dst);
3155          ctx->block->instructions.emplace_back(std::move(vec));
3156          emit_split_vector(ctx, dst, dst.size());
3157       }
3158
3159    } else if (ctx->stage == fragment_fs) {
3160       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3161       if (off_instr->type != nir_instr_type_load_const ||
3162           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3163          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3164          nir_print_instr(off_instr, stderr);
3165          fprintf(stderr, "\n");
3166       }
3167
3168       Temp prim_mask = ctx->prim_mask;
3169       nir_const_value* offset = nir_src_as_const_value(instr->src[0]);
3170       if (offset) {
3171          assert(offset->u32 == 0);
3172       } else {
3173          /* the lower 15bit of the prim_mask contain the offset into LDS
3174           * while the upper bits contain the number of prims */
3175          Temp offset_src = get_ssa_temp(ctx, instr->src[0].ssa);
3176          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3177          Builder bld(ctx->program, ctx->block);
3178          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3179          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3180          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3181          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3182          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3183       }
3184
3185       unsigned idx = nir_intrinsic_base(instr);
3186       unsigned component = nir_intrinsic_component(instr);
3187
3188       if (dst.size() == 1) {
3189          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(2u), bld.m0(prim_mask), idx, component);
3190       } else {
3191          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3192          for (unsigned i = 0; i < dst.size(); i++)
3193             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(2u), bld.m0(prim_mask), idx, component + i);
3194          vec->definitions[0] = Definition(dst);
3195          bld.insert(std::move(vec));
3196       }
3197
3198    } else {
3199       unreachable("Shader stage not implemented");
3200    }
3201 }
3202
3203 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3204 {
3205    if (ctx->program->info->need_indirect_descriptor_sets) {
3206       Builder bld(ctx->program, ctx->block);
3207       Temp ptr64 = convert_pointer_to_64_bit(ctx, ctx->descriptor_sets[0]);
3208       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, Operand(desc_set << 2));//, false, false, false);
3209    }
3210
3211    return ctx->descriptor_sets[desc_set];
3212 }
3213
3214
3215 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3216 {
3217    Builder bld(ctx->program, ctx->block);
3218    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3219    if (!ctx->divergent_vals[instr->dest.ssa.index])
3220       index = bld.as_uniform(index);
3221    unsigned desc_set = nir_intrinsic_desc_set(instr);
3222    unsigned binding = nir_intrinsic_binding(instr);
3223
3224    Temp desc_ptr;
3225    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3226    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3227    unsigned offset = layout->binding[binding].offset;
3228    unsigned stride;
3229    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3230        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3231       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3232       desc_ptr = ctx->push_constants;
3233       offset = pipeline_layout->push_constant_size + 16 * idx;
3234       stride = 16;
3235    } else {
3236       desc_ptr = load_desc_ptr(ctx, desc_set);
3237       stride = layout->binding[binding].size;
3238    }
3239
3240    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3241    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3242    if (stride != 1) {
3243       if (nir_const_index) {
3244          const_index = const_index * stride;
3245       } else if (index.type() == RegType::vgpr) {
3246          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3247          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3248       } else {
3249          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3250       }
3251    }
3252    if (offset) {
3253       if (nir_const_index) {
3254          const_index = const_index + offset;
3255       } else if (index.type() == RegType::vgpr) {
3256          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3257       } else {
3258          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3259       }
3260    }
3261
3262    if (nir_const_index && const_index == 0) {
3263       index = desc_ptr;
3264    } else if (index.type() == RegType::vgpr) {
3265       index = bld.vadd32(bld.def(v1),
3266                          nir_const_index ? Operand(const_index) : Operand(index),
3267                          Operand(desc_ptr));
3268    } else {
3269       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3270                        nir_const_index ? Operand(const_index) : Operand(index),
3271                        Operand(desc_ptr));
3272    }
3273
3274    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3275 }
3276
3277 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3278                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3279 {
3280    Builder bld(ctx->program, ctx->block);
3281
3282    unsigned num_bytes = dst.size() * 4;
3283    bool dlc = glc && ctx->options->chip_class >= GFX10;
3284
3285    aco_opcode op;
3286    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
3287       if (ctx->options->chip_class < GFX8)
3288          offset = as_vgpr(ctx, offset);
3289
3290       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3291       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3292       unsigned const_offset = 0;
3293
3294       Temp lower = Temp();
3295       if (num_bytes > 16) {
3296          assert(num_components == 3 || num_components == 4);
3297          op = aco_opcode::buffer_load_dwordx4;
3298          lower = bld.tmp(v4);
3299          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3300          mubuf->definitions[0] = Definition(lower);
3301          mubuf->operands[0] = vaddr;
3302          mubuf->operands[1] = Operand(rsrc);
3303          mubuf->operands[2] = soffset;
3304          mubuf->offen = (offset.type() == RegType::vgpr);
3305          mubuf->glc = glc;
3306          mubuf->dlc = dlc;
3307          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3308          mubuf->can_reorder = readonly;
3309          bld.insert(std::move(mubuf));
3310          emit_split_vector(ctx, lower, 2);
3311          num_bytes -= 16;
3312          const_offset = 16;
3313       }
3314
3315       switch (num_bytes) {
3316          case 4:
3317             op = aco_opcode::buffer_load_dword;
3318             break;
3319          case 8:
3320             op = aco_opcode::buffer_load_dwordx2;
3321             break;
3322          case 12:
3323             op = aco_opcode::buffer_load_dwordx3;
3324             break;
3325          case 16:
3326             op = aco_opcode::buffer_load_dwordx4;
3327             break;
3328          default:
3329             unreachable("Load SSBO not implemented for this size.");
3330       }
3331       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3332       mubuf->operands[0] = vaddr;
3333       mubuf->operands[1] = Operand(rsrc);
3334       mubuf->operands[2] = soffset;
3335       mubuf->offen = (offset.type() == RegType::vgpr);
3336       mubuf->glc = glc;
3337       mubuf->dlc = dlc;
3338       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3339       mubuf->can_reorder = readonly;
3340       mubuf->offset = const_offset;
3341       aco_ptr<Instruction> instr = std::move(mubuf);
3342
3343       if (dst.size() > 4) {
3344          assert(lower != Temp());
3345          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3346          instr->definitions[0] = Definition(upper);
3347          bld.insert(std::move(instr));
3348          if (dst.size() == 8)
3349             emit_split_vector(ctx, upper, 2);
3350          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3351          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3352          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3353          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3354          if (dst.size() == 8)
3355             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3356       }
3357
3358       if (dst.type() == RegType::sgpr) {
3359          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3360          instr->definitions[0] = Definition(vec);
3361          bld.insert(std::move(instr));
3362          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
3363       } else {
3364          instr->definitions[0] = Definition(dst);
3365          bld.insert(std::move(instr));
3366       }
3367    } else {
3368       switch (num_bytes) {
3369          case 4:
3370             op = aco_opcode::s_buffer_load_dword;
3371             break;
3372          case 8:
3373             op = aco_opcode::s_buffer_load_dwordx2;
3374             break;
3375          case 12:
3376          case 16:
3377             op = aco_opcode::s_buffer_load_dwordx4;
3378             break;
3379          case 24:
3380          case 32:
3381             op = aco_opcode::s_buffer_load_dwordx8;
3382             break;
3383          default:
3384             unreachable("Load SSBO not implemented for this size.");
3385       }
3386       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3387       load->operands[0] = Operand(rsrc);
3388       load->operands[1] = Operand(bld.as_uniform(offset));
3389       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3390       load->definitions[0] = Definition(dst);
3391       load->glc = glc;
3392       load->dlc = dlc;
3393       load->barrier = readonly ? barrier_none : barrier_buffer;
3394       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3395       assert(ctx->options->chip_class >= GFX8 || !glc);
3396
3397       /* trim vector */
3398       if (dst.size() == 3) {
3399          Temp vec = bld.tmp(s4);
3400          load->definitions[0] = Definition(vec);
3401          bld.insert(std::move(load));
3402          emit_split_vector(ctx, vec, 4);
3403
3404          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3405                     emit_extract_vector(ctx, vec, 0, s1),
3406                     emit_extract_vector(ctx, vec, 1, s1),
3407                     emit_extract_vector(ctx, vec, 2, s1));
3408       } else if (dst.size() == 6) {
3409          Temp vec = bld.tmp(s8);
3410          load->definitions[0] = Definition(vec);
3411          bld.insert(std::move(load));
3412          emit_split_vector(ctx, vec, 4);
3413
3414          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3415                     emit_extract_vector(ctx, vec, 0, s2),
3416                     emit_extract_vector(ctx, vec, 1, s2),
3417                     emit_extract_vector(ctx, vec, 2, s2));
3418       } else {
3419          bld.insert(std::move(load));
3420       }
3421
3422    }
3423    emit_split_vector(ctx, dst, num_components);
3424 }
3425
3426 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3427 {
3428    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3429    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3430
3431    Builder bld(ctx->program, ctx->block);
3432
3433    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3434    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3435    unsigned binding = nir_intrinsic_binding(idx_instr);
3436    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3437
3438    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3439       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3440                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3441                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3442                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3443       if (ctx->options->chip_class >= GFX10) {
3444          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3445                       S_008F0C_OOB_SELECT(3) |
3446                       S_008F0C_RESOURCE_LEVEL(1);
3447       } else {
3448          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3449                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3450       }
3451       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3452                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3453                                      Operand(0xFFFFFFFFu),
3454                                      Operand(desc_type));
3455       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3456                         rsrc, upper_dwords);
3457    } else {
3458       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3459       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3460    }
3461
3462    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3463 }
3464
3465 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3466 {
3467    Builder bld(ctx->program, ctx->block);
3468    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3469
3470    unsigned offset = nir_intrinsic_base(instr);
3471    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3472    if (index_cv && instr->dest.ssa.bit_size == 32) {
3473
3474       unsigned count = instr->dest.ssa.num_components;
3475       unsigned start = (offset + index_cv->u32) / 4u;
3476       start -= ctx->base_inline_push_consts;
3477       if (start + count <= ctx->num_inline_push_consts) {
3478          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3479          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3480          for (unsigned i = 0; i < count; ++i) {
3481             elems[i] = ctx->inline_push_consts[start + i];
3482             vec->operands[i] = Operand{elems[i]};
3483          }
3484          vec->definitions[0] = Definition(dst);
3485          ctx->block->instructions.emplace_back(std::move(vec));
3486          ctx->allocated_vec.emplace(dst.id(), elems);
3487          return;
3488       }
3489    }
3490
3491    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3492    if (offset != 0) // TODO check if index != 0 as well
3493       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3494    Temp ptr = convert_pointer_to_64_bit(ctx, ctx->push_constants);
3495    Temp vec = dst;
3496    bool trim = false;
3497    aco_opcode op;
3498
3499    switch (dst.size()) {
3500    case 1:
3501       op = aco_opcode::s_load_dword;
3502       break;
3503    case 2:
3504       op = aco_opcode::s_load_dwordx2;
3505       break;
3506    case 3:
3507       vec = bld.tmp(s4);
3508       trim = true;
3509    case 4:
3510       op = aco_opcode::s_load_dwordx4;
3511       break;
3512    case 6:
3513       vec = bld.tmp(s8);
3514       trim = true;
3515    case 8:
3516       op = aco_opcode::s_load_dwordx8;
3517       break;
3518    default:
3519       unreachable("unimplemented or forbidden load_push_constant.");
3520    }
3521
3522    bld.smem(op, Definition(vec), ptr, index);
3523
3524    if (trim) {
3525       emit_split_vector(ctx, vec, 4);
3526       RegClass rc = dst.size() == 3 ? s1 : s2;
3527       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3528                  emit_extract_vector(ctx, vec, 0, rc),
3529                  emit_extract_vector(ctx, vec, 1, rc),
3530                  emit_extract_vector(ctx, vec, 2, rc));
3531
3532    }
3533    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3534 }
3535
3536 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3537 {
3538    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3539
3540    Builder bld(ctx->program, ctx->block);
3541
3542    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3543                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3544                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3545                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3546    if (ctx->options->chip_class >= GFX10) {
3547       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3548                    S_008F0C_OOB_SELECT(3) |
3549                    S_008F0C_RESOURCE_LEVEL(1);
3550    } else {
3551       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3552                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3553    }
3554
3555    unsigned base = nir_intrinsic_base(instr);
3556    unsigned range = nir_intrinsic_range(instr);
3557
3558    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3559    if (base && offset.type() == RegType::sgpr)
3560       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3561    else if (base && offset.type() == RegType::vgpr)
3562       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3563
3564    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3565                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3566                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3567                           Operand(desc_type));
3568
3569    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3570 }
3571
3572 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3573 {
3574    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3575       ctx->cf_info.exec_potentially_empty = true;
3576
3577    ctx->program->needs_exact = true;
3578
3579    // TODO: optimize uniform conditions
3580    Builder bld(ctx->program, ctx->block);
3581    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3582    assert(src.regClass() == s2);
3583    src = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
3584    bld.pseudo(aco_opcode::p_discard_if, src);
3585    ctx->block->kind |= block_kind_uses_discard_if;
3586    return;
3587 }
3588
3589 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3590 {
3591    Builder bld(ctx->program, ctx->block);
3592
3593    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3594       ctx->cf_info.exec_potentially_empty = true;
3595
3596    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3597                     ctx->cf_info.parent_loop.has_divergent_continue;
3598
3599    if (ctx->block->loop_nest_depth &&
3600        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3601       /* we handle discards the same way as jump instructions */
3602       append_logical_end(ctx->block);
3603
3604       /* in loops, discard behaves like break */
3605       Block *linear_target = ctx->cf_info.parent_loop.exit;
3606       ctx->block->kind |= block_kind_discard;
3607
3608       if (!divergent) {
3609          /* uniform discard - loop ends here */
3610          assert(nir_instr_is_last(&instr->instr));
3611          ctx->block->kind |= block_kind_uniform;
3612          ctx->cf_info.has_branch = true;
3613          bld.branch(aco_opcode::p_branch);
3614          add_linear_edge(ctx->block->index, linear_target);
3615          return;
3616       }
3617
3618       /* we add a break right behind the discard() instructions */
3619       ctx->block->kind |= block_kind_break;
3620       unsigned idx = ctx->block->index;
3621
3622       /* remove critical edges from linear CFG */
3623       bld.branch(aco_opcode::p_branch);
3624       Block* break_block = ctx->program->create_and_insert_block();
3625       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3626       break_block->kind |= block_kind_uniform;
3627       add_linear_edge(idx, break_block);
3628       add_linear_edge(break_block->index, linear_target);
3629       bld.reset(break_block);
3630       bld.branch(aco_opcode::p_branch);
3631
3632       Block* continue_block = ctx->program->create_and_insert_block();
3633       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3634       add_linear_edge(idx, continue_block);
3635       append_logical_start(continue_block);
3636       ctx->block = continue_block;
3637
3638       return;
3639    }
3640
3641    /* it can currently happen that NIR doesn't remove the unreachable code */
3642    if (!nir_instr_is_last(&instr->instr)) {
3643       ctx->program->needs_exact = true;
3644       /* save exec somewhere temporarily so that it doesn't get
3645        * overwritten before the discard from outer exec masks */
3646       Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, s2));
3647       bld.pseudo(aco_opcode::p_discard_if, cond);
3648       ctx->block->kind |= block_kind_uses_discard_if;
3649       return;
3650    }
3651
3652    /* This condition is incorrect for uniformly branched discards in a loop
3653     * predicated by a divergent condition, but the above code catches that case
3654     * and the discard would end up turning into a discard_if.
3655     * For example:
3656     * if (divergent) {
3657     *    while (...) {
3658     *       if (uniform) {
3659     *          discard;
3660     *       }
3661     *    }
3662     * }
3663     */
3664    if (!ctx->cf_info.parent_if.is_divergent) {
3665       /* program just ends here */
3666       ctx->block->kind |= block_kind_uniform;
3667       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
3668               0 /* enabled mask */, 9 /* dest */,
3669               false /* compressed */, true/* done */, true /* valid mask */);
3670       bld.sopp(aco_opcode::s_endpgm);
3671       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3672    } else {
3673       ctx->block->kind |= block_kind_discard;
3674       /* branch and linear edge is added by visit_if() */
3675    }
3676 }
3677
3678 enum aco_descriptor_type {
3679    ACO_DESC_IMAGE,
3680    ACO_DESC_FMASK,
3681    ACO_DESC_SAMPLER,
3682    ACO_DESC_BUFFER,
3683    ACO_DESC_PLANE_0,
3684    ACO_DESC_PLANE_1,
3685    ACO_DESC_PLANE_2,
3686 };
3687
3688 static bool
3689 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
3690    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
3691       return false;
3692    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
3693    return dim == ac_image_cube ||
3694           dim == ac_image_1darray ||
3695           dim == ac_image_2darray ||
3696           dim == ac_image_2darraymsaa;
3697 }
3698
3699 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
3700                       enum aco_descriptor_type desc_type,
3701                       const nir_tex_instr *tex_instr, bool image, bool write)
3702 {
3703 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3704    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3705    if (it != ctx->tex_desc.end())
3706       return it->second;
3707 */
3708    Temp index = Temp();
3709    bool index_set = false;
3710    unsigned constant_index = 0;
3711    unsigned descriptor_set;
3712    unsigned base_index;
3713    Builder bld(ctx->program, ctx->block);
3714
3715    if (!deref_instr) {
3716       assert(tex_instr && !image);
3717       descriptor_set = 0;
3718       base_index = tex_instr->sampler_index;
3719    } else {
3720       while(deref_instr->deref_type != nir_deref_type_var) {
3721          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
3722          if (!array_size)
3723             array_size = 1;
3724
3725          assert(deref_instr->deref_type == nir_deref_type_array);
3726          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
3727          if (const_value) {
3728             constant_index += array_size * const_value->u32;
3729          } else {
3730             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
3731             if (indirect.type() == RegType::vgpr)
3732                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
3733
3734             if (array_size != 1)
3735                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
3736
3737             if (!index_set) {
3738                index = indirect;
3739                index_set = true;
3740             } else {
3741                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
3742             }
3743          }
3744
3745          deref_instr = nir_src_as_deref(deref_instr->parent);
3746       }
3747       descriptor_set = deref_instr->var->data.descriptor_set;
3748       base_index = deref_instr->var->data.binding;
3749    }
3750
3751    Temp list = load_desc_ptr(ctx, descriptor_set);
3752    list = convert_pointer_to_64_bit(ctx, list);
3753
3754    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
3755    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
3756    unsigned offset = binding->offset;
3757    unsigned stride = binding->size;
3758    aco_opcode opcode;
3759    RegClass type;
3760
3761    assert(base_index < layout->binding_count);
3762
3763    switch (desc_type) {
3764    case ACO_DESC_IMAGE:
3765       type = s8;
3766       opcode = aco_opcode::s_load_dwordx8;
3767       break;
3768    case ACO_DESC_FMASK:
3769       type = s8;
3770       opcode = aco_opcode::s_load_dwordx8;
3771       offset += 32;
3772       break;
3773    case ACO_DESC_SAMPLER:
3774       type = s4;
3775       opcode = aco_opcode::s_load_dwordx4;
3776       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3777          offset += radv_combined_image_descriptor_sampler_offset(binding);
3778       break;
3779    case ACO_DESC_BUFFER:
3780       type = s4;
3781       opcode = aco_opcode::s_load_dwordx4;
3782       break;
3783    case ACO_DESC_PLANE_0:
3784    case ACO_DESC_PLANE_1:
3785       type = s8;
3786       opcode = aco_opcode::s_load_dwordx8;
3787       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
3788       break;
3789    case ACO_DESC_PLANE_2:
3790       type = s4;
3791       opcode = aco_opcode::s_load_dwordx4;
3792       offset += 64;
3793       break;
3794    default:
3795       unreachable("invalid desc_type\n");
3796    }
3797
3798    offset += constant_index * stride;
3799
3800    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
3801       (!index_set || binding->immutable_samplers_equal)) {
3802       if (binding->immutable_samplers_equal)
3803          constant_index = 0;
3804
3805       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
3806       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3807                         Operand(samplers[constant_index * 4 + 0]),
3808                         Operand(samplers[constant_index * 4 + 1]),
3809                         Operand(samplers[constant_index * 4 + 2]),
3810                         Operand(samplers[constant_index * 4 + 3]));
3811    }
3812
3813    Operand off;
3814    if (!index_set) {
3815       off = Operand(offset);
3816    } else {
3817       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
3818                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
3819    }
3820
3821    Temp res = bld.smem(opcode, bld.def(type), list, off);
3822
3823    if (desc_type == ACO_DESC_PLANE_2) {
3824       Temp components[8];
3825       for (unsigned i = 0; i < 8; i++)
3826          components[i] = bld.tmp(s1);
3827       bld.pseudo(aco_opcode::p_split_vector,
3828                  Definition(components[0]),
3829                  Definition(components[1]),
3830                  Definition(components[2]),
3831                  Definition(components[3]),
3832                  res);
3833
3834       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
3835       bld.pseudo(aco_opcode::p_split_vector,
3836                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
3837                  Definition(components[4]),
3838                  Definition(components[5]),
3839                  Definition(components[6]),
3840                  Definition(components[7]),
3841                  desc2);
3842
3843       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
3844                        components[0], components[1], components[2], components[3],
3845                        components[4], components[5], components[6], components[7]);
3846    }
3847
3848    return res;
3849 }
3850
3851 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3852 {
3853    switch (dim) {
3854    case GLSL_SAMPLER_DIM_BUF:
3855       return 1;
3856    case GLSL_SAMPLER_DIM_1D:
3857       return array ? 2 : 1;
3858    case GLSL_SAMPLER_DIM_2D:
3859       return array ? 3 : 2;
3860    case GLSL_SAMPLER_DIM_MS:
3861       return array ? 4 : 3;
3862    case GLSL_SAMPLER_DIM_3D:
3863    case GLSL_SAMPLER_DIM_CUBE:
3864       return 3;
3865    case GLSL_SAMPLER_DIM_RECT:
3866    case GLSL_SAMPLER_DIM_SUBPASS:
3867       return 2;
3868    case GLSL_SAMPLER_DIM_SUBPASS_MS:
3869       return 3;
3870    default:
3871       break;
3872    }
3873    return 0;
3874 }
3875
3876
3877 /* Adjust the sample index according to FMASK.
3878  *
3879  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3880  * which is the identity mapping. Each nibble says which physical sample
3881  * should be fetched to get that sample.
3882  *
3883  * For example, 0x11111100 means there are only 2 samples stored and
3884  * the second sample covers 3/4 of the pixel. When reading samples 0
3885  * and 1, return physical sample 0 (determined by the first two 0s
3886  * in FMASK), otherwise return physical sample 1.
3887  *
3888  * The sample index should be adjusted as follows:
3889  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
3890  */
3891 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, Temp coords, Operand sample_index, Temp fmask_desc_ptr)
3892 {
3893    Builder bld(ctx->program, ctx->block);
3894    Temp fmask = bld.tmp(v1);
3895    unsigned dim = ctx->options->chip_class >= GFX10
3896                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
3897                   : 0;
3898
3899    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
3900    load->operands[0] = Operand(coords);
3901    load->operands[1] = Operand(fmask_desc_ptr);
3902    load->definitions[0] = Definition(fmask);
3903    load->glc = false;
3904    load->dlc = false;
3905    load->dmask = 0x1;
3906    load->unrm = true;
3907    load->da = da;
3908    load->dim = dim;
3909    load->can_reorder = true; /* fmask images shouldn't be modified */
3910    ctx->block->instructions.emplace_back(std::move(load));
3911
3912    Operand sample_index4;
3913    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
3914       sample_index4 = Operand(sample_index.constantValue() << 2);
3915    } else if (sample_index.regClass() == s1) {
3916       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
3917    } else {
3918       assert(sample_index.regClass() == v1);
3919       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
3920    }
3921
3922    Temp final_sample;
3923    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
3924       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
3925    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
3926       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
3927    else
3928       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
3929
3930    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3931     * resource descriptor is 0 (invalid),
3932     */
3933    Temp compare = bld.tmp(s2);
3934    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
3935                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
3936
3937    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
3938
3939    /* Replace the MSAA sample index. */
3940    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
3941 }
3942
3943 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
3944 {
3945
3946    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
3947    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3948    bool is_array = glsl_sampler_type_is_array(type);
3949    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3950    assert(!add_frag_pos && "Input attachments should be lowered.");
3951    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3952    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3953    int count = image_type_to_components_count(dim, is_array);
3954    std::vector<Operand> coords(count);
3955
3956    if (is_ms) {
3957       Operand sample_index;
3958       nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
3959       if (sample_cv)
3960          sample_index = Operand(sample_cv->u32);
3961       else
3962          sample_index = Operand(emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[2].ssa), 0, v1));
3963
3964       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
3965          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, is_array ? 3 : 2, 1)};
3966          for (unsigned i = 0; i < vec->operands.size(); i++)
3967             vec->operands[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
3968          Temp fmask_load_address = {ctx->program->allocateId(), is_array ? v3 : v2};
3969          vec->definitions[0] = Definition(fmask_load_address);
3970          ctx->block->instructions.emplace_back(std::move(vec));
3971
3972          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
3973          sample_index = Operand(adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr));
3974       }
3975       count--;
3976       coords[count] = sample_index;
3977    }
3978
3979    if (count == 1 && !gfx9_1d)
3980       return emit_extract_vector(ctx, src0, 0, v1);
3981
3982    if (gfx9_1d) {
3983       coords[0] = Operand(emit_extract_vector(ctx, src0, 0, v1));
3984       coords.resize(coords.size() + 1);
3985       coords[1] = Operand((uint32_t) 0);
3986       if (is_array)
3987          coords[2] = Operand(emit_extract_vector(ctx, src0, 1, v1));
3988    } else {
3989       for (int i = 0; i < count; i++)
3990          coords[i] = Operand(emit_extract_vector(ctx, src0, i, v1));
3991    }
3992
3993    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
3994    for (unsigned i = 0; i < coords.size(); i++)
3995       vec->operands[i] = coords[i];
3996    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
3997    vec->definitions[0] = Definition(res);
3998    ctx->block->instructions.emplace_back(std::move(vec));
3999    return res;
4000 }
4001
4002
4003 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4004 {
4005    Builder bld(ctx->program, ctx->block);
4006    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4007    const struct glsl_type *type = glsl_without_array(var->type);
4008    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4009    bool is_array = glsl_sampler_type_is_array(type);
4010    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4011
4012    if (dim == GLSL_SAMPLER_DIM_BUF) {
4013       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4014       unsigned num_channels = util_last_bit(mask);
4015       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4016       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4017
4018       aco_opcode opcode;
4019       switch (num_channels) {
4020       case 1:
4021          opcode = aco_opcode::buffer_load_format_x;
4022          break;
4023       case 2:
4024          opcode = aco_opcode::buffer_load_format_xy;
4025          break;
4026       case 3:
4027          opcode = aco_opcode::buffer_load_format_xyz;
4028          break;
4029       case 4:
4030          opcode = aco_opcode::buffer_load_format_xyzw;
4031          break;
4032       default:
4033          unreachable(">4 channel buffer image load");
4034       }
4035       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4036       load->operands[0] = Operand(vindex);
4037       load->operands[1] = Operand(rsrc);
4038       load->operands[2] = Operand((uint32_t) 0);
4039       Temp tmp;
4040       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4041          tmp = dst;
4042       else
4043          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4044       load->definitions[0] = Definition(tmp);
4045       load->idxen = true;
4046       load->barrier = barrier_image;
4047       ctx->block->instructions.emplace_back(std::move(load));
4048
4049       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4050       return;
4051    }
4052
4053    Temp coords = get_image_coords(ctx, instr, type);
4054    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4055
4056    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4057    unsigned num_components = util_bitcount(dmask);
4058    Temp tmp;
4059    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4060       tmp = dst;
4061    else
4062       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4063
4064    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 2, 1)};
4065    load->operands[0] = Operand(coords);
4066    load->operands[1] = Operand(resource);
4067    load->definitions[0] = Definition(tmp);
4068    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4069    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4070    load->dmask = dmask;
4071    load->unrm = true;
4072    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4073    load->barrier = barrier_image;
4074    ctx->block->instructions.emplace_back(std::move(load));
4075
4076    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4077    return;
4078 }
4079
4080 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4081 {
4082    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4083    const struct glsl_type *type = glsl_without_array(var->type);
4084    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4085    bool is_array = glsl_sampler_type_is_array(type);
4086    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4087
4088    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4089
4090    if (dim == GLSL_SAMPLER_DIM_BUF) {
4091       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4092       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4093       aco_opcode opcode;
4094       switch (data.size()) {
4095       case 1:
4096          opcode = aco_opcode::buffer_store_format_x;
4097          break;
4098       case 2:
4099          opcode = aco_opcode::buffer_store_format_xy;
4100          break;
4101       case 3:
4102          opcode = aco_opcode::buffer_store_format_xyz;
4103          break;
4104       case 4:
4105          opcode = aco_opcode::buffer_store_format_xyzw;
4106          break;
4107       default:
4108          unreachable(">4 channel buffer image store");
4109       }
4110       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4111       store->operands[0] = Operand(vindex);
4112       store->operands[1] = Operand(rsrc);
4113       store->operands[2] = Operand((uint32_t) 0);
4114       store->operands[3] = Operand(data);
4115       store->idxen = true;
4116       store->glc = glc;
4117       store->dlc = false;
4118       store->disable_wqm = true;
4119       store->barrier = barrier_image;
4120       ctx->program->needs_exact = true;
4121       ctx->block->instructions.emplace_back(std::move(store));
4122       return;
4123    }
4124
4125    assert(data.type() == RegType::vgpr);
4126    Temp coords = get_image_coords(ctx, instr, type);
4127    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4128
4129    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(aco_opcode::image_store, Format::MIMG, 4, 0)};
4130    store->operands[0] = Operand(coords);
4131    store->operands[1] = Operand(resource);
4132    store->operands[2] = Operand(s4);
4133    store->operands[3] = Operand(data);
4134    store->glc = glc;
4135    store->dlc = false;
4136    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4137    store->dmask = (1 << data.size()) - 1;
4138    store->unrm = true;
4139    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4140    store->disable_wqm = true;
4141    store->barrier = barrier_image;
4142    ctx->program->needs_exact = true;
4143    ctx->block->instructions.emplace_back(std::move(store));
4144    return;
4145 }
4146
4147 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4148 {
4149    /* return the previous value if dest is ever used */
4150    bool return_previous = false;
4151    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4152       return_previous = true;
4153       break;
4154    }
4155    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4156       return_previous = true;
4157       break;
4158    }
4159
4160    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4161    const struct glsl_type *type = glsl_without_array(var->type);
4162    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4163    bool is_array = glsl_sampler_type_is_array(type);
4164    Builder bld(ctx->program, ctx->block);
4165
4166    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4167    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4168
4169    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4170       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4171
4172    aco_opcode buf_op, image_op;
4173    switch (instr->intrinsic) {
4174       case nir_intrinsic_image_deref_atomic_add:
4175          buf_op = aco_opcode::buffer_atomic_add;
4176          image_op = aco_opcode::image_atomic_add;
4177          break;
4178       case nir_intrinsic_image_deref_atomic_umin:
4179          buf_op = aco_opcode::buffer_atomic_umin;
4180          image_op = aco_opcode::image_atomic_umin;
4181          break;
4182       case nir_intrinsic_image_deref_atomic_imin:
4183          buf_op = aco_opcode::buffer_atomic_smin;
4184          image_op = aco_opcode::image_atomic_smin;
4185          break;
4186       case nir_intrinsic_image_deref_atomic_umax:
4187          buf_op = aco_opcode::buffer_atomic_umax;
4188          image_op = aco_opcode::image_atomic_umax;
4189          break;
4190       case nir_intrinsic_image_deref_atomic_imax:
4191          buf_op = aco_opcode::buffer_atomic_smax;
4192          image_op = aco_opcode::image_atomic_smax;
4193          break;
4194       case nir_intrinsic_image_deref_atomic_and:
4195          buf_op = aco_opcode::buffer_atomic_and;
4196          image_op = aco_opcode::image_atomic_and;
4197          break;
4198       case nir_intrinsic_image_deref_atomic_or:
4199          buf_op = aco_opcode::buffer_atomic_or;
4200          image_op = aco_opcode::image_atomic_or;
4201          break;
4202       case nir_intrinsic_image_deref_atomic_xor:
4203          buf_op = aco_opcode::buffer_atomic_xor;
4204          image_op = aco_opcode::image_atomic_xor;
4205          break;
4206       case nir_intrinsic_image_deref_atomic_exchange:
4207          buf_op = aco_opcode::buffer_atomic_swap;
4208          image_op = aco_opcode::image_atomic_swap;
4209          break;
4210       case nir_intrinsic_image_deref_atomic_comp_swap:
4211          buf_op = aco_opcode::buffer_atomic_cmpswap;
4212          image_op = aco_opcode::image_atomic_cmpswap;
4213          break;
4214       default:
4215          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4216    }
4217
4218    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4219
4220    if (dim == GLSL_SAMPLER_DIM_BUF) {
4221       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4222       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4223       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4224       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4225       mubuf->operands[0] = Operand(vindex);
4226       mubuf->operands[1] = Operand(resource);
4227       mubuf->operands[2] = Operand((uint32_t)0);
4228       mubuf->operands[3] = Operand(data);
4229       if (return_previous)
4230          mubuf->definitions[0] = Definition(dst);
4231       mubuf->offset = 0;
4232       mubuf->idxen = true;
4233       mubuf->glc = return_previous;
4234       mubuf->dlc = false; /* Not needed for atomics */
4235       mubuf->disable_wqm = true;
4236       mubuf->barrier = barrier_image;
4237       ctx->program->needs_exact = true;
4238       ctx->block->instructions.emplace_back(std::move(mubuf));
4239       return;
4240    }
4241
4242    Temp coords = get_image_coords(ctx, instr, type);
4243    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4244    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 4, return_previous ? 1 : 0)};
4245    mimg->operands[0] = Operand(coords);
4246    mimg->operands[1] = Operand(resource);
4247    mimg->operands[2] = Operand(s4); /* no sampler */
4248    mimg->operands[3] = Operand(data);
4249    if (return_previous)
4250       mimg->definitions[0] = Definition(dst);
4251    mimg->glc = return_previous;
4252    mimg->dlc = false; /* Not needed for atomics */
4253    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4254    mimg->dmask = (1 << data.size()) - 1;
4255    mimg->unrm = true;
4256    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4257    mimg->disable_wqm = true;
4258    mimg->barrier = barrier_image;
4259    ctx->program->needs_exact = true;
4260    ctx->block->instructions.emplace_back(std::move(mimg));
4261    return;
4262 }
4263
4264 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4265 {
4266    if (in_elements && ctx->options->chip_class == GFX8) {
4267       Builder bld(ctx->program, ctx->block);
4268
4269       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4270       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4271       stride = bld.vop1(aco_opcode::v_cvt_f32_ubyte0, bld.def(v1), stride);
4272       stride = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), stride);
4273
4274       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4275       size = bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), size);
4276
4277       Temp res = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), size, stride);
4278       res = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), res);
4279       bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
4280
4281       // TODO: we can probably calculate this faster on the scalar unit to do: size / stride{1,2,4,8,12,16}
4282       /* idea
4283        * for 1,2,4,8,16, the result is just (stride >> S_FF1_I32_B32)
4284        * in case 12 (or 3?), we have to divide by 3:
4285        * set v_skip in case it's 12 (if we also have to take care of 3, shift first)
4286        * use v_mul_hi_u32 with magic number to divide
4287        * we need some pseudo merge opcode to overwrite the original SALU result with readfirstlane
4288        * disable v_skip
4289        * total: 6 SALU + 2 VALU instructions vs 1 SALU + 6 VALU instructions
4290        */
4291
4292    } else {
4293       emit_extract_vector(ctx, desc, 2, dst);
4294    }
4295 }
4296
4297 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4298 {
4299    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4300    const struct glsl_type *type = glsl_without_array(var->type);
4301    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4302    bool is_array = glsl_sampler_type_is_array(type);
4303    Builder bld(ctx->program, ctx->block);
4304
4305    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4306       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4307       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4308    }
4309
4310    /* LOD */
4311    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4312
4313    /* Resource */
4314    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4315
4316    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4317
4318    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1)};
4319    mimg->operands[0] = Operand(lod);
4320    mimg->operands[1] = Operand(resource);
4321    unsigned& dmask = mimg->dmask;
4322    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4323    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4324    mimg->da = glsl_sampler_type_is_array(type);
4325    mimg->can_reorder = true;
4326    Definition& def = mimg->definitions[0];
4327    ctx->block->instructions.emplace_back(std::move(mimg));
4328
4329    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4330        glsl_sampler_type_is_array(type)) {
4331
4332       assert(instr->dest.ssa.num_components == 3);
4333       Temp tmp = {ctx->program->allocateId(), v3};
4334       def = Definition(tmp);
4335       emit_split_vector(ctx, tmp, 3);
4336
4337       /* divide 3rd value by 6 by multiplying with magic number */
4338       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4339       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4340
4341       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4342                  emit_extract_vector(ctx, tmp, 0, v1),
4343                  emit_extract_vector(ctx, tmp, 1, v1),
4344                  by_6);
4345
4346    } else if (ctx->options->chip_class == GFX9 &&
4347               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4348               glsl_sampler_type_is_array(type)) {
4349       assert(instr->dest.ssa.num_components == 2);
4350       def = Definition(dst);
4351       dmask = 0x5;
4352    } else {
4353       def = Definition(dst);
4354    }
4355
4356    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4357 }
4358
4359 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4360 {
4361    Builder bld(ctx->program, ctx->block);
4362    unsigned num_components = instr->num_components;
4363
4364    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4365    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4366    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4367
4368    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4369    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4370 }
4371
4372 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4373 {
4374    Builder bld(ctx->program, ctx->block);
4375    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4376    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4377    unsigned writemask = nir_intrinsic_write_mask(instr);
4378
4379    Temp offset;
4380    if (ctx->options->chip_class < GFX8)
4381       offset = as_vgpr(ctx,get_ssa_temp(ctx, instr->src[2].ssa));
4382    else
4383       offset = get_ssa_temp(ctx, instr->src[2].ssa);
4384
4385    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4386    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4387
4388    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4389                ctx->options->chip_class >= GFX8;
4390    if (smem)
4391       offset = bld.as_uniform(offset);
4392    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4393
4394    while (writemask) {
4395       int start, count;
4396       u_bit_scan_consecutive_range(&writemask, &start, &count);
4397       if (count == 3 && smem) {
4398          writemask |= 1u << (start + 2);
4399          count = 2;
4400       }
4401       int num_bytes = count * elem_size_bytes;
4402
4403       if (num_bytes > 16) {
4404          assert(elem_size_bytes == 8);
4405          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4406          count = 2;
4407          num_bytes = 16;
4408       }
4409
4410       // TODO: check alignment of sub-dword stores
4411       // TODO: split 3 bytes. there is no store instruction for that
4412
4413       Temp write_data;
4414       if (count != instr->num_components) {
4415          emit_split_vector(ctx, data, instr->num_components);
4416          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4417          for (int i = 0; i < count; i++) {
4418             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4419             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4420          }
4421          write_data = bld.tmp(smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4422          vec->definitions[0] = Definition(write_data);
4423          ctx->block->instructions.emplace_back(std::move(vec));
4424       } else if (!smem && data.type() != RegType::vgpr) {
4425          assert(num_bytes % 4 == 0);
4426          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4427       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4428          assert(num_bytes % 4 == 0);
4429          write_data = bld.as_uniform(data);
4430       } else {
4431          write_data = data;
4432       }
4433
4434       aco_opcode vmem_op, smem_op;
4435       switch (num_bytes) {
4436          case 4:
4437             vmem_op = aco_opcode::buffer_store_dword;
4438             smem_op = aco_opcode::s_buffer_store_dword;
4439             break;
4440          case 8:
4441             vmem_op = aco_opcode::buffer_store_dwordx2;
4442             smem_op = aco_opcode::s_buffer_store_dwordx2;
4443             break;
4444          case 12:
4445             vmem_op = aco_opcode::buffer_store_dwordx3;
4446             smem_op = aco_opcode::last_opcode;
4447             assert(!smem);
4448             break;
4449          case 16:
4450             vmem_op = aco_opcode::buffer_store_dwordx4;
4451             smem_op = aco_opcode::s_buffer_store_dwordx4;
4452             break;
4453          default:
4454             unreachable("Store SSBO not implemented for this size.");
4455       }
4456       if (ctx->stage == fragment_fs)
4457          smem_op = aco_opcode::p_fs_buffer_store_smem;
4458
4459       if (smem) {
4460          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4461          store->operands[0] = Operand(rsrc);
4462          if (start) {
4463             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4464                                 offset, Operand(start * elem_size_bytes));
4465             store->operands[1] = Operand(off);
4466          } else {
4467             store->operands[1] = Operand(offset);
4468          }
4469          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4470             store->operands[1].setFixed(m0);
4471          store->operands[2] = Operand(write_data);
4472          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4473          store->dlc = false;
4474          store->disable_wqm = true;
4475          store->barrier = barrier_buffer;
4476          ctx->block->instructions.emplace_back(std::move(store));
4477          ctx->program->wb_smem_l1_on_end = true;
4478          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4479             ctx->block->kind |= block_kind_needs_lowering;
4480             ctx->program->needs_exact = true;
4481          }
4482       } else {
4483          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4484          store->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4485          store->operands[1] = Operand(rsrc);
4486          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4487          store->operands[3] = Operand(write_data);
4488          store->offset = start * elem_size_bytes;
4489          store->offen = (offset.type() == RegType::vgpr);
4490          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4491          store->dlc = false;
4492          store->disable_wqm = true;
4493          store->barrier = barrier_buffer;
4494          ctx->program->needs_exact = true;
4495          ctx->block->instructions.emplace_back(std::move(store));
4496       }
4497    }
4498 }
4499
4500 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4501 {
4502    /* return the previous value if dest is ever used */
4503    bool return_previous = false;
4504    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4505       return_previous = true;
4506       break;
4507    }
4508    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4509       return_previous = true;
4510       break;
4511    }
4512
4513    Builder bld(ctx->program, ctx->block);
4514    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4515
4516    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4517       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4518                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4519
4520    Temp offset;
4521    if (ctx->options->chip_class < GFX8)
4522       offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4523    else
4524       offset = get_ssa_temp(ctx, instr->src[1].ssa);
4525
4526    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4527    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4528
4529    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4530
4531    aco_opcode op32, op64;
4532    switch (instr->intrinsic) {
4533       case nir_intrinsic_ssbo_atomic_add:
4534          op32 = aco_opcode::buffer_atomic_add;
4535          op64 = aco_opcode::buffer_atomic_add_x2;
4536          break;
4537       case nir_intrinsic_ssbo_atomic_imin:
4538          op32 = aco_opcode::buffer_atomic_smin;
4539          op64 = aco_opcode::buffer_atomic_smin_x2;
4540          break;
4541       case nir_intrinsic_ssbo_atomic_umin:
4542          op32 = aco_opcode::buffer_atomic_umin;
4543          op64 = aco_opcode::buffer_atomic_umin_x2;
4544          break;
4545       case nir_intrinsic_ssbo_atomic_imax:
4546          op32 = aco_opcode::buffer_atomic_smax;
4547          op64 = aco_opcode::buffer_atomic_smax_x2;
4548          break;
4549       case nir_intrinsic_ssbo_atomic_umax:
4550          op32 = aco_opcode::buffer_atomic_umax;
4551          op64 = aco_opcode::buffer_atomic_umax_x2;
4552          break;
4553       case nir_intrinsic_ssbo_atomic_and:
4554          op32 = aco_opcode::buffer_atomic_and;
4555          op64 = aco_opcode::buffer_atomic_and_x2;
4556          break;
4557       case nir_intrinsic_ssbo_atomic_or:
4558          op32 = aco_opcode::buffer_atomic_or;
4559          op64 = aco_opcode::buffer_atomic_or_x2;
4560          break;
4561       case nir_intrinsic_ssbo_atomic_xor:
4562          op32 = aco_opcode::buffer_atomic_xor;
4563          op64 = aco_opcode::buffer_atomic_xor_x2;
4564          break;
4565       case nir_intrinsic_ssbo_atomic_exchange:
4566          op32 = aco_opcode::buffer_atomic_swap;
4567          op64 = aco_opcode::buffer_atomic_swap_x2;
4568          break;
4569       case nir_intrinsic_ssbo_atomic_comp_swap:
4570          op32 = aco_opcode::buffer_atomic_cmpswap;
4571          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4572          break;
4573       default:
4574          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4575    }
4576    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4577    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4578    mubuf->operands[0] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4579    mubuf->operands[1] = Operand(rsrc);
4580    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4581    mubuf->operands[3] = Operand(data);
4582    if (return_previous)
4583       mubuf->definitions[0] = Definition(dst);
4584    mubuf->offset = 0;
4585    mubuf->offen = (offset.type() == RegType::vgpr);
4586    mubuf->glc = return_previous;
4587    mubuf->dlc = false; /* Not needed for atomics */
4588    mubuf->disable_wqm = true;
4589    mubuf->barrier = barrier_buffer;
4590    ctx->program->needs_exact = true;
4591    ctx->block->instructions.emplace_back(std::move(mubuf));
4592 }
4593
4594 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4595
4596    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4597    Builder bld(ctx->program, ctx->block);
4598    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4599    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4600 }
4601
4602 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4603 {
4604    Builder bld(ctx->program, ctx->block);
4605    unsigned num_components = instr->num_components;
4606    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4607
4608    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4609    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4610
4611    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4612    bool dlc = glc && ctx->options->chip_class >= GFX10;
4613    aco_opcode op;
4614    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4615       bool global = ctx->options->chip_class >= GFX9;
4616       aco_opcode op;
4617       switch (num_bytes) {
4618       case 4:
4619          op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4620          break;
4621       case 8:
4622          op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4623          break;
4624       case 12:
4625          op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
4626          break;
4627       case 16:
4628          op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
4629          break;
4630       default:
4631          unreachable("load_global not implemented for this size.");
4632       }
4633       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
4634       flat->operands[0] = Operand(addr);
4635       flat->operands[1] = Operand(s1);
4636       flat->glc = glc;
4637       flat->dlc = dlc;
4638
4639       if (dst.type() == RegType::sgpr) {
4640          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4641          flat->definitions[0] = Definition(vec);
4642          ctx->block->instructions.emplace_back(std::move(flat));
4643          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
4644       } else {
4645          flat->definitions[0] = Definition(dst);
4646          ctx->block->instructions.emplace_back(std::move(flat));
4647       }
4648       emit_split_vector(ctx, dst, num_components);
4649    } else {
4650       switch (num_bytes) {
4651          case 4:
4652             op = aco_opcode::s_load_dword;
4653             break;
4654          case 8:
4655             op = aco_opcode::s_load_dwordx2;
4656             break;
4657          case 12:
4658          case 16:
4659             op = aco_opcode::s_load_dwordx4;
4660             break;
4661          default:
4662             unreachable("load_global not implemented for this size.");
4663       }
4664       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4665       load->operands[0] = Operand(addr);
4666       load->operands[1] = Operand(0u);
4667       load->definitions[0] = Definition(dst);
4668       load->glc = glc;
4669       load->dlc = dlc;
4670       load->barrier = barrier_buffer;
4671       assert(ctx->options->chip_class >= GFX8 || !glc);
4672
4673       if (dst.size() == 3) {
4674          /* trim vector */
4675          Temp vec = bld.tmp(s4);
4676          load->definitions[0] = Definition(vec);
4677          ctx->block->instructions.emplace_back(std::move(load));
4678          emit_split_vector(ctx, vec, 4);
4679
4680          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4681                     emit_extract_vector(ctx, vec, 0, s1),
4682                     emit_extract_vector(ctx, vec, 1, s1),
4683                     emit_extract_vector(ctx, vec, 2, s1));
4684       } else {
4685          ctx->block->instructions.emplace_back(std::move(load));
4686       }
4687    }
4688 }
4689
4690 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
4691 {
4692    Builder bld(ctx->program, ctx->block);
4693    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4694
4695    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4696    Temp addr = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4697
4698    unsigned writemask = nir_intrinsic_write_mask(instr);
4699    while (writemask) {
4700       int start, count;
4701       u_bit_scan_consecutive_range(&writemask, &start, &count);
4702       unsigned num_bytes = count * elem_size_bytes;
4703
4704       Temp write_data = data;
4705       if (count != instr->num_components) {
4706          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4707          for (int i = 0; i < count; i++)
4708             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
4709          write_data = bld.tmp(RegType::vgpr, count);
4710          vec->definitions[0] = Definition(write_data);
4711          ctx->block->instructions.emplace_back(std::move(vec));
4712       }
4713
4714       unsigned offset = start * elem_size_bytes;
4715       if (offset > 0 && ctx->options->chip_class < GFX9) {
4716          Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
4717          Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
4718          Temp carry = bld.tmp(s2);
4719          bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
4720
4721          bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
4722                   Operand(offset), addr0);
4723          bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(s2),
4724                   Operand(0u), addr1,
4725                   carry).def(1).setHint(vcc);
4726
4727          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
4728
4729          offset = 0;
4730       }
4731
4732       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4733       bool global = ctx->options->chip_class >= GFX9;
4734       aco_opcode op;
4735       switch (num_bytes) {
4736       case 4:
4737          op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
4738          break;
4739       case 8:
4740          op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
4741          break;
4742       case 12:
4743          op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
4744          break;
4745       case 16:
4746          op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
4747          break;
4748       default:
4749          unreachable("store_global not implemented for this size.");
4750       }
4751       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
4752       flat->operands[0] = Operand(addr);
4753       flat->operands[1] = Operand(s1);
4754       flat->operands[2] = Operand(data);
4755       flat->glc = glc;
4756       flat->dlc = false;
4757       flat->offset = offset;
4758       ctx->block->instructions.emplace_back(std::move(flat));
4759    }
4760 }
4761
4762 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
4763    Builder bld(ctx->program, ctx->block);
4764    switch(instr->intrinsic) {
4765       case nir_intrinsic_group_memory_barrier:
4766       case nir_intrinsic_memory_barrier:
4767          bld.barrier(aco_opcode::p_memory_barrier_all);
4768          break;
4769       case nir_intrinsic_memory_barrier_atomic_counter:
4770          bld.barrier(aco_opcode::p_memory_barrier_atomic);
4771          break;
4772       case nir_intrinsic_memory_barrier_buffer:
4773          bld.barrier(aco_opcode::p_memory_barrier_buffer);
4774          break;
4775       case nir_intrinsic_memory_barrier_image:
4776          bld.barrier(aco_opcode::p_memory_barrier_image);
4777          break;
4778       case nir_intrinsic_memory_barrier_shared:
4779          bld.barrier(aco_opcode::p_memory_barrier_shared);
4780          break;
4781       default:
4782          unreachable("Unimplemented memory barrier intrinsic");
4783          break;
4784    }
4785 }
4786
4787 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4788 {
4789    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4790    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4791    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
4792    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4793    Builder bld(ctx->program, ctx->block);
4794
4795    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
4796    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4797    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
4798 }
4799
4800 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
4801 {
4802    unsigned writemask = nir_intrinsic_write_mask(instr);
4803    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4804    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4805    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4806    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
4807
4808    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
4809    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
4810 }
4811
4812 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4813 {
4814    unsigned offset = nir_intrinsic_base(instr);
4815    Operand m = load_lds_size_m0(ctx);
4816    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4817    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4818
4819    unsigned num_operands = 3;
4820    aco_opcode op32, op64, op32_rtn, op64_rtn;
4821    switch(instr->intrinsic) {
4822       case nir_intrinsic_shared_atomic_add:
4823          op32 = aco_opcode::ds_add_u32;
4824          op64 = aco_opcode::ds_add_u64;
4825          op32_rtn = aco_opcode::ds_add_rtn_u32;
4826          op64_rtn = aco_opcode::ds_add_rtn_u64;
4827          break;
4828       case nir_intrinsic_shared_atomic_imin:
4829          op32 = aco_opcode::ds_min_i32;
4830          op64 = aco_opcode::ds_min_i64;
4831          op32_rtn = aco_opcode::ds_min_rtn_i32;
4832          op64_rtn = aco_opcode::ds_min_rtn_i64;
4833          break;
4834       case nir_intrinsic_shared_atomic_umin:
4835          op32 = aco_opcode::ds_min_u32;
4836          op64 = aco_opcode::ds_min_u64;
4837          op32_rtn = aco_opcode::ds_min_rtn_u32;
4838          op64_rtn = aco_opcode::ds_min_rtn_u64;
4839          break;
4840       case nir_intrinsic_shared_atomic_imax:
4841          op32 = aco_opcode::ds_max_i32;
4842          op64 = aco_opcode::ds_max_i64;
4843          op32_rtn = aco_opcode::ds_max_rtn_i32;
4844          op64_rtn = aco_opcode::ds_max_rtn_i64;
4845          break;
4846       case nir_intrinsic_shared_atomic_umax:
4847          op32 = aco_opcode::ds_max_u32;
4848          op64 = aco_opcode::ds_max_u64;
4849          op32_rtn = aco_opcode::ds_max_rtn_u32;
4850          op64_rtn = aco_opcode::ds_max_rtn_u64;
4851          break;
4852       case nir_intrinsic_shared_atomic_and:
4853          op32 = aco_opcode::ds_and_b32;
4854          op64 = aco_opcode::ds_and_b64;
4855          op32_rtn = aco_opcode::ds_and_rtn_b32;
4856          op64_rtn = aco_opcode::ds_and_rtn_b64;
4857          break;
4858       case nir_intrinsic_shared_atomic_or:
4859          op32 = aco_opcode::ds_or_b32;
4860          op64 = aco_opcode::ds_or_b64;
4861          op32_rtn = aco_opcode::ds_or_rtn_b32;
4862          op64_rtn = aco_opcode::ds_or_rtn_b64;
4863          break;
4864       case nir_intrinsic_shared_atomic_xor:
4865          op32 = aco_opcode::ds_xor_b32;
4866          op64 = aco_opcode::ds_xor_b64;
4867          op32_rtn = aco_opcode::ds_xor_rtn_b32;
4868          op64_rtn = aco_opcode::ds_xor_rtn_b64;
4869          break;
4870       case nir_intrinsic_shared_atomic_exchange:
4871          op32 = aco_opcode::ds_write_b32;
4872          op64 = aco_opcode::ds_write_b64;
4873          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
4874          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
4875          break;
4876       case nir_intrinsic_shared_atomic_comp_swap:
4877          op32 = aco_opcode::ds_cmpst_b32;
4878          op64 = aco_opcode::ds_cmpst_b64;
4879          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
4880          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
4881          num_operands = 4;
4882          break;
4883       default:
4884          unreachable("Unhandled shared atomic intrinsic");
4885    }
4886
4887    /* return the previous value if dest is ever used */
4888    bool return_previous = false;
4889    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4890       return_previous = true;
4891       break;
4892    }
4893    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4894       return_previous = true;
4895       break;
4896    }
4897
4898    aco_opcode op;
4899    if (data.size() == 1) {
4900       assert(instr->dest.ssa.bit_size == 32);
4901       op = return_previous ? op32_rtn : op32;
4902    } else {
4903       assert(instr->dest.ssa.bit_size == 64);
4904       op = return_previous ? op64_rtn : op64;
4905    }
4906
4907    if (offset > 65535) {
4908       Builder bld(ctx->program, ctx->block);
4909       address = bld.vadd32(bld.def(v1), Operand(offset), address);
4910       offset = 0;
4911    }
4912
4913    aco_ptr<DS_instruction> ds;
4914    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
4915    ds->operands[0] = Operand(address);
4916    ds->operands[1] = Operand(data);
4917    if (num_operands == 4)
4918       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
4919    ds->operands[num_operands - 1] = m;
4920    ds->offset0 = offset;
4921    if (return_previous)
4922       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
4923    ctx->block->instructions.emplace_back(std::move(ds));
4924 }
4925
4926 Temp get_scratch_resource(isel_context *ctx)
4927 {
4928    Builder bld(ctx->program, ctx->block);
4929    Temp scratch_addr = ctx->program->private_segment_buffer;
4930    if (ctx->stage != compute_cs)
4931       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
4932
4933    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
4934                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
4935
4936    if (ctx->program->chip_class >= GFX10) {
4937       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4938                    S_008F0C_OOB_SELECT(3) |
4939                    S_008F0C_RESOURCE_LEVEL(1);
4940    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
4941       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4942                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4943    }
4944
4945    /* older generations need element size = 16 bytes. element size removed in GFX9 */
4946    if (ctx->program->chip_class <= GFX8)
4947       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
4948
4949    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
4950 }
4951
4952 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
4953    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
4954    Builder bld(ctx->program, ctx->block);
4955    Temp rsrc = get_scratch_resource(ctx);
4956    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4957    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4958
4959    aco_opcode op;
4960    switch (dst.size()) {
4961       case 1:
4962          op = aco_opcode::buffer_load_dword;
4963          break;
4964       case 2:
4965          op = aco_opcode::buffer_load_dwordx2;
4966          break;
4967       case 3:
4968          op = aco_opcode::buffer_load_dwordx3;
4969          break;
4970       case 4:
4971          op = aco_opcode::buffer_load_dwordx4;
4972          break;
4973       case 6:
4974       case 8: {
4975          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4976          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
4977                                 bld.def(v4), offset, rsrc,
4978                                 ctx->program->scratch_offset, 0, true);
4979          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
4980                                                   aco_opcode::buffer_load_dwordx4,
4981                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
4982                                 offset, rsrc, ctx->program->scratch_offset, 16, true);
4983          emit_split_vector(ctx, lower, 2);
4984          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
4985          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
4986          if (dst.size() == 8) {
4987             emit_split_vector(ctx, upper, 2);
4988             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
4989             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
4990          } else {
4991             elems[2] = upper;
4992          }
4993
4994          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
4995                                                                          Format::PSEUDO, dst.size() / 2, 1)};
4996          for (unsigned i = 0; i < dst.size() / 2; i++)
4997             vec->operands[i] = Operand(elems[i]);
4998          vec->definitions[0] = Definition(dst);
4999          bld.insert(std::move(vec));
5000          ctx->allocated_vec.emplace(dst.id(), elems);
5001          return;
5002       }
5003       default:
5004          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5005    }
5006
5007    bld.mubuf(op, Definition(dst), offset, rsrc, ctx->program->scratch_offset, 0, true);
5008    emit_split_vector(ctx, dst, instr->num_components);
5009 }
5010
5011 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5012    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5013    Builder bld(ctx->program, ctx->block);
5014    Temp rsrc = get_scratch_resource(ctx);
5015    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5016    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5017
5018    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5019    unsigned writemask = nir_intrinsic_write_mask(instr);
5020
5021    while (writemask) {
5022       int start, count;
5023       u_bit_scan_consecutive_range(&writemask, &start, &count);
5024       int num_bytes = count * elem_size_bytes;
5025
5026       if (num_bytes > 16) {
5027          assert(elem_size_bytes == 8);
5028          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5029          count = 2;
5030          num_bytes = 16;
5031       }
5032
5033       // TODO: check alignment of sub-dword stores
5034       // TODO: split 3 bytes. there is no store instruction for that
5035
5036       Temp write_data;
5037       if (count != instr->num_components) {
5038          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5039          for (int i = 0; i < count; i++) {
5040             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5041             vec->operands[i] = Operand(elem);
5042          }
5043          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5044          vec->definitions[0] = Definition(write_data);
5045          ctx->block->instructions.emplace_back(std::move(vec));
5046       } else {
5047          write_data = data;
5048       }
5049
5050       aco_opcode op;
5051       switch (num_bytes) {
5052          case 4:
5053             op = aco_opcode::buffer_store_dword;
5054             break;
5055          case 8:
5056             op = aco_opcode::buffer_store_dwordx2;
5057             break;
5058          case 12:
5059             op = aco_opcode::buffer_store_dwordx3;
5060             break;
5061          case 16:
5062             op = aco_opcode::buffer_store_dwordx4;
5063             break;
5064          default:
5065             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5066       }
5067
5068       bld.mubuf(op, offset, rsrc, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5069    }
5070 }
5071
5072 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5073    uint8_t log2_ps_iter_samples;
5074    if (ctx->program->info->ps.force_persample) {
5075       log2_ps_iter_samples =
5076          util_logbase2(ctx->options->key.fs.num_samples);
5077    } else {
5078       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5079    }
5080
5081    /* The bit pattern matches that used by fixed function fragment
5082     * processing. */
5083    static const unsigned ps_iter_masks[] = {
5084       0xffff, /* not used */
5085       0x5555,
5086       0x1111,
5087       0x0101,
5088       0x0001,
5089    };
5090    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5091
5092    Builder bld(ctx->program, ctx->block);
5093
5094    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), ctx->fs_inputs[fs_input::ancillary], Operand(8u), Operand(4u));
5095    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5096    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5097    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5098    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, ctx->fs_inputs[fs_input::sample_coverage]);
5099 }
5100
5101 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5102 {
5103    Builder bld(ctx->program, ctx->block);
5104
5105    if (cluster_size == 1) {
5106       return src;
5107    } if (op == nir_op_iand && cluster_size == 4) {
5108       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5109       Temp tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src);
5110       return bld.sop1(aco_opcode::s_not_b64, bld.def(s2), bld.def(s1, scc),
5111                       bld.sop1(aco_opcode::s_wqm_b64, bld.def(s2), bld.def(s1, scc), tmp));
5112    } else if (op == nir_op_ior && cluster_size == 4) {
5113       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5114       return bld.sop1(aco_opcode::s_wqm_b64, bld.def(s2), bld.def(s1, scc),
5115                       bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2)));
5116    } else if (op == nir_op_iand && cluster_size == 64) {
5117       //subgroupAnd(val) -> (exec & ~val) == 0
5118       Temp tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src).def(1).getTemp();
5119       return bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), Operand(0u), Operand(-1u), bld.scc(tmp));
5120    } else if (op == nir_op_ior && cluster_size == 64) {
5121       //subgroupOr(val) -> (val & exec) != 0
5122       Temp tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2)).def(1).getTemp();
5123       return bool_to_vector_condition(ctx, tmp);
5124    } else if (op == nir_op_ixor && cluster_size == 64) {
5125       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5126       Temp tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5127       tmp = bld.sop1(aco_opcode::s_bcnt1_i32_b64, bld.def(s2), bld.def(s1, scc), tmp);
5128       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5129       return bool_to_vector_condition(ctx, tmp);
5130    } else {
5131       //subgroupClustered{And,Or,Xor}(val, n) ->
5132       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0))
5133       //cluster_offset = ~(n - 1) & lane_id
5134       //cluster_mask = ((1 << n) - 1)
5135       //subgroupClusteredAnd():
5136       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5137       //subgroupClusteredOr():
5138       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5139       //subgroupClusteredXor():
5140       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5141       Temp lane_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
5142                               bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5143       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5144
5145       Temp tmp;
5146       if (op == nir_op_iand)
5147          tmp = bld.sop2(aco_opcode::s_orn2_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5148       else
5149          tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5150
5151       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5152       tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5153       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5154       if (cluster_mask != 0xffffffff)
5155          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5156
5157       Definition cmp_def = Definition();
5158       if (op == nir_op_iand) {
5159          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2), Operand(cluster_mask), tmp).def(0);
5160       } else if (op == nir_op_ior) {
5161          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp).def(0);
5162       } else if (op == nir_op_ixor) {
5163          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5164                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5165          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp).def(0);
5166       }
5167       cmp_def.setHint(vcc);
5168       return cmp_def.getTemp();
5169    }
5170 }
5171
5172 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5173 {
5174    Builder bld(ctx->program, ctx->block);
5175
5176    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5177    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5178    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5179    Temp tmp;
5180    if (op == nir_op_iand)
5181       tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src);
5182    else
5183       tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5184
5185    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5186    Temp lo = lohi.def(0).getTemp();
5187    Temp hi = lohi.def(1).getTemp();
5188    Temp mbcnt = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), hi,
5189                          bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), lo, Operand(0u)));
5190
5191    Definition cmp_def = Definition();
5192    if (op == nir_op_iand)
5193       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(s2), Operand(0u), mbcnt).def(0);
5194    else if (op == nir_op_ior)
5195       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), mbcnt).def(0);
5196    else if (op == nir_op_ixor)
5197       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u),
5198                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5199    cmp_def.setHint(vcc);
5200    return cmp_def.getTemp();
5201 }
5202
5203 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5204 {
5205    Builder bld(ctx->program, ctx->block);
5206
5207    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5208    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5209    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5210    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5211    if (op == nir_op_iand)
5212       return bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5213    else if (op == nir_op_ior)
5214       return bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5215    else if (op == nir_op_ixor)
5216       return bld.sop2(aco_opcode::s_xor_b64, bld.def(s2), bld.def(s1, scc), tmp, src);
5217
5218    assert(false);
5219    return Temp();
5220 }
5221
5222 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5223 {
5224    Builder bld(ctx->program, ctx->block);
5225    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5226    if (src.regClass().type() == RegType::vgpr) {
5227       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5228    } else if (src.regClass() == s1) {
5229       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5230    } else if (src.regClass() == s2) {
5231       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5232    } else {
5233       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5234       nir_print_instr(&instr->instr, stderr);
5235       fprintf(stderr, "\n");
5236    }
5237 }
5238
5239 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5240 {
5241    Builder bld(ctx->program, ctx->block);
5242    Temp p1 = ctx->fs_inputs[fs_input::persp_center_p1];
5243    Temp p2 = ctx->fs_inputs[fs_input::persp_center_p2];
5244
5245    /* Build DD X/Y */
5246    Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_quad_perm(0, 0, 0, 0));
5247    Temp ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(1, 1, 1, 1));
5248    Temp ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_quad_perm(2, 2, 2, 2));
5249    Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_quad_perm(0, 0, 0, 0));
5250    Temp ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(1, 1, 1, 1));
5251    Temp ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_quad_perm(2, 2, 2, 2));
5252
5253    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5254    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
5255    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
5256    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
5257    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
5258    Temp wqm1 = bld.tmp(v1);
5259    emit_wqm(ctx, tmp1, wqm1, true);
5260    Temp wqm2 = bld.tmp(v1);
5261    emit_wqm(ctx, tmp2, wqm2, true);
5262    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
5263    return;
5264 }
5265
5266 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
5267 {
5268    Builder bld(ctx->program, ctx->block);
5269    switch(instr->intrinsic) {
5270    case nir_intrinsic_load_barycentric_sample:
5271    case nir_intrinsic_load_barycentric_pixel:
5272    case nir_intrinsic_load_barycentric_centroid: {
5273       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
5274       fs_input input = get_interp_input(instr->intrinsic, mode);
5275
5276       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5277       if (input == fs_input::max_inputs) {
5278          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5279                     Operand(0u), Operand(0u));
5280       } else {
5281          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5282                     ctx->fs_inputs[input],
5283                     ctx->fs_inputs[input + 1]);
5284       }
5285       emit_split_vector(ctx, dst, 2);
5286       break;
5287    }
5288    case nir_intrinsic_load_barycentric_at_sample: {
5289       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
5290       switch (ctx->options->key.fs.num_samples) {
5291          case 2: sample_pos_offset += 1 << 3; break;
5292          case 4: sample_pos_offset += 3 << 3; break;
5293          case 8: sample_pos_offset += 7 << 3; break;
5294          default: break;
5295       }
5296       Temp sample_pos;
5297       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5298       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
5299       Temp private_segment_buffer = ctx->program->private_segment_buffer;
5300       if (addr.type() == RegType::sgpr) {
5301          Operand offset;
5302          if (const_addr) {
5303             sample_pos_offset += const_addr->u32 << 3;
5304             offset = Operand(sample_pos_offset);
5305          } else if (ctx->options->chip_class >= GFX9) {
5306             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5307          } else {
5308             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
5309             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
5310          }
5311          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, Operand(offset));
5312
5313       } else if (ctx->options->chip_class >= GFX9) {
5314          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5315          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
5316       } else {
5317          /* addr += private_segment_buffer + sample_pos_offset */
5318          Temp tmp0 = bld.tmp(s1);
5319          Temp tmp1 = bld.tmp(s1);
5320          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
5321          Definition scc_tmp = bld.def(s1, scc);
5322          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
5323          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
5324          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
5325          Temp pck0 = bld.tmp(v1);
5326          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
5327          tmp1 = as_vgpr(ctx, tmp1);
5328          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(s2)), tmp1, Operand(0u), carry);
5329          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
5330
5331          /* sample_pos = flat_load_dwordx2 addr */
5332          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
5333       }
5334
5335       /* sample_pos -= 0.5 */
5336       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
5337       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
5338       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
5339       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
5340       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
5341
5342       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5343       break;
5344    }
5345    case nir_intrinsic_load_barycentric_at_offset: {
5346       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
5347       RegClass rc = RegClass(offset.type(), 1);
5348       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
5349       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
5350       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
5351       break;
5352    }
5353    case nir_intrinsic_load_front_face: {
5354       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5355                Operand(0u), ctx->fs_inputs[fs_input::front_face]).def(0).setHint(vcc);
5356       break;
5357    }
5358    case nir_intrinsic_load_view_index:
5359    case nir_intrinsic_load_layer_id: {
5360       if (instr->intrinsic == nir_intrinsic_load_view_index && (ctx->stage & sw_vs)) {
5361          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5362          bld.copy(Definition(dst), Operand(ctx->view_index));
5363          break;
5364       }
5365
5366       unsigned idx = nir_intrinsic_base(instr);
5367       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5368                  Operand(2u), bld.m0(ctx->prim_mask), idx, 0);
5369       break;
5370    }
5371    case nir_intrinsic_load_frag_coord: {
5372       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
5373       break;
5374    }
5375    case nir_intrinsic_load_sample_pos: {
5376       Temp posx = ctx->fs_inputs[fs_input::frag_pos_0];
5377       Temp posy = ctx->fs_inputs[fs_input::frag_pos_1];
5378       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5379                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
5380                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
5381       break;
5382    }
5383    case nir_intrinsic_load_interpolated_input:
5384       visit_load_interpolated_input(ctx, instr);
5385       break;
5386    case nir_intrinsic_store_output:
5387       visit_store_output(ctx, instr);
5388       break;
5389    case nir_intrinsic_load_input:
5390       visit_load_input(ctx, instr);
5391       break;
5392    case nir_intrinsic_load_ubo:
5393       visit_load_ubo(ctx, instr);
5394       break;
5395    case nir_intrinsic_load_push_constant:
5396       visit_load_push_constant(ctx, instr);
5397       break;
5398    case nir_intrinsic_load_constant:
5399       visit_load_constant(ctx, instr);
5400       break;
5401    case nir_intrinsic_vulkan_resource_index:
5402       visit_load_resource(ctx, instr);
5403       break;
5404    case nir_intrinsic_discard:
5405       visit_discard(ctx, instr);
5406       break;
5407    case nir_intrinsic_discard_if:
5408       visit_discard_if(ctx, instr);
5409       break;
5410    case nir_intrinsic_load_shared:
5411       visit_load_shared(ctx, instr);
5412       break;
5413    case nir_intrinsic_store_shared:
5414       visit_store_shared(ctx, instr);
5415       break;
5416    case nir_intrinsic_shared_atomic_add:
5417    case nir_intrinsic_shared_atomic_imin:
5418    case nir_intrinsic_shared_atomic_umin:
5419    case nir_intrinsic_shared_atomic_imax:
5420    case nir_intrinsic_shared_atomic_umax:
5421    case nir_intrinsic_shared_atomic_and:
5422    case nir_intrinsic_shared_atomic_or:
5423    case nir_intrinsic_shared_atomic_xor:
5424    case nir_intrinsic_shared_atomic_exchange:
5425    case nir_intrinsic_shared_atomic_comp_swap:
5426       visit_shared_atomic(ctx, instr);
5427       break;
5428    case nir_intrinsic_image_deref_load:
5429       visit_image_load(ctx, instr);
5430       break;
5431    case nir_intrinsic_image_deref_store:
5432       visit_image_store(ctx, instr);
5433       break;
5434    case nir_intrinsic_image_deref_atomic_add:
5435    case nir_intrinsic_image_deref_atomic_umin:
5436    case nir_intrinsic_image_deref_atomic_imin:
5437    case nir_intrinsic_image_deref_atomic_umax:
5438    case nir_intrinsic_image_deref_atomic_imax:
5439    case nir_intrinsic_image_deref_atomic_and:
5440    case nir_intrinsic_image_deref_atomic_or:
5441    case nir_intrinsic_image_deref_atomic_xor:
5442    case nir_intrinsic_image_deref_atomic_exchange:
5443    case nir_intrinsic_image_deref_atomic_comp_swap:
5444       visit_image_atomic(ctx, instr);
5445       break;
5446    case nir_intrinsic_image_deref_size:
5447       visit_image_size(ctx, instr);
5448       break;
5449    case nir_intrinsic_load_ssbo:
5450       visit_load_ssbo(ctx, instr);
5451       break;
5452    case nir_intrinsic_store_ssbo:
5453       visit_store_ssbo(ctx, instr);
5454       break;
5455    case nir_intrinsic_load_global:
5456       visit_load_global(ctx, instr);
5457       break;
5458    case nir_intrinsic_store_global:
5459       visit_store_global(ctx, instr);
5460       break;
5461    case nir_intrinsic_ssbo_atomic_add:
5462    case nir_intrinsic_ssbo_atomic_imin:
5463    case nir_intrinsic_ssbo_atomic_umin:
5464    case nir_intrinsic_ssbo_atomic_imax:
5465    case nir_intrinsic_ssbo_atomic_umax:
5466    case nir_intrinsic_ssbo_atomic_and:
5467    case nir_intrinsic_ssbo_atomic_or:
5468    case nir_intrinsic_ssbo_atomic_xor:
5469    case nir_intrinsic_ssbo_atomic_exchange:
5470    case nir_intrinsic_ssbo_atomic_comp_swap:
5471       visit_atomic_ssbo(ctx, instr);
5472       break;
5473    case nir_intrinsic_load_scratch:
5474       visit_load_scratch(ctx, instr);
5475       break;
5476    case nir_intrinsic_store_scratch:
5477       visit_store_scratch(ctx, instr);
5478       break;
5479    case nir_intrinsic_get_buffer_size:
5480       visit_get_buffer_size(ctx, instr);
5481       break;
5482    case nir_intrinsic_barrier: {
5483       unsigned* bsize = ctx->program->info->cs.block_size;
5484       unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
5485       if (workgroup_size > 64)
5486          bld.sopp(aco_opcode::s_barrier);
5487       break;
5488    }
5489    case nir_intrinsic_group_memory_barrier:
5490    case nir_intrinsic_memory_barrier:
5491    case nir_intrinsic_memory_barrier_atomic_counter:
5492    case nir_intrinsic_memory_barrier_buffer:
5493    case nir_intrinsic_memory_barrier_image:
5494    case nir_intrinsic_memory_barrier_shared:
5495       emit_memory_barrier(ctx, instr);
5496       break;
5497    case nir_intrinsic_load_num_work_groups:
5498    case nir_intrinsic_load_work_group_id:
5499    case nir_intrinsic_load_local_invocation_id: {
5500       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5501       Temp* ids;
5502       if (instr->intrinsic == nir_intrinsic_load_num_work_groups)
5503          ids = ctx->num_workgroups;
5504       else if (instr->intrinsic == nir_intrinsic_load_work_group_id)
5505          ids = ctx->workgroup_ids;
5506       else
5507          ids = ctx->local_invocation_ids;
5508       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5509                  ids[0].id() ? Operand(ids[0]) : Operand(1u),
5510                  ids[1].id() ? Operand(ids[1]) : Operand(1u),
5511                  ids[2].id() ? Operand(ids[2]) : Operand(1u));
5512       emit_split_vector(ctx, dst, 3);
5513       break;
5514    }
5515    case nir_intrinsic_load_local_invocation_index: {
5516       Temp id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
5517                          bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5518       Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u), ctx->tg_size);
5519       bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
5520       break;
5521    }
5522    case nir_intrinsic_load_subgroup_id: {
5523       if (ctx->stage == compute_cs) {
5524          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u), ctx->tg_size);
5525          bld.sop2(aco_opcode::s_lshr_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), tg_num, Operand(0x6u));
5526       } else {
5527          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
5528       }
5529       break;
5530    }
5531    case nir_intrinsic_load_subgroup_invocation: {
5532       bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand((uint32_t) -1),
5533                bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
5534       break;
5535    }
5536    case nir_intrinsic_load_num_subgroups: {
5537       if (ctx->stage == compute_cs)
5538          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu), ctx->tg_size);
5539       else
5540          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
5541       break;
5542    }
5543    case nir_intrinsic_ballot: {
5544       Definition tmp = bld.def(s2);
5545       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5546       if (instr->src[0].ssa->bit_size == 1) {
5547          assert(src.regClass() == s2);
5548          bld.sop2(aco_opcode::s_and_b64, tmp, bld.def(s1, scc), Operand(exec, s2), src);
5549       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
5550          bld.vopc(aco_opcode::v_cmp_lg_u32, tmp, Operand(0u), src);
5551       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
5552          bld.vopc(aco_opcode::v_cmp_lg_u64, tmp, Operand(0u), src);
5553       } else {
5554          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5555          nir_print_instr(&instr->instr, stderr);
5556          fprintf(stderr, "\n");
5557       }
5558       emit_wqm(ctx, tmp.getTemp(), get_ssa_temp(ctx, &instr->dest.ssa));
5559       break;
5560    }
5561    case nir_intrinsic_shuffle:
5562    case nir_intrinsic_read_invocation: {
5563       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5564       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
5565          emit_uniform_subgroup(ctx, instr, src);
5566       } else {
5567          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
5568          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
5569             tid = bld.as_uniform(tid);
5570          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5571          if (src.regClass() == v1) {
5572             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
5573          } else if (src.regClass() == v2) {
5574             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5575             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5576             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
5577             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
5578             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5579             emit_split_vector(ctx, dst, 2);
5580          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
5581             assert(src.regClass() == s2);
5582             Temp tmp = bld.sopc(aco_opcode::s_bitcmp1_b64, bld.def(s1, scc), src, tid);
5583             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5584          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
5585             assert(src.regClass() == s2);
5586             Temp tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
5587             tmp = emit_extract_vector(ctx, tmp, 0, v1);
5588             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
5589             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), tmp), dst);
5590          } else {
5591             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5592             nir_print_instr(&instr->instr, stderr);
5593             fprintf(stderr, "\n");
5594          }
5595       }
5596       break;
5597    }
5598    case nir_intrinsic_load_sample_id: {
5599       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
5600                ctx->fs_inputs[ancillary], Operand(8u), Operand(4u));
5601       break;
5602    }
5603    case nir_intrinsic_load_sample_mask_in: {
5604       visit_load_sample_mask_in(ctx, instr);
5605       break;
5606    }
5607    case nir_intrinsic_read_first_invocation: {
5608       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5609       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5610       if (src.regClass() == v1) {
5611          emit_wqm(ctx,
5612                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
5613                   dst);
5614       } else if (src.regClass() == v2) {
5615          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5616          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5617          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
5618          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
5619          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5620          emit_split_vector(ctx, dst, 2);
5621       } else if (instr->dest.ssa.bit_size == 1) {
5622          assert(src.regClass() == s2);
5623          Temp tmp = bld.sopc(aco_opcode::s_bitcmp1_b64, bld.def(s1, scc), src,
5624                              bld.sop1(aco_opcode::s_ff1_i32_b64, bld.def(s1), Operand(exec, s2)));
5625          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
5626       } else if (src.regClass() == s1) {
5627          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
5628       } else if (src.regClass() == s2) {
5629          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
5630       } else {
5631          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5632          nir_print_instr(&instr->instr, stderr);
5633          fprintf(stderr, "\n");
5634       }
5635       break;
5636    }
5637    case nir_intrinsic_vote_all: {
5638       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5639       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5640       assert(src.regClass() == s2);
5641       assert(dst.regClass() == s2);
5642
5643       Temp tmp = bld.sop2(aco_opcode::s_andn2_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src).def(1).getTemp();
5644       Temp val = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), Operand(0u), Operand(-1u), bld.scc(tmp));
5645       emit_wqm(ctx, val, dst);
5646       break;
5647    }
5648    case nir_intrinsic_vote_any: {
5649       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5650       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5651       assert(src.regClass() == s2);
5652       assert(dst.regClass() == s2);
5653
5654       Temp tmp = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), Operand(exec, s2), src).def(1).getTemp();
5655       Temp val = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), Operand(-1u), Operand(0u), bld.scc(tmp));
5656       emit_wqm(ctx, val, dst);
5657       break;
5658    }
5659    case nir_intrinsic_reduce:
5660    case nir_intrinsic_inclusive_scan:
5661    case nir_intrinsic_exclusive_scan: {
5662       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5663       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5664       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
5665       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
5666          nir_intrinsic_cluster_size(instr) : 0;
5667       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : 64, 64));
5668
5669       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
5670          emit_uniform_subgroup(ctx, instr, src);
5671       } else if (instr->dest.ssa.bit_size == 1) {
5672          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
5673             op = nir_op_iand;
5674          else if (op == nir_op_iadd)
5675             op = nir_op_ixor;
5676          else if (op == nir_op_umax || op == nir_op_imax)
5677             op = nir_op_ior;
5678          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
5679
5680          switch (instr->intrinsic) {
5681          case nir_intrinsic_reduce:
5682             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
5683             break;
5684          case nir_intrinsic_exclusive_scan:
5685             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
5686             break;
5687          case nir_intrinsic_inclusive_scan:
5688             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
5689             break;
5690          default:
5691             assert(false);
5692          }
5693       } else if (cluster_size == 1) {
5694          bld.copy(Definition(dst), src);
5695       } else {
5696          src = as_vgpr(ctx, src);
5697
5698          ReduceOp reduce_op;
5699          switch (op) {
5700          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5701             CASE(iadd)
5702             CASE(imul)
5703             CASE(fadd)
5704             CASE(fmul)
5705             CASE(imin)
5706             CASE(umin)
5707             CASE(fmin)
5708             CASE(imax)
5709             CASE(umax)
5710             CASE(fmax)
5711             CASE(iand)
5712             CASE(ior)
5713             CASE(ixor)
5714             default:
5715                unreachable("unknown reduction op");
5716          #undef CASE
5717          }
5718
5719          aco_opcode aco_op;
5720          switch (instr->intrinsic) {
5721             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
5722             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
5723             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
5724             default:
5725                unreachable("unknown reduce intrinsic");
5726          }
5727
5728          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
5729          reduce->operands[0] = Operand(src);
5730          // filled in by aco_reduce_assign.cpp, used internally as part of the
5731          // reduce sequence
5732          assert(dst.size() == 1 || dst.size() == 2);
5733          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
5734          reduce->operands[2] = Operand(v1.as_linear());
5735
5736          Temp tmp_dst = bld.tmp(dst.regClass());
5737          reduce->definitions[0] = Definition(tmp_dst);
5738          reduce->definitions[1] = bld.def(s2); // used internally
5739          reduce->definitions[2] = Definition();
5740          reduce->definitions[3] = Definition(scc, s1);
5741          reduce->definitions[4] = Definition();
5742          reduce->reduce_op = reduce_op;
5743          reduce->cluster_size = cluster_size;
5744          ctx->block->instructions.emplace_back(std::move(reduce));
5745
5746          emit_wqm(ctx, tmp_dst, dst);
5747       }
5748       break;
5749    }
5750    case nir_intrinsic_quad_broadcast: {
5751       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5752       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5753          emit_uniform_subgroup(ctx, instr, src);
5754       } else {
5755          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5756          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
5757          if (instr->dest.ssa.bit_size == 1) {
5758             assert(src.regClass() == s2);
5759             uint32_t half_mask = 0x11111111u << lane;
5760             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
5761             Temp tmp = bld.tmp(s2);
5762             bld.sop1(aco_opcode::s_wqm_b64, Definition(tmp),
5763                      bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), mask_tmp,
5764                               bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2))));
5765             emit_wqm(ctx, tmp, dst);
5766          } else if (instr->dest.ssa.bit_size == 32) {
5767             emit_wqm(ctx,
5768                      bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src,
5769                                   dpp_quad_perm(lane, lane, lane, lane)),
5770                      dst);
5771          } else if (instr->dest.ssa.bit_size == 64) {
5772             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5773             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5774             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_quad_perm(lane, lane, lane, lane)));
5775             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_quad_perm(lane, lane, lane, lane)));
5776             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5777             emit_split_vector(ctx, dst, 2);
5778          } else {
5779             fprintf(stderr, "Unimplemented NIR instr bit size: ");
5780             nir_print_instr(&instr->instr, stderr);
5781             fprintf(stderr, "\n");
5782          }
5783       }
5784       break;
5785    }
5786    case nir_intrinsic_quad_swap_horizontal:
5787    case nir_intrinsic_quad_swap_vertical:
5788    case nir_intrinsic_quad_swap_diagonal:
5789    case nir_intrinsic_quad_swizzle_amd: {
5790       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5791       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5792          emit_uniform_subgroup(ctx, instr, src);
5793          break;
5794       }
5795       uint16_t dpp_ctrl = 0;
5796       switch (instr->intrinsic) {
5797       case nir_intrinsic_quad_swap_horizontal:
5798          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
5799          break;
5800       case nir_intrinsic_quad_swap_vertical:
5801          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
5802          break;
5803       case nir_intrinsic_quad_swap_diagonal:
5804          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
5805          break;
5806       case nir_intrinsic_quad_swizzle_amd: {
5807          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
5808          break;
5809       }
5810       default:
5811          break;
5812       }
5813
5814       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5815       if (instr->dest.ssa.bit_size == 1) {
5816          assert(src.regClass() == s2);
5817          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
5818          src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5819          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(s2), Operand(0u), src);
5820          emit_wqm(ctx, tmp, dst);
5821       } else if (instr->dest.ssa.bit_size == 32) {
5822          Temp tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
5823          emit_wqm(ctx, tmp, dst);
5824       } else if (instr->dest.ssa.bit_size == 64) {
5825          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5826          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5827          lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
5828          hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
5829          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5830          emit_split_vector(ctx, dst, 2);
5831       } else {
5832          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5833          nir_print_instr(&instr->instr, stderr);
5834          fprintf(stderr, "\n");
5835       }
5836       break;
5837    }
5838    case nir_intrinsic_masked_swizzle_amd: {
5839       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5840       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
5841          emit_uniform_subgroup(ctx, instr, src);
5842          break;
5843       }
5844       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5845       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
5846       if (dst.regClass() == v1) {
5847          emit_wqm(ctx,
5848                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
5849                   dst);
5850       } else if (dst.regClass() == v2) {
5851          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
5852          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
5853          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
5854          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
5855          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5856          emit_split_vector(ctx, dst, 2);
5857       } else {
5858          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5859          nir_print_instr(&instr->instr, stderr);
5860          fprintf(stderr, "\n");
5861       }
5862       break;
5863    }
5864    case nir_intrinsic_write_invocation_amd: {
5865       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5866       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
5867       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
5868       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5869       if (dst.regClass() == v1) {
5870          /* src2 is ignored for writelane. RA assigns the same reg for dst */
5871          emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val, lane, src), dst);
5872       } else if (dst.regClass() == v2) {
5873          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
5874          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
5875          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
5876          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
5877          Temp lo = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_lo, lane, src_hi));
5878          Temp hi = emit_wqm(ctx, bld.vop3(aco_opcode::v_writelane_b32, bld.def(v1), val_hi, lane, src_hi));
5879          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
5880          emit_split_vector(ctx, dst, 2);
5881       } else {
5882          fprintf(stderr, "Unimplemented NIR instr bit size: ");
5883          nir_print_instr(&instr->instr, stderr);
5884          fprintf(stderr, "\n");
5885       }
5886       break;
5887    }
5888    case nir_intrinsic_mbcnt_amd: {
5889       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5890       RegClass rc = RegClass(src.type(), 1);
5891       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
5892       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
5893       Temp tmp = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), mask_lo, Operand(0u));
5894       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5895       Temp wqm_tmp = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), mask_hi, tmp);
5896       emit_wqm(ctx, wqm_tmp, dst);
5897       break;
5898    }
5899    case nir_intrinsic_load_helper_invocation: {
5900       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5901       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
5902       ctx->block->kind |= block_kind_needs_lowering;
5903       ctx->program->needs_exact = true;
5904       break;
5905    }
5906    case nir_intrinsic_is_helper_invocation: {
5907       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5908       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
5909       ctx->block->kind |= block_kind_needs_lowering;
5910       ctx->program->needs_exact = true;
5911       break;
5912    }
5913    case nir_intrinsic_demote:
5914       bld.pseudo(aco_opcode::p_demote_to_helper);
5915       ctx->block->kind |= block_kind_uses_demote;
5916       ctx->program->needs_exact = true;
5917       break;
5918    case nir_intrinsic_demote_if: {
5919       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
5920       assert(src.regClass() == s2);
5921       Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.def(s2), bld.def(s1, scc), src, Operand(exec, s2));
5922       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
5923       ctx->block->kind |= block_kind_uses_demote;
5924       ctx->program->needs_exact = true;
5925       break;
5926    }
5927    case nir_intrinsic_first_invocation: {
5928       emit_wqm(ctx, bld.sop1(aco_opcode::s_ff1_i32_b64, bld.def(s1), Operand(exec, s2)),
5929                get_ssa_temp(ctx, &instr->dest.ssa));
5930       break;
5931    }
5932    case nir_intrinsic_shader_clock:
5933       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
5934       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
5935       break;
5936    case nir_intrinsic_load_vertex_id_zero_base: {
5937       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5938       bld.copy(Definition(dst), ctx->vertex_id);
5939       break;
5940    }
5941    case nir_intrinsic_load_first_vertex: {
5942       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5943       bld.copy(Definition(dst), ctx->base_vertex);
5944       break;
5945    }
5946    case nir_intrinsic_load_base_instance: {
5947       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5948       bld.copy(Definition(dst), ctx->start_instance);
5949       break;
5950    }
5951    case nir_intrinsic_load_instance_id: {
5952       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5953       bld.copy(Definition(dst), ctx->instance_id);
5954       break;
5955    }
5956    case nir_intrinsic_load_draw_id: {
5957       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5958       bld.copy(Definition(dst), ctx->draw_id);
5959       break;
5960    }
5961    default:
5962       fprintf(stderr, "Unimplemented intrinsic instr: ");
5963       nir_print_instr(&instr->instr, stderr);
5964       fprintf(stderr, "\n");
5965       abort();
5966
5967       break;
5968    }
5969 }
5970
5971
5972 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
5973                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
5974                     enum glsl_base_type *stype)
5975 {
5976    nir_deref_instr *texture_deref_instr = NULL;
5977    nir_deref_instr *sampler_deref_instr = NULL;
5978    int plane = -1;
5979
5980    for (unsigned i = 0; i < instr->num_srcs; i++) {
5981       switch (instr->src[i].src_type) {
5982       case nir_tex_src_texture_deref:
5983          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
5984          break;
5985       case nir_tex_src_sampler_deref:
5986          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
5987          break;
5988       case nir_tex_src_plane:
5989          plane = nir_src_as_int(instr->src[i].src);
5990          break;
5991       default:
5992          break;
5993       }
5994    }
5995
5996    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
5997
5998    if (!sampler_deref_instr)
5999       sampler_deref_instr = texture_deref_instr;
6000
6001    if (plane >= 0) {
6002       assert(instr->op != nir_texop_txf_ms &&
6003              instr->op != nir_texop_samples_identical);
6004       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6005       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6006    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6007       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6008    } else {
6009       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6010    }
6011    if (samp_ptr) {
6012       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6013       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6014          fprintf(stderr, "Unimplemented sampler descriptor: ");
6015          nir_print_instr(&instr->instr, stderr);
6016          fprintf(stderr, "\n");
6017          abort();
6018          // TODO: build samp_ptr = and(samp_ptr, res_ptr)
6019       }
6020    }
6021    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
6022                      instr->op == nir_texop_samples_identical))
6023       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6024 }
6025
6026 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
6027                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
6028 {
6029    Builder bld(ctx->program, ctx->block);
6030
6031    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
6032    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
6033    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
6034
6035    Operand neg_one(0xbf800000u);
6036    Operand one(0x3f800000u);
6037    Operand two(0x40000000u);
6038    Operand four(0x40800000u);
6039
6040    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), Operand(0u), ma);
6041    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
6042    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
6043
6044    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(s2)), four, id);
6045    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(s2), two, id);
6046    is_ma_y = bld.sop2(aco_opcode::s_andn2_b64, bld.hint_vcc(bld.def(s2)), is_ma_y, is_ma_z);
6047    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), is_ma_z, is_ma_y);
6048
6049    // select sc
6050    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
6051    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
6052                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
6053                        one, is_ma_y);
6054    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6055
6056    // select tc
6057    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
6058    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
6059    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
6060
6061    // select ma
6062    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6063                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
6064                   deriv_z, is_ma_z);
6065    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
6066    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
6067 }
6068
6069 void prepare_cube_coords(isel_context *ctx, Temp* coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
6070 {
6071    Builder bld(ctx->program, ctx->block);
6072    Temp coord_args[4], ma, tc, sc, id;
6073    for (unsigned i = 0; i < (is_array ? 4 : 3); i++)
6074       coord_args[i] = emit_extract_vector(ctx, *coords, i, v1);
6075
6076    if (is_array) {
6077       coord_args[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_args[3]);
6078
6079       // see comment in ac_prepare_cube_coords()
6080       if (ctx->options->chip_class <= GFX8)
6081          coord_args[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coord_args[3]);
6082    }
6083
6084    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6085
6086    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
6087    vop3a->operands[0] = Operand(ma);
6088    vop3a->abs[0] = true;
6089    Temp invma = bld.tmp(v1);
6090    vop3a->definitions[0] = Definition(invma);
6091    ctx->block->instructions.emplace_back(std::move(vop3a));
6092
6093    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6094    if (!is_deriv)
6095       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
6096
6097    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6098    if (!is_deriv)
6099       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
6100
6101    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coord_args[0], coord_args[1], coord_args[2]);
6102
6103    if (is_deriv) {
6104       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
6105       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
6106
6107       for (unsigned i = 0; i < 2; i++) {
6108          // see comment in ac_prepare_cube_coords()
6109          Temp deriv_ma;
6110          Temp deriv_sc, deriv_tc;
6111          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
6112                            &deriv_ma, &deriv_sc, &deriv_tc);
6113
6114          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
6115
6116          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6117                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
6118                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
6119          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
6120                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
6121                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
6122          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
6123       }
6124
6125       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
6126       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
6127    }
6128
6129    if (is_array)
6130       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coord_args[3], id, Operand(0x41000000u/*8.0*/));
6131    *coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), sc, tc, id);
6132
6133 }
6134
6135 Temp apply_round_slice(isel_context *ctx, Temp coords, unsigned idx)
6136 {
6137    Temp coord_vec[3];
6138    for (unsigned i = 0; i < coords.size(); i++)
6139       coord_vec[i] = emit_extract_vector(ctx, coords, i, v1);
6140
6141    Builder bld(ctx->program, ctx->block);
6142    coord_vec[idx] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coord_vec[idx]);
6143
6144    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6145    for (unsigned i = 0; i < coords.size(); i++)
6146       vec->operands[i] = Operand(coord_vec[i]);
6147    Temp res = bld.tmp(RegType::vgpr, coords.size());
6148    vec->definitions[0] = Definition(res);
6149    ctx->block->instructions.emplace_back(std::move(vec));
6150    return res;
6151 }
6152
6153 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
6154 {
6155    if (vec->parent_instr->type != nir_instr_type_alu)
6156       return;
6157    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
6158    if (vec_instr->op != nir_op_vec(vec->num_components))
6159       return;
6160
6161    for (unsigned i = 0; i < vec->num_components; i++) {
6162       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
6163               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
6164    }
6165 }
6166
6167 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
6168 {
6169    Builder bld(ctx->program, ctx->block);
6170    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
6171         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
6172    Temp resource, sampler, fmask_ptr, bias = Temp(), coords, compare = Temp(), sample_index = Temp(),
6173         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp(), derivs = Temp();
6174    nir_const_value *sample_index_cv = NULL;
6175    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
6176    enum glsl_base_type stype;
6177    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
6178
6179    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
6180                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
6181    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
6182                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
6183
6184    for (unsigned i = 0; i < instr->num_srcs; i++) {
6185       switch (instr->src[i].src_type) {
6186       case nir_tex_src_coord:
6187          coords = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[i].src.ssa));
6188          break;
6189       case nir_tex_src_bias:
6190          if (instr->op == nir_texop_txb) {
6191             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
6192             has_bias = true;
6193          }
6194          break;
6195       case nir_tex_src_lod: {
6196          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
6197
6198          if (val && val->f32 <= 0.0) {
6199             level_zero = true;
6200          } else {
6201             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
6202             has_lod = true;
6203          }
6204          break;
6205       }
6206       case nir_tex_src_comparator:
6207          if (instr->is_shadow) {
6208             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
6209             has_compare = true;
6210          }
6211          break;
6212       case nir_tex_src_offset:
6213          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
6214          get_const_vec(instr->src[i].src.ssa, const_offset);
6215          has_offset = true;
6216          break;
6217       case nir_tex_src_ddx:
6218          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
6219          has_ddx = true;
6220          break;
6221       case nir_tex_src_ddy:
6222          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
6223          has_ddy = true;
6224          break;
6225       case nir_tex_src_ms_index:
6226          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
6227          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
6228          has_sample_index = true;
6229          break;
6230       case nir_tex_src_texture_offset:
6231       case nir_tex_src_sampler_offset:
6232       default:
6233          break;
6234       }
6235    }
6236 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6237    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
6238       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
6239
6240    if (instr->op == nir_texop_texture_samples) {
6241       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
6242
6243       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
6244       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
6245       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6246       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
6247
6248       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6249                samples, Operand(1u), bld.scc(is_msaa));
6250       return;
6251    }
6252
6253    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
6254       aco_ptr<Instruction> tmp_instr;
6255       Temp acc, pack = Temp();
6256
6257       uint32_t pack_const = 0;
6258       for (unsigned i = 0; i < offset.size(); i++) {
6259          if (!const_offset[i])
6260             continue;
6261          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
6262       }
6263
6264       if (offset.type() == RegType::sgpr) {
6265          for (unsigned i = 0; i < offset.size(); i++) {
6266             if (const_offset[i])
6267                continue;
6268
6269             acc = emit_extract_vector(ctx, offset, i, s1);
6270             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
6271
6272             if (i) {
6273                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
6274             }
6275
6276             if (pack == Temp()) {
6277                pack = acc;
6278             } else {
6279                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
6280             }
6281          }
6282
6283          if (pack_const && pack != Temp())
6284             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
6285       } else {
6286          for (unsigned i = 0; i < offset.size(); i++) {
6287             if (const_offset[i])
6288                continue;
6289
6290             acc = emit_extract_vector(ctx, offset, i, v1);
6291             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
6292
6293             if (i) {
6294                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
6295             }
6296
6297             if (pack == Temp()) {
6298                pack = acc;
6299             } else {
6300                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
6301             }
6302          }
6303
6304          if (pack_const && pack != Temp())
6305             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
6306       }
6307       if (pack_const && pack == Temp())
6308          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
6309       else if (pack == Temp())
6310          has_offset = false;
6311       else
6312          offset = pack;
6313    }
6314
6315    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
6316       prepare_cube_coords(ctx, &coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
6317
6318    /* pack derivatives */
6319    if (has_ddx || has_ddy) {
6320       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
6321          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(v4),
6322                              ddx, Operand(0u), ddy, Operand(0u));
6323       } else {
6324          derivs = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, ddx.size() + ddy.size()), ddx, ddy);
6325       }
6326       has_derivs = true;
6327    }
6328
6329    if (instr->coord_components > 1 &&
6330        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6331        instr->is_array &&
6332        instr->op != nir_texop_txf)
6333       coords = apply_round_slice(ctx, coords, 1);
6334
6335    if (instr->coord_components > 2 &&
6336       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
6337        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6338        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
6339        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6340        instr->is_array &&
6341        instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms)
6342       coords = apply_round_slice(ctx, coords, 2);
6343
6344    if (ctx->options->chip_class == GFX9 &&
6345        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6346        instr->op != nir_texop_lod && instr->coord_components) {
6347       assert(coords.size() > 0 && coords.size() < 3);
6348
6349       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size() + 1, 1)};
6350       vec->operands[0] = Operand(emit_extract_vector(ctx, coords, 0, v1));
6351       vec->operands[1] = instr->op == nir_texop_txf ? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6352       if (coords.size() > 1)
6353          vec->operands[2] = Operand(emit_extract_vector(ctx, coords, 1, v1));
6354       coords = bld.tmp(RegType::vgpr, coords.size() + 1);
6355       vec->definitions[0] = Definition(coords);
6356       ctx->block->instructions.emplace_back(std::move(vec));
6357    }
6358
6359    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
6360
6361    if (instr->op == nir_texop_samples_identical)
6362       resource = fmask_ptr;
6363
6364    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
6365              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
6366             instr->op != nir_texop_txs) {
6367       assert(has_sample_index);
6368       Operand op(sample_index);
6369       if (sample_index_cv)
6370          op = Operand(sample_index_cv->u32);
6371       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
6372    }
6373
6374    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
6375       Temp split_coords[coords.size()];
6376       emit_split_vector(ctx, coords, coords.size());
6377       for (unsigned i = 0; i < coords.size(); i++)
6378          split_coords[i] = emit_extract_vector(ctx, coords, i, v1);
6379
6380       unsigned i = 0;
6381       for (; i < std::min(offset.size(), instr->coord_components); i++) {
6382          Temp off = emit_extract_vector(ctx, offset, i, v1);
6383          split_coords[i] = bld.vadd32(bld.def(v1), split_coords[i], off);
6384       }
6385
6386       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
6387       for (unsigned i = 0; i < coords.size(); i++)
6388          vec->operands[i] = Operand(split_coords[i]);
6389       coords = bld.tmp(coords.regClass());
6390       vec->definitions[0] = Definition(coords);
6391       ctx->block->instructions.emplace_back(std::move(vec));
6392
6393       has_offset = false;
6394    }
6395
6396    /* Build tex instruction */
6397    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
6398    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
6399                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
6400                   : 0;
6401    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6402    Temp tmp_dst = dst;
6403
6404    /* gather4 selects the component by dmask and always returns vec4 */
6405    if (instr->op == nir_texop_tg4) {
6406       assert(instr->dest.ssa.num_components == 4);
6407       if (instr->is_shadow)
6408          dmask = 1;
6409       else
6410          dmask = 1 << instr->component;
6411       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
6412          tmp_dst = bld.tmp(v4);
6413    } else if (instr->op == nir_texop_samples_identical) {
6414       tmp_dst = bld.tmp(v1);
6415    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
6416       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
6417    }
6418
6419    aco_ptr<MIMG_instruction> tex;
6420    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
6421       if (!has_lod)
6422          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6423
6424       bool div_by_6 = instr->op == nir_texop_txs &&
6425                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
6426                       instr->is_array &&
6427                       (dmask & (1 << 2));
6428       if (tmp_dst.id() == dst.id() && div_by_6)
6429          tmp_dst = bld.tmp(tmp_dst.regClass());
6430
6431       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6432       tex->operands[0] = Operand(as_vgpr(ctx,lod));
6433       tex->operands[1] = Operand(resource);
6434       if (ctx->options->chip_class == GFX9 &&
6435           instr->op == nir_texop_txs &&
6436           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
6437           instr->is_array) {
6438          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
6439       } else if (instr->op == nir_texop_query_levels) {
6440          tex->dmask = 1 << 3;
6441       } else {
6442          tex->dmask = dmask;
6443       }
6444       tex->da = da;
6445       tex->definitions[0] = Definition(tmp_dst);
6446       tex->dim = dim;
6447       tex->can_reorder = true;
6448       ctx->block->instructions.emplace_back(std::move(tex));
6449
6450       if (div_by_6) {
6451          /* divide 3rd value by 6 by multiplying with magic number */
6452          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6453          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
6454          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
6455          assert(instr->dest.ssa.num_components == 3);
6456          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
6457          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6458                               emit_extract_vector(ctx, tmp_dst, 0, v1),
6459                               emit_extract_vector(ctx, tmp_dst, 1, v1),
6460                               by_6);
6461
6462       }
6463
6464       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6465       return;
6466    }
6467
6468    Temp tg4_compare_cube_wa64 = Temp();
6469
6470    if (tg4_integer_workarounds) {
6471       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 2, 1));
6472       tex->operands[0] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
6473       tex->operands[1] = Operand(resource);
6474       tex->dim = dim;
6475       tex->dmask = 0x3;
6476       tex->da = da;
6477       Temp size = bld.tmp(v2);
6478       tex->definitions[0] = Definition(size);
6479       tex->can_reorder = true;
6480       ctx->block->instructions.emplace_back(std::move(tex));
6481       emit_split_vector(ctx, size, size.size());
6482
6483       Temp half_texel[2];
6484       for (unsigned i = 0; i < 2; i++) {
6485          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
6486          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
6487          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
6488          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
6489       }
6490
6491       Temp orig_coords[2] = {
6492          emit_extract_vector(ctx, coords, 0, v1),
6493          emit_extract_vector(ctx, coords, 1, v1)};
6494       Temp new_coords[2] = {
6495          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[0], half_texel[0]),
6496          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), orig_coords[1], half_texel[1])
6497       };
6498
6499       if (tg4_integer_cube_workaround) {
6500          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6501          Temp desc[resource.size()];
6502          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
6503                                                                            Format::PSEUDO, 1, resource.size())};
6504          split->operands[0] = Operand(resource);
6505          for (unsigned i = 0; i < resource.size(); i++) {
6506             desc[i] = bld.tmp(s1);
6507             split->definitions[i] = Definition(desc[i]);
6508          }
6509          ctx->block->instructions.emplace_back(std::move(split));
6510
6511          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
6512          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
6513                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
6514
6515          Temp nfmt;
6516          if (stype == GLSL_TYPE_UINT) {
6517             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6518                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
6519                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
6520                             bld.scc(compare_cube_wa));
6521          } else {
6522             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
6523                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
6524                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
6525                             bld.scc(compare_cube_wa));
6526          }
6527          tg4_compare_cube_wa64 = bld.tmp(s2);
6528          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
6529
6530          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
6531
6532          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
6533                             Operand((uint32_t)C_008F14_NUM_FORMAT));
6534          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
6535
6536          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6537                                                                          Format::PSEUDO, resource.size(), 1)};
6538          for (unsigned i = 0; i < resource.size(); i++)
6539             vec->operands[i] = Operand(desc[i]);
6540          resource = bld.tmp(resource.regClass());
6541          vec->definitions[0] = Definition(resource);
6542          ctx->block->instructions.emplace_back(std::move(vec));
6543
6544          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6545                                   new_coords[0], orig_coords[0], tg4_compare_cube_wa64);
6546          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
6547                                   new_coords[1], orig_coords[1], tg4_compare_cube_wa64);
6548       }
6549
6550       if (coords.size() == 3) {
6551          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v3),
6552                              new_coords[0], new_coords[1],
6553                              emit_extract_vector(ctx, coords, 2, v1));
6554       } else {
6555          assert(coords.size() == 2);
6556          coords = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2),
6557                              new_coords[0], new_coords[1]);
6558       }
6559    }
6560
6561    if (!(has_ddx && has_ddy) && !has_lod && !level_zero &&
6562        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
6563        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
6564       coords = emit_wqm(ctx, coords, bld.tmp(coords.regClass()), true);
6565
6566    std::vector<Operand> args;
6567    if (has_offset)
6568       args.emplace_back(Operand(offset));
6569    if (has_bias)
6570       args.emplace_back(Operand(bias));
6571    if (has_compare)
6572       args.emplace_back(Operand(compare));
6573    if (has_derivs)
6574       args.emplace_back(Operand(derivs));
6575    args.emplace_back(Operand(coords));
6576    if (has_sample_index)
6577       args.emplace_back(Operand(sample_index));
6578    if (has_lod)
6579       args.emplace_back(lod);
6580
6581    Operand arg;
6582    if (args.size() > 1) {
6583       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
6584       unsigned size = 0;
6585       for (unsigned i = 0; i < args.size(); i++) {
6586          size += args[i].size();
6587          vec->operands[i] = args[i];
6588       }
6589       RegClass rc = RegClass(RegType::vgpr, size);
6590       Temp tmp = bld.tmp(rc);
6591       vec->definitions[0] = Definition(tmp);
6592       ctx->block->instructions.emplace_back(std::move(vec));
6593       arg = Operand(tmp);
6594    } else {
6595       assert(args[0].isTemp());
6596       arg = Operand(as_vgpr(ctx, args[0].getTemp()));
6597    }
6598
6599    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
6600       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6601
6602       assert(coords.size() == 1);
6603       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
6604       aco_opcode op;
6605       switch (last_bit) {
6606       case 1:
6607          op = aco_opcode::buffer_load_format_x; break;
6608       case 2:
6609          op = aco_opcode::buffer_load_format_xy; break;
6610       case 3:
6611          op = aco_opcode::buffer_load_format_xyz; break;
6612       case 4:
6613          op = aco_opcode::buffer_load_format_xyzw; break;
6614       default:
6615          unreachable("Tex instruction loads more than 4 components.");
6616       }
6617
6618       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6619       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
6620          tmp_dst = dst;
6621       else
6622          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
6623
6624       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
6625       mubuf->operands[0] = Operand(coords);
6626       mubuf->operands[1] = Operand(resource);
6627       mubuf->operands[2] = Operand((uint32_t) 0);
6628       mubuf->definitions[0] = Definition(tmp_dst);
6629       mubuf->idxen = true;
6630       mubuf->can_reorder = true;
6631       ctx->block->instructions.emplace_back(std::move(mubuf));
6632
6633       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
6634       return;
6635    }
6636
6637
6638    if (instr->op == nir_texop_txf ||
6639        instr->op == nir_texop_txf_ms ||
6640        instr->op == nir_texop_samples_identical) {
6641       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
6642       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 2, 1));
6643       tex->operands[0] = Operand(arg);
6644       tex->operands[1] = Operand(resource);
6645       tex->dim = dim;
6646       tex->dmask = dmask;
6647       tex->unrm = true;
6648       tex->da = da;
6649       tex->definitions[0] = Definition(tmp_dst);
6650       tex->can_reorder = true;
6651       ctx->block->instructions.emplace_back(std::move(tex));
6652
6653       if (instr->op == nir_texop_samples_identical) {
6654          assert(dmask == 1 && dst.regClass() == v1);
6655          assert(dst.id() != tmp_dst.id());
6656
6657          Temp tmp = bld.tmp(s2);
6658          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
6659          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
6660
6661       } else {
6662          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
6663       }
6664       return;
6665    }
6666
6667    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6668    aco_opcode opcode = aco_opcode::image_sample;
6669    if (has_offset) { /* image_sample_*_o */
6670       if (has_compare) {
6671          opcode = aco_opcode::image_sample_c_o;
6672          if (has_derivs)
6673             opcode = aco_opcode::image_sample_c_d_o;
6674          if (has_bias)
6675             opcode = aco_opcode::image_sample_c_b_o;
6676          if (level_zero)
6677             opcode = aco_opcode::image_sample_c_lz_o;
6678          if (has_lod)
6679             opcode = aco_opcode::image_sample_c_l_o;
6680       } else {
6681          opcode = aco_opcode::image_sample_o;
6682          if (has_derivs)
6683             opcode = aco_opcode::image_sample_d_o;
6684          if (has_bias)
6685             opcode = aco_opcode::image_sample_b_o;
6686          if (level_zero)
6687             opcode = aco_opcode::image_sample_lz_o;
6688          if (has_lod)
6689             opcode = aco_opcode::image_sample_l_o;
6690       }
6691    } else { /* no offset */
6692       if (has_compare) {
6693          opcode = aco_opcode::image_sample_c;
6694          if (has_derivs)
6695             opcode = aco_opcode::image_sample_c_d;
6696          if (has_bias)
6697             opcode = aco_opcode::image_sample_c_b;
6698          if (level_zero)
6699             opcode = aco_opcode::image_sample_c_lz;
6700          if (has_lod)
6701             opcode = aco_opcode::image_sample_c_l;
6702       } else {
6703          opcode = aco_opcode::image_sample;
6704          if (has_derivs)
6705             opcode = aco_opcode::image_sample_d;
6706          if (has_bias)
6707             opcode = aco_opcode::image_sample_b;
6708          if (level_zero)
6709             opcode = aco_opcode::image_sample_lz;
6710          if (has_lod)
6711             opcode = aco_opcode::image_sample_l;
6712       }
6713    }
6714
6715    if (instr->op == nir_texop_tg4) {
6716       if (has_offset) {
6717          opcode = aco_opcode::image_gather4_lz_o;
6718          if (has_compare)
6719             opcode = aco_opcode::image_gather4_c_lz_o;
6720       } else {
6721          opcode = aco_opcode::image_gather4_lz;
6722          if (has_compare)
6723             opcode = aco_opcode::image_gather4_c_lz;
6724       }
6725    } else if (instr->op == nir_texop_lod) {
6726       opcode = aco_opcode::image_get_lod;
6727    }
6728
6729    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
6730    tex->operands[0] = arg;
6731    tex->operands[1] = Operand(resource);
6732    tex->operands[2] = Operand(sampler);
6733    tex->dim = dim;
6734    tex->dmask = dmask;
6735    tex->da = da;
6736    tex->definitions[0] = Definition(tmp_dst);
6737    tex->can_reorder = true;
6738    ctx->block->instructions.emplace_back(std::move(tex));
6739
6740    if (tg4_integer_cube_workaround) {
6741       assert(tmp_dst.id() != dst.id());
6742       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
6743
6744       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
6745       Temp val[4];
6746       for (unsigned i = 0; i < dst.size(); i++) {
6747          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
6748          Temp cvt_val;
6749          if (stype == GLSL_TYPE_UINT)
6750             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
6751          else
6752             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
6753          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
6754       }
6755       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
6756       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
6757                            val[0], val[1], val[2], val[3]);
6758    }
6759    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
6760    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
6761
6762 }
6763
6764
6765 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
6766 {
6767    Temp tmp = get_ssa_temp(ctx, ssa);
6768    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
6769       return Operand(tmp.regClass());
6770    else
6771       return Operand(tmp);
6772 }
6773
6774 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
6775 {
6776    aco_ptr<Pseudo_instruction> phi;
6777    unsigned num_src = exec_list_length(&instr->srcs);
6778    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6779    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == s2);
6780
6781    aco_opcode opcode = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index] ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
6782
6783    std::map<unsigned, nir_ssa_def*> phi_src;
6784    bool all_undef = true;
6785    nir_foreach_phi_src(src, instr) {
6786       phi_src[src->pred->index] = src->src.ssa;
6787       if (src->src.ssa->parent_instr->type != nir_instr_type_ssa_undef)
6788          all_undef = false;
6789    }
6790    if (all_undef) {
6791       Builder bld(ctx->program, ctx->block);
6792       if (dst.regClass() == s1) {
6793          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
6794       } else if (dst.regClass() == v1) {
6795          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
6796       } else {
6797          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
6798          for (unsigned i = 0; i < dst.size(); i++)
6799             vec->operands[i] = Operand(0u);
6800          vec->definitions[0] = Definition(dst);
6801          ctx->block->instructions.emplace_back(std::move(vec));
6802       }
6803       return;
6804    }
6805
6806    /* try to scalarize vector phis */
6807    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
6808       // TODO: scalarize linear phis on divergent ifs
6809       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
6810       std::array<Temp, 4> new_vec;
6811       for (std::pair<const unsigned, nir_ssa_def*>& pair : phi_src) {
6812          Operand src = get_phi_operand(ctx, pair.second);
6813          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end()) {
6814             can_scalarize = false;
6815             break;
6816          }
6817       }
6818       if (can_scalarize) {
6819          unsigned num_components = instr->dest.ssa.num_components;
6820          assert(dst.size() % num_components == 0);
6821          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
6822
6823          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
6824          for (unsigned k = 0; k < num_components; k++) {
6825             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_src, 1));
6826             std::map<unsigned, nir_ssa_def*>::iterator it = phi_src.begin();
6827             for (unsigned i = 0; i < num_src; i++) {
6828                Operand src = get_phi_operand(ctx, it->second);
6829                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
6830                ++it;
6831             }
6832             Temp phi_dst = {ctx->program->allocateId(), rc};
6833             phi->definitions[0] = Definition(phi_dst);
6834             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
6835             new_vec[k] = phi_dst;
6836             vec->operands[k] = Operand(phi_dst);
6837          }
6838          vec->definitions[0] = Definition(dst);
6839          ctx->block->instructions.emplace_back(std::move(vec));
6840          ctx->allocated_vec.emplace(dst.id(), new_vec);
6841          return;
6842       }
6843    }
6844
6845    unsigned extra_src = 0;
6846    if (opcode == aco_opcode::p_linear_phi && (ctx->block->kind & block_kind_loop_exit) &&
6847        ctx->program->blocks[ctx->block->index-2].kind & block_kind_continue_or_break) {
6848       extra_src++;
6849    }
6850
6851    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_src + extra_src, 1));
6852
6853    /* if we have a linear phi on a divergent if, we know that one src is undef */
6854    if (opcode == aco_opcode::p_linear_phi && ctx->block->kind & block_kind_merge) {
6855       assert(extra_src == 0);
6856       Block* block;
6857       /* we place the phi either in the invert-block or in the current block */
6858       if (phi_src.begin()->second->parent_instr->type != nir_instr_type_ssa_undef) {
6859          assert((++phi_src.begin())->second->parent_instr->type == nir_instr_type_ssa_undef);
6860          Block& linear_else = ctx->program->blocks[ctx->block->linear_preds[1]];
6861          block = &ctx->program->blocks[linear_else.linear_preds[0]];
6862          assert(block->kind & block_kind_invert);
6863          phi->operands[0] = get_phi_operand(ctx, phi_src.begin()->second);
6864       } else {
6865          assert((++phi_src.begin())->second->parent_instr->type != nir_instr_type_ssa_undef);
6866          block = ctx->block;
6867          phi->operands[0] = get_phi_operand(ctx, (++phi_src.begin())->second);
6868       }
6869       phi->operands[1] = Operand(dst.regClass());
6870       phi->definitions[0] = Definition(dst);
6871       block->instructions.emplace(block->instructions.begin(), std::move(phi));
6872       return;
6873    }
6874
6875    std::map<unsigned, nir_ssa_def*>::iterator it = phi_src.begin();
6876    for (unsigned i = 0; i < num_src; i++) {
6877       phi->operands[i] = get_phi_operand(ctx, it->second);
6878       ++it;
6879    }
6880    for (unsigned i = 0; i < extra_src; i++)
6881       phi->operands[num_src + i] = Operand(dst.regClass());
6882    phi->definitions[0] = Definition(dst);
6883    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
6884 }
6885
6886
6887 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
6888 {
6889    Temp dst = get_ssa_temp(ctx, &instr->def);
6890
6891    assert(dst.type() == RegType::sgpr);
6892
6893    if (dst.size() == 1) {
6894       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
6895    } else {
6896       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
6897       for (unsigned i = 0; i < dst.size(); i++)
6898          vec->operands[i] = Operand(0u);
6899       vec->definitions[0] = Definition(dst);
6900       ctx->block->instructions.emplace_back(std::move(vec));
6901    }
6902 }
6903
6904 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
6905 {
6906    Builder bld(ctx->program, ctx->block);
6907    Block *logical_target;
6908    append_logical_end(ctx->block);
6909    unsigned idx = ctx->block->index;
6910
6911    switch (instr->type) {
6912    case nir_jump_break:
6913       logical_target = ctx->cf_info.parent_loop.exit;
6914       add_logical_edge(idx, logical_target);
6915       ctx->block->kind |= block_kind_break;
6916
6917       if (!ctx->cf_info.parent_if.is_divergent &&
6918           !ctx->cf_info.parent_loop.has_divergent_continue) {
6919          /* uniform break - directly jump out of the loop */
6920          ctx->block->kind |= block_kind_uniform;
6921          ctx->cf_info.has_branch = true;
6922          bld.branch(aco_opcode::p_branch);
6923          add_linear_edge(idx, logical_target);
6924          return;
6925       }
6926       ctx->cf_info.parent_loop.has_divergent_branch = true;
6927       break;
6928    case nir_jump_continue:
6929       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
6930       add_logical_edge(idx, logical_target);
6931       ctx->block->kind |= block_kind_continue;
6932
6933       if (ctx->cf_info.parent_if.is_divergent) {
6934          /* for potential uniform breaks after this continue,
6935             we must ensure that they are handled correctly */
6936          ctx->cf_info.parent_loop.has_divergent_continue = true;
6937          ctx->cf_info.parent_loop.has_divergent_branch = true;
6938       } else {
6939          /* uniform continue - directly jump to the loop header */
6940          ctx->block->kind |= block_kind_uniform;
6941          ctx->cf_info.has_branch = true;
6942          bld.branch(aco_opcode::p_branch);
6943          add_linear_edge(idx, logical_target);
6944          return;
6945       }
6946       break;
6947    default:
6948       fprintf(stderr, "Unknown NIR jump instr: ");
6949       nir_print_instr(&instr->instr, stderr);
6950       fprintf(stderr, "\n");
6951       abort();
6952    }
6953
6954    /* remove critical edges from linear CFG */
6955    bld.branch(aco_opcode::p_branch);
6956    Block* break_block = ctx->program->create_and_insert_block();
6957    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
6958    break_block->kind |= block_kind_uniform;
6959    add_linear_edge(idx, break_block);
6960    /* the loop_header pointer might be invalidated by this point */
6961    if (instr->type == nir_jump_continue)
6962       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
6963    add_linear_edge(break_block->index, logical_target);
6964    bld.reset(break_block);
6965    bld.branch(aco_opcode::p_branch);
6966
6967    Block* continue_block = ctx->program->create_and_insert_block();
6968    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
6969    add_linear_edge(idx, continue_block);
6970    append_logical_start(continue_block);
6971    ctx->block = continue_block;
6972    return;
6973 }
6974
6975 void visit_block(isel_context *ctx, nir_block *block)
6976 {
6977    nir_foreach_instr(instr, block) {
6978       switch (instr->type) {
6979       case nir_instr_type_alu:
6980          visit_alu_instr(ctx, nir_instr_as_alu(instr));
6981          break;
6982       case nir_instr_type_load_const:
6983          visit_load_const(ctx, nir_instr_as_load_const(instr));
6984          break;
6985       case nir_instr_type_intrinsic:
6986          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
6987          break;
6988       case nir_instr_type_tex:
6989          visit_tex(ctx, nir_instr_as_tex(instr));
6990          break;
6991       case nir_instr_type_phi:
6992          visit_phi(ctx, nir_instr_as_phi(instr));
6993          break;
6994       case nir_instr_type_ssa_undef:
6995          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
6996          break;
6997       case nir_instr_type_deref:
6998          break;
6999       case nir_instr_type_jump:
7000          visit_jump(ctx, nir_instr_as_jump(instr));
7001          break;
7002       default:
7003          fprintf(stderr, "Unknown NIR instr type: ");
7004          nir_print_instr(instr, stderr);
7005          fprintf(stderr, "\n");
7006          //abort();
7007       }
7008    }
7009 }
7010
7011
7012
7013 static void visit_loop(isel_context *ctx, nir_loop *loop)
7014 {
7015    append_logical_end(ctx->block);
7016    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7017    Builder bld(ctx->program, ctx->block);
7018    bld.branch(aco_opcode::p_branch);
7019    unsigned loop_preheader_idx = ctx->block->index;
7020
7021    Block loop_exit = Block();
7022    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7023    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
7024
7025    Block* loop_header = ctx->program->create_and_insert_block();
7026    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
7027    loop_header->kind |= block_kind_loop_header;
7028    add_edge(loop_preheader_idx, loop_header);
7029    ctx->block = loop_header;
7030
7031    /* emit loop body */
7032    unsigned loop_header_idx = loop_header->index;
7033    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
7034    append_logical_start(ctx->block);
7035    visit_cf_list(ctx, &loop->body);
7036
7037    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7038    if (!ctx->cf_info.has_branch) {
7039       append_logical_end(ctx->block);
7040       if (ctx->cf_info.exec_potentially_empty) {
7041          /* Discards can result in code running with an empty exec mask.
7042           * This would result in divergent breaks not ever being taken. As a
7043           * workaround, break the loop when the loop mask is empty instead of
7044           * always continuing. */
7045          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
7046          unsigned block_idx = ctx->block->index;
7047
7048          /* create helper blocks to avoid critical edges */
7049          Block *break_block = ctx->program->create_and_insert_block();
7050          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7051          break_block->kind = block_kind_uniform;
7052          bld.reset(break_block);
7053          bld.branch(aco_opcode::p_branch);
7054          add_linear_edge(block_idx, break_block);
7055          add_linear_edge(break_block->index, &loop_exit);
7056
7057          Block *continue_block = ctx->program->create_and_insert_block();
7058          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7059          continue_block->kind = block_kind_uniform;
7060          bld.reset(continue_block);
7061          bld.branch(aco_opcode::p_branch);
7062          add_linear_edge(block_idx, continue_block);
7063          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
7064
7065          add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
7066          ctx->block = &ctx->program->blocks[block_idx];
7067       } else {
7068          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
7069          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7070             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7071          else
7072             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
7073       }
7074
7075       bld.reset(ctx->block);
7076       bld.branch(aco_opcode::p_branch);
7077    }
7078
7079    /* fixup phis in loop header from unreachable blocks */
7080    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
7081       bool linear = ctx->cf_info.has_branch;
7082       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
7083       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
7084          if ((logical && instr->opcode == aco_opcode::p_phi) ||
7085              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
7086             /* the last operand should be the one that needs to be removed */
7087             instr->operands.pop_back();
7088          } else if (!is_phi(instr)) {
7089             break;
7090          }
7091       }
7092    }
7093
7094    ctx->cf_info.has_branch = false;
7095
7096    // TODO: if the loop has not a single exit, we must add one °°
7097    /* emit loop successor block */
7098    ctx->block = ctx->program->insert_block(std::move(loop_exit));
7099    append_logical_start(ctx->block);
7100
7101    #if 0
7102    // TODO: check if it is beneficial to not branch on continues
7103    /* trim linear phis in loop header */
7104    for (auto&& instr : loop_entry->instructions) {
7105       if (instr->opcode == aco_opcode::p_linear_phi) {
7106          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
7107          new_phi->definitions[0] = instr->definitions[0];
7108          for (unsigned i = 0; i < new_phi->operands.size(); i++)
7109             new_phi->operands[i] = instr->operands[i];
7110          /* check that the remaining operands are all the same */
7111          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
7112             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
7113          instr.swap(new_phi);
7114       } else if (instr->opcode == aco_opcode::p_phi) {
7115          continue;
7116       } else {
7117          break;
7118       }
7119    }
7120    #endif
7121 }
7122
7123 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
7124 {
7125    ic->cond = cond;
7126
7127    append_logical_end(ctx->block);
7128    ctx->block->kind |= block_kind_branch;
7129
7130    /* branch to linear then block */
7131    assert(cond.regClass() == s2);
7132    aco_ptr<Pseudo_branch_instruction> branch;
7133    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7134    branch->operands[0] = Operand(cond);
7135    ctx->block->instructions.push_back(std::move(branch));
7136
7137    ic->BB_if_idx = ctx->block->index;
7138    ic->BB_invert = Block();
7139    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7140    /* Invert blocks are intentionally not marked as top level because they
7141     * are not part of the logical cfg. */
7142    ic->BB_invert.kind |= block_kind_invert;
7143    ic->BB_endif = Block();
7144    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7145    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
7146
7147    ic->exec_potentially_empty_old = ctx->cf_info.exec_potentially_empty;
7148    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
7149    ctx->cf_info.parent_if.is_divergent = true;
7150    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7151
7152    /** emit logical then block */
7153    Block* BB_then_logical = ctx->program->create_and_insert_block();
7154    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7155    add_edge(ic->BB_if_idx, BB_then_logical);
7156    ctx->block = BB_then_logical;
7157    append_logical_start(BB_then_logical);
7158 }
7159
7160 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
7161 {
7162    Block *BB_then_logical = ctx->block;
7163    append_logical_end(BB_then_logical);
7164     /* branch from logical then block to invert block */
7165    aco_ptr<Pseudo_branch_instruction> branch;
7166    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7167    BB_then_logical->instructions.emplace_back(std::move(branch));
7168    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
7169    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7170       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
7171    BB_then_logical->kind |= block_kind_uniform;
7172    assert(!ctx->cf_info.has_branch);
7173    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7174    ctx->cf_info.parent_loop.has_divergent_branch = false;
7175
7176    /** emit linear then block */
7177    Block* BB_then_linear = ctx->program->create_and_insert_block();
7178    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7179    BB_then_linear->kind |= block_kind_uniform;
7180    add_linear_edge(ic->BB_if_idx, BB_then_linear);
7181    /* branch from linear then block to invert block */
7182    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7183    BB_then_linear->instructions.emplace_back(std::move(branch));
7184    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
7185
7186    /** emit invert merge block */
7187    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
7188    ic->invert_idx = ctx->block->index;
7189
7190    /* branch to linear else block (skip else) */
7191    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
7192    branch->operands[0] = Operand(ic->cond);
7193    ctx->block->instructions.push_back(std::move(branch));
7194
7195    ic->exec_potentially_empty_old |= ctx->cf_info.exec_potentially_empty;
7196    ctx->cf_info.exec_potentially_empty = false; /* divergent branches use cbranch_execz */
7197
7198    /** emit logical else block */
7199    Block* BB_else_logical = ctx->program->create_and_insert_block();
7200    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7201    add_logical_edge(ic->BB_if_idx, BB_else_logical);
7202    add_linear_edge(ic->invert_idx, BB_else_logical);
7203    ctx->block = BB_else_logical;
7204    append_logical_start(BB_else_logical);
7205 }
7206
7207 static void end_divergent_if(isel_context *ctx, if_context *ic)
7208 {
7209    Block *BB_else_logical = ctx->block;
7210    append_logical_end(BB_else_logical);
7211
7212    /* branch from logical else block to endif block */
7213    aco_ptr<Pseudo_branch_instruction> branch;
7214    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7215    BB_else_logical->instructions.emplace_back(std::move(branch));
7216    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
7217    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7218       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
7219    BB_else_logical->kind |= block_kind_uniform;
7220
7221    assert(!ctx->cf_info.has_branch);
7222    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
7223
7224
7225    /** emit linear else block */
7226    Block* BB_else_linear = ctx->program->create_and_insert_block();
7227    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7228    BB_else_linear->kind |= block_kind_uniform;
7229    add_linear_edge(ic->invert_idx, BB_else_linear);
7230
7231    /* branch from linear else block to endif block */
7232    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7233    BB_else_linear->instructions.emplace_back(std::move(branch));
7234    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
7235
7236
7237    /** emit endif merge block */
7238    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
7239    append_logical_start(ctx->block);
7240
7241
7242    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
7243    ctx->cf_info.exec_potentially_empty |= ic->exec_potentially_empty_old;
7244    /* uniform control flow never has an empty exec-mask */
7245    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
7246       ctx->cf_info.exec_potentially_empty = false;
7247 }
7248
7249 static void visit_if(isel_context *ctx, nir_if *if_stmt)
7250 {
7251    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
7252    Builder bld(ctx->program, ctx->block);
7253    aco_ptr<Pseudo_branch_instruction> branch;
7254
7255    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
7256       /**
7257        * Uniform conditionals are represented in the following way*) :
7258        *
7259        * The linear and logical CFG:
7260        *                        BB_IF
7261        *                        /    \
7262        *       BB_THEN (logical)      BB_ELSE (logical)
7263        *                        \    /
7264        *                        BB_ENDIF
7265        *
7266        * *) Exceptions may be due to break and continue statements within loops
7267        *    If a break/continue happens within uniform control flow, it branches
7268        *    to the loop exit/entry block. Otherwise, it branches to the next
7269        *    merge block.
7270        **/
7271       append_logical_end(ctx->block);
7272       ctx->block->kind |= block_kind_uniform;
7273
7274       /* emit branch */
7275       assert(cond.regClass() == s2);
7276       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7277       cond = bool_to_scalar_condition(ctx, cond);
7278
7279       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
7280       branch->operands[0] = Operand(cond);
7281       branch->operands[0].setFixed(scc);
7282       ctx->block->instructions.emplace_back(std::move(branch));
7283
7284       unsigned BB_if_idx = ctx->block->index;
7285       Block BB_endif = Block();
7286       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
7287       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
7288
7289       /** emit then block */
7290       Block* BB_then = ctx->program->create_and_insert_block();
7291       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7292       add_edge(BB_if_idx, BB_then);
7293       append_logical_start(BB_then);
7294       ctx->block = BB_then;
7295       visit_cf_list(ctx, &if_stmt->then_list);
7296       BB_then = ctx->block;
7297       bool then_branch = ctx->cf_info.has_branch;
7298       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
7299
7300       if (!then_branch) {
7301          append_logical_end(BB_then);
7302          /* branch from then block to endif block */
7303          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7304          BB_then->instructions.emplace_back(std::move(branch));
7305          add_linear_edge(BB_then->index, &BB_endif);
7306          if (!then_branch_divergent)
7307             add_logical_edge(BB_then->index, &BB_endif);
7308          BB_then->kind |= block_kind_uniform;
7309       }
7310
7311       ctx->cf_info.has_branch = false;
7312       ctx->cf_info.parent_loop.has_divergent_branch = false;
7313
7314       /** emit else block */
7315       Block* BB_else = ctx->program->create_and_insert_block();
7316       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7317       add_edge(BB_if_idx, BB_else);
7318       append_logical_start(BB_else);
7319       ctx->block = BB_else;
7320       visit_cf_list(ctx, &if_stmt->else_list);
7321       BB_else = ctx->block;
7322
7323       if (!ctx->cf_info.has_branch) {
7324          append_logical_end(BB_else);
7325          /* branch from then block to endif block */
7326          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
7327          BB_else->instructions.emplace_back(std::move(branch));
7328          add_linear_edge(BB_else->index, &BB_endif);
7329          if (!ctx->cf_info.parent_loop.has_divergent_branch)
7330             add_logical_edge(BB_else->index, &BB_endif);
7331          BB_else->kind |= block_kind_uniform;
7332       }
7333
7334       ctx->cf_info.has_branch &= then_branch;
7335       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
7336
7337       /** emit endif merge block */
7338       if (!ctx->cf_info.has_branch) {
7339          ctx->block = ctx->program->insert_block(std::move(BB_endif));
7340          append_logical_start(ctx->block);
7341       }
7342    } else { /* non-uniform condition */
7343       /**
7344        * To maintain a logical and linear CFG without critical edges,
7345        * non-uniform conditionals are represented in the following way*) :
7346        *
7347        * The linear CFG:
7348        *                        BB_IF
7349        *                        /    \
7350        *       BB_THEN (logical)      BB_THEN (linear)
7351        *                        \    /
7352        *                        BB_INVERT (linear)
7353        *                        /    \
7354        *       BB_ELSE (logical)      BB_ELSE (linear)
7355        *                        \    /
7356        *                        BB_ENDIF
7357        *
7358        * The logical CFG:
7359        *                        BB_IF
7360        *                        /    \
7361        *       BB_THEN (logical)      BB_ELSE (logical)
7362        *                        \    /
7363        *                        BB_ENDIF
7364        *
7365        * *) Exceptions may be due to break and continue statements within loops
7366        **/
7367
7368       if_context ic;
7369
7370       begin_divergent_if_then(ctx, &ic, cond);
7371       visit_cf_list(ctx, &if_stmt->then_list);
7372
7373       begin_divergent_if_else(ctx, &ic);
7374       visit_cf_list(ctx, &if_stmt->else_list);
7375
7376       end_divergent_if(ctx, &ic);
7377    }
7378 }
7379
7380 static void visit_cf_list(isel_context *ctx,
7381                           struct exec_list *list)
7382 {
7383    foreach_list_typed(nir_cf_node, node, node, list) {
7384       switch (node->type) {
7385       case nir_cf_node_block:
7386          visit_block(ctx, nir_cf_node_as_block(node));
7387          break;
7388       case nir_cf_node_if:
7389          visit_if(ctx, nir_cf_node_as_if(node));
7390          break;
7391       case nir_cf_node_loop:
7392          visit_loop(ctx, nir_cf_node_as_loop(node));
7393          break;
7394       default:
7395          unreachable("unimplemented cf list type");
7396       }
7397    }
7398 }
7399
7400 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
7401 {
7402    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
7403    uint64_t mask = ctx->vs_output.mask[slot];
7404    if (!is_pos && !mask)
7405       return;
7406    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
7407       return;
7408    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7409    exp->enabled_mask = mask;
7410    for (unsigned i = 0; i < 4; ++i) {
7411       if (mask & (1 << i))
7412          exp->operands[i] = Operand(ctx->vs_output.outputs[slot][i]);
7413       else
7414          exp->operands[i] = Operand(v1);
7415    }
7416    exp->valid_mask = false;
7417    exp->done = false;
7418    exp->compressed = false;
7419    if (is_pos)
7420       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7421    else
7422       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
7423    ctx->block->instructions.emplace_back(std::move(exp));
7424 }
7425
7426 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
7427 {
7428    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
7429    exp->enabled_mask = 0;
7430    for (unsigned i = 0; i < 4; ++i)
7431       exp->operands[i] = Operand(v1);
7432    if (ctx->vs_output.mask[VARYING_SLOT_PSIZ]) {
7433       exp->operands[0] = Operand(ctx->vs_output.outputs[VARYING_SLOT_PSIZ][0]);
7434       exp->enabled_mask |= 0x1;
7435    }
7436    if (ctx->vs_output.mask[VARYING_SLOT_LAYER]) {
7437       exp->operands[2] = Operand(ctx->vs_output.outputs[VARYING_SLOT_LAYER][0]);
7438       exp->enabled_mask |= 0x4;
7439    }
7440    if (ctx->vs_output.mask[VARYING_SLOT_VIEWPORT]) {
7441       if (ctx->options->chip_class < GFX9) {
7442          exp->operands[3] = Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]);
7443          exp->enabled_mask |= 0x8;
7444       } else {
7445          Builder bld(ctx->program, ctx->block);
7446
7447          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
7448                              Operand(ctx->vs_output.outputs[VARYING_SLOT_VIEWPORT][0]));
7449          if (exp->operands[2].isTemp())
7450             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
7451
7452          exp->operands[2] = Operand(out);
7453          exp->enabled_mask |= 0x4;
7454       }
7455    }
7456    exp->valid_mask = false;
7457    exp->done = false;
7458    exp->compressed = false;
7459    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
7460    ctx->block->instructions.emplace_back(std::move(exp));
7461 }
7462
7463 static void create_vs_exports(isel_context *ctx)
7464 {
7465    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
7466
7467    if (outinfo->export_prim_id) {
7468       ctx->vs_output.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
7469       ctx->vs_output.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = ctx->vs_prim_id;
7470    }
7471
7472    if (ctx->options->key.has_multiview_view_index) {
7473       ctx->vs_output.mask[VARYING_SLOT_LAYER] |= 0x1;
7474       ctx->vs_output.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, ctx->view_index);
7475    }
7476
7477    /* the order these position exports are created is important */
7478    int next_pos = 0;
7479    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
7480    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
7481       export_vs_psiz_layer_viewport(ctx, &next_pos);
7482    }
7483    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7484       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
7485    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7486       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
7487
7488    if (ctx->options->key.vs_common_out.export_clip_dists) {
7489       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
7490          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
7491       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
7492          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
7493    }
7494
7495    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
7496       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
7497           i != VARYING_SLOT_PRIMITIVE_ID)
7498          continue;
7499
7500       export_vs_varying(ctx, i, false, NULL);
7501    }
7502 }
7503
7504 static void emit_stream_output(isel_context *ctx,
7505                                Temp const *so_buffers,
7506                                Temp const *so_write_offset,
7507                                const struct radv_stream_output *output)
7508 {
7509    unsigned num_comps = util_bitcount(output->component_mask);
7510    unsigned loc = output->location;
7511    unsigned buf = output->buffer;
7512    unsigned offset = output->offset;
7513
7514    assert(num_comps && num_comps <= 4);
7515    if (!num_comps || num_comps > 4)
7516       return;
7517
7518    unsigned start = ffs(output->component_mask) - 1;
7519
7520    Temp out[4];
7521    bool all_undef = true;
7522    assert(ctx->stage == vertex_vs);
7523    for (unsigned i = 0; i < num_comps; i++) {
7524       out[i] = ctx->vs_output.outputs[loc][start + i];
7525       all_undef = all_undef && !out[i].id();
7526    }
7527    if (all_undef)
7528       return;
7529
7530    Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_comps)};
7531    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_comps, 1)};
7532    for (unsigned i = 0; i < num_comps; ++i)
7533       vec->operands[i] = (ctx->vs_output.mask[loc] & 1 << i) ? Operand(out[i]) : Operand(0u);
7534    vec->definitions[0] = Definition(write_data);
7535    ctx->block->instructions.emplace_back(std::move(vec));
7536
7537    aco_opcode opcode;
7538    switch (num_comps) {
7539    case 1:
7540       opcode = aco_opcode::buffer_store_dword;
7541       break;
7542    case 2:
7543       opcode = aco_opcode::buffer_store_dwordx2;
7544       break;
7545    case 3:
7546       opcode = aco_opcode::buffer_store_dwordx3;
7547       break;
7548    case 4:
7549       opcode = aco_opcode::buffer_store_dwordx4;
7550       break;
7551    }
7552
7553    aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
7554    store->operands[0] = Operand(so_write_offset[buf]);
7555    store->operands[1] = Operand(so_buffers[buf]);
7556    store->operands[2] = Operand((uint32_t) 0);
7557    store->operands[3] = Operand(write_data);
7558    if (offset > 4095) {
7559       /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7560       Builder bld(ctx->program, ctx->block);
7561       store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
7562    } else {
7563       store->offset = offset;
7564    }
7565    store->offen = true;
7566    store->glc = true;
7567    store->dlc = false;
7568    store->slc = true;
7569    store->can_reorder = true;
7570    ctx->block->instructions.emplace_back(std::move(store));
7571 }
7572
7573 static void emit_streamout(isel_context *ctx, unsigned stream)
7574 {
7575    Builder bld(ctx->program, ctx->block);
7576
7577    Temp so_buffers[4];
7578    Temp buf_ptr = convert_pointer_to_64_bit(ctx, ctx->streamout_buffers);
7579    for (unsigned i = 0; i < 4; i++) {
7580       unsigned stride = ctx->program->info->so.strides[i];
7581       if (!stride)
7582          continue;
7583
7584       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, Operand(i * 16u));
7585    }
7586
7587    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
7588                                 ctx->streamout_config, Operand(0x70010u));
7589
7590    Temp tid = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
7591                        bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
7592
7593    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(s2), so_vtx_count, tid);
7594
7595    if_context ic;
7596    begin_divergent_if_then(ctx, &ic, can_emit);
7597
7598    bld.reset(ctx->block);
7599
7600    Temp so_write_index = bld.vadd32(bld.def(v1), ctx->streamout_write_idx, tid);
7601
7602    Temp so_write_offset[4];
7603
7604    for (unsigned i = 0; i < 4; i++) {
7605       unsigned stride = ctx->program->info->so.strides[i];
7606       if (!stride)
7607          continue;
7608
7609       if (stride == 1) {
7610          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
7611                                 ctx->streamout_write_idx, ctx->streamout_offset[i]);
7612          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
7613
7614          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
7615       } else {
7616          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
7617          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u), ctx->streamout_offset[i]);
7618          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
7619       }
7620    }
7621
7622    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
7623       struct radv_stream_output *output =
7624          &ctx->program->info->so.outputs[i];
7625       if (stream != output->stream)
7626          continue;
7627
7628       emit_stream_output(ctx, so_buffers, so_write_offset, output);
7629    }
7630
7631    begin_divergent_if_else(ctx, &ic);
7632    end_divergent_if(ctx, &ic);
7633 }
7634
7635 } /* end namespace */
7636
7637 void handle_bc_optimize(isel_context *ctx)
7638 {
7639    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7640    Builder bld(ctx->program, ctx->block);
7641    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
7642    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
7643    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
7644    if (uses_center && uses_centroid) {
7645       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(s2)), ctx->prim_mask, Operand(0u));
7646
7647       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
7648          for (unsigned i = 0; i < 2; i++) {
7649             Temp new_coord = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7650                                       ctx->fs_inputs[fs_input::persp_centroid_p1 + i],
7651                                       ctx->fs_inputs[fs_input::persp_center_p1 + i],
7652                                       sel);
7653             ctx->fs_inputs[fs_input::persp_centroid_p1 + i] = new_coord;
7654          }
7655       }
7656
7657       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
7658          for (unsigned i = 0; i < 2; i++) {
7659             Temp new_coord = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7660                                       ctx->fs_inputs[fs_input::linear_centroid_p1 + i],
7661                                       ctx->fs_inputs[fs_input::linear_center_p1 + i],
7662                                       sel);
7663             ctx->fs_inputs[fs_input::linear_centroid_p1 + i] = new_coord;
7664          }
7665       }
7666    }
7667 }
7668
7669 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
7670 {
7671    Program *program = ctx->program;
7672
7673    unsigned float_controls = shader->info.float_controls_execution_mode;
7674
7675    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
7676       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
7677    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
7678       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
7679                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
7680
7681    program->next_fp_mode.must_flush_denorms32 =
7682       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
7683    program->next_fp_mode.must_flush_denorms16_64 =
7684       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
7685                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
7686
7687    program->next_fp_mode.care_about_round32 =
7688       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
7689
7690    program->next_fp_mode.care_about_round16_64 =
7691       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
7692                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
7693
7694    /* default to preserving fp16 and fp64 denorms, since it's free */
7695    if (program->next_fp_mode.must_flush_denorms16_64)
7696       program->next_fp_mode.denorm16_64 = 0;
7697    else
7698       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
7699
7700    /* preserving fp32 denorms is expensive, so only do it if asked */
7701    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
7702       program->next_fp_mode.denorm32 = fp_denorm_keep;
7703    else
7704       program->next_fp_mode.denorm32 = 0;
7705
7706    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
7707       program->next_fp_mode.round32 = fp_round_tz;
7708    else
7709       program->next_fp_mode.round32 = fp_round_ne;
7710
7711    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
7712       program->next_fp_mode.round16_64 = fp_round_tz;
7713    else
7714       program->next_fp_mode.round16_64 = fp_round_ne;
7715
7716    ctx->block->fp_mode = program->next_fp_mode;
7717 }
7718
7719 void select_program(Program *program,
7720                     unsigned shader_count,
7721                     struct nir_shader *const *shaders,
7722                     ac_shader_config* config,
7723                     struct radv_shader_info *info,
7724                     const struct radv_nir_compiler_options *options)
7725 {
7726    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, info, options);
7727
7728    for (unsigned i = 0; i < shader_count; i++) {
7729       nir_shader *nir = shaders[i];
7730       init_context(&ctx, nir);
7731
7732       setup_fp_mode(&ctx, nir);
7733
7734       if (!i) {
7735          add_startpgm(&ctx); /* needs to be after init_context() for FS */
7736          append_logical_start(ctx.block);
7737       }
7738
7739       if_context ic;
7740       if (shader_count >= 2) {
7741          Builder bld(ctx.program, ctx.block);
7742          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), ctx.merged_wave_info, Operand((8u << 16) | (i * 8u)));
7743          Temp thread_id = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, bld.def(v1), Operand((uint32_t) -1),
7744                                    bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, bld.def(v1), Operand((uint32_t) -1), Operand(0u)));
7745          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(s2)), count, thread_id);
7746
7747          begin_divergent_if_then(&ctx, &ic, cond);
7748       }
7749
7750       if (i) {
7751          Builder bld(ctx.program, ctx.block);
7752          bld.barrier(aco_opcode::p_memory_barrier_shared); //TODO: different barriers are needed for different stages
7753          bld.sopp(aco_opcode::s_barrier);
7754       }
7755
7756       if (ctx.stage == fragment_fs)
7757          handle_bc_optimize(&ctx);
7758
7759       nir_function_impl *func = nir_shader_get_entrypoint(nir);
7760       visit_cf_list(&ctx, &func->body);
7761
7762       if (ctx.program->info->so.num_outputs/*&& !ctx->is_gs_copy_shader */)
7763          emit_streamout(&ctx, 0);
7764
7765       if (ctx.stage == vertex_vs)
7766          create_vs_exports(&ctx);
7767
7768       if (shader_count >= 2) {
7769          begin_divergent_if_else(&ctx, &ic);
7770          end_divergent_if(&ctx, &ic);
7771       }
7772
7773       ralloc_free(ctx.divergent_vals);
7774    }
7775
7776    program->config->float_mode = program->blocks[0].fp_mode.val;
7777
7778    append_logical_end(ctx.block);
7779    ctx.block->kind |= block_kind_uniform;
7780    Builder bld(ctx.program, ctx.block);
7781    if (ctx.program->wb_smem_l1_on_end)
7782       bld.smem(aco_opcode::s_dcache_wb, false);
7783    bld.sopp(aco_opcode::s_endpgm);
7784
7785    /* cleanup CFG */
7786    for (Block& BB : program->blocks) {
7787       for (unsigned idx : BB.linear_preds)
7788          program->blocks[idx].linear_succs.emplace_back(BB.index);
7789       for (unsigned idx : BB.logical_preds)
7790          program->blocks[idx].logical_succs.emplace_back(BB.index);
7791    }
7792 }
7793 }