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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
594 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
595 if (src1
.type() == RegType::sgpr
) {
596 if (commutative
&& src0
.type() == RegType::vgpr
) {
601 src1
= as_vgpr(ctx
, src1
);
605 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
606 assert(dst
.size() == 1);
607 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
608 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
610 bld
.vop2(op
, Definition(dst
), src0
, src1
);
614 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
615 bool flush_denorms
= false)
617 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
618 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
619 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
621 /* ensure that the instruction has at most 1 sgpr operand
622 * The optimizer will inline constants for us */
623 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
624 src0
= as_vgpr(ctx
, src0
);
625 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
626 src1
= as_vgpr(ctx
, src1
);
627 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
628 src2
= as_vgpr(ctx
, src2
);
630 Builder
bld(ctx
->program
, ctx
->block
);
631 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
632 assert(dst
.size() == 1);
633 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
634 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
636 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
640 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
642 Builder
bld(ctx
->program
, ctx
->block
);
643 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
646 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
648 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
649 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
650 assert(src0
.size() == src1
.size());
652 aco_ptr
<Instruction
> vopc
;
653 if (src1
.type() == RegType::sgpr
) {
654 if (src0
.type() == RegType::vgpr
) {
655 /* to swap the operands, we might also have to change the opcode */
657 case aco_opcode::v_cmp_lt_f16
:
658 op
= aco_opcode::v_cmp_gt_f16
;
660 case aco_opcode::v_cmp_ge_f16
:
661 op
= aco_opcode::v_cmp_le_f16
;
663 case aco_opcode::v_cmp_lt_i16
:
664 op
= aco_opcode::v_cmp_gt_i16
;
666 case aco_opcode::v_cmp_ge_i16
:
667 op
= aco_opcode::v_cmp_le_i16
;
669 case aco_opcode::v_cmp_lt_u16
:
670 op
= aco_opcode::v_cmp_gt_u16
;
672 case aco_opcode::v_cmp_ge_u16
:
673 op
= aco_opcode::v_cmp_le_u16
;
675 case aco_opcode::v_cmp_lt_f32
:
676 op
= aco_opcode::v_cmp_gt_f32
;
678 case aco_opcode::v_cmp_ge_f32
:
679 op
= aco_opcode::v_cmp_le_f32
;
681 case aco_opcode::v_cmp_lt_i32
:
682 op
= aco_opcode::v_cmp_gt_i32
;
684 case aco_opcode::v_cmp_ge_i32
:
685 op
= aco_opcode::v_cmp_le_i32
;
687 case aco_opcode::v_cmp_lt_u32
:
688 op
= aco_opcode::v_cmp_gt_u32
;
690 case aco_opcode::v_cmp_ge_u32
:
691 op
= aco_opcode::v_cmp_le_u32
;
693 case aco_opcode::v_cmp_lt_f64
:
694 op
= aco_opcode::v_cmp_gt_f64
;
696 case aco_opcode::v_cmp_ge_f64
:
697 op
= aco_opcode::v_cmp_le_f64
;
699 case aco_opcode::v_cmp_lt_i64
:
700 op
= aco_opcode::v_cmp_gt_i64
;
702 case aco_opcode::v_cmp_ge_i64
:
703 op
= aco_opcode::v_cmp_le_i64
;
705 case aco_opcode::v_cmp_lt_u64
:
706 op
= aco_opcode::v_cmp_gt_u64
;
708 case aco_opcode::v_cmp_ge_u64
:
709 op
= aco_opcode::v_cmp_le_u64
;
711 default: /* eq and ne are commutative */
718 src1
= as_vgpr(ctx
, src1
);
722 Builder
bld(ctx
->program
, ctx
->block
);
723 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
726 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
728 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
729 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
730 Builder
bld(ctx
->program
, ctx
->block
);
732 assert(dst
.regClass() == bld
.lm
);
733 assert(src0
.type() == RegType::sgpr
);
734 assert(src1
.type() == RegType::sgpr
);
735 assert(src0
.regClass() == src1
.regClass());
737 /* Emit the SALU comparison instruction */
738 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
739 /* Turn the result into a per-lane bool */
740 bool_to_vector_condition(ctx
, cmp
, dst
);
743 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
744 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
746 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
747 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
748 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
749 nir_dest_is_divergent(instr
->dest
.dest
) ||
750 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
751 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
752 aco_opcode op
= use_valu
? v_op
: s_op
;
753 assert(op
!= aco_opcode::num_opcodes
);
754 assert(dst
.regClass() == ctx
->program
->lane_mask
);
757 emit_vopc_instruction(ctx
, instr
, op
, dst
);
759 emit_sopc_instruction(ctx
, instr
, op
, dst
);
762 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
764 Builder
bld(ctx
->program
, ctx
->block
);
765 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
766 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
768 assert(dst
.regClass() == bld
.lm
);
769 assert(src0
.regClass() == bld
.lm
);
770 assert(src1
.regClass() == bld
.lm
);
772 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
775 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
777 Builder
bld(ctx
->program
, ctx
->block
);
778 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
779 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
780 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
782 assert(cond
.regClass() == bld
.lm
);
784 if (dst
.type() == RegType::vgpr
) {
785 aco_ptr
<Instruction
> bcsel
;
786 if (dst
.size() == 1) {
787 then
= as_vgpr(ctx
, then
);
788 els
= as_vgpr(ctx
, els
);
790 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
791 } else if (dst
.size() == 2) {
792 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
793 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
794 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
795 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
797 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
798 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
800 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
802 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
803 nir_print_instr(&instr
->instr
, stderr
);
804 fprintf(stderr
, "\n");
809 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
810 assert(dst
.regClass() == bld
.lm
);
811 assert(then
.regClass() == bld
.lm
);
812 assert(els
.regClass() == bld
.lm
);
815 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
816 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
817 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
818 assert(dst
.size() == then
.size());
819 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
820 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
822 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
823 nir_print_instr(&instr
->instr
, stderr
);
824 fprintf(stderr
, "\n");
829 /* divergent boolean bcsel
830 * this implements bcsel on bools: dst = s0 ? s1 : s2
831 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
832 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
834 if (cond
.id() != then
.id())
835 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
837 if (cond
.id() == els
.id())
838 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
840 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
841 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
844 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
845 aco_opcode op
, uint32_t undo
)
847 /* multiply by 16777216 to handle denormals */
848 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
849 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
850 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
851 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
852 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
854 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
856 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
859 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
861 if (ctx
->block
->fp_mode
.denorm32
== 0) {
862 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
866 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
869 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
871 if (ctx
->block
->fp_mode
.denorm32
== 0) {
872 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
876 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
879 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
881 if (ctx
->block
->fp_mode
.denorm32
== 0) {
882 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
886 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
889 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
891 if (ctx
->block
->fp_mode
.denorm32
== 0) {
892 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
896 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
899 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
901 if (ctx
->options
->chip_class
>= GFX7
)
902 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
904 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
905 /* TODO: create more efficient code! */
906 if (val
.type() == RegType::sgpr
)
907 val
= as_vgpr(ctx
, val
);
909 /* Split the input value. */
910 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
911 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
913 /* Extract the exponent and compute the unbiased value. */
914 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
915 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
917 /* Extract the fractional part. */
918 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
919 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
921 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
924 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
925 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
926 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
927 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
928 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
930 /* Get the sign bit. */
931 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
933 /* Decide the operation to apply depending on the unbiased exponent. */
934 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
935 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
936 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
937 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
938 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
939 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
941 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
944 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
946 if (ctx
->options
->chip_class
>= GFX7
)
947 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
949 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
950 Temp src0
= as_vgpr(ctx
, val
);
952 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
953 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
955 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
956 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
957 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
959 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
960 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
961 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
964 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
965 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
967 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
969 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
970 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
972 return add
->definitions
[0].getTemp();
975 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
977 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
978 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
980 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
983 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
984 return bld
.copy(Definition(dst
), src
);
985 else if (dst
.bytes() < src
.bytes())
986 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
990 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
993 } else if (src
.regClass() == s1
) {
995 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
997 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
998 } else if (ctx
->options
->chip_class
>= GFX8
) {
999 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1000 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1001 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1002 sdwa
->operands
[0] = Operand(src
);
1003 sdwa
->definitions
[0] = Definition(tmp
);
1005 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1007 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1008 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1009 bld
.insert(std::move(sdwa
));
1011 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1012 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1013 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1016 if (dst_bits
== 64) {
1017 if (is_signed
&& dst
.regClass() == s2
) {
1018 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1019 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1020 } else if (is_signed
&& dst
.regClass() == v2
) {
1021 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1022 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1024 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1031 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1033 if (!instr
->dest
.dest
.is_ssa
) {
1034 fprintf(stderr
, "nir alu dst not in ssa: ");
1035 nir_print_instr(&instr
->instr
, stderr
);
1036 fprintf(stderr
, "\n");
1039 Builder
bld(ctx
->program
, ctx
->block
);
1040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1045 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1046 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1047 for (unsigned i
= 0; i
< num
; ++i
)
1048 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1050 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1051 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1052 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1053 for (unsigned i
= 0; i
< num
; ++i
) {
1054 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1055 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1057 vec
->operands
[i
] = Operand
{elems
[i
]};
1059 vec
->definitions
[0] = Definition(dst
);
1060 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1061 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1063 // TODO: that is a bit suboptimal..
1064 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1065 for (unsigned i
= 0; i
< num
- 1; ++i
)
1066 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1067 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1068 for (unsigned i
= 0; i
< num
; ++i
) {
1069 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1070 if (bit
% 32 == 0) {
1071 elems
[bit
/ 32] = elems
[i
];
1073 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1074 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1075 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1078 if (dst
.size() == 1)
1079 bld
.copy(Definition(dst
), elems
[0]);
1081 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1086 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1087 aco_ptr
<Instruction
> mov
;
1088 if (dst
.type() == RegType::sgpr
) {
1089 if (src
.type() == RegType::vgpr
)
1090 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1091 else if (src
.regClass() == s1
)
1092 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1093 else if (src
.regClass() == s2
)
1094 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1096 unreachable("wrong src register class for nir_op_imov");
1098 if (dst
.regClass() == v1
)
1099 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1100 else if (dst
.regClass() == v1b
||
1101 dst
.regClass() == v2b
||
1102 dst
.regClass() == v2
)
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1105 unreachable("wrong src register class for nir_op_imov");
1110 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1111 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1112 assert(src
.regClass() == bld
.lm
);
1113 assert(dst
.regClass() == bld
.lm
);
1114 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1115 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1116 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1117 } else if (dst
.regClass() == v1
) {
1118 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1119 } else if (dst
.type() == RegType::sgpr
) {
1120 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1121 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1124 nir_print_instr(&instr
->instr
, stderr
);
1125 fprintf(stderr
, "\n");
1130 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1131 if (dst
.regClass() == v1
) {
1132 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1133 } else if (dst
.regClass() == s1
) {
1134 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1135 } else if (dst
.size() == 2) {
1136 Temp src0
= bld
.tmp(dst
.type(), 1);
1137 Temp src1
= bld
.tmp(dst
.type(), 1);
1138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1140 if (dst
.regClass() == s2
) {
1141 Temp carry
= bld
.tmp(s1
);
1142 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1143 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1144 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1146 Temp lower
= bld
.tmp(v1
);
1147 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1148 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1149 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1152 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1153 nir_print_instr(&instr
->instr
, stderr
);
1154 fprintf(stderr
, "\n");
1159 if (dst
.regClass() == s1
) {
1160 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1161 } else if (dst
.regClass() == v1
) {
1162 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1163 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1166 nir_print_instr(&instr
->instr
, stderr
);
1167 fprintf(stderr
, "\n");
1171 case nir_op_isign
: {
1172 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1173 if (dst
.regClass() == s1
) {
1174 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1175 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1176 } else if (dst
.regClass() == s2
) {
1177 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1179 if (ctx
->program
->chip_class
>= GFX8
)
1180 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1182 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1183 /* SCC gets zero-extended to 64 bit */
1184 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1185 } else if (dst
.regClass() == v1
) {
1186 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1187 } else if (dst
.regClass() == v2
) {
1188 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1189 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1190 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1191 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1192 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1193 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1195 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1196 nir_print_instr(&instr
->instr
, stderr
);
1197 fprintf(stderr
, "\n");
1202 if (dst
.regClass() == v1
) {
1203 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1204 } else if (dst
.regClass() == s1
) {
1205 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1207 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1208 nir_print_instr(&instr
->instr
, stderr
);
1209 fprintf(stderr
, "\n");
1214 if (dst
.regClass() == v1
) {
1215 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1216 } else if (dst
.regClass() == s1
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1219 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1220 nir_print_instr(&instr
->instr
, stderr
);
1221 fprintf(stderr
, "\n");
1226 if (dst
.regClass() == v1
) {
1227 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1228 } else if (dst
.regClass() == s1
) {
1229 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (dst
.regClass() == v1
) {
1239 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1243 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1244 nir_print_instr(&instr
->instr
, stderr
);
1245 fprintf(stderr
, "\n");
1250 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1251 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1252 } else if (dst
.regClass() == v1
) {
1253 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1254 } else if (dst
.regClass() == s1
) {
1255 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1256 } else if (dst
.regClass() == s2
) {
1257 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1259 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1260 nir_print_instr(&instr
->instr
, stderr
);
1261 fprintf(stderr
, "\n");
1266 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1267 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1268 } else if (dst
.regClass() == v1
) {
1269 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1270 } else if (dst
.regClass() == s1
) {
1271 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1272 } else if (dst
.regClass() == s2
) {
1273 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1275 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1276 nir_print_instr(&instr
->instr
, stderr
);
1277 fprintf(stderr
, "\n");
1282 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1283 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1284 } else if (dst
.regClass() == v1
) {
1285 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1286 } else if (dst
.regClass() == s1
) {
1287 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1288 } else if (dst
.regClass() == s2
) {
1289 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1291 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1292 nir_print_instr(&instr
->instr
, stderr
);
1293 fprintf(stderr
, "\n");
1298 if (dst
.regClass() == v1
) {
1299 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1300 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1301 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1302 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1303 } else if (dst
.regClass() == v2
) {
1304 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1305 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1306 } else if (dst
.regClass() == s2
) {
1307 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1308 } else if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1311 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1312 nir_print_instr(&instr
->instr
, stderr
);
1313 fprintf(stderr
, "\n");
1318 if (dst
.regClass() == v1
) {
1319 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1320 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1321 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1322 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1323 } else if (dst
.regClass() == v2
) {
1324 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1325 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1326 } else if (dst
.regClass() == s1
) {
1327 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1328 } else if (dst
.regClass() == s2
) {
1329 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1331 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1332 nir_print_instr(&instr
->instr
, stderr
);
1333 fprintf(stderr
, "\n");
1338 if (dst
.regClass() == v1
) {
1339 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1340 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1341 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1342 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1343 } else if (dst
.regClass() == v2
) {
1344 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1345 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1346 } else if (dst
.regClass() == s1
) {
1347 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1348 } else if (dst
.regClass() == s2
) {
1349 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1351 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1352 nir_print_instr(&instr
->instr
, stderr
);
1353 fprintf(stderr
, "\n");
1357 case nir_op_find_lsb
: {
1358 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1359 if (src
.regClass() == s1
) {
1360 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1361 } else if (src
.regClass() == v1
) {
1362 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1363 } else if (src
.regClass() == s2
) {
1364 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1372 case nir_op_ufind_msb
:
1373 case nir_op_ifind_msb
: {
1374 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1375 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1376 aco_opcode op
= src
.regClass() == s2
?
1377 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1378 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1379 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1381 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1382 Operand(src
.size() * 32u - 1u), msb_rev
);
1383 Temp msb
= sub
.def(0).getTemp();
1384 Temp carry
= sub
.def(1).getTemp();
1386 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1387 } else if (src
.regClass() == v1
) {
1388 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1389 Temp msb_rev
= bld
.tmp(v1
);
1390 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1391 Temp msb
= bld
.tmp(v1
);
1392 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1393 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1395 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1396 nir_print_instr(&instr
->instr
, stderr
);
1397 fprintf(stderr
, "\n");
1401 case nir_op_bitfield_reverse
: {
1402 if (dst
.regClass() == s1
) {
1403 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1404 } else if (dst
.regClass() == v1
) {
1405 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1407 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1408 nir_print_instr(&instr
->instr
, stderr
);
1409 fprintf(stderr
, "\n");
1414 if (dst
.regClass() == s1
) {
1415 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1419 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1420 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1421 if (dst
.regClass() == v1
) {
1422 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1426 assert(src0
.size() == 2 && src1
.size() == 2);
1427 Temp src00
= bld
.tmp(src0
.type(), 1);
1428 Temp src01
= bld
.tmp(dst
.type(), 1);
1429 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1430 Temp src10
= bld
.tmp(src1
.type(), 1);
1431 Temp src11
= bld
.tmp(dst
.type(), 1);
1432 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1434 if (dst
.regClass() == s2
) {
1435 Temp carry
= bld
.tmp(s1
);
1436 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1437 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1438 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1439 } else if (dst
.regClass() == v2
) {
1440 Temp dst0
= bld
.tmp(v1
);
1441 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1442 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1443 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1445 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1446 nir_print_instr(&instr
->instr
, stderr
);
1447 fprintf(stderr
, "\n");
1451 case nir_op_uadd_sat
: {
1452 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1453 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1454 if (dst
.regClass() == s1
) {
1455 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1456 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1458 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1459 } else if (dst
.regClass() == v1
) {
1460 if (ctx
->options
->chip_class
>= GFX9
) {
1461 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1462 add
->operands
[0] = Operand(src0
);
1463 add
->operands
[1] = Operand(src1
);
1464 add
->definitions
[0] = Definition(dst
);
1466 ctx
->block
->instructions
.emplace_back(std::move(add
));
1468 if (src1
.regClass() != v1
)
1469 std::swap(src0
, src1
);
1470 assert(src1
.regClass() == v1
);
1471 Temp tmp
= bld
.tmp(v1
);
1472 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1473 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1476 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1477 nir_print_instr(&instr
->instr
, stderr
);
1478 fprintf(stderr
, "\n");
1482 case nir_op_uadd_carry
: {
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == s1
) {
1486 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1489 if (dst
.regClass() == v1
) {
1490 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1491 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1495 Temp src00
= bld
.tmp(src0
.type(), 1);
1496 Temp src01
= bld
.tmp(dst
.type(), 1);
1497 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1498 Temp src10
= bld
.tmp(src1
.type(), 1);
1499 Temp src11
= bld
.tmp(dst
.type(), 1);
1500 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1501 if (dst
.regClass() == s2
) {
1502 Temp carry
= bld
.tmp(s1
);
1503 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1504 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1506 } else if (dst
.regClass() == v2
) {
1507 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1508 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1509 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1512 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1513 nir_print_instr(&instr
->instr
, stderr
);
1514 fprintf(stderr
, "\n");
1519 if (dst
.regClass() == s1
) {
1520 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1524 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1525 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1526 if (dst
.regClass() == v1
) {
1527 bld
.vsub32(Definition(dst
), src0
, src1
);
1531 Temp src00
= bld
.tmp(src0
.type(), 1);
1532 Temp src01
= bld
.tmp(dst
.type(), 1);
1533 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1534 Temp src10
= bld
.tmp(src1
.type(), 1);
1535 Temp src11
= bld
.tmp(dst
.type(), 1);
1536 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1537 if (dst
.regClass() == s2
) {
1538 Temp carry
= bld
.tmp(s1
);
1539 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1540 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1541 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1542 } else if (dst
.regClass() == v2
) {
1543 Temp lower
= bld
.tmp(v1
);
1544 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1545 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1546 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1554 case nir_op_usub_borrow
: {
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.regClass() == s1
) {
1558 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1560 } else if (dst
.regClass() == v1
) {
1561 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1562 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1566 Temp src00
= bld
.tmp(src0
.type(), 1);
1567 Temp src01
= bld
.tmp(dst
.type(), 1);
1568 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1569 Temp src10
= bld
.tmp(src1
.type(), 1);
1570 Temp src11
= bld
.tmp(dst
.type(), 1);
1571 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1572 if (dst
.regClass() == s2
) {
1573 Temp borrow
= bld
.tmp(s1
);
1574 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1575 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1576 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1577 } else if (dst
.regClass() == v2
) {
1578 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1579 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1580 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1581 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1583 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1584 nir_print_instr(&instr
->instr
, stderr
);
1585 fprintf(stderr
, "\n");
1590 if (dst
.regClass() == v1
) {
1591 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1592 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1593 } else if (dst
.regClass() == s1
) {
1594 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1596 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1597 nir_print_instr(&instr
->instr
, stderr
);
1598 fprintf(stderr
, "\n");
1602 case nir_op_umul_high
: {
1603 if (dst
.regClass() == v1
) {
1604 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1605 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1606 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1607 } else if (dst
.regClass() == s1
) {
1608 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1609 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1610 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1612 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1613 nir_print_instr(&instr
->instr
, stderr
);
1614 fprintf(stderr
, "\n");
1618 case nir_op_imul_high
: {
1619 if (dst
.regClass() == v1
) {
1620 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1621 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1622 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1623 } else if (dst
.regClass() == s1
) {
1624 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1625 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1626 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1628 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1629 nir_print_instr(&instr
->instr
, stderr
);
1630 fprintf(stderr
, "\n");
1635 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1636 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1637 if (dst
.regClass() == v2b
) {
1638 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1639 } else if (dst
.regClass() == v1
) {
1640 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1641 } else if (dst
.regClass() == v2
) {
1642 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1644 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1645 nir_print_instr(&instr
->instr
, stderr
);
1646 fprintf(stderr
, "\n");
1651 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1652 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1653 if (dst
.regClass() == v2b
) {
1654 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1655 } else if (dst
.regClass() == v1
) {
1656 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1657 } else if (dst
.regClass() == v2
) {
1658 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1660 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1661 nir_print_instr(&instr
->instr
, stderr
);
1662 fprintf(stderr
, "\n");
1667 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1668 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1669 if (dst
.regClass() == v2b
) {
1670 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1671 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1673 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1674 } else if (dst
.regClass() == v1
) {
1675 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1676 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1678 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1679 } else if (dst
.regClass() == v2
) {
1680 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1681 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1682 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1686 nir_print_instr(&instr
->instr
, stderr
);
1687 fprintf(stderr
, "\n");
1692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1693 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1694 if (dst
.regClass() == v2b
) {
1695 // TODO: check fp_mode.must_flush_denorms16_64
1696 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1697 } else if (dst
.regClass() == v1
) {
1698 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1699 } else if (dst
.regClass() == v2
) {
1700 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1701 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1702 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1704 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1715 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1716 if (dst
.regClass() == v2b
) {
1717 // TODO: check fp_mode.must_flush_denorms16_64
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1719 } else if (dst
.regClass() == v1
) {
1720 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1721 } else if (dst
.regClass() == v2
) {
1722 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1723 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1724 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1726 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1729 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1730 nir_print_instr(&instr
->instr
, stderr
);
1731 fprintf(stderr
, "\n");
1735 case nir_op_fmax3
: {
1736 if (dst
.regClass() == v2b
) {
1737 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1738 } else if (dst
.regClass() == v1
) {
1739 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1742 nir_print_instr(&instr
->instr
, stderr
);
1743 fprintf(stderr
, "\n");
1747 case nir_op_fmin3
: {
1748 if (dst
.regClass() == v2b
) {
1749 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1750 } else if (dst
.regClass() == v1
) {
1751 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1753 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1754 nir_print_instr(&instr
->instr
, stderr
);
1755 fprintf(stderr
, "\n");
1759 case nir_op_fmed3
: {
1760 if (dst
.regClass() == v2b
) {
1761 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1765 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1766 nir_print_instr(&instr
->instr
, stderr
);
1767 fprintf(stderr
, "\n");
1771 case nir_op_umax3
: {
1772 if (dst
.size() == 1) {
1773 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1775 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1776 nir_print_instr(&instr
->instr
, stderr
);
1777 fprintf(stderr
, "\n");
1781 case nir_op_umin3
: {
1782 if (dst
.size() == 1) {
1783 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1785 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1786 nir_print_instr(&instr
->instr
, stderr
);
1787 fprintf(stderr
, "\n");
1791 case nir_op_umed3
: {
1792 if (dst
.size() == 1) {
1793 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1795 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1796 nir_print_instr(&instr
->instr
, stderr
);
1797 fprintf(stderr
, "\n");
1801 case nir_op_imax3
: {
1802 if (dst
.size() == 1) {
1803 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1805 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1806 nir_print_instr(&instr
->instr
, stderr
);
1807 fprintf(stderr
, "\n");
1811 case nir_op_imin3
: {
1812 if (dst
.size() == 1) {
1813 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1815 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1816 nir_print_instr(&instr
->instr
, stderr
);
1817 fprintf(stderr
, "\n");
1821 case nir_op_imed3
: {
1822 if (dst
.size() == 1) {
1823 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1825 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1826 nir_print_instr(&instr
->instr
, stderr
);
1827 fprintf(stderr
, "\n");
1831 case nir_op_cube_face_coord
: {
1832 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1833 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1834 emit_extract_vector(ctx
, in
, 1, v1
),
1835 emit_extract_vector(ctx
, in
, 2, v1
) };
1836 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1837 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1838 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1839 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1840 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1841 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1842 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1845 case nir_op_cube_face_index
: {
1846 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1847 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1848 emit_extract_vector(ctx
, in
, 1, v1
),
1849 emit_extract_vector(ctx
, in
, 2, v1
) };
1850 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1853 case nir_op_bcsel
: {
1854 emit_bcsel(ctx
, instr
, dst
);
1858 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1859 if (dst
.regClass() == v2b
) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1861 } else if (dst
.regClass() == v1
) {
1862 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1863 } else if (dst
.regClass() == v2
) {
1864 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1866 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1867 nir_print_instr(&instr
->instr
, stderr
);
1868 fprintf(stderr
, "\n");
1873 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1874 if (dst
.regClass() == v2b
) {
1875 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1898 } else if (dst
.regClass() == v1
) {
1899 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1900 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1901 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1902 } else if (dst
.regClass() == v2
) {
1903 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1904 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1905 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1906 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1907 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1908 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1911 nir_print_instr(&instr
->instr
, stderr
);
1912 fprintf(stderr
, "\n");
1917 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1918 if (dst
.regClass() == v2b
) {
1919 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1920 } else if (dst
.regClass() == v1
) {
1921 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1922 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1923 // TODO: confirm that this holds under any circumstances
1924 } else if (dst
.regClass() == v2
) {
1925 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1926 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1935 case nir_op_flog2
: {
1936 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1937 if (dst
.regClass() == v2b
) {
1938 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1939 } else if (dst
.regClass() == v1
) {
1940 emit_log2(ctx
, bld
, Definition(dst
), src
);
1942 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1943 nir_print_instr(&instr
->instr
, stderr
);
1944 fprintf(stderr
, "\n");
1949 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1950 if (dst
.regClass() == v2b
) {
1951 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1952 } else if (dst
.regClass() == v1
) {
1953 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1954 } else if (dst
.regClass() == v2
) {
1955 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1958 nir_print_instr(&instr
->instr
, stderr
);
1959 fprintf(stderr
, "\n");
1963 case nir_op_fexp2
: {
1964 if (dst
.regClass() == v2b
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1966 } else if (dst
.regClass() == v1
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1969 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1970 nir_print_instr(&instr
->instr
, stderr
);
1971 fprintf(stderr
, "\n");
1975 case nir_op_fsqrt
: {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 if (dst
.regClass() == v2b
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffract
: {
1991 if (dst
.regClass() == v2b
) {
1992 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1993 } else if (dst
.regClass() == v1
) {
1994 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1995 } else if (dst
.regClass() == v2
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1998 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1999 nir_print_instr(&instr
->instr
, stderr
);
2000 fprintf(stderr
, "\n");
2004 case nir_op_ffloor
: {
2005 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2006 if (dst
.regClass() == v2b
) {
2007 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2008 } else if (dst
.regClass() == v1
) {
2009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2010 } else if (dst
.regClass() == v2
) {
2011 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2013 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2014 nir_print_instr(&instr
->instr
, stderr
);
2015 fprintf(stderr
, "\n");
2019 case nir_op_fceil
: {
2020 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2021 if (dst
.regClass() == v2b
) {
2022 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2023 } else if (dst
.regClass() == v1
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2025 } else if (dst
.regClass() == v2
) {
2026 if (ctx
->options
->chip_class
>= GFX7
) {
2027 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2029 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2030 /* trunc = trunc(src0)
2031 * if (src0 > 0.0 && src0 != trunc)
2034 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2035 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2036 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2037 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2038 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2039 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2040 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2044 nir_print_instr(&instr
->instr
, stderr
);
2045 fprintf(stderr
, "\n");
2049 case nir_op_ftrunc
: {
2050 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2051 if (dst
.regClass() == v2b
) {
2052 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2053 } else if (dst
.regClass() == v1
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2055 } else if (dst
.regClass() == v2
) {
2056 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2058 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2059 nir_print_instr(&instr
->instr
, stderr
);
2060 fprintf(stderr
, "\n");
2064 case nir_op_fround_even
: {
2065 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2066 if (dst
.regClass() == v2b
) {
2067 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2068 } else if (dst
.regClass() == v1
) {
2069 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2070 } else if (dst
.regClass() == v2
) {
2071 if (ctx
->options
->chip_class
>= GFX7
) {
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2074 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2075 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2078 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2079 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2080 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2081 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2082 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2083 tmp
= sub
->definitions
[0].getTemp();
2085 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2086 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2087 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2088 Temp cond
= vop3
->definitions
[0].getTemp();
2090 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2091 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2092 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2093 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2095 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2098 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2099 nir_print_instr(&instr
->instr
, stderr
);
2100 fprintf(stderr
, "\n");
2106 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2107 aco_ptr
<Instruction
> norm
;
2108 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2109 if (dst
.regClass() == v2b
) {
2110 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2113 } else if (dst
.regClass() == v1
) {
2114 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2116 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2117 if (ctx
->options
->chip_class
< GFX9
)
2118 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2120 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2121 bld
.vop1(opcode
, Definition(dst
), tmp
);
2123 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2124 nir_print_instr(&instr
->instr
, stderr
);
2125 fprintf(stderr
, "\n");
2129 case nir_op_ldexp
: {
2130 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2131 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2132 if (dst
.regClass() == v2b
) {
2133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2134 } else if (dst
.regClass() == v1
) {
2135 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2136 } else if (dst
.regClass() == v2
) {
2137 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2139 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2140 nir_print_instr(&instr
->instr
, stderr
);
2141 fprintf(stderr
, "\n");
2145 case nir_op_frexp_sig
: {
2146 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2147 if (dst
.regClass() == v2b
) {
2148 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2149 } else if (dst
.regClass() == v1
) {
2150 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2151 } else if (dst
.regClass() == v2
) {
2152 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2155 nir_print_instr(&instr
->instr
, stderr
);
2156 fprintf(stderr
, "\n");
2160 case nir_op_frexp_exp
: {
2161 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2162 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2163 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2164 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2165 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2166 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2167 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2168 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2169 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2171 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2172 nir_print_instr(&instr
->instr
, stderr
);
2173 fprintf(stderr
, "\n");
2177 case nir_op_fsign
: {
2178 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2179 if (dst
.regClass() == v2b
) {
2180 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2181 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2186 } else if (dst
.regClass() == v1
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2189 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2190 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2191 } else if (dst
.regClass() == v2
) {
2192 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2193 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2194 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2196 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2197 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2198 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2200 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2203 nir_print_instr(&instr
->instr
, stderr
);
2204 fprintf(stderr
, "\n");
2209 case nir_op_f2f16_rtne
: {
2210 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2211 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2212 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2213 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2216 case nir_op_f2f16_rtz
: {
2217 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2218 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2219 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2220 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2223 case nir_op_f2f32
: {
2224 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2225 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2226 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2229 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2230 nir_print_instr(&instr
->instr
, stderr
);
2231 fprintf(stderr
, "\n");
2235 case nir_op_f2f64
: {
2236 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2237 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2238 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2239 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2242 case nir_op_i2f16
: {
2243 assert(dst
.regClass() == v2b
);
2244 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2245 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2246 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2247 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2248 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2249 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2252 case nir_op_i2f32
: {
2253 assert(dst
.size() == 1);
2254 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2255 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2256 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2257 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2260 case nir_op_i2f64
: {
2261 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2262 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2263 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2264 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2265 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2266 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2267 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2268 RegClass rc
= RegClass(src
.type(), 1);
2269 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2270 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2271 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2272 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2273 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2274 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2277 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2278 nir_print_instr(&instr
->instr
, stderr
);
2279 fprintf(stderr
, "\n");
2283 case nir_op_u2f16
: {
2284 assert(dst
.regClass() == v2b
);
2285 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2286 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2287 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2288 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2289 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2290 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2293 case nir_op_u2f32
: {
2294 assert(dst
.size() == 1);
2295 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2296 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2297 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2298 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2300 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2301 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2302 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2306 case nir_op_u2f64
: {
2307 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2310 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2311 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2312 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2313 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2314 RegClass rc
= RegClass(src
.type(), 1);
2315 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2316 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2317 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2318 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2319 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2320 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2322 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2323 nir_print_instr(&instr
->instr
, stderr
);
2324 fprintf(stderr
, "\n");
2329 case nir_op_f2i16
: {
2330 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2331 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2332 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2333 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2334 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2336 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2338 if (dst
.type() == RegType::vgpr
)
2339 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2345 case nir_op_f2u16
: {
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2348 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2349 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2350 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2352 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2354 if (dst
.type() == RegType::vgpr
)
2355 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2357 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2360 case nir_op_f2i32
: {
2361 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2362 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2363 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2364 if (dst
.type() == RegType::vgpr
) {
2365 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2367 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2368 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2370 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2371 if (dst
.type() == RegType::vgpr
)
2372 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2374 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2375 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2377 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2378 if (dst
.type() == RegType::vgpr
)
2379 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2381 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2382 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2385 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2386 nir_print_instr(&instr
->instr
, stderr
);
2387 fprintf(stderr
, "\n");
2391 case nir_op_f2u32
: {
2392 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2393 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2394 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2395 if (dst
.type() == RegType::vgpr
) {
2396 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2399 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2401 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2402 if (dst
.type() == RegType::vgpr
)
2403 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2405 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2406 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2409 if (dst
.type() == RegType::vgpr
)
2410 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2412 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2413 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2416 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2417 nir_print_instr(&instr
->instr
, stderr
);
2418 fprintf(stderr
, "\n");
2422 case nir_op_f2i64
: {
2423 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2424 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2425 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2427 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2428 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2429 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2430 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2431 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2432 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2433 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2434 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2435 Temp new_exponent
= bld
.tmp(v1
);
2436 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2437 if (ctx
->program
->chip_class
>= GFX8
)
2438 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2440 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2441 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2442 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2443 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2444 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2445 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2446 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2447 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2448 Temp new_lower
= bld
.tmp(v1
);
2449 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2450 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2453 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2454 if (src
.type() == RegType::vgpr
)
2455 src
= bld
.as_uniform(src
);
2456 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2457 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2458 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2459 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2460 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2461 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2462 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2463 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2464 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2465 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2466 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2467 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2468 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2469 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2470 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2471 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2472 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2473 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2474 Temp borrow
= bld
.tmp(s1
);
2475 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2476 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2479 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2480 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2481 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2482 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2483 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2484 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2485 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2486 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2487 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2488 if (dst
.type() == RegType::sgpr
) {
2489 lower
= bld
.as_uniform(lower
);
2490 upper
= bld
.as_uniform(upper
);
2492 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2495 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2496 nir_print_instr(&instr
->instr
, stderr
);
2497 fprintf(stderr
, "\n");
2501 case nir_op_f2u64
: {
2502 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2503 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2504 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2506 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2507 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2508 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2509 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2510 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2511 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2512 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2513 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2514 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2515 Temp new_exponent
= bld
.tmp(v1
);
2516 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2517 if (ctx
->program
->chip_class
>= GFX8
)
2518 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2520 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2521 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2522 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2523 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2524 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2525 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2526 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2527 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2529 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2530 if (src
.type() == RegType::vgpr
)
2531 src
= bld
.as_uniform(src
);
2532 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2533 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2534 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2535 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2536 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2537 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2538 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2539 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2540 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2541 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2542 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2543 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2544 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2545 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2546 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2547 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2548 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2549 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2551 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2552 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2553 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2554 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2555 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2556 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2557 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2558 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2559 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2560 if (dst
.type() == RegType::sgpr
) {
2561 lower
= bld
.as_uniform(lower
);
2562 upper
= bld
.as_uniform(upper
);
2564 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2567 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2568 nir_print_instr(&instr
->instr
, stderr
);
2569 fprintf(stderr
, "\n");
2573 case nir_op_b2f16
: {
2574 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2575 assert(src
.regClass() == bld
.lm
);
2577 if (dst
.regClass() == s1
) {
2578 src
= bool_to_scalar_condition(ctx
, src
);
2579 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2580 } else if (dst
.regClass() == v2b
) {
2581 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2582 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2584 unreachable("Wrong destination register class for nir_op_b2f16.");
2588 case nir_op_b2f32
: {
2589 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2590 assert(src
.regClass() == bld
.lm
);
2592 if (dst
.regClass() == s1
) {
2593 src
= bool_to_scalar_condition(ctx
, src
);
2594 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2595 } else if (dst
.regClass() == v1
) {
2596 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2598 unreachable("Wrong destination register class for nir_op_b2f32.");
2602 case nir_op_b2f64
: {
2603 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2604 assert(src
.regClass() == bld
.lm
);
2606 if (dst
.regClass() == s2
) {
2607 src
= bool_to_scalar_condition(ctx
, src
);
2608 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2609 } else if (dst
.regClass() == v2
) {
2610 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2611 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2612 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2614 unreachable("Wrong destination register class for nir_op_b2f64.");
2621 case nir_op_i2i64
: {
2622 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2623 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2629 case nir_op_u2u64
: {
2630 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2631 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2635 case nir_op_b2i32
: {
2636 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2637 assert(src
.regClass() == bld
.lm
);
2639 if (dst
.regClass() == s1
) {
2640 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2641 bool_to_scalar_condition(ctx
, src
, dst
);
2642 } else if (dst
.regClass() == v1
) {
2643 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2645 unreachable("Invalid register class for b2i32");
2651 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2652 assert(dst
.regClass() == bld
.lm
);
2654 if (src
.type() == RegType::vgpr
) {
2655 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2656 assert(dst
.regClass() == bld
.lm
);
2657 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2658 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2660 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2662 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2663 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2665 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2666 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2668 bool_to_vector_condition(ctx
, tmp
, dst
);
2672 case nir_op_pack_64_2x32_split
: {
2673 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2674 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2676 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2679 case nir_op_unpack_64_2x32_split_x
:
2680 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2682 case nir_op_unpack_64_2x32_split_y
:
2683 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2685 case nir_op_unpack_32_2x16_split_x
:
2686 if (dst
.type() == RegType::vgpr
) {
2687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2689 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2692 case nir_op_unpack_32_2x16_split_y
:
2693 if (dst
.type() == RegType::vgpr
) {
2694 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2696 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2699 case nir_op_pack_32_2x16_split
: {
2700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2702 if (dst
.regClass() == v1
) {
2703 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2704 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2705 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2707 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2708 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2709 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2713 case nir_op_pack_half_2x16
: {
2714 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2716 if (dst
.regClass() == v1
) {
2717 Temp src0
= bld
.tmp(v1
);
2718 Temp src1
= bld
.tmp(v1
);
2719 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2720 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2721 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2723 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2724 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2725 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2728 nir_print_instr(&instr
->instr
, stderr
);
2729 fprintf(stderr
, "\n");
2733 case nir_op_unpack_half_2x16_split_x
: {
2734 if (dst
.regClass() == v1
) {
2735 Builder
bld(ctx
->program
, ctx
->block
);
2736 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2738 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2739 nir_print_instr(&instr
->instr
, stderr
);
2740 fprintf(stderr
, "\n");
2744 case nir_op_unpack_half_2x16_split_y
: {
2745 if (dst
.regClass() == v1
) {
2746 Builder
bld(ctx
->program
, ctx
->block
);
2747 /* TODO: use SDWA here */
2748 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2749 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2752 nir_print_instr(&instr
->instr
, stderr
);
2753 fprintf(stderr
, "\n");
2757 case nir_op_fquantize2f16
: {
2758 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2759 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2762 if (ctx
->program
->chip_class
>= GFX8
) {
2763 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2764 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2765 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2767 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2768 * so compare the result and flush to 0 if it's smaller.
2770 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2771 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2772 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2773 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2774 cmp_res
= vop3
->definitions
[0].getTemp();
2777 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2778 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2779 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2781 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2786 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2787 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2789 if (dst
.regClass() == s1
) {
2790 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2791 } else if (dst
.regClass() == v1
) {
2792 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2794 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2795 nir_print_instr(&instr
->instr
, stderr
);
2796 fprintf(stderr
, "\n");
2800 case nir_op_bitfield_select
: {
2801 /* (mask & insert) | (~mask & base) */
2802 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2803 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2804 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2806 /* dst = (insert & bitmask) | (base & ~bitmask) */
2807 if (dst
.regClass() == s1
) {
2808 aco_ptr
<Instruction
> sop2
;
2809 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2810 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2812 if (const_insert
&& const_bitmask
) {
2813 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2815 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2816 lhs
= Operand(insert
);
2820 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2821 if (const_base
&& const_bitmask
) {
2822 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2824 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2825 rhs
= Operand(base
);
2828 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2830 } else if (dst
.regClass() == v1
) {
2831 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2832 base
= as_vgpr(ctx
, base
);
2833 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2834 insert
= as_vgpr(ctx
, insert
);
2836 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2839 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2840 nir_print_instr(&instr
->instr
, stderr
);
2841 fprintf(stderr
, "\n");
2847 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2848 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2849 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2851 if (dst
.type() == RegType::sgpr
) {
2853 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2854 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2855 if (const_offset
&& const_bits
) {
2856 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2857 extract
= Operand(const_extract
);
2861 width
= Operand(const_bits
->u32
<< 16);
2863 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2865 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2869 if (dst
.regClass() == s1
) {
2870 if (instr
->op
== nir_op_ubfe
)
2871 opcode
= aco_opcode::s_bfe_u32
;
2873 opcode
= aco_opcode::s_bfe_i32
;
2874 } else if (dst
.regClass() == s2
) {
2875 if (instr
->op
== nir_op_ubfe
)
2876 opcode
= aco_opcode::s_bfe_u64
;
2878 opcode
= aco_opcode::s_bfe_i64
;
2880 unreachable("Unsupported BFE bit size");
2883 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2887 if (dst
.regClass() == v1
) {
2888 if (instr
->op
== nir_op_ubfe
)
2889 opcode
= aco_opcode::v_bfe_u32
;
2891 opcode
= aco_opcode::v_bfe_i32
;
2893 unreachable("Unsupported BFE bit size");
2896 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2900 case nir_op_bit_count
: {
2901 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2902 if (src
.regClass() == s1
) {
2903 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2904 } else if (src
.regClass() == v1
) {
2905 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2906 } else if (src
.regClass() == v2
) {
2907 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2908 emit_extract_vector(ctx
, src
, 1, v1
),
2909 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2910 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2911 } else if (src
.regClass() == s2
) {
2912 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2915 nir_print_instr(&instr
->instr
, stderr
);
2916 fprintf(stderr
, "\n");
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2941 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2945 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2946 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2948 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2949 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2953 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2954 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2956 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2957 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2961 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2965 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2970 case nir_op_fddx_fine
:
2971 case nir_op_fddy_fine
:
2972 case nir_op_fddx_coarse
:
2973 case nir_op_fddy_coarse
: {
2974 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2975 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2976 if (instr
->op
== nir_op_fddx_fine
) {
2977 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2978 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2979 } else if (instr
->op
== nir_op_fddy_fine
) {
2980 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2981 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2983 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2984 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2985 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2987 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2991 if (ctx
->program
->chip_class
>= GFX8
) {
2992 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2993 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2995 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2996 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2997 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2999 emit_wqm(ctx
, tmp
, dst
, true);
3003 fprintf(stderr
, "Unknown NIR ALU instr: ");
3004 nir_print_instr(&instr
->instr
, stderr
);
3005 fprintf(stderr
, "\n");
3009 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3011 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3013 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3014 // which get truncated the lsb if double and msb if int
3015 // for now, we only use s_mov_b64 with 64bit inline constants
3016 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3017 assert(dst
.type() == RegType::sgpr
);
3019 Builder
bld(ctx
->program
, ctx
->block
);
3021 if (instr
->def
.bit_size
== 1) {
3022 assert(dst
.regClass() == bld
.lm
);
3023 int val
= instr
->value
[0].b
? -1 : 0;
3024 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3025 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3026 } else if (instr
->def
.bit_size
== 8) {
3027 /* ensure that the value is correctly represented in the low byte of the register */
3028 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3029 } else if (instr
->def
.bit_size
== 16) {
3030 /* ensure that the value is correctly represented in the low half of the register */
3031 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3032 } else if (dst
.size() == 1) {
3033 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3035 assert(dst
.size() != 1);
3036 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3037 if (instr
->def
.bit_size
== 64)
3038 for (unsigned i
= 0; i
< dst
.size(); i
++)
3039 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3041 for (unsigned i
= 0; i
< dst
.size(); i
++)
3042 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3044 vec
->definitions
[0] = Definition(dst
);
3045 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3049 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3051 uint32_t new_mask
= 0;
3052 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3053 if (mask
& (1u << i
))
3054 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3058 struct LoadEmitInfo
{
3061 unsigned num_components
;
3062 unsigned component_size
;
3063 Temp resource
= Temp(0, s1
);
3064 unsigned component_stride
= 0;
3065 unsigned const_offset
= 0;
3066 unsigned align_mul
= 0;
3067 unsigned align_offset
= 0;
3070 unsigned swizzle_component_size
= 0;
3071 barrier_interaction barrier
= barrier_none
;
3072 bool can_reorder
= true;
3073 Temp soffset
= Temp(0, s1
);
3076 using LoadCallback
= Temp(*)(
3077 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3078 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3080 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3081 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3083 unsigned load_size
= info
->num_components
* info
->component_size
;
3084 unsigned component_size
= info
->component_size
;
3086 unsigned num_vals
= 0;
3087 Temp vals
[info
->dst
.bytes()];
3089 unsigned const_offset
= info
->const_offset
;
3091 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3092 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3094 unsigned bytes_read
= 0;
3095 while (bytes_read
< load_size
) {
3096 unsigned bytes_needed
= load_size
- bytes_read
;
3098 /* add buffer for unaligned loads */
3099 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3102 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3103 if (info
->component_stride
) {
3104 assert(supports_8bit_16bit_loads
&& "unimplemented");
3108 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3109 bytes_needed
= align(bytes_needed
, 4);
3116 if (info
->swizzle_component_size
)
3117 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3118 if (info
->component_stride
)
3119 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3121 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3123 /* reduce constant offset */
3124 Operand offset
= info
->offset
;
3125 unsigned reduced_const_offset
= const_offset
;
3126 bool remove_const_offset_completely
= need_to_align_offset
;
3127 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3128 unsigned to_add
= const_offset
;
3129 if (remove_const_offset_completely
) {
3130 reduced_const_offset
= 0;
3132 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3133 reduced_const_offset
%= max_const_offset_plus_one
;
3135 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3136 if (offset
.isConstant()) {
3137 offset
= Operand(offset
.constantValue() + to_add
);
3138 } else if (offset_tmp
.regClass() == s1
) {
3139 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3140 offset_tmp
, Operand(to_add
));
3141 } else if (offset_tmp
.regClass() == v1
) {
3142 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3144 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3145 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3146 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3148 if (offset_tmp
.regClass() == s2
) {
3149 Temp carry
= bld
.tmp(s1
);
3150 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3151 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3152 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3154 Temp new_lo
= bld
.tmp(v1
);
3155 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3156 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3157 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3162 /* align offset down if needed */
3163 Operand aligned_offset
= offset
;
3164 if (need_to_align_offset
) {
3165 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3166 if (offset
.isConstant()) {
3167 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3168 } else if (offset_tmp
.regClass() == s1
) {
3169 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3170 } else if (offset_tmp
.regClass() == s2
) {
3171 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3172 } else if (offset_tmp
.regClass() == v1
) {
3173 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3174 } else if (offset_tmp
.regClass() == v2
) {
3175 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3176 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3177 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3178 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3181 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3182 bld
.copy(bld
.def(s1
), aligned_offset
);
3184 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3185 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3186 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3188 /* the callback wrote directly to dst */
3189 if (val
== info
->dst
) {
3190 assert(num_vals
== 0);
3191 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3195 /* shift result right if needed */
3196 if (info
->component_size
< 4) {
3197 Operand
align((uint32_t)byte_align
);
3198 if (byte_align
== -1) {
3199 if (offset
.isConstant())
3200 align
= Operand(offset
.constantValue() % 4u);
3201 else if (offset
.size() == 2)
3202 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3207 assert(val
.bytes() >= load_size
&& "unimplemented");
3208 if (val
.type() == RegType::sgpr
)
3209 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3211 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3215 /* add result to list and advance */
3216 if (info
->component_stride
) {
3217 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3218 const_offset
+= info
->component_stride
;
3219 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3221 const_offset
+= val
.bytes();
3222 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3224 bytes_read
+= val
.bytes();
3225 vals
[num_vals
++] = val
;
3228 /* create array of components */
3229 unsigned components_split
= 0;
3230 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3231 bool has_vgprs
= false;
3232 for (unsigned i
= 0; i
< num_vals
;) {
3234 unsigned num_tmps
= 0;
3235 unsigned tmp_size
= 0;
3236 RegType reg_type
= RegType::sgpr
;
3237 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3238 if (vals
[i
].type() == RegType::vgpr
)
3239 reg_type
= RegType::vgpr
;
3240 tmp_size
+= vals
[i
].bytes();
3241 tmp
[num_tmps
++] = vals
[i
++];
3244 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3245 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3246 for (unsigned i
= 0; i
< num_vals
; i
++)
3247 vec
->operands
[i
] = Operand(tmp
[i
]);
3248 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3249 vec
->definitions
[0] = Definition(tmp
[0]);
3250 bld
.insert(std::move(vec
));
3253 if (tmp
[0].bytes() % component_size
) {
3255 assert(i
== num_vals
);
3256 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3257 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3260 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3262 unsigned start
= components_split
;
3264 if (tmp_size
== elem_rc
.bytes()) {
3265 allocated_vec
[components_split
++] = tmp
[0];
3267 assert(tmp_size
% elem_rc
.bytes() == 0);
3268 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3269 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3270 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3271 Temp component
= bld
.tmp(elem_rc
);
3272 allocated_vec
[components_split
++] = component
;
3273 split
->definitions
[i
] = Definition(component
);
3275 split
->operands
[0] = Operand(tmp
[0]);
3276 bld
.insert(std::move(split
));
3279 /* try to p_as_uniform early so we can create more optimizable code and
3280 * also update allocated_vec */
3281 for (unsigned j
= start
; j
< components_split
; j
++) {
3282 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3283 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3284 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3288 /* concatenate components and p_as_uniform() result if needed */
3289 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3290 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3292 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3294 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3295 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3296 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3297 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3299 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3300 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3301 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3302 vec
->definitions
[0] = Definition(tmp
);
3303 bld
.insert(std::move(vec
));
3304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3306 vec
->definitions
[0] = Definition(info
->dst
);
3307 bld
.insert(std::move(vec
));
3311 Operand
load_lds_size_m0(Builder
& bld
)
3313 /* TODO: m0 does not need to be initialized on GFX9+ */
3314 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3317 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3318 Temp offset
, unsigned bytes_needed
,
3319 unsigned align
, unsigned const_offset
,
3322 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3324 Operand m
= load_lds_size_m0(bld
);
3326 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3327 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3332 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3333 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3335 op
= aco_opcode::ds_read_b128
;
3336 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3339 op
= aco_opcode::ds_read2_b64
;
3340 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3342 op
= aco_opcode::ds_read_b96
;
3343 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3345 op
= aco_opcode::ds_read_b64
;
3346 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3349 op
= aco_opcode::ds_read2_b32
;
3350 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3352 op
= aco_opcode::ds_read_b32
;
3353 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3355 op
= aco_opcode::ds_read_u16
;
3358 op
= aco_opcode::ds_read_u8
;
3361 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3362 if (const_offset
>= max_offset_plus_one
) {
3363 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3364 const_offset
%= max_offset_plus_one
;
3368 const_offset
/= (size
/ 2u);
3370 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3371 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3373 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3375 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3378 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3383 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3385 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3386 Temp offset
, unsigned bytes_needed
,
3387 unsigned align
, unsigned const_offset
,
3392 if (bytes_needed
<= 4) {
3394 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3395 } else if (bytes_needed
<= 8) {
3397 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3398 } else if (bytes_needed
<= 16) {
3400 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3401 } else if (bytes_needed
<= 32) {
3403 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3406 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3408 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3409 if (info
->resource
.id()) {
3410 load
->operands
[0] = Operand(info
->resource
);
3411 load
->operands
[1] = Operand(offset
);
3413 load
->operands
[0] = Operand(offset
);
3414 load
->operands
[1] = Operand(0u);
3416 RegClass
rc(RegType::sgpr
, size
);
3417 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3418 load
->definitions
[0] = Definition(val
);
3419 load
->glc
= info
->glc
;
3420 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3421 load
->barrier
= info
->barrier
;
3422 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3423 bld
.insert(std::move(load
));
3427 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3429 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3430 Temp offset
, unsigned bytes_needed
,
3431 unsigned align_
, unsigned const_offset
,
3434 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3435 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3437 if (info
->soffset
.id()) {
3438 if (soffset
.isTemp())
3439 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3440 soffset
= Operand(info
->soffset
);
3443 unsigned bytes_size
= 0;
3445 if (bytes_needed
== 1) {
3447 op
= aco_opcode::buffer_load_ubyte
;
3448 } else if (bytes_needed
== 2) {
3450 op
= aco_opcode::buffer_load_ushort
;
3451 } else if (bytes_needed
<= 4) {
3453 op
= aco_opcode::buffer_load_dword
;
3454 } else if (bytes_needed
<= 8) {
3456 op
= aco_opcode::buffer_load_dwordx2
;
3457 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3459 op
= aco_opcode::buffer_load_dwordx3
;
3462 op
= aco_opcode::buffer_load_dwordx4
;
3464 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3465 mubuf
->operands
[0] = Operand(info
->resource
);
3466 mubuf
->operands
[1] = vaddr
;
3467 mubuf
->operands
[2] = soffset
;
3468 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3469 mubuf
->glc
= info
->glc
;
3470 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3471 mubuf
->barrier
= info
->barrier
;
3472 mubuf
->can_reorder
= info
->can_reorder
;
3473 mubuf
->offset
= const_offset
;
3474 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3475 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3476 mubuf
->definitions
[0] = Definition(val
);
3477 bld
.insert(std::move(mubuf
));
3482 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3484 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3486 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3487 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3489 if (addr
.type() == RegType::vgpr
)
3490 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3491 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3494 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3495 Temp offset
, unsigned bytes_needed
,
3496 unsigned align_
, unsigned const_offset
,
3499 unsigned bytes_size
= 0;
3500 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3501 bool global
= bld
.program
->chip_class
>= GFX9
;
3503 if (bytes_needed
== 1) {
3505 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3506 } else if (bytes_needed
== 2) {
3508 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3509 } else if (bytes_needed
<= 4) {
3511 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3512 } else if (bytes_needed
<= 8) {
3514 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3515 } else if (bytes_needed
<= 12 && !mubuf
) {
3517 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3520 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3522 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3523 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3525 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3526 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3527 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3528 mubuf
->operands
[2] = Operand(0u);
3529 mubuf
->glc
= info
->glc
;
3532 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3533 mubuf
->disable_wqm
= false;
3534 mubuf
->barrier
= info
->barrier
;
3535 mubuf
->definitions
[0] = Definition(val
);
3536 bld
.insert(std::move(mubuf
));
3538 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3540 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3541 flat
->operands
[0] = Operand(offset
);
3542 flat
->operands
[1] = Operand(s1
);
3543 flat
->glc
= info
->glc
;
3544 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3545 flat
->barrier
= info
->barrier
;
3547 flat
->definitions
[0] = Definition(val
);
3548 bld
.insert(std::move(flat
));
3554 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3556 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3557 Temp address
, unsigned base_offset
, unsigned align
)
3559 assert(util_is_power_of_two_nonzero(align
));
3561 Builder
bld(ctx
->program
, ctx
->block
);
3563 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3564 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3565 info
.align_mul
= align
;
3566 info
.align_offset
= 0;
3567 info
.barrier
= barrier_shared
;
3568 info
.can_reorder
= false;
3569 info
.const_offset
= base_offset
;
3570 emit_lds_load(ctx
, bld
, &info
);
3575 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3580 Builder
bld(ctx
->program
, ctx
->block
);
3582 ASSERTED
bool is_subdword
= false;
3583 for (unsigned i
= 0; i
< count
; i
++)
3584 is_subdword
|= offsets
[i
] % 4;
3585 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3586 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3588 /* count == 1 fast path */
3590 if (dst_type
== RegType::sgpr
)
3591 dst
[0] = bld
.as_uniform(src
);
3593 dst
[0] = as_vgpr(ctx
, src
);
3597 for (unsigned i
= 0; i
< count
- 1; i
++)
3598 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3599 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3601 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3602 src
= as_vgpr(ctx
, src
);
3604 /* use allocated_vec if possible */
3605 auto it
= ctx
->allocated_vec
.find(src
.id());
3606 if (it
!= ctx
->allocated_vec
.end()) {
3607 unsigned total_size
= 0;
3608 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3609 total_size
+= it
->second
[i
].bytes();
3610 if (total_size
!= src
.bytes())
3613 unsigned elem_size
= it
->second
[0].bytes();
3615 for (unsigned i
= 0; i
< count
; i
++) {
3616 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3620 for (unsigned i
= 0; i
< count
; i
++) {
3621 unsigned start_idx
= offsets
[i
] / elem_size
;
3622 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3623 if (op_count
== 1) {
3624 if (dst_type
== RegType::sgpr
)
3625 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3627 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3631 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3632 for (unsigned j
= 0; j
< op_count
; j
++) {
3633 Temp tmp
= it
->second
[start_idx
+ j
];
3634 if (dst_type
== RegType::sgpr
)
3635 tmp
= bld
.as_uniform(tmp
);
3636 vec
->operands
[j
] = Operand(tmp
);
3638 vec
->definitions
[0] = Definition(dst
[i
]);
3639 bld
.insert(std::move(vec
));
3645 if (dst_type
== RegType::sgpr
)
3646 src
= bld
.as_uniform(src
);
3650 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3651 split
->operands
[0] = Operand(src
);
3652 for (unsigned i
= 0; i
< count
; i
++)
3653 split
->definitions
[i
] = Definition(dst
[i
]);
3654 bld
.insert(std::move(split
));
3657 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3658 int *start
, int *count
)
3660 unsigned start_elem
= ffs(todo_mask
) - 1;
3661 bool skip
= !(mask
& (1 << start_elem
));
3663 mask
= ~mask
& todo_mask
;
3667 u_bit_scan_consecutive_range(&mask
, start
, count
);
3672 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3674 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3677 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3678 Temp address
, unsigned base_offset
, unsigned align
)
3680 assert(util_is_power_of_two_nonzero(align
));
3681 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3683 Builder
bld(ctx
->program
, ctx
->block
);
3684 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3685 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3687 unsigned write_count
= 0;
3688 Temp write_datas
[32];
3689 unsigned offsets
[32];
3690 aco_opcode opcodes
[32];
3692 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3694 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3697 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3698 offsets
[write_count
] = offset
;
3699 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3701 advance_write_mask(&todo
, offset
, bytes
);
3705 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3706 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3707 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3708 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3710 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3711 aco_opcode op
= aco_opcode::num_opcodes
;
3712 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3713 op
= aco_opcode::ds_write_b128
;
3715 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3716 op
= aco_opcode::ds_write_b96
;
3718 } else if (bytes
>= 8 && aligned8
) {
3719 op
= aco_opcode::ds_write_b64
;
3721 } else if (bytes
>= 4 && aligned4
) {
3722 op
= aco_opcode::ds_write_b32
;
3724 } else if (bytes
>= 2 && aligned2
) {
3725 op
= aco_opcode::ds_write_b16
;
3727 } else if (bytes
>= 1) {
3728 op
= aco_opcode::ds_write_b8
;
3734 offsets
[write_count
] = offset
;
3735 opcodes
[write_count
] = op
;
3737 advance_write_mask(&todo
, offset
, bytes
);
3740 Operand m
= load_lds_size_m0(bld
);
3742 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3744 for (unsigned i
= 0; i
< write_count
; i
++) {
3745 aco_opcode op
= opcodes
[i
];
3746 if (op
== aco_opcode::num_opcodes
)
3749 Temp data
= write_datas
[i
];
3751 unsigned second
= write_count
;
3752 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3753 for (second
= i
+ 1; second
< write_count
; second
++) {
3754 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3755 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3756 opcodes
[second
] = aco_opcode::num_opcodes
;
3762 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3763 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3765 unsigned inline_offset
= base_offset
+ offsets
[i
];
3766 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3767 Temp address_offset
= address
;
3768 if (inline_offset
> max_offset
) {
3769 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3770 inline_offset
= offsets
[i
];
3772 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3775 Temp second_data
= write_datas
[second
];
3776 inline_offset
/= data
.bytes();
3777 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3779 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3784 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3786 unsigned align
= 16;
3788 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3794 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3799 return aco_opcode::buffer_store_byte
;
3802 return aco_opcode::buffer_store_short
;
3804 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3806 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3809 return aco_opcode::buffer_store_dwordx3
;
3811 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3813 unreachable("Unexpected store size");
3814 return aco_opcode::num_opcodes
;
3817 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3818 Temp data
, unsigned writemask
, int swizzle_element_size
,
3819 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3821 unsigned write_count_with_skips
= 0;
3824 /* determine how to split the data */
3825 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3828 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3829 offsets
[write_count_with_skips
] = offset
;
3830 if (skips
[write_count_with_skips
]) {
3831 advance_write_mask(&todo
, offset
, bytes
);
3832 write_count_with_skips
++;
3836 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3837 * larger than swizzle_element_size */
3838 bytes
= MIN2(bytes
, swizzle_element_size
);
3840 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3842 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3843 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3846 /* dword or larger stores have to be dword-aligned */
3847 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3848 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3849 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3850 if (bytes
>= 4 && !dword_aligned
)
3851 bytes
= MIN2(bytes
, 2);
3853 advance_write_mask(&todo
, offset
, bytes
);
3854 write_count_with_skips
++;
3857 /* actually split data */
3858 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3861 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3864 write_datas
[*write_count
] = write_datas
[i
];
3865 offsets
[*write_count
] = offsets
[i
];
3870 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3871 unsigned split_cnt
= 0u, Temp dst
= Temp())
3873 Builder
bld(ctx
->program
, ctx
->block
);
3874 unsigned dword_size
= elem_size_bytes
/ 4;
3877 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3879 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3880 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3881 instr
->definitions
[0] = Definition(dst
);
3883 for (unsigned i
= 0; i
< cnt
; ++i
) {
3885 assert(arr
[i
].size() == dword_size
);
3886 allocated_vec
[i
] = arr
[i
];
3887 instr
->operands
[i
] = Operand(arr
[i
]);
3889 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3890 allocated_vec
[i
] = zero
;
3891 instr
->operands
[i
] = Operand(zero
);
3895 bld
.insert(std::move(instr
));
3898 emit_split_vector(ctx
, dst
, split_cnt
);
3900 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3905 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3907 if (const_offset
>= 4096) {
3908 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3909 const_offset
%= 4096u;
3912 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3913 else if (unlikely(voffset
.regClass() == s1
))
3914 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3915 else if (likely(voffset
.regClass() == v1
))
3916 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3918 unreachable("Unsupported register class of voffset");
3921 return const_offset
;
3924 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3925 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3928 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3929 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3931 Builder
bld(ctx
->program
, ctx
->block
);
3932 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3933 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3935 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3936 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3937 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3938 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3939 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3941 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3944 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3945 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3946 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3948 Builder
bld(ctx
->program
, ctx
->block
);
3949 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3951 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3953 unsigned write_count
= 0;
3954 Temp write_datas
[32];
3955 unsigned offsets
[32];
3956 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3957 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3959 for (unsigned i
= 0; i
< write_count
; i
++) {
3960 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3961 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3965 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3966 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3967 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3969 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3970 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3971 assert(!!stride
!= allow_combining
);
3973 Builder
bld(ctx
->program
, ctx
->block
);
3975 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3976 info
.component_stride
= allow_combining
? 0 : stride
;
3978 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3979 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3980 info
.align_offset
= 0;
3981 info
.soffset
= soffset
;
3982 info
.const_offset
= base_const_offset
;
3983 emit_mubuf_load(ctx
, bld
, &info
);
3986 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3988 Builder
bld(ctx
->program
, ctx
->block
);
3989 Temp offset
= base_offset
.first
;
3990 unsigned const_offset
= base_offset
.second
;
3992 if (!nir_src_is_const(*off_src
)) {
3993 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3996 /* Calculate indirect offset with stride */
3997 if (likely(indirect_offset_arg
.regClass() == v1
))
3998 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3999 else if (indirect_offset_arg
.regClass() == s1
)
4000 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4002 unreachable("Unsupported register class of indirect offset");
4004 /* Add to the supplied base offset */
4005 if (offset
.id() == 0)
4006 offset
= with_stride
;
4007 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4008 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4009 else if (offset
.size() == 1 && with_stride
.size() == 1)
4010 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4012 unreachable("Unsupported register class of indirect offset");
4014 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4015 const_offset
+= const_offset_arg
* stride
;
4018 return std::make_pair(offset
, const_offset
);
4021 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4023 Builder
bld(ctx
->program
, ctx
->block
);
4026 if (off1
.first
.id() && off2
.first
.id()) {
4027 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4028 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4029 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4030 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4032 unreachable("Unsupported register class of indirect offset");
4034 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4037 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4040 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4042 Builder
bld(ctx
->program
, ctx
->block
);
4043 unsigned const_offset
= offs
.second
* multiplier
;
4045 if (!offs
.first
.id())
4046 return std::make_pair(offs
.first
, const_offset
);
4048 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4049 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4050 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4052 return std::make_pair(offset
, const_offset
);
4055 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4057 Builder
bld(ctx
->program
, ctx
->block
);
4059 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4060 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4061 /* component is in bytes */
4062 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4064 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4065 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4066 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4069 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4071 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4074 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4076 Builder
bld(ctx
->program
, ctx
->block
);
4078 switch (ctx
->shader
->info
.stage
) {
4079 case MESA_SHADER_TESS_CTRL
:
4080 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4081 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4082 case MESA_SHADER_TESS_EVAL
:
4083 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4085 unreachable("Unsupported stage in get_tess_rel_patch_id");
4089 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4091 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4092 Builder
bld(ctx
->program
, ctx
->block
);
4094 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4095 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4097 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4099 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4100 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4102 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4103 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4104 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4106 return offset_mul(ctx
, offs
, 4u);
4109 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4111 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4112 Builder
bld(ctx
->program
, ctx
->block
);
4114 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4115 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4116 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4117 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4119 std::pair
<Temp
, unsigned> offs
= instr
4120 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4121 : std::make_pair(Temp(), 0u);
4123 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4124 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4129 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4130 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4132 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4133 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4135 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4136 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4142 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4144 Builder
bld(ctx
->program
, ctx
->block
);
4146 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4147 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4149 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4151 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4152 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4153 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4155 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4156 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4161 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4163 Builder
bld(ctx
->program
, ctx
->block
);
4165 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4166 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4167 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4168 unsigned attr_stride
= ctx
->tcs_num_patches
;
4170 std::pair
<Temp
, unsigned> offs
= instr
4171 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4172 : std::make_pair(Temp(), 0u);
4174 if (const_base_offset
)
4175 offs
.second
+= const_base_offset
* attr_stride
;
4177 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4178 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4179 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4184 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4186 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4191 unsigned drv_loc
= nir_intrinsic_base(instr
);
4192 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4194 if (!nir_src_is_const(*off_src
)) {
4200 uint64_t slot
= per_vertex
4201 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4202 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4203 return (((uint64_t) 1) << slot
) & mask
;
4206 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4208 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4209 unsigned component
= nir_intrinsic_component(instr
);
4210 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4212 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4213 if (off_instr
->type
!= nir_instr_type_load_const
)
4216 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4217 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4219 if (instr
->src
[0].ssa
->bit_size
== 64)
4220 write_mask
= widen_mask(write_mask
, 2);
4222 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4224 for (unsigned i
= 0; i
< 8; ++i
) {
4225 if (write_mask
& (1 << i
)) {
4226 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4227 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4235 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4237 /* Only TCS per-vertex inputs are supported by this function.
4238 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4240 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4243 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4244 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4245 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4246 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4247 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4248 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4253 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4254 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4255 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4260 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4262 Builder
bld(ctx
->program
, ctx
->block
);
4264 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4265 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4266 bool indirect_write
;
4267 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4268 if (temp_only_input
&& !indirect_write
)
4272 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4273 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4274 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4275 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4277 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4278 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4279 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4280 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4281 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4285 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4286 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4287 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4288 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4289 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4290 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4291 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4292 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4293 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4294 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4295 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4296 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4297 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4299 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4300 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4302 unreachable("Invalid LS or ES stage");
4305 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4306 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4307 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4311 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4316 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4317 return off
== ctx
->tcs_tess_lvl_out_loc
||
4318 off
== ctx
->tcs_tess_lvl_in_loc
;
4322 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4324 uint64_t mask
= per_vertex
4325 ? ctx
->program
->info
->tcs
.tes_inputs_read
4326 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4328 bool indirect_write
= false;
4329 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4330 return indirect_write
|| output_read_by_tes
;
4333 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4335 uint64_t mask
= per_vertex
4336 ? ctx
->shader
->info
.outputs_read
4337 : ctx
->shader
->info
.patch_outputs_read
;
4339 bool indirect_write
= false;
4340 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4341 return indirect_write
|| output_read
;
4344 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4346 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4347 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4349 Builder
bld(ctx
->program
, ctx
->block
);
4351 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4352 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4353 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4355 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4356 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4357 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4359 if (write_to_vmem
) {
4360 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4361 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4362 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4364 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4365 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4366 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4370 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4371 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4372 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4376 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4378 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4379 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4381 Builder
bld(ctx
->program
, ctx
->block
);
4383 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4384 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4385 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4386 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4388 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4391 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4393 if (ctx
->stage
== vertex_vs
||
4394 ctx
->stage
== tess_eval_vs
||
4395 ctx
->stage
== fragment_fs
||
4396 ctx
->stage
== ngg_vertex_gs
||
4397 ctx
->stage
== ngg_tess_eval_gs
||
4398 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4399 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4400 if (!stored_to_temps
) {
4401 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4402 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4403 fprintf(stderr
, "\n");
4406 } else if (ctx
->stage
== vertex_es
||
4407 ctx
->stage
== vertex_ls
||
4408 ctx
->stage
== tess_eval_es
||
4409 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4410 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4411 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4412 visit_store_ls_or_es_output(ctx
, instr
);
4413 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4414 visit_store_tcs_output(ctx
, instr
, false);
4416 unreachable("Shader stage not implemented");
4420 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4422 visit_load_tcs_output(ctx
, instr
, false);
4425 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4427 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4428 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4430 Builder
bld(ctx
->program
, ctx
->block
);
4432 if (dst
.regClass() == v2b
) {
4433 if (ctx
->program
->has_16bank_lds
) {
4434 assert(ctx
->options
->chip_class
<= GFX8
);
4435 Builder::Result interp_p1
=
4436 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4437 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4438 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4439 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4440 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4441 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4443 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4445 if (ctx
->options
->chip_class
== GFX8
)
4446 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4448 Builder::Result interp_p1
=
4449 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4450 coord1
, bld
.m0(prim_mask
), idx
, component
);
4451 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4452 interp_p1
, idx
, component
);
4455 Builder::Result interp_p1
=
4456 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4457 bld
.m0(prim_mask
), idx
, component
);
4459 if (ctx
->program
->has_16bank_lds
)
4460 interp_p1
.instr
->operands
[0].setLateKill(true);
4462 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4463 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4467 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4469 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4470 for (unsigned i
= 0; i
< num_components
; i
++)
4471 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4472 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4473 assert(num_components
== 4);
4474 Builder
bld(ctx
->program
, ctx
->block
);
4475 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4478 for (Operand
& op
: vec
->operands
)
4479 op
= op
.isUndefined() ? Operand(0u) : op
;
4481 vec
->definitions
[0] = Definition(dst
);
4482 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4483 emit_split_vector(ctx
, dst
, num_components
);
4487 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4489 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4490 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4491 unsigned idx
= nir_intrinsic_base(instr
);
4492 unsigned component
= nir_intrinsic_component(instr
);
4493 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4495 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4497 assert(offset
->u32
== 0);
4499 /* the lower 15bit of the prim_mask contain the offset into LDS
4500 * while the upper bits contain the number of prims */
4501 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4502 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4503 Builder
bld(ctx
->program
, ctx
->block
);
4504 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4505 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4506 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4507 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4508 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4511 if (instr
->dest
.ssa
.num_components
== 1) {
4512 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4514 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4515 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4517 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4518 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4519 vec
->operands
[i
] = Operand(tmp
);
4521 vec
->definitions
[0] = Definition(dst
);
4522 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4526 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4527 unsigned offset
, unsigned stride
, unsigned channels
)
4529 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4530 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4532 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4533 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4536 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4537 unsigned offset
, unsigned stride
, unsigned *channels
)
4539 if (!vtx_info
->chan_byte_size
) {
4540 *channels
= vtx_info
->num_channels
;
4541 return vtx_info
->chan_format
;
4544 unsigned num_channels
= *channels
;
4545 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4546 unsigned new_channels
= num_channels
+ 1;
4547 /* first, assume more loads is worse and try using a larger data format */
4548 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4550 /* don't make the attribute potentially out-of-bounds */
4551 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4555 if (new_channels
== 5) {
4556 /* then try decreasing load size (at the cost of more loads) */
4557 new_channels
= *channels
;
4558 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4562 if (new_channels
< *channels
)
4563 *channels
= new_channels
;
4564 num_channels
= new_channels
;
4567 switch (vtx_info
->chan_format
) {
4568 case V_008F0C_BUF_DATA_FORMAT_8
:
4569 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4570 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4571 case V_008F0C_BUF_DATA_FORMAT_16
:
4572 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4573 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4574 case V_008F0C_BUF_DATA_FORMAT_32
:
4575 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4576 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4578 unreachable("shouldn't reach here");
4579 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4582 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4583 * so we may need to fix it up. */
4584 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4586 Builder
bld(ctx
->program
, ctx
->block
);
4588 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4589 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4591 /* For the integer-like cases, do a natural sign extension.
4593 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4594 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4597 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4598 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4600 /* Convert back to the right type. */
4601 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4602 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4603 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4604 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4605 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4606 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4612 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4614 Builder
bld(ctx
->program
, ctx
->block
);
4615 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4616 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4618 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4619 if (off_instr
->type
!= nir_instr_type_load_const
) {
4620 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4621 nir_print_instr(off_instr
, stderr
);
4622 fprintf(stderr
, "\n");
4624 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4626 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4628 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4629 unsigned component
= nir_intrinsic_component(instr
);
4630 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4631 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4632 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4633 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4634 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4636 unsigned dfmt
= attrib_format
& 0xf;
4637 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4638 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4640 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4641 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4642 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4643 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4645 num_channels
= MAX2(num_channels
, 3);
4647 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4648 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4651 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4652 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4653 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4655 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4657 Temp divided
= bld
.tmp(v1
);
4658 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4659 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4661 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4664 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4667 index
= bld
.vadd32(bld
.def(v1
),
4668 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4669 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4672 Temp channels
[num_channels
];
4673 unsigned channel_start
= 0;
4674 bool direct_fetch
= false;
4676 /* skip unused channels at the start */
4677 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4678 channel_start
= ffs(mask
) - 1;
4679 for (unsigned i
= 0; i
< channel_start
; i
++)
4680 channels
[i
] = Temp(0, s1
);
4681 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4682 num_channels
= 3 - (ffs(mask
) - 1);
4686 while (channel_start
< num_channels
) {
4687 unsigned fetch_component
= num_channels
- channel_start
;
4688 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4689 bool expanded
= false;
4691 /* use MUBUF when possible to avoid possible alignment issues */
4692 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4693 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4694 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4695 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4696 vtx_info
->chan_byte_size
== 4;
4697 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4699 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4701 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4702 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4703 fetch_component
= 4;
4708 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4710 Temp fetch_index
= index
;
4711 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4712 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4713 fetch_offset
= fetch_offset
% attrib_stride
;
4716 Operand
soffset(0u);
4717 if (fetch_offset
>= 4096) {
4718 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4719 fetch_offset
%= 4096;
4723 switch (fetch_bytes
) {
4725 assert(!use_mubuf
&& bitsize
== 16);
4726 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4729 if (bitsize
== 16) {
4731 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4733 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4737 assert(!use_mubuf
&& bitsize
== 16);
4738 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4741 if (bitsize
== 16) {
4743 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4745 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4749 assert(ctx
->options
->chip_class
>= GFX7
||
4750 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4751 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4754 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4757 unreachable("Unimplemented load_input vector size");
4761 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4762 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4763 num_channels
<= 3)) {
4764 direct_fetch
= true;
4767 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4771 Instruction
*mubuf
= bld
.mubuf(opcode
,
4772 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4773 fetch_offset
, false, true).instr
;
4774 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4776 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4777 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4778 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4779 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4782 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4784 if (fetch_component
== 1) {
4785 channels
[channel_start
] = fetch_dst
;
4787 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4788 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4789 bitsize
== 16 ? v2b
: v1
);
4792 channel_start
+= fetch_component
;
4795 if (!direct_fetch
) {
4796 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4797 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4799 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4800 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4801 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4803 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4804 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4805 unsigned num_temp
= 0;
4806 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4807 unsigned idx
= i
+ component
;
4808 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4809 Temp channel
= channels
[swizzle
[idx
]];
4810 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4811 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4812 vec
->operands
[i
] = Operand(channel
);
4816 } else if (is_float
&& idx
== 3) {
4817 vec
->operands
[i
] = Operand(0x3f800000u
);
4818 } else if (!is_float
&& idx
== 3) {
4819 vec
->operands
[i
] = Operand(1u);
4821 vec
->operands
[i
] = Operand(0u);
4824 vec
->definitions
[0] = Definition(dst
);
4825 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4826 emit_split_vector(ctx
, dst
, dst
.size());
4828 if (num_temp
== dst
.size())
4829 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4831 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4832 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4833 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4834 if (off_instr
->type
!= nir_instr_type_load_const
||
4835 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4836 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4837 nir_print_instr(off_instr
, stderr
);
4838 fprintf(stderr
, "\n");
4841 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4842 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4844 assert(offset
->u32
== 0);
4846 /* the lower 15bit of the prim_mask contain the offset into LDS
4847 * while the upper bits contain the number of prims */
4848 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4849 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4850 Builder
bld(ctx
->program
, ctx
->block
);
4851 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4852 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4853 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4854 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4855 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4858 unsigned idx
= nir_intrinsic_base(instr
);
4859 unsigned component
= nir_intrinsic_component(instr
);
4860 unsigned vertex_id
= 2; /* P0 */
4862 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4863 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4864 switch (src0
->u32
) {
4866 vertex_id
= 2; /* P0 */
4869 vertex_id
= 0; /* P10 */
4872 vertex_id
= 1; /* P20 */
4875 unreachable("invalid vertex index");
4879 if (dst
.size() == 1) {
4880 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4882 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4883 for (unsigned i
= 0; i
< dst
.size(); i
++)
4884 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4885 vec
->definitions
[0] = Definition(dst
);
4886 bld
.insert(std::move(vec
));
4889 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4890 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4891 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4892 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4893 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4895 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4897 unreachable("Shader stage not implemented");
4901 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4903 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4905 Builder
bld(ctx
->program
, ctx
->block
);
4906 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4909 if (!nir_src_is_const(*vertex_src
)) {
4910 /* better code could be created, but this case probably doesn't happen
4911 * much in practice */
4912 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4913 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4916 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4917 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4919 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4921 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4924 if (vertex_offset
.id()) {
4925 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4926 Operand(i
), indirect_vertex
);
4927 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4929 vertex_offset
= elem
;
4933 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4934 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4936 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4937 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4938 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4939 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4940 Operand((vertex
% 2u) * 16u), Operand(16u));
4942 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4945 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4946 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4947 return offset_mul(ctx
, offs
, 4u);
4950 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4952 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4954 Builder
bld(ctx
->program
, ctx
->block
);
4955 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4956 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4958 if (ctx
->stage
== geometry_gs
) {
4959 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4960 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4961 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4962 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4963 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4964 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4965 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4967 unreachable("Unsupported GS stage.");
4971 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4973 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4975 Builder
bld(ctx
->program
, ctx
->block
);
4976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4978 if (load_input_from_temps(ctx
, instr
, dst
))
4981 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4982 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4983 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4985 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4988 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4990 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4992 Builder
bld(ctx
->program
, ctx
->block
);
4994 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4995 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4996 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4998 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4999 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5001 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5004 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5006 switch (ctx
->shader
->info
.stage
) {
5007 case MESA_SHADER_GEOMETRY
:
5008 visit_load_gs_per_vertex_input(ctx
, instr
);
5010 case MESA_SHADER_TESS_CTRL
:
5011 visit_load_tcs_per_vertex_input(ctx
, instr
);
5013 case MESA_SHADER_TESS_EVAL
:
5014 visit_load_tes_per_vertex_input(ctx
, instr
);
5017 unreachable("Unimplemented shader stage");
5021 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5023 visit_load_tcs_output(ctx
, instr
, true);
5026 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5028 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5029 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5031 visit_store_tcs_output(ctx
, instr
, true);
5034 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5036 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5038 Builder
bld(ctx
->program
, ctx
->block
);
5039 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5041 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5042 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5045 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5046 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5047 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5048 tes_w
= Operand(tmp
);
5051 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5052 emit_split_vector(ctx
, tess_coord
, 3);
5055 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5057 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5058 Builder
bld(ctx
->program
, ctx
->block
);
5059 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5060 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5061 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5064 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5068 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5070 Builder
bld(ctx
->program
, ctx
->block
);
5071 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5072 if (!nir_dest_is_divergent(instr
->dest
))
5073 index
= bld
.as_uniform(index
);
5074 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5075 unsigned binding
= nir_intrinsic_binding(instr
);
5078 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5079 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5080 unsigned offset
= layout
->binding
[binding
].offset
;
5082 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5083 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5084 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5085 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5086 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5089 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5090 stride
= layout
->binding
[binding
].size
;
5093 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5094 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5096 if (nir_const_index
) {
5097 const_index
= const_index
* stride
;
5098 } else if (index
.type() == RegType::vgpr
) {
5099 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5100 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5102 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5106 if (nir_const_index
) {
5107 const_index
= const_index
+ offset
;
5108 } else if (index
.type() == RegType::vgpr
) {
5109 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5111 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5115 if (nir_const_index
&& const_index
== 0) {
5117 } else if (index
.type() == RegType::vgpr
) {
5118 index
= bld
.vadd32(bld
.def(v1
),
5119 nir_const_index
? Operand(const_index
) : Operand(index
),
5122 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5123 nir_const_index
? Operand(const_index
) : Operand(index
),
5127 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5130 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5131 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5132 bool glc
=false, bool readonly
=true)
5134 Builder
bld(ctx
->program
, ctx
->block
);
5136 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5138 offset
= bld
.as_uniform(offset
);
5140 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5142 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5143 info
.can_reorder
= readonly
;
5144 info
.align_mul
= align_mul
;
5145 info
.align_offset
= align_offset
;
5147 emit_smem_load(ctx
, bld
, &info
);
5149 emit_mubuf_load(ctx
, bld
, &info
);
5152 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5154 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5155 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5157 Builder
bld(ctx
->program
, ctx
->block
);
5159 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5160 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5161 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5162 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5164 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5165 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5166 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5167 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5168 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5169 if (ctx
->options
->chip_class
>= GFX10
) {
5170 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5171 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5172 S_008F0C_RESOURCE_LEVEL(1);
5174 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5175 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5177 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5178 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5179 Operand(0xFFFFFFFFu
),
5180 Operand(desc_type
));
5181 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5182 rsrc
, upper_dwords
);
5184 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5185 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5187 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5188 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5189 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5192 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5194 Builder
bld(ctx
->program
, ctx
->block
);
5195 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5196 unsigned offset
= nir_intrinsic_base(instr
);
5197 unsigned count
= instr
->dest
.ssa
.num_components
;
5198 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5200 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5201 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5202 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5203 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5204 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5205 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5206 for (unsigned i
= 0; i
< count
; ++i
) {
5207 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5208 vec
->operands
[i
] = Operand
{elems
[i
]};
5210 vec
->definitions
[0] = Definition(dst
);
5211 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5212 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5217 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5218 if (offset
!= 0) // TODO check if index != 0 as well
5219 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5220 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5223 bool aligned
= true;
5225 if (instr
->dest
.ssa
.bit_size
== 8) {
5226 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5227 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5229 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5230 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5231 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5233 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5238 switch (vec
.size()) {
5240 op
= aco_opcode::s_load_dword
;
5243 op
= aco_opcode::s_load_dwordx2
;
5249 op
= aco_opcode::s_load_dwordx4
;
5255 op
= aco_opcode::s_load_dwordx8
;
5258 unreachable("unimplemented or forbidden load_push_constant.");
5261 bld
.smem(op
, Definition(vec
), ptr
, index
);
5264 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5265 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5270 emit_split_vector(ctx
, vec
, 4);
5271 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5272 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5273 emit_extract_vector(ctx
, vec
, 0, rc
),
5274 emit_extract_vector(ctx
, vec
, 1, rc
),
5275 emit_extract_vector(ctx
, vec
, 2, rc
));
5278 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5281 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5283 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5285 Builder
bld(ctx
->program
, ctx
->block
);
5287 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5288 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5289 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5290 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5291 if (ctx
->options
->chip_class
>= GFX10
) {
5292 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5293 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5294 S_008F0C_RESOURCE_LEVEL(1);
5296 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5297 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5300 unsigned base
= nir_intrinsic_base(instr
);
5301 unsigned range
= nir_intrinsic_range(instr
);
5303 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5304 if (base
&& offset
.type() == RegType::sgpr
)
5305 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5306 else if (base
&& offset
.type() == RegType::vgpr
)
5307 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5309 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5310 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5311 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5312 Operand(desc_type
));
5313 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5314 // TODO: get alignment information for subdword constants
5315 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5318 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5320 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5321 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5323 ctx
->program
->needs_exact
= true;
5325 // TODO: optimize uniform conditions
5326 Builder
bld(ctx
->program
, ctx
->block
);
5327 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5328 assert(src
.regClass() == bld
.lm
);
5329 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5330 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5331 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5335 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5337 Builder
bld(ctx
->program
, ctx
->block
);
5339 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5340 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5342 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5343 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5345 if (ctx
->block
->loop_nest_depth
&&
5346 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5347 /* we handle discards the same way as jump instructions */
5348 append_logical_end(ctx
->block
);
5350 /* in loops, discard behaves like break */
5351 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5352 ctx
->block
->kind
|= block_kind_discard
;
5355 /* uniform discard - loop ends here */
5356 assert(nir_instr_is_last(&instr
->instr
));
5357 ctx
->block
->kind
|= block_kind_uniform
;
5358 ctx
->cf_info
.has_branch
= true;
5359 bld
.branch(aco_opcode::p_branch
);
5360 add_linear_edge(ctx
->block
->index
, linear_target
);
5364 /* we add a break right behind the discard() instructions */
5365 ctx
->block
->kind
|= block_kind_break
;
5366 unsigned idx
= ctx
->block
->index
;
5368 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5369 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5371 /* remove critical edges from linear CFG */
5372 bld
.branch(aco_opcode::p_branch
);
5373 Block
* break_block
= ctx
->program
->create_and_insert_block();
5374 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5375 break_block
->kind
|= block_kind_uniform
;
5376 add_linear_edge(idx
, break_block
);
5377 add_linear_edge(break_block
->index
, linear_target
);
5378 bld
.reset(break_block
);
5379 bld
.branch(aco_opcode::p_branch
);
5381 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5382 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5383 add_linear_edge(idx
, continue_block
);
5384 append_logical_start(continue_block
);
5385 ctx
->block
= continue_block
;
5390 /* it can currently happen that NIR doesn't remove the unreachable code */
5391 if (!nir_instr_is_last(&instr
->instr
)) {
5392 ctx
->program
->needs_exact
= true;
5393 /* save exec somewhere temporarily so that it doesn't get
5394 * overwritten before the discard from outer exec masks */
5395 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5396 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5397 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5401 /* This condition is incorrect for uniformly branched discards in a loop
5402 * predicated by a divergent condition, but the above code catches that case
5403 * and the discard would end up turning into a discard_if.
5413 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5414 /* program just ends here */
5415 ctx
->block
->kind
|= block_kind_uniform
;
5416 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5417 0 /* enabled mask */, 9 /* dest */,
5418 false /* compressed */, true/* done */, true /* valid mask */);
5419 bld
.sopp(aco_opcode::s_endpgm
);
5420 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5422 ctx
->block
->kind
|= block_kind_discard
;
5423 /* branch and linear edge is added by visit_if() */
5427 enum aco_descriptor_type
{
5438 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5439 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5441 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5442 return dim
== ac_image_cube
||
5443 dim
== ac_image_1darray
||
5444 dim
== ac_image_2darray
||
5445 dim
== ac_image_2darraymsaa
;
5448 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5449 enum aco_descriptor_type desc_type
,
5450 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5452 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5453 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5454 if (it != ctx->tex_desc.end())
5457 Temp index
= Temp();
5458 bool index_set
= false;
5459 unsigned constant_index
= 0;
5460 unsigned descriptor_set
;
5461 unsigned base_index
;
5462 Builder
bld(ctx
->program
, ctx
->block
);
5465 assert(tex_instr
&& !image
);
5467 base_index
= tex_instr
->sampler_index
;
5469 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5470 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5474 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5475 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5477 constant_index
+= array_size
* const_value
->u32
;
5479 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5480 if (indirect
.type() == RegType::vgpr
)
5481 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5483 if (array_size
!= 1)
5484 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5490 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5494 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5496 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5497 base_index
= deref_instr
->var
->data
.binding
;
5500 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5501 list
= convert_pointer_to_64_bit(ctx
, list
);
5503 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5504 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5505 unsigned offset
= binding
->offset
;
5506 unsigned stride
= binding
->size
;
5510 assert(base_index
< layout
->binding_count
);
5512 switch (desc_type
) {
5513 case ACO_DESC_IMAGE
:
5515 opcode
= aco_opcode::s_load_dwordx8
;
5517 case ACO_DESC_FMASK
:
5519 opcode
= aco_opcode::s_load_dwordx8
;
5522 case ACO_DESC_SAMPLER
:
5524 opcode
= aco_opcode::s_load_dwordx4
;
5525 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5526 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5528 case ACO_DESC_BUFFER
:
5530 opcode
= aco_opcode::s_load_dwordx4
;
5532 case ACO_DESC_PLANE_0
:
5533 case ACO_DESC_PLANE_1
:
5535 opcode
= aco_opcode::s_load_dwordx8
;
5536 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5538 case ACO_DESC_PLANE_2
:
5540 opcode
= aco_opcode::s_load_dwordx4
;
5544 unreachable("invalid desc_type\n");
5547 offset
+= constant_index
* stride
;
5549 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5550 (!index_set
|| binding
->immutable_samplers_equal
)) {
5551 if (binding
->immutable_samplers_equal
)
5554 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5555 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5556 Operand(samplers
[constant_index
* 4 + 0]),
5557 Operand(samplers
[constant_index
* 4 + 1]),
5558 Operand(samplers
[constant_index
* 4 + 2]),
5559 Operand(samplers
[constant_index
* 4 + 3]));
5564 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5566 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5567 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5570 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5572 if (desc_type
== ACO_DESC_PLANE_2
) {
5574 for (unsigned i
= 0; i
< 8; i
++)
5575 components
[i
] = bld
.tmp(s1
);
5576 bld
.pseudo(aco_opcode::p_split_vector
,
5577 Definition(components
[0]),
5578 Definition(components
[1]),
5579 Definition(components
[2]),
5580 Definition(components
[3]),
5583 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5584 bld
.pseudo(aco_opcode::p_split_vector
,
5585 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5586 Definition(components
[4]),
5587 Definition(components
[5]),
5588 Definition(components
[6]),
5589 Definition(components
[7]),
5592 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5593 components
[0], components
[1], components
[2], components
[3],
5594 components
[4], components
[5], components
[6], components
[7]);
5600 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5603 case GLSL_SAMPLER_DIM_BUF
:
5605 case GLSL_SAMPLER_DIM_1D
:
5606 return array
? 2 : 1;
5607 case GLSL_SAMPLER_DIM_2D
:
5608 return array
? 3 : 2;
5609 case GLSL_SAMPLER_DIM_MS
:
5610 return array
? 4 : 3;
5611 case GLSL_SAMPLER_DIM_3D
:
5612 case GLSL_SAMPLER_DIM_CUBE
:
5614 case GLSL_SAMPLER_DIM_RECT
:
5615 case GLSL_SAMPLER_DIM_SUBPASS
:
5617 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5626 /* Adjust the sample index according to FMASK.
5628 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5629 * which is the identity mapping. Each nibble says which physical sample
5630 * should be fetched to get that sample.
5632 * For example, 0x11111100 means there are only 2 samples stored and
5633 * the second sample covers 3/4 of the pixel. When reading samples 0
5634 * and 1, return physical sample 0 (determined by the first two 0s
5635 * in FMASK), otherwise return physical sample 1.
5637 * The sample index should be adjusted as follows:
5638 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5640 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5642 Builder
bld(ctx
->program
, ctx
->block
);
5643 Temp fmask
= bld
.tmp(v1
);
5644 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5645 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5648 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5649 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5650 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5651 load
->operands
[0] = Operand(fmask_desc_ptr
);
5652 load
->operands
[1] = Operand(s4
); /* no sampler */
5653 load
->operands
[2] = Operand(coord
);
5654 load
->definitions
[0] = Definition(fmask
);
5661 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5662 ctx
->block
->instructions
.emplace_back(std::move(load
));
5664 Operand sample_index4
;
5665 if (sample_index
.isConstant()) {
5666 if (sample_index
.constantValue() < 16) {
5667 sample_index4
= Operand(sample_index
.constantValue() << 2);
5669 sample_index4
= Operand(0u);
5671 } else if (sample_index
.regClass() == s1
) {
5672 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5674 assert(sample_index
.regClass() == v1
);
5675 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5679 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5680 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5681 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5682 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5684 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5686 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5687 * resource descriptor is 0 (invalid),
5689 Temp compare
= bld
.tmp(bld
.lm
);
5690 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5691 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5693 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5695 /* Replace the MSAA sample index. */
5696 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5699 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5702 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5703 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5704 bool is_array
= glsl_sampler_type_is_array(type
);
5705 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5706 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5707 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5708 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5709 int count
= image_type_to_components_count(dim
, is_array
);
5710 std::vector
<Temp
> coords(count
);
5711 Builder
bld(ctx
->program
, ctx
->block
);
5715 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5716 /* get sample index */
5717 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5718 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5719 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5720 std::vector
<Temp
> fmask_load_address
;
5721 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5722 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5724 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5725 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5727 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5732 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5733 coords
.resize(coords
.size() + 1);
5734 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5736 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5738 for (int i
= 0; i
< count
; i
++)
5739 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5742 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5743 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5744 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5745 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5748 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5751 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5752 for (unsigned i
= 0; i
< coords
.size(); i
++)
5753 vec
->operands
[i
] = Operand(coords
[i
]);
5754 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5755 vec
->definitions
[0] = Definition(res
);
5756 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5761 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5763 Builder
bld(ctx
->program
, ctx
->block
);
5764 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5765 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5766 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5767 bool is_array
= glsl_sampler_type_is_array(type
);
5768 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5770 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5771 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5772 unsigned num_channels
= util_last_bit(mask
);
5773 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5774 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5777 switch (num_channels
) {
5779 opcode
= aco_opcode::buffer_load_format_x
;
5782 opcode
= aco_opcode::buffer_load_format_xy
;
5785 opcode
= aco_opcode::buffer_load_format_xyz
;
5788 opcode
= aco_opcode::buffer_load_format_xyzw
;
5791 unreachable(">4 channel buffer image load");
5793 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5794 load
->operands
[0] = Operand(rsrc
);
5795 load
->operands
[1] = Operand(vindex
);
5796 load
->operands
[2] = Operand((uint32_t) 0);
5798 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5801 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5802 load
->definitions
[0] = Definition(tmp
);
5804 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5805 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5806 load
->barrier
= barrier_image
;
5807 ctx
->block
->instructions
.emplace_back(std::move(load
));
5809 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5813 Temp coords
= get_image_coords(ctx
, instr
, type
);
5814 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5816 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5817 unsigned num_components
= util_bitcount(dmask
);
5819 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5822 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5824 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5825 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5827 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5828 load
->operands
[0] = Operand(resource
);
5829 load
->operands
[1] = Operand(s4
); /* no sampler */
5830 load
->operands
[2] = Operand(coords
);
5831 load
->definitions
[0] = Definition(tmp
);
5832 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5833 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5834 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5835 load
->dmask
= dmask
;
5837 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5838 load
->barrier
= barrier_image
;
5839 ctx
->block
->instructions
.emplace_back(std::move(load
));
5841 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5845 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5847 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5848 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5849 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5850 bool is_array
= glsl_sampler_type_is_array(type
);
5851 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5853 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5855 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5856 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5857 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5859 switch (data
.size()) {
5861 opcode
= aco_opcode::buffer_store_format_x
;
5864 opcode
= aco_opcode::buffer_store_format_xy
;
5867 opcode
= aco_opcode::buffer_store_format_xyz
;
5870 opcode
= aco_opcode::buffer_store_format_xyzw
;
5873 unreachable(">4 channel buffer image store");
5875 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5876 store
->operands
[0] = Operand(rsrc
);
5877 store
->operands
[1] = Operand(vindex
);
5878 store
->operands
[2] = Operand((uint32_t) 0);
5879 store
->operands
[3] = Operand(data
);
5880 store
->idxen
= true;
5883 store
->disable_wqm
= true;
5884 store
->barrier
= barrier_image
;
5885 ctx
->program
->needs_exact
= true;
5886 ctx
->block
->instructions
.emplace_back(std::move(store
));
5890 assert(data
.type() == RegType::vgpr
);
5891 Temp coords
= get_image_coords(ctx
, instr
, type
);
5892 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5894 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5895 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5897 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5898 store
->operands
[0] = Operand(resource
);
5899 store
->operands
[1] = Operand(data
);
5900 store
->operands
[2] = Operand(coords
);
5903 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5904 store
->dmask
= (1 << data
.size()) - 1;
5906 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5907 store
->disable_wqm
= true;
5908 store
->barrier
= barrier_image
;
5909 ctx
->program
->needs_exact
= true;
5910 ctx
->block
->instructions
.emplace_back(std::move(store
));
5914 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5916 /* return the previous value if dest is ever used */
5917 bool return_previous
= false;
5918 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5919 return_previous
= true;
5922 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5923 return_previous
= true;
5927 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5928 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5929 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5930 bool is_array
= glsl_sampler_type_is_array(type
);
5931 Builder
bld(ctx
->program
, ctx
->block
);
5933 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5934 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5936 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5937 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5939 aco_opcode buf_op
, image_op
;
5940 switch (instr
->intrinsic
) {
5941 case nir_intrinsic_image_deref_atomic_add
:
5942 buf_op
= aco_opcode::buffer_atomic_add
;
5943 image_op
= aco_opcode::image_atomic_add
;
5945 case nir_intrinsic_image_deref_atomic_umin
:
5946 buf_op
= aco_opcode::buffer_atomic_umin
;
5947 image_op
= aco_opcode::image_atomic_umin
;
5949 case nir_intrinsic_image_deref_atomic_imin
:
5950 buf_op
= aco_opcode::buffer_atomic_smin
;
5951 image_op
= aco_opcode::image_atomic_smin
;
5953 case nir_intrinsic_image_deref_atomic_umax
:
5954 buf_op
= aco_opcode::buffer_atomic_umax
;
5955 image_op
= aco_opcode::image_atomic_umax
;
5957 case nir_intrinsic_image_deref_atomic_imax
:
5958 buf_op
= aco_opcode::buffer_atomic_smax
;
5959 image_op
= aco_opcode::image_atomic_smax
;
5961 case nir_intrinsic_image_deref_atomic_and
:
5962 buf_op
= aco_opcode::buffer_atomic_and
;
5963 image_op
= aco_opcode::image_atomic_and
;
5965 case nir_intrinsic_image_deref_atomic_or
:
5966 buf_op
= aco_opcode::buffer_atomic_or
;
5967 image_op
= aco_opcode::image_atomic_or
;
5969 case nir_intrinsic_image_deref_atomic_xor
:
5970 buf_op
= aco_opcode::buffer_atomic_xor
;
5971 image_op
= aco_opcode::image_atomic_xor
;
5973 case nir_intrinsic_image_deref_atomic_exchange
:
5974 buf_op
= aco_opcode::buffer_atomic_swap
;
5975 image_op
= aco_opcode::image_atomic_swap
;
5977 case nir_intrinsic_image_deref_atomic_comp_swap
:
5978 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5979 image_op
= aco_opcode::image_atomic_cmpswap
;
5982 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5985 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5987 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5988 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5989 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5990 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5991 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5992 mubuf
->operands
[0] = Operand(resource
);
5993 mubuf
->operands
[1] = Operand(vindex
);
5994 mubuf
->operands
[2] = Operand((uint32_t)0);
5995 mubuf
->operands
[3] = Operand(data
);
5996 if (return_previous
)
5997 mubuf
->definitions
[0] = Definition(dst
);
5999 mubuf
->idxen
= true;
6000 mubuf
->glc
= return_previous
;
6001 mubuf
->dlc
= false; /* Not needed for atomics */
6002 mubuf
->disable_wqm
= true;
6003 mubuf
->barrier
= barrier_image
;
6004 ctx
->program
->needs_exact
= true;
6005 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6009 Temp coords
= get_image_coords(ctx
, instr
, type
);
6010 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6011 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6012 mimg
->operands
[0] = Operand(resource
);
6013 mimg
->operands
[1] = Operand(data
);
6014 mimg
->operands
[2] = Operand(coords
);
6015 if (return_previous
)
6016 mimg
->definitions
[0] = Definition(dst
);
6017 mimg
->glc
= return_previous
;
6018 mimg
->dlc
= false; /* Not needed for atomics */
6019 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6020 mimg
->dmask
= (1 << data
.size()) - 1;
6022 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6023 mimg
->disable_wqm
= true;
6024 mimg
->barrier
= barrier_image
;
6025 ctx
->program
->needs_exact
= true;
6026 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6030 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6032 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6033 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6034 Builder
bld(ctx
->program
, ctx
->block
);
6036 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6038 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6039 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6041 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6042 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6044 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6045 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6047 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6048 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6049 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6050 if (dst
.type() == RegType::vgpr
)
6051 bld
.copy(Definition(dst
), shr_dst
);
6053 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6055 emit_extract_vector(ctx
, desc
, 2, dst
);
6059 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6061 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6062 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6063 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6064 bool is_array
= glsl_sampler_type_is_array(type
);
6065 Builder
bld(ctx
->program
, ctx
->block
);
6067 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6068 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6069 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6073 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6076 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6078 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6080 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6081 mimg
->operands
[0] = Operand(resource
);
6082 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6083 mimg
->operands
[2] = Operand(lod
);
6084 uint8_t& dmask
= mimg
->dmask
;
6085 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6086 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6087 mimg
->da
= glsl_sampler_type_is_array(type
);
6088 mimg
->can_reorder
= true;
6089 Definition
& def
= mimg
->definitions
[0];
6090 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6092 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6093 glsl_sampler_type_is_array(type
)) {
6095 assert(instr
->dest
.ssa
.num_components
== 3);
6096 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6097 def
= Definition(tmp
);
6098 emit_split_vector(ctx
, tmp
, 3);
6100 /* divide 3rd value by 6 by multiplying with magic number */
6101 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6102 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6104 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6105 emit_extract_vector(ctx
, tmp
, 0, v1
),
6106 emit_extract_vector(ctx
, tmp
, 1, v1
),
6109 } else if (ctx
->options
->chip_class
== GFX9
&&
6110 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6111 glsl_sampler_type_is_array(type
)) {
6112 assert(instr
->dest
.ssa
.num_components
== 2);
6113 def
= Definition(dst
);
6116 def
= Definition(dst
);
6119 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6122 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6124 Builder
bld(ctx
->program
, ctx
->block
);
6125 unsigned num_components
= instr
->num_components
;
6127 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6128 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6129 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6131 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6132 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6133 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6134 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6137 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6139 Builder
bld(ctx
->program
, ctx
->block
);
6140 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6141 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6142 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6143 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6145 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6146 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6148 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6149 ctx
->options
->chip_class
>= GFX8
&&
6150 elem_size_bytes
>= 4;
6152 offset
= bld
.as_uniform(offset
);
6153 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6155 unsigned write_count
= 0;
6156 Temp write_datas
[32];
6157 unsigned offsets
[32];
6158 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6159 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6161 for (unsigned i
= 0; i
< write_count
; i
++) {
6162 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6163 if (smem
&& ctx
->stage
== fragment_fs
)
6164 op
= aco_opcode::p_fs_buffer_store_smem
;
6167 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6168 store
->operands
[0] = Operand(rsrc
);
6170 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6171 offset
, Operand(offsets
[i
]));
6172 store
->operands
[1] = Operand(off
);
6174 store
->operands
[1] = Operand(offset
);
6176 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6177 store
->operands
[1].setFixed(m0
);
6178 store
->operands
[2] = Operand(write_datas
[i
]);
6179 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6181 store
->disable_wqm
= true;
6182 store
->barrier
= barrier_buffer
;
6183 ctx
->block
->instructions
.emplace_back(std::move(store
));
6184 ctx
->program
->wb_smem_l1_on_end
= true;
6185 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6186 ctx
->block
->kind
|= block_kind_needs_lowering
;
6187 ctx
->program
->needs_exact
= true;
6190 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6191 store
->operands
[0] = Operand(rsrc
);
6192 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6193 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6194 store
->operands
[3] = Operand(write_datas
[i
]);
6195 store
->offset
= offsets
[i
];
6196 store
->offen
= (offset
.type() == RegType::vgpr
);
6197 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6199 store
->disable_wqm
= true;
6200 store
->barrier
= barrier_buffer
;
6201 ctx
->program
->needs_exact
= true;
6202 ctx
->block
->instructions
.emplace_back(std::move(store
));
6207 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6209 /* return the previous value if dest is ever used */
6210 bool return_previous
= false;
6211 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6212 return_previous
= true;
6215 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6216 return_previous
= true;
6220 Builder
bld(ctx
->program
, ctx
->block
);
6221 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6223 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6224 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6225 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6227 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6228 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6229 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6231 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6233 aco_opcode op32
, op64
;
6234 switch (instr
->intrinsic
) {
6235 case nir_intrinsic_ssbo_atomic_add
:
6236 op32
= aco_opcode::buffer_atomic_add
;
6237 op64
= aco_opcode::buffer_atomic_add_x2
;
6239 case nir_intrinsic_ssbo_atomic_imin
:
6240 op32
= aco_opcode::buffer_atomic_smin
;
6241 op64
= aco_opcode::buffer_atomic_smin_x2
;
6243 case nir_intrinsic_ssbo_atomic_umin
:
6244 op32
= aco_opcode::buffer_atomic_umin
;
6245 op64
= aco_opcode::buffer_atomic_umin_x2
;
6247 case nir_intrinsic_ssbo_atomic_imax
:
6248 op32
= aco_opcode::buffer_atomic_smax
;
6249 op64
= aco_opcode::buffer_atomic_smax_x2
;
6251 case nir_intrinsic_ssbo_atomic_umax
:
6252 op32
= aco_opcode::buffer_atomic_umax
;
6253 op64
= aco_opcode::buffer_atomic_umax_x2
;
6255 case nir_intrinsic_ssbo_atomic_and
:
6256 op32
= aco_opcode::buffer_atomic_and
;
6257 op64
= aco_opcode::buffer_atomic_and_x2
;
6259 case nir_intrinsic_ssbo_atomic_or
:
6260 op32
= aco_opcode::buffer_atomic_or
;
6261 op64
= aco_opcode::buffer_atomic_or_x2
;
6263 case nir_intrinsic_ssbo_atomic_xor
:
6264 op32
= aco_opcode::buffer_atomic_xor
;
6265 op64
= aco_opcode::buffer_atomic_xor_x2
;
6267 case nir_intrinsic_ssbo_atomic_exchange
:
6268 op32
= aco_opcode::buffer_atomic_swap
;
6269 op64
= aco_opcode::buffer_atomic_swap_x2
;
6271 case nir_intrinsic_ssbo_atomic_comp_swap
:
6272 op32
= aco_opcode::buffer_atomic_cmpswap
;
6273 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6276 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6278 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6279 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6280 mubuf
->operands
[0] = Operand(rsrc
);
6281 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6282 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6283 mubuf
->operands
[3] = Operand(data
);
6284 if (return_previous
)
6285 mubuf
->definitions
[0] = Definition(dst
);
6287 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6288 mubuf
->glc
= return_previous
;
6289 mubuf
->dlc
= false; /* Not needed for atomics */
6290 mubuf
->disable_wqm
= true;
6291 mubuf
->barrier
= barrier_buffer
;
6292 ctx
->program
->needs_exact
= true;
6293 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6296 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6298 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6299 Builder
bld(ctx
->program
, ctx
->block
);
6300 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6301 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6304 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6306 Builder
bld(ctx
->program
, ctx
->block
);
6307 unsigned num_components
= instr
->num_components
;
6308 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6310 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6311 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6312 num_components
, component_size
};
6313 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6314 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6315 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6316 info
.barrier
= barrier_buffer
;
6317 info
.can_reorder
= false;
6318 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6319 * it's safe to use SMEM */
6320 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6321 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6322 emit_global_load(ctx
, bld
, &info
);
6324 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6325 emit_smem_load(ctx
, bld
, &info
);
6329 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6331 Builder
bld(ctx
->program
, ctx
->block
);
6332 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6333 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6335 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6336 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6337 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6339 if (ctx
->options
->chip_class
>= GFX7
)
6340 addr
= as_vgpr(ctx
, addr
);
6342 unsigned write_count
= 0;
6343 Temp write_datas
[32];
6344 unsigned offsets
[32];
6345 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6346 16, &write_count
, write_datas
, offsets
);
6348 for (unsigned i
= 0; i
< write_count
; i
++) {
6349 if (ctx
->options
->chip_class
>= GFX7
) {
6350 unsigned offset
= offsets
[i
];
6351 Temp store_addr
= addr
;
6352 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6353 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6354 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6355 Temp carry
= bld
.tmp(bld
.lm
);
6356 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6358 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6359 Operand(offset
), addr0
);
6360 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6362 carry
).def(1).setHint(vcc
);
6364 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6369 bool global
= ctx
->options
->chip_class
>= GFX9
;
6371 switch (write_datas
[i
].bytes()) {
6373 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6376 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6379 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6382 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6385 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6388 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6391 unreachable("store_global not implemented for this size.");
6394 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6395 flat
->operands
[0] = Operand(store_addr
);
6396 flat
->operands
[1] = Operand(s1
);
6397 flat
->operands
[2] = Operand(write_datas
[i
]);
6400 flat
->offset
= offset
;
6401 flat
->disable_wqm
= true;
6402 flat
->barrier
= barrier_buffer
;
6403 ctx
->program
->needs_exact
= true;
6404 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6406 assert(ctx
->options
->chip_class
== GFX6
);
6408 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6410 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6412 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6413 mubuf
->operands
[0] = Operand(rsrc
);
6414 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6415 mubuf
->operands
[2] = Operand(0u);
6416 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6419 mubuf
->offset
= offsets
[i
];
6420 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6421 mubuf
->disable_wqm
= true;
6422 mubuf
->barrier
= barrier_buffer
;
6423 ctx
->program
->needs_exact
= true;
6424 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6429 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6431 /* return the previous value if dest is ever used */
6432 bool return_previous
= false;
6433 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6434 return_previous
= true;
6437 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6438 return_previous
= true;
6442 Builder
bld(ctx
->program
, ctx
->block
);
6443 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6444 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6446 if (ctx
->options
->chip_class
>= GFX7
)
6447 addr
= as_vgpr(ctx
, addr
);
6449 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6450 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6451 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6453 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6455 aco_opcode op32
, op64
;
6457 if (ctx
->options
->chip_class
>= GFX7
) {
6458 bool global
= ctx
->options
->chip_class
>= GFX9
;
6459 switch (instr
->intrinsic
) {
6460 case nir_intrinsic_global_atomic_add
:
6461 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6462 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6464 case nir_intrinsic_global_atomic_imin
:
6465 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6466 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6468 case nir_intrinsic_global_atomic_umin
:
6469 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6470 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6472 case nir_intrinsic_global_atomic_imax
:
6473 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6474 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6476 case nir_intrinsic_global_atomic_umax
:
6477 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6478 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6480 case nir_intrinsic_global_atomic_and
:
6481 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6482 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6484 case nir_intrinsic_global_atomic_or
:
6485 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6486 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6488 case nir_intrinsic_global_atomic_xor
:
6489 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6490 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6492 case nir_intrinsic_global_atomic_exchange
:
6493 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6494 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6496 case nir_intrinsic_global_atomic_comp_swap
:
6497 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6498 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6501 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6504 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6505 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6506 flat
->operands
[0] = Operand(addr
);
6507 flat
->operands
[1] = Operand(s1
);
6508 flat
->operands
[2] = Operand(data
);
6509 if (return_previous
)
6510 flat
->definitions
[0] = Definition(dst
);
6511 flat
->glc
= return_previous
;
6512 flat
->dlc
= false; /* Not needed for atomics */
6514 flat
->disable_wqm
= true;
6515 flat
->barrier
= barrier_buffer
;
6516 ctx
->program
->needs_exact
= true;
6517 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6519 assert(ctx
->options
->chip_class
== GFX6
);
6521 switch (instr
->intrinsic
) {
6522 case nir_intrinsic_global_atomic_add
:
6523 op32
= aco_opcode::buffer_atomic_add
;
6524 op64
= aco_opcode::buffer_atomic_add_x2
;
6526 case nir_intrinsic_global_atomic_imin
:
6527 op32
= aco_opcode::buffer_atomic_smin
;
6528 op64
= aco_opcode::buffer_atomic_smin_x2
;
6530 case nir_intrinsic_global_atomic_umin
:
6531 op32
= aco_opcode::buffer_atomic_umin
;
6532 op64
= aco_opcode::buffer_atomic_umin_x2
;
6534 case nir_intrinsic_global_atomic_imax
:
6535 op32
= aco_opcode::buffer_atomic_smax
;
6536 op64
= aco_opcode::buffer_atomic_smax_x2
;
6538 case nir_intrinsic_global_atomic_umax
:
6539 op32
= aco_opcode::buffer_atomic_umax
;
6540 op64
= aco_opcode::buffer_atomic_umax_x2
;
6542 case nir_intrinsic_global_atomic_and
:
6543 op32
= aco_opcode::buffer_atomic_and
;
6544 op64
= aco_opcode::buffer_atomic_and_x2
;
6546 case nir_intrinsic_global_atomic_or
:
6547 op32
= aco_opcode::buffer_atomic_or
;
6548 op64
= aco_opcode::buffer_atomic_or_x2
;
6550 case nir_intrinsic_global_atomic_xor
:
6551 op32
= aco_opcode::buffer_atomic_xor
;
6552 op64
= aco_opcode::buffer_atomic_xor_x2
;
6554 case nir_intrinsic_global_atomic_exchange
:
6555 op32
= aco_opcode::buffer_atomic_swap
;
6556 op64
= aco_opcode::buffer_atomic_swap_x2
;
6558 case nir_intrinsic_global_atomic_comp_swap
:
6559 op32
= aco_opcode::buffer_atomic_cmpswap
;
6560 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6563 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6566 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6568 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6570 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6571 mubuf
->operands
[0] = Operand(rsrc
);
6572 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6573 mubuf
->operands
[2] = Operand(0u);
6574 mubuf
->operands
[3] = Operand(data
);
6575 if (return_previous
)
6576 mubuf
->definitions
[0] = Definition(dst
);
6577 mubuf
->glc
= return_previous
;
6580 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6581 mubuf
->disable_wqm
= true;
6582 mubuf
->barrier
= barrier_buffer
;
6583 ctx
->program
->needs_exact
= true;
6584 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6588 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6589 Builder
bld(ctx
->program
, ctx
->block
);
6590 switch(instr
->intrinsic
) {
6591 case nir_intrinsic_group_memory_barrier
:
6592 case nir_intrinsic_memory_barrier
:
6593 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6595 case nir_intrinsic_memory_barrier_buffer
:
6596 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6598 case nir_intrinsic_memory_barrier_image
:
6599 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6601 case nir_intrinsic_memory_barrier_tcs_patch
:
6602 case nir_intrinsic_memory_barrier_shared
:
6603 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6606 unreachable("Unimplemented memory barrier intrinsic");
6611 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6613 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6614 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6615 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6616 Builder
bld(ctx
->program
, ctx
->block
);
6618 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6619 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6620 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6623 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6625 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6626 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6627 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6628 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6630 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6631 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6634 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6636 unsigned offset
= nir_intrinsic_base(instr
);
6637 Builder
bld(ctx
->program
, ctx
->block
);
6638 Operand m
= load_lds_size_m0(bld
);
6639 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6640 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6642 unsigned num_operands
= 3;
6643 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6644 switch(instr
->intrinsic
) {
6645 case nir_intrinsic_shared_atomic_add
:
6646 op32
= aco_opcode::ds_add_u32
;
6647 op64
= aco_opcode::ds_add_u64
;
6648 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6649 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6651 case nir_intrinsic_shared_atomic_imin
:
6652 op32
= aco_opcode::ds_min_i32
;
6653 op64
= aco_opcode::ds_min_i64
;
6654 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6655 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6657 case nir_intrinsic_shared_atomic_umin
:
6658 op32
= aco_opcode::ds_min_u32
;
6659 op64
= aco_opcode::ds_min_u64
;
6660 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6661 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6663 case nir_intrinsic_shared_atomic_imax
:
6664 op32
= aco_opcode::ds_max_i32
;
6665 op64
= aco_opcode::ds_max_i64
;
6666 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6667 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6669 case nir_intrinsic_shared_atomic_umax
:
6670 op32
= aco_opcode::ds_max_u32
;
6671 op64
= aco_opcode::ds_max_u64
;
6672 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6673 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6675 case nir_intrinsic_shared_atomic_and
:
6676 op32
= aco_opcode::ds_and_b32
;
6677 op64
= aco_opcode::ds_and_b64
;
6678 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6679 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6681 case nir_intrinsic_shared_atomic_or
:
6682 op32
= aco_opcode::ds_or_b32
;
6683 op64
= aco_opcode::ds_or_b64
;
6684 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6685 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6687 case nir_intrinsic_shared_atomic_xor
:
6688 op32
= aco_opcode::ds_xor_b32
;
6689 op64
= aco_opcode::ds_xor_b64
;
6690 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6691 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6693 case nir_intrinsic_shared_atomic_exchange
:
6694 op32
= aco_opcode::ds_write_b32
;
6695 op64
= aco_opcode::ds_write_b64
;
6696 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6697 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6699 case nir_intrinsic_shared_atomic_comp_swap
:
6700 op32
= aco_opcode::ds_cmpst_b32
;
6701 op64
= aco_opcode::ds_cmpst_b64
;
6702 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6703 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6707 unreachable("Unhandled shared atomic intrinsic");
6710 /* return the previous value if dest is ever used */
6711 bool return_previous
= false;
6712 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6713 return_previous
= true;
6716 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6717 return_previous
= true;
6722 if (data
.size() == 1) {
6723 assert(instr
->dest
.ssa
.bit_size
== 32);
6724 op
= return_previous
? op32_rtn
: op32
;
6726 assert(instr
->dest
.ssa
.bit_size
== 64);
6727 op
= return_previous
? op64_rtn
: op64
;
6730 if (offset
> 65535) {
6731 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6735 aco_ptr
<DS_instruction
> ds
;
6736 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6737 ds
->operands
[0] = Operand(address
);
6738 ds
->operands
[1] = Operand(data
);
6739 if (num_operands
== 4)
6740 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6741 ds
->operands
[num_operands
- 1] = m
;
6742 ds
->offset0
= offset
;
6743 if (return_previous
)
6744 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6745 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6748 Temp
get_scratch_resource(isel_context
*ctx
)
6750 Builder
bld(ctx
->program
, ctx
->block
);
6751 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6752 if (ctx
->stage
!= compute_cs
)
6753 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6755 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6756 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6758 if (ctx
->program
->chip_class
>= GFX10
) {
6759 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6760 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6761 S_008F0C_RESOURCE_LEVEL(1);
6762 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6763 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6764 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6767 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6768 if (ctx
->program
->chip_class
<= GFX8
)
6769 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6771 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6774 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6775 Builder
bld(ctx
->program
, ctx
->block
);
6776 Temp rsrc
= get_scratch_resource(ctx
);
6777 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6778 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6780 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6781 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6782 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6783 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6784 info
.swizzle_component_size
= 16;
6785 info
.can_reorder
= false;
6786 info
.soffset
= ctx
->program
->scratch_offset
;
6787 emit_mubuf_load(ctx
, bld
, &info
);
6790 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6791 Builder
bld(ctx
->program
, ctx
->block
);
6792 Temp rsrc
= get_scratch_resource(ctx
);
6793 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6794 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6796 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6797 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6799 unsigned write_count
= 0;
6800 Temp write_datas
[32];
6801 unsigned offsets
[32];
6802 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6803 16, &write_count
, write_datas
, offsets
);
6805 for (unsigned i
= 0; i
< write_count
; i
++) {
6806 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6807 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6811 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6812 uint8_t log2_ps_iter_samples
;
6813 if (ctx
->program
->info
->ps
.force_persample
) {
6814 log2_ps_iter_samples
=
6815 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6817 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6820 /* The bit pattern matches that used by fixed function fragment
6822 static const unsigned ps_iter_masks
[] = {
6823 0xffff, /* not used */
6829 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6831 Builder
bld(ctx
->program
, ctx
->block
);
6833 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6834 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6835 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6836 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6837 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6838 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6841 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6842 Builder
bld(ctx
->program
, ctx
->block
);
6844 unsigned stream
= nir_intrinsic_stream_id(instr
);
6845 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6846 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6847 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6850 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6852 unsigned num_components
=
6853 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6854 assert(num_components
);
6856 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6857 unsigned stream_offset
= 0;
6858 for (unsigned i
= 0; i
< stream
; i
++) {
6859 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6860 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6863 /* Limit on the stride field for <= GFX7. */
6864 assert(stride
< (1 << 14));
6866 Temp gsvs_dwords
[4];
6867 for (unsigned i
= 0; i
< 4; i
++)
6868 gsvs_dwords
[i
] = bld
.tmp(s1
);
6869 bld
.pseudo(aco_opcode::p_split_vector
,
6870 Definition(gsvs_dwords
[0]),
6871 Definition(gsvs_dwords
[1]),
6872 Definition(gsvs_dwords
[2]),
6873 Definition(gsvs_dwords
[3]),
6876 if (stream_offset
) {
6877 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6879 Temp carry
= bld
.tmp(s1
);
6880 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6881 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6884 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6885 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6887 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6888 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6890 unsigned offset
= 0;
6891 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6892 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6895 for (unsigned j
= 0; j
< 4; j
++) {
6896 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6899 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6900 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6901 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6902 if (const_offset
>= 4096u) {
6903 if (vaddr_offset
.isUndefined())
6904 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6906 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6907 const_offset
%= 4096u;
6910 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6911 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6912 mtbuf
->operands
[1] = vaddr_offset
;
6913 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6914 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6915 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6916 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6917 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6918 mtbuf
->offset
= const_offset
;
6921 mtbuf
->barrier
= barrier_gs_data
;
6922 mtbuf
->can_reorder
= true;
6923 bld
.insert(std::move(mtbuf
));
6926 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6929 /* outputs for the next vertex are undefined and keeping them around can
6930 * create invalid IR with control flow */
6931 ctx
->outputs
.mask
[i
] = 0;
6934 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6937 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6939 Builder
bld(ctx
->program
, ctx
->block
);
6941 if (cluster_size
== 1) {
6943 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6944 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6945 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6946 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6947 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6948 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6949 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6950 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6951 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6952 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6953 //subgroupAnd(val) -> (exec & ~val) == 0
6954 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6955 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6956 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6957 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6958 //subgroupOr(val) -> (val & exec) != 0
6959 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6960 return bool_to_vector_condition(ctx
, tmp
);
6961 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6962 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6963 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6964 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6965 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6966 return bool_to_vector_condition(ctx
, tmp
);
6968 //subgroupClustered{And,Or,Xor}(val, n) ->
6969 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6970 //cluster_offset = ~(n - 1) & lane_id
6971 //cluster_mask = ((1 << n) - 1)
6972 //subgroupClusteredAnd():
6973 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6974 //subgroupClusteredOr():
6975 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6976 //subgroupClusteredXor():
6977 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6978 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6979 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6982 if (op
== nir_op_iand
)
6983 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6985 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6987 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6989 if (ctx
->program
->chip_class
<= GFX7
)
6990 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6991 else if (ctx
->program
->wave_size
== 64)
6992 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6994 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6995 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6996 if (cluster_mask
!= 0xffffffff)
6997 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6999 Definition cmp_def
= Definition();
7000 if (op
== nir_op_iand
) {
7001 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7002 } else if (op
== nir_op_ior
) {
7003 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7004 } else if (op
== nir_op_ixor
) {
7005 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7006 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7007 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7009 cmp_def
.setHint(vcc
);
7010 return cmp_def
.getTemp();
7014 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7016 Builder
bld(ctx
->program
, ctx
->block
);
7018 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7019 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7020 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7022 if (op
== nir_op_iand
)
7023 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7025 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7027 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7028 Temp lo
= lohi
.def(0).getTemp();
7029 Temp hi
= lohi
.def(1).getTemp();
7030 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7032 Definition cmp_def
= Definition();
7033 if (op
== nir_op_iand
)
7034 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7035 else if (op
== nir_op_ior
)
7036 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7037 else if (op
== nir_op_ixor
)
7038 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7039 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7040 cmp_def
.setHint(vcc
);
7041 return cmp_def
.getTemp();
7044 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7046 Builder
bld(ctx
->program
, ctx
->block
);
7048 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7049 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7050 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7051 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7052 if (op
== nir_op_iand
)
7053 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7054 else if (op
== nir_op_ior
)
7055 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7056 else if (op
== nir_op_ixor
)
7057 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7063 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7065 Builder
bld(ctx
->program
, ctx
->block
);
7066 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7067 if (src
.regClass().type() == RegType::vgpr
) {
7068 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7069 } else if (src
.regClass() == s1
) {
7070 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7071 } else if (src
.regClass() == s2
) {
7072 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7074 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7075 nir_print_instr(&instr
->instr
, stderr
);
7076 fprintf(stderr
, "\n");
7080 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7082 Builder
bld(ctx
->program
, ctx
->block
);
7083 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7084 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7085 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7087 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7088 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7089 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7090 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7093 if (ctx
->program
->chip_class
>= GFX8
) {
7094 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7095 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7096 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7097 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7098 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7099 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7101 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7102 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7103 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7104 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7105 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7106 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7107 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7108 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7109 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7110 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7113 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7114 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7115 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7116 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7117 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7118 Temp wqm1
= bld
.tmp(v1
);
7119 emit_wqm(ctx
, tmp1
, wqm1
, true);
7120 Temp wqm2
= bld
.tmp(v1
);
7121 emit_wqm(ctx
, tmp2
, wqm2
, true);
7122 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7126 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7128 Builder
bld(ctx
->program
, ctx
->block
);
7129 switch(instr
->intrinsic
) {
7130 case nir_intrinsic_load_barycentric_sample
:
7131 case nir_intrinsic_load_barycentric_pixel
:
7132 case nir_intrinsic_load_barycentric_centroid
: {
7133 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7134 Temp bary
= Temp(0, s2
);
7136 case INTERP_MODE_SMOOTH
:
7137 case INTERP_MODE_NONE
:
7138 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7139 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7140 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7141 bary
= ctx
->persp_centroid
;
7142 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7143 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7145 case INTERP_MODE_NOPERSPECTIVE
:
7146 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7147 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7148 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7149 bary
= ctx
->linear_centroid
;
7150 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7151 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7156 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7157 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7158 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7159 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7160 Operand(p1
), Operand(p2
));
7161 emit_split_vector(ctx
, dst
, 2);
7164 case nir_intrinsic_load_barycentric_model
: {
7165 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7167 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7168 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7169 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7170 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7171 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7172 Operand(p1
), Operand(p2
), Operand(p3
));
7173 emit_split_vector(ctx
, dst
, 3);
7176 case nir_intrinsic_load_barycentric_at_sample
: {
7177 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7178 switch (ctx
->options
->key
.fs
.num_samples
) {
7179 case 2: sample_pos_offset
+= 1 << 3; break;
7180 case 4: sample_pos_offset
+= 3 << 3; break;
7181 case 8: sample_pos_offset
+= 7 << 3; break;
7185 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7186 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7187 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7188 if (addr
.type() == RegType::sgpr
) {
7191 sample_pos_offset
+= const_addr
->u32
<< 3;
7192 offset
= Operand(sample_pos_offset
);
7193 } else if (ctx
->options
->chip_class
>= GFX9
) {
7194 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7196 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7197 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7200 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7201 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7203 } else if (ctx
->options
->chip_class
>= GFX9
) {
7204 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7205 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7206 } else if (ctx
->options
->chip_class
>= GFX7
) {
7207 /* addr += private_segment_buffer + sample_pos_offset */
7208 Temp tmp0
= bld
.tmp(s1
);
7209 Temp tmp1
= bld
.tmp(s1
);
7210 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7211 Definition scc_tmp
= bld
.def(s1
, scc
);
7212 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7213 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7214 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7215 Temp pck0
= bld
.tmp(v1
);
7216 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7217 tmp1
= as_vgpr(ctx
, tmp1
);
7218 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7219 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7221 /* sample_pos = flat_load_dwordx2 addr */
7222 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7224 assert(ctx
->options
->chip_class
== GFX6
);
7226 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7227 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7228 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7230 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7231 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7233 sample_pos
= bld
.tmp(v2
);
7235 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7236 load
->definitions
[0] = Definition(sample_pos
);
7237 load
->operands
[0] = Operand(rsrc
);
7238 load
->operands
[1] = Operand(addr
);
7239 load
->operands
[2] = Operand(0u);
7240 load
->offset
= sample_pos_offset
;
7242 load
->addr64
= true;
7245 load
->disable_wqm
= false;
7246 load
->barrier
= barrier_none
;
7247 load
->can_reorder
= true;
7248 ctx
->block
->instructions
.emplace_back(std::move(load
));
7251 /* sample_pos -= 0.5 */
7252 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7253 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7254 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7255 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7256 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7258 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7261 case nir_intrinsic_load_barycentric_at_offset
: {
7262 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7263 RegClass rc
= RegClass(offset
.type(), 1);
7264 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7265 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7266 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7269 case nir_intrinsic_load_front_face
: {
7270 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7271 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7274 case nir_intrinsic_load_view_index
: {
7275 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7276 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7277 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7283 case nir_intrinsic_load_layer_id
: {
7284 unsigned idx
= nir_intrinsic_base(instr
);
7285 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7286 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7289 case nir_intrinsic_load_frag_coord
: {
7290 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7293 case nir_intrinsic_load_sample_pos
: {
7294 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7295 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7296 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7297 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7298 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7301 case nir_intrinsic_load_tess_coord
:
7302 visit_load_tess_coord(ctx
, instr
);
7304 case nir_intrinsic_load_interpolated_input
:
7305 visit_load_interpolated_input(ctx
, instr
);
7307 case nir_intrinsic_store_output
:
7308 visit_store_output(ctx
, instr
);
7310 case nir_intrinsic_load_input
:
7311 case nir_intrinsic_load_input_vertex
:
7312 visit_load_input(ctx
, instr
);
7314 case nir_intrinsic_load_output
:
7315 visit_load_output(ctx
, instr
);
7317 case nir_intrinsic_load_per_vertex_input
:
7318 visit_load_per_vertex_input(ctx
, instr
);
7320 case nir_intrinsic_load_per_vertex_output
:
7321 visit_load_per_vertex_output(ctx
, instr
);
7323 case nir_intrinsic_store_per_vertex_output
:
7324 visit_store_per_vertex_output(ctx
, instr
);
7326 case nir_intrinsic_load_ubo
:
7327 visit_load_ubo(ctx
, instr
);
7329 case nir_intrinsic_load_push_constant
:
7330 visit_load_push_constant(ctx
, instr
);
7332 case nir_intrinsic_load_constant
:
7333 visit_load_constant(ctx
, instr
);
7335 case nir_intrinsic_vulkan_resource_index
:
7336 visit_load_resource(ctx
, instr
);
7338 case nir_intrinsic_discard
:
7339 visit_discard(ctx
, instr
);
7341 case nir_intrinsic_discard_if
:
7342 visit_discard_if(ctx
, instr
);
7344 case nir_intrinsic_load_shared
:
7345 visit_load_shared(ctx
, instr
);
7347 case nir_intrinsic_store_shared
:
7348 visit_store_shared(ctx
, instr
);
7350 case nir_intrinsic_shared_atomic_add
:
7351 case nir_intrinsic_shared_atomic_imin
:
7352 case nir_intrinsic_shared_atomic_umin
:
7353 case nir_intrinsic_shared_atomic_imax
:
7354 case nir_intrinsic_shared_atomic_umax
:
7355 case nir_intrinsic_shared_atomic_and
:
7356 case nir_intrinsic_shared_atomic_or
:
7357 case nir_intrinsic_shared_atomic_xor
:
7358 case nir_intrinsic_shared_atomic_exchange
:
7359 case nir_intrinsic_shared_atomic_comp_swap
:
7360 visit_shared_atomic(ctx
, instr
);
7362 case nir_intrinsic_image_deref_load
:
7363 visit_image_load(ctx
, instr
);
7365 case nir_intrinsic_image_deref_store
:
7366 visit_image_store(ctx
, instr
);
7368 case nir_intrinsic_image_deref_atomic_add
:
7369 case nir_intrinsic_image_deref_atomic_umin
:
7370 case nir_intrinsic_image_deref_atomic_imin
:
7371 case nir_intrinsic_image_deref_atomic_umax
:
7372 case nir_intrinsic_image_deref_atomic_imax
:
7373 case nir_intrinsic_image_deref_atomic_and
:
7374 case nir_intrinsic_image_deref_atomic_or
:
7375 case nir_intrinsic_image_deref_atomic_xor
:
7376 case nir_intrinsic_image_deref_atomic_exchange
:
7377 case nir_intrinsic_image_deref_atomic_comp_swap
:
7378 visit_image_atomic(ctx
, instr
);
7380 case nir_intrinsic_image_deref_size
:
7381 visit_image_size(ctx
, instr
);
7383 case nir_intrinsic_load_ssbo
:
7384 visit_load_ssbo(ctx
, instr
);
7386 case nir_intrinsic_store_ssbo
:
7387 visit_store_ssbo(ctx
, instr
);
7389 case nir_intrinsic_load_global
:
7390 visit_load_global(ctx
, instr
);
7392 case nir_intrinsic_store_global
:
7393 visit_store_global(ctx
, instr
);
7395 case nir_intrinsic_global_atomic_add
:
7396 case nir_intrinsic_global_atomic_imin
:
7397 case nir_intrinsic_global_atomic_umin
:
7398 case nir_intrinsic_global_atomic_imax
:
7399 case nir_intrinsic_global_atomic_umax
:
7400 case nir_intrinsic_global_atomic_and
:
7401 case nir_intrinsic_global_atomic_or
:
7402 case nir_intrinsic_global_atomic_xor
:
7403 case nir_intrinsic_global_atomic_exchange
:
7404 case nir_intrinsic_global_atomic_comp_swap
:
7405 visit_global_atomic(ctx
, instr
);
7407 case nir_intrinsic_ssbo_atomic_add
:
7408 case nir_intrinsic_ssbo_atomic_imin
:
7409 case nir_intrinsic_ssbo_atomic_umin
:
7410 case nir_intrinsic_ssbo_atomic_imax
:
7411 case nir_intrinsic_ssbo_atomic_umax
:
7412 case nir_intrinsic_ssbo_atomic_and
:
7413 case nir_intrinsic_ssbo_atomic_or
:
7414 case nir_intrinsic_ssbo_atomic_xor
:
7415 case nir_intrinsic_ssbo_atomic_exchange
:
7416 case nir_intrinsic_ssbo_atomic_comp_swap
:
7417 visit_atomic_ssbo(ctx
, instr
);
7419 case nir_intrinsic_load_scratch
:
7420 visit_load_scratch(ctx
, instr
);
7422 case nir_intrinsic_store_scratch
:
7423 visit_store_scratch(ctx
, instr
);
7425 case nir_intrinsic_get_buffer_size
:
7426 visit_get_buffer_size(ctx
, instr
);
7428 case nir_intrinsic_control_barrier
: {
7429 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7430 /* GFX6 only (thanks to a hw bug workaround):
7431 * The real barrier instruction isn’t needed, because an entire patch
7432 * always fits into a single wave.
7437 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7438 bld
.sopp(aco_opcode::s_barrier
);
7442 case nir_intrinsic_memory_barrier_tcs_patch
:
7443 case nir_intrinsic_group_memory_barrier
:
7444 case nir_intrinsic_memory_barrier
:
7445 case nir_intrinsic_memory_barrier_buffer
:
7446 case nir_intrinsic_memory_barrier_image
:
7447 case nir_intrinsic_memory_barrier_shared
:
7448 emit_memory_barrier(ctx
, instr
);
7450 case nir_intrinsic_load_num_work_groups
: {
7451 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7452 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7453 emit_split_vector(ctx
, dst
, 3);
7456 case nir_intrinsic_load_local_invocation_id
: {
7457 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7458 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7459 emit_split_vector(ctx
, dst
, 3);
7462 case nir_intrinsic_load_work_group_id
: {
7463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7464 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7465 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7466 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7467 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7468 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7469 emit_split_vector(ctx
, dst
, 3);
7472 case nir_intrinsic_load_local_invocation_index
: {
7473 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7475 /* The tg_size bits [6:11] contain the subgroup id,
7476 * we need this multiplied by the wave size, and then OR the thread id to it.
7478 if (ctx
->program
->wave_size
== 64) {
7479 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7480 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7481 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7482 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7484 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7485 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7486 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7487 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7491 case nir_intrinsic_load_subgroup_id
: {
7492 if (ctx
->stage
== compute_cs
) {
7493 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7494 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7496 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7500 case nir_intrinsic_load_subgroup_invocation
: {
7501 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7504 case nir_intrinsic_load_num_subgroups
: {
7505 if (ctx
->stage
== compute_cs
)
7506 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7507 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7509 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7512 case nir_intrinsic_ballot
: {
7513 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7514 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7515 Definition tmp
= bld
.def(dst
.regClass());
7516 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7517 if (instr
->src
[0].ssa
->bit_size
== 1) {
7518 assert(src
.regClass() == bld
.lm
);
7519 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7520 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7521 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7522 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7523 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7526 nir_print_instr(&instr
->instr
, stderr
);
7527 fprintf(stderr
, "\n");
7529 if (dst
.size() != bld
.lm
.size()) {
7530 /* Wave32 with ballot size set to 64 */
7531 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7533 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7536 case nir_intrinsic_shuffle
:
7537 case nir_intrinsic_read_invocation
: {
7538 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7539 if (!nir_src_is_divergent(instr
->src
[0])) {
7540 emit_uniform_subgroup(ctx
, instr
, src
);
7542 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7543 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7544 tid
= bld
.as_uniform(tid
);
7545 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7546 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7547 Temp tmp
= bld
.tmp(v1
);
7548 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7549 if (dst
.type() == RegType::vgpr
)
7550 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7552 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7553 } else if (src
.regClass() == v1
) {
7554 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7555 } else if (src
.regClass() == v2
) {
7556 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7557 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7558 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7559 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7560 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7561 emit_split_vector(ctx
, dst
, 2);
7562 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7563 assert(src
.regClass() == bld
.lm
);
7564 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7565 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7566 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7567 assert(src
.regClass() == bld
.lm
);
7569 if (ctx
->program
->chip_class
<= GFX7
)
7570 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7571 else if (ctx
->program
->wave_size
== 64)
7572 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7574 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7575 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7576 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7577 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7579 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7580 nir_print_instr(&instr
->instr
, stderr
);
7581 fprintf(stderr
, "\n");
7586 case nir_intrinsic_load_sample_id
: {
7587 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7588 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7591 case nir_intrinsic_load_sample_mask_in
: {
7592 visit_load_sample_mask_in(ctx
, instr
);
7595 case nir_intrinsic_read_first_invocation
: {
7596 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7597 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7598 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7600 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7602 } else if (src
.regClass() == v2
) {
7603 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7604 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7605 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7606 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7608 emit_split_vector(ctx
, dst
, 2);
7609 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7610 assert(src
.regClass() == bld
.lm
);
7611 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7612 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7613 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7614 } else if (src
.regClass() == s1
) {
7615 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7616 } else if (src
.regClass() == s2
) {
7617 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7619 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7620 nir_print_instr(&instr
->instr
, stderr
);
7621 fprintf(stderr
, "\n");
7625 case nir_intrinsic_vote_all
: {
7626 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7627 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7628 assert(src
.regClass() == bld
.lm
);
7629 assert(dst
.regClass() == bld
.lm
);
7631 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7632 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7633 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7636 case nir_intrinsic_vote_any
: {
7637 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7638 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7639 assert(src
.regClass() == bld
.lm
);
7640 assert(dst
.regClass() == bld
.lm
);
7642 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7643 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7646 case nir_intrinsic_reduce
:
7647 case nir_intrinsic_inclusive_scan
:
7648 case nir_intrinsic_exclusive_scan
: {
7649 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7650 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7651 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7652 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7653 nir_intrinsic_cluster_size(instr
) : 0;
7654 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7656 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7657 emit_uniform_subgroup(ctx
, instr
, src
);
7658 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7659 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7661 else if (op
== nir_op_iadd
)
7663 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7665 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7667 switch (instr
->intrinsic
) {
7668 case nir_intrinsic_reduce
:
7669 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7671 case nir_intrinsic_exclusive_scan
:
7672 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7674 case nir_intrinsic_inclusive_scan
:
7675 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7680 } else if (cluster_size
== 1) {
7681 bld
.copy(Definition(dst
), src
);
7683 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7685 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7689 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7690 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7705 unreachable("unknown reduction op");
7711 switch (instr
->intrinsic
) {
7712 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7713 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7714 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7716 unreachable("unknown reduce intrinsic");
7719 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7720 reduce
->operands
[0] = Operand(src
);
7721 // filled in by aco_reduce_assign.cpp, used internally as part of the
7723 assert(dst
.size() == 1 || dst
.size() == 2);
7724 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7725 reduce
->operands
[2] = Operand(v1
.as_linear());
7727 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7728 reduce
->definitions
[0] = Definition(tmp_dst
);
7729 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7730 reduce
->definitions
[2] = Definition();
7731 reduce
->definitions
[3] = Definition(scc
, s1
);
7732 reduce
->definitions
[4] = Definition();
7733 reduce
->reduce_op
= reduce_op
;
7734 reduce
->cluster_size
= cluster_size
;
7735 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7737 emit_wqm(ctx
, tmp_dst
, dst
);
7741 case nir_intrinsic_quad_broadcast
: {
7742 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7743 if (!nir_dest_is_divergent(instr
->dest
)) {
7744 emit_uniform_subgroup(ctx
, instr
, src
);
7746 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7747 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7748 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7750 if (instr
->dest
.ssa
.bit_size
== 1) {
7751 assert(src
.regClass() == bld
.lm
);
7752 assert(dst
.regClass() == bld
.lm
);
7753 uint32_t half_mask
= 0x11111111u
<< lane
;
7754 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7755 Temp tmp
= bld
.tmp(bld
.lm
);
7756 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7757 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7758 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7759 emit_wqm(ctx
, tmp
, dst
);
7760 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7761 Temp tmp
= bld
.tmp(v1
);
7762 if (ctx
->program
->chip_class
>= GFX8
)
7763 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7765 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7767 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7768 Temp tmp
= bld
.tmp(v1
);
7769 if (ctx
->program
->chip_class
>= GFX8
)
7770 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7772 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7773 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7774 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7775 if (ctx
->program
->chip_class
>= GFX8
)
7776 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7778 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7779 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7780 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7781 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7782 if (ctx
->program
->chip_class
>= GFX8
) {
7783 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7784 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7786 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7787 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7789 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7790 emit_split_vector(ctx
, dst
, 2);
7792 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7793 nir_print_instr(&instr
->instr
, stderr
);
7794 fprintf(stderr
, "\n");
7799 case nir_intrinsic_quad_swap_horizontal
:
7800 case nir_intrinsic_quad_swap_vertical
:
7801 case nir_intrinsic_quad_swap_diagonal
:
7802 case nir_intrinsic_quad_swizzle_amd
: {
7803 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7804 if (!nir_dest_is_divergent(instr
->dest
)) {
7805 emit_uniform_subgroup(ctx
, instr
, src
);
7808 uint16_t dpp_ctrl
= 0;
7809 switch (instr
->intrinsic
) {
7810 case nir_intrinsic_quad_swap_horizontal
:
7811 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7813 case nir_intrinsic_quad_swap_vertical
:
7814 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7816 case nir_intrinsic_quad_swap_diagonal
:
7817 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7819 case nir_intrinsic_quad_swizzle_amd
:
7820 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7825 if (ctx
->program
->chip_class
< GFX8
)
7826 dpp_ctrl
|= (1 << 15);
7828 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7829 if (instr
->dest
.ssa
.bit_size
== 1) {
7830 assert(src
.regClass() == bld
.lm
);
7831 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7832 if (ctx
->program
->chip_class
>= GFX8
)
7833 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7835 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7836 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7837 emit_wqm(ctx
, tmp
, dst
);
7838 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7839 Temp tmp
= bld
.tmp(v1
);
7840 if (ctx
->program
->chip_class
>= GFX8
)
7841 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7843 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7844 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7845 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7846 Temp tmp
= bld
.tmp(v1
);
7847 if (ctx
->program
->chip_class
>= GFX8
)
7848 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7850 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7851 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7852 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7854 if (ctx
->program
->chip_class
>= GFX8
)
7855 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7857 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7858 emit_wqm(ctx
, tmp
, dst
);
7859 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7860 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7862 if (ctx
->program
->chip_class
>= GFX8
) {
7863 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7864 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7866 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7867 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7870 emit_split_vector(ctx
, dst
, 2);
7872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7873 nir_print_instr(&instr
->instr
, stderr
);
7874 fprintf(stderr
, "\n");
7878 case nir_intrinsic_masked_swizzle_amd
: {
7879 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7880 if (!nir_dest_is_divergent(instr
->dest
)) {
7881 emit_uniform_subgroup(ctx
, instr
, src
);
7884 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7885 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7886 if (dst
.regClass() == v1
) {
7888 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7890 } else if (dst
.regClass() == v2
) {
7891 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7893 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7894 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7895 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7896 emit_split_vector(ctx
, dst
, 2);
7898 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7899 nir_print_instr(&instr
->instr
, stderr
);
7900 fprintf(stderr
, "\n");
7904 case nir_intrinsic_write_invocation_amd
: {
7905 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7906 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7907 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7908 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7909 if (dst
.regClass() == v1
) {
7910 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7911 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7912 } else if (dst
.regClass() == v2
) {
7913 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7914 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7915 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7917 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7918 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7919 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7920 emit_split_vector(ctx
, dst
, 2);
7922 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7923 nir_print_instr(&instr
->instr
, stderr
);
7924 fprintf(stderr
, "\n");
7928 case nir_intrinsic_mbcnt_amd
: {
7929 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7930 RegClass rc
= RegClass(src
.type(), 1);
7931 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7933 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7934 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7935 emit_wqm(ctx
, wqm_tmp
, dst
);
7938 case nir_intrinsic_load_helper_invocation
: {
7939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7940 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7941 ctx
->block
->kind
|= block_kind_needs_lowering
;
7942 ctx
->program
->needs_exact
= true;
7945 case nir_intrinsic_is_helper_invocation
: {
7946 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7947 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7948 ctx
->block
->kind
|= block_kind_needs_lowering
;
7949 ctx
->program
->needs_exact
= true;
7952 case nir_intrinsic_demote
:
7953 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7955 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7956 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7957 ctx
->block
->kind
|= block_kind_uses_demote
;
7958 ctx
->program
->needs_exact
= true;
7960 case nir_intrinsic_demote_if
: {
7961 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7962 assert(src
.regClass() == bld
.lm
);
7963 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7964 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7966 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7967 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7968 ctx
->block
->kind
|= block_kind_uses_demote
;
7969 ctx
->program
->needs_exact
= true;
7972 case nir_intrinsic_first_invocation
: {
7973 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7974 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7977 case nir_intrinsic_shader_clock
: {
7979 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7980 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7981 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7982 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7985 case nir_intrinsic_load_vertex_id_zero_base
: {
7986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7987 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7990 case nir_intrinsic_load_first_vertex
: {
7991 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7992 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7995 case nir_intrinsic_load_base_instance
: {
7996 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7997 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8000 case nir_intrinsic_load_instance_id
: {
8001 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8002 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8005 case nir_intrinsic_load_draw_id
: {
8006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8007 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8010 case nir_intrinsic_load_invocation_id
: {
8011 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8013 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8014 if (ctx
->options
->chip_class
>= GFX10
)
8015 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8017 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8018 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8019 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8020 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8022 unreachable("Unsupported stage for load_invocation_id");
8027 case nir_intrinsic_load_primitive_id
: {
8028 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8030 switch (ctx
->shader
->info
.stage
) {
8031 case MESA_SHADER_GEOMETRY
:
8032 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8034 case MESA_SHADER_TESS_CTRL
:
8035 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8037 case MESA_SHADER_TESS_EVAL
:
8038 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8041 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8046 case nir_intrinsic_load_patch_vertices_in
: {
8047 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8048 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8050 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8051 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8054 case nir_intrinsic_emit_vertex_with_counter
: {
8055 visit_emit_vertex_with_counter(ctx
, instr
);
8058 case nir_intrinsic_end_primitive_with_counter
: {
8059 unsigned stream
= nir_intrinsic_stream_id(instr
);
8060 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8063 case nir_intrinsic_set_vertex_count
: {
8064 /* unused, the HW keeps track of this for us */
8068 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8069 nir_print_instr(&instr
->instr
, stderr
);
8070 fprintf(stderr
, "\n");
8078 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8079 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8080 enum glsl_base_type
*stype
)
8082 nir_deref_instr
*texture_deref_instr
= NULL
;
8083 nir_deref_instr
*sampler_deref_instr
= NULL
;
8086 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8087 switch (instr
->src
[i
].src_type
) {
8088 case nir_tex_src_texture_deref
:
8089 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8091 case nir_tex_src_sampler_deref
:
8092 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8094 case nir_tex_src_plane
:
8095 plane
= nir_src_as_int(instr
->src
[i
].src
);
8102 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8104 if (!sampler_deref_instr
)
8105 sampler_deref_instr
= texture_deref_instr
;
8108 assert(instr
->op
!= nir_texop_txf_ms
&&
8109 instr
->op
!= nir_texop_samples_identical
);
8110 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8111 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8112 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8113 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8114 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8115 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8117 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8120 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8122 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8123 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8124 Builder
bld(ctx
->program
, ctx
->block
);
8126 /* to avoid unnecessary moves, we split and recombine sampler and image */
8127 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8128 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8129 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8130 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8131 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8132 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8134 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8136 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8137 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8138 img
[0], img
[1], img
[2], img
[3],
8139 img
[4], img
[5], img
[6], img
[7]);
8140 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8141 samp
[0], samp
[1], samp
[2], samp
[3]);
8144 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8145 instr
->op
== nir_texop_samples_identical
))
8146 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8149 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8150 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8152 Builder
bld(ctx
->program
, ctx
->block
);
8154 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8155 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8156 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8158 Operand
neg_one(0xbf800000u
);
8159 Operand
one(0x3f800000u
);
8160 Operand
two(0x40000000u
);
8161 Operand
four(0x40800000u
);
8163 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8164 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8165 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8167 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8168 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8169 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8170 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8173 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8174 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8175 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8177 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8180 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8181 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8182 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8185 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8186 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8188 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8189 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8192 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8194 Builder
bld(ctx
->program
, ctx
->block
);
8195 Temp ma
, tc
, sc
, id
;
8198 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8200 // see comment in ac_prepare_cube_coords()
8201 if (ctx
->options
->chip_class
<= GFX8
)
8202 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8205 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8207 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8208 vop3a
->operands
[0] = Operand(ma
);
8209 vop3a
->abs
[0] = true;
8210 Temp invma
= bld
.tmp(v1
);
8211 vop3a
->definitions
[0] = Definition(invma
);
8212 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8214 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8216 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8218 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8220 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8222 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8225 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8226 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8228 for (unsigned i
= 0; i
< 2; i
++) {
8229 // see comment in ac_prepare_cube_coords()
8231 Temp deriv_sc
, deriv_tc
;
8232 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8233 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8235 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8237 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8238 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8239 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8240 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8241 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8242 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8243 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8246 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8247 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8251 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8258 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8260 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8262 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8263 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8266 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8267 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8268 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8272 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8274 Builder
bld(ctx
->program
, ctx
->block
);
8275 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8276 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8277 has_clamped_lod
= false;
8278 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8279 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8280 clamped_lod
= Temp();
8281 std::vector
<Temp
> coords
;
8282 std::vector
<Temp
> derivs
;
8283 nir_const_value
*sample_index_cv
= NULL
;
8284 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8285 enum glsl_base_type stype
;
8286 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8288 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8289 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8290 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8291 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8293 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8294 switch (instr
->src
[i
].src_type
) {
8295 case nir_tex_src_coord
: {
8296 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8297 for (unsigned i
= 0; i
< coord
.size(); i
++)
8298 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8301 case nir_tex_src_bias
:
8302 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8305 case nir_tex_src_lod
: {
8306 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8308 if (val
&& val
->f32
<= 0.0) {
8311 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8316 case nir_tex_src_min_lod
:
8317 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8318 has_clamped_lod
= true;
8320 case nir_tex_src_comparator
:
8321 if (instr
->is_shadow
) {
8322 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8326 case nir_tex_src_offset
:
8327 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8328 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8331 case nir_tex_src_ddx
:
8332 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8335 case nir_tex_src_ddy
:
8336 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8339 case nir_tex_src_ms_index
:
8340 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8341 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8342 has_sample_index
= true;
8344 case nir_tex_src_texture_offset
:
8345 case nir_tex_src_sampler_offset
:
8351 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8352 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8354 if (instr
->op
== nir_texop_texture_samples
) {
8355 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8357 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8358 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8359 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8361 Operand default_sample
= Operand(1u);
8362 if (ctx
->options
->robust_buffer_access
) {
8363 /* Extract the second dword of the descriptor, if it's
8364 * all zero, then it's a null descriptor.
8366 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8367 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8368 default_sample
= Operand(is_non_null_descriptor
);
8371 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8372 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8373 samples
, default_sample
, bld
.scc(is_msaa
));
8377 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8378 aco_ptr
<Instruction
> tmp_instr
;
8379 Temp acc
, pack
= Temp();
8381 uint32_t pack_const
= 0;
8382 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8383 if (!const_offset
[i
])
8385 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8388 if (offset
.type() == RegType::sgpr
) {
8389 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8390 if (const_offset
[i
])
8393 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8394 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8397 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8400 if (pack
== Temp()) {
8403 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8407 if (pack_const
&& pack
!= Temp())
8408 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8410 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8411 if (const_offset
[i
])
8414 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8415 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8418 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8421 if (pack
== Temp()) {
8424 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8428 if (pack_const
&& pack
!= Temp())
8429 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8431 if (pack_const
&& pack
== Temp())
8432 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8433 else if (pack
== Temp())
8439 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8440 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8442 /* pack derivatives */
8443 if (has_ddx
|| has_ddy
) {
8444 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8445 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8446 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8447 derivs
= {ddx
, zero
, ddy
, zero
};
8449 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8450 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8451 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8452 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8457 if (instr
->coord_components
> 1 &&
8458 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8460 instr
->op
!= nir_texop_txf
)
8461 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8463 if (instr
->coord_components
> 2 &&
8464 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8465 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8466 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8467 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8469 instr
->op
!= nir_texop_txf
&&
8470 instr
->op
!= nir_texop_txf_ms
&&
8471 instr
->op
!= nir_texop_fragment_fetch
&&
8472 instr
->op
!= nir_texop_fragment_mask_fetch
)
8473 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8475 if (ctx
->options
->chip_class
== GFX9
&&
8476 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8477 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8478 assert(coords
.size() > 0 && coords
.size() < 3);
8480 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8481 Operand((uint32_t) 0) :
8482 Operand((uint32_t) 0x3f000000)));
8485 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8487 if (instr
->op
== nir_texop_samples_identical
)
8488 resource
= fmask_ptr
;
8490 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8491 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8492 instr
->op
!= nir_texop_txs
&&
8493 instr
->op
!= nir_texop_fragment_fetch
&&
8494 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8495 assert(has_sample_index
);
8496 Operand
op(sample_index
);
8497 if (sample_index_cv
)
8498 op
= Operand(sample_index_cv
->u32
);
8499 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8502 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8503 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8504 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8505 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8510 /* Build tex instruction */
8511 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8512 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8513 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8515 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8518 /* gather4 selects the component by dmask and always returns vec4 */
8519 if (instr
->op
== nir_texop_tg4
) {
8520 assert(instr
->dest
.ssa
.num_components
== 4);
8521 if (instr
->is_shadow
)
8524 dmask
= 1 << instr
->component
;
8525 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8526 tmp_dst
= bld
.tmp(v4
);
8527 } else if (instr
->op
== nir_texop_samples_identical
) {
8528 tmp_dst
= bld
.tmp(v1
);
8529 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8530 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8533 aco_ptr
<MIMG_instruction
> tex
;
8534 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8536 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8538 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8539 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8542 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8543 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8545 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8546 tex
->operands
[0] = Operand(resource
);
8547 tex
->operands
[1] = Operand(s4
); /* no sampler */
8548 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8549 if (ctx
->options
->chip_class
== GFX9
&&
8550 instr
->op
== nir_texop_txs
&&
8551 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8553 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8554 } else if (instr
->op
== nir_texop_query_levels
) {
8555 tex
->dmask
= 1 << 3;
8560 tex
->definitions
[0] = Definition(tmp_dst
);
8562 tex
->can_reorder
= true;
8563 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8566 /* divide 3rd value by 6 by multiplying with magic number */
8567 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8568 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8569 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8570 assert(instr
->dest
.ssa
.num_components
== 3);
8571 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8572 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8573 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8574 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8579 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8583 Temp tg4_compare_cube_wa64
= Temp();
8585 if (tg4_integer_workarounds
) {
8586 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8587 tex
->operands
[0] = Operand(resource
);
8588 tex
->operands
[1] = Operand(s4
); /* no sampler */
8589 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8593 Temp size
= bld
.tmp(v2
);
8594 tex
->definitions
[0] = Definition(size
);
8595 tex
->can_reorder
= true;
8596 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8597 emit_split_vector(ctx
, size
, size
.size());
8600 for (unsigned i
= 0; i
< 2; i
++) {
8601 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8602 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8603 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8604 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8607 Temp new_coords
[2] = {
8608 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8609 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8612 if (tg4_integer_cube_workaround
) {
8613 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8614 Temp desc
[resource
.size()];
8615 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8616 Format::PSEUDO
, 1, resource
.size())};
8617 split
->operands
[0] = Operand(resource
);
8618 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8619 desc
[i
] = bld
.tmp(s1
);
8620 split
->definitions
[i
] = Definition(desc
[i
]);
8622 ctx
->block
->instructions
.emplace_back(std::move(split
));
8624 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8625 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8626 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8629 if (stype
== GLSL_TYPE_UINT
) {
8630 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8631 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8632 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8633 bld
.scc(compare_cube_wa
));
8635 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8636 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8637 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8638 bld
.scc(compare_cube_wa
));
8640 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8641 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8643 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8645 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8646 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8647 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8649 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8650 Format::PSEUDO
, resource
.size(), 1)};
8651 for (unsigned i
= 0; i
< resource
.size(); i
++)
8652 vec
->operands
[i
] = Operand(desc
[i
]);
8653 resource
= bld
.tmp(resource
.regClass());
8654 vec
->definitions
[0] = Definition(resource
);
8655 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8657 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8658 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8659 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8660 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8662 coords
[0] = new_coords
[0];
8663 coords
[1] = new_coords
[1];
8666 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8667 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8669 assert(coords
.size() == 1);
8670 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8674 op
= aco_opcode::buffer_load_format_x
; break;
8676 op
= aco_opcode::buffer_load_format_xy
; break;
8678 op
= aco_opcode::buffer_load_format_xyz
; break;
8680 op
= aco_opcode::buffer_load_format_xyzw
; break;
8682 unreachable("Tex instruction loads more than 4 components.");
8685 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8686 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8689 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8691 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8692 mubuf
->operands
[0] = Operand(resource
);
8693 mubuf
->operands
[1] = Operand(coords
[0]);
8694 mubuf
->operands
[2] = Operand((uint32_t) 0);
8695 mubuf
->definitions
[0] = Definition(tmp_dst
);
8696 mubuf
->idxen
= true;
8697 mubuf
->can_reorder
= true;
8698 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8700 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8704 /* gather MIMG address components */
8705 std::vector
<Temp
> args
;
8707 args
.emplace_back(offset
);
8709 args
.emplace_back(bias
);
8711 args
.emplace_back(compare
);
8713 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8715 args
.insert(args
.end(), coords
.begin(), coords
.end());
8716 if (has_sample_index
)
8717 args
.emplace_back(sample_index
);
8719 args
.emplace_back(lod
);
8720 if (has_clamped_lod
)
8721 args
.emplace_back(clamped_lod
);
8723 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8724 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8725 vec
->definitions
[0] = Definition(arg
);
8726 for (unsigned i
= 0; i
< args
.size(); i
++)
8727 vec
->operands
[i
] = Operand(args
[i
]);
8728 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8731 if (instr
->op
== nir_texop_txf
||
8732 instr
->op
== nir_texop_txf_ms
||
8733 instr
->op
== nir_texop_samples_identical
||
8734 instr
->op
== nir_texop_fragment_fetch
||
8735 instr
->op
== nir_texop_fragment_mask_fetch
) {
8736 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8737 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8738 tex
->operands
[0] = Operand(resource
);
8739 tex
->operands
[1] = Operand(s4
); /* no sampler */
8740 tex
->operands
[2] = Operand(arg
);
8745 tex
->definitions
[0] = Definition(tmp_dst
);
8746 tex
->can_reorder
= true;
8747 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8749 if (instr
->op
== nir_texop_samples_identical
) {
8750 assert(dmask
== 1 && dst
.regClass() == v1
);
8751 assert(dst
.id() != tmp_dst
.id());
8753 Temp tmp
= bld
.tmp(bld
.lm
);
8754 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8755 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8758 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8763 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8764 aco_opcode opcode
= aco_opcode::image_sample
;
8765 if (has_offset
) { /* image_sample_*_o */
8766 if (has_clamped_lod
) {
8768 opcode
= aco_opcode::image_sample_c_cl_o
;
8770 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8772 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8774 opcode
= aco_opcode::image_sample_cl_o
;
8776 opcode
= aco_opcode::image_sample_d_cl_o
;
8778 opcode
= aco_opcode::image_sample_b_cl_o
;
8780 } else if (has_compare
) {
8781 opcode
= aco_opcode::image_sample_c_o
;
8783 opcode
= aco_opcode::image_sample_c_d_o
;
8785 opcode
= aco_opcode::image_sample_c_b_o
;
8787 opcode
= aco_opcode::image_sample_c_lz_o
;
8789 opcode
= aco_opcode::image_sample_c_l_o
;
8791 opcode
= aco_opcode::image_sample_o
;
8793 opcode
= aco_opcode::image_sample_d_o
;
8795 opcode
= aco_opcode::image_sample_b_o
;
8797 opcode
= aco_opcode::image_sample_lz_o
;
8799 opcode
= aco_opcode::image_sample_l_o
;
8801 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8803 opcode
= aco_opcode::image_sample_c_cl
;
8805 opcode
= aco_opcode::image_sample_c_d_cl
;
8807 opcode
= aco_opcode::image_sample_c_b_cl
;
8809 opcode
= aco_opcode::image_sample_cl
;
8811 opcode
= aco_opcode::image_sample_d_cl
;
8813 opcode
= aco_opcode::image_sample_b_cl
;
8815 } else { /* no offset */
8817 opcode
= aco_opcode::image_sample_c
;
8819 opcode
= aco_opcode::image_sample_c_d
;
8821 opcode
= aco_opcode::image_sample_c_b
;
8823 opcode
= aco_opcode::image_sample_c_lz
;
8825 opcode
= aco_opcode::image_sample_c_l
;
8827 opcode
= aco_opcode::image_sample
;
8829 opcode
= aco_opcode::image_sample_d
;
8831 opcode
= aco_opcode::image_sample_b
;
8833 opcode
= aco_opcode::image_sample_lz
;
8835 opcode
= aco_opcode::image_sample_l
;
8839 if (instr
->op
== nir_texop_tg4
) {
8840 if (has_offset
) { /* image_gather4_*_o */
8842 opcode
= aco_opcode::image_gather4_c_lz_o
;
8844 opcode
= aco_opcode::image_gather4_c_l_o
;
8846 opcode
= aco_opcode::image_gather4_c_b_o
;
8848 opcode
= aco_opcode::image_gather4_lz_o
;
8850 opcode
= aco_opcode::image_gather4_l_o
;
8852 opcode
= aco_opcode::image_gather4_b_o
;
8856 opcode
= aco_opcode::image_gather4_c_lz
;
8858 opcode
= aco_opcode::image_gather4_c_l
;
8860 opcode
= aco_opcode::image_gather4_c_b
;
8862 opcode
= aco_opcode::image_gather4_lz
;
8864 opcode
= aco_opcode::image_gather4_l
;
8866 opcode
= aco_opcode::image_gather4_b
;
8869 } else if (instr
->op
== nir_texop_lod
) {
8870 opcode
= aco_opcode::image_get_lod
;
8873 /* we don't need the bias, sample index, compare value or offset to be
8874 * computed in WQM but if the p_create_vector copies the coordinates, then it
8875 * needs to be in WQM */
8876 if (ctx
->stage
== fragment_fs
&&
8877 !has_derivs
&& !has_lod
&& !level_zero
&&
8878 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8879 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8880 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8882 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8883 tex
->operands
[0] = Operand(resource
);
8884 tex
->operands
[1] = Operand(sampler
);
8885 tex
->operands
[2] = Operand(arg
);
8889 tex
->definitions
[0] = Definition(tmp_dst
);
8890 tex
->can_reorder
= true;
8891 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8893 if (tg4_integer_cube_workaround
) {
8894 assert(tmp_dst
.id() != dst
.id());
8895 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8897 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8899 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8900 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8902 if (stype
== GLSL_TYPE_UINT
)
8903 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8905 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8906 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8908 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8909 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8910 val
[0], val
[1], val
[2], val
[3]);
8912 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8913 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8918 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8920 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8921 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8922 return Operand(tmp
.regClass());
8924 return Operand(tmp
);
8927 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8929 aco_ptr
<Pseudo_instruction
> phi
;
8930 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8931 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8933 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8934 logical
|= ctx
->block
->kind
& block_kind_merge
;
8935 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8937 /* we want a sorted list of sources, since the predecessor list is also sorted */
8938 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8939 nir_foreach_phi_src(src
, instr
)
8940 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8942 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8943 unsigned num_operands
= 0;
8944 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8945 unsigned num_defined
= 0;
8946 unsigned cur_pred_idx
= 0;
8947 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8948 if (cur_pred_idx
< preds
.size()) {
8949 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8950 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8951 unsigned skipped
= 0;
8952 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8954 if (cur_pred_idx
+ skipped
< preds
.size()) {
8955 for (unsigned i
= 0; i
< skipped
; i
++)
8956 operands
[num_operands
++] = Operand(dst
.regClass());
8957 cur_pred_idx
+= skipped
;
8962 /* Handle missing predecessors at the end. This shouldn't happen with loop
8963 * headers and we can't ignore these sources for loop header phis. */
8964 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8967 Operand op
= get_phi_operand(ctx
, src
.second
);
8968 operands
[num_operands
++] = op
;
8969 num_defined
+= !op
.isUndefined();
8971 /* handle block_kind_continue_or_break at loop exit blocks */
8972 while (cur_pred_idx
++ < preds
.size())
8973 operands
[num_operands
++] = Operand(dst
.regClass());
8975 /* If the loop ends with a break, still add a linear continue edge in case
8976 * that break is divergent or continue_or_break is used. We'll either remove
8977 * this operand later in visit_loop() if it's not necessary or replace the
8978 * undef with something correct. */
8979 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8980 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8981 nir_block
*last
= nir_loop_last_block(loop
);
8982 if (last
->successors
[0] != instr
->instr
.block
)
8983 operands
[num_operands
++] = Operand(RegClass());
8986 if (num_defined
== 0) {
8987 Builder
bld(ctx
->program
, ctx
->block
);
8988 if (dst
.regClass() == s1
) {
8989 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8990 } else if (dst
.regClass() == v1
) {
8991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8993 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8994 for (unsigned i
= 0; i
< dst
.size(); i
++)
8995 vec
->operands
[i
] = Operand(0u);
8996 vec
->definitions
[0] = Definition(dst
);
8997 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9002 /* we can use a linear phi in some cases if one src is undef */
9003 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9004 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9006 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9007 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9008 assert(invert
->kind
& block_kind_invert
);
9010 unsigned then_block
= invert
->linear_preds
[0];
9012 Block
* insert_block
= NULL
;
9013 for (unsigned i
= 0; i
< num_operands
; i
++) {
9014 Operand op
= operands
[i
];
9015 if (op
.isUndefined())
9017 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9018 phi
->operands
[0] = op
;
9021 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9022 phi
->operands
[1] = Operand(dst
.regClass());
9023 phi
->definitions
[0] = Definition(dst
);
9024 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9028 /* try to scalarize vector phis */
9029 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9030 // TODO: scalarize linear phis on divergent ifs
9031 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9032 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9033 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9034 Operand src
= operands
[i
];
9035 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9036 can_scalarize
= false;
9038 if (can_scalarize
) {
9039 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9040 assert(dst
.size() % num_components
== 0);
9041 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9043 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9044 for (unsigned k
= 0; k
< num_components
; k
++) {
9045 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9046 for (unsigned i
= 0; i
< num_operands
; i
++) {
9047 Operand src
= operands
[i
];
9048 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9050 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9051 phi
->definitions
[0] = Definition(phi_dst
);
9052 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9053 new_vec
[k
] = phi_dst
;
9054 vec
->operands
[k
] = Operand(phi_dst
);
9056 vec
->definitions
[0] = Definition(dst
);
9057 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9058 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9063 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9064 for (unsigned i
= 0; i
< num_operands
; i
++)
9065 phi
->operands
[i
] = operands
[i
];
9066 phi
->definitions
[0] = Definition(dst
);
9067 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9071 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9073 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9075 assert(dst
.type() == RegType::sgpr
);
9077 if (dst
.size() == 1) {
9078 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9080 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9081 for (unsigned i
= 0; i
< dst
.size(); i
++)
9082 vec
->operands
[i
] = Operand(0u);
9083 vec
->definitions
[0] = Definition(dst
);
9084 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9088 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9090 Builder
bld(ctx
->program
, ctx
->block
);
9091 Block
*logical_target
;
9092 append_logical_end(ctx
->block
);
9093 unsigned idx
= ctx
->block
->index
;
9095 switch (instr
->type
) {
9096 case nir_jump_break
:
9097 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9098 add_logical_edge(idx
, logical_target
);
9099 ctx
->block
->kind
|= block_kind_break
;
9101 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9102 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9103 /* uniform break - directly jump out of the loop */
9104 ctx
->block
->kind
|= block_kind_uniform
;
9105 ctx
->cf_info
.has_branch
= true;
9106 bld
.branch(aco_opcode::p_branch
);
9107 add_linear_edge(idx
, logical_target
);
9110 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9111 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9113 case nir_jump_continue
:
9114 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9115 add_logical_edge(idx
, logical_target
);
9116 ctx
->block
->kind
|= block_kind_continue
;
9118 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9119 /* for potential uniform breaks after this continue,
9120 we must ensure that they are handled correctly */
9121 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9122 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9123 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9125 /* uniform continue - directly jump to the loop header */
9126 ctx
->block
->kind
|= block_kind_uniform
;
9127 ctx
->cf_info
.has_branch
= true;
9128 bld
.branch(aco_opcode::p_branch
);
9129 add_linear_edge(idx
, logical_target
);
9134 fprintf(stderr
, "Unknown NIR jump instr: ");
9135 nir_print_instr(&instr
->instr
, stderr
);
9136 fprintf(stderr
, "\n");
9140 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9141 ctx
->cf_info
.exec_potentially_empty_break
= true;
9142 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9145 /* remove critical edges from linear CFG */
9146 bld
.branch(aco_opcode::p_branch
);
9147 Block
* break_block
= ctx
->program
->create_and_insert_block();
9148 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9149 break_block
->kind
|= block_kind_uniform
;
9150 add_linear_edge(idx
, break_block
);
9151 /* the loop_header pointer might be invalidated by this point */
9152 if (instr
->type
== nir_jump_continue
)
9153 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9154 add_linear_edge(break_block
->index
, logical_target
);
9155 bld
.reset(break_block
);
9156 bld
.branch(aco_opcode::p_branch
);
9158 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9159 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9160 add_linear_edge(idx
, continue_block
);
9161 append_logical_start(continue_block
);
9162 ctx
->block
= continue_block
;
9166 void visit_block(isel_context
*ctx
, nir_block
*block
)
9168 nir_foreach_instr(instr
, block
) {
9169 switch (instr
->type
) {
9170 case nir_instr_type_alu
:
9171 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9173 case nir_instr_type_load_const
:
9174 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9176 case nir_instr_type_intrinsic
:
9177 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9179 case nir_instr_type_tex
:
9180 visit_tex(ctx
, nir_instr_as_tex(instr
));
9182 case nir_instr_type_phi
:
9183 visit_phi(ctx
, nir_instr_as_phi(instr
));
9185 case nir_instr_type_ssa_undef
:
9186 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9188 case nir_instr_type_deref
:
9190 case nir_instr_type_jump
:
9191 visit_jump(ctx
, nir_instr_as_jump(instr
));
9194 fprintf(stderr
, "Unknown NIR instr type: ");
9195 nir_print_instr(instr
, stderr
);
9196 fprintf(stderr
, "\n");
9201 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9202 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9207 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9208 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9210 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9211 RegClass rc
= vals
[0].regClass();
9213 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9215 unsigned next_pred
= 1;
9217 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9218 Block
& block
= ctx
->program
->blocks
[idx
];
9219 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9220 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9224 if (block
.kind
& block_kind_continue
) {
9225 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9230 bool all_same
= true;
9231 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9232 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9236 val
= vals
[block
.linear_preds
[0] - first
];
9238 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9239 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9240 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9241 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9242 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9243 phi
->definitions
[0] = Definition(val
.getTemp());
9244 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9246 vals
[idx
- first
] = val
;
9249 return vals
[last
- first
];
9252 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9254 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9255 append_logical_end(ctx
->block
);
9256 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9257 Builder
bld(ctx
->program
, ctx
->block
);
9258 bld
.branch(aco_opcode::p_branch
);
9259 unsigned loop_preheader_idx
= ctx
->block
->index
;
9261 Block loop_exit
= Block();
9262 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9263 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9265 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9266 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9267 loop_header
->kind
|= block_kind_loop_header
;
9268 add_edge(loop_preheader_idx
, loop_header
);
9269 ctx
->block
= loop_header
;
9271 /* emit loop body */
9272 unsigned loop_header_idx
= loop_header
->index
;
9273 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9274 append_logical_start(ctx
->block
);
9275 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9277 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9278 if (!ctx
->cf_info
.has_branch
) {
9279 append_logical_end(ctx
->block
);
9280 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9281 /* Discards can result in code running with an empty exec mask.
9282 * This would result in divergent breaks not ever being taken. As a
9283 * workaround, break the loop when the loop mask is empty instead of
9284 * always continuing. */
9285 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9286 unsigned block_idx
= ctx
->block
->index
;
9288 /* create helper blocks to avoid critical edges */
9289 Block
*break_block
= ctx
->program
->create_and_insert_block();
9290 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9291 break_block
->kind
= block_kind_uniform
;
9292 bld
.reset(break_block
);
9293 bld
.branch(aco_opcode::p_branch
);
9294 add_linear_edge(block_idx
, break_block
);
9295 add_linear_edge(break_block
->index
, &loop_exit
);
9297 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9298 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9299 continue_block
->kind
= block_kind_uniform
;
9300 bld
.reset(continue_block
);
9301 bld
.branch(aco_opcode::p_branch
);
9302 add_linear_edge(block_idx
, continue_block
);
9303 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9305 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9306 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9307 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9309 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9310 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9311 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9313 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9316 bld
.reset(ctx
->block
);
9317 bld
.branch(aco_opcode::p_branch
);
9320 /* Fixup phis in loop header from unreachable blocks.
9321 * has_branch/has_divergent_branch also indicates if the loop ends with a
9322 * break/continue instruction, but we don't emit those if unreachable=true */
9324 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9325 bool linear
= ctx
->cf_info
.has_branch
;
9326 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9327 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9328 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9329 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9330 /* the last operand should be the one that needs to be removed */
9331 instr
->operands
.pop_back();
9332 } else if (!is_phi(instr
)) {
9338 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9339 * and the previous one shouldn't both happen at once because a break in the
9340 * merge block would get CSE'd */
9341 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9342 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9343 Operand vals
[num_vals
];
9344 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9345 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9346 if (ctx
->cf_info
.has_branch
)
9347 instr
->operands
.pop_back();
9349 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9350 } else if (!is_phi(instr
)) {
9356 ctx
->cf_info
.has_branch
= false;
9358 // TODO: if the loop has not a single exit, we must add one °°
9359 /* emit loop successor block */
9360 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9361 append_logical_start(ctx
->block
);
9364 // TODO: check if it is beneficial to not branch on continues
9365 /* trim linear phis in loop header */
9366 for (auto&& instr
: loop_entry
->instructions
) {
9367 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9368 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9369 new_phi
->definitions
[0] = instr
->definitions
[0];
9370 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9371 new_phi
->operands
[i
] = instr
->operands
[i
];
9372 /* check that the remaining operands are all the same */
9373 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9374 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9375 instr
.swap(new_phi
);
9376 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9385 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9389 append_logical_end(ctx
->block
);
9390 ctx
->block
->kind
|= block_kind_branch
;
9392 /* branch to linear then block */
9393 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9394 aco_ptr
<Pseudo_branch_instruction
> branch
;
9395 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9396 branch
->operands
[0] = Operand(cond
);
9397 ctx
->block
->instructions
.push_back(std::move(branch
));
9399 ic
->BB_if_idx
= ctx
->block
->index
;
9400 ic
->BB_invert
= Block();
9401 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9402 /* Invert blocks are intentionally not marked as top level because they
9403 * are not part of the logical cfg. */
9404 ic
->BB_invert
.kind
|= block_kind_invert
;
9405 ic
->BB_endif
= Block();
9406 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9407 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9409 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9410 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9411 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9412 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9413 ctx
->cf_info
.parent_if
.is_divergent
= true;
9415 /* divergent branches use cbranch_execz */
9416 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9417 ctx
->cf_info
.exec_potentially_empty_break
= false;
9418 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9420 /** emit logical then block */
9421 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9422 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9423 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9424 ctx
->block
= BB_then_logical
;
9425 append_logical_start(BB_then_logical
);
9428 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9430 Block
*BB_then_logical
= ctx
->block
;
9431 append_logical_end(BB_then_logical
);
9432 /* branch from logical then block to invert block */
9433 aco_ptr
<Pseudo_branch_instruction
> branch
;
9434 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9435 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9436 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9437 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9438 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9439 BB_then_logical
->kind
|= block_kind_uniform
;
9440 assert(!ctx
->cf_info
.has_branch
);
9441 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9442 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9444 /** emit linear then block */
9445 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9446 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9447 BB_then_linear
->kind
|= block_kind_uniform
;
9448 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9449 /* branch from linear then block to invert block */
9450 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9451 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9452 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9454 /** emit invert merge block */
9455 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9456 ic
->invert_idx
= ctx
->block
->index
;
9458 /* branch to linear else block (skip else) */
9459 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9460 branch
->operands
[0] = Operand(ic
->cond
);
9461 ctx
->block
->instructions
.push_back(std::move(branch
));
9463 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9464 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9465 ic
->exec_potentially_empty_break_depth_old
=
9466 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9467 /* divergent branches use cbranch_execz */
9468 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9469 ctx
->cf_info
.exec_potentially_empty_break
= false;
9470 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9472 /** emit logical else block */
9473 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9474 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9475 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9476 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9477 ctx
->block
= BB_else_logical
;
9478 append_logical_start(BB_else_logical
);
9481 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9483 Block
*BB_else_logical
= ctx
->block
;
9484 append_logical_end(BB_else_logical
);
9486 /* branch from logical else block to endif block */
9487 aco_ptr
<Pseudo_branch_instruction
> branch
;
9488 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9489 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9490 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9491 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9492 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9493 BB_else_logical
->kind
|= block_kind_uniform
;
9495 assert(!ctx
->cf_info
.has_branch
);
9496 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9499 /** emit linear else block */
9500 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9501 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9502 BB_else_linear
->kind
|= block_kind_uniform
;
9503 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9505 /* branch from linear else block to endif block */
9506 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9507 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9508 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9511 /** emit endif merge block */
9512 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9513 append_logical_start(ctx
->block
);
9516 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9517 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9518 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9519 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9520 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9521 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9522 !ctx
->cf_info
.parent_if
.is_divergent
) {
9523 ctx
->cf_info
.exec_potentially_empty_break
= false;
9524 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9526 /* uniform control flow never has an empty exec-mask */
9527 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9528 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9529 ctx
->cf_info
.exec_potentially_empty_break
= false;
9530 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9534 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9536 assert(cond
.regClass() == s1
);
9538 append_logical_end(ctx
->block
);
9539 ctx
->block
->kind
|= block_kind_uniform
;
9541 aco_ptr
<Pseudo_branch_instruction
> branch
;
9542 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9543 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9544 branch
->operands
[0] = Operand(cond
);
9545 branch
->operands
[0].setFixed(scc
);
9546 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9548 ic
->BB_if_idx
= ctx
->block
->index
;
9549 ic
->BB_endif
= Block();
9550 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9551 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9553 ctx
->cf_info
.has_branch
= false;
9554 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9556 /** emit then block */
9557 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9558 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9559 add_edge(ic
->BB_if_idx
, BB_then
);
9560 append_logical_start(BB_then
);
9561 ctx
->block
= BB_then
;
9564 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9566 Block
*BB_then
= ctx
->block
;
9568 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9569 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9571 if (!ic
->uniform_has_then_branch
) {
9572 append_logical_end(BB_then
);
9573 /* branch from then block to endif block */
9574 aco_ptr
<Pseudo_branch_instruction
> branch
;
9575 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9576 BB_then
->instructions
.emplace_back(std::move(branch
));
9577 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9578 if (!ic
->then_branch_divergent
)
9579 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9580 BB_then
->kind
|= block_kind_uniform
;
9583 ctx
->cf_info
.has_branch
= false;
9584 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9586 /** emit else block */
9587 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9588 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9589 add_edge(ic
->BB_if_idx
, BB_else
);
9590 append_logical_start(BB_else
);
9591 ctx
->block
= BB_else
;
9594 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9596 Block
*BB_else
= ctx
->block
;
9598 if (!ctx
->cf_info
.has_branch
) {
9599 append_logical_end(BB_else
);
9600 /* branch from then block to endif block */
9601 aco_ptr
<Pseudo_branch_instruction
> branch
;
9602 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9603 BB_else
->instructions
.emplace_back(std::move(branch
));
9604 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9605 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9606 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9607 BB_else
->kind
|= block_kind_uniform
;
9610 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9611 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9613 /** emit endif merge block */
9614 if (!ctx
->cf_info
.has_branch
) {
9615 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9616 append_logical_start(ctx
->block
);
9620 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9622 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9623 Builder
bld(ctx
->program
, ctx
->block
);
9624 aco_ptr
<Pseudo_branch_instruction
> branch
;
9627 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9629 * Uniform conditionals are represented in the following way*) :
9631 * The linear and logical CFG:
9634 * BB_THEN (logical) BB_ELSE (logical)
9638 * *) Exceptions may be due to break and continue statements within loops
9639 * If a break/continue happens within uniform control flow, it branches
9640 * to the loop exit/entry block. Otherwise, it branches to the next
9644 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9645 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9646 cond
= bool_to_scalar_condition(ctx
, cond
);
9648 begin_uniform_if_then(ctx
, &ic
, cond
);
9649 visit_cf_list(ctx
, &if_stmt
->then_list
);
9651 begin_uniform_if_else(ctx
, &ic
);
9652 visit_cf_list(ctx
, &if_stmt
->else_list
);
9654 end_uniform_if(ctx
, &ic
);
9655 } else { /* non-uniform condition */
9657 * To maintain a logical and linear CFG without critical edges,
9658 * non-uniform conditionals are represented in the following way*) :
9663 * BB_THEN (logical) BB_THEN (linear)
9665 * BB_INVERT (linear)
9667 * BB_ELSE (logical) BB_ELSE (linear)
9674 * BB_THEN (logical) BB_ELSE (logical)
9678 * *) Exceptions may be due to break and continue statements within loops
9681 begin_divergent_if_then(ctx
, &ic
, cond
);
9682 visit_cf_list(ctx
, &if_stmt
->then_list
);
9684 begin_divergent_if_else(ctx
, &ic
);
9685 visit_cf_list(ctx
, &if_stmt
->else_list
);
9687 end_divergent_if(ctx
, &ic
);
9690 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9693 static bool visit_cf_list(isel_context
*ctx
,
9694 struct exec_list
*list
)
9696 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9697 switch (node
->type
) {
9698 case nir_cf_node_block
:
9699 visit_block(ctx
, nir_cf_node_as_block(node
));
9701 case nir_cf_node_if
:
9702 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9705 case nir_cf_node_loop
:
9706 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9709 unreachable("unimplemented cf list type");
9715 static void create_null_export(isel_context
*ctx
)
9717 /* Some shader stages always need to have exports.
9718 * So when there is none, we need to add a null export.
9721 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9722 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9723 Builder
bld(ctx
->program
, ctx
->block
);
9724 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9725 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9728 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9730 assert(ctx
->stage
== vertex_vs
||
9731 ctx
->stage
== tess_eval_vs
||
9732 ctx
->stage
== gs_copy_vs
||
9733 ctx
->stage
== ngg_vertex_gs
||
9734 ctx
->stage
== ngg_tess_eval_gs
);
9736 int offset
= (ctx
->stage
& sw_tes
)
9737 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9738 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9739 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9740 if (!is_pos
&& !mask
)
9742 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9744 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9745 exp
->enabled_mask
= mask
;
9746 for (unsigned i
= 0; i
< 4; ++i
) {
9747 if (mask
& (1 << i
))
9748 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9750 exp
->operands
[i
] = Operand(v1
);
9752 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9753 * Setting valid_mask=1 prevents it and has no other effect.
9755 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9757 exp
->compressed
= false;
9759 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9761 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9762 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9767 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9769 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9770 exp
->enabled_mask
= 0;
9771 for (unsigned i
= 0; i
< 4; ++i
)
9772 exp
->operands
[i
] = Operand(v1
);
9773 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9774 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9775 exp
->enabled_mask
|= 0x1;
9777 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9778 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9779 exp
->enabled_mask
|= 0x4;
9781 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9782 if (ctx
->options
->chip_class
< GFX9
) {
9783 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9784 exp
->enabled_mask
|= 0x8;
9786 Builder
bld(ctx
->program
, ctx
->block
);
9788 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9789 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9790 if (exp
->operands
[2].isTemp())
9791 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9793 exp
->operands
[2] = Operand(out
);
9794 exp
->enabled_mask
|= 0x4;
9797 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9799 exp
->compressed
= false;
9800 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9801 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9804 static void create_export_phis(isel_context
*ctx
)
9806 /* Used when exports are needed, but the output temps are defined in a preceding block.
9807 * This function will set up phis in order to access the outputs in the next block.
9810 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9811 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9812 ctx
->block
->instructions
.pop_back();
9814 Builder
bld(ctx
->program
, ctx
->block
);
9816 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9817 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9818 for (unsigned i
= 0; i
< 4; ++i
) {
9819 if (!(mask
& (1 << i
)))
9822 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9823 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9824 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9828 bld
.insert(std::move(logical_start
));
9831 static void create_vs_exports(isel_context
*ctx
)
9833 assert(ctx
->stage
== vertex_vs
||
9834 ctx
->stage
== tess_eval_vs
||
9835 ctx
->stage
== gs_copy_vs
||
9836 ctx
->stage
== ngg_vertex_gs
||
9837 ctx
->stage
== ngg_tess_eval_gs
);
9839 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9840 ? &ctx
->program
->info
->tes
.outinfo
9841 : &ctx
->program
->info
->vs
.outinfo
;
9843 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9844 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9845 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9848 if (ctx
->options
->key
.has_multiview_view_index
) {
9849 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9850 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9853 /* the order these position exports are created is important */
9855 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9856 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9857 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9858 exported_pos
= true;
9860 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9861 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9862 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9863 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9865 if (ctx
->export_clip_dists
) {
9866 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9867 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9868 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9869 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9872 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9873 if (i
< VARYING_SLOT_VAR0
&&
9874 i
!= VARYING_SLOT_LAYER
&&
9875 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9876 i
!= VARYING_SLOT_VIEWPORT
)
9879 export_vs_varying(ctx
, i
, false, NULL
);
9883 create_null_export(ctx
);
9886 static bool export_fs_mrt_z(isel_context
*ctx
)
9888 Builder
bld(ctx
->program
, ctx
->block
);
9889 unsigned enabled_channels
= 0;
9893 for (unsigned i
= 0; i
< 4; ++i
) {
9894 values
[i
] = Operand(v1
);
9897 /* Both stencil and sample mask only need 16-bits. */
9898 if (!ctx
->program
->info
->ps
.writes_z
&&
9899 (ctx
->program
->info
->ps
.writes_stencil
||
9900 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9901 compr
= true; /* COMPR flag */
9903 if (ctx
->program
->info
->ps
.writes_stencil
) {
9904 /* Stencil should be in X[23:16]. */
9905 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9906 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9907 enabled_channels
|= 0x3;
9910 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9911 /* SampleMask should be in Y[15:0]. */
9912 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9913 enabled_channels
|= 0xc;
9916 if (ctx
->program
->info
->ps
.writes_z
) {
9917 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9918 enabled_channels
|= 0x1;
9921 if (ctx
->program
->info
->ps
.writes_stencil
) {
9922 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9923 enabled_channels
|= 0x2;
9926 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9927 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9928 enabled_channels
|= 0x4;
9932 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9933 * writemask component.
9935 if (ctx
->options
->chip_class
== GFX6
&&
9936 ctx
->options
->family
!= CHIP_OLAND
&&
9937 ctx
->options
->family
!= CHIP_HAINAN
) {
9938 enabled_channels
|= 0x1;
9941 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9942 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9947 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9949 Builder
bld(ctx
->program
, ctx
->block
);
9950 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9953 for (unsigned i
= 0; i
< 4; ++i
) {
9954 if (write_mask
& (1 << i
)) {
9955 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9957 values
[i
] = Operand(v1
);
9961 unsigned target
, col_format
;
9962 unsigned enabled_channels
= 0;
9963 aco_opcode compr_op
= (aco_opcode
)0;
9965 slot
-= FRAG_RESULT_DATA0
;
9966 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9967 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9969 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9970 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9971 bool is_16bit
= values
[0].regClass() == v2b
;
9975 case V_028714_SPI_SHADER_ZERO
:
9976 enabled_channels
= 0; /* writemask */
9977 target
= V_008DFC_SQ_EXP_NULL
;
9980 case V_028714_SPI_SHADER_32_R
:
9981 enabled_channels
= 1;
9984 case V_028714_SPI_SHADER_32_GR
:
9985 enabled_channels
= 0x3;
9988 case V_028714_SPI_SHADER_32_AR
:
9989 if (ctx
->options
->chip_class
>= GFX10
) {
9990 /* Special case: on GFX10, the outputs are different for 32_AR */
9991 enabled_channels
= 0x3;
9992 values
[1] = values
[3];
9993 values
[3] = Operand(v1
);
9995 enabled_channels
= 0x9;
9999 case V_028714_SPI_SHADER_FP16_ABGR
:
10000 enabled_channels
= 0x5;
10001 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10003 if (ctx
->options
->chip_class
>= GFX9
) {
10004 /* Pack the FP16 values together instead of converting them to
10005 * FP32 and back to FP16.
10006 * TODO: use p_create_vector and let the compiler optimizes.
10008 compr_op
= aco_opcode::v_pack_b32_f16
;
10010 for (unsigned i
= 0; i
< 4; i
++) {
10011 if ((write_mask
>> i
) & 1)
10012 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10018 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10019 enabled_channels
= 0x5;
10020 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10021 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10023 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10027 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10028 enabled_channels
= 0x5;
10029 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10030 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10032 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10036 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10037 enabled_channels
= 0x5;
10038 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10039 if (is_int8
|| is_int10
) {
10041 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10042 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10044 for (unsigned i
= 0; i
< 4; i
++) {
10045 if ((write_mask
>> i
) & 1) {
10046 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10047 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10051 } else if (is_16bit
) {
10052 for (unsigned i
= 0; i
< 4; i
++) {
10053 if ((write_mask
>> i
) & 1) {
10054 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10055 values
[i
] = Operand(tmp
);
10062 case V_028714_SPI_SHADER_SINT16_ABGR
:
10063 enabled_channels
= 0x5;
10064 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10065 if (is_int8
|| is_int10
) {
10067 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10068 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10069 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10070 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10072 for (unsigned i
= 0; i
< 4; i
++) {
10073 if ((write_mask
>> i
) & 1) {
10074 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10075 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10077 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10078 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10082 } else if (is_16bit
) {
10083 for (unsigned i
= 0; i
< 4; i
++) {
10084 if ((write_mask
>> i
) & 1) {
10085 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10086 values
[i
] = Operand(tmp
);
10092 case V_028714_SPI_SHADER_32_ABGR
:
10093 enabled_channels
= 0xF;
10100 if (target
== V_008DFC_SQ_EXP_NULL
)
10103 if ((bool) compr_op
) {
10104 for (int i
= 0; i
< 2; i
++) {
10105 /* check if at least one of the values to be compressed is enabled */
10106 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10108 enabled_channels
|= enabled
<< (i
*2);
10109 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10110 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10111 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10113 values
[i
] = Operand(v1
);
10116 values
[2] = Operand(v1
);
10117 values
[3] = Operand(v1
);
10119 for (int i
= 0; i
< 4; i
++)
10120 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10123 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10124 enabled_channels
, target
, (bool) compr_op
);
10128 static void create_fs_exports(isel_context
*ctx
)
10130 bool exported
= false;
10132 /* Export depth, stencil and sample mask. */
10133 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10134 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10135 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10136 exported
|= export_fs_mrt_z(ctx
);
10138 /* Export all color render targets. */
10139 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10140 if (ctx
->outputs
.mask
[i
])
10141 exported
|= export_fs_mrt_color(ctx
, i
);
10144 create_null_export(ctx
);
10147 static void write_tcs_tess_factors(isel_context
*ctx
)
10149 unsigned outer_comps
;
10150 unsigned inner_comps
;
10152 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10169 Builder
bld(ctx
->program
, ctx
->block
);
10171 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10172 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10173 bld
.sopp(aco_opcode::s_barrier
);
10175 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10176 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10178 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10179 if_context ic_invocation_id_is_zero
;
10180 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10181 bld
.reset(ctx
->block
);
10183 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10185 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10186 unsigned stride
= inner_comps
+ outer_comps
;
10187 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10191 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10193 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10195 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10196 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10197 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10199 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10200 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10202 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10203 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10204 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10205 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10208 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10209 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10210 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10211 unsigned tf_const_offset
= 0;
10213 if (ctx
->program
->chip_class
<= GFX8
) {
10214 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10215 if_context ic_rel_patch_id_is_zero
;
10216 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10217 bld
.reset(ctx
->block
);
10219 /* Store the dynamic HS control word. */
10220 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10221 bld
.mubuf(aco_opcode::buffer_store_dword
,
10222 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10223 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10224 /* disable_wqm */ false, /* glc */ true);
10225 tf_const_offset
+= 4;
10227 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10228 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10229 bld
.reset(ctx
->block
);
10232 assert(stride
== 2 || stride
== 4 || stride
== 6);
10233 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10234 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10236 /* Store to offchip for TES to read - only if TES reads them */
10237 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10238 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10239 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10241 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10242 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10244 if (likely(inner_comps
)) {
10245 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10246 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10250 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10251 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10254 static void emit_stream_output(isel_context
*ctx
,
10255 Temp
const *so_buffers
,
10256 Temp
const *so_write_offset
,
10257 const struct radv_stream_output
*output
)
10259 unsigned num_comps
= util_bitcount(output
->component_mask
);
10260 unsigned writemask
= (1 << num_comps
) - 1;
10261 unsigned loc
= output
->location
;
10262 unsigned buf
= output
->buffer
;
10264 assert(num_comps
&& num_comps
<= 4);
10265 if (!num_comps
|| num_comps
> 4)
10268 unsigned start
= ffs(output
->component_mask
) - 1;
10271 bool all_undef
= true;
10272 assert(ctx
->stage
& hw_vs
);
10273 for (unsigned i
= 0; i
< num_comps
; i
++) {
10274 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10275 all_undef
= all_undef
&& !out
[i
].id();
10280 while (writemask
) {
10282 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10283 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10284 /* GFX6 doesn't support storing vec3, split it. */
10285 writemask
|= 1u << (start
+ 2);
10289 unsigned offset
= output
->offset
+ start
* 4;
10291 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10292 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10293 for (int i
= 0; i
< count
; ++i
)
10294 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10295 vec
->definitions
[0] = Definition(write_data
);
10296 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10301 opcode
= aco_opcode::buffer_store_dword
;
10304 opcode
= aco_opcode::buffer_store_dwordx2
;
10307 opcode
= aco_opcode::buffer_store_dwordx3
;
10310 opcode
= aco_opcode::buffer_store_dwordx4
;
10313 unreachable("Unsupported dword count.");
10316 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10317 store
->operands
[0] = Operand(so_buffers
[buf
]);
10318 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10319 store
->operands
[2] = Operand((uint32_t) 0);
10320 store
->operands
[3] = Operand(write_data
);
10321 if (offset
> 4095) {
10322 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10323 Builder
bld(ctx
->program
, ctx
->block
);
10324 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10326 store
->offset
= offset
;
10328 store
->offen
= true;
10330 store
->dlc
= false;
10332 store
->can_reorder
= true;
10333 ctx
->block
->instructions
.emplace_back(std::move(store
));
10337 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10339 Builder
bld(ctx
->program
, ctx
->block
);
10341 Temp so_buffers
[4];
10342 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10343 for (unsigned i
= 0; i
< 4; i
++) {
10344 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10348 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10349 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10352 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10353 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10355 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10357 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10360 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10362 bld
.reset(ctx
->block
);
10364 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10366 Temp so_write_offset
[4];
10368 for (unsigned i
= 0; i
< 4; i
++) {
10369 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10374 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10375 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10376 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10377 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10379 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10381 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10382 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10383 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10384 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10388 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10389 struct radv_stream_output
*output
=
10390 &ctx
->program
->info
->so
.outputs
[i
];
10391 if (stream
!= output
->stream
)
10394 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10397 begin_divergent_if_else(ctx
, &ic
);
10398 end_divergent_if(ctx
, &ic
);
10401 } /* end namespace */
10403 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10405 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10406 Builder
bld(ctx
->program
, ctx
->block
);
10407 constexpr unsigned hs_idx
= 1u;
10408 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10409 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10410 Operand((8u << 16) | (hs_idx
* 8u)));
10411 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10413 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10415 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10416 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10417 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10418 ls_has_nonzero_hs_threads
);
10419 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10420 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10421 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10422 ls_has_nonzero_hs_threads
);
10423 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10424 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10425 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10426 ls_has_nonzero_hs_threads
);
10428 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10429 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10430 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10433 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10435 /* Split all arguments except for the first (ring_offsets) and the last
10436 * (exec) so that the dead channels don't stay live throughout the program.
10438 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10439 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10440 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10441 startpgm
->definitions
[i
].regClass().size());
10446 void handle_bc_optimize(isel_context
*ctx
)
10448 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10449 Builder
bld(ctx
->program
, ctx
->block
);
10450 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10451 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10452 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10453 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10454 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10455 if (uses_center
&& uses_centroid
) {
10456 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10457 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10459 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10461 for (unsigned i
= 0; i
< 2; i
++) {
10462 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10463 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10464 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10465 persp_centroid
, persp_center
, sel
);
10467 ctx
->persp_centroid
= bld
.tmp(v2
);
10468 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10469 Operand(new_coord
[0]), Operand(new_coord
[1]));
10470 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10473 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10475 for (unsigned i
= 0; i
< 2; i
++) {
10476 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10477 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10478 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10479 linear_centroid
, linear_center
, sel
);
10481 ctx
->linear_centroid
= bld
.tmp(v2
);
10482 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10483 Operand(new_coord
[0]), Operand(new_coord
[1]));
10484 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10489 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10491 Program
*program
= ctx
->program
;
10493 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10495 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10496 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10497 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10498 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10499 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10501 program
->next_fp_mode
.must_flush_denorms32
=
10502 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10503 program
->next_fp_mode
.must_flush_denorms16_64
=
10504 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10505 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10507 program
->next_fp_mode
.care_about_round32
=
10508 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10510 program
->next_fp_mode
.care_about_round16_64
=
10511 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10512 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10514 /* default to preserving fp16 and fp64 denorms, since it's free */
10515 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10516 program
->next_fp_mode
.denorm16_64
= 0;
10518 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10520 /* preserving fp32 denorms is expensive, so only do it if asked */
10521 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10522 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10524 program
->next_fp_mode
.denorm32
= 0;
10526 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10527 program
->next_fp_mode
.round32
= fp_round_tz
;
10529 program
->next_fp_mode
.round32
= fp_round_ne
;
10531 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10532 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10534 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10536 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10539 void cleanup_cfg(Program
*program
)
10541 /* create linear_succs/logical_succs */
10542 for (Block
& BB
: program
->blocks
) {
10543 for (unsigned idx
: BB
.linear_preds
)
10544 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10545 for (unsigned idx
: BB
.logical_preds
)
10546 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10550 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10552 Builder
bld(ctx
->program
, ctx
->block
);
10554 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10555 Temp count
= i
== 0
10556 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10557 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10558 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10560 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10563 if (ctx
->program
->wave_size
== 64) {
10564 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10565 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10566 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10568 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10569 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10575 bool ngg_early_prim_export(isel_context
*ctx
)
10577 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10581 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10583 Builder
bld(ctx
->program
, ctx
->block
);
10585 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10586 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10588 /* Get the id of the current wave within the threadgroup (workgroup) */
10589 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10590 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10592 /* Execute the following code only on the first wave (wave id 0),
10593 * use the SCC def to tell if the wave id is zero or not.
10595 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10597 begin_uniform_if_then(ctx
, &ic
, cond
);
10598 begin_uniform_if_else(ctx
, &ic
);
10599 bld
.reset(ctx
->block
);
10601 /* Number of vertices output by VS/TES */
10602 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10603 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10604 /* Number of primitives output by VS/TES */
10605 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10606 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10608 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10609 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10610 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10612 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10613 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10615 end_uniform_if(ctx
, &ic
);
10617 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10618 bld
.reset(ctx
->block
);
10619 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10622 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10624 Builder
bld(ctx
->program
, ctx
->block
);
10626 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10627 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10630 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10633 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10634 assert(vtxindex
[i
].id());
10637 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10641 /* The initial edge flag is always false in tess eval shaders. */
10642 if (ctx
->stage
== ngg_vertex_gs
) {
10643 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10644 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10648 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10653 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10655 Builder
bld(ctx
->program
, ctx
->block
);
10656 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10658 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10659 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10660 false /* compressed */, true/* done */, false /* valid mask */);
10663 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10665 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10666 * These must always come before VS exports.
10668 * It is recommended to do these as early as possible. They can be at the beginning when
10669 * there is no SW GS and the shader doesn't write edge flags.
10673 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10674 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10676 Builder
bld(ctx
->program
, ctx
->block
);
10677 constexpr unsigned max_vertices_per_primitive
= 3;
10678 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10680 if (ctx
->stage
== ngg_vertex_gs
) {
10681 /* TODO: optimize for points & lines */
10682 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10683 if (ctx
->shader
->info
.tess
.point_mode
)
10684 num_vertices_per_primitive
= 1;
10685 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10686 num_vertices_per_primitive
= 2;
10688 unreachable("Unsupported NGG shader stage");
10691 Temp vtxindex
[max_vertices_per_primitive
];
10692 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10693 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10694 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10695 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10696 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10697 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10698 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10699 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10701 /* Export primitive data to the index buffer. */
10702 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10704 /* Export primitive ID. */
10705 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10706 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10707 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10708 Temp provoking_vtx_index
= vtxindex
[0];
10709 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10711 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10714 begin_divergent_if_else(ctx
, &ic
);
10715 end_divergent_if(ctx
, &ic
);
10718 void ngg_emit_nogs_output(isel_context
*ctx
)
10720 /* Emits NGG GS output, for stages that don't have SW GS. */
10723 Builder
bld(ctx
->program
, ctx
->block
);
10724 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10726 /* NGG streamout is currently disabled by default. */
10727 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10729 if (late_prim_export
) {
10730 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10731 create_export_phis(ctx
);
10732 /* Do what we need to do in the GS threads. */
10733 ngg_emit_nogs_gsthreads(ctx
);
10735 /* What comes next should be executed on ES threads. */
10736 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10737 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10738 bld
.reset(ctx
->block
);
10741 /* Export VS outputs */
10742 ctx
->block
->kind
|= block_kind_export_end
;
10743 create_vs_exports(ctx
);
10745 /* Export primitive ID */
10746 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10749 if (ctx
->stage
== ngg_vertex_gs
) {
10750 /* Wait for GS threads to store primitive ID in LDS. */
10751 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10752 bld
.sopp(aco_opcode::s_barrier
);
10754 /* Calculate LDS address where the GS threads stored the primitive ID. */
10755 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10756 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10757 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10758 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10759 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10760 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10762 /* Load primitive ID from LDS. */
10763 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10764 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10765 /* TES: Just use the patch ID as the primitive ID. */
10766 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10768 unreachable("unsupported NGG shader stage.");
10771 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10772 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10774 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10777 if (late_prim_export
) {
10778 begin_divergent_if_else(ctx
, &ic
);
10779 end_divergent_if(ctx
, &ic
);
10780 bld
.reset(ctx
->block
);
10784 void select_program(Program
*program
,
10785 unsigned shader_count
,
10786 struct nir_shader
*const *shaders
,
10787 ac_shader_config
* config
,
10788 struct radv_shader_args
*args
)
10790 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10791 if_context ic_merged_wave_info
;
10792 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10794 for (unsigned i
= 0; i
< shader_count
; i
++) {
10795 nir_shader
*nir
= shaders
[i
];
10796 init_context(&ctx
, nir
);
10798 setup_fp_mode(&ctx
, nir
);
10801 /* needs to be after init_context() for FS */
10802 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10803 append_logical_start(ctx
.block
);
10805 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10806 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10808 split_arguments(&ctx
, startpgm
);
10812 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10814 if (ngg_early_prim_export(&ctx
))
10815 ngg_emit_nogs_gsthreads(&ctx
);
10818 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10819 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10820 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10821 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10822 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10823 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10824 ctx
.stage
== tess_eval_geometry_gs
));
10826 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10827 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10828 if (check_merged_wave_info
) {
10829 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10830 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10834 Builder
bld(ctx
.program
, ctx
.block
);
10836 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10837 bld
.sopp(aco_opcode::s_barrier
);
10839 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10840 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10842 } else if (ctx
.stage
== geometry_gs
)
10843 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10845 if (ctx
.stage
== fragment_fs
)
10846 handle_bc_optimize(&ctx
);
10848 visit_cf_list(&ctx
, &func
->body
);
10850 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10851 emit_streamout(&ctx
, 0);
10853 if (ctx
.stage
& hw_vs
) {
10854 create_vs_exports(&ctx
);
10855 ctx
.block
->kind
|= block_kind_export_end
;
10856 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10857 ngg_emit_nogs_output(&ctx
);
10858 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10859 Builder
bld(ctx
.program
, ctx
.block
);
10860 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10861 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10862 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10863 write_tcs_tess_factors(&ctx
);
10866 if (ctx
.stage
== fragment_fs
) {
10867 create_fs_exports(&ctx
);
10868 ctx
.block
->kind
|= block_kind_export_end
;
10871 if (endif_merged_wave_info
) {
10872 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10873 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10876 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10877 ngg_emit_nogs_output(&ctx
);
10879 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10880 /* Outputs of the previous stage are inputs to the next stage */
10881 ctx
.inputs
= ctx
.outputs
;
10882 ctx
.outputs
= shader_io_state();
10886 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10888 append_logical_end(ctx
.block
);
10889 ctx
.block
->kind
|= block_kind_uniform
;
10890 Builder
bld(ctx
.program
, ctx
.block
);
10891 if (ctx
.program
->wb_smem_l1_on_end
)
10892 bld
.smem(aco_opcode::s_dcache_wb
, false);
10893 bld
.sopp(aco_opcode::s_endpgm
);
10895 cleanup_cfg(program
);
10898 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10899 ac_shader_config
* config
,
10900 struct radv_shader_args
*args
)
10902 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10904 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10905 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10906 program
->next_fp_mode
.must_flush_denorms32
= false;
10907 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10908 program
->next_fp_mode
.care_about_round32
= false;
10909 program
->next_fp_mode
.care_about_round16_64
= false;
10910 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10911 program
->next_fp_mode
.denorm32
= 0;
10912 program
->next_fp_mode
.round32
= fp_round_ne
;
10913 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10914 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10916 add_startpgm(&ctx
);
10917 append_logical_start(ctx
.block
);
10919 Builder
bld(ctx
.program
, ctx
.block
);
10921 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10923 Operand
stream_id(0u);
10924 if (args
->shader_info
->so
.num_outputs
)
10925 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10926 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10928 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10930 std::stack
<Block
> endif_blocks
;
10932 for (unsigned stream
= 0; stream
< 4; stream
++) {
10933 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10936 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10937 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10940 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10942 unsigned BB_if_idx
= ctx
.block
->index
;
10943 Block BB_endif
= Block();
10944 if (!stream_id
.isConstant()) {
10946 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10947 append_logical_end(ctx
.block
);
10948 ctx
.block
->kind
|= block_kind_uniform
;
10949 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10951 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10953 ctx
.block
= ctx
.program
->create_and_insert_block();
10954 add_edge(BB_if_idx
, ctx
.block
);
10955 bld
.reset(ctx
.block
);
10956 append_logical_start(ctx
.block
);
10959 unsigned offset
= 0;
10960 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10961 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10964 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10965 unsigned length
= util_last_bit(output_usage_mask
);
10966 for (unsigned j
= 0; j
< length
; ++j
) {
10967 if (!(output_usage_mask
& (1 << j
)))
10970 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10971 Temp voffset
= vtx_offset
;
10972 if (const_offset
>= 4096u) {
10973 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10974 const_offset
%= 4096u;
10977 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10978 mubuf
->definitions
[0] = bld
.def(v1
);
10979 mubuf
->operands
[0] = Operand(gsvs_ring
);
10980 mubuf
->operands
[1] = Operand(voffset
);
10981 mubuf
->operands
[2] = Operand(0u);
10982 mubuf
->offen
= true;
10983 mubuf
->offset
= const_offset
;
10986 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10987 mubuf
->barrier
= barrier_none
;
10988 mubuf
->can_reorder
= true;
10990 ctx
.outputs
.mask
[i
] |= 1 << j
;
10991 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10993 bld
.insert(std::move(mubuf
));
10999 if (args
->shader_info
->so
.num_outputs
) {
11000 emit_streamout(&ctx
, stream
);
11001 bld
.reset(ctx
.block
);
11005 create_vs_exports(&ctx
);
11006 ctx
.block
->kind
|= block_kind_export_end
;
11009 if (!stream_id
.isConstant()) {
11010 append_logical_end(ctx
.block
);
11012 /* branch from then block to endif block */
11013 bld
.branch(aco_opcode::p_branch
);
11014 add_edge(ctx
.block
->index
, &BB_endif
);
11015 ctx
.block
->kind
|= block_kind_uniform
;
11017 /* emit else block */
11018 ctx
.block
= ctx
.program
->create_and_insert_block();
11019 add_edge(BB_if_idx
, ctx
.block
);
11020 bld
.reset(ctx
.block
);
11021 append_logical_start(ctx
.block
);
11023 endif_blocks
.push(std::move(BB_endif
));
11027 while (!endif_blocks
.empty()) {
11028 Block BB_endif
= std::move(endif_blocks
.top());
11029 endif_blocks
.pop();
11031 Block
*BB_else
= ctx
.block
;
11033 append_logical_end(BB_else
);
11034 /* branch from else block to endif block */
11035 bld
.branch(aco_opcode::p_branch
);
11036 add_edge(BB_else
->index
, &BB_endif
);
11037 BB_else
->kind
|= block_kind_uniform
;
11039 /** emit endif merge block */
11040 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11041 bld
.reset(ctx
.block
);
11042 append_logical_start(ctx
.block
);
11045 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11047 append_logical_end(ctx
.block
);
11048 ctx
.block
->kind
|= block_kind_uniform
;
11049 bld
.sopp(aco_opcode::s_endpgm
);
11051 cleanup_cfg(program
);