2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_fmax3
: {
1797 if (dst
.regClass() == v2b
) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1799 } else if (dst
.regClass() == v1
) {
1800 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1802 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1806 case nir_op_fmin3
: {
1807 if (dst
.regClass() == v2b
) {
1808 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1809 } else if (dst
.regClass() == v1
) {
1810 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1812 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1816 case nir_op_fmed3
: {
1817 if (dst
.regClass() == v2b
) {
1818 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1819 } else if (dst
.regClass() == v1
) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1822 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1826 case nir_op_umax3
: {
1827 if (dst
.size() == 1) {
1828 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1830 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1834 case nir_op_umin3
: {
1835 if (dst
.size() == 1) {
1836 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1838 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1842 case nir_op_umed3
: {
1843 if (dst
.size() == 1) {
1844 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1846 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1850 case nir_op_imax3
: {
1851 if (dst
.size() == 1) {
1852 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1854 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1858 case nir_op_imin3
: {
1859 if (dst
.size() == 1) {
1860 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1862 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1866 case nir_op_imed3
: {
1867 if (dst
.size() == 1) {
1868 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1870 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1874 case nir_op_cube_face_coord
: {
1875 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1876 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1877 emit_extract_vector(ctx
, in
, 1, v1
),
1878 emit_extract_vector(ctx
, in
, 2, v1
) };
1879 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1880 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1881 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1882 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1883 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1884 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
), Operand(0x3f000000u
/*0.5*/));
1885 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1886 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
), Operand(0x3f000000u
/*0.5*/));
1887 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1890 case nir_op_cube_face_index
: {
1891 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1892 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1893 emit_extract_vector(ctx
, in
, 1, v1
),
1894 emit_extract_vector(ctx
, in
, 2, v1
) };
1895 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1898 case nir_op_bcsel
: {
1899 emit_bcsel(ctx
, instr
, dst
);
1903 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1904 if (dst
.regClass() == v2b
) {
1905 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1906 } else if (dst
.regClass() == v1
) {
1907 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1908 } else if (dst
.regClass() == v2
) {
1909 /* Lowered at NIR level for precision reasons. */
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1912 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1917 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1918 if (dst
.regClass() == v2b
) {
1919 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1920 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1921 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1922 } else if (dst
.regClass() == v1
) {
1923 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1924 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1925 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1926 } else if (dst
.regClass() == v2
) {
1927 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1928 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1929 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1931 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1932 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1934 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1939 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1940 if (dst
.regClass() == v2b
) {
1941 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1942 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1943 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1944 } else if (dst
.regClass() == v1
) {
1945 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1946 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1947 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1948 } else if (dst
.regClass() == v2
) {
1949 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1950 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1951 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1952 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1953 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1956 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1961 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1962 if (dst
.regClass() == v2b
) {
1963 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1964 } else if (dst
.regClass() == v1
) {
1965 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1966 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1967 // TODO: confirm that this holds under any circumstances
1968 } else if (dst
.regClass() == v2
) {
1969 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1970 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1973 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1977 case nir_op_flog2
: {
1978 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1979 if (dst
.regClass() == v2b
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1981 } else if (dst
.regClass() == v1
) {
1982 emit_log2(ctx
, bld
, Definition(dst
), src
);
1984 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1989 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1990 if (dst
.regClass() == v2b
) {
1991 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1992 } else if (dst
.regClass() == v1
) {
1993 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1994 } else if (dst
.regClass() == v2
) {
1995 /* Lowered at NIR level for precision reasons. */
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1998 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2002 case nir_op_fexp2
: {
2003 if (dst
.regClass() == v2b
) {
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2005 } else if (dst
.regClass() == v1
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2008 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2012 case nir_op_fsqrt
: {
2013 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2014 if (dst
.regClass() == v2b
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2016 } else if (dst
.regClass() == v1
) {
2017 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2018 } else if (dst
.regClass() == v2
) {
2019 /* Lowered at NIR level for precision reasons. */
2020 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2022 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2026 case nir_op_ffract
: {
2027 if (dst
.regClass() == v2b
) {
2028 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2029 } else if (dst
.regClass() == v1
) {
2030 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2031 } else if (dst
.regClass() == v2
) {
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2034 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2038 case nir_op_ffloor
: {
2039 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2040 if (dst
.regClass() == v2b
) {
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2047 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2051 case nir_op_fceil
: {
2052 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2053 if (dst
.regClass() == v2b
) {
2054 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2055 } else if (dst
.regClass() == v1
) {
2056 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2057 } else if (dst
.regClass() == v2
) {
2058 if (ctx
->options
->chip_class
>= GFX7
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2061 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2062 /* trunc = trunc(src0)
2063 * if (src0 > 0.0 && src0 != trunc)
2066 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2067 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2068 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2069 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2070 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2071 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2072 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2075 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2079 case nir_op_ftrunc
: {
2080 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2083 } else if (dst
.regClass() == v1
) {
2084 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2085 } else if (dst
.regClass() == v2
) {
2086 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2088 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2092 case nir_op_fround_even
: {
2093 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2094 if (dst
.regClass() == v2b
) {
2095 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2096 } else if (dst
.regClass() == v1
) {
2097 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2098 } else if (dst
.regClass() == v2
) {
2099 if (ctx
->options
->chip_class
>= GFX7
) {
2100 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2102 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2103 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2104 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2106 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2107 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2108 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2109 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2110 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2111 tmp
= sub
->definitions
[0].getTemp();
2113 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2114 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2115 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2116 Temp cond
= vop3
->definitions
[0].getTemp();
2118 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2119 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2120 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2121 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2123 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2126 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2132 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2133 aco_ptr
<Instruction
> norm
;
2134 if (dst
.regClass() == v2b
) {
2135 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2136 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2137 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2138 bld
.vop1(opcode
, Definition(dst
), tmp
);
2139 } else if (dst
.regClass() == v1
) {
2140 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2141 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2143 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2144 if (ctx
->options
->chip_class
< GFX9
)
2145 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2147 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2148 bld
.vop1(opcode
, Definition(dst
), tmp
);
2150 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2154 case nir_op_ldexp
: {
2155 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2156 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2157 if (dst
.regClass() == v2b
) {
2158 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2159 } else if (dst
.regClass() == v1
) {
2160 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2161 } else if (dst
.regClass() == v2
) {
2162 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2164 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2168 case nir_op_frexp_sig
: {
2169 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2170 if (dst
.regClass() == v2b
) {
2171 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2172 } else if (dst
.regClass() == v1
) {
2173 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2174 } else if (dst
.regClass() == v2
) {
2175 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2177 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2181 case nir_op_frexp_exp
: {
2182 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2184 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2185 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2186 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2187 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2188 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2189 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2190 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2192 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2196 case nir_op_fsign
: {
2197 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2198 if (dst
.regClass() == v2b
) {
2199 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2200 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2201 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2202 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2203 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2204 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2205 } else if (dst
.regClass() == v1
) {
2206 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2207 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2208 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2209 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2210 } else if (dst
.regClass() == v2
) {
2211 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2212 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2213 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2215 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2216 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2217 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2219 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2221 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2226 case nir_op_f2f16_rtne
: {
2227 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2228 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2229 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2230 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2231 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2232 * keep value numbering and the scheduler simpler.
2234 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2239 case nir_op_f2f16_rtz
: {
2240 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2241 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2242 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2243 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2246 case nir_op_f2f32
: {
2247 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2248 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2249 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2250 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2252 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2256 case nir_op_f2f64
: {
2257 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2258 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2259 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2260 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2263 case nir_op_i2f16
: {
2264 assert(dst
.regClass() == v2b
);
2265 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2266 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2267 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2268 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2269 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2270 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2273 case nir_op_i2f32
: {
2274 assert(dst
.size() == 1);
2275 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2276 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2277 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2278 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2281 case nir_op_i2f64
: {
2282 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2283 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2284 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2285 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2286 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2287 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2289 RegClass rc
= RegClass(src
.type(), 1);
2290 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2291 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2292 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2293 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2294 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2295 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2298 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2302 case nir_op_u2f16
: {
2303 assert(dst
.regClass() == v2b
);
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2306 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2307 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2308 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2309 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2312 case nir_op_u2f32
: {
2313 assert(dst
.size() == 1);
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2316 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2318 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2319 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2320 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2324 case nir_op_u2f64
: {
2325 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2326 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2327 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2328 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2329 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2330 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2331 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2332 RegClass rc
= RegClass(src
.type(), 1);
2333 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2334 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2335 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2336 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2337 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2338 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2340 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2345 case nir_op_f2i16
: {
2346 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2347 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2348 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2349 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2351 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2355 case nir_op_f2u16
: {
2356 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2357 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2358 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2359 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2361 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2364 case nir_op_f2i32
: {
2365 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2366 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2367 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2368 if (dst
.type() == RegType::vgpr
) {
2369 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2371 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2372 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2374 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2375 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2376 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2377 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2379 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2383 case nir_op_f2u32
: {
2384 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2385 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2386 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2387 if (dst
.type() == RegType::vgpr
) {
2388 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2390 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2393 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2394 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2395 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2396 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2398 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2402 case nir_op_f2i64
: {
2403 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2404 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2405 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2407 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2408 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2409 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2410 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2411 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2412 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2413 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2414 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2415 Temp new_exponent
= bld
.tmp(v1
);
2416 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2417 if (ctx
->program
->chip_class
>= GFX8
)
2418 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2420 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2421 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2422 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2423 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2424 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2425 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2426 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2427 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2428 Temp new_lower
= bld
.tmp(v1
);
2429 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2430 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2431 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2433 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2434 if (src
.type() == RegType::vgpr
)
2435 src
= bld
.as_uniform(src
);
2436 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2437 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2438 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2439 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2440 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2441 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2442 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2443 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2444 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2445 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2446 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2447 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2448 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2449 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2450 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2451 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2452 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2453 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2454 Temp borrow
= bld
.tmp(s1
);
2455 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2456 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2457 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2460 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2461 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2462 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2463 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2464 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2465 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2466 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2467 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2468 if (dst
.type() == RegType::sgpr
) {
2469 lower
= bld
.as_uniform(lower
);
2470 upper
= bld
.as_uniform(upper
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2475 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2479 case nir_op_f2u64
: {
2480 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2481 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2482 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2484 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2485 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2486 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2487 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2488 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2489 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2490 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2491 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2492 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2493 Temp new_exponent
= bld
.tmp(v1
);
2494 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2495 if (ctx
->program
->chip_class
>= GFX8
)
2496 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2498 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2499 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2500 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2501 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2502 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2503 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2504 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2507 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2508 if (src
.type() == RegType::vgpr
)
2509 src
= bld
.as_uniform(src
);
2510 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2511 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2512 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2513 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2514 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2515 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2516 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2517 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2518 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2519 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2520 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2521 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2522 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2523 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2524 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2525 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2526 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2527 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2529 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2530 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2531 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2532 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2533 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2534 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2535 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2536 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2537 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2538 if (dst
.type() == RegType::sgpr
) {
2539 lower
= bld
.as_uniform(lower
);
2540 upper
= bld
.as_uniform(upper
);
2542 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2545 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2549 case nir_op_b2f16
: {
2550 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2551 assert(src
.regClass() == bld
.lm
);
2553 if (dst
.regClass() == s1
) {
2554 src
= bool_to_scalar_condition(ctx
, src
);
2555 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2556 } else if (dst
.regClass() == v2b
) {
2557 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2558 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2560 unreachable("Wrong destination register class for nir_op_b2f16.");
2564 case nir_op_b2f32
: {
2565 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2566 assert(src
.regClass() == bld
.lm
);
2568 if (dst
.regClass() == s1
) {
2569 src
= bool_to_scalar_condition(ctx
, src
);
2570 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2571 } else if (dst
.regClass() == v1
) {
2572 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2574 unreachable("Wrong destination register class for nir_op_b2f32.");
2578 case nir_op_b2f64
: {
2579 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2580 assert(src
.regClass() == bld
.lm
);
2582 if (dst
.regClass() == s2
) {
2583 src
= bool_to_scalar_condition(ctx
, src
);
2584 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2585 } else if (dst
.regClass() == v2
) {
2586 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2587 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2590 unreachable("Wrong destination register class for nir_op_b2f64.");
2597 case nir_op_i2i64
: {
2598 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2599 /* no need to do the extract in get_alu_src() */
2600 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2601 sgpr_extract_sext
: sgpr_extract_undef
;
2602 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2604 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2605 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2612 case nir_op_u2u64
: {
2613 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2614 /* no need to do the extract in get_alu_src() */
2615 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2616 sgpr_extract_zext
: sgpr_extract_undef
;
2617 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2619 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2620 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2628 case nir_op_b2i64
: {
2629 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2630 assert(src
.regClass() == bld
.lm
);
2632 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2633 if (tmp
.regClass() == s1
) {
2634 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2635 bool_to_scalar_condition(ctx
, src
, tmp
);
2636 } else if (tmp
.type() == RegType::vgpr
) {
2637 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2639 unreachable("Invalid register class for b2i32");
2643 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2648 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2649 assert(dst
.regClass() == bld
.lm
);
2651 if (src
.type() == RegType::vgpr
) {
2652 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2653 assert(dst
.regClass() == bld
.lm
);
2654 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2655 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2657 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2659 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2660 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2662 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2663 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2665 bool_to_vector_condition(ctx
, tmp
, dst
);
2669 case nir_op_pack_64_2x32_split
: {
2670 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2671 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2676 case nir_op_unpack_64_2x32_split_x
:
2677 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2679 case nir_op_unpack_64_2x32_split_y
:
2680 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2682 case nir_op_unpack_32_2x16_split_x
:
2683 if (dst
.type() == RegType::vgpr
) {
2684 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2686 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2689 case nir_op_unpack_32_2x16_split_y
:
2690 if (dst
.type() == RegType::vgpr
) {
2691 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2693 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2696 case nir_op_pack_32_2x16_split
: {
2697 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2699 if (dst
.regClass() == v1
) {
2700 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2701 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2704 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2705 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2706 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2710 case nir_op_pack_half_2x16
: {
2711 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2713 if (dst
.regClass() == v1
) {
2714 Temp src0
= bld
.tmp(v1
);
2715 Temp src1
= bld
.tmp(v1
);
2716 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2717 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2718 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2720 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2721 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2722 if (ctx
->program
->chip_class
>= GFX10
) {
2723 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2724 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2726 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2730 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2734 case nir_op_unpack_half_2x16_split_x
: {
2735 if (dst
.regClass() == v1
) {
2736 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2738 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2742 case nir_op_unpack_half_2x16_split_y
: {
2743 if (dst
.regClass() == v1
) {
2744 /* TODO: use SDWA here */
2745 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2746 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2748 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2752 case nir_op_fquantize2f16
: {
2753 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2754 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2757 if (ctx
->program
->chip_class
>= GFX8
) {
2758 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2759 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2760 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2762 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2763 * so compare the result and flush to 0 if it's smaller.
2765 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2766 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2767 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2768 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2769 cmp_res
= vop3
->definitions
[0].getTemp();
2772 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2773 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2774 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2776 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2781 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2782 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2784 if (dst
.regClass() == s1
) {
2785 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2786 } else if (dst
.regClass() == v1
) {
2787 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2789 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2793 case nir_op_bitfield_select
: {
2794 /* (mask & insert) | (~mask & base) */
2795 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2796 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2797 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2799 /* dst = (insert & bitmask) | (base & ~bitmask) */
2800 if (dst
.regClass() == s1
) {
2801 aco_ptr
<Instruction
> sop2
;
2802 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2803 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2805 if (const_insert
&& const_bitmask
) {
2806 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2808 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2809 lhs
= Operand(insert
);
2813 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2814 if (const_base
&& const_bitmask
) {
2815 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2817 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2818 rhs
= Operand(base
);
2821 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2823 } else if (dst
.regClass() == v1
) {
2824 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2825 base
= as_vgpr(ctx
, base
);
2826 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2827 insert
= as_vgpr(ctx
, insert
);
2829 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2832 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2838 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2839 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2840 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2842 if (dst
.type() == RegType::sgpr
) {
2844 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2845 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2846 if (const_offset
&& const_bits
) {
2847 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2848 extract
= Operand(const_extract
);
2852 width
= Operand(const_bits
->u32
<< 16);
2854 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2856 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2860 if (dst
.regClass() == s1
) {
2861 if (instr
->op
== nir_op_ubfe
)
2862 opcode
= aco_opcode::s_bfe_u32
;
2864 opcode
= aco_opcode::s_bfe_i32
;
2865 } else if (dst
.regClass() == s2
) {
2866 if (instr
->op
== nir_op_ubfe
)
2867 opcode
= aco_opcode::s_bfe_u64
;
2869 opcode
= aco_opcode::s_bfe_i64
;
2871 unreachable("Unsupported BFE bit size");
2874 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2878 if (dst
.regClass() == v1
) {
2879 if (instr
->op
== nir_op_ubfe
)
2880 opcode
= aco_opcode::v_bfe_u32
;
2882 opcode
= aco_opcode::v_bfe_i32
;
2884 unreachable("Unsupported BFE bit size");
2887 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2891 case nir_op_bit_count
: {
2892 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2893 if (src
.regClass() == s1
) {
2894 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2895 } else if (src
.regClass() == v1
) {
2896 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2897 } else if (src
.regClass() == v2
) {
2898 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2899 emit_extract_vector(ctx
, src
, 1, v1
),
2900 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2901 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2902 } else if (src
.regClass() == s2
) {
2903 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2905 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2910 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2914 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2918 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2922 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2926 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2930 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2934 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2935 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2938 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2942 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2943 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2946 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2950 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2954 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2959 case nir_op_fddx_fine
:
2960 case nir_op_fddy_fine
:
2961 case nir_op_fddx_coarse
:
2962 case nir_op_fddy_coarse
: {
2963 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2964 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2965 if (instr
->op
== nir_op_fddx_fine
) {
2966 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2967 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2968 } else if (instr
->op
== nir_op_fddy_fine
) {
2969 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2970 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2972 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2973 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2974 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2976 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2980 if (ctx
->program
->chip_class
>= GFX8
) {
2981 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2982 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2984 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2985 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2986 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2988 emit_wqm(ctx
, tmp
, dst
, true);
2992 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2996 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2998 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3000 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3001 // which get truncated the lsb if double and msb if int
3002 // for now, we only use s_mov_b64 with 64bit inline constants
3003 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3004 assert(dst
.type() == RegType::sgpr
);
3006 Builder
bld(ctx
->program
, ctx
->block
);
3008 if (instr
->def
.bit_size
== 1) {
3009 assert(dst
.regClass() == bld
.lm
);
3010 int val
= instr
->value
[0].b
? -1 : 0;
3011 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3012 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3013 } else if (instr
->def
.bit_size
== 8) {
3014 /* ensure that the value is correctly represented in the low byte of the register */
3015 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3016 } else if (instr
->def
.bit_size
== 16) {
3017 /* ensure that the value is correctly represented in the low half of the register */
3018 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3019 } else if (dst
.size() == 1) {
3020 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3022 assert(dst
.size() != 1);
3023 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3024 if (instr
->def
.bit_size
== 64)
3025 for (unsigned i
= 0; i
< dst
.size(); i
++)
3026 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3028 for (unsigned i
= 0; i
< dst
.size(); i
++)
3029 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3031 vec
->definitions
[0] = Definition(dst
);
3032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3036 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3038 uint32_t new_mask
= 0;
3039 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3040 if (mask
& (1u << i
))
3041 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3045 struct LoadEmitInfo
{
3048 unsigned num_components
;
3049 unsigned component_size
;
3050 Temp resource
= Temp(0, s1
);
3051 unsigned component_stride
= 0;
3052 unsigned const_offset
= 0;
3053 unsigned align_mul
= 0;
3054 unsigned align_offset
= 0;
3057 unsigned swizzle_component_size
= 0;
3058 memory_sync_info sync
;
3059 Temp soffset
= Temp(0, s1
);
3062 using LoadCallback
= Temp(*)(
3063 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3064 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3066 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3067 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3069 unsigned load_size
= info
->num_components
* info
->component_size
;
3070 unsigned component_size
= info
->component_size
;
3072 unsigned num_vals
= 0;
3073 Temp vals
[info
->dst
.bytes()];
3075 unsigned const_offset
= info
->const_offset
;
3077 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3078 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3080 unsigned bytes_read
= 0;
3081 while (bytes_read
< load_size
) {
3082 unsigned bytes_needed
= load_size
- bytes_read
;
3084 /* add buffer for unaligned loads */
3085 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3088 if ((bytes_needed
> 2 ||
3089 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3090 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3091 if (info
->component_stride
) {
3092 assert(supports_8bit_16bit_loads
&& "unimplemented");
3096 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3097 bytes_needed
= align(bytes_needed
, 4);
3104 if (info
->swizzle_component_size
)
3105 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3106 if (info
->component_stride
)
3107 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3109 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3111 /* reduce constant offset */
3112 Operand offset
= info
->offset
;
3113 unsigned reduced_const_offset
= const_offset
;
3114 bool remove_const_offset_completely
= need_to_align_offset
;
3115 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3116 unsigned to_add
= const_offset
;
3117 if (remove_const_offset_completely
) {
3118 reduced_const_offset
= 0;
3120 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3121 reduced_const_offset
%= max_const_offset_plus_one
;
3123 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3124 if (offset
.isConstant()) {
3125 offset
= Operand(offset
.constantValue() + to_add
);
3126 } else if (offset_tmp
.regClass() == s1
) {
3127 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3128 offset_tmp
, Operand(to_add
));
3129 } else if (offset_tmp
.regClass() == v1
) {
3130 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3132 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3133 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3134 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3136 if (offset_tmp
.regClass() == s2
) {
3137 Temp carry
= bld
.tmp(s1
);
3138 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3139 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3140 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3142 Temp new_lo
= bld
.tmp(v1
);
3143 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3144 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3145 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3150 /* align offset down if needed */
3151 Operand aligned_offset
= offset
;
3152 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3153 if (need_to_align_offset
) {
3155 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3156 if (offset
.isConstant()) {
3157 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3158 } else if (offset_tmp
.regClass() == s1
) {
3159 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3160 } else if (offset_tmp
.regClass() == s2
) {
3161 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3162 } else if (offset_tmp
.regClass() == v1
) {
3163 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3164 } else if (offset_tmp
.regClass() == v2
) {
3165 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3166 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3167 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3168 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3171 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3172 bld
.copy(bld
.def(s1
), aligned_offset
);
3174 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3175 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3177 /* the callback wrote directly to dst */
3178 if (val
== info
->dst
) {
3179 assert(num_vals
== 0);
3180 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3184 /* shift result right if needed */
3185 if (info
->component_size
< 4 && byte_align_loads
) {
3186 Operand
align((uint32_t)byte_align
);
3187 if (byte_align
== -1) {
3188 if (offset
.isConstant())
3189 align
= Operand(offset
.constantValue() % 4u);
3190 else if (offset
.size() == 2)
3191 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3196 assert(val
.bytes() >= load_size
&& "unimplemented");
3197 if (val
.type() == RegType::sgpr
)
3198 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3200 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3204 /* add result to list and advance */
3205 if (info
->component_stride
) {
3206 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3207 const_offset
+= info
->component_stride
;
3208 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3210 const_offset
+= val
.bytes();
3211 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3213 bytes_read
+= val
.bytes();
3214 vals
[num_vals
++] = val
;
3217 /* create array of components */
3218 unsigned components_split
= 0;
3219 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3220 bool has_vgprs
= false;
3221 for (unsigned i
= 0; i
< num_vals
;) {
3223 unsigned num_tmps
= 0;
3224 unsigned tmp_size
= 0;
3225 RegType reg_type
= RegType::sgpr
;
3226 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3227 if (vals
[i
].type() == RegType::vgpr
)
3228 reg_type
= RegType::vgpr
;
3229 tmp_size
+= vals
[i
].bytes();
3230 tmp
[num_tmps
++] = vals
[i
++];
3233 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3234 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3235 for (unsigned i
= 0; i
< num_tmps
; i
++)
3236 vec
->operands
[i
] = Operand(tmp
[i
]);
3237 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3238 vec
->definitions
[0] = Definition(tmp
[0]);
3239 bld
.insert(std::move(vec
));
3242 if (tmp
[0].bytes() % component_size
) {
3244 assert(i
== num_vals
);
3245 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3246 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3249 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3251 unsigned start
= components_split
;
3253 if (tmp_size
== elem_rc
.bytes()) {
3254 allocated_vec
[components_split
++] = tmp
[0];
3256 assert(tmp_size
% elem_rc
.bytes() == 0);
3257 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3258 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3259 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3260 Temp component
= bld
.tmp(elem_rc
);
3261 allocated_vec
[components_split
++] = component
;
3262 split
->definitions
[i
] = Definition(component
);
3264 split
->operands
[0] = Operand(tmp
[0]);
3265 bld
.insert(std::move(split
));
3268 /* try to p_as_uniform early so we can create more optimizable code and
3269 * also update allocated_vec */
3270 for (unsigned j
= start
; j
< components_split
; j
++) {
3271 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3272 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3273 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3277 /* concatenate components and p_as_uniform() result if needed */
3278 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3279 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3281 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3283 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3284 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3285 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3286 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3288 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3289 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3290 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3291 vec
->definitions
[0] = Definition(tmp
);
3292 bld
.insert(std::move(vec
));
3293 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3295 vec
->definitions
[0] = Definition(info
->dst
);
3296 bld
.insert(std::move(vec
));
3300 Operand
load_lds_size_m0(Builder
& bld
)
3302 /* TODO: m0 does not need to be initialized on GFX9+ */
3303 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3306 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3307 Temp offset
, unsigned bytes_needed
,
3308 unsigned align
, unsigned const_offset
,
3311 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3313 Operand m
= load_lds_size_m0(bld
);
3315 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3316 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3321 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3322 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3324 op
= aco_opcode::ds_read_b128
;
3325 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3328 op
= aco_opcode::ds_read2_b64
;
3329 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3331 op
= aco_opcode::ds_read_b96
;
3332 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3334 op
= aco_opcode::ds_read_b64
;
3335 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3338 op
= aco_opcode::ds_read2_b32
;
3339 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3341 op
= aco_opcode::ds_read_b32
;
3342 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3344 op
= aco_opcode::ds_read_u16
;
3347 op
= aco_opcode::ds_read_u8
;
3350 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3351 if (const_offset
>= max_offset_plus_one
) {
3352 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3353 const_offset
%= max_offset_plus_one
;
3357 const_offset
/= (size
/ 2u);
3359 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3360 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3363 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3365 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3366 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3369 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3374 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3376 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3377 Temp offset
, unsigned bytes_needed
,
3378 unsigned align
, unsigned const_offset
,
3383 if (bytes_needed
<= 4) {
3385 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3386 } else if (bytes_needed
<= 8) {
3388 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3389 } else if (bytes_needed
<= 16) {
3391 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3392 } else if (bytes_needed
<= 32) {
3394 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3397 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3399 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3400 if (info
->resource
.id()) {
3401 load
->operands
[0] = Operand(info
->resource
);
3402 load
->operands
[1] = Operand(offset
);
3404 load
->operands
[0] = Operand(offset
);
3405 load
->operands
[1] = Operand(0u);
3407 RegClass
rc(RegType::sgpr
, size
);
3408 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3409 load
->definitions
[0] = Definition(val
);
3410 load
->glc
= info
->glc
;
3411 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3412 load
->sync
= info
->sync
;
3413 bld
.insert(std::move(load
));
3417 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3419 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3420 Temp offset
, unsigned bytes_needed
,
3421 unsigned align_
, unsigned const_offset
,
3424 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3425 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3427 if (info
->soffset
.id()) {
3428 if (soffset
.isTemp())
3429 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3430 soffset
= Operand(info
->soffset
);
3433 unsigned bytes_size
= 0;
3435 if (bytes_needed
== 1 || align_
% 2) {
3437 op
= aco_opcode::buffer_load_ubyte
;
3438 } else if (bytes_needed
== 2 || align_
% 4) {
3440 op
= aco_opcode::buffer_load_ushort
;
3441 } else if (bytes_needed
<= 4) {
3443 op
= aco_opcode::buffer_load_dword
;
3444 } else if (bytes_needed
<= 8) {
3446 op
= aco_opcode::buffer_load_dwordx2
;
3447 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3449 op
= aco_opcode::buffer_load_dwordx3
;
3452 op
= aco_opcode::buffer_load_dwordx4
;
3454 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3455 mubuf
->operands
[0] = Operand(info
->resource
);
3456 mubuf
->operands
[1] = vaddr
;
3457 mubuf
->operands
[2] = soffset
;
3458 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3459 mubuf
->glc
= info
->glc
;
3460 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3461 mubuf
->sync
= info
->sync
;
3462 mubuf
->offset
= const_offset
;
3463 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3464 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3465 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3466 mubuf
->definitions
[0] = Definition(val
);
3467 bld
.insert(std::move(mubuf
));
3472 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3473 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3475 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3477 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3478 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3480 if (addr
.type() == RegType::vgpr
)
3481 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3482 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3485 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3486 Temp offset
, unsigned bytes_needed
,
3487 unsigned align_
, unsigned const_offset
,
3490 unsigned bytes_size
= 0;
3491 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3492 bool global
= bld
.program
->chip_class
>= GFX9
;
3494 if (bytes_needed
== 1) {
3496 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3497 } else if (bytes_needed
== 2) {
3499 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3500 } else if (bytes_needed
<= 4) {
3502 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3503 } else if (bytes_needed
<= 8) {
3505 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3506 } else if (bytes_needed
<= 12 && !mubuf
) {
3508 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3511 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3513 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3514 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3516 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3517 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3518 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3519 mubuf
->operands
[2] = Operand(0u);
3520 mubuf
->glc
= info
->glc
;
3523 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3524 mubuf
->disable_wqm
= false;
3525 mubuf
->sync
= info
->sync
;
3526 mubuf
->definitions
[0] = Definition(val
);
3527 bld
.insert(std::move(mubuf
));
3529 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3531 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3532 flat
->operands
[0] = Operand(offset
);
3533 flat
->operands
[1] = Operand(s1
);
3534 flat
->glc
= info
->glc
;
3535 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3536 flat
->sync
= info
->sync
;
3538 flat
->definitions
[0] = Definition(val
);
3539 bld
.insert(std::move(flat
));
3545 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3547 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3548 Temp address
, unsigned base_offset
, unsigned align
)
3550 assert(util_is_power_of_two_nonzero(align
));
3552 Builder
bld(ctx
->program
, ctx
->block
);
3554 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3555 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3556 info
.align_mul
= align
;
3557 info
.align_offset
= 0;
3558 info
.sync
= memory_sync_info(storage_shared
);
3559 info
.const_offset
= base_offset
;
3560 emit_lds_load(ctx
, bld
, &info
);
3565 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3570 Builder
bld(ctx
->program
, ctx
->block
);
3572 ASSERTED
bool is_subdword
= false;
3573 for (unsigned i
= 0; i
< count
; i
++)
3574 is_subdword
|= offsets
[i
] % 4;
3575 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3576 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3578 /* count == 1 fast path */
3580 if (dst_type
== RegType::sgpr
)
3581 dst
[0] = bld
.as_uniform(src
);
3583 dst
[0] = as_vgpr(ctx
, src
);
3587 for (unsigned i
= 0; i
< count
- 1; i
++)
3588 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3589 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3591 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3592 src
= as_vgpr(ctx
, src
);
3594 /* use allocated_vec if possible */
3595 auto it
= ctx
->allocated_vec
.find(src
.id());
3596 if (it
!= ctx
->allocated_vec
.end()) {
3597 if (!it
->second
[0].id())
3599 unsigned elem_size
= it
->second
[0].bytes();
3600 assert(src
.bytes() % elem_size
== 0);
3602 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3603 if (!it
->second
[i
].id())
3607 for (unsigned i
= 0; i
< count
; i
++) {
3608 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3612 for (unsigned i
= 0; i
< count
; i
++) {
3613 unsigned start_idx
= offsets
[i
] / elem_size
;
3614 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3615 if (op_count
== 1) {
3616 if (dst_type
== RegType::sgpr
)
3617 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3619 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3623 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3624 for (unsigned j
= 0; j
< op_count
; j
++) {
3625 Temp tmp
= it
->second
[start_idx
+ j
];
3626 if (dst_type
== RegType::sgpr
)
3627 tmp
= bld
.as_uniform(tmp
);
3628 vec
->operands
[j
] = Operand(tmp
);
3630 vec
->definitions
[0] = Definition(dst
[i
]);
3631 bld
.insert(std::move(vec
));
3639 if (dst_type
== RegType::sgpr
)
3640 src
= bld
.as_uniform(src
);
3643 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3644 split
->operands
[0] = Operand(src
);
3645 for (unsigned i
= 0; i
< count
; i
++)
3646 split
->definitions
[i
] = Definition(dst
[i
]);
3647 bld
.insert(std::move(split
));
3650 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3651 int *start
, int *count
)
3653 unsigned start_elem
= ffs(todo_mask
) - 1;
3654 bool skip
= !(mask
& (1 << start_elem
));
3656 mask
= ~mask
& todo_mask
;
3660 u_bit_scan_consecutive_range(&mask
, start
, count
);
3665 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3667 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3670 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3671 Temp address
, unsigned base_offset
, unsigned align
)
3673 assert(util_is_power_of_two_nonzero(align
));
3674 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3676 Builder
bld(ctx
->program
, ctx
->block
);
3677 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3678 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3680 unsigned write_count
= 0;
3681 Temp write_datas
[32];
3682 unsigned offsets
[32];
3683 aco_opcode opcodes
[32];
3685 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3687 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3690 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3691 offsets
[write_count
] = offset
;
3692 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3694 advance_write_mask(&todo
, offset
, bytes
);
3698 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3699 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3700 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3701 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3703 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3704 aco_opcode op
= aco_opcode::num_opcodes
;
3705 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3706 op
= aco_opcode::ds_write_b128
;
3708 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3709 op
= aco_opcode::ds_write_b96
;
3711 } else if (bytes
>= 8 && aligned8
) {
3712 op
= aco_opcode::ds_write_b64
;
3714 } else if (bytes
>= 4 && aligned4
) {
3715 op
= aco_opcode::ds_write_b32
;
3717 } else if (bytes
>= 2 && aligned2
) {
3718 op
= aco_opcode::ds_write_b16
;
3720 } else if (bytes
>= 1) {
3721 op
= aco_opcode::ds_write_b8
;
3727 offsets
[write_count
] = offset
;
3728 opcodes
[write_count
] = op
;
3730 advance_write_mask(&todo
, offset
, bytes
);
3733 Operand m
= load_lds_size_m0(bld
);
3735 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3737 for (unsigned i
= 0; i
< write_count
; i
++) {
3738 aco_opcode op
= opcodes
[i
];
3739 if (op
== aco_opcode::num_opcodes
)
3742 Temp data
= write_datas
[i
];
3744 unsigned second
= write_count
;
3745 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3746 for (second
= i
+ 1; second
< write_count
; second
++) {
3747 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3748 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3749 opcodes
[second
] = aco_opcode::num_opcodes
;
3755 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3756 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3758 unsigned inline_offset
= base_offset
+ offsets
[i
];
3759 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3760 Temp address_offset
= address
;
3761 if (inline_offset
> max_offset
) {
3762 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3763 inline_offset
= offsets
[i
];
3765 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3769 Temp second_data
= write_datas
[second
];
3770 inline_offset
/= data
.bytes();
3771 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3773 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3775 static_cast<DS_instruction
*>(instr
)->sync
=
3776 memory_sync_info(storage_shared
);
3780 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3782 unsigned align
= 16;
3784 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3790 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3795 return aco_opcode::buffer_store_byte
;
3798 return aco_opcode::buffer_store_short
;
3800 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3802 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3805 return aco_opcode::buffer_store_dwordx3
;
3807 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3809 unreachable("Unexpected store size");
3810 return aco_opcode::num_opcodes
;
3813 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3814 Temp data
, unsigned writemask
, int swizzle_element_size
,
3815 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3817 unsigned write_count_with_skips
= 0;
3820 /* determine how to split the data */
3821 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3824 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3825 offsets
[write_count_with_skips
] = offset
;
3826 if (skips
[write_count_with_skips
]) {
3827 advance_write_mask(&todo
, offset
, bytes
);
3828 write_count_with_skips
++;
3832 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3833 * larger than swizzle_element_size */
3834 bytes
= MIN2(bytes
, swizzle_element_size
);
3836 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3838 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3839 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3842 /* dword or larger stores have to be dword-aligned */
3843 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3844 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3845 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3847 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3849 advance_write_mask(&todo
, offset
, bytes
);
3850 write_count_with_skips
++;
3853 /* actually split data */
3854 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3857 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3860 write_datas
[*write_count
] = write_datas
[i
];
3861 offsets
[*write_count
] = offsets
[i
];
3866 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3867 unsigned split_cnt
= 0u, Temp dst
= Temp())
3869 Builder
bld(ctx
->program
, ctx
->block
);
3870 unsigned dword_size
= elem_size_bytes
/ 4;
3873 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3875 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3876 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3877 instr
->definitions
[0] = Definition(dst
);
3879 for (unsigned i
= 0; i
< cnt
; ++i
) {
3881 assert(arr
[i
].size() == dword_size
);
3882 allocated_vec
[i
] = arr
[i
];
3883 instr
->operands
[i
] = Operand(arr
[i
]);
3885 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3886 allocated_vec
[i
] = zero
;
3887 instr
->operands
[i
] = Operand(zero
);
3891 bld
.insert(std::move(instr
));
3894 emit_split_vector(ctx
, dst
, split_cnt
);
3896 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3901 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3903 if (const_offset
>= 4096) {
3904 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3905 const_offset
%= 4096u;
3908 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3909 else if (unlikely(voffset
.regClass() == s1
))
3910 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3911 else if (likely(voffset
.regClass() == v1
))
3912 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3914 unreachable("Unsupported register class of voffset");
3917 return const_offset
;
3920 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3921 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3922 bool slc
= false, bool swizzled
= false)
3925 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3926 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3928 Builder
bld(ctx
->program
, ctx
->block
);
3929 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3930 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3932 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3933 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3934 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3935 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3936 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3937 /* dlc*/ false, /* slc */ slc
);
3939 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3942 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3943 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3944 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3946 Builder
bld(ctx
->program
, ctx
->block
);
3947 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3949 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3951 unsigned write_count
= 0;
3952 Temp write_datas
[32];
3953 unsigned offsets
[32];
3954 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3955 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3957 for (unsigned i
= 0; i
< write_count
; i
++) {
3958 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3959 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3963 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3964 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3965 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3967 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3968 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3969 assert(!!stride
!= allow_combining
);
3971 Builder
bld(ctx
->program
, ctx
->block
);
3973 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3974 info
.component_stride
= allow_combining
? 0 : stride
;
3976 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3977 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3978 info
.align_offset
= 0;
3979 info
.soffset
= soffset
;
3980 info
.const_offset
= base_const_offset
;
3981 emit_mubuf_load(ctx
, bld
, &info
);
3984 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3986 Builder
bld(ctx
->program
, ctx
->block
);
3987 Temp offset
= base_offset
.first
;
3988 unsigned const_offset
= base_offset
.second
;
3990 if (!nir_src_is_const(*off_src
)) {
3991 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3994 /* Calculate indirect offset with stride */
3995 if (likely(indirect_offset_arg
.regClass() == v1
))
3996 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3997 else if (indirect_offset_arg
.regClass() == s1
)
3998 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4000 unreachable("Unsupported register class of indirect offset");
4002 /* Add to the supplied base offset */
4003 if (offset
.id() == 0)
4004 offset
= with_stride
;
4005 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4006 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4007 else if (offset
.size() == 1 && with_stride
.size() == 1)
4008 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4010 unreachable("Unsupported register class of indirect offset");
4012 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4013 const_offset
+= const_offset_arg
* stride
;
4016 return std::make_pair(offset
, const_offset
);
4019 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4021 Builder
bld(ctx
->program
, ctx
->block
);
4024 if (off1
.first
.id() && off2
.first
.id()) {
4025 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4026 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4027 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4028 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4030 unreachable("Unsupported register class of indirect offset");
4032 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4035 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4038 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4040 Builder
bld(ctx
->program
, ctx
->block
);
4041 unsigned const_offset
= offs
.second
* multiplier
;
4043 if (!offs
.first
.id())
4044 return std::make_pair(offs
.first
, const_offset
);
4046 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4047 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4048 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4050 return std::make_pair(offset
, const_offset
);
4053 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4055 Builder
bld(ctx
->program
, ctx
->block
);
4057 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4058 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4059 /* component is in bytes */
4060 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4062 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4063 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4064 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4067 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4069 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4072 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4074 Builder
bld(ctx
->program
, ctx
->block
);
4076 switch (ctx
->shader
->info
.stage
) {
4077 case MESA_SHADER_TESS_CTRL
:
4078 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4079 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4080 case MESA_SHADER_TESS_EVAL
:
4081 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4083 unreachable("Unsupported stage in get_tess_rel_patch_id");
4087 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4089 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4090 Builder
bld(ctx
->program
, ctx
->block
);
4092 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4093 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4095 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4097 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4098 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4100 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4101 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4102 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4104 return offset_mul(ctx
, offs
, 4u);
4107 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4109 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4110 Builder
bld(ctx
->program
, ctx
->block
);
4112 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4113 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4114 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4115 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4117 std::pair
<Temp
, unsigned> offs
= instr
4118 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4119 : std::make_pair(Temp(), 0u);
4121 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4122 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4127 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4128 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4130 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4131 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4133 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4134 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4140 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4142 Builder
bld(ctx
->program
, ctx
->block
);
4144 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4145 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4147 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4149 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4150 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4151 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4153 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4154 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4159 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4161 Builder
bld(ctx
->program
, ctx
->block
);
4163 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4164 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4165 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4166 unsigned attr_stride
= ctx
->tcs_num_patches
;
4168 std::pair
<Temp
, unsigned> offs
= instr
4169 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4170 : std::make_pair(Temp(), 0u);
4172 if (const_base_offset
)
4173 offs
.second
+= const_base_offset
* attr_stride
;
4175 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4176 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4177 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4182 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4184 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4189 unsigned drv_loc
= nir_intrinsic_base(instr
);
4190 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4192 if (!nir_src_is_const(*off_src
)) {
4198 uint64_t slot
= per_vertex
4199 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4200 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4201 return (((uint64_t) 1) << slot
) & mask
;
4204 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4206 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4207 unsigned component
= nir_intrinsic_component(instr
);
4208 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4210 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4211 if (off_instr
->type
!= nir_instr_type_load_const
)
4214 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4215 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4217 if (instr
->src
[0].ssa
->bit_size
== 64)
4218 write_mask
= widen_mask(write_mask
, 2);
4220 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4222 for (unsigned i
= 0; i
< 8; ++i
) {
4223 if (write_mask
& (1 << i
)) {
4224 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4225 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4233 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4235 /* Only TCS per-vertex inputs are supported by this function.
4236 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4238 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4241 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4242 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4243 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4244 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4245 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4246 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4251 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4252 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4253 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4258 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4260 Builder
bld(ctx
->program
, ctx
->block
);
4262 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4263 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4264 bool indirect_write
;
4265 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4266 if (temp_only_input
&& !indirect_write
)
4270 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4271 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4272 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4273 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4275 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4276 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4277 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4278 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4279 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4283 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4284 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4285 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4286 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4287 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4288 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4289 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4290 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4291 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4292 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4293 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4294 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4295 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4297 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4298 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4300 unreachable("Invalid LS or ES stage");
4303 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4304 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4305 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4309 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4314 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4315 return off
== ctx
->tcs_tess_lvl_out_loc
||
4316 off
== ctx
->tcs_tess_lvl_in_loc
;
4320 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4322 uint64_t mask
= per_vertex
4323 ? ctx
->program
->info
->tcs
.tes_inputs_read
4324 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4326 bool indirect_write
= false;
4327 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4328 return indirect_write
|| output_read_by_tes
;
4331 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4333 uint64_t mask
= per_vertex
4334 ? ctx
->shader
->info
.outputs_read
4335 : ctx
->shader
->info
.patch_outputs_read
;
4337 bool indirect_write
= false;
4338 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4339 return indirect_write
|| output_read
;
4342 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4344 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4345 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4347 Builder
bld(ctx
->program
, ctx
->block
);
4349 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4350 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4351 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4353 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4354 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4355 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4357 if (write_to_vmem
) {
4358 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4359 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4360 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4362 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4363 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4364 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4368 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4369 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4370 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4374 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4376 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4377 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4379 Builder
bld(ctx
->program
, ctx
->block
);
4381 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4382 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4383 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4384 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4386 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4389 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4391 if (ctx
->stage
== vertex_vs
||
4392 ctx
->stage
== tess_eval_vs
||
4393 ctx
->stage
== fragment_fs
||
4394 ctx
->stage
== ngg_vertex_gs
||
4395 ctx
->stage
== ngg_tess_eval_gs
||
4396 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4397 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4398 if (!stored_to_temps
) {
4399 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4402 } else if (ctx
->stage
== vertex_es
||
4403 ctx
->stage
== vertex_ls
||
4404 ctx
->stage
== tess_eval_es
||
4405 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4406 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4407 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4408 visit_store_ls_or_es_output(ctx
, instr
);
4409 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4410 visit_store_tcs_output(ctx
, instr
, false);
4412 unreachable("Shader stage not implemented");
4416 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4418 visit_load_tcs_output(ctx
, instr
, false);
4421 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4423 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4424 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4426 Builder
bld(ctx
->program
, ctx
->block
);
4428 if (dst
.regClass() == v2b
) {
4429 if (ctx
->program
->has_16bank_lds
) {
4430 assert(ctx
->options
->chip_class
<= GFX8
);
4431 Builder::Result interp_p1
=
4432 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4433 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4434 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4435 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4436 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4437 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4439 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4441 if (ctx
->options
->chip_class
== GFX8
)
4442 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4444 Builder::Result interp_p1
=
4445 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4446 coord1
, bld
.m0(prim_mask
), idx
, component
);
4447 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4448 interp_p1
, idx
, component
);
4451 Builder::Result interp_p1
=
4452 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4453 bld
.m0(prim_mask
), idx
, component
);
4455 if (ctx
->program
->has_16bank_lds
)
4456 interp_p1
.instr
->operands
[0].setLateKill(true);
4458 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4459 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4463 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4465 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4466 for (unsigned i
= 0; i
< num_components
; i
++)
4467 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4468 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4469 assert(num_components
== 4);
4470 Builder
bld(ctx
->program
, ctx
->block
);
4471 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4474 for (Operand
& op
: vec
->operands
)
4475 op
= op
.isUndefined() ? Operand(0u) : op
;
4477 vec
->definitions
[0] = Definition(dst
);
4478 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4479 emit_split_vector(ctx
, dst
, num_components
);
4483 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4485 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4486 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4487 unsigned idx
= nir_intrinsic_base(instr
);
4488 unsigned component
= nir_intrinsic_component(instr
);
4489 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4491 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4493 assert(offset
->u32
== 0);
4495 /* the lower 15bit of the prim_mask contain the offset into LDS
4496 * while the upper bits contain the number of prims */
4497 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4498 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4499 Builder
bld(ctx
->program
, ctx
->block
);
4500 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4501 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4502 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4503 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4504 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4507 if (instr
->dest
.ssa
.num_components
== 1) {
4508 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4510 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4511 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4513 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4514 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4515 vec
->operands
[i
] = Operand(tmp
);
4517 vec
->definitions
[0] = Definition(dst
);
4518 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4522 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4523 unsigned offset
, unsigned stride
, unsigned channels
)
4525 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4526 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4528 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4529 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4532 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4533 unsigned offset
, unsigned stride
, unsigned *channels
)
4535 if (!vtx_info
->chan_byte_size
) {
4536 *channels
= vtx_info
->num_channels
;
4537 return vtx_info
->chan_format
;
4540 unsigned num_channels
= *channels
;
4541 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4542 unsigned new_channels
= num_channels
+ 1;
4543 /* first, assume more loads is worse and try using a larger data format */
4544 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4546 /* don't make the attribute potentially out-of-bounds */
4547 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4551 if (new_channels
== 5) {
4552 /* then try decreasing load size (at the cost of more loads) */
4553 new_channels
= *channels
;
4554 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4558 if (new_channels
< *channels
)
4559 *channels
= new_channels
;
4560 num_channels
= new_channels
;
4563 switch (vtx_info
->chan_format
) {
4564 case V_008F0C_BUF_DATA_FORMAT_8
:
4565 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4566 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4567 case V_008F0C_BUF_DATA_FORMAT_16
:
4568 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4569 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4570 case V_008F0C_BUF_DATA_FORMAT_32
:
4571 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4572 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4574 unreachable("shouldn't reach here");
4575 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4578 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4579 * so we may need to fix it up. */
4580 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4582 Builder
bld(ctx
->program
, ctx
->block
);
4584 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4585 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4587 /* For the integer-like cases, do a natural sign extension.
4589 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4590 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4593 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4594 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4596 /* Convert back to the right type. */
4597 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4598 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4599 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4600 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4601 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4602 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4608 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4610 Builder
bld(ctx
->program
, ctx
->block
);
4611 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4612 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4614 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4615 if (off_instr
->type
!= nir_instr_type_load_const
) {
4616 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4618 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4620 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4622 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4623 unsigned component
= nir_intrinsic_component(instr
);
4624 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4625 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4626 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4627 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4628 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4630 unsigned dfmt
= attrib_format
& 0xf;
4631 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4632 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4634 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4635 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4636 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4637 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4639 num_channels
= MAX2(num_channels
, 3);
4641 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4642 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4645 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4646 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4647 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4649 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4651 Temp divided
= bld
.tmp(v1
);
4652 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4653 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4655 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4658 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4661 index
= bld
.vadd32(bld
.def(v1
),
4662 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4663 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4666 Temp channels
[num_channels
];
4667 unsigned channel_start
= 0;
4668 bool direct_fetch
= false;
4670 /* skip unused channels at the start */
4671 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4672 channel_start
= ffs(mask
) - 1;
4673 for (unsigned i
= 0; i
< channel_start
; i
++)
4674 channels
[i
] = Temp(0, s1
);
4675 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4676 num_channels
= 3 - (ffs(mask
) - 1);
4680 while (channel_start
< num_channels
) {
4681 unsigned fetch_component
= num_channels
- channel_start
;
4682 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4683 bool expanded
= false;
4685 /* use MUBUF when possible to avoid possible alignment issues */
4686 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4687 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4688 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4689 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4690 vtx_info
->chan_byte_size
== 4;
4691 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4693 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4695 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4696 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4697 fetch_component
= 4;
4702 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4704 Temp fetch_index
= index
;
4705 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4706 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4707 fetch_offset
= fetch_offset
% attrib_stride
;
4710 Operand
soffset(0u);
4711 if (fetch_offset
>= 4096) {
4712 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4713 fetch_offset
%= 4096;
4717 switch (fetch_bytes
) {
4719 assert(!use_mubuf
&& bitsize
== 16);
4720 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4723 if (bitsize
== 16) {
4725 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4727 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4731 assert(!use_mubuf
&& bitsize
== 16);
4732 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4735 if (bitsize
== 16) {
4737 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4739 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4743 assert(ctx
->options
->chip_class
>= GFX7
||
4744 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4745 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4748 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4751 unreachable("Unimplemented load_input vector size");
4755 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4756 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4757 num_channels
<= 3)) {
4758 direct_fetch
= true;
4761 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4766 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4767 fetch_offset
, false, false, true).instr
;
4770 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4771 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4774 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4776 if (fetch_component
== 1) {
4777 channels
[channel_start
] = fetch_dst
;
4779 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4780 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4781 bitsize
== 16 ? v2b
: v1
);
4784 channel_start
+= fetch_component
;
4787 if (!direct_fetch
) {
4788 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4789 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4791 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4792 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4793 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4795 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4796 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4797 unsigned num_temp
= 0;
4798 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4799 unsigned idx
= i
+ component
;
4800 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4801 Temp channel
= channels
[swizzle
[idx
]];
4802 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4803 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4804 vec
->operands
[i
] = Operand(channel
);
4808 } else if (is_float
&& idx
== 3) {
4809 vec
->operands
[i
] = Operand(0x3f800000u
);
4810 } else if (!is_float
&& idx
== 3) {
4811 vec
->operands
[i
] = Operand(1u);
4813 vec
->operands
[i
] = Operand(0u);
4816 vec
->definitions
[0] = Definition(dst
);
4817 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4818 emit_split_vector(ctx
, dst
, dst
.size());
4820 if (num_temp
== dst
.size())
4821 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4823 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4824 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4825 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4826 if (off_instr
->type
!= nir_instr_type_load_const
||
4827 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4828 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4831 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4832 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4834 assert(offset
->u32
== 0);
4836 /* the lower 15bit of the prim_mask contain the offset into LDS
4837 * while the upper bits contain the number of prims */
4838 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4839 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4840 Builder
bld(ctx
->program
, ctx
->block
);
4841 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4842 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4843 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4844 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4845 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4848 unsigned idx
= nir_intrinsic_base(instr
);
4849 unsigned component
= nir_intrinsic_component(instr
);
4850 unsigned vertex_id
= 2; /* P0 */
4852 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4853 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4854 switch (src0
->u32
) {
4856 vertex_id
= 2; /* P0 */
4859 vertex_id
= 0; /* P10 */
4862 vertex_id
= 1; /* P20 */
4865 unreachable("invalid vertex index");
4869 if (dst
.size() == 1) {
4870 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4872 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4873 for (unsigned i
= 0; i
< dst
.size(); i
++)
4874 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4875 vec
->definitions
[0] = Definition(dst
);
4876 bld
.insert(std::move(vec
));
4879 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4880 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4881 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4882 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4883 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4885 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4887 unreachable("Shader stage not implemented");
4891 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4893 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4895 Builder
bld(ctx
->program
, ctx
->block
);
4896 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4899 if (!nir_src_is_const(*vertex_src
)) {
4900 /* better code could be created, but this case probably doesn't happen
4901 * much in practice */
4902 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4903 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4906 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4907 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4909 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4911 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4914 if (vertex_offset
.id()) {
4915 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4916 Operand(i
), indirect_vertex
);
4917 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4919 vertex_offset
= elem
;
4923 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4924 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4926 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4927 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4928 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4929 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4930 Operand((vertex
% 2u) * 16u), Operand(16u));
4932 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4935 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4936 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4937 return offset_mul(ctx
, offs
, 4u);
4940 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4942 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4944 Builder
bld(ctx
->program
, ctx
->block
);
4945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4946 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4948 if (ctx
->stage
== geometry_gs
) {
4949 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4950 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4951 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4952 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4953 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4954 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4955 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4957 unreachable("Unsupported GS stage.");
4961 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4963 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4965 Builder
bld(ctx
->program
, ctx
->block
);
4966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4968 if (load_input_from_temps(ctx
, instr
, dst
))
4971 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4972 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4973 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4975 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4978 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4980 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4982 Builder
bld(ctx
->program
, ctx
->block
);
4984 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4985 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4988 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4989 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4991 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4994 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4996 switch (ctx
->shader
->info
.stage
) {
4997 case MESA_SHADER_GEOMETRY
:
4998 visit_load_gs_per_vertex_input(ctx
, instr
);
5000 case MESA_SHADER_TESS_CTRL
:
5001 visit_load_tcs_per_vertex_input(ctx
, instr
);
5003 case MESA_SHADER_TESS_EVAL
:
5004 visit_load_tes_per_vertex_input(ctx
, instr
);
5007 unreachable("Unimplemented shader stage");
5011 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5013 visit_load_tcs_output(ctx
, instr
, true);
5016 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5018 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5019 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5021 visit_store_tcs_output(ctx
, instr
, true);
5024 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5026 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5028 Builder
bld(ctx
->program
, ctx
->block
);
5029 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5031 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5032 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5035 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5036 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5037 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5038 tes_w
= Operand(tmp
);
5041 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5042 emit_split_vector(ctx
, tess_coord
, 3);
5045 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5047 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5048 Builder
bld(ctx
->program
, ctx
->block
);
5049 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5050 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5051 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5054 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5058 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5060 Builder
bld(ctx
->program
, ctx
->block
);
5061 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5062 if (!nir_dest_is_divergent(instr
->dest
))
5063 index
= bld
.as_uniform(index
);
5064 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5065 unsigned binding
= nir_intrinsic_binding(instr
);
5068 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5069 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5070 unsigned offset
= layout
->binding
[binding
].offset
;
5072 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5073 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5074 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5075 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5076 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5079 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5080 stride
= layout
->binding
[binding
].size
;
5083 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5084 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5086 if (nir_const_index
) {
5087 const_index
= const_index
* stride
;
5088 } else if (index
.type() == RegType::vgpr
) {
5089 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5090 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5092 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5096 if (nir_const_index
) {
5097 const_index
= const_index
+ offset
;
5098 } else if (index
.type() == RegType::vgpr
) {
5099 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5101 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5105 if (nir_const_index
&& const_index
== 0) {
5107 } else if (index
.type() == RegType::vgpr
) {
5108 index
= bld
.vadd32(bld
.def(v1
),
5109 nir_const_index
? Operand(const_index
) : Operand(index
),
5112 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5113 nir_const_index
? Operand(const_index
) : Operand(index
),
5117 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5120 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5121 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5122 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5124 Builder
bld(ctx
->program
, ctx
->block
);
5126 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5128 offset
= bld
.as_uniform(offset
);
5130 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5133 info
.align_mul
= align_mul
;
5134 info
.align_offset
= align_offset
;
5136 emit_smem_load(ctx
, bld
, &info
);
5138 emit_mubuf_load(ctx
, bld
, &info
);
5141 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5143 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5144 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5146 Builder
bld(ctx
->program
, ctx
->block
);
5148 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5149 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5150 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5151 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5153 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5154 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5155 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5156 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5157 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5158 if (ctx
->options
->chip_class
>= GFX10
) {
5159 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5160 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5161 S_008F0C_RESOURCE_LEVEL(1);
5163 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5164 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5166 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5167 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5168 Operand(0xFFFFFFFFu
),
5169 Operand(desc_type
));
5170 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5171 rsrc
, upper_dwords
);
5173 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5174 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5176 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5177 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5178 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5181 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5183 Builder
bld(ctx
->program
, ctx
->block
);
5184 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5185 unsigned offset
= nir_intrinsic_base(instr
);
5186 unsigned count
= instr
->dest
.ssa
.num_components
;
5187 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5189 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5190 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5191 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5192 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5193 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5194 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5195 for (unsigned i
= 0; i
< count
; ++i
) {
5196 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5197 vec
->operands
[i
] = Operand
{elems
[i
]};
5199 vec
->definitions
[0] = Definition(dst
);
5200 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5201 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5206 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5207 if (offset
!= 0) // TODO check if index != 0 as well
5208 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5209 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5212 bool aligned
= true;
5214 if (instr
->dest
.ssa
.bit_size
== 8) {
5215 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5216 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5218 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5219 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5220 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5222 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5227 switch (vec
.size()) {
5229 op
= aco_opcode::s_load_dword
;
5232 op
= aco_opcode::s_load_dwordx2
;
5238 op
= aco_opcode::s_load_dwordx4
;
5244 op
= aco_opcode::s_load_dwordx8
;
5247 unreachable("unimplemented or forbidden load_push_constant.");
5250 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5253 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5254 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5259 emit_split_vector(ctx
, vec
, 4);
5260 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5262 emit_extract_vector(ctx
, vec
, 0, rc
),
5263 emit_extract_vector(ctx
, vec
, 1, rc
),
5264 emit_extract_vector(ctx
, vec
, 2, rc
));
5267 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5270 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5272 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5274 Builder
bld(ctx
->program
, ctx
->block
);
5276 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5280 if (ctx
->options
->chip_class
>= GFX10
) {
5281 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5282 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5283 S_008F0C_RESOURCE_LEVEL(1);
5285 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5286 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5289 unsigned base
= nir_intrinsic_base(instr
);
5290 unsigned range
= nir_intrinsic_range(instr
);
5292 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5293 if (base
&& offset
.type() == RegType::sgpr
)
5294 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5295 else if (base
&& offset
.type() == RegType::vgpr
)
5296 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5298 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5299 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5300 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5301 Operand(desc_type
));
5302 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5303 // TODO: get alignment information for subdword constants
5304 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5307 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5309 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5310 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5312 ctx
->program
->needs_exact
= true;
5314 // TODO: optimize uniform conditions
5315 Builder
bld(ctx
->program
, ctx
->block
);
5316 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5317 assert(src
.regClass() == bld
.lm
);
5318 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5319 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5320 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5324 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5326 Builder
bld(ctx
->program
, ctx
->block
);
5328 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5329 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5331 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5332 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5334 if (ctx
->block
->loop_nest_depth
&&
5335 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5336 /* we handle discards the same way as jump instructions */
5337 append_logical_end(ctx
->block
);
5339 /* in loops, discard behaves like break */
5340 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5341 ctx
->block
->kind
|= block_kind_discard
;
5344 /* uniform discard - loop ends here */
5345 assert(nir_instr_is_last(&instr
->instr
));
5346 ctx
->block
->kind
|= block_kind_uniform
;
5347 ctx
->cf_info
.has_branch
= true;
5348 bld
.branch(aco_opcode::p_branch
);
5349 add_linear_edge(ctx
->block
->index
, linear_target
);
5353 /* we add a break right behind the discard() instructions */
5354 ctx
->block
->kind
|= block_kind_break
;
5355 unsigned idx
= ctx
->block
->index
;
5357 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5358 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5360 /* remove critical edges from linear CFG */
5361 bld
.branch(aco_opcode::p_branch
);
5362 Block
* break_block
= ctx
->program
->create_and_insert_block();
5363 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5364 break_block
->kind
|= block_kind_uniform
;
5365 add_linear_edge(idx
, break_block
);
5366 add_linear_edge(break_block
->index
, linear_target
);
5367 bld
.reset(break_block
);
5368 bld
.branch(aco_opcode::p_branch
);
5370 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5371 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5372 add_linear_edge(idx
, continue_block
);
5373 append_logical_start(continue_block
);
5374 ctx
->block
= continue_block
;
5379 /* it can currently happen that NIR doesn't remove the unreachable code */
5380 if (!nir_instr_is_last(&instr
->instr
)) {
5381 ctx
->program
->needs_exact
= true;
5382 /* save exec somewhere temporarily so that it doesn't get
5383 * overwritten before the discard from outer exec masks */
5384 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5385 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5386 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5390 /* This condition is incorrect for uniformly branched discards in a loop
5391 * predicated by a divergent condition, but the above code catches that case
5392 * and the discard would end up turning into a discard_if.
5402 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5403 /* program just ends here */
5404 ctx
->block
->kind
|= block_kind_uniform
;
5405 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5406 0 /* enabled mask */, 9 /* dest */,
5407 false /* compressed */, true/* done */, true /* valid mask */);
5408 bld
.sopp(aco_opcode::s_endpgm
);
5409 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5411 ctx
->block
->kind
|= block_kind_discard
;
5412 /* branch and linear edge is added by visit_if() */
5416 enum aco_descriptor_type
{
5427 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5428 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5430 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5431 return dim
== ac_image_cube
||
5432 dim
== ac_image_1darray
||
5433 dim
== ac_image_2darray
||
5434 dim
== ac_image_2darraymsaa
;
5437 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5438 enum aco_descriptor_type desc_type
,
5439 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5441 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5442 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5443 if (it != ctx->tex_desc.end())
5446 Temp index
= Temp();
5447 bool index_set
= false;
5448 unsigned constant_index
= 0;
5449 unsigned descriptor_set
;
5450 unsigned base_index
;
5451 Builder
bld(ctx
->program
, ctx
->block
);
5454 assert(tex_instr
&& !image
);
5456 base_index
= tex_instr
->sampler_index
;
5458 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5459 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5463 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5464 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5466 constant_index
+= array_size
* const_value
->u32
;
5468 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5469 if (indirect
.type() == RegType::vgpr
)
5470 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5472 if (array_size
!= 1)
5473 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5479 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5483 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5485 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5486 base_index
= deref_instr
->var
->data
.binding
;
5489 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5490 list
= convert_pointer_to_64_bit(ctx
, list
);
5492 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5493 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5494 unsigned offset
= binding
->offset
;
5495 unsigned stride
= binding
->size
;
5499 assert(base_index
< layout
->binding_count
);
5501 switch (desc_type
) {
5502 case ACO_DESC_IMAGE
:
5504 opcode
= aco_opcode::s_load_dwordx8
;
5506 case ACO_DESC_FMASK
:
5508 opcode
= aco_opcode::s_load_dwordx8
;
5511 case ACO_DESC_SAMPLER
:
5513 opcode
= aco_opcode::s_load_dwordx4
;
5514 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5515 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5517 case ACO_DESC_BUFFER
:
5519 opcode
= aco_opcode::s_load_dwordx4
;
5521 case ACO_DESC_PLANE_0
:
5522 case ACO_DESC_PLANE_1
:
5524 opcode
= aco_opcode::s_load_dwordx8
;
5525 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5527 case ACO_DESC_PLANE_2
:
5529 opcode
= aco_opcode::s_load_dwordx4
;
5533 unreachable("invalid desc_type\n");
5536 offset
+= constant_index
* stride
;
5538 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5539 (!index_set
|| binding
->immutable_samplers_equal
)) {
5540 if (binding
->immutable_samplers_equal
)
5543 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5544 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5545 Operand(samplers
[constant_index
* 4 + 0]),
5546 Operand(samplers
[constant_index
* 4 + 1]),
5547 Operand(samplers
[constant_index
* 4 + 2]),
5548 Operand(samplers
[constant_index
* 4 + 3]));
5553 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5555 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5556 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5559 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5561 if (desc_type
== ACO_DESC_PLANE_2
) {
5563 for (unsigned i
= 0; i
< 8; i
++)
5564 components
[i
] = bld
.tmp(s1
);
5565 bld
.pseudo(aco_opcode::p_split_vector
,
5566 Definition(components
[0]),
5567 Definition(components
[1]),
5568 Definition(components
[2]),
5569 Definition(components
[3]),
5572 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5573 bld
.pseudo(aco_opcode::p_split_vector
,
5574 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5575 Definition(components
[4]),
5576 Definition(components
[5]),
5577 Definition(components
[6]),
5578 Definition(components
[7]),
5581 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5582 components
[0], components
[1], components
[2], components
[3],
5583 components
[4], components
[5], components
[6], components
[7]);
5589 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5592 case GLSL_SAMPLER_DIM_BUF
:
5594 case GLSL_SAMPLER_DIM_1D
:
5595 return array
? 2 : 1;
5596 case GLSL_SAMPLER_DIM_2D
:
5597 return array
? 3 : 2;
5598 case GLSL_SAMPLER_DIM_MS
:
5599 return array
? 4 : 3;
5600 case GLSL_SAMPLER_DIM_3D
:
5601 case GLSL_SAMPLER_DIM_CUBE
:
5603 case GLSL_SAMPLER_DIM_RECT
:
5604 case GLSL_SAMPLER_DIM_SUBPASS
:
5606 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5615 /* Adjust the sample index according to FMASK.
5617 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5618 * which is the identity mapping. Each nibble says which physical sample
5619 * should be fetched to get that sample.
5621 * For example, 0x11111100 means there are only 2 samples stored and
5622 * the second sample covers 3/4 of the pixel. When reading samples 0
5623 * and 1, return physical sample 0 (determined by the first two 0s
5624 * in FMASK), otherwise return physical sample 1.
5626 * The sample index should be adjusted as follows:
5627 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5629 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5631 Builder
bld(ctx
->program
, ctx
->block
);
5632 Temp fmask
= bld
.tmp(v1
);
5633 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5634 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5637 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5638 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5639 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5640 load
->operands
[0] = Operand(fmask_desc_ptr
);
5641 load
->operands
[1] = Operand(s4
); /* no sampler */
5642 load
->operands
[2] = Operand(coord
);
5643 load
->definitions
[0] = Definition(fmask
);
5650 ctx
->block
->instructions
.emplace_back(std::move(load
));
5652 Operand sample_index4
;
5653 if (sample_index
.isConstant()) {
5654 if (sample_index
.constantValue() < 16) {
5655 sample_index4
= Operand(sample_index
.constantValue() << 2);
5657 sample_index4
= Operand(0u);
5659 } else if (sample_index
.regClass() == s1
) {
5660 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5662 assert(sample_index
.regClass() == v1
);
5663 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5667 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5668 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5669 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5670 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5672 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5674 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5675 * resource descriptor is 0 (invalid),
5677 Temp compare
= bld
.tmp(bld
.lm
);
5678 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5679 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5681 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5683 /* Replace the MSAA sample index. */
5684 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5687 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5690 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5691 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5692 bool is_array
= glsl_sampler_type_is_array(type
);
5693 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5694 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5695 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5696 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5697 int count
= image_type_to_components_count(dim
, is_array
);
5698 std::vector
<Temp
> coords(count
);
5699 Builder
bld(ctx
->program
, ctx
->block
);
5703 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5704 /* get sample index */
5705 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5706 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5707 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5708 std::vector
<Temp
> fmask_load_address
;
5709 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5710 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5712 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5713 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5715 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5720 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5721 coords
.resize(coords
.size() + 1);
5722 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5724 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5726 for (int i
= 0; i
< count
; i
++)
5727 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5730 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5731 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5732 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5733 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5736 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5739 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5740 for (unsigned i
= 0; i
< coords
.size(); i
++)
5741 vec
->operands
[i
] = Operand(coords
[i
]);
5742 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5743 vec
->definitions
[0] = Definition(res
);
5744 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5749 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5751 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5752 if (semantics
& semantic_atomicrmw
)
5753 return memory_sync_info(storage
, semantics
);
5755 unsigned access
= nir_intrinsic_access(instr
);
5757 if (access
& ACCESS_VOLATILE
)
5758 semantics
|= semantic_volatile
;
5759 if (access
& ACCESS_CAN_REORDER
)
5760 semantics
|= semantic_can_reorder
| semantic_private
;
5762 return memory_sync_info(storage
, semantics
);
5765 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5767 Builder
bld(ctx
->program
, ctx
->block
);
5768 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5769 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5770 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5771 bool is_array
= glsl_sampler_type_is_array(type
);
5772 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5774 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5775 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5777 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5778 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5779 unsigned num_channels
= util_last_bit(mask
);
5780 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5781 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5784 switch (num_channels
) {
5786 opcode
= aco_opcode::buffer_load_format_x
;
5789 opcode
= aco_opcode::buffer_load_format_xy
;
5792 opcode
= aco_opcode::buffer_load_format_xyz
;
5795 opcode
= aco_opcode::buffer_load_format_xyzw
;
5798 unreachable(">4 channel buffer image load");
5800 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5801 load
->operands
[0] = Operand(rsrc
);
5802 load
->operands
[1] = Operand(vindex
);
5803 load
->operands
[2] = Operand((uint32_t) 0);
5805 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5808 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5809 load
->definitions
[0] = Definition(tmp
);
5811 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5812 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5814 ctx
->block
->instructions
.emplace_back(std::move(load
));
5816 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5820 Temp coords
= get_image_coords(ctx
, instr
, type
);
5821 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5823 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5824 unsigned num_components
= util_bitcount(dmask
);
5826 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5829 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5831 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5832 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5834 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5835 load
->operands
[0] = Operand(resource
);
5836 load
->operands
[1] = Operand(s4
); /* no sampler */
5837 load
->operands
[2] = Operand(coords
);
5838 load
->definitions
[0] = Definition(tmp
);
5839 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5840 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5841 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5842 load
->dmask
= dmask
;
5844 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5846 ctx
->block
->instructions
.emplace_back(std::move(load
));
5848 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5852 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5854 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5855 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5856 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5857 bool is_array
= glsl_sampler_type_is_array(type
);
5858 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5860 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5861 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5862 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5864 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5865 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5866 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5868 switch (data
.size()) {
5870 opcode
= aco_opcode::buffer_store_format_x
;
5873 opcode
= aco_opcode::buffer_store_format_xy
;
5876 opcode
= aco_opcode::buffer_store_format_xyz
;
5879 opcode
= aco_opcode::buffer_store_format_xyzw
;
5882 unreachable(">4 channel buffer image store");
5884 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5885 store
->operands
[0] = Operand(rsrc
);
5886 store
->operands
[1] = Operand(vindex
);
5887 store
->operands
[2] = Operand((uint32_t) 0);
5888 store
->operands
[3] = Operand(data
);
5889 store
->idxen
= true;
5892 store
->disable_wqm
= true;
5894 ctx
->program
->needs_exact
= true;
5895 ctx
->block
->instructions
.emplace_back(std::move(store
));
5899 assert(data
.type() == RegType::vgpr
);
5900 Temp coords
= get_image_coords(ctx
, instr
, type
);
5901 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5903 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5904 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5906 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5907 store
->operands
[0] = Operand(resource
);
5908 store
->operands
[1] = Operand(data
);
5909 store
->operands
[2] = Operand(coords
);
5912 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5913 store
->dmask
= (1 << data
.size()) - 1;
5915 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5916 store
->disable_wqm
= true;
5918 ctx
->program
->needs_exact
= true;
5919 ctx
->block
->instructions
.emplace_back(std::move(store
));
5923 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5925 /* return the previous value if dest is ever used */
5926 bool return_previous
= false;
5927 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5928 return_previous
= true;
5931 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5932 return_previous
= true;
5936 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5937 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5938 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5939 bool is_array
= glsl_sampler_type_is_array(type
);
5940 Builder
bld(ctx
->program
, ctx
->block
);
5942 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5943 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5945 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5946 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5948 aco_opcode buf_op
, image_op
;
5949 switch (instr
->intrinsic
) {
5950 case nir_intrinsic_image_deref_atomic_add
:
5951 buf_op
= aco_opcode::buffer_atomic_add
;
5952 image_op
= aco_opcode::image_atomic_add
;
5954 case nir_intrinsic_image_deref_atomic_umin
:
5955 buf_op
= aco_opcode::buffer_atomic_umin
;
5956 image_op
= aco_opcode::image_atomic_umin
;
5958 case nir_intrinsic_image_deref_atomic_imin
:
5959 buf_op
= aco_opcode::buffer_atomic_smin
;
5960 image_op
= aco_opcode::image_atomic_smin
;
5962 case nir_intrinsic_image_deref_atomic_umax
:
5963 buf_op
= aco_opcode::buffer_atomic_umax
;
5964 image_op
= aco_opcode::image_atomic_umax
;
5966 case nir_intrinsic_image_deref_atomic_imax
:
5967 buf_op
= aco_opcode::buffer_atomic_smax
;
5968 image_op
= aco_opcode::image_atomic_smax
;
5970 case nir_intrinsic_image_deref_atomic_and
:
5971 buf_op
= aco_opcode::buffer_atomic_and
;
5972 image_op
= aco_opcode::image_atomic_and
;
5974 case nir_intrinsic_image_deref_atomic_or
:
5975 buf_op
= aco_opcode::buffer_atomic_or
;
5976 image_op
= aco_opcode::image_atomic_or
;
5978 case nir_intrinsic_image_deref_atomic_xor
:
5979 buf_op
= aco_opcode::buffer_atomic_xor
;
5980 image_op
= aco_opcode::image_atomic_xor
;
5982 case nir_intrinsic_image_deref_atomic_exchange
:
5983 buf_op
= aco_opcode::buffer_atomic_swap
;
5984 image_op
= aco_opcode::image_atomic_swap
;
5986 case nir_intrinsic_image_deref_atomic_comp_swap
:
5987 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5988 image_op
= aco_opcode::image_atomic_cmpswap
;
5991 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5994 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5995 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5997 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5998 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5999 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6000 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6001 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6002 mubuf
->operands
[0] = Operand(resource
);
6003 mubuf
->operands
[1] = Operand(vindex
);
6004 mubuf
->operands
[2] = Operand((uint32_t)0);
6005 mubuf
->operands
[3] = Operand(data
);
6006 if (return_previous
)
6007 mubuf
->definitions
[0] = Definition(dst
);
6009 mubuf
->idxen
= true;
6010 mubuf
->glc
= return_previous
;
6011 mubuf
->dlc
= false; /* Not needed for atomics */
6012 mubuf
->disable_wqm
= true;
6014 ctx
->program
->needs_exact
= true;
6015 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6019 Temp coords
= get_image_coords(ctx
, instr
, type
);
6020 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6021 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6022 mimg
->operands
[0] = Operand(resource
);
6023 mimg
->operands
[1] = Operand(data
);
6024 mimg
->operands
[2] = Operand(coords
);
6025 if (return_previous
)
6026 mimg
->definitions
[0] = Definition(dst
);
6027 mimg
->glc
= return_previous
;
6028 mimg
->dlc
= false; /* Not needed for atomics */
6029 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6030 mimg
->dmask
= (1 << data
.size()) - 1;
6032 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6033 mimg
->disable_wqm
= true;
6035 ctx
->program
->needs_exact
= true;
6036 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6040 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6042 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6043 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6044 Builder
bld(ctx
->program
, ctx
->block
);
6046 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6048 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6049 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6051 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6052 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6054 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6055 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6057 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6058 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6059 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6060 if (dst
.type() == RegType::vgpr
)
6061 bld
.copy(Definition(dst
), shr_dst
);
6063 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6065 emit_extract_vector(ctx
, desc
, 2, dst
);
6069 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6071 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6072 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6073 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6074 bool is_array
= glsl_sampler_type_is_array(type
);
6075 Builder
bld(ctx
->program
, ctx
->block
);
6077 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6078 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6079 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6083 assert(nir_src_as_uint(instr
->src
[1]) == 0);
6084 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6087 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6089 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6091 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6092 mimg
->operands
[0] = Operand(resource
);
6093 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6094 mimg
->operands
[2] = Operand(lod
);
6095 uint8_t& dmask
= mimg
->dmask
;
6096 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6097 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6098 mimg
->da
= glsl_sampler_type_is_array(type
);
6099 Definition
& def
= mimg
->definitions
[0];
6100 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6102 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6103 glsl_sampler_type_is_array(type
)) {
6105 assert(instr
->dest
.ssa
.num_components
== 3);
6106 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6107 def
= Definition(tmp
);
6108 emit_split_vector(ctx
, tmp
, 3);
6110 /* divide 3rd value by 6 by multiplying with magic number */
6111 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6112 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6114 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6115 emit_extract_vector(ctx
, tmp
, 0, v1
),
6116 emit_extract_vector(ctx
, tmp
, 1, v1
),
6119 } else if (ctx
->options
->chip_class
== GFX9
&&
6120 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6121 glsl_sampler_type_is_array(type
)) {
6122 assert(instr
->dest
.ssa
.num_components
== 2);
6123 def
= Definition(dst
);
6126 def
= Definition(dst
);
6129 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6132 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6134 Builder
bld(ctx
->program
, ctx
->block
);
6135 unsigned num_components
= instr
->num_components
;
6137 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6138 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6139 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6141 unsigned access
= nir_intrinsic_access(instr
);
6142 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6143 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6145 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6146 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6147 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6149 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6150 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6152 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6153 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6154 get_memory_sync_info(instr
, storage_buffer
, 0));
6157 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6159 Builder
bld(ctx
->program
, ctx
->block
);
6160 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6161 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6162 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6163 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6165 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6166 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6168 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6169 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6170 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6171 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6172 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6174 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6176 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6177 ctx
->options
->chip_class
>= GFX8
&&
6178 ctx
->options
->chip_class
< GFX10_3
&&
6179 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6182 offset
= bld
.as_uniform(offset
);
6183 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6185 unsigned write_count
= 0;
6186 Temp write_datas
[32];
6187 unsigned offsets
[32];
6188 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6189 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6191 for (unsigned i
= 0; i
< write_count
; i
++) {
6192 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6193 if (smem
&& ctx
->stage
== fragment_fs
)
6194 op
= aco_opcode::p_fs_buffer_store_smem
;
6197 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6198 store
->operands
[0] = Operand(rsrc
);
6200 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6201 offset
, Operand(offsets
[i
]));
6202 store
->operands
[1] = Operand(off
);
6204 store
->operands
[1] = Operand(offset
);
6206 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6207 store
->operands
[1].setFixed(m0
);
6208 store
->operands
[2] = Operand(write_datas
[i
]);
6211 store
->disable_wqm
= true;
6213 ctx
->block
->instructions
.emplace_back(std::move(store
));
6214 ctx
->program
->wb_smem_l1_on_end
= true;
6215 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6216 ctx
->block
->kind
|= block_kind_needs_lowering
;
6217 ctx
->program
->needs_exact
= true;
6220 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6221 store
->operands
[0] = Operand(rsrc
);
6222 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6223 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6224 store
->operands
[3] = Operand(write_datas
[i
]);
6225 store
->offset
= offsets
[i
];
6226 store
->offen
= (offset
.type() == RegType::vgpr
);
6229 store
->disable_wqm
= true;
6231 ctx
->program
->needs_exact
= true;
6232 ctx
->block
->instructions
.emplace_back(std::move(store
));
6237 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6239 /* return the previous value if dest is ever used */
6240 bool return_previous
= false;
6241 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6242 return_previous
= true;
6245 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6246 return_previous
= true;
6250 Builder
bld(ctx
->program
, ctx
->block
);
6251 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6253 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6254 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6255 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6257 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6258 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6259 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6261 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6263 aco_opcode op32
, op64
;
6264 switch (instr
->intrinsic
) {
6265 case nir_intrinsic_ssbo_atomic_add
:
6266 op32
= aco_opcode::buffer_atomic_add
;
6267 op64
= aco_opcode::buffer_atomic_add_x2
;
6269 case nir_intrinsic_ssbo_atomic_imin
:
6270 op32
= aco_opcode::buffer_atomic_smin
;
6271 op64
= aco_opcode::buffer_atomic_smin_x2
;
6273 case nir_intrinsic_ssbo_atomic_umin
:
6274 op32
= aco_opcode::buffer_atomic_umin
;
6275 op64
= aco_opcode::buffer_atomic_umin_x2
;
6277 case nir_intrinsic_ssbo_atomic_imax
:
6278 op32
= aco_opcode::buffer_atomic_smax
;
6279 op64
= aco_opcode::buffer_atomic_smax_x2
;
6281 case nir_intrinsic_ssbo_atomic_umax
:
6282 op32
= aco_opcode::buffer_atomic_umax
;
6283 op64
= aco_opcode::buffer_atomic_umax_x2
;
6285 case nir_intrinsic_ssbo_atomic_and
:
6286 op32
= aco_opcode::buffer_atomic_and
;
6287 op64
= aco_opcode::buffer_atomic_and_x2
;
6289 case nir_intrinsic_ssbo_atomic_or
:
6290 op32
= aco_opcode::buffer_atomic_or
;
6291 op64
= aco_opcode::buffer_atomic_or_x2
;
6293 case nir_intrinsic_ssbo_atomic_xor
:
6294 op32
= aco_opcode::buffer_atomic_xor
;
6295 op64
= aco_opcode::buffer_atomic_xor_x2
;
6297 case nir_intrinsic_ssbo_atomic_exchange
:
6298 op32
= aco_opcode::buffer_atomic_swap
;
6299 op64
= aco_opcode::buffer_atomic_swap_x2
;
6301 case nir_intrinsic_ssbo_atomic_comp_swap
:
6302 op32
= aco_opcode::buffer_atomic_cmpswap
;
6303 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6306 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6308 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6309 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6310 mubuf
->operands
[0] = Operand(rsrc
);
6311 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6312 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6313 mubuf
->operands
[3] = Operand(data
);
6314 if (return_previous
)
6315 mubuf
->definitions
[0] = Definition(dst
);
6317 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6318 mubuf
->glc
= return_previous
;
6319 mubuf
->dlc
= false; /* Not needed for atomics */
6320 mubuf
->disable_wqm
= true;
6321 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6322 ctx
->program
->needs_exact
= true;
6323 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6326 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6328 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6329 Builder
bld(ctx
->program
, ctx
->block
);
6330 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6331 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6334 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6336 Builder
bld(ctx
->program
, ctx
->block
);
6337 unsigned num_components
= instr
->num_components
;
6338 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6340 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6341 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6342 num_components
, component_size
};
6343 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6344 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6345 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6346 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6347 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6348 * it's safe to use SMEM */
6349 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6350 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6351 emit_global_load(ctx
, bld
, &info
);
6353 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6354 emit_smem_load(ctx
, bld
, &info
);
6358 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6360 Builder
bld(ctx
->program
, ctx
->block
);
6361 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6362 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6364 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6365 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6366 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6367 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6369 if (ctx
->options
->chip_class
>= GFX7
)
6370 addr
= as_vgpr(ctx
, addr
);
6372 unsigned write_count
= 0;
6373 Temp write_datas
[32];
6374 unsigned offsets
[32];
6375 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6376 16, &write_count
, write_datas
, offsets
);
6378 for (unsigned i
= 0; i
< write_count
; i
++) {
6379 if (ctx
->options
->chip_class
>= GFX7
) {
6380 unsigned offset
= offsets
[i
];
6381 Temp store_addr
= addr
;
6382 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6383 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6384 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6385 Temp carry
= bld
.tmp(bld
.lm
);
6386 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6388 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6389 Operand(offset
), addr0
);
6390 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6392 carry
).def(1).setHint(vcc
);
6394 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6399 bool global
= ctx
->options
->chip_class
>= GFX9
;
6401 switch (write_datas
[i
].bytes()) {
6403 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6406 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6409 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6412 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6415 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6418 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6421 unreachable("store_global not implemented for this size.");
6424 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6425 flat
->operands
[0] = Operand(store_addr
);
6426 flat
->operands
[1] = Operand(s1
);
6427 flat
->operands
[2] = Operand(write_datas
[i
]);
6430 flat
->offset
= offset
;
6431 flat
->disable_wqm
= true;
6433 ctx
->program
->needs_exact
= true;
6434 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6436 assert(ctx
->options
->chip_class
== GFX6
);
6438 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6440 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6442 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6443 mubuf
->operands
[0] = Operand(rsrc
);
6444 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6445 mubuf
->operands
[2] = Operand(0u);
6446 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6449 mubuf
->offset
= offsets
[i
];
6450 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6451 mubuf
->disable_wqm
= true;
6453 ctx
->program
->needs_exact
= true;
6454 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6459 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6461 /* return the previous value if dest is ever used */
6462 bool return_previous
= false;
6463 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6464 return_previous
= true;
6467 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6468 return_previous
= true;
6472 Builder
bld(ctx
->program
, ctx
->block
);
6473 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6474 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6476 if (ctx
->options
->chip_class
>= GFX7
)
6477 addr
= as_vgpr(ctx
, addr
);
6479 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6480 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6481 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6483 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6485 aco_opcode op32
, op64
;
6487 if (ctx
->options
->chip_class
>= GFX7
) {
6488 bool global
= ctx
->options
->chip_class
>= GFX9
;
6489 switch (instr
->intrinsic
) {
6490 case nir_intrinsic_global_atomic_add
:
6491 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6492 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6494 case nir_intrinsic_global_atomic_imin
:
6495 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6496 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6498 case nir_intrinsic_global_atomic_umin
:
6499 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6500 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6502 case nir_intrinsic_global_atomic_imax
:
6503 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6504 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6506 case nir_intrinsic_global_atomic_umax
:
6507 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6508 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6510 case nir_intrinsic_global_atomic_and
:
6511 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6512 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6514 case nir_intrinsic_global_atomic_or
:
6515 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6516 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6518 case nir_intrinsic_global_atomic_xor
:
6519 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6520 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6522 case nir_intrinsic_global_atomic_exchange
:
6523 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6524 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6526 case nir_intrinsic_global_atomic_comp_swap
:
6527 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6528 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6531 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6534 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6535 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6536 flat
->operands
[0] = Operand(addr
);
6537 flat
->operands
[1] = Operand(s1
);
6538 flat
->operands
[2] = Operand(data
);
6539 if (return_previous
)
6540 flat
->definitions
[0] = Definition(dst
);
6541 flat
->glc
= return_previous
;
6542 flat
->dlc
= false; /* Not needed for atomics */
6544 flat
->disable_wqm
= true;
6545 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6546 ctx
->program
->needs_exact
= true;
6547 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6549 assert(ctx
->options
->chip_class
== GFX6
);
6551 switch (instr
->intrinsic
) {
6552 case nir_intrinsic_global_atomic_add
:
6553 op32
= aco_opcode::buffer_atomic_add
;
6554 op64
= aco_opcode::buffer_atomic_add_x2
;
6556 case nir_intrinsic_global_atomic_imin
:
6557 op32
= aco_opcode::buffer_atomic_smin
;
6558 op64
= aco_opcode::buffer_atomic_smin_x2
;
6560 case nir_intrinsic_global_atomic_umin
:
6561 op32
= aco_opcode::buffer_atomic_umin
;
6562 op64
= aco_opcode::buffer_atomic_umin_x2
;
6564 case nir_intrinsic_global_atomic_imax
:
6565 op32
= aco_opcode::buffer_atomic_smax
;
6566 op64
= aco_opcode::buffer_atomic_smax_x2
;
6568 case nir_intrinsic_global_atomic_umax
:
6569 op32
= aco_opcode::buffer_atomic_umax
;
6570 op64
= aco_opcode::buffer_atomic_umax_x2
;
6572 case nir_intrinsic_global_atomic_and
:
6573 op32
= aco_opcode::buffer_atomic_and
;
6574 op64
= aco_opcode::buffer_atomic_and_x2
;
6576 case nir_intrinsic_global_atomic_or
:
6577 op32
= aco_opcode::buffer_atomic_or
;
6578 op64
= aco_opcode::buffer_atomic_or_x2
;
6580 case nir_intrinsic_global_atomic_xor
:
6581 op32
= aco_opcode::buffer_atomic_xor
;
6582 op64
= aco_opcode::buffer_atomic_xor_x2
;
6584 case nir_intrinsic_global_atomic_exchange
:
6585 op32
= aco_opcode::buffer_atomic_swap
;
6586 op64
= aco_opcode::buffer_atomic_swap_x2
;
6588 case nir_intrinsic_global_atomic_comp_swap
:
6589 op32
= aco_opcode::buffer_atomic_cmpswap
;
6590 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6593 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6596 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6598 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6600 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6601 mubuf
->operands
[0] = Operand(rsrc
);
6602 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6603 mubuf
->operands
[2] = Operand(0u);
6604 mubuf
->operands
[3] = Operand(data
);
6605 if (return_previous
)
6606 mubuf
->definitions
[0] = Definition(dst
);
6607 mubuf
->glc
= return_previous
;
6610 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6611 mubuf
->disable_wqm
= true;
6612 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6613 ctx
->program
->needs_exact
= true;
6614 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6618 sync_scope
translate_nir_scope(nir_scope scope
)
6621 case NIR_SCOPE_NONE
:
6622 case NIR_SCOPE_INVOCATION
:
6623 return scope_invocation
;
6624 case NIR_SCOPE_SUBGROUP
:
6625 return scope_subgroup
;
6626 case NIR_SCOPE_WORKGROUP
:
6627 return scope_workgroup
;
6628 case NIR_SCOPE_QUEUE_FAMILY
:
6629 return scope_queuefamily
;
6630 case NIR_SCOPE_DEVICE
:
6631 return scope_device
;
6633 unreachable("invalid scope");
6636 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6637 Builder
bld(ctx
->program
, ctx
->block
);
6639 unsigned semantics
= 0;
6640 unsigned storage
= 0;
6641 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6642 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6644 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6645 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6646 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6647 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6648 storage
|= storage_shared
;
6649 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6650 storage
|= storage_shared
;
6652 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6653 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6654 semantics
|= semantic_acquire
| semantic_release
;
6655 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6656 semantics
|= semantic_acquire
| semantic_release
;
6658 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6660 bld
.barrier(aco_opcode::p_barrier
,
6661 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6665 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6667 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6668 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6669 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6670 Builder
bld(ctx
->program
, ctx
->block
);
6672 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6673 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6674 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6677 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6679 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6680 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6681 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6682 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6684 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6685 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6688 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6690 unsigned offset
= nir_intrinsic_base(instr
);
6691 Builder
bld(ctx
->program
, ctx
->block
);
6692 Operand m
= load_lds_size_m0(bld
);
6693 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6694 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6696 unsigned num_operands
= 3;
6697 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6698 switch(instr
->intrinsic
) {
6699 case nir_intrinsic_shared_atomic_add
:
6700 op32
= aco_opcode::ds_add_u32
;
6701 op64
= aco_opcode::ds_add_u64
;
6702 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6703 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6705 case nir_intrinsic_shared_atomic_imin
:
6706 op32
= aco_opcode::ds_min_i32
;
6707 op64
= aco_opcode::ds_min_i64
;
6708 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6709 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6711 case nir_intrinsic_shared_atomic_umin
:
6712 op32
= aco_opcode::ds_min_u32
;
6713 op64
= aco_opcode::ds_min_u64
;
6714 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6715 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6717 case nir_intrinsic_shared_atomic_imax
:
6718 op32
= aco_opcode::ds_max_i32
;
6719 op64
= aco_opcode::ds_max_i64
;
6720 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6721 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6723 case nir_intrinsic_shared_atomic_umax
:
6724 op32
= aco_opcode::ds_max_u32
;
6725 op64
= aco_opcode::ds_max_u64
;
6726 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6727 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6729 case nir_intrinsic_shared_atomic_and
:
6730 op32
= aco_opcode::ds_and_b32
;
6731 op64
= aco_opcode::ds_and_b64
;
6732 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6733 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6735 case nir_intrinsic_shared_atomic_or
:
6736 op32
= aco_opcode::ds_or_b32
;
6737 op64
= aco_opcode::ds_or_b64
;
6738 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6739 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6741 case nir_intrinsic_shared_atomic_xor
:
6742 op32
= aco_opcode::ds_xor_b32
;
6743 op64
= aco_opcode::ds_xor_b64
;
6744 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6745 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6747 case nir_intrinsic_shared_atomic_exchange
:
6748 op32
= aco_opcode::ds_write_b32
;
6749 op64
= aco_opcode::ds_write_b64
;
6750 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6751 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6753 case nir_intrinsic_shared_atomic_comp_swap
:
6754 op32
= aco_opcode::ds_cmpst_b32
;
6755 op64
= aco_opcode::ds_cmpst_b64
;
6756 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6757 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6760 case nir_intrinsic_shared_atomic_fadd
:
6761 op32
= aco_opcode::ds_add_f32
;
6762 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6763 op64
= aco_opcode::num_opcodes
;
6764 op64_rtn
= aco_opcode::num_opcodes
;
6767 unreachable("Unhandled shared atomic intrinsic");
6770 /* return the previous value if dest is ever used */
6771 bool return_previous
= false;
6772 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6773 return_previous
= true;
6776 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6777 return_previous
= true;
6782 if (data
.size() == 1) {
6783 assert(instr
->dest
.ssa
.bit_size
== 32);
6784 op
= return_previous
? op32_rtn
: op32
;
6786 assert(instr
->dest
.ssa
.bit_size
== 64);
6787 op
= return_previous
? op64_rtn
: op64
;
6790 if (offset
> 65535) {
6791 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6795 aco_ptr
<DS_instruction
> ds
;
6796 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6797 ds
->operands
[0] = Operand(address
);
6798 ds
->operands
[1] = Operand(data
);
6799 if (num_operands
== 4)
6800 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6801 ds
->operands
[num_operands
- 1] = m
;
6802 ds
->offset0
= offset
;
6803 if (return_previous
)
6804 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6805 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6806 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6809 Temp
get_scratch_resource(isel_context
*ctx
)
6811 Builder
bld(ctx
->program
, ctx
->block
);
6812 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6813 if (ctx
->stage
!= compute_cs
)
6814 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6816 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6817 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6819 if (ctx
->program
->chip_class
>= GFX10
) {
6820 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6821 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6822 S_008F0C_RESOURCE_LEVEL(1);
6823 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6824 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6825 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6828 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6829 if (ctx
->program
->chip_class
<= GFX8
)
6830 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6832 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6835 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6836 Builder
bld(ctx
->program
, ctx
->block
);
6837 Temp rsrc
= get_scratch_resource(ctx
);
6838 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6839 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6841 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6842 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6843 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6844 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6845 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6846 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6847 info
.soffset
= ctx
->program
->scratch_offset
;
6848 emit_scratch_load(ctx
, bld
, &info
);
6851 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6852 Builder
bld(ctx
->program
, ctx
->block
);
6853 Temp rsrc
= get_scratch_resource(ctx
);
6854 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6855 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6857 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6858 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6860 unsigned write_count
= 0;
6861 Temp write_datas
[32];
6862 unsigned offsets
[32];
6863 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6864 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6865 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6867 for (unsigned i
= 0; i
< write_count
; i
++) {
6868 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6869 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6870 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6874 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6875 uint8_t log2_ps_iter_samples
;
6876 if (ctx
->program
->info
->ps
.force_persample
) {
6877 log2_ps_iter_samples
=
6878 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6880 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6883 /* The bit pattern matches that used by fixed function fragment
6885 static const unsigned ps_iter_masks
[] = {
6886 0xffff, /* not used */
6892 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6894 Builder
bld(ctx
->program
, ctx
->block
);
6896 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6897 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6898 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6899 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6900 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6901 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6904 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6905 Builder
bld(ctx
->program
, ctx
->block
);
6907 unsigned stream
= nir_intrinsic_stream_id(instr
);
6908 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6909 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6910 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6913 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6915 unsigned num_components
=
6916 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6917 assert(num_components
);
6919 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6920 unsigned stream_offset
= 0;
6921 for (unsigned i
= 0; i
< stream
; i
++) {
6922 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6923 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6926 /* Limit on the stride field for <= GFX7. */
6927 assert(stride
< (1 << 14));
6929 Temp gsvs_dwords
[4];
6930 for (unsigned i
= 0; i
< 4; i
++)
6931 gsvs_dwords
[i
] = bld
.tmp(s1
);
6932 bld
.pseudo(aco_opcode::p_split_vector
,
6933 Definition(gsvs_dwords
[0]),
6934 Definition(gsvs_dwords
[1]),
6935 Definition(gsvs_dwords
[2]),
6936 Definition(gsvs_dwords
[3]),
6939 if (stream_offset
) {
6940 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6942 Temp carry
= bld
.tmp(s1
);
6943 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6944 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6947 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6948 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6950 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6951 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6953 unsigned offset
= 0;
6954 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6955 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6958 for (unsigned j
= 0; j
< 4; j
++) {
6959 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6962 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6963 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6964 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6965 if (const_offset
>= 4096u) {
6966 if (vaddr_offset
.isUndefined())
6967 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6969 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6970 const_offset
%= 4096u;
6973 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6974 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6975 mtbuf
->operands
[1] = vaddr_offset
;
6976 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6977 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6978 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6979 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6980 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6981 mtbuf
->offset
= const_offset
;
6984 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6985 bld
.insert(std::move(mtbuf
));
6988 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6991 /* outputs for the next vertex are undefined and keeping them around can
6992 * create invalid IR with control flow */
6993 ctx
->outputs
.mask
[i
] = 0;
6996 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6999 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7001 Builder
bld(ctx
->program
, ctx
->block
);
7003 if (cluster_size
== 1) {
7005 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7006 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7007 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7008 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7009 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7010 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7011 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7012 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7013 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7014 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7015 //subgroupAnd(val) -> (exec & ~val) == 0
7016 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7017 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7018 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7019 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7020 //subgroupOr(val) -> (val & exec) != 0
7021 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7022 return bool_to_vector_condition(ctx
, tmp
);
7023 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7024 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7025 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7026 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7027 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7028 return bool_to_vector_condition(ctx
, tmp
);
7030 //subgroupClustered{And,Or,Xor}(val, n) ->
7031 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7032 //cluster_offset = ~(n - 1) & lane_id
7033 //cluster_mask = ((1 << n) - 1)
7034 //subgroupClusteredAnd():
7035 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7036 //subgroupClusteredOr():
7037 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7038 //subgroupClusteredXor():
7039 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7040 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7041 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7044 if (op
== nir_op_iand
)
7045 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7047 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7049 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7051 if (ctx
->program
->chip_class
<= GFX7
)
7052 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7053 else if (ctx
->program
->wave_size
== 64)
7054 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7056 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7057 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7058 if (cluster_mask
!= 0xffffffff)
7059 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7061 Definition cmp_def
= Definition();
7062 if (op
== nir_op_iand
) {
7063 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7064 } else if (op
== nir_op_ior
) {
7065 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7066 } else if (op
== nir_op_ixor
) {
7067 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7068 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7069 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7071 cmp_def
.setHint(vcc
);
7072 return cmp_def
.getTemp();
7076 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7078 Builder
bld(ctx
->program
, ctx
->block
);
7080 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7081 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7082 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7084 if (op
== nir_op_iand
)
7085 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7087 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7089 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7090 Temp lo
= lohi
.def(0).getTemp();
7091 Temp hi
= lohi
.def(1).getTemp();
7092 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7094 Definition cmp_def
= Definition();
7095 if (op
== nir_op_iand
)
7096 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7097 else if (op
== nir_op_ior
)
7098 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7099 else if (op
== nir_op_ixor
)
7100 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7101 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7102 cmp_def
.setHint(vcc
);
7103 return cmp_def
.getTemp();
7106 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7108 Builder
bld(ctx
->program
, ctx
->block
);
7110 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7111 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7112 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7113 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7114 if (op
== nir_op_iand
)
7115 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7116 else if (op
== nir_op_ior
)
7117 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7118 else if (op
== nir_op_ixor
)
7119 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7125 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7127 Builder
bld(ctx
->program
, ctx
->block
);
7128 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7129 if (src
.regClass().type() == RegType::vgpr
) {
7130 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7131 } else if (src
.regClass() == s1
) {
7132 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7133 } else if (src
.regClass() == s2
) {
7134 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7136 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7140 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7142 Builder
bld(ctx
->program
, ctx
->block
);
7143 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7144 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7145 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7147 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7148 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7149 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7150 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7153 if (ctx
->program
->chip_class
>= GFX8
) {
7154 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7155 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7156 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7157 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7158 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7159 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7161 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7162 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7163 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7164 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7165 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7166 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7167 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7168 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7169 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7170 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7173 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7174 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7175 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7176 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7177 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7178 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7179 Temp wqm1
= bld
.tmp(v1
);
7180 emit_wqm(ctx
, tmp1
, wqm1
, true);
7181 Temp wqm2
= bld
.tmp(v1
);
7182 emit_wqm(ctx
, tmp2
, wqm2
, true);
7183 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7187 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7189 Builder
bld(ctx
->program
, ctx
->block
);
7190 switch(instr
->intrinsic
) {
7191 case nir_intrinsic_load_barycentric_sample
:
7192 case nir_intrinsic_load_barycentric_pixel
:
7193 case nir_intrinsic_load_barycentric_centroid
: {
7194 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7195 Temp bary
= Temp(0, s2
);
7197 case INTERP_MODE_SMOOTH
:
7198 case INTERP_MODE_NONE
:
7199 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7200 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7201 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7202 bary
= ctx
->persp_centroid
;
7203 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7204 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7206 case INTERP_MODE_NOPERSPECTIVE
:
7207 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7208 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7209 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7210 bary
= ctx
->linear_centroid
;
7211 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7212 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7217 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7218 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7219 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7220 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7221 Operand(p1
), Operand(p2
));
7222 emit_split_vector(ctx
, dst
, 2);
7225 case nir_intrinsic_load_barycentric_model
: {
7226 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7228 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7229 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7230 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7231 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7232 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7233 Operand(p1
), Operand(p2
), Operand(p3
));
7234 emit_split_vector(ctx
, dst
, 3);
7237 case nir_intrinsic_load_barycentric_at_sample
: {
7238 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7239 switch (ctx
->options
->key
.fs
.num_samples
) {
7240 case 2: sample_pos_offset
+= 1 << 3; break;
7241 case 4: sample_pos_offset
+= 3 << 3; break;
7242 case 8: sample_pos_offset
+= 7 << 3; break;
7246 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7247 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7248 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7249 //TODO: bounds checking?
7250 if (addr
.type() == RegType::sgpr
) {
7253 sample_pos_offset
+= const_addr
->u32
<< 3;
7254 offset
= Operand(sample_pos_offset
);
7255 } else if (ctx
->options
->chip_class
>= GFX9
) {
7256 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7258 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7259 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7262 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7263 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7265 } else if (ctx
->options
->chip_class
>= GFX9
) {
7266 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7267 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7268 } else if (ctx
->options
->chip_class
>= GFX7
) {
7269 /* addr += private_segment_buffer + sample_pos_offset */
7270 Temp tmp0
= bld
.tmp(s1
);
7271 Temp tmp1
= bld
.tmp(s1
);
7272 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7273 Definition scc_tmp
= bld
.def(s1
, scc
);
7274 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7275 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7276 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7277 Temp pck0
= bld
.tmp(v1
);
7278 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7279 tmp1
= as_vgpr(ctx
, tmp1
);
7280 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7281 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7283 /* sample_pos = flat_load_dwordx2 addr */
7284 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7286 assert(ctx
->options
->chip_class
== GFX6
);
7288 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7290 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7292 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7293 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7295 sample_pos
= bld
.tmp(v2
);
7297 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7298 load
->definitions
[0] = Definition(sample_pos
);
7299 load
->operands
[0] = Operand(rsrc
);
7300 load
->operands
[1] = Operand(addr
);
7301 load
->operands
[2] = Operand(0u);
7302 load
->offset
= sample_pos_offset
;
7304 load
->addr64
= true;
7307 load
->disable_wqm
= false;
7308 ctx
->block
->instructions
.emplace_back(std::move(load
));
7311 /* sample_pos -= 0.5 */
7312 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7313 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7314 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7315 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7316 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7318 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7321 case nir_intrinsic_load_barycentric_at_offset
: {
7322 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7323 RegClass rc
= RegClass(offset
.type(), 1);
7324 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7325 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7326 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7329 case nir_intrinsic_load_front_face
: {
7330 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7331 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7334 case nir_intrinsic_load_view_index
: {
7335 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7336 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7337 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7343 case nir_intrinsic_load_layer_id
: {
7344 unsigned idx
= nir_intrinsic_base(instr
);
7345 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7346 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7349 case nir_intrinsic_load_frag_coord
: {
7350 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7353 case nir_intrinsic_load_sample_pos
: {
7354 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7355 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7356 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7357 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7358 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7361 case nir_intrinsic_load_tess_coord
:
7362 visit_load_tess_coord(ctx
, instr
);
7364 case nir_intrinsic_load_interpolated_input
:
7365 visit_load_interpolated_input(ctx
, instr
);
7367 case nir_intrinsic_store_output
:
7368 visit_store_output(ctx
, instr
);
7370 case nir_intrinsic_load_input
:
7371 case nir_intrinsic_load_input_vertex
:
7372 visit_load_input(ctx
, instr
);
7374 case nir_intrinsic_load_output
:
7375 visit_load_output(ctx
, instr
);
7377 case nir_intrinsic_load_per_vertex_input
:
7378 visit_load_per_vertex_input(ctx
, instr
);
7380 case nir_intrinsic_load_per_vertex_output
:
7381 visit_load_per_vertex_output(ctx
, instr
);
7383 case nir_intrinsic_store_per_vertex_output
:
7384 visit_store_per_vertex_output(ctx
, instr
);
7386 case nir_intrinsic_load_ubo
:
7387 visit_load_ubo(ctx
, instr
);
7389 case nir_intrinsic_load_push_constant
:
7390 visit_load_push_constant(ctx
, instr
);
7392 case nir_intrinsic_load_constant
:
7393 visit_load_constant(ctx
, instr
);
7395 case nir_intrinsic_vulkan_resource_index
:
7396 visit_load_resource(ctx
, instr
);
7398 case nir_intrinsic_discard
:
7399 visit_discard(ctx
, instr
);
7401 case nir_intrinsic_discard_if
:
7402 visit_discard_if(ctx
, instr
);
7404 case nir_intrinsic_load_shared
:
7405 visit_load_shared(ctx
, instr
);
7407 case nir_intrinsic_store_shared
:
7408 visit_store_shared(ctx
, instr
);
7410 case nir_intrinsic_shared_atomic_add
:
7411 case nir_intrinsic_shared_atomic_imin
:
7412 case nir_intrinsic_shared_atomic_umin
:
7413 case nir_intrinsic_shared_atomic_imax
:
7414 case nir_intrinsic_shared_atomic_umax
:
7415 case nir_intrinsic_shared_atomic_and
:
7416 case nir_intrinsic_shared_atomic_or
:
7417 case nir_intrinsic_shared_atomic_xor
:
7418 case nir_intrinsic_shared_atomic_exchange
:
7419 case nir_intrinsic_shared_atomic_comp_swap
:
7420 case nir_intrinsic_shared_atomic_fadd
:
7421 visit_shared_atomic(ctx
, instr
);
7423 case nir_intrinsic_image_deref_load
:
7424 visit_image_load(ctx
, instr
);
7426 case nir_intrinsic_image_deref_store
:
7427 visit_image_store(ctx
, instr
);
7429 case nir_intrinsic_image_deref_atomic_add
:
7430 case nir_intrinsic_image_deref_atomic_umin
:
7431 case nir_intrinsic_image_deref_atomic_imin
:
7432 case nir_intrinsic_image_deref_atomic_umax
:
7433 case nir_intrinsic_image_deref_atomic_imax
:
7434 case nir_intrinsic_image_deref_atomic_and
:
7435 case nir_intrinsic_image_deref_atomic_or
:
7436 case nir_intrinsic_image_deref_atomic_xor
:
7437 case nir_intrinsic_image_deref_atomic_exchange
:
7438 case nir_intrinsic_image_deref_atomic_comp_swap
:
7439 visit_image_atomic(ctx
, instr
);
7441 case nir_intrinsic_image_deref_size
:
7442 visit_image_size(ctx
, instr
);
7444 case nir_intrinsic_load_ssbo
:
7445 visit_load_ssbo(ctx
, instr
);
7447 case nir_intrinsic_store_ssbo
:
7448 visit_store_ssbo(ctx
, instr
);
7450 case nir_intrinsic_load_global
:
7451 visit_load_global(ctx
, instr
);
7453 case nir_intrinsic_store_global
:
7454 visit_store_global(ctx
, instr
);
7456 case nir_intrinsic_global_atomic_add
:
7457 case nir_intrinsic_global_atomic_imin
:
7458 case nir_intrinsic_global_atomic_umin
:
7459 case nir_intrinsic_global_atomic_imax
:
7460 case nir_intrinsic_global_atomic_umax
:
7461 case nir_intrinsic_global_atomic_and
:
7462 case nir_intrinsic_global_atomic_or
:
7463 case nir_intrinsic_global_atomic_xor
:
7464 case nir_intrinsic_global_atomic_exchange
:
7465 case nir_intrinsic_global_atomic_comp_swap
:
7466 visit_global_atomic(ctx
, instr
);
7468 case nir_intrinsic_ssbo_atomic_add
:
7469 case nir_intrinsic_ssbo_atomic_imin
:
7470 case nir_intrinsic_ssbo_atomic_umin
:
7471 case nir_intrinsic_ssbo_atomic_imax
:
7472 case nir_intrinsic_ssbo_atomic_umax
:
7473 case nir_intrinsic_ssbo_atomic_and
:
7474 case nir_intrinsic_ssbo_atomic_or
:
7475 case nir_intrinsic_ssbo_atomic_xor
:
7476 case nir_intrinsic_ssbo_atomic_exchange
:
7477 case nir_intrinsic_ssbo_atomic_comp_swap
:
7478 visit_atomic_ssbo(ctx
, instr
);
7480 case nir_intrinsic_load_scratch
:
7481 visit_load_scratch(ctx
, instr
);
7483 case nir_intrinsic_store_scratch
:
7484 visit_store_scratch(ctx
, instr
);
7486 case nir_intrinsic_get_buffer_size
:
7487 visit_get_buffer_size(ctx
, instr
);
7489 case nir_intrinsic_scoped_barrier
:
7490 emit_scoped_barrier(ctx
, instr
);
7492 case nir_intrinsic_load_num_work_groups
: {
7493 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7494 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7495 emit_split_vector(ctx
, dst
, 3);
7498 case nir_intrinsic_load_local_invocation_id
: {
7499 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7500 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7501 emit_split_vector(ctx
, dst
, 3);
7504 case nir_intrinsic_load_work_group_id
: {
7505 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7506 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7508 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7509 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7510 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7511 emit_split_vector(ctx
, dst
, 3);
7514 case nir_intrinsic_load_local_invocation_index
: {
7515 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7517 /* The tg_size bits [6:11] contain the subgroup id,
7518 * we need this multiplied by the wave size, and then OR the thread id to it.
7520 if (ctx
->program
->wave_size
== 64) {
7521 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7522 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7523 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7524 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7526 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7527 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7528 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7529 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7533 case nir_intrinsic_load_subgroup_id
: {
7534 if (ctx
->stage
== compute_cs
) {
7535 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7536 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7538 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7542 case nir_intrinsic_load_subgroup_invocation
: {
7543 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7546 case nir_intrinsic_load_num_subgroups
: {
7547 if (ctx
->stage
== compute_cs
)
7548 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7549 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7551 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7554 case nir_intrinsic_ballot
: {
7555 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7556 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7557 Definition tmp
= bld
.def(dst
.regClass());
7558 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7559 if (instr
->src
[0].ssa
->bit_size
== 1) {
7560 assert(src
.regClass() == bld
.lm
);
7561 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7562 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7563 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7564 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7565 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7567 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7569 if (dst
.size() != bld
.lm
.size()) {
7570 /* Wave32 with ballot size set to 64 */
7571 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7573 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7576 case nir_intrinsic_shuffle
:
7577 case nir_intrinsic_read_invocation
: {
7578 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7579 if (!nir_src_is_divergent(instr
->src
[0])) {
7580 emit_uniform_subgroup(ctx
, instr
, src
);
7582 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7583 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7584 tid
= bld
.as_uniform(tid
);
7585 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7586 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7587 Temp tmp
= bld
.tmp(v1
);
7588 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7589 if (dst
.type() == RegType::vgpr
)
7590 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7592 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7593 } else if (src
.regClass() == v1
) {
7594 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7595 } else if (src
.regClass() == v2
) {
7596 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7597 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7598 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7599 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7601 emit_split_vector(ctx
, dst
, 2);
7602 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7603 assert(src
.regClass() == bld
.lm
);
7604 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7605 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7606 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7607 assert(src
.regClass() == bld
.lm
);
7609 if (ctx
->program
->chip_class
<= GFX7
)
7610 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7611 else if (ctx
->program
->wave_size
== 64)
7612 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7614 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7615 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7616 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7617 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7619 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7624 case nir_intrinsic_load_sample_id
: {
7625 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7626 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7629 case nir_intrinsic_load_sample_mask_in
: {
7630 visit_load_sample_mask_in(ctx
, instr
);
7633 case nir_intrinsic_read_first_invocation
: {
7634 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7635 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7636 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7638 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7640 } else if (src
.regClass() == v2
) {
7641 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7642 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7643 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7644 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7645 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7646 emit_split_vector(ctx
, dst
, 2);
7647 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7648 assert(src
.regClass() == bld
.lm
);
7649 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7650 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7651 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7652 } else if (src
.regClass() == s1
) {
7653 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7654 } else if (src
.regClass() == s2
) {
7655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7657 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7661 case nir_intrinsic_vote_all
: {
7662 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7663 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7664 assert(src
.regClass() == bld
.lm
);
7665 assert(dst
.regClass() == bld
.lm
);
7667 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7668 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7669 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7672 case nir_intrinsic_vote_any
: {
7673 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7674 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7675 assert(src
.regClass() == bld
.lm
);
7676 assert(dst
.regClass() == bld
.lm
);
7678 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7679 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7682 case nir_intrinsic_reduce
:
7683 case nir_intrinsic_inclusive_scan
:
7684 case nir_intrinsic_exclusive_scan
: {
7685 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7686 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7687 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7688 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7689 nir_intrinsic_cluster_size(instr
) : 0;
7690 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7692 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7693 emit_uniform_subgroup(ctx
, instr
, src
);
7694 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7695 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7697 else if (op
== nir_op_iadd
)
7699 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7701 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7703 switch (instr
->intrinsic
) {
7704 case nir_intrinsic_reduce
:
7705 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7707 case nir_intrinsic_exclusive_scan
:
7708 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7710 case nir_intrinsic_inclusive_scan
:
7711 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7716 } else if (cluster_size
== 1) {
7717 bld
.copy(Definition(dst
), src
);
7719 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7721 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7725 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7726 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7741 unreachable("unknown reduction op");
7747 switch (instr
->intrinsic
) {
7748 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7749 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7750 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7752 unreachable("unknown reduce intrinsic");
7755 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7756 reduce
->operands
[0] = Operand(src
);
7757 // filled in by aco_reduce_assign.cpp, used internally as part of the
7759 assert(dst
.size() == 1 || dst
.size() == 2);
7760 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7761 reduce
->operands
[2] = Operand(v1
.as_linear());
7763 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7764 reduce
->definitions
[0] = Definition(tmp_dst
);
7765 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7766 reduce
->definitions
[2] = Definition();
7767 reduce
->definitions
[3] = Definition(scc
, s1
);
7768 reduce
->definitions
[4] = Definition();
7769 reduce
->reduce_op
= reduce_op
;
7770 reduce
->cluster_size
= cluster_size
;
7771 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7773 emit_wqm(ctx
, tmp_dst
, dst
);
7777 case nir_intrinsic_quad_broadcast
: {
7778 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7779 if (!nir_dest_is_divergent(instr
->dest
)) {
7780 emit_uniform_subgroup(ctx
, instr
, src
);
7782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7783 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7784 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7786 if (instr
->dest
.ssa
.bit_size
== 1) {
7787 assert(src
.regClass() == bld
.lm
);
7788 assert(dst
.regClass() == bld
.lm
);
7789 uint32_t half_mask
= 0x11111111u
<< lane
;
7790 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7791 Temp tmp
= bld
.tmp(bld
.lm
);
7792 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7793 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7794 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7795 emit_wqm(ctx
, tmp
, dst
);
7796 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7797 Temp tmp
= bld
.tmp(v1
);
7798 if (ctx
->program
->chip_class
>= GFX8
)
7799 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7801 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7802 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7803 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7804 Temp tmp
= bld
.tmp(v1
);
7805 if (ctx
->program
->chip_class
>= GFX8
)
7806 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7808 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7809 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7810 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7811 if (ctx
->program
->chip_class
>= GFX8
)
7812 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7814 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7815 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7816 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7817 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7818 if (ctx
->program
->chip_class
>= GFX8
) {
7819 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7820 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7822 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7823 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7825 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7826 emit_split_vector(ctx
, dst
, 2);
7828 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7833 case nir_intrinsic_quad_swap_horizontal
:
7834 case nir_intrinsic_quad_swap_vertical
:
7835 case nir_intrinsic_quad_swap_diagonal
:
7836 case nir_intrinsic_quad_swizzle_amd
: {
7837 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7838 if (!nir_dest_is_divergent(instr
->dest
)) {
7839 emit_uniform_subgroup(ctx
, instr
, src
);
7842 uint16_t dpp_ctrl
= 0;
7843 switch (instr
->intrinsic
) {
7844 case nir_intrinsic_quad_swap_horizontal
:
7845 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7847 case nir_intrinsic_quad_swap_vertical
:
7848 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7850 case nir_intrinsic_quad_swap_diagonal
:
7851 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7853 case nir_intrinsic_quad_swizzle_amd
:
7854 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7859 if (ctx
->program
->chip_class
< GFX8
)
7860 dpp_ctrl
|= (1 << 15);
7862 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7863 if (instr
->dest
.ssa
.bit_size
== 1) {
7864 assert(src
.regClass() == bld
.lm
);
7865 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7866 if (ctx
->program
->chip_class
>= GFX8
)
7867 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7869 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7870 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7871 emit_wqm(ctx
, tmp
, dst
);
7872 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7873 Temp tmp
= bld
.tmp(v1
);
7874 if (ctx
->program
->chip_class
>= GFX8
)
7875 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7877 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7879 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7880 Temp tmp
= bld
.tmp(v1
);
7881 if (ctx
->program
->chip_class
>= GFX8
)
7882 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7884 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7885 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7886 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7888 if (ctx
->program
->chip_class
>= GFX8
)
7889 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7891 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7892 emit_wqm(ctx
, tmp
, dst
);
7893 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7894 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7895 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7896 if (ctx
->program
->chip_class
>= GFX8
) {
7897 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7898 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7900 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7901 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7903 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7904 emit_split_vector(ctx
, dst
, 2);
7906 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7910 case nir_intrinsic_masked_swizzle_amd
: {
7911 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7912 if (!nir_dest_is_divergent(instr
->dest
)) {
7913 emit_uniform_subgroup(ctx
, instr
, src
);
7916 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7917 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7918 if (instr
->dest
.ssa
.bit_size
== 1) {
7919 assert(src
.regClass() == bld
.lm
);
7920 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7921 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7922 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7923 emit_wqm(ctx
, tmp
, dst
);
7924 } else if (dst
.regClass() == v1b
) {
7925 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7926 emit_extract_vector(ctx
, tmp
, 0, dst
);
7927 } else if (dst
.regClass() == v2b
) {
7928 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7929 emit_extract_vector(ctx
, tmp
, 0, dst
);
7930 } else if (dst
.regClass() == v1
) {
7931 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7932 } else if (dst
.regClass() == v2
) {
7933 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7935 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7936 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7937 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7938 emit_split_vector(ctx
, dst
, 2);
7940 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7944 case nir_intrinsic_write_invocation_amd
: {
7945 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7946 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7947 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7948 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7949 if (dst
.regClass() == v1
) {
7950 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7951 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7952 } else if (dst
.regClass() == v2
) {
7953 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7954 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7956 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7957 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7958 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7959 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7960 emit_split_vector(ctx
, dst
, 2);
7962 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7966 case nir_intrinsic_mbcnt_amd
: {
7967 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7968 RegClass rc
= RegClass(src
.type(), 1);
7969 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7970 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7973 emit_wqm(ctx
, wqm_tmp
, dst
);
7976 case nir_intrinsic_load_helper_invocation
: {
7977 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7978 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7979 ctx
->block
->kind
|= block_kind_needs_lowering
;
7980 ctx
->program
->needs_exact
= true;
7983 case nir_intrinsic_is_helper_invocation
: {
7984 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7985 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7986 ctx
->block
->kind
|= block_kind_needs_lowering
;
7987 ctx
->program
->needs_exact
= true;
7990 case nir_intrinsic_demote
:
7991 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7993 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7994 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7995 ctx
->block
->kind
|= block_kind_uses_demote
;
7996 ctx
->program
->needs_exact
= true;
7998 case nir_intrinsic_demote_if
: {
7999 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8000 assert(src
.regClass() == bld
.lm
);
8001 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8002 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8004 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8005 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8006 ctx
->block
->kind
|= block_kind_uses_demote
;
8007 ctx
->program
->needs_exact
= true;
8010 case nir_intrinsic_first_invocation
: {
8011 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8012 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8015 case nir_intrinsic_shader_clock
: {
8016 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8017 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
8018 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
8019 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
8020 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
8023 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8024 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8025 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
8027 emit_split_vector(ctx
, dst
, 2);
8030 case nir_intrinsic_load_vertex_id_zero_base
: {
8031 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8032 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8035 case nir_intrinsic_load_first_vertex
: {
8036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8037 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8040 case nir_intrinsic_load_base_instance
: {
8041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8042 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8045 case nir_intrinsic_load_instance_id
: {
8046 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8047 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8050 case nir_intrinsic_load_draw_id
: {
8051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8052 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8055 case nir_intrinsic_load_invocation_id
: {
8056 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8058 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8059 if (ctx
->options
->chip_class
>= GFX10
)
8060 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8062 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8063 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8064 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8065 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8067 unreachable("Unsupported stage for load_invocation_id");
8072 case nir_intrinsic_load_primitive_id
: {
8073 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8075 switch (ctx
->shader
->info
.stage
) {
8076 case MESA_SHADER_GEOMETRY
:
8077 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8079 case MESA_SHADER_TESS_CTRL
:
8080 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8082 case MESA_SHADER_TESS_EVAL
:
8083 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8086 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8091 case nir_intrinsic_load_patch_vertices_in
: {
8092 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8093 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8096 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8099 case nir_intrinsic_emit_vertex_with_counter
: {
8100 visit_emit_vertex_with_counter(ctx
, instr
);
8103 case nir_intrinsic_end_primitive_with_counter
: {
8104 unsigned stream
= nir_intrinsic_stream_id(instr
);
8105 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8108 case nir_intrinsic_set_vertex_count
: {
8109 /* unused, the HW keeps track of this for us */
8113 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8121 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8122 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8123 enum glsl_base_type
*stype
)
8125 nir_deref_instr
*texture_deref_instr
= NULL
;
8126 nir_deref_instr
*sampler_deref_instr
= NULL
;
8129 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8130 switch (instr
->src
[i
].src_type
) {
8131 case nir_tex_src_texture_deref
:
8132 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8134 case nir_tex_src_sampler_deref
:
8135 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8137 case nir_tex_src_plane
:
8138 plane
= nir_src_as_int(instr
->src
[i
].src
);
8145 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8147 if (!sampler_deref_instr
)
8148 sampler_deref_instr
= texture_deref_instr
;
8151 assert(instr
->op
!= nir_texop_txf_ms
&&
8152 instr
->op
!= nir_texop_samples_identical
);
8153 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8154 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8155 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8156 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8157 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8158 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8160 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8163 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8165 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8166 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8167 Builder
bld(ctx
->program
, ctx
->block
);
8169 /* to avoid unnecessary moves, we split and recombine sampler and image */
8170 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8171 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8172 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8173 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8174 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8175 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8176 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8177 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8179 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8180 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8181 img
[0], img
[1], img
[2], img
[3],
8182 img
[4], img
[5], img
[6], img
[7]);
8183 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8184 samp
[0], samp
[1], samp
[2], samp
[3]);
8187 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8188 instr
->op
== nir_texop_samples_identical
))
8189 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8192 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8193 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8195 Builder
bld(ctx
->program
, ctx
->block
);
8197 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8198 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8199 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8201 Operand
neg_one(0xbf800000u
);
8202 Operand
one(0x3f800000u
);
8203 Operand
two(0x40000000u
);
8204 Operand
four(0x40800000u
);
8206 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8207 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8208 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8210 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8211 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8212 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8213 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8216 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8217 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8218 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8220 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8223 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8224 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8225 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8228 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8229 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8231 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8232 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8235 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8237 Builder
bld(ctx
->program
, ctx
->block
);
8238 Temp ma
, tc
, sc
, id
;
8239 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8240 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8243 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8245 // see comment in ac_prepare_cube_coords()
8246 if (ctx
->options
->chip_class
<= GFX8
)
8247 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8250 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8252 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8253 vop3a
->operands
[0] = Operand(ma
);
8254 vop3a
->abs
[0] = true;
8255 Temp invma
= bld
.tmp(v1
);
8256 vop3a
->definitions
[0] = Definition(invma
);
8257 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8259 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8261 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8263 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8265 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8267 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8270 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8271 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8273 for (unsigned i
= 0; i
< 2; i
++) {
8274 // see comment in ac_prepare_cube_coords()
8276 Temp deriv_sc
, deriv_tc
;
8277 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8278 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8280 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8282 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8283 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8284 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8285 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8286 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8287 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8288 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8291 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8292 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8296 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8303 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8305 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8307 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8308 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8311 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8312 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8313 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8317 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8319 Builder
bld(ctx
->program
, ctx
->block
);
8320 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8321 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8322 has_clamped_lod
= false;
8323 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8324 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8325 clamped_lod
= Temp();
8326 std::vector
<Temp
> coords
;
8327 std::vector
<Temp
> derivs
;
8328 nir_const_value
*sample_index_cv
= NULL
;
8329 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8330 enum glsl_base_type stype
;
8331 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8333 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8334 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8335 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8336 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8338 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8339 switch (instr
->src
[i
].src_type
) {
8340 case nir_tex_src_coord
: {
8341 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8342 for (unsigned i
= 0; i
< coord
.size(); i
++)
8343 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8346 case nir_tex_src_bias
:
8347 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8350 case nir_tex_src_lod
: {
8351 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8353 if (val
&& val
->f32
<= 0.0) {
8356 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8361 case nir_tex_src_min_lod
:
8362 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8363 has_clamped_lod
= true;
8365 case nir_tex_src_comparator
:
8366 if (instr
->is_shadow
) {
8367 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8371 case nir_tex_src_offset
:
8372 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8373 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8376 case nir_tex_src_ddx
:
8377 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8380 case nir_tex_src_ddy
:
8381 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8384 case nir_tex_src_ms_index
:
8385 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8386 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8387 has_sample_index
= true;
8389 case nir_tex_src_texture_offset
:
8390 case nir_tex_src_sampler_offset
:
8396 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8397 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8399 if (instr
->op
== nir_texop_texture_samples
) {
8400 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8402 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8403 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8404 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8406 Operand default_sample
= Operand(1u);
8407 if (ctx
->options
->robust_buffer_access
) {
8408 /* Extract the second dword of the descriptor, if it's
8409 * all zero, then it's a null descriptor.
8411 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8412 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8413 default_sample
= Operand(is_non_null_descriptor
);
8416 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8418 samples
, default_sample
, bld
.scc(is_msaa
));
8422 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8423 aco_ptr
<Instruction
> tmp_instr
;
8424 Temp acc
, pack
= Temp();
8426 uint32_t pack_const
= 0;
8427 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8428 if (!const_offset
[i
])
8430 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8433 if (offset
.type() == RegType::sgpr
) {
8434 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8435 if (const_offset
[i
])
8438 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8439 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8442 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8445 if (pack
== Temp()) {
8448 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8452 if (pack_const
&& pack
!= Temp())
8453 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8455 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8456 if (const_offset
[i
])
8459 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8460 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8463 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8466 if (pack
== Temp()) {
8469 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8473 if (pack_const
&& pack
!= Temp())
8474 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8476 if (pack_const
&& pack
== Temp())
8477 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8478 else if (pack
== Temp())
8484 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8485 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8487 /* pack derivatives */
8488 if (has_ddx
|| has_ddy
) {
8489 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8490 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8491 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8492 derivs
= {ddx
, zero
, ddy
, zero
};
8494 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8495 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8496 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8497 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8502 if (instr
->coord_components
> 1 &&
8503 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8505 instr
->op
!= nir_texop_txf
)
8506 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8508 if (instr
->coord_components
> 2 &&
8509 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8510 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8511 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8512 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8514 instr
->op
!= nir_texop_txf
&&
8515 instr
->op
!= nir_texop_txf_ms
&&
8516 instr
->op
!= nir_texop_fragment_fetch
&&
8517 instr
->op
!= nir_texop_fragment_mask_fetch
)
8518 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8520 if (ctx
->options
->chip_class
== GFX9
&&
8521 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8522 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8523 assert(coords
.size() > 0 && coords
.size() < 3);
8525 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8526 Operand((uint32_t) 0) :
8527 Operand((uint32_t) 0x3f000000)));
8530 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8532 if (instr
->op
== nir_texop_samples_identical
)
8533 resource
= fmask_ptr
;
8535 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8536 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8537 instr
->op
!= nir_texop_txs
&&
8538 instr
->op
!= nir_texop_fragment_fetch
&&
8539 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8540 assert(has_sample_index
);
8541 Operand
op(sample_index
);
8542 if (sample_index_cv
)
8543 op
= Operand(sample_index_cv
->u32
);
8544 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8547 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8548 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8549 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8550 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8555 /* Build tex instruction */
8556 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8557 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8558 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8560 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8563 /* gather4 selects the component by dmask and always returns vec4 */
8564 if (instr
->op
== nir_texop_tg4
) {
8565 assert(instr
->dest
.ssa
.num_components
== 4);
8566 if (instr
->is_shadow
)
8569 dmask
= 1 << instr
->component
;
8570 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8571 tmp_dst
= bld
.tmp(v4
);
8572 } else if (instr
->op
== nir_texop_samples_identical
) {
8573 tmp_dst
= bld
.tmp(v1
);
8574 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8575 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8578 aco_ptr
<MIMG_instruction
> tex
;
8579 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8581 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8583 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8584 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8587 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8588 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8590 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8591 tex
->operands
[0] = Operand(resource
);
8592 tex
->operands
[1] = Operand(s4
); /* no sampler */
8593 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8594 if (ctx
->options
->chip_class
== GFX9
&&
8595 instr
->op
== nir_texop_txs
&&
8596 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8598 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8599 } else if (instr
->op
== nir_texop_query_levels
) {
8600 tex
->dmask
= 1 << 3;
8605 tex
->definitions
[0] = Definition(tmp_dst
);
8607 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8610 /* divide 3rd value by 6 by multiplying with magic number */
8611 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8612 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8613 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8614 assert(instr
->dest
.ssa
.num_components
== 3);
8615 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8616 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8617 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8618 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8623 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8627 Temp tg4_compare_cube_wa64
= Temp();
8629 if (tg4_integer_workarounds
) {
8630 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8631 tex
->operands
[0] = Operand(resource
);
8632 tex
->operands
[1] = Operand(s4
); /* no sampler */
8633 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8637 Temp size
= bld
.tmp(v2
);
8638 tex
->definitions
[0] = Definition(size
);
8639 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8640 emit_split_vector(ctx
, size
, size
.size());
8643 for (unsigned i
= 0; i
< 2; i
++) {
8644 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8645 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8646 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8647 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8650 Temp new_coords
[2] = {
8651 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8652 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8655 if (tg4_integer_cube_workaround
) {
8656 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8657 Temp desc
[resource
.size()];
8658 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8659 Format::PSEUDO
, 1, resource
.size())};
8660 split
->operands
[0] = Operand(resource
);
8661 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8662 desc
[i
] = bld
.tmp(s1
);
8663 split
->definitions
[i
] = Definition(desc
[i
]);
8665 ctx
->block
->instructions
.emplace_back(std::move(split
));
8667 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8668 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8669 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8672 if (stype
== GLSL_TYPE_UINT
) {
8673 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8674 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8675 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8676 bld
.scc(compare_cube_wa
));
8678 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8679 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8680 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8681 bld
.scc(compare_cube_wa
));
8683 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8684 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8686 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8688 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8689 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8690 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8692 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8693 Format::PSEUDO
, resource
.size(), 1)};
8694 for (unsigned i
= 0; i
< resource
.size(); i
++)
8695 vec
->operands
[i
] = Operand(desc
[i
]);
8696 resource
= bld
.tmp(resource
.regClass());
8697 vec
->definitions
[0] = Definition(resource
);
8698 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8700 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8701 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8702 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8703 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8705 coords
[0] = new_coords
[0];
8706 coords
[1] = new_coords
[1];
8709 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8710 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8712 assert(coords
.size() == 1);
8713 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8717 op
= aco_opcode::buffer_load_format_x
; break;
8719 op
= aco_opcode::buffer_load_format_xy
; break;
8721 op
= aco_opcode::buffer_load_format_xyz
; break;
8723 op
= aco_opcode::buffer_load_format_xyzw
; break;
8725 unreachable("Tex instruction loads more than 4 components.");
8728 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8729 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8732 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8734 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8735 mubuf
->operands
[0] = Operand(resource
);
8736 mubuf
->operands
[1] = Operand(coords
[0]);
8737 mubuf
->operands
[2] = Operand((uint32_t) 0);
8738 mubuf
->definitions
[0] = Definition(tmp_dst
);
8739 mubuf
->idxen
= true;
8740 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8742 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8746 /* gather MIMG address components */
8747 std::vector
<Temp
> args
;
8749 args
.emplace_back(offset
);
8751 args
.emplace_back(bias
);
8753 args
.emplace_back(compare
);
8755 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8757 args
.insert(args
.end(), coords
.begin(), coords
.end());
8758 if (has_sample_index
)
8759 args
.emplace_back(sample_index
);
8761 args
.emplace_back(lod
);
8762 if (has_clamped_lod
)
8763 args
.emplace_back(clamped_lod
);
8765 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8766 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8767 vec
->definitions
[0] = Definition(arg
);
8768 for (unsigned i
= 0; i
< args
.size(); i
++)
8769 vec
->operands
[i
] = Operand(args
[i
]);
8770 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8773 if (instr
->op
== nir_texop_txf
||
8774 instr
->op
== nir_texop_txf_ms
||
8775 instr
->op
== nir_texop_samples_identical
||
8776 instr
->op
== nir_texop_fragment_fetch
||
8777 instr
->op
== nir_texop_fragment_mask_fetch
) {
8778 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8779 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8780 tex
->operands
[0] = Operand(resource
);
8781 tex
->operands
[1] = Operand(s4
); /* no sampler */
8782 tex
->operands
[2] = Operand(arg
);
8787 tex
->definitions
[0] = Definition(tmp_dst
);
8788 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8790 if (instr
->op
== nir_texop_samples_identical
) {
8791 assert(dmask
== 1 && dst
.regClass() == v1
);
8792 assert(dst
.id() != tmp_dst
.id());
8794 Temp tmp
= bld
.tmp(bld
.lm
);
8795 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8796 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8799 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8804 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8805 aco_opcode opcode
= aco_opcode::image_sample
;
8806 if (has_offset
) { /* image_sample_*_o */
8807 if (has_clamped_lod
) {
8809 opcode
= aco_opcode::image_sample_c_cl_o
;
8811 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8813 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8815 opcode
= aco_opcode::image_sample_cl_o
;
8817 opcode
= aco_opcode::image_sample_d_cl_o
;
8819 opcode
= aco_opcode::image_sample_b_cl_o
;
8821 } else if (has_compare
) {
8822 opcode
= aco_opcode::image_sample_c_o
;
8824 opcode
= aco_opcode::image_sample_c_d_o
;
8826 opcode
= aco_opcode::image_sample_c_b_o
;
8828 opcode
= aco_opcode::image_sample_c_lz_o
;
8830 opcode
= aco_opcode::image_sample_c_l_o
;
8832 opcode
= aco_opcode::image_sample_o
;
8834 opcode
= aco_opcode::image_sample_d_o
;
8836 opcode
= aco_opcode::image_sample_b_o
;
8838 opcode
= aco_opcode::image_sample_lz_o
;
8840 opcode
= aco_opcode::image_sample_l_o
;
8842 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8844 opcode
= aco_opcode::image_sample_c_cl
;
8846 opcode
= aco_opcode::image_sample_c_d_cl
;
8848 opcode
= aco_opcode::image_sample_c_b_cl
;
8850 opcode
= aco_opcode::image_sample_cl
;
8852 opcode
= aco_opcode::image_sample_d_cl
;
8854 opcode
= aco_opcode::image_sample_b_cl
;
8856 } else { /* no offset */
8858 opcode
= aco_opcode::image_sample_c
;
8860 opcode
= aco_opcode::image_sample_c_d
;
8862 opcode
= aco_opcode::image_sample_c_b
;
8864 opcode
= aco_opcode::image_sample_c_lz
;
8866 opcode
= aco_opcode::image_sample_c_l
;
8868 opcode
= aco_opcode::image_sample
;
8870 opcode
= aco_opcode::image_sample_d
;
8872 opcode
= aco_opcode::image_sample_b
;
8874 opcode
= aco_opcode::image_sample_lz
;
8876 opcode
= aco_opcode::image_sample_l
;
8880 if (instr
->op
== nir_texop_tg4
) {
8881 if (has_offset
) { /* image_gather4_*_o */
8883 opcode
= aco_opcode::image_gather4_c_lz_o
;
8885 opcode
= aco_opcode::image_gather4_c_l_o
;
8887 opcode
= aco_opcode::image_gather4_c_b_o
;
8889 opcode
= aco_opcode::image_gather4_lz_o
;
8891 opcode
= aco_opcode::image_gather4_l_o
;
8893 opcode
= aco_opcode::image_gather4_b_o
;
8897 opcode
= aco_opcode::image_gather4_c_lz
;
8899 opcode
= aco_opcode::image_gather4_c_l
;
8901 opcode
= aco_opcode::image_gather4_c_b
;
8903 opcode
= aco_opcode::image_gather4_lz
;
8905 opcode
= aco_opcode::image_gather4_l
;
8907 opcode
= aco_opcode::image_gather4_b
;
8910 } else if (instr
->op
== nir_texop_lod
) {
8911 opcode
= aco_opcode::image_get_lod
;
8914 /* we don't need the bias, sample index, compare value or offset to be
8915 * computed in WQM but if the p_create_vector copies the coordinates, then it
8916 * needs to be in WQM */
8917 if (ctx
->stage
== fragment_fs
&&
8918 !has_derivs
&& !has_lod
&& !level_zero
&&
8919 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8920 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8921 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8923 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8924 tex
->operands
[0] = Operand(resource
);
8925 tex
->operands
[1] = Operand(sampler
);
8926 tex
->operands
[2] = Operand(arg
);
8930 tex
->definitions
[0] = Definition(tmp_dst
);
8931 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8933 if (tg4_integer_cube_workaround
) {
8934 assert(tmp_dst
.id() != dst
.id());
8935 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8937 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8939 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8940 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8942 if (stype
== GLSL_TYPE_UINT
)
8943 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8945 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8946 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8948 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8949 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8950 val
[0], val
[1], val
[2], val
[3]);
8952 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8953 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8958 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8960 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8961 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8963 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8964 if (ctx
->program
->wave_size
== 64)
8965 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8967 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8969 return Operand(tmp
);
8973 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8975 aco_ptr
<Pseudo_instruction
> phi
;
8976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8977 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8979 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8980 logical
|= ctx
->block
->kind
& block_kind_merge
;
8981 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8983 /* we want a sorted list of sources, since the predecessor list is also sorted */
8984 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8985 nir_foreach_phi_src(src
, instr
)
8986 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8988 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8989 unsigned num_operands
= 0;
8990 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8991 unsigned num_defined
= 0;
8992 unsigned cur_pred_idx
= 0;
8993 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8994 if (cur_pred_idx
< preds
.size()) {
8995 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8996 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8997 unsigned skipped
= 0;
8998 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
9000 if (cur_pred_idx
+ skipped
< preds
.size()) {
9001 for (unsigned i
= 0; i
< skipped
; i
++)
9002 operands
[num_operands
++] = Operand(dst
.regClass());
9003 cur_pred_idx
+= skipped
;
9008 /* Handle missing predecessors at the end. This shouldn't happen with loop
9009 * headers and we can't ignore these sources for loop header phis. */
9010 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9013 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
9014 operands
[num_operands
++] = op
;
9015 num_defined
+= !op
.isUndefined();
9017 /* handle block_kind_continue_or_break at loop exit blocks */
9018 while (cur_pred_idx
++ < preds
.size())
9019 operands
[num_operands
++] = Operand(dst
.regClass());
9021 /* If the loop ends with a break, still add a linear continue edge in case
9022 * that break is divergent or continue_or_break is used. We'll either remove
9023 * this operand later in visit_loop() if it's not necessary or replace the
9024 * undef with something correct. */
9025 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9026 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9027 nir_block
*last
= nir_loop_last_block(loop
);
9028 if (last
->successors
[0] != instr
->instr
.block
)
9029 operands
[num_operands
++] = Operand(RegClass());
9032 if (num_defined
== 0) {
9033 Builder
bld(ctx
->program
, ctx
->block
);
9034 if (dst
.regClass() == s1
) {
9035 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9036 } else if (dst
.regClass() == v1
) {
9037 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9039 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9040 for (unsigned i
= 0; i
< dst
.size(); i
++)
9041 vec
->operands
[i
] = Operand(0u);
9042 vec
->definitions
[0] = Definition(dst
);
9043 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9048 /* we can use a linear phi in some cases if one src is undef */
9049 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9050 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9052 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9053 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9054 assert(invert
->kind
& block_kind_invert
);
9056 unsigned then_block
= invert
->linear_preds
[0];
9058 Block
* insert_block
= NULL
;
9059 for (unsigned i
= 0; i
< num_operands
; i
++) {
9060 Operand op
= operands
[i
];
9061 if (op
.isUndefined())
9063 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9064 phi
->operands
[0] = op
;
9067 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9068 phi
->operands
[1] = Operand(dst
.regClass());
9069 phi
->definitions
[0] = Definition(dst
);
9070 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9074 /* try to scalarize vector phis */
9075 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9076 // TODO: scalarize linear phis on divergent ifs
9077 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9078 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9079 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9080 Operand src
= operands
[i
];
9081 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9082 can_scalarize
= false;
9084 if (can_scalarize
) {
9085 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9086 assert(dst
.size() % num_components
== 0);
9087 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9089 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9090 for (unsigned k
= 0; k
< num_components
; k
++) {
9091 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9092 for (unsigned i
= 0; i
< num_operands
; i
++) {
9093 Operand src
= operands
[i
];
9094 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9096 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9097 phi
->definitions
[0] = Definition(phi_dst
);
9098 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9099 new_vec
[k
] = phi_dst
;
9100 vec
->operands
[k
] = Operand(phi_dst
);
9102 vec
->definitions
[0] = Definition(dst
);
9103 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9104 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9109 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9110 for (unsigned i
= 0; i
< num_operands
; i
++)
9111 phi
->operands
[i
] = operands
[i
];
9112 phi
->definitions
[0] = Definition(dst
);
9113 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9117 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9119 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9121 assert(dst
.type() == RegType::sgpr
);
9123 if (dst
.size() == 1) {
9124 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9126 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9127 for (unsigned i
= 0; i
< dst
.size(); i
++)
9128 vec
->operands
[i
] = Operand(0u);
9129 vec
->definitions
[0] = Definition(dst
);
9130 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9134 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9136 Builder
bld(ctx
->program
, ctx
->block
);
9137 Block
*logical_target
;
9138 append_logical_end(ctx
->block
);
9139 unsigned idx
= ctx
->block
->index
;
9141 switch (instr
->type
) {
9142 case nir_jump_break
:
9143 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9144 add_logical_edge(idx
, logical_target
);
9145 ctx
->block
->kind
|= block_kind_break
;
9147 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9148 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9149 /* uniform break - directly jump out of the loop */
9150 ctx
->block
->kind
|= block_kind_uniform
;
9151 ctx
->cf_info
.has_branch
= true;
9152 bld
.branch(aco_opcode::p_branch
);
9153 add_linear_edge(idx
, logical_target
);
9156 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9157 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9159 case nir_jump_continue
:
9160 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9161 add_logical_edge(idx
, logical_target
);
9162 ctx
->block
->kind
|= block_kind_continue
;
9164 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9165 /* for potential uniform breaks after this continue,
9166 we must ensure that they are handled correctly */
9167 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9168 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9169 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9171 /* uniform continue - directly jump to the loop header */
9172 ctx
->block
->kind
|= block_kind_uniform
;
9173 ctx
->cf_info
.has_branch
= true;
9174 bld
.branch(aco_opcode::p_branch
);
9175 add_linear_edge(idx
, logical_target
);
9180 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9184 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9185 ctx
->cf_info
.exec_potentially_empty_break
= true;
9186 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9189 /* remove critical edges from linear CFG */
9190 bld
.branch(aco_opcode::p_branch
);
9191 Block
* break_block
= ctx
->program
->create_and_insert_block();
9192 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9193 break_block
->kind
|= block_kind_uniform
;
9194 add_linear_edge(idx
, break_block
);
9195 /* the loop_header pointer might be invalidated by this point */
9196 if (instr
->type
== nir_jump_continue
)
9197 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9198 add_linear_edge(break_block
->index
, logical_target
);
9199 bld
.reset(break_block
);
9200 bld
.branch(aco_opcode::p_branch
);
9202 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9203 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9204 add_linear_edge(idx
, continue_block
);
9205 append_logical_start(continue_block
);
9206 ctx
->block
= continue_block
;
9210 void visit_block(isel_context
*ctx
, nir_block
*block
)
9212 nir_foreach_instr(instr
, block
) {
9213 switch (instr
->type
) {
9214 case nir_instr_type_alu
:
9215 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9217 case nir_instr_type_load_const
:
9218 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9220 case nir_instr_type_intrinsic
:
9221 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9223 case nir_instr_type_tex
:
9224 visit_tex(ctx
, nir_instr_as_tex(instr
));
9226 case nir_instr_type_phi
:
9227 visit_phi(ctx
, nir_instr_as_phi(instr
));
9229 case nir_instr_type_ssa_undef
:
9230 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9232 case nir_instr_type_deref
:
9234 case nir_instr_type_jump
:
9235 visit_jump(ctx
, nir_instr_as_jump(instr
));
9238 isel_err(instr
, "Unknown NIR instr type");
9243 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9244 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9249 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9250 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9252 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9253 RegClass rc
= vals
[0].regClass();
9255 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9257 unsigned next_pred
= 1;
9259 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9260 Block
& block
= ctx
->program
->blocks
[idx
];
9261 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9262 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9266 if (block
.kind
& block_kind_continue
) {
9267 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9272 bool all_same
= true;
9273 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9274 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9278 val
= vals
[block
.linear_preds
[0] - first
];
9280 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9281 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9282 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9283 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9284 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9285 phi
->definitions
[0] = Definition(val
.getTemp());
9286 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9288 vals
[idx
- first
] = val
;
9291 return vals
[last
- first
];
9294 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9296 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9297 append_logical_end(ctx
->block
);
9298 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9299 Builder
bld(ctx
->program
, ctx
->block
);
9300 bld
.branch(aco_opcode::p_branch
);
9301 unsigned loop_preheader_idx
= ctx
->block
->index
;
9303 Block loop_exit
= Block();
9304 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9305 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9307 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9308 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9309 loop_header
->kind
|= block_kind_loop_header
;
9310 add_edge(loop_preheader_idx
, loop_header
);
9311 ctx
->block
= loop_header
;
9313 /* emit loop body */
9314 unsigned loop_header_idx
= loop_header
->index
;
9315 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9316 append_logical_start(ctx
->block
);
9317 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9319 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9320 if (!ctx
->cf_info
.has_branch
) {
9321 append_logical_end(ctx
->block
);
9322 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9323 /* Discards can result in code running with an empty exec mask.
9324 * This would result in divergent breaks not ever being taken. As a
9325 * workaround, break the loop when the loop mask is empty instead of
9326 * always continuing. */
9327 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9328 unsigned block_idx
= ctx
->block
->index
;
9330 /* create helper blocks to avoid critical edges */
9331 Block
*break_block
= ctx
->program
->create_and_insert_block();
9332 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9333 break_block
->kind
= block_kind_uniform
;
9334 bld
.reset(break_block
);
9335 bld
.branch(aco_opcode::p_branch
);
9336 add_linear_edge(block_idx
, break_block
);
9337 add_linear_edge(break_block
->index
, &loop_exit
);
9339 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9340 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9341 continue_block
->kind
= block_kind_uniform
;
9342 bld
.reset(continue_block
);
9343 bld
.branch(aco_opcode::p_branch
);
9344 add_linear_edge(block_idx
, continue_block
);
9345 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9347 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9348 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9349 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9351 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9352 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9353 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9355 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9358 bld
.reset(ctx
->block
);
9359 bld
.branch(aco_opcode::p_branch
);
9362 /* Fixup phis in loop header from unreachable blocks.
9363 * has_branch/has_divergent_branch also indicates if the loop ends with a
9364 * break/continue instruction, but we don't emit those if unreachable=true */
9366 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9367 bool linear
= ctx
->cf_info
.has_branch
;
9368 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9369 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9370 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9371 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9372 /* the last operand should be the one that needs to be removed */
9373 instr
->operands
.pop_back();
9374 } else if (!is_phi(instr
)) {
9380 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9381 * and the previous one shouldn't both happen at once because a break in the
9382 * merge block would get CSE'd */
9383 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9384 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9385 Operand vals
[num_vals
];
9386 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9387 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9388 if (ctx
->cf_info
.has_branch
)
9389 instr
->operands
.pop_back();
9391 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9392 } else if (!is_phi(instr
)) {
9398 ctx
->cf_info
.has_branch
= false;
9400 // TODO: if the loop has not a single exit, we must add one °°
9401 /* emit loop successor block */
9402 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9403 append_logical_start(ctx
->block
);
9406 // TODO: check if it is beneficial to not branch on continues
9407 /* trim linear phis in loop header */
9408 for (auto&& instr
: loop_entry
->instructions
) {
9409 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9410 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9411 new_phi
->definitions
[0] = instr
->definitions
[0];
9412 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9413 new_phi
->operands
[i
] = instr
->operands
[i
];
9414 /* check that the remaining operands are all the same */
9415 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9416 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9417 instr
.swap(new_phi
);
9418 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9427 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9431 append_logical_end(ctx
->block
);
9432 ctx
->block
->kind
|= block_kind_branch
;
9434 /* branch to linear then block */
9435 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9436 aco_ptr
<Pseudo_branch_instruction
> branch
;
9437 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9438 branch
->operands
[0] = Operand(cond
);
9439 ctx
->block
->instructions
.push_back(std::move(branch
));
9441 ic
->BB_if_idx
= ctx
->block
->index
;
9442 ic
->BB_invert
= Block();
9443 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9444 /* Invert blocks are intentionally not marked as top level because they
9445 * are not part of the logical cfg. */
9446 ic
->BB_invert
.kind
|= block_kind_invert
;
9447 ic
->BB_endif
= Block();
9448 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9449 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9451 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9452 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9453 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9454 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9455 ctx
->cf_info
.parent_if
.is_divergent
= true;
9457 /* divergent branches use cbranch_execz */
9458 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9459 ctx
->cf_info
.exec_potentially_empty_break
= false;
9460 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9462 /** emit logical then block */
9463 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9464 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9465 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9466 ctx
->block
= BB_then_logical
;
9467 append_logical_start(BB_then_logical
);
9470 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9472 Block
*BB_then_logical
= ctx
->block
;
9473 append_logical_end(BB_then_logical
);
9474 /* branch from logical then block to invert block */
9475 aco_ptr
<Pseudo_branch_instruction
> branch
;
9476 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9477 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9478 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9479 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9480 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9481 BB_then_logical
->kind
|= block_kind_uniform
;
9482 assert(!ctx
->cf_info
.has_branch
);
9483 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9484 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9486 /** emit linear then block */
9487 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9488 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9489 BB_then_linear
->kind
|= block_kind_uniform
;
9490 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9491 /* branch from linear then block to invert block */
9492 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9493 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9494 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9496 /** emit invert merge block */
9497 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9498 ic
->invert_idx
= ctx
->block
->index
;
9500 /* branch to linear else block (skip else) */
9501 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9502 branch
->operands
[0] = Operand(ic
->cond
);
9503 ctx
->block
->instructions
.push_back(std::move(branch
));
9505 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9506 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9507 ic
->exec_potentially_empty_break_depth_old
=
9508 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9509 /* divergent branches use cbranch_execz */
9510 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9511 ctx
->cf_info
.exec_potentially_empty_break
= false;
9512 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9514 /** emit logical else block */
9515 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9516 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9517 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9518 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9519 ctx
->block
= BB_else_logical
;
9520 append_logical_start(BB_else_logical
);
9523 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9525 Block
*BB_else_logical
= ctx
->block
;
9526 append_logical_end(BB_else_logical
);
9528 /* branch from logical else block to endif block */
9529 aco_ptr
<Pseudo_branch_instruction
> branch
;
9530 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9531 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9532 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9533 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9534 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9535 BB_else_logical
->kind
|= block_kind_uniform
;
9537 assert(!ctx
->cf_info
.has_branch
);
9538 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9541 /** emit linear else block */
9542 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9543 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9544 BB_else_linear
->kind
|= block_kind_uniform
;
9545 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9547 /* branch from linear else block to endif block */
9548 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9549 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9550 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9553 /** emit endif merge block */
9554 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9555 append_logical_start(ctx
->block
);
9558 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9559 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9560 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9561 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9562 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9563 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9564 !ctx
->cf_info
.parent_if
.is_divergent
) {
9565 ctx
->cf_info
.exec_potentially_empty_break
= false;
9566 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9568 /* uniform control flow never has an empty exec-mask */
9569 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9570 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9571 ctx
->cf_info
.exec_potentially_empty_break
= false;
9572 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9576 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9578 assert(cond
.regClass() == s1
);
9580 append_logical_end(ctx
->block
);
9581 ctx
->block
->kind
|= block_kind_uniform
;
9583 aco_ptr
<Pseudo_branch_instruction
> branch
;
9584 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9585 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9586 branch
->operands
[0] = Operand(cond
);
9587 branch
->operands
[0].setFixed(scc
);
9588 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9590 ic
->BB_if_idx
= ctx
->block
->index
;
9591 ic
->BB_endif
= Block();
9592 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9593 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9595 ctx
->cf_info
.has_branch
= false;
9596 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9598 /** emit then block */
9599 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9600 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9601 add_edge(ic
->BB_if_idx
, BB_then
);
9602 append_logical_start(BB_then
);
9603 ctx
->block
= BB_then
;
9606 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9608 Block
*BB_then
= ctx
->block
;
9610 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9611 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9613 if (!ic
->uniform_has_then_branch
) {
9614 append_logical_end(BB_then
);
9615 /* branch from then block to endif block */
9616 aco_ptr
<Pseudo_branch_instruction
> branch
;
9617 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9618 BB_then
->instructions
.emplace_back(std::move(branch
));
9619 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9620 if (!ic
->then_branch_divergent
)
9621 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9622 BB_then
->kind
|= block_kind_uniform
;
9625 ctx
->cf_info
.has_branch
= false;
9626 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9628 /** emit else block */
9629 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9630 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9631 add_edge(ic
->BB_if_idx
, BB_else
);
9632 append_logical_start(BB_else
);
9633 ctx
->block
= BB_else
;
9636 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9638 Block
*BB_else
= ctx
->block
;
9640 if (!ctx
->cf_info
.has_branch
) {
9641 append_logical_end(BB_else
);
9642 /* branch from then block to endif block */
9643 aco_ptr
<Pseudo_branch_instruction
> branch
;
9644 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9645 BB_else
->instructions
.emplace_back(std::move(branch
));
9646 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9647 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9648 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9649 BB_else
->kind
|= block_kind_uniform
;
9652 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9653 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9655 /** emit endif merge block */
9656 if (!ctx
->cf_info
.has_branch
) {
9657 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9658 append_logical_start(ctx
->block
);
9662 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9664 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9665 Builder
bld(ctx
->program
, ctx
->block
);
9666 aco_ptr
<Pseudo_branch_instruction
> branch
;
9669 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9671 * Uniform conditionals are represented in the following way*) :
9673 * The linear and logical CFG:
9676 * BB_THEN (logical) BB_ELSE (logical)
9680 * *) Exceptions may be due to break and continue statements within loops
9681 * If a break/continue happens within uniform control flow, it branches
9682 * to the loop exit/entry block. Otherwise, it branches to the next
9686 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9687 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9688 cond
= bool_to_scalar_condition(ctx
, cond
);
9690 begin_uniform_if_then(ctx
, &ic
, cond
);
9691 visit_cf_list(ctx
, &if_stmt
->then_list
);
9693 begin_uniform_if_else(ctx
, &ic
);
9694 visit_cf_list(ctx
, &if_stmt
->else_list
);
9696 end_uniform_if(ctx
, &ic
);
9697 } else { /* non-uniform condition */
9699 * To maintain a logical and linear CFG without critical edges,
9700 * non-uniform conditionals are represented in the following way*) :
9705 * BB_THEN (logical) BB_THEN (linear)
9707 * BB_INVERT (linear)
9709 * BB_ELSE (logical) BB_ELSE (linear)
9716 * BB_THEN (logical) BB_ELSE (logical)
9720 * *) Exceptions may be due to break and continue statements within loops
9723 begin_divergent_if_then(ctx
, &ic
, cond
);
9724 visit_cf_list(ctx
, &if_stmt
->then_list
);
9726 begin_divergent_if_else(ctx
, &ic
);
9727 visit_cf_list(ctx
, &if_stmt
->else_list
);
9729 end_divergent_if(ctx
, &ic
);
9732 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9735 static bool visit_cf_list(isel_context
*ctx
,
9736 struct exec_list
*list
)
9738 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9739 switch (node
->type
) {
9740 case nir_cf_node_block
:
9741 visit_block(ctx
, nir_cf_node_as_block(node
));
9743 case nir_cf_node_if
:
9744 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9747 case nir_cf_node_loop
:
9748 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9751 unreachable("unimplemented cf list type");
9757 static void create_null_export(isel_context
*ctx
)
9759 /* Some shader stages always need to have exports.
9760 * So when there is none, we need to add a null export.
9763 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9764 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9765 Builder
bld(ctx
->program
, ctx
->block
);
9766 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9767 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9770 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9772 assert(ctx
->stage
== vertex_vs
||
9773 ctx
->stage
== tess_eval_vs
||
9774 ctx
->stage
== gs_copy_vs
||
9775 ctx
->stage
== ngg_vertex_gs
||
9776 ctx
->stage
== ngg_tess_eval_gs
);
9778 int offset
= (ctx
->stage
& sw_tes
)
9779 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9780 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9781 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9782 if (!is_pos
&& !mask
)
9784 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9786 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9787 exp
->enabled_mask
= mask
;
9788 for (unsigned i
= 0; i
< 4; ++i
) {
9789 if (mask
& (1 << i
))
9790 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9792 exp
->operands
[i
] = Operand(v1
);
9794 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9795 * Setting valid_mask=1 prevents it and has no other effect.
9797 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9799 exp
->compressed
= false;
9801 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9803 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9804 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9809 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9811 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9812 exp
->enabled_mask
= 0;
9813 for (unsigned i
= 0; i
< 4; ++i
)
9814 exp
->operands
[i
] = Operand(v1
);
9815 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9816 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9817 exp
->enabled_mask
|= 0x1;
9819 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9820 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9821 exp
->enabled_mask
|= 0x4;
9823 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9824 if (ctx
->options
->chip_class
< GFX9
) {
9825 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9826 exp
->enabled_mask
|= 0x8;
9828 Builder
bld(ctx
->program
, ctx
->block
);
9830 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9831 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9832 if (exp
->operands
[2].isTemp())
9833 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9835 exp
->operands
[2] = Operand(out
);
9836 exp
->enabled_mask
|= 0x4;
9839 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9841 exp
->compressed
= false;
9842 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9843 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9846 static void create_export_phis(isel_context
*ctx
)
9848 /* Used when exports are needed, but the output temps are defined in a preceding block.
9849 * This function will set up phis in order to access the outputs in the next block.
9852 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9853 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9854 ctx
->block
->instructions
.pop_back();
9856 Builder
bld(ctx
->program
, ctx
->block
);
9858 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9859 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9860 for (unsigned i
= 0; i
< 4; ++i
) {
9861 if (!(mask
& (1 << i
)))
9864 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9865 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9866 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9870 bld
.insert(std::move(logical_start
));
9873 static void create_vs_exports(isel_context
*ctx
)
9875 assert(ctx
->stage
== vertex_vs
||
9876 ctx
->stage
== tess_eval_vs
||
9877 ctx
->stage
== gs_copy_vs
||
9878 ctx
->stage
== ngg_vertex_gs
||
9879 ctx
->stage
== ngg_tess_eval_gs
);
9881 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9882 ? &ctx
->program
->info
->tes
.outinfo
9883 : &ctx
->program
->info
->vs
.outinfo
;
9885 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9886 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9887 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9890 if (ctx
->options
->key
.has_multiview_view_index
) {
9891 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9892 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9895 /* the order these position exports are created is important */
9897 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9898 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9899 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9900 exported_pos
= true;
9902 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9903 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9904 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9905 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9907 if (ctx
->export_clip_dists
) {
9908 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9909 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9910 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9911 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9914 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9915 if (i
< VARYING_SLOT_VAR0
&&
9916 i
!= VARYING_SLOT_LAYER
&&
9917 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9918 i
!= VARYING_SLOT_VIEWPORT
)
9921 export_vs_varying(ctx
, i
, false, NULL
);
9925 create_null_export(ctx
);
9928 static bool export_fs_mrt_z(isel_context
*ctx
)
9930 Builder
bld(ctx
->program
, ctx
->block
);
9931 unsigned enabled_channels
= 0;
9935 for (unsigned i
= 0; i
< 4; ++i
) {
9936 values
[i
] = Operand(v1
);
9939 /* Both stencil and sample mask only need 16-bits. */
9940 if (!ctx
->program
->info
->ps
.writes_z
&&
9941 (ctx
->program
->info
->ps
.writes_stencil
||
9942 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9943 compr
= true; /* COMPR flag */
9945 if (ctx
->program
->info
->ps
.writes_stencil
) {
9946 /* Stencil should be in X[23:16]. */
9947 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9948 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9949 enabled_channels
|= 0x3;
9952 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9953 /* SampleMask should be in Y[15:0]. */
9954 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9955 enabled_channels
|= 0xc;
9958 if (ctx
->program
->info
->ps
.writes_z
) {
9959 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9960 enabled_channels
|= 0x1;
9963 if (ctx
->program
->info
->ps
.writes_stencil
) {
9964 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9965 enabled_channels
|= 0x2;
9968 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9969 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9970 enabled_channels
|= 0x4;
9974 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9975 * writemask component.
9977 if (ctx
->options
->chip_class
== GFX6
&&
9978 ctx
->options
->family
!= CHIP_OLAND
&&
9979 ctx
->options
->family
!= CHIP_HAINAN
) {
9980 enabled_channels
|= 0x1;
9983 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9984 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9989 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9991 Builder
bld(ctx
->program
, ctx
->block
);
9992 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9995 for (unsigned i
= 0; i
< 4; ++i
) {
9996 if (write_mask
& (1 << i
)) {
9997 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9999 values
[i
] = Operand(v1
);
10003 unsigned target
, col_format
;
10004 unsigned enabled_channels
= 0;
10005 aco_opcode compr_op
= (aco_opcode
)0;
10007 slot
-= FRAG_RESULT_DATA0
;
10008 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10009 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10011 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10012 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10013 bool is_16bit
= values
[0].regClass() == v2b
;
10015 switch (col_format
)
10017 case V_028714_SPI_SHADER_ZERO
:
10018 enabled_channels
= 0; /* writemask */
10019 target
= V_008DFC_SQ_EXP_NULL
;
10022 case V_028714_SPI_SHADER_32_R
:
10023 enabled_channels
= 1;
10026 case V_028714_SPI_SHADER_32_GR
:
10027 enabled_channels
= 0x3;
10030 case V_028714_SPI_SHADER_32_AR
:
10031 if (ctx
->options
->chip_class
>= GFX10
) {
10032 /* Special case: on GFX10, the outputs are different for 32_AR */
10033 enabled_channels
= 0x3;
10034 values
[1] = values
[3];
10035 values
[3] = Operand(v1
);
10037 enabled_channels
= 0x9;
10041 case V_028714_SPI_SHADER_FP16_ABGR
:
10042 enabled_channels
= 0x5;
10043 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10045 if (ctx
->options
->chip_class
>= GFX9
) {
10046 /* Pack the FP16 values together instead of converting them to
10047 * FP32 and back to FP16.
10048 * TODO: use p_create_vector and let the compiler optimizes.
10050 compr_op
= aco_opcode::v_pack_b32_f16
;
10052 for (unsigned i
= 0; i
< 4; i
++) {
10053 if ((write_mask
>> i
) & 1)
10054 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10060 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10061 enabled_channels
= 0x5;
10062 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10063 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10065 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10069 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10070 enabled_channels
= 0x5;
10071 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10072 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10074 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10078 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10079 enabled_channels
= 0x5;
10080 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10081 if (is_int8
|| is_int10
) {
10083 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10084 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10086 for (unsigned i
= 0; i
< 4; i
++) {
10087 if ((write_mask
>> i
) & 1) {
10088 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10089 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10093 } else if (is_16bit
) {
10094 for (unsigned i
= 0; i
< 4; i
++) {
10095 if ((write_mask
>> i
) & 1) {
10096 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10097 values
[i
] = Operand(tmp
);
10104 case V_028714_SPI_SHADER_SINT16_ABGR
:
10105 enabled_channels
= 0x5;
10106 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10107 if (is_int8
|| is_int10
) {
10109 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10110 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10111 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10112 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10114 for (unsigned i
= 0; i
< 4; i
++) {
10115 if ((write_mask
>> i
) & 1) {
10116 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10117 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10119 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10120 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10124 } else if (is_16bit
) {
10125 for (unsigned i
= 0; i
< 4; i
++) {
10126 if ((write_mask
>> i
) & 1) {
10127 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10128 values
[i
] = Operand(tmp
);
10134 case V_028714_SPI_SHADER_32_ABGR
:
10135 enabled_channels
= 0xF;
10142 if (target
== V_008DFC_SQ_EXP_NULL
)
10145 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10146 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10148 (col_format
== V_028714_SPI_SHADER_32_R
||
10149 col_format
== V_028714_SPI_SHADER_32_GR
||
10150 col_format
== V_028714_SPI_SHADER_32_AR
||
10151 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10152 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10153 for (int i
= 0; i
< 4; i
++) {
10154 if (!(write_mask
& (1 << i
)))
10157 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10158 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10159 bld
.copy(bld
.def(v1
), Operand(3u)));
10160 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10161 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10165 if ((bool) compr_op
) {
10166 for (int i
= 0; i
< 2; i
++) {
10167 /* check if at least one of the values to be compressed is enabled */
10168 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10170 enabled_channels
|= enabled
<< (i
*2);
10171 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10172 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10173 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10175 values
[i
] = Operand(v1
);
10178 values
[2] = Operand(v1
);
10179 values
[3] = Operand(v1
);
10181 for (int i
= 0; i
< 4; i
++)
10182 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10185 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10186 enabled_channels
, target
, (bool) compr_op
);
10190 static void create_fs_exports(isel_context
*ctx
)
10192 bool exported
= false;
10194 /* Export depth, stencil and sample mask. */
10195 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10196 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10197 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10198 exported
|= export_fs_mrt_z(ctx
);
10200 /* Export all color render targets. */
10201 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10202 if (ctx
->outputs
.mask
[i
])
10203 exported
|= export_fs_mrt_color(ctx
, i
);
10206 create_null_export(ctx
);
10209 static void create_workgroup_barrier(Builder
& bld
)
10211 bld
.barrier(aco_opcode::p_barrier
,
10212 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10216 static void write_tcs_tess_factors(isel_context
*ctx
)
10218 unsigned outer_comps
;
10219 unsigned inner_comps
;
10221 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10238 Builder
bld(ctx
->program
, ctx
->block
);
10240 create_workgroup_barrier(bld
);
10242 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10243 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10245 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10246 if_context ic_invocation_id_is_zero
;
10247 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10248 bld
.reset(ctx
->block
);
10250 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10252 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10253 unsigned stride
= inner_comps
+ outer_comps
;
10254 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10258 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10260 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10262 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10263 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10264 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10266 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10267 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10269 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10270 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10271 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10272 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10275 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10276 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10277 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10278 unsigned tf_const_offset
= 0;
10280 if (ctx
->program
->chip_class
<= GFX8
) {
10281 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10282 if_context ic_rel_patch_id_is_zero
;
10283 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10284 bld
.reset(ctx
->block
);
10286 /* Store the dynamic HS control word. */
10287 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10288 bld
.mubuf(aco_opcode::buffer_store_dword
,
10289 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10290 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10291 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10292 tf_const_offset
+= 4;
10294 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10295 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10296 bld
.reset(ctx
->block
);
10299 assert(stride
== 2 || stride
== 4 || stride
== 6);
10300 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10301 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10303 /* Store to offchip for TES to read - only if TES reads them */
10304 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10305 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10306 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10308 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10309 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10311 if (likely(inner_comps
)) {
10312 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10313 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10317 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10318 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10321 static void emit_stream_output(isel_context
*ctx
,
10322 Temp
const *so_buffers
,
10323 Temp
const *so_write_offset
,
10324 const struct radv_stream_output
*output
)
10326 unsigned num_comps
= util_bitcount(output
->component_mask
);
10327 unsigned writemask
= (1 << num_comps
) - 1;
10328 unsigned loc
= output
->location
;
10329 unsigned buf
= output
->buffer
;
10331 assert(num_comps
&& num_comps
<= 4);
10332 if (!num_comps
|| num_comps
> 4)
10335 unsigned start
= ffs(output
->component_mask
) - 1;
10338 bool all_undef
= true;
10339 assert(ctx
->stage
& hw_vs
);
10340 for (unsigned i
= 0; i
< num_comps
; i
++) {
10341 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10342 all_undef
= all_undef
&& !out
[i
].id();
10347 while (writemask
) {
10349 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10350 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10351 /* GFX6 doesn't support storing vec3, split it. */
10352 writemask
|= 1u << (start
+ 2);
10356 unsigned offset
= output
->offset
+ start
* 4;
10358 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10359 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10360 for (int i
= 0; i
< count
; ++i
)
10361 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10362 vec
->definitions
[0] = Definition(write_data
);
10363 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10368 opcode
= aco_opcode::buffer_store_dword
;
10371 opcode
= aco_opcode::buffer_store_dwordx2
;
10374 opcode
= aco_opcode::buffer_store_dwordx3
;
10377 opcode
= aco_opcode::buffer_store_dwordx4
;
10380 unreachable("Unsupported dword count.");
10383 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10384 store
->operands
[0] = Operand(so_buffers
[buf
]);
10385 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10386 store
->operands
[2] = Operand((uint32_t) 0);
10387 store
->operands
[3] = Operand(write_data
);
10388 if (offset
> 4095) {
10389 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10390 Builder
bld(ctx
->program
, ctx
->block
);
10391 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10393 store
->offset
= offset
;
10395 store
->offen
= true;
10397 store
->dlc
= false;
10399 ctx
->block
->instructions
.emplace_back(std::move(store
));
10403 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10405 Builder
bld(ctx
->program
, ctx
->block
);
10407 Temp so_buffers
[4];
10408 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10409 for (unsigned i
= 0; i
< 4; i
++) {
10410 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10414 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10415 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10418 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10419 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10421 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10423 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10426 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10428 bld
.reset(ctx
->block
);
10430 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10432 Temp so_write_offset
[4];
10434 for (unsigned i
= 0; i
< 4; i
++) {
10435 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10440 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10441 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10442 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10443 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10445 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10447 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10448 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10449 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10450 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10454 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10455 struct radv_stream_output
*output
=
10456 &ctx
->program
->info
->so
.outputs
[i
];
10457 if (stream
!= output
->stream
)
10460 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10463 begin_divergent_if_else(ctx
, &ic
);
10464 end_divergent_if(ctx
, &ic
);
10467 } /* end namespace */
10469 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10471 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10472 Builder
bld(ctx
->program
, ctx
->block
);
10473 constexpr unsigned hs_idx
= 1u;
10474 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10475 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10476 Operand((8u << 16) | (hs_idx
* 8u)));
10477 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10479 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10481 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10482 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10483 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10484 ls_has_nonzero_hs_threads
);
10485 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10486 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10487 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10488 ls_has_nonzero_hs_threads
);
10489 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10490 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10491 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10492 ls_has_nonzero_hs_threads
);
10494 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10495 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10496 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10499 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10501 /* Split all arguments except for the first (ring_offsets) and the last
10502 * (exec) so that the dead channels don't stay live throughout the program.
10504 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10505 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10506 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10507 startpgm
->definitions
[i
].regClass().size());
10512 void handle_bc_optimize(isel_context
*ctx
)
10514 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10515 Builder
bld(ctx
->program
, ctx
->block
);
10516 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10517 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10518 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10519 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10520 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10521 if (uses_center
&& uses_centroid
) {
10522 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10523 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10525 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10527 for (unsigned i
= 0; i
< 2; i
++) {
10528 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10529 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10530 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10531 persp_centroid
, persp_center
, sel
);
10533 ctx
->persp_centroid
= bld
.tmp(v2
);
10534 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10535 Operand(new_coord
[0]), Operand(new_coord
[1]));
10536 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10539 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10541 for (unsigned i
= 0; i
< 2; i
++) {
10542 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10543 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10544 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10545 linear_centroid
, linear_center
, sel
);
10547 ctx
->linear_centroid
= bld
.tmp(v2
);
10548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10549 Operand(new_coord
[0]), Operand(new_coord
[1]));
10550 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10555 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10557 Program
*program
= ctx
->program
;
10559 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10561 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10562 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10563 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10564 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10565 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10567 program
->next_fp_mode
.must_flush_denorms32
=
10568 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10569 program
->next_fp_mode
.must_flush_denorms16_64
=
10570 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10571 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10573 program
->next_fp_mode
.care_about_round32
=
10574 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10576 program
->next_fp_mode
.care_about_round16_64
=
10577 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10578 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10580 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10581 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10582 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10583 program
->next_fp_mode
.denorm16_64
= 0;
10585 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10587 /* preserving fp32 denorms is expensive, so only do it if asked */
10588 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10589 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10591 program
->next_fp_mode
.denorm32
= 0;
10593 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10594 program
->next_fp_mode
.round32
= fp_round_tz
;
10596 program
->next_fp_mode
.round32
= fp_round_ne
;
10598 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10599 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10601 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10603 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10606 void cleanup_cfg(Program
*program
)
10608 /* create linear_succs/logical_succs */
10609 for (Block
& BB
: program
->blocks
) {
10610 for (unsigned idx
: BB
.linear_preds
)
10611 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10612 for (unsigned idx
: BB
.logical_preds
)
10613 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10617 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10619 Builder
bld(ctx
->program
, ctx
->block
);
10621 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10622 Temp count
= i
== 0
10623 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10624 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10625 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10627 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10630 if (ctx
->program
->wave_size
== 64) {
10631 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10632 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10633 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10635 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10636 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10642 bool ngg_early_prim_export(isel_context
*ctx
)
10644 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10648 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10650 Builder
bld(ctx
->program
, ctx
->block
);
10652 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10653 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10655 /* Get the id of the current wave within the threadgroup (workgroup) */
10656 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10657 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10659 /* Execute the following code only on the first wave (wave id 0),
10660 * use the SCC def to tell if the wave id is zero or not.
10662 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10664 begin_uniform_if_then(ctx
, &ic
, cond
);
10665 begin_uniform_if_else(ctx
, &ic
);
10666 bld
.reset(ctx
->block
);
10668 /* Number of vertices output by VS/TES */
10669 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10670 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10671 /* Number of primitives output by VS/TES */
10672 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10673 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10675 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10676 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10677 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10679 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10680 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10682 end_uniform_if(ctx
, &ic
);
10684 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10685 bld
.reset(ctx
->block
);
10686 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10689 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10691 Builder
bld(ctx
->program
, ctx
->block
);
10693 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10694 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10697 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10700 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10701 assert(vtxindex
[i
].id());
10704 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10708 /* The initial edge flag is always false in tess eval shaders. */
10709 if (ctx
->stage
== ngg_vertex_gs
) {
10710 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10711 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10715 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10720 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10722 Builder
bld(ctx
->program
, ctx
->block
);
10723 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10725 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10726 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10727 false /* compressed */, true/* done */, false /* valid mask */);
10730 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10732 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10733 * These must always come before VS exports.
10735 * It is recommended to do these as early as possible. They can be at the beginning when
10736 * there is no SW GS and the shader doesn't write edge flags.
10740 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10741 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10743 Builder
bld(ctx
->program
, ctx
->block
);
10744 constexpr unsigned max_vertices_per_primitive
= 3;
10745 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10747 if (ctx
->stage
== ngg_vertex_gs
) {
10748 /* TODO: optimize for points & lines */
10749 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10750 if (ctx
->shader
->info
.tess
.point_mode
)
10751 num_vertices_per_primitive
= 1;
10752 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10753 num_vertices_per_primitive
= 2;
10755 unreachable("Unsupported NGG shader stage");
10758 Temp vtxindex
[max_vertices_per_primitive
];
10759 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10760 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10761 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10762 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10763 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10764 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10765 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10766 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10768 /* Export primitive data to the index buffer. */
10769 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10771 /* Export primitive ID. */
10772 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10773 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10774 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10775 Temp provoking_vtx_index
= vtxindex
[0];
10776 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10778 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10781 begin_divergent_if_else(ctx
, &ic
);
10782 end_divergent_if(ctx
, &ic
);
10785 void ngg_emit_nogs_output(isel_context
*ctx
)
10787 /* Emits NGG GS output, for stages that don't have SW GS. */
10790 Builder
bld(ctx
->program
, ctx
->block
);
10791 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10793 /* NGG streamout is currently disabled by default. */
10794 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10796 if (late_prim_export
) {
10797 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10798 create_export_phis(ctx
);
10799 /* Do what we need to do in the GS threads. */
10800 ngg_emit_nogs_gsthreads(ctx
);
10802 /* What comes next should be executed on ES threads. */
10803 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10804 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10805 bld
.reset(ctx
->block
);
10808 /* Export VS outputs */
10809 ctx
->block
->kind
|= block_kind_export_end
;
10810 create_vs_exports(ctx
);
10812 /* Export primitive ID */
10813 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10816 if (ctx
->stage
== ngg_vertex_gs
) {
10817 /* Wait for GS threads to store primitive ID in LDS. */
10818 create_workgroup_barrier(bld
);
10820 /* Calculate LDS address where the GS threads stored the primitive ID. */
10821 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10822 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10823 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10824 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10825 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10826 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10828 /* Load primitive ID from LDS. */
10829 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10830 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10831 /* TES: Just use the patch ID as the primitive ID. */
10832 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10834 unreachable("unsupported NGG shader stage.");
10837 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10838 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10840 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10843 if (late_prim_export
) {
10844 begin_divergent_if_else(ctx
, &ic
);
10845 end_divergent_if(ctx
, &ic
);
10846 bld
.reset(ctx
->block
);
10850 void select_program(Program
*program
,
10851 unsigned shader_count
,
10852 struct nir_shader
*const *shaders
,
10853 ac_shader_config
* config
,
10854 struct radv_shader_args
*args
)
10856 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10857 if_context ic_merged_wave_info
;
10858 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10860 for (unsigned i
= 0; i
< shader_count
; i
++) {
10861 nir_shader
*nir
= shaders
[i
];
10862 init_context(&ctx
, nir
);
10864 setup_fp_mode(&ctx
, nir
);
10867 /* needs to be after init_context() for FS */
10868 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10869 append_logical_start(ctx
.block
);
10871 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10872 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10874 split_arguments(&ctx
, startpgm
);
10878 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10880 if (ngg_early_prim_export(&ctx
))
10881 ngg_emit_nogs_gsthreads(&ctx
);
10884 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10885 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10886 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10887 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10888 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10889 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10890 ctx
.stage
== tess_eval_geometry_gs
));
10892 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10893 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10894 if (check_merged_wave_info
) {
10895 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10896 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10900 Builder
bld(ctx
.program
, ctx
.block
);
10902 create_workgroup_barrier(bld
);
10904 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10905 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10907 } else if (ctx
.stage
== geometry_gs
)
10908 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10910 if (ctx
.stage
== fragment_fs
)
10911 handle_bc_optimize(&ctx
);
10913 visit_cf_list(&ctx
, &func
->body
);
10915 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10916 emit_streamout(&ctx
, 0);
10918 if (ctx
.stage
& hw_vs
) {
10919 create_vs_exports(&ctx
);
10920 ctx
.block
->kind
|= block_kind_export_end
;
10921 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10922 ngg_emit_nogs_output(&ctx
);
10923 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10924 Builder
bld(ctx
.program
, ctx
.block
);
10925 bld
.barrier(aco_opcode::p_barrier
,
10926 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10927 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10928 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10929 write_tcs_tess_factors(&ctx
);
10932 if (ctx
.stage
== fragment_fs
) {
10933 create_fs_exports(&ctx
);
10934 ctx
.block
->kind
|= block_kind_export_end
;
10937 if (endif_merged_wave_info
) {
10938 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10939 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10942 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10943 ngg_emit_nogs_output(&ctx
);
10945 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10946 /* Outputs of the previous stage are inputs to the next stage */
10947 ctx
.inputs
= ctx
.outputs
;
10948 ctx
.outputs
= shader_io_state();
10952 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10954 append_logical_end(ctx
.block
);
10955 ctx
.block
->kind
|= block_kind_uniform
;
10956 Builder
bld(ctx
.program
, ctx
.block
);
10957 if (ctx
.program
->wb_smem_l1_on_end
)
10958 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10959 bld
.sopp(aco_opcode::s_endpgm
);
10961 cleanup_cfg(program
);
10964 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10965 ac_shader_config
* config
,
10966 struct radv_shader_args
*args
)
10968 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10970 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10972 add_startpgm(&ctx
);
10973 append_logical_start(ctx
.block
);
10975 Builder
bld(ctx
.program
, ctx
.block
);
10977 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10979 Operand
stream_id(0u);
10980 if (args
->shader_info
->so
.num_outputs
)
10981 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10982 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10984 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10986 std::stack
<Block
> endif_blocks
;
10988 for (unsigned stream
= 0; stream
< 4; stream
++) {
10989 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10992 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10993 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10996 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10998 unsigned BB_if_idx
= ctx
.block
->index
;
10999 Block BB_endif
= Block();
11000 if (!stream_id
.isConstant()) {
11002 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11003 append_logical_end(ctx
.block
);
11004 ctx
.block
->kind
|= block_kind_uniform
;
11005 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11007 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11009 ctx
.block
= ctx
.program
->create_and_insert_block();
11010 add_edge(BB_if_idx
, ctx
.block
);
11011 bld
.reset(ctx
.block
);
11012 append_logical_start(ctx
.block
);
11015 unsigned offset
= 0;
11016 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11017 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11020 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11021 unsigned length
= util_last_bit(output_usage_mask
);
11022 for (unsigned j
= 0; j
< length
; ++j
) {
11023 if (!(output_usage_mask
& (1 << j
)))
11026 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11027 Temp voffset
= vtx_offset
;
11028 if (const_offset
>= 4096u) {
11029 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11030 const_offset
%= 4096u;
11033 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11034 mubuf
->definitions
[0] = bld
.def(v1
);
11035 mubuf
->operands
[0] = Operand(gsvs_ring
);
11036 mubuf
->operands
[1] = Operand(voffset
);
11037 mubuf
->operands
[2] = Operand(0u);
11038 mubuf
->offen
= true;
11039 mubuf
->offset
= const_offset
;
11042 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11044 ctx
.outputs
.mask
[i
] |= 1 << j
;
11045 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11047 bld
.insert(std::move(mubuf
));
11053 if (args
->shader_info
->so
.num_outputs
) {
11054 emit_streamout(&ctx
, stream
);
11055 bld
.reset(ctx
.block
);
11059 create_vs_exports(&ctx
);
11060 ctx
.block
->kind
|= block_kind_export_end
;
11063 if (!stream_id
.isConstant()) {
11064 append_logical_end(ctx
.block
);
11066 /* branch from then block to endif block */
11067 bld
.branch(aco_opcode::p_branch
);
11068 add_edge(ctx
.block
->index
, &BB_endif
);
11069 ctx
.block
->kind
|= block_kind_uniform
;
11071 /* emit else block */
11072 ctx
.block
= ctx
.program
->create_and_insert_block();
11073 add_edge(BB_if_idx
, ctx
.block
);
11074 bld
.reset(ctx
.block
);
11075 append_logical_start(ctx
.block
);
11077 endif_blocks
.push(std::move(BB_endif
));
11081 while (!endif_blocks
.empty()) {
11082 Block BB_endif
= std::move(endif_blocks
.top());
11083 endif_blocks
.pop();
11085 Block
*BB_else
= ctx
.block
;
11087 append_logical_end(BB_else
);
11088 /* branch from else block to endif block */
11089 bld
.branch(aco_opcode::p_branch
);
11090 add_edge(BB_else
->index
, &BB_endif
);
11091 BB_else
->kind
|= block_kind_uniform
;
11093 /** emit endif merge block */
11094 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11095 bld
.reset(ctx
.block
);
11096 append_logical_start(ctx
.block
);
11099 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11101 append_logical_end(ctx
.block
);
11102 ctx
.block
->kind
|= block_kind_uniform
;
11103 bld
.sopp(aco_opcode::s_endpgm
);
11105 cleanup_cfg(program
);
11108 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11109 ac_shader_config
* config
,
11110 struct radv_shader_args
*args
)
11112 assert(args
->options
->chip_class
== GFX8
);
11114 init_program(program
, compute_cs
, args
->shader_info
,
11115 args
->options
->chip_class
, args
->options
->family
, config
);
11117 isel_context ctx
= {};
11118 ctx
.program
= program
;
11120 ctx
.options
= args
->options
;
11121 ctx
.stage
= program
->stage
;
11123 ctx
.block
= ctx
.program
->create_and_insert_block();
11124 ctx
.block
->loop_nest_depth
= 0;
11125 ctx
.block
->kind
= block_kind_top_level
;
11127 program
->workgroup_size
= 1; /* XXX */
11129 add_startpgm(&ctx
);
11130 append_logical_start(ctx
.block
);
11132 Builder
bld(ctx
.program
, ctx
.block
);
11134 /* Load the buffer descriptor from TMA. */
11135 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11136 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11138 /* Store TTMP0-TTMP1. */
11139 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11140 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11142 uint32_t hw_regs_idx
[] = {
11143 2, /* HW_REG_STATUS */
11144 3, /* HW_REG_TRAP_STS */
11145 4, /* HW_REG_HW_ID */
11146 7, /* HW_REG_IB_STS */
11149 /* Store some hardware registers. */
11150 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11151 /* "((size - 1) << 11) | register" */
11152 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11153 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11155 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11156 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11159 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11161 append_logical_end(ctx
.block
);
11162 ctx
.block
->kind
|= block_kind_uniform
;
11163 bld
.sopp(aco_opcode::s_endpgm
);
11165 cleanup_cfg(program
);