2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
308 if (num_components
> vec_src
.size()) {
309 if (vec_src
.type() == RegType::sgpr
) {
310 /* should still help get_alu_src() */
311 emit_split_vector(ctx
, vec_src
, vec_src
.size());
314 /* sub-dword split */
315 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
317 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
319 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
320 split
->operands
[0] = Operand(vec_src
);
321 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
322 for (unsigned i
= 0; i
< num_components
; i
++) {
323 elems
[i
] = {ctx
->program
->allocateId(), rc
};
324 split
->definitions
[i
] = Definition(elems
[i
]);
326 ctx
->block
->instructions
.emplace_back(std::move(split
));
327 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
330 /* This vector expansion uses a mask to determine which elements in the new vector
331 * come from the original vector. The other elements are undefined. */
332 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
334 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
339 Builder
bld(ctx
->program
, ctx
->block
);
340 if (num_components
== 1) {
341 if (dst
.type() == RegType::sgpr
)
342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
344 bld
.copy(Definition(dst
), vec_src
);
348 unsigned component_size
= dst
.size() / num_components
;
349 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
351 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
352 vec
->definitions
[0] = Definition(dst
);
354 for (unsigned i
= 0; i
< num_components
; i
++) {
355 if (mask
& (1 << i
)) {
356 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
357 if (dst
.type() == RegType::sgpr
)
358 src
= bld
.as_uniform(src
);
359 vec
->operands
[i
] = Operand(src
);
361 vec
->operands
[i
] = Operand(0u);
363 elems
[i
] = vec
->operands
[i
].getTemp();
365 ctx
->block
->instructions
.emplace_back(std::move(vec
));
366 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
369 /* adjust misaligned small bit size loads */
370 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
372 Builder
bld(ctx
->program
, ctx
->block
);
374 Temp select
= Temp();
375 if (offset
.isConstant()) {
376 assert(offset
.constantValue() && offset
.constantValue() < 4);
377 shift
= Operand(offset
.constantValue() * 8);
379 /* bit_offset = 8 * (offset & 0x3) */
380 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
381 select
= bld
.tmp(s1
);
382 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
385 if (vec
.size() == 1) {
386 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
387 } else if (vec
.size() == 2) {
388 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
389 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
391 emit_split_vector(ctx
, dst
, 2);
393 emit_extract_vector(ctx
, tmp
, 0, dst
);
394 } else if (vec
.size() == 4) {
395 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
396 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
397 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
398 if (select
!= Temp())
399 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
400 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
401 Temp mid
= bld
.tmp(s1
);
402 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
403 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
404 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
406 emit_split_vector(ctx
, dst
, 2);
410 /* this function trims subdword vectors:
411 * if dst is vgpr - split the src and create a shrunk version according to the mask.
412 * if dst is sgpr - split the src, but move the original to sgpr. */
413 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
415 assert(vec_src
.type() == RegType::vgpr
);
416 emit_split_vector(ctx
, vec_src
, num_components
);
418 Builder
bld(ctx
->program
, ctx
->block
);
419 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
420 unsigned component_size
= vec_src
.bytes() / num_components
;
421 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
424 for (unsigned i
= 0; i
< num_components
; i
++) {
426 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
429 if (dst
.type() == RegType::vgpr
) {
430 assert(dst
.bytes() == k
* component_size
);
431 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
432 for (unsigned i
= 0; i
< k
; i
++)
433 vec
->operands
[i
] = Operand(elems
[i
]);
434 vec
->definitions
[0] = Definition(dst
);
435 bld
.insert(std::move(vec
));
437 // TODO: alignbyte if mask doesn't start with 1?
439 assert(dst
.size() == vec_src
.size());
440 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
442 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
445 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
447 Builder
bld(ctx
->program
, ctx
->block
);
449 dst
= bld
.tmp(bld
.lm
);
451 assert(val
.regClass() == s1
);
452 assert(dst
.regClass() == bld
.lm
);
454 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
457 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
459 Builder
bld(ctx
->program
, ctx
->block
);
463 assert(val
.regClass() == bld
.lm
);
464 assert(dst
.regClass() == s1
);
466 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
467 Temp tmp
= bld
.tmp(s1
);
468 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
469 return emit_wqm(ctx
, tmp
, dst
);
472 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
474 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
475 return get_ssa_temp(ctx
, src
.src
.ssa
);
477 if (src
.src
.ssa
->num_components
== size
) {
478 bool identity_swizzle
= true;
479 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
480 if (src
.swizzle
[i
] != i
)
481 identity_swizzle
= false;
483 if (identity_swizzle
)
484 return get_ssa_temp(ctx
, src
.src
.ssa
);
487 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
488 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
489 assert(elem_size
> 0);
490 assert(vec
.bytes() % elem_size
== 0);
492 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
493 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
495 unsigned swizzle
= src
.swizzle
[0];
496 if (vec
.size() > 1) {
497 assert(src
.src
.ssa
->bit_size
== 16);
498 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
499 swizzle
= swizzle
& 1;
504 Temp dst
{ctx
->program
->allocateId(), s1
};
505 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
506 bfe
->operands
[0] = Operand(vec
);
507 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
508 bfe
->definitions
[0] = Definition(dst
);
509 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
510 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
514 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
516 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
519 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
520 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
521 for (unsigned i
= 0; i
< size
; ++i
) {
522 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
523 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
525 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
526 vec_instr
->definitions
[0] = Definition(dst
);
527 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
528 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
533 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
537 Builder
bld(ctx
->program
, ctx
->block
);
538 if (ptr
.type() == RegType::vgpr
)
539 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
540 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
541 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
544 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
546 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
547 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
548 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
549 sop2
->definitions
[0] = Definition(dst
);
551 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
552 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
555 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
556 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
558 Builder
bld(ctx
->program
, ctx
->block
);
559 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
560 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
561 if (src1
.type() == RegType::sgpr
) {
562 if (commutative
&& src0
.type() == RegType::vgpr
) {
567 src1
= as_vgpr(ctx
, src1
);
571 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
572 assert(dst
.size() == 1);
573 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
574 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
576 bld
.vop2(op
, Definition(dst
), src0
, src1
);
580 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
581 bool flush_denorms
= false)
583 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
584 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
585 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
587 /* ensure that the instruction has at most 1 sgpr operand
588 * The optimizer will inline constants for us */
589 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
590 src0
= as_vgpr(ctx
, src0
);
591 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
592 src1
= as_vgpr(ctx
, src1
);
593 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
594 src2
= as_vgpr(ctx
, src2
);
596 Builder
bld(ctx
->program
, ctx
->block
);
597 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
598 assert(dst
.size() == 1);
599 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
600 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
602 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
608 Builder
bld(ctx
->program
, ctx
->block
);
609 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
612 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
615 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
616 assert(src0
.size() == src1
.size());
618 aco_ptr
<Instruction
> vopc
;
619 if (src1
.type() == RegType::sgpr
) {
620 if (src0
.type() == RegType::vgpr
) {
621 /* to swap the operands, we might also have to change the opcode */
623 case aco_opcode::v_cmp_lt_f16
:
624 op
= aco_opcode::v_cmp_gt_f16
;
626 case aco_opcode::v_cmp_ge_f16
:
627 op
= aco_opcode::v_cmp_le_f16
;
629 case aco_opcode::v_cmp_lt_i16
:
630 op
= aco_opcode::v_cmp_gt_i16
;
632 case aco_opcode::v_cmp_ge_i16
:
633 op
= aco_opcode::v_cmp_le_i16
;
635 case aco_opcode::v_cmp_lt_u16
:
636 op
= aco_opcode::v_cmp_gt_u16
;
638 case aco_opcode::v_cmp_ge_u16
:
639 op
= aco_opcode::v_cmp_le_u16
;
641 case aco_opcode::v_cmp_lt_f32
:
642 op
= aco_opcode::v_cmp_gt_f32
;
644 case aco_opcode::v_cmp_ge_f32
:
645 op
= aco_opcode::v_cmp_le_f32
;
647 case aco_opcode::v_cmp_lt_i32
:
648 op
= aco_opcode::v_cmp_gt_i32
;
650 case aco_opcode::v_cmp_ge_i32
:
651 op
= aco_opcode::v_cmp_le_i32
;
653 case aco_opcode::v_cmp_lt_u32
:
654 op
= aco_opcode::v_cmp_gt_u32
;
656 case aco_opcode::v_cmp_ge_u32
:
657 op
= aco_opcode::v_cmp_le_u32
;
659 case aco_opcode::v_cmp_lt_f64
:
660 op
= aco_opcode::v_cmp_gt_f64
;
662 case aco_opcode::v_cmp_ge_f64
:
663 op
= aco_opcode::v_cmp_le_f64
;
665 case aco_opcode::v_cmp_lt_i64
:
666 op
= aco_opcode::v_cmp_gt_i64
;
668 case aco_opcode::v_cmp_ge_i64
:
669 op
= aco_opcode::v_cmp_le_i64
;
671 case aco_opcode::v_cmp_lt_u64
:
672 op
= aco_opcode::v_cmp_gt_u64
;
674 case aco_opcode::v_cmp_ge_u64
:
675 op
= aco_opcode::v_cmp_le_u64
;
677 default: /* eq and ne are commutative */
684 src1
= as_vgpr(ctx
, src1
);
688 Builder
bld(ctx
->program
, ctx
->block
);
689 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
692 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
694 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
695 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
696 Builder
bld(ctx
->program
, ctx
->block
);
698 assert(dst
.regClass() == bld
.lm
);
699 assert(src0
.type() == RegType::sgpr
);
700 assert(src1
.type() == RegType::sgpr
);
701 assert(src0
.regClass() == src1
.regClass());
703 /* Emit the SALU comparison instruction */
704 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
705 /* Turn the result into a per-lane bool */
706 bool_to_vector_condition(ctx
, cmp
, dst
);
709 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
710 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
712 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
713 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
714 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 nir_dest_is_divergent(instr
->dest
.dest
) ||
716 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
717 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
718 aco_opcode op
= use_valu
? v_op
: s_op
;
719 assert(op
!= aco_opcode::num_opcodes
);
720 assert(dst
.regClass() == ctx
->program
->lane_mask
);
723 emit_vopc_instruction(ctx
, instr
, op
, dst
);
725 emit_sopc_instruction(ctx
, instr
, op
, dst
);
728 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
730 Builder
bld(ctx
->program
, ctx
->block
);
731 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
734 assert(dst
.regClass() == bld
.lm
);
735 assert(src0
.regClass() == bld
.lm
);
736 assert(src1
.regClass() == bld
.lm
);
738 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
741 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
743 Builder
bld(ctx
->program
, ctx
->block
);
744 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
745 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
746 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
748 assert(cond
.regClass() == bld
.lm
);
750 if (dst
.type() == RegType::vgpr
) {
751 aco_ptr
<Instruction
> bcsel
;
752 if (dst
.size() == 1) {
753 then
= as_vgpr(ctx
, then
);
754 els
= as_vgpr(ctx
, els
);
756 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
757 } else if (dst
.size() == 2) {
758 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
759 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
760 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
761 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
763 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
764 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
766 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
768 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
769 nir_print_instr(&instr
->instr
, stderr
);
770 fprintf(stderr
, "\n");
775 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
776 assert(dst
.regClass() == bld
.lm
);
777 assert(then
.regClass() == bld
.lm
);
778 assert(els
.regClass() == bld
.lm
);
781 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
782 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
783 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
784 assert(dst
.size() == then
.size());
785 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
786 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
788 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
789 nir_print_instr(&instr
->instr
, stderr
);
790 fprintf(stderr
, "\n");
795 /* divergent boolean bcsel
796 * this implements bcsel on bools: dst = s0 ? s1 : s2
797 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
798 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
800 if (cond
.id() != then
.id())
801 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
803 if (cond
.id() == els
.id())
804 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
806 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
807 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
810 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
811 aco_opcode op
, uint32_t undo
)
813 /* multiply by 16777216 to handle denormals */
814 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
815 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
816 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
817 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
818 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
820 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
822 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
825 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
827 if (ctx
->block
->fp_mode
.denorm32
== 0) {
828 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
832 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
835 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
837 if (ctx
->block
->fp_mode
.denorm32
== 0) {
838 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
842 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
845 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
847 if (ctx
->block
->fp_mode
.denorm32
== 0) {
848 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
852 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
855 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
857 if (ctx
->block
->fp_mode
.denorm32
== 0) {
858 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
862 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
865 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
867 if (ctx
->options
->chip_class
>= GFX7
)
868 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
870 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
871 /* TODO: create more efficient code! */
872 if (val
.type() == RegType::sgpr
)
873 val
= as_vgpr(ctx
, val
);
875 /* Split the input value. */
876 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
877 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
879 /* Extract the exponent and compute the unbiased value. */
880 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
881 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
883 /* Extract the fractional part. */
884 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
885 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
887 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
888 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
890 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
891 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
892 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
893 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
894 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
896 /* Get the sign bit. */
897 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
899 /* Decide the operation to apply depending on the unbiased exponent. */
900 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
901 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
902 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
903 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
904 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
905 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
907 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
910 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
912 if (ctx
->options
->chip_class
>= GFX7
)
913 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
915 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
916 Temp src0
= as_vgpr(ctx
, val
);
918 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
919 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
921 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
922 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
923 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
925 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
926 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
927 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
928 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
930 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
931 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
933 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
935 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
936 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
938 return add
->definitions
[0].getTemp();
941 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
943 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
944 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
946 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
949 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
950 return bld
.copy(Definition(dst
), src
);
951 else if (dst
.bytes() < src
.bytes())
952 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
956 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
959 } else if (src
.regClass() == s1
) {
961 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
963 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
965 assert(src_bits
!= 8 || src
.regClass() == v1b
);
966 assert(src_bits
!= 16 || src
.regClass() == v2b
);
967 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
968 sdwa
->operands
[0] = Operand(src
);
969 sdwa
->definitions
[0] = Definition(tmp
);
971 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
973 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
974 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
975 bld
.insert(std::move(sdwa
));
978 if (dst_bits
== 64) {
979 if (is_signed
&& dst
.regClass() == s2
) {
980 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
981 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
982 } else if (is_signed
&& dst
.regClass() == v2
) {
983 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
984 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
993 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
995 if (!instr
->dest
.dest
.is_ssa
) {
996 fprintf(stderr
, "nir alu dst not in ssa: ");
997 nir_print_instr(&instr
->instr
, stderr
);
998 fprintf(stderr
, "\n");
1001 Builder
bld(ctx
->program
, ctx
->block
);
1002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1007 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1008 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1009 for (unsigned i
= 0; i
< num
; ++i
)
1010 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1012 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1013 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1014 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1015 for (unsigned i
= 0; i
< num
; ++i
) {
1016 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1017 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1021 vec
->definitions
[0] = Definition(dst
);
1022 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1023 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1025 // TODO: that is a bit suboptimal..
1026 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1027 for (unsigned i
= 0; i
< num
- 1; ++i
)
1028 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1029 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1030 for (unsigned i
= 0; i
< num
; ++i
) {
1031 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1032 if (bit
% 32 == 0) {
1033 elems
[bit
/ 32] = elems
[i
];
1035 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1036 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1037 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1040 if (dst
.size() == 1)
1041 bld
.copy(Definition(dst
), elems
[0]);
1043 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1048 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1049 aco_ptr
<Instruction
> mov
;
1050 if (dst
.type() == RegType::sgpr
) {
1051 if (src
.type() == RegType::vgpr
)
1052 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1053 else if (src
.regClass() == s1
)
1054 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1055 else if (src
.regClass() == s2
)
1056 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1058 unreachable("wrong src register class for nir_op_imov");
1060 if (dst
.regClass() == v1
)
1061 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1062 else if (dst
.regClass() == v1b
||
1063 dst
.regClass() == v2b
||
1064 dst
.regClass() == v2
)
1065 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1067 unreachable("wrong src register class for nir_op_imov");
1072 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1073 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1074 assert(src
.regClass() == bld
.lm
);
1075 assert(dst
.regClass() == bld
.lm
);
1076 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1077 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1078 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1079 } else if (dst
.regClass() == v1
) {
1080 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1081 } else if (dst
.type() == RegType::sgpr
) {
1082 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1083 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1085 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1086 nir_print_instr(&instr
->instr
, stderr
);
1087 fprintf(stderr
, "\n");
1092 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1093 if (dst
.regClass() == v1
) {
1094 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1095 } else if (dst
.regClass() == s1
) {
1096 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1097 } else if (dst
.size() == 2) {
1098 Temp src0
= bld
.tmp(dst
.type(), 1);
1099 Temp src1
= bld
.tmp(dst
.type(), 1);
1100 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1102 if (dst
.regClass() == s2
) {
1103 Temp carry
= bld
.tmp(s1
);
1104 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1105 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1106 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1108 Temp lower
= bld
.tmp(v1
);
1109 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1110 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1111 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1115 nir_print_instr(&instr
->instr
, stderr
);
1116 fprintf(stderr
, "\n");
1121 if (dst
.regClass() == s1
) {
1122 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1123 } else if (dst
.regClass() == v1
) {
1124 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1125 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1127 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1128 nir_print_instr(&instr
->instr
, stderr
);
1129 fprintf(stderr
, "\n");
1133 case nir_op_isign
: {
1134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1135 if (dst
.regClass() == s1
) {
1136 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1137 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1138 } else if (dst
.regClass() == s2
) {
1139 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1141 if (ctx
->program
->chip_class
>= GFX8
)
1142 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1144 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1145 /* SCC gets zero-extended to 64 bit */
1146 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1147 } else if (dst
.regClass() == v1
) {
1148 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1149 } else if (dst
.regClass() == v2
) {
1150 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1151 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1152 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1153 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1154 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1155 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1157 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1158 nir_print_instr(&instr
->instr
, stderr
);
1159 fprintf(stderr
, "\n");
1164 if (dst
.regClass() == v1
) {
1165 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1166 } else if (dst
.regClass() == s1
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (dst
.regClass() == v1
) {
1177 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1178 } else if (dst
.regClass() == s1
) {
1179 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1181 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1182 nir_print_instr(&instr
->instr
, stderr
);
1183 fprintf(stderr
, "\n");
1188 if (dst
.regClass() == v1
) {
1189 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1190 } else if (dst
.regClass() == s1
) {
1191 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (dst
.regClass() == v1
) {
1201 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1213 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1214 } else if (dst
.regClass() == v1
) {
1215 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1216 } else if (dst
.regClass() == s1
) {
1217 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1218 } else if (dst
.regClass() == s2
) {
1219 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1221 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1222 nir_print_instr(&instr
->instr
, stderr
);
1223 fprintf(stderr
, "\n");
1228 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1229 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1230 } else if (dst
.regClass() == v1
) {
1231 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1232 } else if (dst
.regClass() == s1
) {
1233 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1234 } else if (dst
.regClass() == s2
) {
1235 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1237 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1238 nir_print_instr(&instr
->instr
, stderr
);
1239 fprintf(stderr
, "\n");
1244 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1245 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1246 } else if (dst
.regClass() == v1
) {
1247 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1248 } else if (dst
.regClass() == s1
) {
1249 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1250 } else if (dst
.regClass() == s2
) {
1251 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1253 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1254 nir_print_instr(&instr
->instr
, stderr
);
1255 fprintf(stderr
, "\n");
1260 if (dst
.regClass() == v1
) {
1261 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1262 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1263 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1264 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1265 } else if (dst
.regClass() == v2
) {
1266 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1267 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1268 } else if (dst
.regClass() == s2
) {
1269 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1270 } else if (dst
.regClass() == s1
) {
1271 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1273 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1274 nir_print_instr(&instr
->instr
, stderr
);
1275 fprintf(stderr
, "\n");
1280 if (dst
.regClass() == v1
) {
1281 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1282 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1283 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1284 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1285 } else if (dst
.regClass() == v2
) {
1286 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1287 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1288 } else if (dst
.regClass() == s1
) {
1289 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1290 } else if (dst
.regClass() == s2
) {
1291 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1293 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1294 nir_print_instr(&instr
->instr
, stderr
);
1295 fprintf(stderr
, "\n");
1300 if (dst
.regClass() == v1
) {
1301 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1302 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1303 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1304 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1305 } else if (dst
.regClass() == v2
) {
1306 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1307 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1308 } else if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1310 } else if (dst
.regClass() == s2
) {
1311 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1314 nir_print_instr(&instr
->instr
, stderr
);
1315 fprintf(stderr
, "\n");
1319 case nir_op_find_lsb
: {
1320 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1321 if (src
.regClass() == s1
) {
1322 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1323 } else if (src
.regClass() == v1
) {
1324 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1325 } else if (src
.regClass() == s2
) {
1326 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1328 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1329 nir_print_instr(&instr
->instr
, stderr
);
1330 fprintf(stderr
, "\n");
1334 case nir_op_ufind_msb
:
1335 case nir_op_ifind_msb
: {
1336 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1337 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1338 aco_opcode op
= src
.regClass() == s2
?
1339 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1340 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1341 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1343 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1344 Operand(src
.size() * 32u - 1u), msb_rev
);
1345 Temp msb
= sub
.def(0).getTemp();
1346 Temp carry
= sub
.def(1).getTemp();
1348 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1349 } else if (src
.regClass() == v1
) {
1350 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1351 Temp msb_rev
= bld
.tmp(v1
);
1352 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1353 Temp msb
= bld
.tmp(v1
);
1354 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1355 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1357 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1358 nir_print_instr(&instr
->instr
, stderr
);
1359 fprintf(stderr
, "\n");
1363 case nir_op_bitfield_reverse
: {
1364 if (dst
.regClass() == s1
) {
1365 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1366 } else if (dst
.regClass() == v1
) {
1367 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1369 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1370 nir_print_instr(&instr
->instr
, stderr
);
1371 fprintf(stderr
, "\n");
1376 if (dst
.regClass() == s1
) {
1377 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1381 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1382 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1383 if (dst
.regClass() == v1
) {
1384 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1388 assert(src0
.size() == 2 && src1
.size() == 2);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1396 if (dst
.regClass() == s2
) {
1397 Temp carry
= bld
.tmp(s1
);
1398 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1399 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1400 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1401 } else if (dst
.regClass() == v2
) {
1402 Temp dst0
= bld
.tmp(v1
);
1403 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1404 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1405 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1407 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1408 nir_print_instr(&instr
->instr
, stderr
);
1409 fprintf(stderr
, "\n");
1413 case nir_op_uadd_sat
: {
1414 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1415 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1416 if (dst
.regClass() == s1
) {
1417 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1418 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1420 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1421 } else if (dst
.regClass() == v1
) {
1422 if (ctx
->options
->chip_class
>= GFX9
) {
1423 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1424 add
->operands
[0] = Operand(src0
);
1425 add
->operands
[1] = Operand(src1
);
1426 add
->definitions
[0] = Definition(dst
);
1428 ctx
->block
->instructions
.emplace_back(std::move(add
));
1430 if (src1
.regClass() != v1
)
1431 std::swap(src0
, src1
);
1432 assert(src1
.regClass() == v1
);
1433 Temp tmp
= bld
.tmp(v1
);
1434 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1435 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1438 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1439 nir_print_instr(&instr
->instr
, stderr
);
1440 fprintf(stderr
, "\n");
1444 case nir_op_uadd_carry
: {
1445 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1446 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1447 if (dst
.regClass() == s1
) {
1448 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1451 if (dst
.regClass() == v1
) {
1452 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1453 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1457 Temp src00
= bld
.tmp(src0
.type(), 1);
1458 Temp src01
= bld
.tmp(dst
.type(), 1);
1459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1460 Temp src10
= bld
.tmp(src1
.type(), 1);
1461 Temp src11
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1463 if (dst
.regClass() == s2
) {
1464 Temp carry
= bld
.tmp(s1
);
1465 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1466 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1467 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1468 } else if (dst
.regClass() == v2
) {
1469 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1470 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1471 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1474 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1475 nir_print_instr(&instr
->instr
, stderr
);
1476 fprintf(stderr
, "\n");
1481 if (dst
.regClass() == s1
) {
1482 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1486 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1487 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1488 if (dst
.regClass() == v1
) {
1489 bld
.vsub32(Definition(dst
), src0
, src1
);
1493 Temp src00
= bld
.tmp(src0
.type(), 1);
1494 Temp src01
= bld
.tmp(dst
.type(), 1);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1496 Temp src10
= bld
.tmp(src1
.type(), 1);
1497 Temp src11
= bld
.tmp(dst
.type(), 1);
1498 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1499 if (dst
.regClass() == s2
) {
1500 Temp carry
= bld
.tmp(s1
);
1501 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1502 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1503 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1504 } else if (dst
.regClass() == v2
) {
1505 Temp lower
= bld
.tmp(v1
);
1506 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1507 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1508 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1510 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1511 nir_print_instr(&instr
->instr
, stderr
);
1512 fprintf(stderr
, "\n");
1516 case nir_op_usub_borrow
: {
1517 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1518 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1519 if (dst
.regClass() == s1
) {
1520 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1522 } else if (dst
.regClass() == v1
) {
1523 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1524 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1528 Temp src00
= bld
.tmp(src0
.type(), 1);
1529 Temp src01
= bld
.tmp(dst
.type(), 1);
1530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1531 Temp src10
= bld
.tmp(src1
.type(), 1);
1532 Temp src11
= bld
.tmp(dst
.type(), 1);
1533 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1534 if (dst
.regClass() == s2
) {
1535 Temp borrow
= bld
.tmp(s1
);
1536 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1537 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1538 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1539 } else if (dst
.regClass() == v2
) {
1540 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1541 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1542 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1543 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1545 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1546 nir_print_instr(&instr
->instr
, stderr
);
1547 fprintf(stderr
, "\n");
1552 if (dst
.regClass() == v1
) {
1553 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1554 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1555 } else if (dst
.regClass() == s1
) {
1556 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1558 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1559 nir_print_instr(&instr
->instr
, stderr
);
1560 fprintf(stderr
, "\n");
1564 case nir_op_umul_high
: {
1565 if (dst
.regClass() == v1
) {
1566 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1567 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1568 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1569 } else if (dst
.regClass() == s1
) {
1570 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1571 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1572 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1574 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1575 nir_print_instr(&instr
->instr
, stderr
);
1576 fprintf(stderr
, "\n");
1580 case nir_op_imul_high
: {
1581 if (dst
.regClass() == v1
) {
1582 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1583 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1584 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1585 } else if (dst
.regClass() == s1
) {
1586 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1587 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1588 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1598 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1599 if (dst
.regClass() == v2b
) {
1600 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1601 } else if (dst
.regClass() == v1
) {
1602 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1603 } else if (dst
.regClass() == v2
) {
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1606 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1607 nir_print_instr(&instr
->instr
, stderr
);
1608 fprintf(stderr
, "\n");
1613 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1614 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1615 if (dst
.regClass() == v2b
) {
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1617 } else if (dst
.regClass() == v1
) {
1618 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1619 } else if (dst
.regClass() == v2
) {
1620 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1623 nir_print_instr(&instr
->instr
, stderr
);
1624 fprintf(stderr
, "\n");
1629 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1630 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1631 if (dst
.regClass() == v2b
) {
1632 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1633 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1635 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1636 } else if (dst
.regClass() == v1
) {
1637 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1638 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1640 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1641 } else if (dst
.regClass() == v2
) {
1642 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1643 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1644 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1647 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1648 nir_print_instr(&instr
->instr
, stderr
);
1649 fprintf(stderr
, "\n");
1654 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1655 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1656 if (dst
.regClass() == v2b
) {
1657 // TODO: check fp_mode.must_flush_denorms16_64
1658 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1659 } else if (dst
.regClass() == v1
) {
1660 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1661 } else if (dst
.regClass() == v2
) {
1662 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1663 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1664 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1666 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1669 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1670 nir_print_instr(&instr
->instr
, stderr
);
1671 fprintf(stderr
, "\n");
1676 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1677 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1678 if (dst
.regClass() == v2b
) {
1679 // TODO: check fp_mode.must_flush_denorms16_64
1680 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1681 } else if (dst
.regClass() == v1
) {
1682 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1683 } else if (dst
.regClass() == v2
) {
1684 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1685 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1686 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1688 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1697 case nir_op_fmax3
: {
1698 if (dst
.regClass() == v2b
) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1700 } else if (dst
.regClass() == v1
) {
1701 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1703 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1704 nir_print_instr(&instr
->instr
, stderr
);
1705 fprintf(stderr
, "\n");
1709 case nir_op_fmin3
: {
1710 if (dst
.regClass() == v2b
) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1712 } else if (dst
.regClass() == v1
) {
1713 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1715 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1716 nir_print_instr(&instr
->instr
, stderr
);
1717 fprintf(stderr
, "\n");
1721 case nir_op_fmed3
: {
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1727 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1728 nir_print_instr(&instr
->instr
, stderr
);
1729 fprintf(stderr
, "\n");
1733 case nir_op_umax3
: {
1734 if (dst
.size() == 1) {
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1737 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1738 nir_print_instr(&instr
->instr
, stderr
);
1739 fprintf(stderr
, "\n");
1743 case nir_op_umin3
: {
1744 if (dst
.size() == 1) {
1745 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1748 nir_print_instr(&instr
->instr
, stderr
);
1749 fprintf(stderr
, "\n");
1753 case nir_op_umed3
: {
1754 if (dst
.size() == 1) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_imax3
: {
1764 if (dst
.size() == 1) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_imin3
: {
1774 if (dst
.size() == 1) {
1775 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1777 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1778 nir_print_instr(&instr
->instr
, stderr
);
1779 fprintf(stderr
, "\n");
1783 case nir_op_imed3
: {
1784 if (dst
.size() == 1) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_cube_face_coord
: {
1794 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1795 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1796 emit_extract_vector(ctx
, in
, 1, v1
),
1797 emit_extract_vector(ctx
, in
, 2, v1
) };
1798 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1799 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1800 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1801 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1803 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1804 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1807 case nir_op_cube_face_index
: {
1808 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1809 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1810 emit_extract_vector(ctx
, in
, 1, v1
),
1811 emit_extract_vector(ctx
, in
, 2, v1
) };
1812 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1815 case nir_op_bcsel
: {
1816 emit_bcsel(ctx
, instr
, dst
);
1820 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1821 if (dst
.regClass() == v2b
) {
1822 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1823 } else if (dst
.regClass() == v1
) {
1824 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1825 } else if (dst
.regClass() == v2
) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1835 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1836 if (dst
.regClass() == v2b
) {
1837 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1838 } else if (dst
.regClass() == v1
) {
1839 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1840 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1841 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1842 } else if (dst
.regClass() == v2
) {
1843 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1844 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1845 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1846 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1847 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1848 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1850 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1851 nir_print_instr(&instr
->instr
, stderr
);
1852 fprintf(stderr
, "\n");
1857 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1858 if (dst
.regClass() == v2b
) {
1859 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1860 } else if (dst
.regClass() == v1
) {
1861 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1862 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1863 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1864 } else if (dst
.regClass() == v2
) {
1865 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1866 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1867 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1868 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1869 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1870 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1873 nir_print_instr(&instr
->instr
, stderr
);
1874 fprintf(stderr
, "\n");
1879 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1880 if (dst
.regClass() == v2b
) {
1881 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1882 } else if (dst
.regClass() == v1
) {
1883 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1884 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1885 // TODO: confirm that this holds under any circumstances
1886 } else if (dst
.regClass() == v2
) {
1887 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1888 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1891 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1892 nir_print_instr(&instr
->instr
, stderr
);
1893 fprintf(stderr
, "\n");
1897 case nir_op_flog2
: {
1898 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1899 if (dst
.regClass() == v2b
) {
1900 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1901 } else if (dst
.regClass() == v1
) {
1902 emit_log2(ctx
, bld
, Definition(dst
), src
);
1904 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1905 nir_print_instr(&instr
->instr
, stderr
);
1906 fprintf(stderr
, "\n");
1911 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1912 if (dst
.regClass() == v2b
) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1914 } else if (dst
.regClass() == v1
) {
1915 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1916 } else if (dst
.regClass() == v2
) {
1917 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1919 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1920 nir_print_instr(&instr
->instr
, stderr
);
1921 fprintf(stderr
, "\n");
1925 case nir_op_fexp2
: {
1926 if (dst
.regClass() == v2b
) {
1927 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1928 } else if (dst
.regClass() == v1
) {
1929 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1931 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1932 nir_print_instr(&instr
->instr
, stderr
);
1933 fprintf(stderr
, "\n");
1937 case nir_op_fsqrt
: {
1938 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1939 if (dst
.regClass() == v2b
) {
1940 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1941 } else if (dst
.regClass() == v1
) {
1942 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1943 } else if (dst
.regClass() == v2
) {
1944 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1946 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1947 nir_print_instr(&instr
->instr
, stderr
);
1948 fprintf(stderr
, "\n");
1952 case nir_op_ffract
: {
1953 if (dst
.regClass() == v2b
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1955 } else if (dst
.regClass() == v1
) {
1956 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1957 } else if (dst
.regClass() == v2
) {
1958 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1960 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1961 nir_print_instr(&instr
->instr
, stderr
);
1962 fprintf(stderr
, "\n");
1966 case nir_op_ffloor
: {
1967 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1968 if (dst
.regClass() == v2b
) {
1969 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1970 } else if (dst
.regClass() == v1
) {
1971 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1972 } else if (dst
.regClass() == v2
) {
1973 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1975 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1976 nir_print_instr(&instr
->instr
, stderr
);
1977 fprintf(stderr
, "\n");
1981 case nir_op_fceil
: {
1982 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1983 if (dst
.regClass() == v2b
) {
1984 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1985 } else if (dst
.regClass() == v1
) {
1986 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1987 } else if (dst
.regClass() == v2
) {
1988 if (ctx
->options
->chip_class
>= GFX7
) {
1989 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1991 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1992 /* trunc = trunc(src0)
1993 * if (src0 > 0.0 && src0 != trunc)
1996 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1997 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1998 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1999 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2000 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2001 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2002 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2005 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2006 nir_print_instr(&instr
->instr
, stderr
);
2007 fprintf(stderr
, "\n");
2011 case nir_op_ftrunc
: {
2012 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2013 if (dst
.regClass() == v2b
) {
2014 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2015 } else if (dst
.regClass() == v1
) {
2016 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2017 } else if (dst
.regClass() == v2
) {
2018 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2020 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2021 nir_print_instr(&instr
->instr
, stderr
);
2022 fprintf(stderr
, "\n");
2026 case nir_op_fround_even
: {
2027 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2028 if (dst
.regClass() == v2b
) {
2029 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2030 } else if (dst
.regClass() == v1
) {
2031 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2032 } else if (dst
.regClass() == v2
) {
2033 if (ctx
->options
->chip_class
>= GFX7
) {
2034 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2036 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2037 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2038 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2040 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2041 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2042 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2043 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2044 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2045 tmp
= sub
->definitions
[0].getTemp();
2047 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2048 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2049 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2050 Temp cond
= vop3
->definitions
[0].getTemp();
2052 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2054 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2055 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2057 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2060 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2061 nir_print_instr(&instr
->instr
, stderr
);
2062 fprintf(stderr
, "\n");
2068 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2069 aco_ptr
<Instruction
> norm
;
2070 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2071 if (dst
.regClass() == v2b
) {
2072 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2073 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2074 bld
.vop1(opcode
, Definition(dst
), tmp
);
2075 } else if (dst
.regClass() == v1
) {
2076 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2078 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2079 if (ctx
->options
->chip_class
< GFX9
)
2080 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2082 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2083 bld
.vop1(opcode
, Definition(dst
), tmp
);
2085 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2086 nir_print_instr(&instr
->instr
, stderr
);
2087 fprintf(stderr
, "\n");
2091 case nir_op_ldexp
: {
2092 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2093 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2094 if (dst
.regClass() == v2b
) {
2095 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2096 } else if (dst
.regClass() == v1
) {
2097 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2098 } else if (dst
.regClass() == v2
) {
2099 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2102 nir_print_instr(&instr
->instr
, stderr
);
2103 fprintf(stderr
, "\n");
2107 case nir_op_frexp_sig
: {
2108 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2109 if (dst
.regClass() == v2b
) {
2110 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2111 } else if (dst
.regClass() == v1
) {
2112 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2113 } else if (dst
.regClass() == v2
) {
2114 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2116 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2117 nir_print_instr(&instr
->instr
, stderr
);
2118 fprintf(stderr
, "\n");
2122 case nir_op_frexp_exp
: {
2123 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2124 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2125 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2126 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2127 convert_int(bld
, tmp
, 8, 32, true, dst
);
2128 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2129 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2130 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2131 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2133 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2134 nir_print_instr(&instr
->instr
, stderr
);
2135 fprintf(stderr
, "\n");
2139 case nir_op_fsign
: {
2140 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2141 if (dst
.regClass() == v2b
) {
2142 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2143 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2144 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2145 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2146 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2147 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2148 } else if (dst
.regClass() == v1
) {
2149 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2150 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2151 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2152 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2153 } else if (dst
.regClass() == v2
) {
2154 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2155 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2156 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2158 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2159 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2160 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2162 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2164 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2165 nir_print_instr(&instr
->instr
, stderr
);
2166 fprintf(stderr
, "\n");
2171 case nir_op_f2f16_rtne
: {
2172 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2173 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2174 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2175 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2178 case nir_op_f2f16_rtz
: {
2179 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2180 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2181 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2182 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2185 case nir_op_f2f32
: {
2186 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2187 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2188 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2189 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2192 nir_print_instr(&instr
->instr
, stderr
);
2193 fprintf(stderr
, "\n");
2197 case nir_op_f2f64
: {
2198 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2199 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2200 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2201 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2204 case nir_op_i2f16
: {
2205 assert(dst
.regClass() == v2b
);
2206 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2207 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2208 src
= convert_int(bld
, src
, 8, 16, true);
2209 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2212 case nir_op_i2f32
: {
2213 assert(dst
.size() == 1);
2214 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2215 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2216 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2217 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2220 case nir_op_i2f64
: {
2221 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2222 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2223 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2224 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2225 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2226 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2227 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2228 RegClass rc
= RegClass(src
.type(), 1);
2229 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2231 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2232 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2233 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2234 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2237 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2238 nir_print_instr(&instr
->instr
, stderr
);
2239 fprintf(stderr
, "\n");
2243 case nir_op_u2f16
: {
2244 assert(dst
.regClass() == v2b
);
2245 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2246 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2247 src
= convert_int(bld
, src
, 8, 16, false);
2248 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2251 case nir_op_u2f32
: {
2252 assert(dst
.size() == 1);
2253 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2254 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2255 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2256 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2258 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2259 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2260 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2264 case nir_op_u2f64
: {
2265 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2266 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2267 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2268 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2269 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2270 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2271 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2272 RegClass rc
= RegClass(src
.type(), 1);
2273 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2274 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2275 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2276 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2277 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2278 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2280 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2281 nir_print_instr(&instr
->instr
, stderr
);
2282 fprintf(stderr
, "\n");
2287 case nir_op_f2i16
: {
2288 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2289 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2290 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2291 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2292 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2294 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2296 if (dst
.type() == RegType::vgpr
)
2297 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2299 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2303 case nir_op_f2u16
: {
2304 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2305 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2306 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2307 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2308 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2310 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2312 if (dst
.type() == RegType::vgpr
)
2313 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2315 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2318 case nir_op_f2i32
: {
2319 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2320 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2321 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2322 if (dst
.type() == RegType::vgpr
) {
2323 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2325 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2326 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2328 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2329 if (dst
.type() == RegType::vgpr
)
2330 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2332 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2333 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2335 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2336 if (dst
.type() == RegType::vgpr
)
2337 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2339 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2340 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2343 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2344 nir_print_instr(&instr
->instr
, stderr
);
2345 fprintf(stderr
, "\n");
2349 case nir_op_f2u32
: {
2350 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2351 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2352 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2353 if (dst
.type() == RegType::vgpr
) {
2354 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2356 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2357 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2359 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2360 if (dst
.type() == RegType::vgpr
)
2361 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2363 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2364 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2366 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2367 if (dst
.type() == RegType::vgpr
)
2368 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2370 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2371 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2374 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2375 nir_print_instr(&instr
->instr
, stderr
);
2376 fprintf(stderr
, "\n");
2380 case nir_op_f2i64
: {
2381 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2382 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2383 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2385 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2386 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2387 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2388 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2389 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2390 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2391 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2392 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2393 Temp new_exponent
= bld
.tmp(v1
);
2394 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2395 if (ctx
->program
->chip_class
>= GFX8
)
2396 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2398 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2399 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2400 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2401 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2402 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2403 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2404 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2405 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2406 Temp new_lower
= bld
.tmp(v1
);
2407 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2408 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2409 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2411 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2412 if (src
.type() == RegType::vgpr
)
2413 src
= bld
.as_uniform(src
);
2414 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2415 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2416 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2417 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2418 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2419 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2420 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2421 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2422 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2423 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2424 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2425 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2426 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2427 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2428 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2429 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2430 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2431 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2432 Temp borrow
= bld
.tmp(s1
);
2433 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2434 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2437 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2438 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2439 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2440 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2441 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2442 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2443 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2444 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2445 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2446 if (dst
.type() == RegType::sgpr
) {
2447 lower
= bld
.as_uniform(lower
);
2448 upper
= bld
.as_uniform(upper
);
2450 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2453 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2454 nir_print_instr(&instr
->instr
, stderr
);
2455 fprintf(stderr
, "\n");
2459 case nir_op_f2u64
: {
2460 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2461 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2462 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2464 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2465 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2466 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2467 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2468 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2469 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2470 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2471 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2472 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2473 Temp new_exponent
= bld
.tmp(v1
);
2474 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2475 if (ctx
->program
->chip_class
>= GFX8
)
2476 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2478 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2479 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2481 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2482 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2483 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2484 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2485 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2487 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2488 if (src
.type() == RegType::vgpr
)
2489 src
= bld
.as_uniform(src
);
2490 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2491 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2492 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2493 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2494 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2495 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2496 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2497 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2498 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2499 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2500 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2501 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2502 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2503 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2504 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2505 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2506 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2507 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2509 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2510 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2511 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2512 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2513 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2514 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2515 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2516 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2517 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2518 if (dst
.type() == RegType::sgpr
) {
2519 lower
= bld
.as_uniform(lower
);
2520 upper
= bld
.as_uniform(upper
);
2522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2526 nir_print_instr(&instr
->instr
, stderr
);
2527 fprintf(stderr
, "\n");
2531 case nir_op_b2f16
: {
2532 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2533 assert(src
.regClass() == bld
.lm
);
2535 if (dst
.regClass() == s1
) {
2536 src
= bool_to_scalar_condition(ctx
, src
);
2537 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2538 } else if (dst
.regClass() == v2b
) {
2539 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2540 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2542 unreachable("Wrong destination register class for nir_op_b2f16.");
2546 case nir_op_b2f32
: {
2547 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2548 assert(src
.regClass() == bld
.lm
);
2550 if (dst
.regClass() == s1
) {
2551 src
= bool_to_scalar_condition(ctx
, src
);
2552 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2553 } else if (dst
.regClass() == v1
) {
2554 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2556 unreachable("Wrong destination register class for nir_op_b2f32.");
2560 case nir_op_b2f64
: {
2561 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2562 assert(src
.regClass() == bld
.lm
);
2564 if (dst
.regClass() == s2
) {
2565 src
= bool_to_scalar_condition(ctx
, src
);
2566 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2567 } else if (dst
.regClass() == v2
) {
2568 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2569 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2570 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2572 unreachable("Wrong destination register class for nir_op_b2f64.");
2579 case nir_op_i2i64
: {
2580 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2581 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2587 case nir_op_u2u64
: {
2588 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2589 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2593 case nir_op_b2i32
: {
2594 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2595 assert(src
.regClass() == bld
.lm
);
2597 if (dst
.regClass() == s1
) {
2598 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2599 bool_to_scalar_condition(ctx
, src
, dst
);
2600 } else if (dst
.regClass() == v1
) {
2601 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2603 unreachable("Invalid register class for b2i32");
2609 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2610 assert(dst
.regClass() == bld
.lm
);
2612 if (src
.type() == RegType::vgpr
) {
2613 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2614 assert(dst
.regClass() == bld
.lm
);
2615 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2616 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2618 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2620 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2621 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2623 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2624 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2626 bool_to_vector_condition(ctx
, tmp
, dst
);
2630 case nir_op_pack_64_2x32_split
: {
2631 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2632 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2634 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2637 case nir_op_unpack_64_2x32_split_x
:
2638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2640 case nir_op_unpack_64_2x32_split_y
:
2641 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2643 case nir_op_unpack_32_2x16_split_x
:
2644 if (dst
.type() == RegType::vgpr
) {
2645 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2647 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2650 case nir_op_unpack_32_2x16_split_y
:
2651 if (dst
.type() == RegType::vgpr
) {
2652 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2654 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2657 case nir_op_pack_32_2x16_split
: {
2658 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2659 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2660 if (dst
.regClass() == v1
) {
2661 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2662 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2663 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2665 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2666 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2667 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2671 case nir_op_pack_half_2x16
: {
2672 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2674 if (dst
.regClass() == v1
) {
2675 Temp src0
= bld
.tmp(v1
);
2676 Temp src1
= bld
.tmp(v1
);
2677 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2678 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2679 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2681 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2682 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2683 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2685 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2686 nir_print_instr(&instr
->instr
, stderr
);
2687 fprintf(stderr
, "\n");
2691 case nir_op_unpack_half_2x16_split_x
: {
2692 if (dst
.regClass() == v1
) {
2693 Builder
bld(ctx
->program
, ctx
->block
);
2694 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2696 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2697 nir_print_instr(&instr
->instr
, stderr
);
2698 fprintf(stderr
, "\n");
2702 case nir_op_unpack_half_2x16_split_y
: {
2703 if (dst
.regClass() == v1
) {
2704 Builder
bld(ctx
->program
, ctx
->block
);
2705 /* TODO: use SDWA here */
2706 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2707 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2709 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2710 nir_print_instr(&instr
->instr
, stderr
);
2711 fprintf(stderr
, "\n");
2715 case nir_op_fquantize2f16
: {
2716 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2717 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2720 if (ctx
->program
->chip_class
>= GFX8
) {
2721 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2722 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2723 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2725 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2726 * so compare the result and flush to 0 if it's smaller.
2728 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2729 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2730 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2731 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2732 cmp_res
= vop3
->definitions
[0].getTemp();
2735 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2736 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2737 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2739 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2744 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2745 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2747 if (dst
.regClass() == s1
) {
2748 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2749 } else if (dst
.regClass() == v1
) {
2750 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2752 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2753 nir_print_instr(&instr
->instr
, stderr
);
2754 fprintf(stderr
, "\n");
2758 case nir_op_bitfield_select
: {
2759 /* (mask & insert) | (~mask & base) */
2760 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2761 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2762 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2764 /* dst = (insert & bitmask) | (base & ~bitmask) */
2765 if (dst
.regClass() == s1
) {
2766 aco_ptr
<Instruction
> sop2
;
2767 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2768 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2770 if (const_insert
&& const_bitmask
) {
2771 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2773 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2774 lhs
= Operand(insert
);
2778 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2779 if (const_base
&& const_bitmask
) {
2780 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2782 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2783 rhs
= Operand(base
);
2786 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2788 } else if (dst
.regClass() == v1
) {
2789 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2790 base
= as_vgpr(ctx
, base
);
2791 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2792 insert
= as_vgpr(ctx
, insert
);
2794 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2798 nir_print_instr(&instr
->instr
, stderr
);
2799 fprintf(stderr
, "\n");
2805 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2806 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2807 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2809 if (dst
.type() == RegType::sgpr
) {
2811 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2812 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2813 if (const_offset
&& const_bits
) {
2814 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2815 extract
= Operand(const_extract
);
2819 width
= Operand(const_bits
->u32
<< 16);
2821 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2823 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2827 if (dst
.regClass() == s1
) {
2828 if (instr
->op
== nir_op_ubfe
)
2829 opcode
= aco_opcode::s_bfe_u32
;
2831 opcode
= aco_opcode::s_bfe_i32
;
2832 } else if (dst
.regClass() == s2
) {
2833 if (instr
->op
== nir_op_ubfe
)
2834 opcode
= aco_opcode::s_bfe_u64
;
2836 opcode
= aco_opcode::s_bfe_i64
;
2838 unreachable("Unsupported BFE bit size");
2841 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2845 if (dst
.regClass() == v1
) {
2846 if (instr
->op
== nir_op_ubfe
)
2847 opcode
= aco_opcode::v_bfe_u32
;
2849 opcode
= aco_opcode::v_bfe_i32
;
2851 unreachable("Unsupported BFE bit size");
2854 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2858 case nir_op_bit_count
: {
2859 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2860 if (src
.regClass() == s1
) {
2861 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2862 } else if (src
.regClass() == v1
) {
2863 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2864 } else if (src
.regClass() == v2
) {
2865 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2866 emit_extract_vector(ctx
, src
, 1, v1
),
2867 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2868 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2869 } else if (src
.regClass() == s2
) {
2870 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2873 nir_print_instr(&instr
->instr
, stderr
);
2874 fprintf(stderr
, "\n");
2879 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2883 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2887 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2891 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2895 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2899 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2903 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2904 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2906 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2907 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2911 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2912 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2914 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2915 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2919 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2923 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2928 case nir_op_fddx_fine
:
2929 case nir_op_fddy_fine
:
2930 case nir_op_fddx_coarse
:
2931 case nir_op_fddy_coarse
: {
2932 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2933 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2934 if (instr
->op
== nir_op_fddx_fine
) {
2935 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2936 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2937 } else if (instr
->op
== nir_op_fddy_fine
) {
2938 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2939 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2941 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2942 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2943 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2945 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2949 if (ctx
->program
->chip_class
>= GFX8
) {
2950 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2951 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2953 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2954 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2955 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2957 emit_wqm(ctx
, tmp
, dst
, true);
2961 fprintf(stderr
, "Unknown NIR ALU instr: ");
2962 nir_print_instr(&instr
->instr
, stderr
);
2963 fprintf(stderr
, "\n");
2967 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2969 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2971 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2972 // which get truncated the lsb if double and msb if int
2973 // for now, we only use s_mov_b64 with 64bit inline constants
2974 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2975 assert(dst
.type() == RegType::sgpr
);
2977 Builder
bld(ctx
->program
, ctx
->block
);
2979 if (instr
->def
.bit_size
== 1) {
2980 assert(dst
.regClass() == bld
.lm
);
2981 int val
= instr
->value
[0].b
? -1 : 0;
2982 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2983 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2984 } else if (instr
->def
.bit_size
== 8) {
2985 /* ensure that the value is correctly represented in the low byte of the register */
2986 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2987 } else if (instr
->def
.bit_size
== 16) {
2988 /* ensure that the value is correctly represented in the low half of the register */
2989 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2990 } else if (dst
.size() == 1) {
2991 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2993 assert(dst
.size() != 1);
2994 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2995 if (instr
->def
.bit_size
== 64)
2996 for (unsigned i
= 0; i
< dst
.size(); i
++)
2997 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2999 for (unsigned i
= 0; i
< dst
.size(); i
++)
3000 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3002 vec
->definitions
[0] = Definition(dst
);
3003 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3007 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3009 uint32_t new_mask
= 0;
3010 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3011 if (mask
& (1u << i
))
3012 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3016 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3018 Builder
bld(ctx
->program
, ctx
->block
);
3019 if (offset
.isTemp()) {
3020 Temp tmp
[3] = {vec
, vec
, vec
};
3022 if (vec
.size() == 3) {
3023 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3024 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3025 } else if (vec
.size() == 2) {
3026 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3027 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3029 for (unsigned i
= 0; i
< dst
.size(); i
++)
3030 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3033 if (dst
.size() == 2)
3034 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3036 offset
= Operand(0u);
3039 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3040 bld
.copy(Definition(dst
), vec
);
3042 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3045 struct LoadEmitInfo
{
3048 unsigned num_components
;
3049 unsigned component_size
;
3050 Temp resource
= Temp(0, s1
);
3051 unsigned component_stride
= 0;
3052 unsigned const_offset
= 0;
3053 unsigned align_mul
= 0;
3054 unsigned align_offset
= 0;
3057 unsigned swizzle_component_size
= 0;
3058 barrier_interaction barrier
= barrier_none
;
3059 bool can_reorder
= true;
3060 Temp soffset
= Temp(0, s1
);
3063 using LoadCallback
= Temp(*)(
3064 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3065 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3067 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3068 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3070 unsigned load_size
= info
->num_components
* info
->component_size
;
3071 unsigned component_size
= info
->component_size
;
3073 unsigned num_vals
= 0;
3074 Temp vals
[info
->dst
.bytes()];
3076 unsigned const_offset
= info
->const_offset
;
3078 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3079 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3081 unsigned bytes_read
= 0;
3082 while (bytes_read
< load_size
) {
3083 unsigned bytes_needed
= load_size
- bytes_read
;
3085 /* add buffer for unaligned loads */
3086 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3089 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3090 if (info
->component_stride
) {
3091 assert(supports_8bit_16bit_loads
&& "unimplemented");
3095 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3096 bytes_needed
= align(bytes_needed
, 4);
3103 if (info
->swizzle_component_size
)
3104 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3105 if (info
->component_stride
)
3106 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3108 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3110 /* reduce constant offset */
3111 Operand offset
= info
->offset
;
3112 unsigned reduced_const_offset
= const_offset
;
3113 bool remove_const_offset_completely
= need_to_align_offset
;
3114 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3115 unsigned to_add
= const_offset
;
3116 if (remove_const_offset_completely
) {
3117 reduced_const_offset
= 0;
3119 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3120 reduced_const_offset
%= max_const_offset_plus_one
;
3122 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3123 if (offset
.isConstant()) {
3124 offset
= Operand(offset
.constantValue() + to_add
);
3125 } else if (offset_tmp
.regClass() == s1
) {
3126 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3127 offset_tmp
, Operand(to_add
));
3128 } else if (offset_tmp
.regClass() == v1
) {
3129 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3131 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3132 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3133 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3135 if (offset_tmp
.regClass() == s2
) {
3136 Temp carry
= bld
.tmp(s1
);
3137 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3138 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3139 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3141 Temp new_lo
= bld
.tmp(v1
);
3142 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3143 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3144 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3149 /* align offset down if needed */
3150 Operand aligned_offset
= offset
;
3151 if (need_to_align_offset
) {
3152 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3153 if (offset
.isConstant()) {
3154 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3155 } else if (offset_tmp
.regClass() == s1
) {
3156 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3157 } else if (offset_tmp
.regClass() == s2
) {
3158 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3159 } else if (offset_tmp
.regClass() == v1
) {
3160 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3161 } else if (offset_tmp
.regClass() == v2
) {
3162 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3163 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3164 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3165 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3168 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3169 bld
.copy(bld
.def(s1
), aligned_offset
);
3171 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3172 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3173 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3175 /* shift result right if needed */
3177 Operand
align((uint32_t)byte_align
);
3178 if (byte_align
== -1) {
3179 if (offset
.isConstant())
3180 align
= Operand(offset
.constantValue() % 4u);
3181 else if (offset
.size() == 2)
3182 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3187 if (align
.isTemp() || align
.constantValue()) {
3188 assert(val
.bytes() >= load_size
&& "unimplemented");
3189 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3190 if (val
.type() == RegType::sgpr
)
3191 byte_align_scalar(ctx
, val
, align
, new_val
);
3193 byte_align_vector(ctx
, val
, align
, new_val
);
3198 /* add result to list and advance */
3199 if (info
->component_stride
) {
3200 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3201 const_offset
+= info
->component_stride
;
3202 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3204 const_offset
+= val
.bytes();
3205 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3207 bytes_read
+= val
.bytes();
3208 vals
[num_vals
++] = val
;
3211 /* the callback wrote directly to dst */
3212 if (vals
[0] == info
->dst
) {
3213 assert(num_vals
== 1);
3214 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3218 /* create array of components */
3219 unsigned components_split
= 0;
3220 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3221 bool has_vgprs
= false;
3222 for (unsigned i
= 0; i
< num_vals
;) {
3224 unsigned num_tmps
= 0;
3225 unsigned tmp_size
= 0;
3226 RegType reg_type
= RegType::sgpr
;
3227 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3228 if (vals
[i
].type() == RegType::vgpr
)
3229 reg_type
= RegType::vgpr
;
3230 tmp_size
+= vals
[i
].bytes();
3231 tmp
[num_tmps
++] = vals
[i
++];
3234 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3235 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3236 for (unsigned i
= 0; i
< num_vals
; i
++)
3237 vec
->operands
[i
] = Operand(tmp
[i
]);
3238 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3239 vec
->definitions
[0] = Definition(tmp
[0]);
3240 bld
.insert(std::move(vec
));
3243 if (tmp
[0].bytes() % component_size
) {
3245 assert(i
== num_vals
);
3246 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3247 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3250 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3252 unsigned start
= components_split
;
3254 if (tmp_size
== elem_rc
.bytes()) {
3255 allocated_vec
[components_split
++] = tmp
[0];
3257 assert(tmp_size
% elem_rc
.bytes() == 0);
3258 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3259 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3260 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3261 Temp component
= bld
.tmp(elem_rc
);
3262 allocated_vec
[components_split
++] = component
;
3263 split
->definitions
[i
] = Definition(component
);
3265 split
->operands
[0] = Operand(tmp
[0]);
3266 bld
.insert(std::move(split
));
3269 /* try to p_as_uniform early so we can create more optimizable code and
3270 * also update allocated_vec */
3271 for (unsigned j
= start
; j
< components_split
; j
++) {
3272 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3273 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3274 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3278 /* concatenate components and p_as_uniform() result if needed */
3279 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3280 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3282 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3284 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3285 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3286 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3287 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3289 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3290 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3291 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3292 vec
->definitions
[0] = Definition(tmp
);
3293 bld
.insert(std::move(vec
));
3294 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3296 vec
->definitions
[0] = Definition(info
->dst
);
3297 bld
.insert(std::move(vec
));
3301 Operand
load_lds_size_m0(Builder
& bld
)
3303 /* TODO: m0 does not need to be initialized on GFX9+ */
3304 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3307 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3308 Temp offset
, unsigned bytes_needed
,
3309 unsigned align
, unsigned const_offset
,
3312 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3314 Operand m
= load_lds_size_m0(bld
);
3316 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3317 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3322 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3323 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3325 op
= aco_opcode::ds_read_b128
;
3326 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3329 op
= aco_opcode::ds_read2_b64
;
3330 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3332 op
= aco_opcode::ds_read_b96
;
3333 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3335 op
= aco_opcode::ds_read_b64
;
3336 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3339 op
= aco_opcode::ds_read2_b32
;
3340 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3342 op
= aco_opcode::ds_read_b32
;
3343 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3345 op
= aco_opcode::ds_read_u16
;
3348 op
= aco_opcode::ds_read_u8
;
3351 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3352 if (const_offset
>= max_offset_plus_one
) {
3353 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3354 const_offset
%= max_offset_plus_one
;
3358 const_offset
/= (size
/ 2u);
3360 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3361 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3363 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3365 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3368 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3373 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3375 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3376 Temp offset
, unsigned bytes_needed
,
3377 unsigned align
, unsigned const_offset
,
3382 if (bytes_needed
<= 4) {
3384 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3385 } else if (bytes_needed
<= 8) {
3387 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3388 } else if (bytes_needed
<= 16) {
3390 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3391 } else if (bytes_needed
<= 32) {
3393 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3396 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3398 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3399 if (info
->resource
.id()) {
3400 load
->operands
[0] = Operand(info
->resource
);
3401 load
->operands
[1] = Operand(offset
);
3403 load
->operands
[0] = Operand(offset
);
3404 load
->operands
[1] = Operand(0u);
3406 RegClass
rc(RegType::sgpr
, size
);
3407 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3408 load
->definitions
[0] = Definition(val
);
3409 load
->glc
= info
->glc
;
3410 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3411 load
->barrier
= info
->barrier
;
3412 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3413 bld
.insert(std::move(load
));
3417 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3419 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3420 Temp offset
, unsigned bytes_needed
,
3421 unsigned align_
, unsigned const_offset
,
3424 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3425 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3427 if (info
->soffset
.id()) {
3428 if (soffset
.isTemp())
3429 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3430 soffset
= Operand(info
->soffset
);
3433 unsigned bytes_size
= 0;
3435 if (bytes_needed
== 1) {
3437 op
= aco_opcode::buffer_load_ubyte
;
3438 } else if (bytes_needed
== 2) {
3440 op
= aco_opcode::buffer_load_ushort
;
3441 } else if (bytes_needed
<= 4) {
3443 op
= aco_opcode::buffer_load_dword
;
3444 } else if (bytes_needed
<= 8) {
3446 op
= aco_opcode::buffer_load_dwordx2
;
3447 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3449 op
= aco_opcode::buffer_load_dwordx3
;
3452 op
= aco_opcode::buffer_load_dwordx4
;
3454 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3455 mubuf
->operands
[0] = Operand(info
->resource
);
3456 mubuf
->operands
[1] = vaddr
;
3457 mubuf
->operands
[2] = soffset
;
3458 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3459 mubuf
->glc
= info
->glc
;
3460 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3461 mubuf
->barrier
= info
->barrier
;
3462 mubuf
->can_reorder
= info
->can_reorder
;
3463 mubuf
->offset
= const_offset
;
3464 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3465 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3466 mubuf
->definitions
[0] = Definition(val
);
3467 bld
.insert(std::move(mubuf
));
3470 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3475 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3477 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3479 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3480 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3482 if (addr
.type() == RegType::vgpr
)
3483 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3484 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3487 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3488 Temp offset
, unsigned bytes_needed
,
3489 unsigned align_
, unsigned const_offset
,
3492 unsigned bytes_size
= 0;
3493 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3494 bool global
= bld
.program
->chip_class
>= GFX9
;
3496 if (bytes_needed
== 1) {
3498 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3499 } else if (bytes_needed
== 2) {
3501 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3502 } else if (bytes_needed
<= 4) {
3504 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3505 } else if (bytes_needed
<= 8) {
3507 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3508 } else if (bytes_needed
<= 12 && !mubuf
) {
3510 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3513 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3515 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3516 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3518 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3519 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3520 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3521 mubuf
->operands
[2] = Operand(0u);
3522 mubuf
->glc
= info
->glc
;
3525 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3526 mubuf
->disable_wqm
= false;
3527 mubuf
->barrier
= info
->barrier
;
3528 mubuf
->definitions
[0] = Definition(val
);
3529 bld
.insert(std::move(mubuf
));
3531 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3533 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3534 flat
->operands
[0] = Operand(offset
);
3535 flat
->operands
[1] = Operand(s1
);
3536 flat
->glc
= info
->glc
;
3537 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3538 flat
->barrier
= info
->barrier
;
3540 flat
->definitions
[0] = Definition(val
);
3541 bld
.insert(std::move(flat
));
3545 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3550 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3552 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3553 Temp address
, unsigned base_offset
, unsigned align
)
3555 assert(util_is_power_of_two_nonzero(align
));
3557 Builder
bld(ctx
->program
, ctx
->block
);
3559 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3560 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3561 info
.align_mul
= align
;
3562 info
.align_offset
= 0;
3563 info
.barrier
= barrier_shared
;
3564 info
.can_reorder
= false;
3565 info
.const_offset
= base_offset
;
3566 emit_lds_load(ctx
, bld
, &info
);
3571 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3576 Builder
bld(ctx
->program
, ctx
->block
);
3578 ASSERTED
bool is_subdword
= false;
3579 for (unsigned i
= 0; i
< count
; i
++)
3580 is_subdword
|= offsets
[i
] % 4;
3581 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3582 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3584 /* count == 1 fast path */
3586 if (dst_type
== RegType::sgpr
)
3587 dst
[0] = bld
.as_uniform(src
);
3589 dst
[0] = as_vgpr(ctx
, src
);
3593 for (unsigned i
= 0; i
< count
- 1; i
++)
3594 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3595 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3597 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3598 src
= as_vgpr(ctx
, src
);
3600 /* use allocated_vec if possible */
3601 auto it
= ctx
->allocated_vec
.find(src
.id());
3602 if (it
!= ctx
->allocated_vec
.end()) {
3603 unsigned total_size
= 0;
3604 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3605 total_size
+= it
->second
[i
].bytes();
3606 if (total_size
!= src
.bytes())
3609 unsigned elem_size
= it
->second
[0].bytes();
3611 for (unsigned i
= 0; i
< count
; i
++) {
3612 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3616 for (unsigned i
= 0; i
< count
; i
++) {
3617 unsigned start_idx
= offsets
[i
] / elem_size
;
3618 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3619 if (op_count
== 1) {
3620 if (dst_type
== RegType::sgpr
)
3621 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3623 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3627 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3628 for (unsigned j
= 0; j
< op_count
; j
++) {
3629 Temp tmp
= it
->second
[start_idx
+ j
];
3630 if (dst_type
== RegType::sgpr
)
3631 tmp
= bld
.as_uniform(tmp
);
3632 vec
->operands
[j
] = Operand(tmp
);
3634 vec
->definitions
[0] = Definition(dst
[i
]);
3635 bld
.insert(std::move(vec
));
3641 if (dst_type
== RegType::sgpr
)
3642 src
= bld
.as_uniform(src
);
3646 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3647 split
->operands
[0] = Operand(src
);
3648 for (unsigned i
= 0; i
< count
; i
++)
3649 split
->definitions
[i
] = Definition(dst
[i
]);
3650 bld
.insert(std::move(split
));
3653 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3654 int *start
, int *count
)
3656 unsigned start_elem
= ffs(todo_mask
) - 1;
3657 bool skip
= !(mask
& (1 << start_elem
));
3659 mask
= ~mask
& todo_mask
;
3663 u_bit_scan_consecutive_range(&mask
, start
, count
);
3668 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3670 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3673 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3674 Temp address
, unsigned base_offset
, unsigned align
)
3676 assert(util_is_power_of_two_nonzero(align
));
3677 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3679 Builder
bld(ctx
->program
, ctx
->block
);
3680 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3681 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3683 unsigned write_count
= 0;
3684 Temp write_datas
[32];
3685 unsigned offsets
[32];
3686 aco_opcode opcodes
[32];
3688 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3690 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3693 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3694 offsets
[write_count
] = offset
;
3695 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3697 advance_write_mask(&todo
, offset
, bytes
);
3701 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3702 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3703 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3704 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3706 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3707 aco_opcode op
= aco_opcode::num_opcodes
;
3708 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3709 op
= aco_opcode::ds_write_b128
;
3711 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3712 op
= aco_opcode::ds_write_b96
;
3714 } else if (bytes
>= 8 && aligned8
) {
3715 op
= aco_opcode::ds_write_b64
;
3717 } else if (bytes
>= 4 && aligned4
) {
3718 op
= aco_opcode::ds_write_b32
;
3720 } else if (bytes
>= 2 && aligned2
) {
3721 op
= aco_opcode::ds_write_b16
;
3723 } else if (bytes
>= 1) {
3724 op
= aco_opcode::ds_write_b8
;
3730 offsets
[write_count
] = offset
;
3731 opcodes
[write_count
] = op
;
3733 advance_write_mask(&todo
, offset
, bytes
);
3736 Operand m
= load_lds_size_m0(bld
);
3738 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3740 for (unsigned i
= 0; i
< write_count
; i
++) {
3741 aco_opcode op
= opcodes
[i
];
3742 if (op
== aco_opcode::num_opcodes
)
3745 Temp data
= write_datas
[i
];
3747 unsigned second
= write_count
;
3748 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3749 for (second
= i
+ 1; second
< write_count
; second
++) {
3750 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3751 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3752 opcodes
[second
] = aco_opcode::num_opcodes
;
3758 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3759 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3761 unsigned inline_offset
= base_offset
+ offsets
[i
];
3762 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3763 Temp address_offset
= address
;
3764 if (inline_offset
> max_offset
) {
3765 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3766 inline_offset
= offsets
[i
];
3768 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3771 Temp second_data
= write_datas
[second
];
3772 inline_offset
/= data
.bytes();
3773 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3775 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3780 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3782 unsigned align
= 16;
3784 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3790 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3795 return aco_opcode::buffer_store_byte
;
3798 return aco_opcode::buffer_store_short
;
3800 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3802 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3805 return aco_opcode::buffer_store_dwordx3
;
3807 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3809 unreachable("Unexpected store size");
3810 return aco_opcode::num_opcodes
;
3813 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3814 Temp data
, unsigned writemask
, int swizzle_element_size
,
3815 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3817 unsigned write_count_with_skips
= 0;
3820 /* determine how to split the data */
3821 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3824 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3825 offsets
[write_count_with_skips
] = offset
;
3826 if (skips
[write_count_with_skips
]) {
3827 advance_write_mask(&todo
, offset
, bytes
);
3828 write_count_with_skips
++;
3832 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3833 * larger than swizzle_element_size */
3834 bytes
= MIN2(bytes
, swizzle_element_size
);
3836 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3838 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3839 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3842 /* dword or larger stores have to be dword-aligned */
3843 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3844 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3845 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3846 if (bytes
>= 4 && !dword_aligned
)
3847 bytes
= MIN2(bytes
, 2);
3849 advance_write_mask(&todo
, offset
, bytes
);
3850 write_count_with_skips
++;
3853 /* actually split data */
3854 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3857 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3860 write_datas
[*write_count
] = write_datas
[i
];
3861 offsets
[*write_count
] = offsets
[i
];
3866 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3867 unsigned split_cnt
= 0u, Temp dst
= Temp())
3869 Builder
bld(ctx
->program
, ctx
->block
);
3870 unsigned dword_size
= elem_size_bytes
/ 4;
3873 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3875 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3876 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3877 instr
->definitions
[0] = Definition(dst
);
3879 for (unsigned i
= 0; i
< cnt
; ++i
) {
3881 assert(arr
[i
].size() == dword_size
);
3882 allocated_vec
[i
] = arr
[i
];
3883 instr
->operands
[i
] = Operand(arr
[i
]);
3885 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3886 allocated_vec
[i
] = zero
;
3887 instr
->operands
[i
] = Operand(zero
);
3891 bld
.insert(std::move(instr
));
3894 emit_split_vector(ctx
, dst
, split_cnt
);
3896 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3901 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3903 if (const_offset
>= 4096) {
3904 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3905 const_offset
%= 4096u;
3908 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3909 else if (unlikely(voffset
.regClass() == s1
))
3910 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3911 else if (likely(voffset
.regClass() == v1
))
3912 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3914 unreachable("Unsupported register class of voffset");
3917 return const_offset
;
3920 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3921 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3924 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3925 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3927 Builder
bld(ctx
->program
, ctx
->block
);
3928 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3929 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3931 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3932 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3933 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3934 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3935 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3937 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3940 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3941 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3942 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3944 Builder
bld(ctx
->program
, ctx
->block
);
3945 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3947 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3949 unsigned write_count
= 0;
3950 Temp write_datas
[32];
3951 unsigned offsets
[32];
3952 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3953 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3955 for (unsigned i
= 0; i
< write_count
; i
++) {
3956 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3957 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3961 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3962 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3963 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3965 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3966 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3967 assert(!!stride
!= allow_combining
);
3969 Builder
bld(ctx
->program
, ctx
->block
);
3971 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3972 info
.component_stride
= allow_combining
? 0 : stride
;
3974 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3975 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3976 info
.align_offset
= 0;
3977 info
.soffset
= soffset
;
3978 info
.const_offset
= base_const_offset
;
3979 emit_mubuf_load(ctx
, bld
, &info
);
3982 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3984 Builder
bld(ctx
->program
, ctx
->block
);
3985 Temp offset
= base_offset
.first
;
3986 unsigned const_offset
= base_offset
.second
;
3988 if (!nir_src_is_const(*off_src
)) {
3989 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3992 /* Calculate indirect offset with stride */
3993 if (likely(indirect_offset_arg
.regClass() == v1
))
3994 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3995 else if (indirect_offset_arg
.regClass() == s1
)
3996 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3998 unreachable("Unsupported register class of indirect offset");
4000 /* Add to the supplied base offset */
4001 if (offset
.id() == 0)
4002 offset
= with_stride
;
4003 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4004 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4005 else if (offset
.size() == 1 && with_stride
.size() == 1)
4006 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4008 unreachable("Unsupported register class of indirect offset");
4010 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4011 const_offset
+= const_offset_arg
* stride
;
4014 return std::make_pair(offset
, const_offset
);
4017 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4019 Builder
bld(ctx
->program
, ctx
->block
);
4022 if (off1
.first
.id() && off2
.first
.id()) {
4023 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4024 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4025 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4026 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4028 unreachable("Unsupported register class of indirect offset");
4030 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4033 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4036 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4038 Builder
bld(ctx
->program
, ctx
->block
);
4039 unsigned const_offset
= offs
.second
* multiplier
;
4041 if (!offs
.first
.id())
4042 return std::make_pair(offs
.first
, const_offset
);
4044 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4045 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4046 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4048 return std::make_pair(offset
, const_offset
);
4051 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4053 Builder
bld(ctx
->program
, ctx
->block
);
4055 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4056 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4057 /* component is in bytes */
4058 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4060 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4061 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4062 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4065 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4067 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4070 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4072 Builder
bld(ctx
->program
, ctx
->block
);
4074 switch (ctx
->shader
->info
.stage
) {
4075 case MESA_SHADER_TESS_CTRL
:
4076 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4077 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4078 case MESA_SHADER_TESS_EVAL
:
4079 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4081 unreachable("Unsupported stage in get_tess_rel_patch_id");
4085 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4087 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4088 Builder
bld(ctx
->program
, ctx
->block
);
4090 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4091 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4093 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4095 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4096 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4098 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4099 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4100 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4102 return offset_mul(ctx
, offs
, 4u);
4105 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4107 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4108 Builder
bld(ctx
->program
, ctx
->block
);
4110 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4111 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4112 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4113 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4115 std::pair
<Temp
, unsigned> offs
= instr
4116 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4117 : std::make_pair(Temp(), 0u);
4119 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4120 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4125 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4126 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4128 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4129 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4131 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4132 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4138 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4140 Builder
bld(ctx
->program
, ctx
->block
);
4142 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4143 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4145 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4147 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4148 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4149 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4151 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4152 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4157 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4159 Builder
bld(ctx
->program
, ctx
->block
);
4161 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4162 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4163 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4164 unsigned attr_stride
= ctx
->tcs_num_patches
;
4166 std::pair
<Temp
, unsigned> offs
= instr
4167 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4168 : std::make_pair(Temp(), 0u);
4170 if (const_base_offset
)
4171 offs
.second
+= const_base_offset
* attr_stride
;
4173 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4174 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4175 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4180 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4182 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4187 unsigned drv_loc
= nir_intrinsic_base(instr
);
4188 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4190 if (!nir_src_is_const(*off_src
)) {
4196 uint64_t slot
= per_vertex
4197 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4198 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4199 return (((uint64_t) 1) << slot
) & mask
;
4202 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4204 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4205 unsigned component
= nir_intrinsic_component(instr
);
4206 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4208 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4209 if (off_instr
->type
!= nir_instr_type_load_const
)
4212 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4213 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4215 if (instr
->src
[0].ssa
->bit_size
== 64)
4216 write_mask
= widen_mask(write_mask
, 2);
4218 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4220 for (unsigned i
= 0; i
< 8; ++i
) {
4221 if (write_mask
& (1 << i
)) {
4222 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4223 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4231 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4233 /* Only TCS per-vertex inputs are supported by this function.
4234 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4236 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4239 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4240 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4241 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4242 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4243 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4244 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4249 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4250 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4251 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4256 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4258 Builder
bld(ctx
->program
, ctx
->block
);
4260 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4261 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4262 bool indirect_write
;
4263 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4264 if (temp_only_input
&& !indirect_write
)
4268 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4269 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4270 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4271 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4273 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4274 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4275 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4276 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4277 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4281 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4282 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4283 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4284 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4285 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4286 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4287 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4288 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4289 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4290 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4291 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4292 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4293 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4295 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4296 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4298 unreachable("Invalid LS or ES stage");
4301 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4302 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4303 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4307 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4312 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4313 return off
== ctx
->tcs_tess_lvl_out_loc
||
4314 off
== ctx
->tcs_tess_lvl_in_loc
;
4318 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4320 uint64_t mask
= per_vertex
4321 ? ctx
->program
->info
->tcs
.tes_inputs_read
4322 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4324 bool indirect_write
= false;
4325 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4326 return indirect_write
|| output_read_by_tes
;
4329 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4331 uint64_t mask
= per_vertex
4332 ? ctx
->shader
->info
.outputs_read
4333 : ctx
->shader
->info
.patch_outputs_read
;
4335 bool indirect_write
= false;
4336 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4337 return indirect_write
|| output_read
;
4340 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4342 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4343 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4345 Builder
bld(ctx
->program
, ctx
->block
);
4347 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4348 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4349 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4351 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4352 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4353 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4355 if (write_to_vmem
) {
4356 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4357 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4358 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4360 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4361 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4362 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4366 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4367 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4368 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4372 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4374 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4375 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4377 Builder
bld(ctx
->program
, ctx
->block
);
4379 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4380 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4381 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4382 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4384 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4387 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4389 if (ctx
->stage
== vertex_vs
||
4390 ctx
->stage
== tess_eval_vs
||
4391 ctx
->stage
== fragment_fs
||
4392 ctx
->stage
== ngg_vertex_gs
||
4393 ctx
->stage
== ngg_tess_eval_gs
||
4394 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4395 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4396 if (!stored_to_temps
) {
4397 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4398 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4399 fprintf(stderr
, "\n");
4402 } else if (ctx
->stage
== vertex_es
||
4403 ctx
->stage
== vertex_ls
||
4404 ctx
->stage
== tess_eval_es
||
4405 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4406 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4407 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4408 visit_store_ls_or_es_output(ctx
, instr
);
4409 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4410 visit_store_tcs_output(ctx
, instr
, false);
4412 unreachable("Shader stage not implemented");
4416 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4418 visit_load_tcs_output(ctx
, instr
, false);
4421 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4423 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4424 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4426 Builder
bld(ctx
->program
, ctx
->block
);
4428 if (dst
.regClass() == v2b
) {
4429 if (ctx
->program
->has_16bank_lds
) {
4430 assert(ctx
->options
->chip_class
<= GFX8
);
4431 Builder::Result interp_p1
=
4432 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4433 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4434 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4435 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4436 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4437 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4439 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4441 if (ctx
->options
->chip_class
== GFX8
)
4442 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4444 Builder::Result interp_p1
=
4445 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4446 coord1
, bld
.m0(prim_mask
), idx
, component
);
4447 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4448 interp_p1
, idx
, component
);
4451 Builder::Result interp_p1
=
4452 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4453 bld
.m0(prim_mask
), idx
, component
);
4455 if (ctx
->program
->has_16bank_lds
)
4456 interp_p1
.instr
->operands
[0].setLateKill(true);
4458 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4459 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4463 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4465 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4466 for (unsigned i
= 0; i
< num_components
; i
++)
4467 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4468 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4469 assert(num_components
== 4);
4470 Builder
bld(ctx
->program
, ctx
->block
);
4471 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4474 for (Operand
& op
: vec
->operands
)
4475 op
= op
.isUndefined() ? Operand(0u) : op
;
4477 vec
->definitions
[0] = Definition(dst
);
4478 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4479 emit_split_vector(ctx
, dst
, num_components
);
4483 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4485 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4486 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4487 unsigned idx
= nir_intrinsic_base(instr
);
4488 unsigned component
= nir_intrinsic_component(instr
);
4489 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4491 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4493 assert(offset
->u32
== 0);
4495 /* the lower 15bit of the prim_mask contain the offset into LDS
4496 * while the upper bits contain the number of prims */
4497 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4498 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4499 Builder
bld(ctx
->program
, ctx
->block
);
4500 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4501 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4502 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4503 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4504 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4507 if (instr
->dest
.ssa
.num_components
== 1) {
4508 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4510 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4511 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4513 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4514 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4515 vec
->operands
[i
] = Operand(tmp
);
4517 vec
->definitions
[0] = Definition(dst
);
4518 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4522 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4523 unsigned offset
, unsigned stride
, unsigned channels
)
4525 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4526 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4528 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4529 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4532 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4533 unsigned offset
, unsigned stride
, unsigned *channels
)
4535 if (!vtx_info
->chan_byte_size
) {
4536 *channels
= vtx_info
->num_channels
;
4537 return vtx_info
->chan_format
;
4540 unsigned num_channels
= *channels
;
4541 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4542 unsigned new_channels
= num_channels
+ 1;
4543 /* first, assume more loads is worse and try using a larger data format */
4544 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4546 /* don't make the attribute potentially out-of-bounds */
4547 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4551 if (new_channels
== 5) {
4552 /* then try decreasing load size (at the cost of more loads) */
4553 new_channels
= *channels
;
4554 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4558 if (new_channels
< *channels
)
4559 *channels
= new_channels
;
4560 num_channels
= new_channels
;
4563 switch (vtx_info
->chan_format
) {
4564 case V_008F0C_BUF_DATA_FORMAT_8
:
4565 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4566 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4567 case V_008F0C_BUF_DATA_FORMAT_16
:
4568 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4569 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4570 case V_008F0C_BUF_DATA_FORMAT_32
:
4571 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4572 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4574 unreachable("shouldn't reach here");
4575 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4578 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4579 * so we may need to fix it up. */
4580 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4582 Builder
bld(ctx
->program
, ctx
->block
);
4584 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4585 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4587 /* For the integer-like cases, do a natural sign extension.
4589 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4590 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4593 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4594 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4596 /* Convert back to the right type. */
4597 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4598 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4599 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4600 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4601 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4602 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4608 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4610 Builder
bld(ctx
->program
, ctx
->block
);
4611 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4612 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4614 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4615 if (off_instr
->type
!= nir_instr_type_load_const
) {
4616 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4617 nir_print_instr(off_instr
, stderr
);
4618 fprintf(stderr
, "\n");
4620 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4622 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4624 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4625 unsigned component
= nir_intrinsic_component(instr
);
4626 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4627 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4628 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4629 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4630 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4632 unsigned dfmt
= attrib_format
& 0xf;
4633 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4634 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4636 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4637 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4638 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4639 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4641 num_channels
= MAX2(num_channels
, 3);
4643 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4644 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4647 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4648 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4649 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4651 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4653 Temp divided
= bld
.tmp(v1
);
4654 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4655 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4657 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4660 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4663 index
= bld
.vadd32(bld
.def(v1
),
4664 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4665 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4668 Temp channels
[num_channels
];
4669 unsigned channel_start
= 0;
4670 bool direct_fetch
= false;
4672 /* skip unused channels at the start */
4673 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4674 channel_start
= ffs(mask
) - 1;
4675 for (unsigned i
= 0; i
< channel_start
; i
++)
4676 channels
[i
] = Temp(0, s1
);
4677 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4678 num_channels
= 3 - (ffs(mask
) - 1);
4682 while (channel_start
< num_channels
) {
4683 unsigned fetch_component
= num_channels
- channel_start
;
4684 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4685 bool expanded
= false;
4687 /* use MUBUF when possible to avoid possible alignment issues */
4688 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4689 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4690 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4691 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4692 vtx_info
->chan_byte_size
== 4;
4693 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4695 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4697 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4698 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4699 fetch_component
= 4;
4704 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4706 Temp fetch_index
= index
;
4707 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4708 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4709 fetch_offset
= fetch_offset
% attrib_stride
;
4712 Operand
soffset(0u);
4713 if (fetch_offset
>= 4096) {
4714 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4715 fetch_offset
%= 4096;
4719 switch (fetch_bytes
) {
4721 assert(!use_mubuf
&& bitsize
== 16);
4722 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4725 if (bitsize
== 16) {
4727 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4729 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4733 assert(!use_mubuf
&& bitsize
== 16);
4734 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4737 if (bitsize
== 16) {
4739 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4741 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4745 assert(ctx
->options
->chip_class
>= GFX7
||
4746 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4747 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4750 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4753 unreachable("Unimplemented load_input vector size");
4757 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4758 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4759 num_channels
<= 3)) {
4760 direct_fetch
= true;
4763 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4767 Instruction
*mubuf
= bld
.mubuf(opcode
,
4768 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4769 fetch_offset
, false, true).instr
;
4770 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4772 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4773 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4774 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4775 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4778 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4780 if (fetch_component
== 1) {
4781 channels
[channel_start
] = fetch_dst
;
4783 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4784 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4785 bitsize
== 16 ? v2b
: v1
);
4788 channel_start
+= fetch_component
;
4791 if (!direct_fetch
) {
4792 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4793 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4795 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4796 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4797 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4799 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4800 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4801 unsigned num_temp
= 0;
4802 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4803 unsigned idx
= i
+ component
;
4804 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4805 Temp channel
= channels
[swizzle
[idx
]];
4806 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4807 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4808 vec
->operands
[i
] = Operand(channel
);
4812 } else if (is_float
&& idx
== 3) {
4813 vec
->operands
[i
] = Operand(0x3f800000u
);
4814 } else if (!is_float
&& idx
== 3) {
4815 vec
->operands
[i
] = Operand(1u);
4817 vec
->operands
[i
] = Operand(0u);
4820 vec
->definitions
[0] = Definition(dst
);
4821 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4822 emit_split_vector(ctx
, dst
, dst
.size());
4824 if (num_temp
== dst
.size())
4825 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4827 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4828 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4829 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4830 if (off_instr
->type
!= nir_instr_type_load_const
||
4831 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4832 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4833 nir_print_instr(off_instr
, stderr
);
4834 fprintf(stderr
, "\n");
4837 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4838 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4840 assert(offset
->u32
== 0);
4842 /* the lower 15bit of the prim_mask contain the offset into LDS
4843 * while the upper bits contain the number of prims */
4844 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4845 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4846 Builder
bld(ctx
->program
, ctx
->block
);
4847 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4848 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4849 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4850 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4851 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4854 unsigned idx
= nir_intrinsic_base(instr
);
4855 unsigned component
= nir_intrinsic_component(instr
);
4856 unsigned vertex_id
= 2; /* P0 */
4858 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4859 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4860 switch (src0
->u32
) {
4862 vertex_id
= 2; /* P0 */
4865 vertex_id
= 0; /* P10 */
4868 vertex_id
= 1; /* P20 */
4871 unreachable("invalid vertex index");
4875 if (dst
.size() == 1) {
4876 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4878 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4879 for (unsigned i
= 0; i
< dst
.size(); i
++)
4880 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4881 vec
->definitions
[0] = Definition(dst
);
4882 bld
.insert(std::move(vec
));
4885 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4886 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4887 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4888 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4889 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4891 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4893 unreachable("Shader stage not implemented");
4897 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4899 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4901 Builder
bld(ctx
->program
, ctx
->block
);
4902 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4905 if (!nir_src_is_const(*vertex_src
)) {
4906 /* better code could be created, but this case probably doesn't happen
4907 * much in practice */
4908 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4909 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4912 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4913 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4915 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4917 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4920 if (vertex_offset
.id()) {
4921 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4922 Operand(i
), indirect_vertex
);
4923 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4925 vertex_offset
= elem
;
4929 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4930 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4932 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4933 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4934 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4935 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4936 Operand((vertex
% 2u) * 16u), Operand(16u));
4938 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4941 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4942 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4943 return offset_mul(ctx
, offs
, 4u);
4946 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4948 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4950 Builder
bld(ctx
->program
, ctx
->block
);
4951 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4952 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4954 if (ctx
->stage
== geometry_gs
) {
4955 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4956 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4957 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4958 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4959 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4960 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4961 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4963 unreachable("Unsupported GS stage.");
4967 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4969 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4971 Builder
bld(ctx
->program
, ctx
->block
);
4972 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4974 if (load_input_from_temps(ctx
, instr
, dst
))
4977 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4978 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4979 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4981 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4984 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4986 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4988 Builder
bld(ctx
->program
, ctx
->block
);
4990 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4991 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4992 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4994 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4995 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4997 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5000 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5002 switch (ctx
->shader
->info
.stage
) {
5003 case MESA_SHADER_GEOMETRY
:
5004 visit_load_gs_per_vertex_input(ctx
, instr
);
5006 case MESA_SHADER_TESS_CTRL
:
5007 visit_load_tcs_per_vertex_input(ctx
, instr
);
5009 case MESA_SHADER_TESS_EVAL
:
5010 visit_load_tes_per_vertex_input(ctx
, instr
);
5013 unreachable("Unimplemented shader stage");
5017 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5019 visit_load_tcs_output(ctx
, instr
, true);
5022 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5024 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5025 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5027 visit_store_tcs_output(ctx
, instr
, true);
5030 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5032 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5034 Builder
bld(ctx
->program
, ctx
->block
);
5035 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5037 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5038 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5041 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5042 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5043 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5044 tes_w
= Operand(tmp
);
5047 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5048 emit_split_vector(ctx
, tess_coord
, 3);
5051 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5053 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5054 Builder
bld(ctx
->program
, ctx
->block
);
5055 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5056 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5057 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5060 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5064 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5066 Builder
bld(ctx
->program
, ctx
->block
);
5067 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5068 if (!nir_dest_is_divergent(instr
->dest
))
5069 index
= bld
.as_uniform(index
);
5070 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5071 unsigned binding
= nir_intrinsic_binding(instr
);
5074 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5075 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5076 unsigned offset
= layout
->binding
[binding
].offset
;
5078 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5079 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5080 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5081 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5082 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5085 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5086 stride
= layout
->binding
[binding
].size
;
5089 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5090 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5092 if (nir_const_index
) {
5093 const_index
= const_index
* stride
;
5094 } else if (index
.type() == RegType::vgpr
) {
5095 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5096 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5098 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5102 if (nir_const_index
) {
5103 const_index
= const_index
+ offset
;
5104 } else if (index
.type() == RegType::vgpr
) {
5105 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5107 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5111 if (nir_const_index
&& const_index
== 0) {
5113 } else if (index
.type() == RegType::vgpr
) {
5114 index
= bld
.vadd32(bld
.def(v1
),
5115 nir_const_index
? Operand(const_index
) : Operand(index
),
5118 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5119 nir_const_index
? Operand(const_index
) : Operand(index
),
5123 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5126 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5127 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5128 bool glc
=false, bool readonly
=true)
5130 Builder
bld(ctx
->program
, ctx
->block
);
5132 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5134 offset
= bld
.as_uniform(offset
);
5136 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5138 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5139 info
.can_reorder
= readonly
;
5140 info
.align_mul
= align_mul
;
5141 info
.align_offset
= align_offset
;
5143 emit_smem_load(ctx
, bld
, &info
);
5145 emit_mubuf_load(ctx
, bld
, &info
);
5148 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5150 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5151 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5153 Builder
bld(ctx
->program
, ctx
->block
);
5155 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5156 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5157 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5158 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5160 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5161 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5165 if (ctx
->options
->chip_class
>= GFX10
) {
5166 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5167 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5168 S_008F0C_RESOURCE_LEVEL(1);
5170 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5171 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5173 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5174 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5175 Operand(0xFFFFFFFFu
),
5176 Operand(desc_type
));
5177 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5178 rsrc
, upper_dwords
);
5180 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5181 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5183 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5184 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5185 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5188 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5190 Builder
bld(ctx
->program
, ctx
->block
);
5191 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5192 unsigned offset
= nir_intrinsic_base(instr
);
5193 unsigned count
= instr
->dest
.ssa
.num_components
;
5194 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5196 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5197 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5198 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5199 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5200 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5201 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5202 for (unsigned i
= 0; i
< count
; ++i
) {
5203 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5204 vec
->operands
[i
] = Operand
{elems
[i
]};
5206 vec
->definitions
[0] = Definition(dst
);
5207 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5208 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5213 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5214 if (offset
!= 0) // TODO check if index != 0 as well
5215 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5216 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5219 bool aligned
= true;
5221 if (instr
->dest
.ssa
.bit_size
== 8) {
5222 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5223 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5225 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5226 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5227 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5229 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5234 switch (vec
.size()) {
5236 op
= aco_opcode::s_load_dword
;
5239 op
= aco_opcode::s_load_dwordx2
;
5245 op
= aco_opcode::s_load_dwordx4
;
5251 op
= aco_opcode::s_load_dwordx8
;
5254 unreachable("unimplemented or forbidden load_push_constant.");
5257 bld
.smem(op
, Definition(vec
), ptr
, index
);
5260 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5261 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5266 emit_split_vector(ctx
, vec
, 4);
5267 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5268 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5269 emit_extract_vector(ctx
, vec
, 0, rc
),
5270 emit_extract_vector(ctx
, vec
, 1, rc
),
5271 emit_extract_vector(ctx
, vec
, 2, rc
));
5274 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5277 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5279 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5281 Builder
bld(ctx
->program
, ctx
->block
);
5283 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5287 if (ctx
->options
->chip_class
>= GFX10
) {
5288 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5289 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5290 S_008F0C_RESOURCE_LEVEL(1);
5292 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5293 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5296 unsigned base
= nir_intrinsic_base(instr
);
5297 unsigned range
= nir_intrinsic_range(instr
);
5299 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5300 if (base
&& offset
.type() == RegType::sgpr
)
5301 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5302 else if (base
&& offset
.type() == RegType::vgpr
)
5303 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5305 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5306 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5307 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5308 Operand(desc_type
));
5309 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5310 // TODO: get alignment information for subdword constants
5311 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5314 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5316 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5317 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5319 ctx
->program
->needs_exact
= true;
5321 // TODO: optimize uniform conditions
5322 Builder
bld(ctx
->program
, ctx
->block
);
5323 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5324 assert(src
.regClass() == bld
.lm
);
5325 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5326 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5327 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5331 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5333 Builder
bld(ctx
->program
, ctx
->block
);
5335 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5336 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5338 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5339 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5341 if (ctx
->block
->loop_nest_depth
&&
5342 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5343 /* we handle discards the same way as jump instructions */
5344 append_logical_end(ctx
->block
);
5346 /* in loops, discard behaves like break */
5347 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5348 ctx
->block
->kind
|= block_kind_discard
;
5351 /* uniform discard - loop ends here */
5352 assert(nir_instr_is_last(&instr
->instr
));
5353 ctx
->block
->kind
|= block_kind_uniform
;
5354 ctx
->cf_info
.has_branch
= true;
5355 bld
.branch(aco_opcode::p_branch
);
5356 add_linear_edge(ctx
->block
->index
, linear_target
);
5360 /* we add a break right behind the discard() instructions */
5361 ctx
->block
->kind
|= block_kind_break
;
5362 unsigned idx
= ctx
->block
->index
;
5364 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5365 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5367 /* remove critical edges from linear CFG */
5368 bld
.branch(aco_opcode::p_branch
);
5369 Block
* break_block
= ctx
->program
->create_and_insert_block();
5370 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5371 break_block
->kind
|= block_kind_uniform
;
5372 add_linear_edge(idx
, break_block
);
5373 add_linear_edge(break_block
->index
, linear_target
);
5374 bld
.reset(break_block
);
5375 bld
.branch(aco_opcode::p_branch
);
5377 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5378 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5379 add_linear_edge(idx
, continue_block
);
5380 append_logical_start(continue_block
);
5381 ctx
->block
= continue_block
;
5386 /* it can currently happen that NIR doesn't remove the unreachable code */
5387 if (!nir_instr_is_last(&instr
->instr
)) {
5388 ctx
->program
->needs_exact
= true;
5389 /* save exec somewhere temporarily so that it doesn't get
5390 * overwritten before the discard from outer exec masks */
5391 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5392 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5393 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5397 /* This condition is incorrect for uniformly branched discards in a loop
5398 * predicated by a divergent condition, but the above code catches that case
5399 * and the discard would end up turning into a discard_if.
5409 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5410 /* program just ends here */
5411 ctx
->block
->kind
|= block_kind_uniform
;
5412 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5413 0 /* enabled mask */, 9 /* dest */,
5414 false /* compressed */, true/* done */, true /* valid mask */);
5415 bld
.sopp(aco_opcode::s_endpgm
);
5416 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5418 ctx
->block
->kind
|= block_kind_discard
;
5419 /* branch and linear edge is added by visit_if() */
5423 enum aco_descriptor_type
{
5434 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5435 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5437 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5438 return dim
== ac_image_cube
||
5439 dim
== ac_image_1darray
||
5440 dim
== ac_image_2darray
||
5441 dim
== ac_image_2darraymsaa
;
5444 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5445 enum aco_descriptor_type desc_type
,
5446 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5448 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5449 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5450 if (it != ctx->tex_desc.end())
5453 Temp index
= Temp();
5454 bool index_set
= false;
5455 unsigned constant_index
= 0;
5456 unsigned descriptor_set
;
5457 unsigned base_index
;
5458 Builder
bld(ctx
->program
, ctx
->block
);
5461 assert(tex_instr
&& !image
);
5463 base_index
= tex_instr
->sampler_index
;
5465 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5466 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5470 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5471 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5473 constant_index
+= array_size
* const_value
->u32
;
5475 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5476 if (indirect
.type() == RegType::vgpr
)
5477 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5479 if (array_size
!= 1)
5480 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5486 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5490 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5492 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5493 base_index
= deref_instr
->var
->data
.binding
;
5496 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5497 list
= convert_pointer_to_64_bit(ctx
, list
);
5499 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5500 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5501 unsigned offset
= binding
->offset
;
5502 unsigned stride
= binding
->size
;
5506 assert(base_index
< layout
->binding_count
);
5508 switch (desc_type
) {
5509 case ACO_DESC_IMAGE
:
5511 opcode
= aco_opcode::s_load_dwordx8
;
5513 case ACO_DESC_FMASK
:
5515 opcode
= aco_opcode::s_load_dwordx8
;
5518 case ACO_DESC_SAMPLER
:
5520 opcode
= aco_opcode::s_load_dwordx4
;
5521 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5522 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5524 case ACO_DESC_BUFFER
:
5526 opcode
= aco_opcode::s_load_dwordx4
;
5528 case ACO_DESC_PLANE_0
:
5529 case ACO_DESC_PLANE_1
:
5531 opcode
= aco_opcode::s_load_dwordx8
;
5532 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5534 case ACO_DESC_PLANE_2
:
5536 opcode
= aco_opcode::s_load_dwordx4
;
5540 unreachable("invalid desc_type\n");
5543 offset
+= constant_index
* stride
;
5545 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5546 (!index_set
|| binding
->immutable_samplers_equal
)) {
5547 if (binding
->immutable_samplers_equal
)
5550 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5551 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5552 Operand(samplers
[constant_index
* 4 + 0]),
5553 Operand(samplers
[constant_index
* 4 + 1]),
5554 Operand(samplers
[constant_index
* 4 + 2]),
5555 Operand(samplers
[constant_index
* 4 + 3]));
5560 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5562 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5563 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5566 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5568 if (desc_type
== ACO_DESC_PLANE_2
) {
5570 for (unsigned i
= 0; i
< 8; i
++)
5571 components
[i
] = bld
.tmp(s1
);
5572 bld
.pseudo(aco_opcode::p_split_vector
,
5573 Definition(components
[0]),
5574 Definition(components
[1]),
5575 Definition(components
[2]),
5576 Definition(components
[3]),
5579 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5580 bld
.pseudo(aco_opcode::p_split_vector
,
5581 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5582 Definition(components
[4]),
5583 Definition(components
[5]),
5584 Definition(components
[6]),
5585 Definition(components
[7]),
5588 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5589 components
[0], components
[1], components
[2], components
[3],
5590 components
[4], components
[5], components
[6], components
[7]);
5596 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5599 case GLSL_SAMPLER_DIM_BUF
:
5601 case GLSL_SAMPLER_DIM_1D
:
5602 return array
? 2 : 1;
5603 case GLSL_SAMPLER_DIM_2D
:
5604 return array
? 3 : 2;
5605 case GLSL_SAMPLER_DIM_MS
:
5606 return array
? 4 : 3;
5607 case GLSL_SAMPLER_DIM_3D
:
5608 case GLSL_SAMPLER_DIM_CUBE
:
5610 case GLSL_SAMPLER_DIM_RECT
:
5611 case GLSL_SAMPLER_DIM_SUBPASS
:
5613 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5622 /* Adjust the sample index according to FMASK.
5624 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5625 * which is the identity mapping. Each nibble says which physical sample
5626 * should be fetched to get that sample.
5628 * For example, 0x11111100 means there are only 2 samples stored and
5629 * the second sample covers 3/4 of the pixel. When reading samples 0
5630 * and 1, return physical sample 0 (determined by the first two 0s
5631 * in FMASK), otherwise return physical sample 1.
5633 * The sample index should be adjusted as follows:
5634 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5636 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5638 Builder
bld(ctx
->program
, ctx
->block
);
5639 Temp fmask
= bld
.tmp(v1
);
5640 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5641 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5644 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5645 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5646 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5647 load
->operands
[0] = Operand(fmask_desc_ptr
);
5648 load
->operands
[1] = Operand(s4
); /* no sampler */
5649 load
->operands
[2] = Operand(coord
);
5650 load
->definitions
[0] = Definition(fmask
);
5657 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5658 ctx
->block
->instructions
.emplace_back(std::move(load
));
5660 Operand sample_index4
;
5661 if (sample_index
.isConstant()) {
5662 if (sample_index
.constantValue() < 16) {
5663 sample_index4
= Operand(sample_index
.constantValue() << 2);
5665 sample_index4
= Operand(0u);
5667 } else if (sample_index
.regClass() == s1
) {
5668 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5670 assert(sample_index
.regClass() == v1
);
5671 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5675 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5676 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5677 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5678 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5680 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5682 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5683 * resource descriptor is 0 (invalid),
5685 Temp compare
= bld
.tmp(bld
.lm
);
5686 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5687 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5689 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5691 /* Replace the MSAA sample index. */
5692 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5695 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5698 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5699 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5700 bool is_array
= glsl_sampler_type_is_array(type
);
5701 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5702 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5703 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5704 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5705 int count
= image_type_to_components_count(dim
, is_array
);
5706 std::vector
<Temp
> coords(count
);
5707 Builder
bld(ctx
->program
, ctx
->block
);
5711 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5712 /* get sample index */
5713 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5714 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5715 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5716 std::vector
<Temp
> fmask_load_address
;
5717 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5718 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5720 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5721 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5723 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5728 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5729 coords
.resize(coords
.size() + 1);
5730 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5732 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5734 for (int i
= 0; i
< count
; i
++)
5735 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5738 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5739 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5740 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5741 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5744 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5747 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5748 for (unsigned i
= 0; i
< coords
.size(); i
++)
5749 vec
->operands
[i
] = Operand(coords
[i
]);
5750 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5751 vec
->definitions
[0] = Definition(res
);
5752 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5757 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5759 Builder
bld(ctx
->program
, ctx
->block
);
5760 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5761 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5762 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5763 bool is_array
= glsl_sampler_type_is_array(type
);
5764 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5766 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5767 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5768 unsigned num_channels
= util_last_bit(mask
);
5769 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5770 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5773 switch (num_channels
) {
5775 opcode
= aco_opcode::buffer_load_format_x
;
5778 opcode
= aco_opcode::buffer_load_format_xy
;
5781 opcode
= aco_opcode::buffer_load_format_xyz
;
5784 opcode
= aco_opcode::buffer_load_format_xyzw
;
5787 unreachable(">4 channel buffer image load");
5789 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5790 load
->operands
[0] = Operand(rsrc
);
5791 load
->operands
[1] = Operand(vindex
);
5792 load
->operands
[2] = Operand((uint32_t) 0);
5794 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5797 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5798 load
->definitions
[0] = Definition(tmp
);
5800 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5801 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5802 load
->barrier
= barrier_image
;
5803 ctx
->block
->instructions
.emplace_back(std::move(load
));
5805 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5809 Temp coords
= get_image_coords(ctx
, instr
, type
);
5810 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5812 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5813 unsigned num_components
= util_bitcount(dmask
);
5815 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5818 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5820 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5821 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5823 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5824 load
->operands
[0] = Operand(resource
);
5825 load
->operands
[1] = Operand(s4
); /* no sampler */
5826 load
->operands
[2] = Operand(coords
);
5827 load
->definitions
[0] = Definition(tmp
);
5828 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5829 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5830 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5831 load
->dmask
= dmask
;
5833 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5834 load
->barrier
= barrier_image
;
5835 ctx
->block
->instructions
.emplace_back(std::move(load
));
5837 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5841 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5843 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5844 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5845 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5846 bool is_array
= glsl_sampler_type_is_array(type
);
5847 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5849 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5851 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5852 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5853 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5855 switch (data
.size()) {
5857 opcode
= aco_opcode::buffer_store_format_x
;
5860 opcode
= aco_opcode::buffer_store_format_xy
;
5863 opcode
= aco_opcode::buffer_store_format_xyz
;
5866 opcode
= aco_opcode::buffer_store_format_xyzw
;
5869 unreachable(">4 channel buffer image store");
5871 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5872 store
->operands
[0] = Operand(rsrc
);
5873 store
->operands
[1] = Operand(vindex
);
5874 store
->operands
[2] = Operand((uint32_t) 0);
5875 store
->operands
[3] = Operand(data
);
5876 store
->idxen
= true;
5879 store
->disable_wqm
= true;
5880 store
->barrier
= barrier_image
;
5881 ctx
->program
->needs_exact
= true;
5882 ctx
->block
->instructions
.emplace_back(std::move(store
));
5886 assert(data
.type() == RegType::vgpr
);
5887 Temp coords
= get_image_coords(ctx
, instr
, type
);
5888 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5890 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5891 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5893 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5894 store
->operands
[0] = Operand(resource
);
5895 store
->operands
[1] = Operand(data
);
5896 store
->operands
[2] = Operand(coords
);
5899 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5900 store
->dmask
= (1 << data
.size()) - 1;
5902 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5903 store
->disable_wqm
= true;
5904 store
->barrier
= barrier_image
;
5905 ctx
->program
->needs_exact
= true;
5906 ctx
->block
->instructions
.emplace_back(std::move(store
));
5910 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5912 /* return the previous value if dest is ever used */
5913 bool return_previous
= false;
5914 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5915 return_previous
= true;
5918 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5919 return_previous
= true;
5923 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5924 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5925 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5926 bool is_array
= glsl_sampler_type_is_array(type
);
5927 Builder
bld(ctx
->program
, ctx
->block
);
5929 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5930 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5932 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5933 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5935 aco_opcode buf_op
, image_op
;
5936 switch (instr
->intrinsic
) {
5937 case nir_intrinsic_image_deref_atomic_add
:
5938 buf_op
= aco_opcode::buffer_atomic_add
;
5939 image_op
= aco_opcode::image_atomic_add
;
5941 case nir_intrinsic_image_deref_atomic_umin
:
5942 buf_op
= aco_opcode::buffer_atomic_umin
;
5943 image_op
= aco_opcode::image_atomic_umin
;
5945 case nir_intrinsic_image_deref_atomic_imin
:
5946 buf_op
= aco_opcode::buffer_atomic_smin
;
5947 image_op
= aco_opcode::image_atomic_smin
;
5949 case nir_intrinsic_image_deref_atomic_umax
:
5950 buf_op
= aco_opcode::buffer_atomic_umax
;
5951 image_op
= aco_opcode::image_atomic_umax
;
5953 case nir_intrinsic_image_deref_atomic_imax
:
5954 buf_op
= aco_opcode::buffer_atomic_smax
;
5955 image_op
= aco_opcode::image_atomic_smax
;
5957 case nir_intrinsic_image_deref_atomic_and
:
5958 buf_op
= aco_opcode::buffer_atomic_and
;
5959 image_op
= aco_opcode::image_atomic_and
;
5961 case nir_intrinsic_image_deref_atomic_or
:
5962 buf_op
= aco_opcode::buffer_atomic_or
;
5963 image_op
= aco_opcode::image_atomic_or
;
5965 case nir_intrinsic_image_deref_atomic_xor
:
5966 buf_op
= aco_opcode::buffer_atomic_xor
;
5967 image_op
= aco_opcode::image_atomic_xor
;
5969 case nir_intrinsic_image_deref_atomic_exchange
:
5970 buf_op
= aco_opcode::buffer_atomic_swap
;
5971 image_op
= aco_opcode::image_atomic_swap
;
5973 case nir_intrinsic_image_deref_atomic_comp_swap
:
5974 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5975 image_op
= aco_opcode::image_atomic_cmpswap
;
5978 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5983 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5984 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5985 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5986 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5987 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5988 mubuf
->operands
[0] = Operand(resource
);
5989 mubuf
->operands
[1] = Operand(vindex
);
5990 mubuf
->operands
[2] = Operand((uint32_t)0);
5991 mubuf
->operands
[3] = Operand(data
);
5992 if (return_previous
)
5993 mubuf
->definitions
[0] = Definition(dst
);
5995 mubuf
->idxen
= true;
5996 mubuf
->glc
= return_previous
;
5997 mubuf
->dlc
= false; /* Not needed for atomics */
5998 mubuf
->disable_wqm
= true;
5999 mubuf
->barrier
= barrier_image
;
6000 ctx
->program
->needs_exact
= true;
6001 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6005 Temp coords
= get_image_coords(ctx
, instr
, type
);
6006 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6007 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6008 mimg
->operands
[0] = Operand(resource
);
6009 mimg
->operands
[1] = Operand(data
);
6010 mimg
->operands
[2] = Operand(coords
);
6011 if (return_previous
)
6012 mimg
->definitions
[0] = Definition(dst
);
6013 mimg
->glc
= return_previous
;
6014 mimg
->dlc
= false; /* Not needed for atomics */
6015 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6016 mimg
->dmask
= (1 << data
.size()) - 1;
6018 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6019 mimg
->disable_wqm
= true;
6020 mimg
->barrier
= barrier_image
;
6021 ctx
->program
->needs_exact
= true;
6022 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6026 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6028 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6029 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6030 Builder
bld(ctx
->program
, ctx
->block
);
6032 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6034 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6035 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6037 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6038 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6040 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6041 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6043 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6044 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6045 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6046 if (dst
.type() == RegType::vgpr
)
6047 bld
.copy(Definition(dst
), shr_dst
);
6049 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6051 emit_extract_vector(ctx
, desc
, 2, dst
);
6055 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6057 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6058 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6059 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6060 bool is_array
= glsl_sampler_type_is_array(type
);
6061 Builder
bld(ctx
->program
, ctx
->block
);
6063 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6064 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6065 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6069 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6072 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6074 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6076 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6077 mimg
->operands
[0] = Operand(resource
);
6078 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6079 mimg
->operands
[2] = Operand(lod
);
6080 uint8_t& dmask
= mimg
->dmask
;
6081 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6082 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6083 mimg
->da
= glsl_sampler_type_is_array(type
);
6084 mimg
->can_reorder
= true;
6085 Definition
& def
= mimg
->definitions
[0];
6086 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6088 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6089 glsl_sampler_type_is_array(type
)) {
6091 assert(instr
->dest
.ssa
.num_components
== 3);
6092 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6093 def
= Definition(tmp
);
6094 emit_split_vector(ctx
, tmp
, 3);
6096 /* divide 3rd value by 6 by multiplying with magic number */
6097 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6098 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6100 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6101 emit_extract_vector(ctx
, tmp
, 0, v1
),
6102 emit_extract_vector(ctx
, tmp
, 1, v1
),
6105 } else if (ctx
->options
->chip_class
== GFX9
&&
6106 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6107 glsl_sampler_type_is_array(type
)) {
6108 assert(instr
->dest
.ssa
.num_components
== 2);
6109 def
= Definition(dst
);
6112 def
= Definition(dst
);
6115 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6118 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6120 Builder
bld(ctx
->program
, ctx
->block
);
6121 unsigned num_components
= instr
->num_components
;
6123 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6124 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6125 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6127 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6128 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6129 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6130 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6133 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6135 Builder
bld(ctx
->program
, ctx
->block
);
6136 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6137 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6138 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6139 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6141 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6142 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6144 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6145 ctx
->options
->chip_class
>= GFX8
&&
6146 elem_size_bytes
>= 4;
6148 offset
= bld
.as_uniform(offset
);
6149 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6151 unsigned write_count
= 0;
6152 Temp write_datas
[32];
6153 unsigned offsets
[32];
6154 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6155 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6157 for (unsigned i
= 0; i
< write_count
; i
++) {
6158 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6159 if (smem
&& ctx
->stage
== fragment_fs
)
6160 op
= aco_opcode::p_fs_buffer_store_smem
;
6163 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6164 store
->operands
[0] = Operand(rsrc
);
6166 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6167 offset
, Operand(offsets
[i
]));
6168 store
->operands
[1] = Operand(off
);
6170 store
->operands
[1] = Operand(offset
);
6172 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6173 store
->operands
[1].setFixed(m0
);
6174 store
->operands
[2] = Operand(write_datas
[i
]);
6175 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6177 store
->disable_wqm
= true;
6178 store
->barrier
= barrier_buffer
;
6179 ctx
->block
->instructions
.emplace_back(std::move(store
));
6180 ctx
->program
->wb_smem_l1_on_end
= true;
6181 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6182 ctx
->block
->kind
|= block_kind_needs_lowering
;
6183 ctx
->program
->needs_exact
= true;
6186 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6187 store
->operands
[0] = Operand(rsrc
);
6188 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6189 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6190 store
->operands
[3] = Operand(write_datas
[i
]);
6191 store
->offset
= offsets
[i
];
6192 store
->offen
= (offset
.type() == RegType::vgpr
);
6193 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6195 store
->disable_wqm
= true;
6196 store
->barrier
= barrier_buffer
;
6197 ctx
->program
->needs_exact
= true;
6198 ctx
->block
->instructions
.emplace_back(std::move(store
));
6203 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6205 /* return the previous value if dest is ever used */
6206 bool return_previous
= false;
6207 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6208 return_previous
= true;
6211 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6212 return_previous
= true;
6216 Builder
bld(ctx
->program
, ctx
->block
);
6217 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6219 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6220 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6221 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6223 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6224 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6225 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6227 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6229 aco_opcode op32
, op64
;
6230 switch (instr
->intrinsic
) {
6231 case nir_intrinsic_ssbo_atomic_add
:
6232 op32
= aco_opcode::buffer_atomic_add
;
6233 op64
= aco_opcode::buffer_atomic_add_x2
;
6235 case nir_intrinsic_ssbo_atomic_imin
:
6236 op32
= aco_opcode::buffer_atomic_smin
;
6237 op64
= aco_opcode::buffer_atomic_smin_x2
;
6239 case nir_intrinsic_ssbo_atomic_umin
:
6240 op32
= aco_opcode::buffer_atomic_umin
;
6241 op64
= aco_opcode::buffer_atomic_umin_x2
;
6243 case nir_intrinsic_ssbo_atomic_imax
:
6244 op32
= aco_opcode::buffer_atomic_smax
;
6245 op64
= aco_opcode::buffer_atomic_smax_x2
;
6247 case nir_intrinsic_ssbo_atomic_umax
:
6248 op32
= aco_opcode::buffer_atomic_umax
;
6249 op64
= aco_opcode::buffer_atomic_umax_x2
;
6251 case nir_intrinsic_ssbo_atomic_and
:
6252 op32
= aco_opcode::buffer_atomic_and
;
6253 op64
= aco_opcode::buffer_atomic_and_x2
;
6255 case nir_intrinsic_ssbo_atomic_or
:
6256 op32
= aco_opcode::buffer_atomic_or
;
6257 op64
= aco_opcode::buffer_atomic_or_x2
;
6259 case nir_intrinsic_ssbo_atomic_xor
:
6260 op32
= aco_opcode::buffer_atomic_xor
;
6261 op64
= aco_opcode::buffer_atomic_xor_x2
;
6263 case nir_intrinsic_ssbo_atomic_exchange
:
6264 op32
= aco_opcode::buffer_atomic_swap
;
6265 op64
= aco_opcode::buffer_atomic_swap_x2
;
6267 case nir_intrinsic_ssbo_atomic_comp_swap
:
6268 op32
= aco_opcode::buffer_atomic_cmpswap
;
6269 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6272 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6274 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6275 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6276 mubuf
->operands
[0] = Operand(rsrc
);
6277 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6278 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6279 mubuf
->operands
[3] = Operand(data
);
6280 if (return_previous
)
6281 mubuf
->definitions
[0] = Definition(dst
);
6283 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6284 mubuf
->glc
= return_previous
;
6285 mubuf
->dlc
= false; /* Not needed for atomics */
6286 mubuf
->disable_wqm
= true;
6287 mubuf
->barrier
= barrier_buffer
;
6288 ctx
->program
->needs_exact
= true;
6289 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6292 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6294 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6295 Builder
bld(ctx
->program
, ctx
->block
);
6296 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6297 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6300 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6302 Builder
bld(ctx
->program
, ctx
->block
);
6303 unsigned num_components
= instr
->num_components
;
6304 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6306 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6307 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6308 num_components
, component_size
};
6309 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6310 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6311 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6312 info
.barrier
= barrier_buffer
;
6313 info
.can_reorder
= false;
6314 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6315 * it's safe to use SMEM */
6316 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6317 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6318 emit_global_load(ctx
, bld
, &info
);
6320 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6321 emit_smem_load(ctx
, bld
, &info
);
6325 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6327 Builder
bld(ctx
->program
, ctx
->block
);
6328 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6329 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6331 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6332 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6333 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6335 if (ctx
->options
->chip_class
>= GFX7
)
6336 addr
= as_vgpr(ctx
, addr
);
6338 unsigned write_count
= 0;
6339 Temp write_datas
[32];
6340 unsigned offsets
[32];
6341 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6342 16, &write_count
, write_datas
, offsets
);
6344 for (unsigned i
= 0; i
< write_count
; i
++) {
6345 if (ctx
->options
->chip_class
>= GFX7
) {
6346 unsigned offset
= offsets
[i
];
6347 Temp store_addr
= addr
;
6348 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6349 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6350 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6351 Temp carry
= bld
.tmp(bld
.lm
);
6352 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6354 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6355 Operand(offset
), addr0
);
6356 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6358 carry
).def(1).setHint(vcc
);
6360 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6365 bool global
= ctx
->options
->chip_class
>= GFX9
;
6367 switch (write_datas
[i
].bytes()) {
6369 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6372 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6375 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6378 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6381 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6384 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6387 unreachable("store_global not implemented for this size.");
6390 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6391 flat
->operands
[0] = Operand(store_addr
);
6392 flat
->operands
[1] = Operand(s1
);
6393 flat
->operands
[2] = Operand(write_datas
[i
]);
6396 flat
->offset
= offset
;
6397 flat
->disable_wqm
= true;
6398 flat
->barrier
= barrier_buffer
;
6399 ctx
->program
->needs_exact
= true;
6400 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6402 assert(ctx
->options
->chip_class
== GFX6
);
6404 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6406 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6408 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6409 mubuf
->operands
[0] = Operand(rsrc
);
6410 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6411 mubuf
->operands
[2] = Operand(0u);
6412 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6415 mubuf
->offset
= offsets
[i
];
6416 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6417 mubuf
->disable_wqm
= true;
6418 mubuf
->barrier
= barrier_buffer
;
6419 ctx
->program
->needs_exact
= true;
6420 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6425 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6427 /* return the previous value if dest is ever used */
6428 bool return_previous
= false;
6429 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6430 return_previous
= true;
6433 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6434 return_previous
= true;
6438 Builder
bld(ctx
->program
, ctx
->block
);
6439 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6440 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6442 if (ctx
->options
->chip_class
>= GFX7
)
6443 addr
= as_vgpr(ctx
, addr
);
6445 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6446 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6447 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6449 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6451 aco_opcode op32
, op64
;
6453 if (ctx
->options
->chip_class
>= GFX7
) {
6454 bool global
= ctx
->options
->chip_class
>= GFX9
;
6455 switch (instr
->intrinsic
) {
6456 case nir_intrinsic_global_atomic_add
:
6457 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6458 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6460 case nir_intrinsic_global_atomic_imin
:
6461 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6462 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6464 case nir_intrinsic_global_atomic_umin
:
6465 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6466 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6468 case nir_intrinsic_global_atomic_imax
:
6469 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6470 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6472 case nir_intrinsic_global_atomic_umax
:
6473 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6474 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6476 case nir_intrinsic_global_atomic_and
:
6477 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6478 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6480 case nir_intrinsic_global_atomic_or
:
6481 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6482 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6484 case nir_intrinsic_global_atomic_xor
:
6485 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6486 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6488 case nir_intrinsic_global_atomic_exchange
:
6489 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6490 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6492 case nir_intrinsic_global_atomic_comp_swap
:
6493 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6494 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6497 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6500 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6501 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6502 flat
->operands
[0] = Operand(addr
);
6503 flat
->operands
[1] = Operand(s1
);
6504 flat
->operands
[2] = Operand(data
);
6505 if (return_previous
)
6506 flat
->definitions
[0] = Definition(dst
);
6507 flat
->glc
= return_previous
;
6508 flat
->dlc
= false; /* Not needed for atomics */
6510 flat
->disable_wqm
= true;
6511 flat
->barrier
= barrier_buffer
;
6512 ctx
->program
->needs_exact
= true;
6513 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6515 assert(ctx
->options
->chip_class
== GFX6
);
6517 switch (instr
->intrinsic
) {
6518 case nir_intrinsic_global_atomic_add
:
6519 op32
= aco_opcode::buffer_atomic_add
;
6520 op64
= aco_opcode::buffer_atomic_add_x2
;
6522 case nir_intrinsic_global_atomic_imin
:
6523 op32
= aco_opcode::buffer_atomic_smin
;
6524 op64
= aco_opcode::buffer_atomic_smin_x2
;
6526 case nir_intrinsic_global_atomic_umin
:
6527 op32
= aco_opcode::buffer_atomic_umin
;
6528 op64
= aco_opcode::buffer_atomic_umin_x2
;
6530 case nir_intrinsic_global_atomic_imax
:
6531 op32
= aco_opcode::buffer_atomic_smax
;
6532 op64
= aco_opcode::buffer_atomic_smax_x2
;
6534 case nir_intrinsic_global_atomic_umax
:
6535 op32
= aco_opcode::buffer_atomic_umax
;
6536 op64
= aco_opcode::buffer_atomic_umax_x2
;
6538 case nir_intrinsic_global_atomic_and
:
6539 op32
= aco_opcode::buffer_atomic_and
;
6540 op64
= aco_opcode::buffer_atomic_and_x2
;
6542 case nir_intrinsic_global_atomic_or
:
6543 op32
= aco_opcode::buffer_atomic_or
;
6544 op64
= aco_opcode::buffer_atomic_or_x2
;
6546 case nir_intrinsic_global_atomic_xor
:
6547 op32
= aco_opcode::buffer_atomic_xor
;
6548 op64
= aco_opcode::buffer_atomic_xor_x2
;
6550 case nir_intrinsic_global_atomic_exchange
:
6551 op32
= aco_opcode::buffer_atomic_swap
;
6552 op64
= aco_opcode::buffer_atomic_swap_x2
;
6554 case nir_intrinsic_global_atomic_comp_swap
:
6555 op32
= aco_opcode::buffer_atomic_cmpswap
;
6556 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6559 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6562 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6564 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6566 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6567 mubuf
->operands
[0] = Operand(rsrc
);
6568 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6569 mubuf
->operands
[2] = Operand(0u);
6570 mubuf
->operands
[3] = Operand(data
);
6571 if (return_previous
)
6572 mubuf
->definitions
[0] = Definition(dst
);
6573 mubuf
->glc
= return_previous
;
6576 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6577 mubuf
->disable_wqm
= true;
6578 mubuf
->barrier
= barrier_buffer
;
6579 ctx
->program
->needs_exact
= true;
6580 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6584 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6585 Builder
bld(ctx
->program
, ctx
->block
);
6586 switch(instr
->intrinsic
) {
6587 case nir_intrinsic_group_memory_barrier
:
6588 case nir_intrinsic_memory_barrier
:
6589 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6591 case nir_intrinsic_memory_barrier_buffer
:
6592 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6594 case nir_intrinsic_memory_barrier_image
:
6595 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6597 case nir_intrinsic_memory_barrier_tcs_patch
:
6598 case nir_intrinsic_memory_barrier_shared
:
6599 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6602 unreachable("Unimplemented memory barrier intrinsic");
6607 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6609 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6610 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6611 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6612 Builder
bld(ctx
->program
, ctx
->block
);
6614 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6615 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6616 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6619 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6621 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6622 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6623 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6624 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6626 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6627 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6630 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6632 unsigned offset
= nir_intrinsic_base(instr
);
6633 Builder
bld(ctx
->program
, ctx
->block
);
6634 Operand m
= load_lds_size_m0(bld
);
6635 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6636 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6638 unsigned num_operands
= 3;
6639 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6640 switch(instr
->intrinsic
) {
6641 case nir_intrinsic_shared_atomic_add
:
6642 op32
= aco_opcode::ds_add_u32
;
6643 op64
= aco_opcode::ds_add_u64
;
6644 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6645 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6647 case nir_intrinsic_shared_atomic_imin
:
6648 op32
= aco_opcode::ds_min_i32
;
6649 op64
= aco_opcode::ds_min_i64
;
6650 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6651 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6653 case nir_intrinsic_shared_atomic_umin
:
6654 op32
= aco_opcode::ds_min_u32
;
6655 op64
= aco_opcode::ds_min_u64
;
6656 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6657 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6659 case nir_intrinsic_shared_atomic_imax
:
6660 op32
= aco_opcode::ds_max_i32
;
6661 op64
= aco_opcode::ds_max_i64
;
6662 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6663 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6665 case nir_intrinsic_shared_atomic_umax
:
6666 op32
= aco_opcode::ds_max_u32
;
6667 op64
= aco_opcode::ds_max_u64
;
6668 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6669 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6671 case nir_intrinsic_shared_atomic_and
:
6672 op32
= aco_opcode::ds_and_b32
;
6673 op64
= aco_opcode::ds_and_b64
;
6674 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6675 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6677 case nir_intrinsic_shared_atomic_or
:
6678 op32
= aco_opcode::ds_or_b32
;
6679 op64
= aco_opcode::ds_or_b64
;
6680 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6681 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6683 case nir_intrinsic_shared_atomic_xor
:
6684 op32
= aco_opcode::ds_xor_b32
;
6685 op64
= aco_opcode::ds_xor_b64
;
6686 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6687 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6689 case nir_intrinsic_shared_atomic_exchange
:
6690 op32
= aco_opcode::ds_write_b32
;
6691 op64
= aco_opcode::ds_write_b64
;
6692 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6693 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6695 case nir_intrinsic_shared_atomic_comp_swap
:
6696 op32
= aco_opcode::ds_cmpst_b32
;
6697 op64
= aco_opcode::ds_cmpst_b64
;
6698 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6699 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6703 unreachable("Unhandled shared atomic intrinsic");
6706 /* return the previous value if dest is ever used */
6707 bool return_previous
= false;
6708 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6709 return_previous
= true;
6712 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6713 return_previous
= true;
6718 if (data
.size() == 1) {
6719 assert(instr
->dest
.ssa
.bit_size
== 32);
6720 op
= return_previous
? op32_rtn
: op32
;
6722 assert(instr
->dest
.ssa
.bit_size
== 64);
6723 op
= return_previous
? op64_rtn
: op64
;
6726 if (offset
> 65535) {
6727 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6731 aco_ptr
<DS_instruction
> ds
;
6732 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6733 ds
->operands
[0] = Operand(address
);
6734 ds
->operands
[1] = Operand(data
);
6735 if (num_operands
== 4)
6736 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6737 ds
->operands
[num_operands
- 1] = m
;
6738 ds
->offset0
= offset
;
6739 if (return_previous
)
6740 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6741 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6744 Temp
get_scratch_resource(isel_context
*ctx
)
6746 Builder
bld(ctx
->program
, ctx
->block
);
6747 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6748 if (ctx
->stage
!= compute_cs
)
6749 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6751 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6752 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6754 if (ctx
->program
->chip_class
>= GFX10
) {
6755 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6756 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6757 S_008F0C_RESOURCE_LEVEL(1);
6758 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6759 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6760 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6763 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6764 if (ctx
->program
->chip_class
<= GFX8
)
6765 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6767 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6770 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6771 Builder
bld(ctx
->program
, ctx
->block
);
6772 Temp rsrc
= get_scratch_resource(ctx
);
6773 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6774 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6776 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6777 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6778 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6779 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6780 info
.swizzle_component_size
= 16;
6781 info
.can_reorder
= false;
6782 info
.soffset
= ctx
->program
->scratch_offset
;
6783 emit_mubuf_load(ctx
, bld
, &info
);
6786 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6787 Builder
bld(ctx
->program
, ctx
->block
);
6788 Temp rsrc
= get_scratch_resource(ctx
);
6789 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6790 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6792 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6793 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6795 unsigned write_count
= 0;
6796 Temp write_datas
[32];
6797 unsigned offsets
[32];
6798 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6799 16, &write_count
, write_datas
, offsets
);
6801 for (unsigned i
= 0; i
< write_count
; i
++) {
6802 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6803 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6807 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6808 uint8_t log2_ps_iter_samples
;
6809 if (ctx
->program
->info
->ps
.force_persample
) {
6810 log2_ps_iter_samples
=
6811 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6813 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6816 /* The bit pattern matches that used by fixed function fragment
6818 static const unsigned ps_iter_masks
[] = {
6819 0xffff, /* not used */
6825 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6827 Builder
bld(ctx
->program
, ctx
->block
);
6829 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6830 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6831 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6832 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6833 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6834 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6837 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6838 Builder
bld(ctx
->program
, ctx
->block
);
6840 unsigned stream
= nir_intrinsic_stream_id(instr
);
6841 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6842 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6843 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6846 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6848 unsigned num_components
=
6849 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6850 assert(num_components
);
6852 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6853 unsigned stream_offset
= 0;
6854 for (unsigned i
= 0; i
< stream
; i
++) {
6855 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6856 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6859 /* Limit on the stride field for <= GFX7. */
6860 assert(stride
< (1 << 14));
6862 Temp gsvs_dwords
[4];
6863 for (unsigned i
= 0; i
< 4; i
++)
6864 gsvs_dwords
[i
] = bld
.tmp(s1
);
6865 bld
.pseudo(aco_opcode::p_split_vector
,
6866 Definition(gsvs_dwords
[0]),
6867 Definition(gsvs_dwords
[1]),
6868 Definition(gsvs_dwords
[2]),
6869 Definition(gsvs_dwords
[3]),
6872 if (stream_offset
) {
6873 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6875 Temp carry
= bld
.tmp(s1
);
6876 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6877 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6880 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6881 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6883 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6884 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6886 unsigned offset
= 0;
6887 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6888 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6891 for (unsigned j
= 0; j
< 4; j
++) {
6892 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6895 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6896 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6897 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6898 if (const_offset
>= 4096u) {
6899 if (vaddr_offset
.isUndefined())
6900 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6902 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6903 const_offset
%= 4096u;
6906 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6907 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6908 mtbuf
->operands
[1] = vaddr_offset
;
6909 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6910 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6911 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6912 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6913 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6914 mtbuf
->offset
= const_offset
;
6917 mtbuf
->barrier
= barrier_gs_data
;
6918 mtbuf
->can_reorder
= true;
6919 bld
.insert(std::move(mtbuf
));
6922 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6925 /* outputs for the next vertex are undefined and keeping them around can
6926 * create invalid IR with control flow */
6927 ctx
->outputs
.mask
[i
] = 0;
6930 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6933 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6935 Builder
bld(ctx
->program
, ctx
->block
);
6937 if (cluster_size
== 1) {
6939 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6940 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6941 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6942 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6943 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6944 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6945 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6946 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6947 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6948 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6949 //subgroupAnd(val) -> (exec & ~val) == 0
6950 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6951 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6952 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6953 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6954 //subgroupOr(val) -> (val & exec) != 0
6955 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6956 return bool_to_vector_condition(ctx
, tmp
);
6957 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6958 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6959 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6960 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6961 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6962 return bool_to_vector_condition(ctx
, tmp
);
6964 //subgroupClustered{And,Or,Xor}(val, n) ->
6965 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6966 //cluster_offset = ~(n - 1) & lane_id
6967 //cluster_mask = ((1 << n) - 1)
6968 //subgroupClusteredAnd():
6969 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6970 //subgroupClusteredOr():
6971 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6972 //subgroupClusteredXor():
6973 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6974 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6975 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6978 if (op
== nir_op_iand
)
6979 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6981 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6983 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6985 if (ctx
->program
->chip_class
<= GFX7
)
6986 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6987 else if (ctx
->program
->wave_size
== 64)
6988 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6990 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6991 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6992 if (cluster_mask
!= 0xffffffff)
6993 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6995 Definition cmp_def
= Definition();
6996 if (op
== nir_op_iand
) {
6997 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6998 } else if (op
== nir_op_ior
) {
6999 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7000 } else if (op
== nir_op_ixor
) {
7001 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7002 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7003 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7005 cmp_def
.setHint(vcc
);
7006 return cmp_def
.getTemp();
7010 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7012 Builder
bld(ctx
->program
, ctx
->block
);
7014 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7015 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7016 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7018 if (op
== nir_op_iand
)
7019 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7021 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7023 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7024 Temp lo
= lohi
.def(0).getTemp();
7025 Temp hi
= lohi
.def(1).getTemp();
7026 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7028 Definition cmp_def
= Definition();
7029 if (op
== nir_op_iand
)
7030 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7031 else if (op
== nir_op_ior
)
7032 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7033 else if (op
== nir_op_ixor
)
7034 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7035 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7036 cmp_def
.setHint(vcc
);
7037 return cmp_def
.getTemp();
7040 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7042 Builder
bld(ctx
->program
, ctx
->block
);
7044 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7045 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7046 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7047 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7048 if (op
== nir_op_iand
)
7049 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7050 else if (op
== nir_op_ior
)
7051 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7052 else if (op
== nir_op_ixor
)
7053 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7059 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7061 Builder
bld(ctx
->program
, ctx
->block
);
7062 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7063 if (src
.regClass().type() == RegType::vgpr
) {
7064 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7065 } else if (src
.regClass() == s1
) {
7066 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7067 } else if (src
.regClass() == s2
) {
7068 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7070 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7071 nir_print_instr(&instr
->instr
, stderr
);
7072 fprintf(stderr
, "\n");
7076 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7078 Builder
bld(ctx
->program
, ctx
->block
);
7079 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7080 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7081 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7083 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7084 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7085 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7086 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7089 if (ctx
->program
->chip_class
>= GFX8
) {
7090 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7091 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7092 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7093 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7094 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7095 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7097 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7098 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7099 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7100 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7101 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7102 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7103 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7104 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7105 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7106 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7109 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7110 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7111 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7112 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7113 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7114 Temp wqm1
= bld
.tmp(v1
);
7115 emit_wqm(ctx
, tmp1
, wqm1
, true);
7116 Temp wqm2
= bld
.tmp(v1
);
7117 emit_wqm(ctx
, tmp2
, wqm2
, true);
7118 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7122 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7124 Builder
bld(ctx
->program
, ctx
->block
);
7125 switch(instr
->intrinsic
) {
7126 case nir_intrinsic_load_barycentric_sample
:
7127 case nir_intrinsic_load_barycentric_pixel
:
7128 case nir_intrinsic_load_barycentric_centroid
: {
7129 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7130 Temp bary
= Temp(0, s2
);
7132 case INTERP_MODE_SMOOTH
:
7133 case INTERP_MODE_NONE
:
7134 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7135 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7136 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7137 bary
= ctx
->persp_centroid
;
7138 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7139 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7141 case INTERP_MODE_NOPERSPECTIVE
:
7142 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7143 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7144 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7145 bary
= ctx
->linear_centroid
;
7146 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7147 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7152 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7153 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7154 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7155 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7156 Operand(p1
), Operand(p2
));
7157 emit_split_vector(ctx
, dst
, 2);
7160 case nir_intrinsic_load_barycentric_model
: {
7161 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7163 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7164 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7165 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7166 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7167 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7168 Operand(p1
), Operand(p2
), Operand(p3
));
7169 emit_split_vector(ctx
, dst
, 3);
7172 case nir_intrinsic_load_barycentric_at_sample
: {
7173 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7174 switch (ctx
->options
->key
.fs
.num_samples
) {
7175 case 2: sample_pos_offset
+= 1 << 3; break;
7176 case 4: sample_pos_offset
+= 3 << 3; break;
7177 case 8: sample_pos_offset
+= 7 << 3; break;
7181 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7182 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7183 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7184 if (addr
.type() == RegType::sgpr
) {
7187 sample_pos_offset
+= const_addr
->u32
<< 3;
7188 offset
= Operand(sample_pos_offset
);
7189 } else if (ctx
->options
->chip_class
>= GFX9
) {
7190 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7192 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7193 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7196 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7197 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7199 } else if (ctx
->options
->chip_class
>= GFX9
) {
7200 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7201 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7202 } else if (ctx
->options
->chip_class
>= GFX7
) {
7203 /* addr += private_segment_buffer + sample_pos_offset */
7204 Temp tmp0
= bld
.tmp(s1
);
7205 Temp tmp1
= bld
.tmp(s1
);
7206 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7207 Definition scc_tmp
= bld
.def(s1
, scc
);
7208 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7209 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7210 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7211 Temp pck0
= bld
.tmp(v1
);
7212 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7213 tmp1
= as_vgpr(ctx
, tmp1
);
7214 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7215 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7217 /* sample_pos = flat_load_dwordx2 addr */
7218 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7220 assert(ctx
->options
->chip_class
== GFX6
);
7222 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7223 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7224 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7226 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7227 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7229 sample_pos
= bld
.tmp(v2
);
7231 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7232 load
->definitions
[0] = Definition(sample_pos
);
7233 load
->operands
[0] = Operand(rsrc
);
7234 load
->operands
[1] = Operand(addr
);
7235 load
->operands
[2] = Operand(0u);
7236 load
->offset
= sample_pos_offset
;
7238 load
->addr64
= true;
7241 load
->disable_wqm
= false;
7242 load
->barrier
= barrier_none
;
7243 load
->can_reorder
= true;
7244 ctx
->block
->instructions
.emplace_back(std::move(load
));
7247 /* sample_pos -= 0.5 */
7248 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7249 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7250 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7251 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7252 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7254 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7257 case nir_intrinsic_load_barycentric_at_offset
: {
7258 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7259 RegClass rc
= RegClass(offset
.type(), 1);
7260 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7261 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7262 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7265 case nir_intrinsic_load_front_face
: {
7266 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7267 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7270 case nir_intrinsic_load_view_index
: {
7271 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7272 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7273 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7279 case nir_intrinsic_load_layer_id
: {
7280 unsigned idx
= nir_intrinsic_base(instr
);
7281 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7282 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7285 case nir_intrinsic_load_frag_coord
: {
7286 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7289 case nir_intrinsic_load_sample_pos
: {
7290 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7291 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7292 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7293 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7294 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7297 case nir_intrinsic_load_tess_coord
:
7298 visit_load_tess_coord(ctx
, instr
);
7300 case nir_intrinsic_load_interpolated_input
:
7301 visit_load_interpolated_input(ctx
, instr
);
7303 case nir_intrinsic_store_output
:
7304 visit_store_output(ctx
, instr
);
7306 case nir_intrinsic_load_input
:
7307 case nir_intrinsic_load_input_vertex
:
7308 visit_load_input(ctx
, instr
);
7310 case nir_intrinsic_load_output
:
7311 visit_load_output(ctx
, instr
);
7313 case nir_intrinsic_load_per_vertex_input
:
7314 visit_load_per_vertex_input(ctx
, instr
);
7316 case nir_intrinsic_load_per_vertex_output
:
7317 visit_load_per_vertex_output(ctx
, instr
);
7319 case nir_intrinsic_store_per_vertex_output
:
7320 visit_store_per_vertex_output(ctx
, instr
);
7322 case nir_intrinsic_load_ubo
:
7323 visit_load_ubo(ctx
, instr
);
7325 case nir_intrinsic_load_push_constant
:
7326 visit_load_push_constant(ctx
, instr
);
7328 case nir_intrinsic_load_constant
:
7329 visit_load_constant(ctx
, instr
);
7331 case nir_intrinsic_vulkan_resource_index
:
7332 visit_load_resource(ctx
, instr
);
7334 case nir_intrinsic_discard
:
7335 visit_discard(ctx
, instr
);
7337 case nir_intrinsic_discard_if
:
7338 visit_discard_if(ctx
, instr
);
7340 case nir_intrinsic_load_shared
:
7341 visit_load_shared(ctx
, instr
);
7343 case nir_intrinsic_store_shared
:
7344 visit_store_shared(ctx
, instr
);
7346 case nir_intrinsic_shared_atomic_add
:
7347 case nir_intrinsic_shared_atomic_imin
:
7348 case nir_intrinsic_shared_atomic_umin
:
7349 case nir_intrinsic_shared_atomic_imax
:
7350 case nir_intrinsic_shared_atomic_umax
:
7351 case nir_intrinsic_shared_atomic_and
:
7352 case nir_intrinsic_shared_atomic_or
:
7353 case nir_intrinsic_shared_atomic_xor
:
7354 case nir_intrinsic_shared_atomic_exchange
:
7355 case nir_intrinsic_shared_atomic_comp_swap
:
7356 visit_shared_atomic(ctx
, instr
);
7358 case nir_intrinsic_image_deref_load
:
7359 visit_image_load(ctx
, instr
);
7361 case nir_intrinsic_image_deref_store
:
7362 visit_image_store(ctx
, instr
);
7364 case nir_intrinsic_image_deref_atomic_add
:
7365 case nir_intrinsic_image_deref_atomic_umin
:
7366 case nir_intrinsic_image_deref_atomic_imin
:
7367 case nir_intrinsic_image_deref_atomic_umax
:
7368 case nir_intrinsic_image_deref_atomic_imax
:
7369 case nir_intrinsic_image_deref_atomic_and
:
7370 case nir_intrinsic_image_deref_atomic_or
:
7371 case nir_intrinsic_image_deref_atomic_xor
:
7372 case nir_intrinsic_image_deref_atomic_exchange
:
7373 case nir_intrinsic_image_deref_atomic_comp_swap
:
7374 visit_image_atomic(ctx
, instr
);
7376 case nir_intrinsic_image_deref_size
:
7377 visit_image_size(ctx
, instr
);
7379 case nir_intrinsic_load_ssbo
:
7380 visit_load_ssbo(ctx
, instr
);
7382 case nir_intrinsic_store_ssbo
:
7383 visit_store_ssbo(ctx
, instr
);
7385 case nir_intrinsic_load_global
:
7386 visit_load_global(ctx
, instr
);
7388 case nir_intrinsic_store_global
:
7389 visit_store_global(ctx
, instr
);
7391 case nir_intrinsic_global_atomic_add
:
7392 case nir_intrinsic_global_atomic_imin
:
7393 case nir_intrinsic_global_atomic_umin
:
7394 case nir_intrinsic_global_atomic_imax
:
7395 case nir_intrinsic_global_atomic_umax
:
7396 case nir_intrinsic_global_atomic_and
:
7397 case nir_intrinsic_global_atomic_or
:
7398 case nir_intrinsic_global_atomic_xor
:
7399 case nir_intrinsic_global_atomic_exchange
:
7400 case nir_intrinsic_global_atomic_comp_swap
:
7401 visit_global_atomic(ctx
, instr
);
7403 case nir_intrinsic_ssbo_atomic_add
:
7404 case nir_intrinsic_ssbo_atomic_imin
:
7405 case nir_intrinsic_ssbo_atomic_umin
:
7406 case nir_intrinsic_ssbo_atomic_imax
:
7407 case nir_intrinsic_ssbo_atomic_umax
:
7408 case nir_intrinsic_ssbo_atomic_and
:
7409 case nir_intrinsic_ssbo_atomic_or
:
7410 case nir_intrinsic_ssbo_atomic_xor
:
7411 case nir_intrinsic_ssbo_atomic_exchange
:
7412 case nir_intrinsic_ssbo_atomic_comp_swap
:
7413 visit_atomic_ssbo(ctx
, instr
);
7415 case nir_intrinsic_load_scratch
:
7416 visit_load_scratch(ctx
, instr
);
7418 case nir_intrinsic_store_scratch
:
7419 visit_store_scratch(ctx
, instr
);
7421 case nir_intrinsic_get_buffer_size
:
7422 visit_get_buffer_size(ctx
, instr
);
7424 case nir_intrinsic_control_barrier
: {
7425 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7426 /* GFX6 only (thanks to a hw bug workaround):
7427 * The real barrier instruction isn’t needed, because an entire patch
7428 * always fits into a single wave.
7433 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7434 bld
.sopp(aco_opcode::s_barrier
);
7438 case nir_intrinsic_memory_barrier_tcs_patch
:
7439 case nir_intrinsic_group_memory_barrier
:
7440 case nir_intrinsic_memory_barrier
:
7441 case nir_intrinsic_memory_barrier_buffer
:
7442 case nir_intrinsic_memory_barrier_image
:
7443 case nir_intrinsic_memory_barrier_shared
:
7444 emit_memory_barrier(ctx
, instr
);
7446 case nir_intrinsic_load_num_work_groups
: {
7447 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7448 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7449 emit_split_vector(ctx
, dst
, 3);
7452 case nir_intrinsic_load_local_invocation_id
: {
7453 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7454 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7455 emit_split_vector(ctx
, dst
, 3);
7458 case nir_intrinsic_load_work_group_id
: {
7459 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7460 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7462 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7463 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7464 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7465 emit_split_vector(ctx
, dst
, 3);
7468 case nir_intrinsic_load_local_invocation_index
: {
7469 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7471 /* The tg_size bits [6:11] contain the subgroup id,
7472 * we need this multiplied by the wave size, and then OR the thread id to it.
7474 if (ctx
->program
->wave_size
== 64) {
7475 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7476 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7477 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7478 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7480 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7481 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7482 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7483 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7487 case nir_intrinsic_load_subgroup_id
: {
7488 if (ctx
->stage
== compute_cs
) {
7489 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7490 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7492 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7496 case nir_intrinsic_load_subgroup_invocation
: {
7497 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7500 case nir_intrinsic_load_num_subgroups
: {
7501 if (ctx
->stage
== compute_cs
)
7502 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7503 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7505 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7508 case nir_intrinsic_ballot
: {
7509 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7510 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7511 Definition tmp
= bld
.def(dst
.regClass());
7512 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7513 if (instr
->src
[0].ssa
->bit_size
== 1) {
7514 assert(src
.regClass() == bld
.lm
);
7515 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7516 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7517 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7518 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7519 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7521 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7522 nir_print_instr(&instr
->instr
, stderr
);
7523 fprintf(stderr
, "\n");
7525 if (dst
.size() != bld
.lm
.size()) {
7526 /* Wave32 with ballot size set to 64 */
7527 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7529 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7532 case nir_intrinsic_shuffle
:
7533 case nir_intrinsic_read_invocation
: {
7534 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7535 if (!nir_src_is_divergent(instr
->src
[0])) {
7536 emit_uniform_subgroup(ctx
, instr
, src
);
7538 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7539 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7540 tid
= bld
.as_uniform(tid
);
7541 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7542 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7543 Temp tmp
= bld
.tmp(v1
);
7544 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7545 if (dst
.type() == RegType::vgpr
)
7546 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7548 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7549 } else if (src
.regClass() == v1
) {
7550 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7551 } else if (src
.regClass() == v2
) {
7552 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7553 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7554 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7555 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7556 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7557 emit_split_vector(ctx
, dst
, 2);
7558 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7559 assert(src
.regClass() == bld
.lm
);
7560 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7561 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7562 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7563 assert(src
.regClass() == bld
.lm
);
7565 if (ctx
->program
->chip_class
<= GFX7
)
7566 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7567 else if (ctx
->program
->wave_size
== 64)
7568 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7570 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7571 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7572 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7573 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7575 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7576 nir_print_instr(&instr
->instr
, stderr
);
7577 fprintf(stderr
, "\n");
7582 case nir_intrinsic_load_sample_id
: {
7583 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7584 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7587 case nir_intrinsic_load_sample_mask_in
: {
7588 visit_load_sample_mask_in(ctx
, instr
);
7591 case nir_intrinsic_read_first_invocation
: {
7592 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7593 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7594 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7596 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7598 } else if (src
.regClass() == v2
) {
7599 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7600 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7601 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7602 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7603 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7604 emit_split_vector(ctx
, dst
, 2);
7605 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7606 assert(src
.regClass() == bld
.lm
);
7607 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7608 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7609 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7610 } else if (src
.regClass() == s1
) {
7611 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7612 } else if (src
.regClass() == s2
) {
7613 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7615 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7616 nir_print_instr(&instr
->instr
, stderr
);
7617 fprintf(stderr
, "\n");
7621 case nir_intrinsic_vote_all
: {
7622 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7623 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7624 assert(src
.regClass() == bld
.lm
);
7625 assert(dst
.regClass() == bld
.lm
);
7627 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7628 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7629 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7632 case nir_intrinsic_vote_any
: {
7633 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7634 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7635 assert(src
.regClass() == bld
.lm
);
7636 assert(dst
.regClass() == bld
.lm
);
7638 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7639 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7642 case nir_intrinsic_reduce
:
7643 case nir_intrinsic_inclusive_scan
:
7644 case nir_intrinsic_exclusive_scan
: {
7645 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7646 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7647 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7648 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7649 nir_intrinsic_cluster_size(instr
) : 0;
7650 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7652 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7653 emit_uniform_subgroup(ctx
, instr
, src
);
7654 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7655 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7657 else if (op
== nir_op_iadd
)
7659 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7661 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7663 switch (instr
->intrinsic
) {
7664 case nir_intrinsic_reduce
:
7665 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7667 case nir_intrinsic_exclusive_scan
:
7668 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7670 case nir_intrinsic_inclusive_scan
:
7671 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7676 } else if (cluster_size
== 1) {
7677 bld
.copy(Definition(dst
), src
);
7679 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7681 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7685 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7686 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7701 unreachable("unknown reduction op");
7707 switch (instr
->intrinsic
) {
7708 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7709 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7710 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7712 unreachable("unknown reduce intrinsic");
7715 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7716 reduce
->operands
[0] = Operand(src
);
7717 // filled in by aco_reduce_assign.cpp, used internally as part of the
7719 assert(dst
.size() == 1 || dst
.size() == 2);
7720 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7721 reduce
->operands
[2] = Operand(v1
.as_linear());
7723 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7724 reduce
->definitions
[0] = Definition(tmp_dst
);
7725 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7726 reduce
->definitions
[2] = Definition();
7727 reduce
->definitions
[3] = Definition(scc
, s1
);
7728 reduce
->definitions
[4] = Definition();
7729 reduce
->reduce_op
= reduce_op
;
7730 reduce
->cluster_size
= cluster_size
;
7731 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7733 emit_wqm(ctx
, tmp_dst
, dst
);
7737 case nir_intrinsic_quad_broadcast
: {
7738 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7739 if (!nir_dest_is_divergent(instr
->dest
)) {
7740 emit_uniform_subgroup(ctx
, instr
, src
);
7742 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7743 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7744 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7746 if (instr
->dest
.ssa
.bit_size
== 1) {
7747 assert(src
.regClass() == bld
.lm
);
7748 assert(dst
.regClass() == bld
.lm
);
7749 uint32_t half_mask
= 0x11111111u
<< lane
;
7750 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7751 Temp tmp
= bld
.tmp(bld
.lm
);
7752 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7753 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7754 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7755 emit_wqm(ctx
, tmp
, dst
);
7756 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7757 Temp tmp
= bld
.tmp(v1
);
7758 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7759 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7760 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7761 Temp tmp
= bld
.tmp(v1
);
7762 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7763 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7764 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7765 if (ctx
->program
->chip_class
>= GFX8
)
7766 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7768 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7769 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7770 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7772 if (ctx
->program
->chip_class
>= GFX8
) {
7773 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7774 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7776 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7777 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7779 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7780 emit_split_vector(ctx
, dst
, 2);
7782 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7783 nir_print_instr(&instr
->instr
, stderr
);
7784 fprintf(stderr
, "\n");
7789 case nir_intrinsic_quad_swap_horizontal
:
7790 case nir_intrinsic_quad_swap_vertical
:
7791 case nir_intrinsic_quad_swap_diagonal
:
7792 case nir_intrinsic_quad_swizzle_amd
: {
7793 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7794 if (!nir_dest_is_divergent(instr
->dest
)) {
7795 emit_uniform_subgroup(ctx
, instr
, src
);
7798 uint16_t dpp_ctrl
= 0;
7799 switch (instr
->intrinsic
) {
7800 case nir_intrinsic_quad_swap_horizontal
:
7801 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7803 case nir_intrinsic_quad_swap_vertical
:
7804 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7806 case nir_intrinsic_quad_swap_diagonal
:
7807 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7809 case nir_intrinsic_quad_swizzle_amd
:
7810 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7815 if (ctx
->program
->chip_class
< GFX8
)
7816 dpp_ctrl
|= (1 << 15);
7818 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7819 if (instr
->dest
.ssa
.bit_size
== 1) {
7820 assert(src
.regClass() == bld
.lm
);
7821 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7822 if (ctx
->program
->chip_class
>= GFX8
)
7823 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7825 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7826 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7827 emit_wqm(ctx
, tmp
, dst
);
7828 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7829 Temp tmp
= bld
.tmp(v1
);
7830 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7831 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7832 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7833 Temp tmp
= bld
.tmp(v1
);
7834 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7835 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7836 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7838 if (ctx
->program
->chip_class
>= GFX8
)
7839 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7841 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7842 emit_wqm(ctx
, tmp
, dst
);
7843 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7844 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7845 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7846 if (ctx
->program
->chip_class
>= GFX8
) {
7847 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7848 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7850 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7851 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7853 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7854 emit_split_vector(ctx
, dst
, 2);
7856 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7857 nir_print_instr(&instr
->instr
, stderr
);
7858 fprintf(stderr
, "\n");
7862 case nir_intrinsic_masked_swizzle_amd
: {
7863 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7864 if (!nir_dest_is_divergent(instr
->dest
)) {
7865 emit_uniform_subgroup(ctx
, instr
, src
);
7868 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7869 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7870 if (dst
.regClass() == v1
) {
7872 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7874 } else if (dst
.regClass() == v2
) {
7875 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7877 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7878 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7879 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7880 emit_split_vector(ctx
, dst
, 2);
7882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7883 nir_print_instr(&instr
->instr
, stderr
);
7884 fprintf(stderr
, "\n");
7888 case nir_intrinsic_write_invocation_amd
: {
7889 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7890 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7891 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7892 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7893 if (dst
.regClass() == v1
) {
7894 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7895 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7896 } else if (dst
.regClass() == v2
) {
7897 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7898 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7899 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7900 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7901 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7902 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7903 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7904 emit_split_vector(ctx
, dst
, 2);
7906 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7907 nir_print_instr(&instr
->instr
, stderr
);
7908 fprintf(stderr
, "\n");
7912 case nir_intrinsic_mbcnt_amd
: {
7913 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7914 RegClass rc
= RegClass(src
.type(), 1);
7915 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7917 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7918 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7919 emit_wqm(ctx
, wqm_tmp
, dst
);
7922 case nir_intrinsic_load_helper_invocation
: {
7923 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7924 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7925 ctx
->block
->kind
|= block_kind_needs_lowering
;
7926 ctx
->program
->needs_exact
= true;
7929 case nir_intrinsic_is_helper_invocation
: {
7930 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7931 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7932 ctx
->block
->kind
|= block_kind_needs_lowering
;
7933 ctx
->program
->needs_exact
= true;
7936 case nir_intrinsic_demote
:
7937 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7939 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7940 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7941 ctx
->block
->kind
|= block_kind_uses_demote
;
7942 ctx
->program
->needs_exact
= true;
7944 case nir_intrinsic_demote_if
: {
7945 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7946 assert(src
.regClass() == bld
.lm
);
7947 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7948 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7950 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7951 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7952 ctx
->block
->kind
|= block_kind_uses_demote
;
7953 ctx
->program
->needs_exact
= true;
7956 case nir_intrinsic_first_invocation
: {
7957 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7958 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7961 case nir_intrinsic_shader_clock
:
7962 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7963 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7965 case nir_intrinsic_load_vertex_id_zero_base
: {
7966 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7967 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7970 case nir_intrinsic_load_first_vertex
: {
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7975 case nir_intrinsic_load_base_instance
: {
7976 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7977 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7980 case nir_intrinsic_load_instance_id
: {
7981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7982 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7985 case nir_intrinsic_load_draw_id
: {
7986 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7987 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7990 case nir_intrinsic_load_invocation_id
: {
7991 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7993 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7994 if (ctx
->options
->chip_class
>= GFX10
)
7995 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7997 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7998 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7999 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8000 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8002 unreachable("Unsupported stage for load_invocation_id");
8007 case nir_intrinsic_load_primitive_id
: {
8008 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8010 switch (ctx
->shader
->info
.stage
) {
8011 case MESA_SHADER_GEOMETRY
:
8012 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8014 case MESA_SHADER_TESS_CTRL
:
8015 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8017 case MESA_SHADER_TESS_EVAL
:
8018 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8021 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8026 case nir_intrinsic_load_patch_vertices_in
: {
8027 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8028 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8030 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8031 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8034 case nir_intrinsic_emit_vertex_with_counter
: {
8035 visit_emit_vertex_with_counter(ctx
, instr
);
8038 case nir_intrinsic_end_primitive_with_counter
: {
8039 unsigned stream
= nir_intrinsic_stream_id(instr
);
8040 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8043 case nir_intrinsic_set_vertex_count
: {
8044 /* unused, the HW keeps track of this for us */
8048 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8049 nir_print_instr(&instr
->instr
, stderr
);
8050 fprintf(stderr
, "\n");
8058 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8059 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8060 enum glsl_base_type
*stype
)
8062 nir_deref_instr
*texture_deref_instr
= NULL
;
8063 nir_deref_instr
*sampler_deref_instr
= NULL
;
8066 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8067 switch (instr
->src
[i
].src_type
) {
8068 case nir_tex_src_texture_deref
:
8069 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8071 case nir_tex_src_sampler_deref
:
8072 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8074 case nir_tex_src_plane
:
8075 plane
= nir_src_as_int(instr
->src
[i
].src
);
8082 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8084 if (!sampler_deref_instr
)
8085 sampler_deref_instr
= texture_deref_instr
;
8088 assert(instr
->op
!= nir_texop_txf_ms
&&
8089 instr
->op
!= nir_texop_samples_identical
);
8090 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8091 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8092 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8093 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8094 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8095 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8097 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8100 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8102 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8103 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8104 Builder
bld(ctx
->program
, ctx
->block
);
8106 /* to avoid unnecessary moves, we split and recombine sampler and image */
8107 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8108 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8109 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8111 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8112 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8113 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8114 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8116 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8117 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8118 img
[0], img
[1], img
[2], img
[3],
8119 img
[4], img
[5], img
[6], img
[7]);
8120 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8121 samp
[0], samp
[1], samp
[2], samp
[3]);
8124 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8125 instr
->op
== nir_texop_samples_identical
))
8126 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8129 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8130 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8132 Builder
bld(ctx
->program
, ctx
->block
);
8134 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8135 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8136 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8138 Operand
neg_one(0xbf800000u
);
8139 Operand
one(0x3f800000u
);
8140 Operand
two(0x40000000u
);
8141 Operand
four(0x40800000u
);
8143 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8144 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8145 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8147 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8148 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8149 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8150 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8153 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8154 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8155 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8157 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8160 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8161 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8162 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8165 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8166 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8168 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8169 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8172 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8174 Builder
bld(ctx
->program
, ctx
->block
);
8175 Temp ma
, tc
, sc
, id
;
8178 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8180 // see comment in ac_prepare_cube_coords()
8181 if (ctx
->options
->chip_class
<= GFX8
)
8182 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8185 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8187 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8188 vop3a
->operands
[0] = Operand(ma
);
8189 vop3a
->abs
[0] = true;
8190 Temp invma
= bld
.tmp(v1
);
8191 vop3a
->definitions
[0] = Definition(invma
);
8192 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8194 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8196 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8198 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8200 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8202 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8205 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8206 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8208 for (unsigned i
= 0; i
< 2; i
++) {
8209 // see comment in ac_prepare_cube_coords()
8211 Temp deriv_sc
, deriv_tc
;
8212 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8213 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8215 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8217 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8218 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8219 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8220 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8221 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8222 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8223 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8226 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8227 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8231 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8238 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8240 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8242 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8243 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8246 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8247 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8248 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8252 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8254 Builder
bld(ctx
->program
, ctx
->block
);
8255 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8256 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8257 has_clamped_lod
= false;
8258 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8259 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8260 clamped_lod
= Temp();
8261 std::vector
<Temp
> coords
;
8262 std::vector
<Temp
> derivs
;
8263 nir_const_value
*sample_index_cv
= NULL
;
8264 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8265 enum glsl_base_type stype
;
8266 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8268 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8269 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8270 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8271 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8273 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8274 switch (instr
->src
[i
].src_type
) {
8275 case nir_tex_src_coord
: {
8276 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8277 for (unsigned i
= 0; i
< coord
.size(); i
++)
8278 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8281 case nir_tex_src_bias
:
8282 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8285 case nir_tex_src_lod
: {
8286 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8288 if (val
&& val
->f32
<= 0.0) {
8291 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8296 case nir_tex_src_min_lod
:
8297 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8298 has_clamped_lod
= true;
8300 case nir_tex_src_comparator
:
8301 if (instr
->is_shadow
) {
8302 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8306 case nir_tex_src_offset
:
8307 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8308 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8311 case nir_tex_src_ddx
:
8312 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8315 case nir_tex_src_ddy
:
8316 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8319 case nir_tex_src_ms_index
:
8320 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8321 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8322 has_sample_index
= true;
8324 case nir_tex_src_texture_offset
:
8325 case nir_tex_src_sampler_offset
:
8331 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8332 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8334 if (instr
->op
== nir_texop_texture_samples
) {
8335 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8337 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8338 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8339 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8341 Operand default_sample
= Operand(1u);
8342 if (ctx
->options
->robust_buffer_access
) {
8343 /* Extract the second dword of the descriptor, if it's
8344 * all zero, then it's a null descriptor.
8346 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8347 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8348 default_sample
= Operand(is_non_null_descriptor
);
8351 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8353 samples
, default_sample
, bld
.scc(is_msaa
));
8357 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8358 aco_ptr
<Instruction
> tmp_instr
;
8359 Temp acc
, pack
= Temp();
8361 uint32_t pack_const
= 0;
8362 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8363 if (!const_offset
[i
])
8365 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8368 if (offset
.type() == RegType::sgpr
) {
8369 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8370 if (const_offset
[i
])
8373 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8374 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8377 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8380 if (pack
== Temp()) {
8383 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8387 if (pack_const
&& pack
!= Temp())
8388 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8390 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8391 if (const_offset
[i
])
8394 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8395 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8398 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8401 if (pack
== Temp()) {
8404 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8408 if (pack_const
&& pack
!= Temp())
8409 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8411 if (pack_const
&& pack
== Temp())
8412 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8413 else if (pack
== Temp())
8419 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8420 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8422 /* pack derivatives */
8423 if (has_ddx
|| has_ddy
) {
8424 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8425 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8426 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8427 derivs
= {ddx
, zero
, ddy
, zero
};
8429 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8430 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8431 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8432 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8437 if (instr
->coord_components
> 1 &&
8438 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8440 instr
->op
!= nir_texop_txf
)
8441 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8443 if (instr
->coord_components
> 2 &&
8444 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8445 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8446 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8447 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8449 instr
->op
!= nir_texop_txf
&&
8450 instr
->op
!= nir_texop_txf_ms
&&
8451 instr
->op
!= nir_texop_fragment_fetch
&&
8452 instr
->op
!= nir_texop_fragment_mask_fetch
)
8453 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8455 if (ctx
->options
->chip_class
== GFX9
&&
8456 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8457 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8458 assert(coords
.size() > 0 && coords
.size() < 3);
8460 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8461 Operand((uint32_t) 0) :
8462 Operand((uint32_t) 0x3f000000)));
8465 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8467 if (instr
->op
== nir_texop_samples_identical
)
8468 resource
= fmask_ptr
;
8470 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8471 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8472 instr
->op
!= nir_texop_txs
&&
8473 instr
->op
!= nir_texop_fragment_fetch
&&
8474 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8475 assert(has_sample_index
);
8476 Operand
op(sample_index
);
8477 if (sample_index_cv
)
8478 op
= Operand(sample_index_cv
->u32
);
8479 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8482 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8483 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8484 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8485 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8490 /* Build tex instruction */
8491 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8492 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8493 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8495 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8498 /* gather4 selects the component by dmask and always returns vec4 */
8499 if (instr
->op
== nir_texop_tg4
) {
8500 assert(instr
->dest
.ssa
.num_components
== 4);
8501 if (instr
->is_shadow
)
8504 dmask
= 1 << instr
->component
;
8505 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8506 tmp_dst
= bld
.tmp(v4
);
8507 } else if (instr
->op
== nir_texop_samples_identical
) {
8508 tmp_dst
= bld
.tmp(v1
);
8509 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8510 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8513 aco_ptr
<MIMG_instruction
> tex
;
8514 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8516 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8518 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8519 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8522 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8523 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8525 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8526 tex
->operands
[0] = Operand(resource
);
8527 tex
->operands
[1] = Operand(s4
); /* no sampler */
8528 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8529 if (ctx
->options
->chip_class
== GFX9
&&
8530 instr
->op
== nir_texop_txs
&&
8531 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8533 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8534 } else if (instr
->op
== nir_texop_query_levels
) {
8535 tex
->dmask
= 1 << 3;
8540 tex
->definitions
[0] = Definition(tmp_dst
);
8542 tex
->can_reorder
= true;
8543 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8546 /* divide 3rd value by 6 by multiplying with magic number */
8547 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8548 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8549 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8550 assert(instr
->dest
.ssa
.num_components
== 3);
8551 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8552 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8553 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8554 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8559 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8563 Temp tg4_compare_cube_wa64
= Temp();
8565 if (tg4_integer_workarounds
) {
8566 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8567 tex
->operands
[0] = Operand(resource
);
8568 tex
->operands
[1] = Operand(s4
); /* no sampler */
8569 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8573 Temp size
= bld
.tmp(v2
);
8574 tex
->definitions
[0] = Definition(size
);
8575 tex
->can_reorder
= true;
8576 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8577 emit_split_vector(ctx
, size
, size
.size());
8580 for (unsigned i
= 0; i
< 2; i
++) {
8581 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8582 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8583 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8584 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8587 Temp new_coords
[2] = {
8588 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8589 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8592 if (tg4_integer_cube_workaround
) {
8593 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8594 Temp desc
[resource
.size()];
8595 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8596 Format::PSEUDO
, 1, resource
.size())};
8597 split
->operands
[0] = Operand(resource
);
8598 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8599 desc
[i
] = bld
.tmp(s1
);
8600 split
->definitions
[i
] = Definition(desc
[i
]);
8602 ctx
->block
->instructions
.emplace_back(std::move(split
));
8604 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8605 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8606 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8609 if (stype
== GLSL_TYPE_UINT
) {
8610 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8611 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8612 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8613 bld
.scc(compare_cube_wa
));
8615 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8616 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8617 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8618 bld
.scc(compare_cube_wa
));
8620 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8621 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8623 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8625 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8626 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8627 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8629 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8630 Format::PSEUDO
, resource
.size(), 1)};
8631 for (unsigned i
= 0; i
< resource
.size(); i
++)
8632 vec
->operands
[i
] = Operand(desc
[i
]);
8633 resource
= bld
.tmp(resource
.regClass());
8634 vec
->definitions
[0] = Definition(resource
);
8635 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8637 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8638 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8639 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8640 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8642 coords
[0] = new_coords
[0];
8643 coords
[1] = new_coords
[1];
8646 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8647 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8649 assert(coords
.size() == 1);
8650 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8654 op
= aco_opcode::buffer_load_format_x
; break;
8656 op
= aco_opcode::buffer_load_format_xy
; break;
8658 op
= aco_opcode::buffer_load_format_xyz
; break;
8660 op
= aco_opcode::buffer_load_format_xyzw
; break;
8662 unreachable("Tex instruction loads more than 4 components.");
8665 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8666 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8669 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8671 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8672 mubuf
->operands
[0] = Operand(resource
);
8673 mubuf
->operands
[1] = Operand(coords
[0]);
8674 mubuf
->operands
[2] = Operand((uint32_t) 0);
8675 mubuf
->definitions
[0] = Definition(tmp_dst
);
8676 mubuf
->idxen
= true;
8677 mubuf
->can_reorder
= true;
8678 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8680 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8684 /* gather MIMG address components */
8685 std::vector
<Temp
> args
;
8687 args
.emplace_back(offset
);
8689 args
.emplace_back(bias
);
8691 args
.emplace_back(compare
);
8693 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8695 args
.insert(args
.end(), coords
.begin(), coords
.end());
8696 if (has_sample_index
)
8697 args
.emplace_back(sample_index
);
8699 args
.emplace_back(lod
);
8700 if (has_clamped_lod
)
8701 args
.emplace_back(clamped_lod
);
8703 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8704 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8705 vec
->definitions
[0] = Definition(arg
);
8706 for (unsigned i
= 0; i
< args
.size(); i
++)
8707 vec
->operands
[i
] = Operand(args
[i
]);
8708 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8711 if (instr
->op
== nir_texop_txf
||
8712 instr
->op
== nir_texop_txf_ms
||
8713 instr
->op
== nir_texop_samples_identical
||
8714 instr
->op
== nir_texop_fragment_fetch
||
8715 instr
->op
== nir_texop_fragment_mask_fetch
) {
8716 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8717 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8718 tex
->operands
[0] = Operand(resource
);
8719 tex
->operands
[1] = Operand(s4
); /* no sampler */
8720 tex
->operands
[2] = Operand(arg
);
8725 tex
->definitions
[0] = Definition(tmp_dst
);
8726 tex
->can_reorder
= true;
8727 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8729 if (instr
->op
== nir_texop_samples_identical
) {
8730 assert(dmask
== 1 && dst
.regClass() == v1
);
8731 assert(dst
.id() != tmp_dst
.id());
8733 Temp tmp
= bld
.tmp(bld
.lm
);
8734 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8735 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8738 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8743 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8744 aco_opcode opcode
= aco_opcode::image_sample
;
8745 if (has_offset
) { /* image_sample_*_o */
8746 if (has_clamped_lod
) {
8748 opcode
= aco_opcode::image_sample_c_cl_o
;
8750 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8752 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8754 opcode
= aco_opcode::image_sample_cl_o
;
8756 opcode
= aco_opcode::image_sample_d_cl_o
;
8758 opcode
= aco_opcode::image_sample_b_cl_o
;
8760 } else if (has_compare
) {
8761 opcode
= aco_opcode::image_sample_c_o
;
8763 opcode
= aco_opcode::image_sample_c_d_o
;
8765 opcode
= aco_opcode::image_sample_c_b_o
;
8767 opcode
= aco_opcode::image_sample_c_lz_o
;
8769 opcode
= aco_opcode::image_sample_c_l_o
;
8771 opcode
= aco_opcode::image_sample_o
;
8773 opcode
= aco_opcode::image_sample_d_o
;
8775 opcode
= aco_opcode::image_sample_b_o
;
8777 opcode
= aco_opcode::image_sample_lz_o
;
8779 opcode
= aco_opcode::image_sample_l_o
;
8781 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8783 opcode
= aco_opcode::image_sample_c_cl
;
8785 opcode
= aco_opcode::image_sample_c_d_cl
;
8787 opcode
= aco_opcode::image_sample_c_b_cl
;
8789 opcode
= aco_opcode::image_sample_cl
;
8791 opcode
= aco_opcode::image_sample_d_cl
;
8793 opcode
= aco_opcode::image_sample_b_cl
;
8795 } else { /* no offset */
8797 opcode
= aco_opcode::image_sample_c
;
8799 opcode
= aco_opcode::image_sample_c_d
;
8801 opcode
= aco_opcode::image_sample_c_b
;
8803 opcode
= aco_opcode::image_sample_c_lz
;
8805 opcode
= aco_opcode::image_sample_c_l
;
8807 opcode
= aco_opcode::image_sample
;
8809 opcode
= aco_opcode::image_sample_d
;
8811 opcode
= aco_opcode::image_sample_b
;
8813 opcode
= aco_opcode::image_sample_lz
;
8815 opcode
= aco_opcode::image_sample_l
;
8819 if (instr
->op
== nir_texop_tg4
) {
8821 opcode
= aco_opcode::image_gather4_lz_o
;
8823 opcode
= aco_opcode::image_gather4_c_lz_o
;
8825 opcode
= aco_opcode::image_gather4_lz
;
8827 opcode
= aco_opcode::image_gather4_c_lz
;
8829 } else if (instr
->op
== nir_texop_lod
) {
8830 opcode
= aco_opcode::image_get_lod
;
8833 /* we don't need the bias, sample index, compare value or offset to be
8834 * computed in WQM but if the p_create_vector copies the coordinates, then it
8835 * needs to be in WQM */
8836 if (ctx
->stage
== fragment_fs
&&
8837 !has_derivs
&& !has_lod
&& !level_zero
&&
8838 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8839 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8840 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8842 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8843 tex
->operands
[0] = Operand(resource
);
8844 tex
->operands
[1] = Operand(sampler
);
8845 tex
->operands
[2] = Operand(arg
);
8849 tex
->definitions
[0] = Definition(tmp_dst
);
8850 tex
->can_reorder
= true;
8851 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8853 if (tg4_integer_cube_workaround
) {
8854 assert(tmp_dst
.id() != dst
.id());
8855 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8857 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8859 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8860 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8862 if (stype
== GLSL_TYPE_UINT
)
8863 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8865 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8866 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8868 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8869 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8870 val
[0], val
[1], val
[2], val
[3]);
8872 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8873 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8878 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8880 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8881 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8882 return Operand(tmp
.regClass());
8884 return Operand(tmp
);
8887 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8889 aco_ptr
<Pseudo_instruction
> phi
;
8890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8891 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8893 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8894 logical
|= ctx
->block
->kind
& block_kind_merge
;
8895 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8897 /* we want a sorted list of sources, since the predecessor list is also sorted */
8898 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8899 nir_foreach_phi_src(src
, instr
)
8900 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8902 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8903 unsigned num_operands
= 0;
8904 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8905 unsigned num_defined
= 0;
8906 unsigned cur_pred_idx
= 0;
8907 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8908 if (cur_pred_idx
< preds
.size()) {
8909 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8910 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8911 unsigned skipped
= 0;
8912 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8914 if (cur_pred_idx
+ skipped
< preds
.size()) {
8915 for (unsigned i
= 0; i
< skipped
; i
++)
8916 operands
[num_operands
++] = Operand(dst
.regClass());
8917 cur_pred_idx
+= skipped
;
8922 /* Handle missing predecessors at the end. This shouldn't happen with loop
8923 * headers and we can't ignore these sources for loop header phis. */
8924 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8927 Operand op
= get_phi_operand(ctx
, src
.second
);
8928 operands
[num_operands
++] = op
;
8929 num_defined
+= !op
.isUndefined();
8931 /* handle block_kind_continue_or_break at loop exit blocks */
8932 while (cur_pred_idx
++ < preds
.size())
8933 operands
[num_operands
++] = Operand(dst
.regClass());
8935 /* If the loop ends with a break, still add a linear continue edge in case
8936 * that break is divergent or continue_or_break is used. We'll either remove
8937 * this operand later in visit_loop() if it's not necessary or replace the
8938 * undef with something correct. */
8939 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8940 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8941 nir_block
*last
= nir_loop_last_block(loop
);
8942 if (last
->successors
[0] != instr
->instr
.block
)
8943 operands
[num_operands
++] = Operand(RegClass());
8946 if (num_defined
== 0) {
8947 Builder
bld(ctx
->program
, ctx
->block
);
8948 if (dst
.regClass() == s1
) {
8949 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8950 } else if (dst
.regClass() == v1
) {
8951 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8953 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8954 for (unsigned i
= 0; i
< dst
.size(); i
++)
8955 vec
->operands
[i
] = Operand(0u);
8956 vec
->definitions
[0] = Definition(dst
);
8957 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8962 /* we can use a linear phi in some cases if one src is undef */
8963 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8964 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8966 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8967 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8968 assert(invert
->kind
& block_kind_invert
);
8970 unsigned then_block
= invert
->linear_preds
[0];
8972 Block
* insert_block
= NULL
;
8973 for (unsigned i
= 0; i
< num_operands
; i
++) {
8974 Operand op
= operands
[i
];
8975 if (op
.isUndefined())
8977 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8978 phi
->operands
[0] = op
;
8981 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8982 phi
->operands
[1] = Operand(dst
.regClass());
8983 phi
->definitions
[0] = Definition(dst
);
8984 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8988 /* try to scalarize vector phis */
8989 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8990 // TODO: scalarize linear phis on divergent ifs
8991 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8992 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8993 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8994 Operand src
= operands
[i
];
8995 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8996 can_scalarize
= false;
8998 if (can_scalarize
) {
8999 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9000 assert(dst
.size() % num_components
== 0);
9001 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9003 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9004 for (unsigned k
= 0; k
< num_components
; k
++) {
9005 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9006 for (unsigned i
= 0; i
< num_operands
; i
++) {
9007 Operand src
= operands
[i
];
9008 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9010 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9011 phi
->definitions
[0] = Definition(phi_dst
);
9012 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9013 new_vec
[k
] = phi_dst
;
9014 vec
->operands
[k
] = Operand(phi_dst
);
9016 vec
->definitions
[0] = Definition(dst
);
9017 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9018 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9023 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9024 for (unsigned i
= 0; i
< num_operands
; i
++)
9025 phi
->operands
[i
] = operands
[i
];
9026 phi
->definitions
[0] = Definition(dst
);
9027 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9031 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9033 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9035 assert(dst
.type() == RegType::sgpr
);
9037 if (dst
.size() == 1) {
9038 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9040 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9041 for (unsigned i
= 0; i
< dst
.size(); i
++)
9042 vec
->operands
[i
] = Operand(0u);
9043 vec
->definitions
[0] = Definition(dst
);
9044 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9048 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9050 Builder
bld(ctx
->program
, ctx
->block
);
9051 Block
*logical_target
;
9052 append_logical_end(ctx
->block
);
9053 unsigned idx
= ctx
->block
->index
;
9055 switch (instr
->type
) {
9056 case nir_jump_break
:
9057 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9058 add_logical_edge(idx
, logical_target
);
9059 ctx
->block
->kind
|= block_kind_break
;
9061 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9062 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9063 /* uniform break - directly jump out of the loop */
9064 ctx
->block
->kind
|= block_kind_uniform
;
9065 ctx
->cf_info
.has_branch
= true;
9066 bld
.branch(aco_opcode::p_branch
);
9067 add_linear_edge(idx
, logical_target
);
9070 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9071 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9073 case nir_jump_continue
:
9074 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9075 add_logical_edge(idx
, logical_target
);
9076 ctx
->block
->kind
|= block_kind_continue
;
9078 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9079 /* for potential uniform breaks after this continue,
9080 we must ensure that they are handled correctly */
9081 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9082 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9083 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9085 /* uniform continue - directly jump to the loop header */
9086 ctx
->block
->kind
|= block_kind_uniform
;
9087 ctx
->cf_info
.has_branch
= true;
9088 bld
.branch(aco_opcode::p_branch
);
9089 add_linear_edge(idx
, logical_target
);
9094 fprintf(stderr
, "Unknown NIR jump instr: ");
9095 nir_print_instr(&instr
->instr
, stderr
);
9096 fprintf(stderr
, "\n");
9100 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9101 ctx
->cf_info
.exec_potentially_empty_break
= true;
9102 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9105 /* remove critical edges from linear CFG */
9106 bld
.branch(aco_opcode::p_branch
);
9107 Block
* break_block
= ctx
->program
->create_and_insert_block();
9108 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9109 break_block
->kind
|= block_kind_uniform
;
9110 add_linear_edge(idx
, break_block
);
9111 /* the loop_header pointer might be invalidated by this point */
9112 if (instr
->type
== nir_jump_continue
)
9113 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9114 add_linear_edge(break_block
->index
, logical_target
);
9115 bld
.reset(break_block
);
9116 bld
.branch(aco_opcode::p_branch
);
9118 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9119 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9120 add_linear_edge(idx
, continue_block
);
9121 append_logical_start(continue_block
);
9122 ctx
->block
= continue_block
;
9126 void visit_block(isel_context
*ctx
, nir_block
*block
)
9128 nir_foreach_instr(instr
, block
) {
9129 switch (instr
->type
) {
9130 case nir_instr_type_alu
:
9131 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9133 case nir_instr_type_load_const
:
9134 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9136 case nir_instr_type_intrinsic
:
9137 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9139 case nir_instr_type_tex
:
9140 visit_tex(ctx
, nir_instr_as_tex(instr
));
9142 case nir_instr_type_phi
:
9143 visit_phi(ctx
, nir_instr_as_phi(instr
));
9145 case nir_instr_type_ssa_undef
:
9146 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9148 case nir_instr_type_deref
:
9150 case nir_instr_type_jump
:
9151 visit_jump(ctx
, nir_instr_as_jump(instr
));
9154 fprintf(stderr
, "Unknown NIR instr type: ");
9155 nir_print_instr(instr
, stderr
);
9156 fprintf(stderr
, "\n");
9161 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9162 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9167 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9168 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9170 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9171 RegClass rc
= vals
[0].regClass();
9173 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9175 unsigned next_pred
= 1;
9177 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9178 Block
& block
= ctx
->program
->blocks
[idx
];
9179 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9180 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9184 if (block
.kind
& block_kind_continue
) {
9185 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9190 bool all_same
= true;
9191 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9192 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9196 val
= vals
[block
.linear_preds
[0] - first
];
9198 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9199 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9200 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9201 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9202 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9203 phi
->definitions
[0] = Definition(val
.getTemp());
9204 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9206 vals
[idx
- first
] = val
;
9209 return vals
[last
- first
];
9212 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9214 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9215 append_logical_end(ctx
->block
);
9216 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9217 Builder
bld(ctx
->program
, ctx
->block
);
9218 bld
.branch(aco_opcode::p_branch
);
9219 unsigned loop_preheader_idx
= ctx
->block
->index
;
9221 Block loop_exit
= Block();
9222 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9223 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9225 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9226 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9227 loop_header
->kind
|= block_kind_loop_header
;
9228 add_edge(loop_preheader_idx
, loop_header
);
9229 ctx
->block
= loop_header
;
9231 /* emit loop body */
9232 unsigned loop_header_idx
= loop_header
->index
;
9233 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9234 append_logical_start(ctx
->block
);
9235 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9237 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9238 if (!ctx
->cf_info
.has_branch
) {
9239 append_logical_end(ctx
->block
);
9240 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9241 /* Discards can result in code running with an empty exec mask.
9242 * This would result in divergent breaks not ever being taken. As a
9243 * workaround, break the loop when the loop mask is empty instead of
9244 * always continuing. */
9245 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9246 unsigned block_idx
= ctx
->block
->index
;
9248 /* create helper blocks to avoid critical edges */
9249 Block
*break_block
= ctx
->program
->create_and_insert_block();
9250 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9251 break_block
->kind
= block_kind_uniform
;
9252 bld
.reset(break_block
);
9253 bld
.branch(aco_opcode::p_branch
);
9254 add_linear_edge(block_idx
, break_block
);
9255 add_linear_edge(break_block
->index
, &loop_exit
);
9257 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9258 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9259 continue_block
->kind
= block_kind_uniform
;
9260 bld
.reset(continue_block
);
9261 bld
.branch(aco_opcode::p_branch
);
9262 add_linear_edge(block_idx
, continue_block
);
9263 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9265 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9266 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9267 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9269 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9270 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9271 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9273 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9276 bld
.reset(ctx
->block
);
9277 bld
.branch(aco_opcode::p_branch
);
9280 /* Fixup phis in loop header from unreachable blocks.
9281 * has_branch/has_divergent_branch also indicates if the loop ends with a
9282 * break/continue instruction, but we don't emit those if unreachable=true */
9284 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9285 bool linear
= ctx
->cf_info
.has_branch
;
9286 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9287 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9288 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9289 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9290 /* the last operand should be the one that needs to be removed */
9291 instr
->operands
.pop_back();
9292 } else if (!is_phi(instr
)) {
9298 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9299 * and the previous one shouldn't both happen at once because a break in the
9300 * merge block would get CSE'd */
9301 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9302 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9303 Operand vals
[num_vals
];
9304 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9305 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9306 if (ctx
->cf_info
.has_branch
)
9307 instr
->operands
.pop_back();
9309 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9310 } else if (!is_phi(instr
)) {
9316 ctx
->cf_info
.has_branch
= false;
9318 // TODO: if the loop has not a single exit, we must add one °°
9319 /* emit loop successor block */
9320 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9321 append_logical_start(ctx
->block
);
9324 // TODO: check if it is beneficial to not branch on continues
9325 /* trim linear phis in loop header */
9326 for (auto&& instr
: loop_entry
->instructions
) {
9327 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9328 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9329 new_phi
->definitions
[0] = instr
->definitions
[0];
9330 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9331 new_phi
->operands
[i
] = instr
->operands
[i
];
9332 /* check that the remaining operands are all the same */
9333 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9334 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9335 instr
.swap(new_phi
);
9336 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9345 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9349 append_logical_end(ctx
->block
);
9350 ctx
->block
->kind
|= block_kind_branch
;
9352 /* branch to linear then block */
9353 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9354 aco_ptr
<Pseudo_branch_instruction
> branch
;
9355 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9356 branch
->operands
[0] = Operand(cond
);
9357 ctx
->block
->instructions
.push_back(std::move(branch
));
9359 ic
->BB_if_idx
= ctx
->block
->index
;
9360 ic
->BB_invert
= Block();
9361 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9362 /* Invert blocks are intentionally not marked as top level because they
9363 * are not part of the logical cfg. */
9364 ic
->BB_invert
.kind
|= block_kind_invert
;
9365 ic
->BB_endif
= Block();
9366 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9367 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9369 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9370 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9371 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9372 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9373 ctx
->cf_info
.parent_if
.is_divergent
= true;
9375 /* divergent branches use cbranch_execz */
9376 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9377 ctx
->cf_info
.exec_potentially_empty_break
= false;
9378 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9380 /** emit logical then block */
9381 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9382 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9383 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9384 ctx
->block
= BB_then_logical
;
9385 append_logical_start(BB_then_logical
);
9388 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9390 Block
*BB_then_logical
= ctx
->block
;
9391 append_logical_end(BB_then_logical
);
9392 /* branch from logical then block to invert block */
9393 aco_ptr
<Pseudo_branch_instruction
> branch
;
9394 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9395 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9396 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9397 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9398 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9399 BB_then_logical
->kind
|= block_kind_uniform
;
9400 assert(!ctx
->cf_info
.has_branch
);
9401 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9402 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9404 /** emit linear then block */
9405 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9406 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9407 BB_then_linear
->kind
|= block_kind_uniform
;
9408 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9409 /* branch from linear then block to invert block */
9410 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9411 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9412 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9414 /** emit invert merge block */
9415 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9416 ic
->invert_idx
= ctx
->block
->index
;
9418 /* branch to linear else block (skip else) */
9419 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9420 branch
->operands
[0] = Operand(ic
->cond
);
9421 ctx
->block
->instructions
.push_back(std::move(branch
));
9423 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9424 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9425 ic
->exec_potentially_empty_break_depth_old
=
9426 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9427 /* divergent branches use cbranch_execz */
9428 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9429 ctx
->cf_info
.exec_potentially_empty_break
= false;
9430 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9432 /** emit logical else block */
9433 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9434 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9435 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9436 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9437 ctx
->block
= BB_else_logical
;
9438 append_logical_start(BB_else_logical
);
9441 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9443 Block
*BB_else_logical
= ctx
->block
;
9444 append_logical_end(BB_else_logical
);
9446 /* branch from logical else block to endif block */
9447 aco_ptr
<Pseudo_branch_instruction
> branch
;
9448 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9449 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9450 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9451 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9452 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9453 BB_else_logical
->kind
|= block_kind_uniform
;
9455 assert(!ctx
->cf_info
.has_branch
);
9456 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9459 /** emit linear else block */
9460 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9461 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9462 BB_else_linear
->kind
|= block_kind_uniform
;
9463 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9465 /* branch from linear else block to endif block */
9466 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9467 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9468 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9471 /** emit endif merge block */
9472 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9473 append_logical_start(ctx
->block
);
9476 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9477 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9478 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9479 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9480 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9481 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9482 !ctx
->cf_info
.parent_if
.is_divergent
) {
9483 ctx
->cf_info
.exec_potentially_empty_break
= false;
9484 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9486 /* uniform control flow never has an empty exec-mask */
9487 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9488 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9489 ctx
->cf_info
.exec_potentially_empty_break
= false;
9490 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9494 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9496 assert(cond
.regClass() == s1
);
9498 append_logical_end(ctx
->block
);
9499 ctx
->block
->kind
|= block_kind_uniform
;
9501 aco_ptr
<Pseudo_branch_instruction
> branch
;
9502 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9503 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9504 branch
->operands
[0] = Operand(cond
);
9505 branch
->operands
[0].setFixed(scc
);
9506 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9508 ic
->BB_if_idx
= ctx
->block
->index
;
9509 ic
->BB_endif
= Block();
9510 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9511 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9513 ctx
->cf_info
.has_branch
= false;
9514 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9516 /** emit then block */
9517 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9518 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9519 add_edge(ic
->BB_if_idx
, BB_then
);
9520 append_logical_start(BB_then
);
9521 ctx
->block
= BB_then
;
9524 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9526 Block
*BB_then
= ctx
->block
;
9528 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9529 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9531 if (!ic
->uniform_has_then_branch
) {
9532 append_logical_end(BB_then
);
9533 /* branch from then block to endif block */
9534 aco_ptr
<Pseudo_branch_instruction
> branch
;
9535 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9536 BB_then
->instructions
.emplace_back(std::move(branch
));
9537 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9538 if (!ic
->then_branch_divergent
)
9539 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9540 BB_then
->kind
|= block_kind_uniform
;
9543 ctx
->cf_info
.has_branch
= false;
9544 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9546 /** emit else block */
9547 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9548 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9549 add_edge(ic
->BB_if_idx
, BB_else
);
9550 append_logical_start(BB_else
);
9551 ctx
->block
= BB_else
;
9554 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9556 Block
*BB_else
= ctx
->block
;
9558 if (!ctx
->cf_info
.has_branch
) {
9559 append_logical_end(BB_else
);
9560 /* branch from then block to endif block */
9561 aco_ptr
<Pseudo_branch_instruction
> branch
;
9562 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9563 BB_else
->instructions
.emplace_back(std::move(branch
));
9564 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9565 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9566 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9567 BB_else
->kind
|= block_kind_uniform
;
9570 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9571 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9573 /** emit endif merge block */
9574 if (!ctx
->cf_info
.has_branch
) {
9575 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9576 append_logical_start(ctx
->block
);
9580 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9582 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9583 Builder
bld(ctx
->program
, ctx
->block
);
9584 aco_ptr
<Pseudo_branch_instruction
> branch
;
9587 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9589 * Uniform conditionals are represented in the following way*) :
9591 * The linear and logical CFG:
9594 * BB_THEN (logical) BB_ELSE (logical)
9598 * *) Exceptions may be due to break and continue statements within loops
9599 * If a break/continue happens within uniform control flow, it branches
9600 * to the loop exit/entry block. Otherwise, it branches to the next
9604 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9605 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9606 cond
= bool_to_scalar_condition(ctx
, cond
);
9608 begin_uniform_if_then(ctx
, &ic
, cond
);
9609 visit_cf_list(ctx
, &if_stmt
->then_list
);
9611 begin_uniform_if_else(ctx
, &ic
);
9612 visit_cf_list(ctx
, &if_stmt
->else_list
);
9614 end_uniform_if(ctx
, &ic
);
9615 } else { /* non-uniform condition */
9617 * To maintain a logical and linear CFG without critical edges,
9618 * non-uniform conditionals are represented in the following way*) :
9623 * BB_THEN (logical) BB_THEN (linear)
9625 * BB_INVERT (linear)
9627 * BB_ELSE (logical) BB_ELSE (linear)
9634 * BB_THEN (logical) BB_ELSE (logical)
9638 * *) Exceptions may be due to break and continue statements within loops
9641 begin_divergent_if_then(ctx
, &ic
, cond
);
9642 visit_cf_list(ctx
, &if_stmt
->then_list
);
9644 begin_divergent_if_else(ctx
, &ic
);
9645 visit_cf_list(ctx
, &if_stmt
->else_list
);
9647 end_divergent_if(ctx
, &ic
);
9650 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9653 static bool visit_cf_list(isel_context
*ctx
,
9654 struct exec_list
*list
)
9656 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9657 switch (node
->type
) {
9658 case nir_cf_node_block
:
9659 visit_block(ctx
, nir_cf_node_as_block(node
));
9661 case nir_cf_node_if
:
9662 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9665 case nir_cf_node_loop
:
9666 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9669 unreachable("unimplemented cf list type");
9675 static void create_null_export(isel_context
*ctx
)
9677 /* Some shader stages always need to have exports.
9678 * So when there is none, we need to add a null export.
9681 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9682 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9683 Builder
bld(ctx
->program
, ctx
->block
);
9684 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9685 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9688 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9690 assert(ctx
->stage
== vertex_vs
||
9691 ctx
->stage
== tess_eval_vs
||
9692 ctx
->stage
== gs_copy_vs
||
9693 ctx
->stage
== ngg_vertex_gs
||
9694 ctx
->stage
== ngg_tess_eval_gs
);
9696 int offset
= (ctx
->stage
& sw_tes
)
9697 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9698 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9699 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9700 if (!is_pos
&& !mask
)
9702 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9704 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9705 exp
->enabled_mask
= mask
;
9706 for (unsigned i
= 0; i
< 4; ++i
) {
9707 if (mask
& (1 << i
))
9708 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9710 exp
->operands
[i
] = Operand(v1
);
9712 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9713 * Setting valid_mask=1 prevents it and has no other effect.
9715 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9717 exp
->compressed
= false;
9719 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9721 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9722 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9727 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9729 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9730 exp
->enabled_mask
= 0;
9731 for (unsigned i
= 0; i
< 4; ++i
)
9732 exp
->operands
[i
] = Operand(v1
);
9733 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9734 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9735 exp
->enabled_mask
|= 0x1;
9737 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9738 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9739 exp
->enabled_mask
|= 0x4;
9741 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9742 if (ctx
->options
->chip_class
< GFX9
) {
9743 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9744 exp
->enabled_mask
|= 0x8;
9746 Builder
bld(ctx
->program
, ctx
->block
);
9748 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9749 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9750 if (exp
->operands
[2].isTemp())
9751 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9753 exp
->operands
[2] = Operand(out
);
9754 exp
->enabled_mask
|= 0x4;
9757 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9759 exp
->compressed
= false;
9760 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9761 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9764 static void create_export_phis(isel_context
*ctx
)
9766 /* Used when exports are needed, but the output temps are defined in a preceding block.
9767 * This function will set up phis in order to access the outputs in the next block.
9770 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9771 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9772 ctx
->block
->instructions
.pop_back();
9774 Builder
bld(ctx
->program
, ctx
->block
);
9776 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9777 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9778 for (unsigned i
= 0; i
< 4; ++i
) {
9779 if (!(mask
& (1 << i
)))
9782 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9783 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9784 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9788 bld
.insert(std::move(logical_start
));
9791 static void create_vs_exports(isel_context
*ctx
)
9793 assert(ctx
->stage
== vertex_vs
||
9794 ctx
->stage
== tess_eval_vs
||
9795 ctx
->stage
== gs_copy_vs
||
9796 ctx
->stage
== ngg_vertex_gs
||
9797 ctx
->stage
== ngg_tess_eval_gs
);
9799 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9800 ? &ctx
->program
->info
->tes
.outinfo
9801 : &ctx
->program
->info
->vs
.outinfo
;
9803 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9804 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9805 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9808 if (ctx
->options
->key
.has_multiview_view_index
) {
9809 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9810 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9813 /* the order these position exports are created is important */
9815 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9816 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9817 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9818 exported_pos
= true;
9820 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9821 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9822 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9823 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9825 if (ctx
->export_clip_dists
) {
9826 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9827 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9828 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9829 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9832 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9833 if (i
< VARYING_SLOT_VAR0
&&
9834 i
!= VARYING_SLOT_LAYER
&&
9835 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9836 i
!= VARYING_SLOT_VIEWPORT
)
9839 export_vs_varying(ctx
, i
, false, NULL
);
9843 create_null_export(ctx
);
9846 static bool export_fs_mrt_z(isel_context
*ctx
)
9848 Builder
bld(ctx
->program
, ctx
->block
);
9849 unsigned enabled_channels
= 0;
9853 for (unsigned i
= 0; i
< 4; ++i
) {
9854 values
[i
] = Operand(v1
);
9857 /* Both stencil and sample mask only need 16-bits. */
9858 if (!ctx
->program
->info
->ps
.writes_z
&&
9859 (ctx
->program
->info
->ps
.writes_stencil
||
9860 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9861 compr
= true; /* COMPR flag */
9863 if (ctx
->program
->info
->ps
.writes_stencil
) {
9864 /* Stencil should be in X[23:16]. */
9865 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9866 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9867 enabled_channels
|= 0x3;
9870 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9871 /* SampleMask should be in Y[15:0]. */
9872 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9873 enabled_channels
|= 0xc;
9876 if (ctx
->program
->info
->ps
.writes_z
) {
9877 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9878 enabled_channels
|= 0x1;
9881 if (ctx
->program
->info
->ps
.writes_stencil
) {
9882 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9883 enabled_channels
|= 0x2;
9886 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9887 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9888 enabled_channels
|= 0x4;
9892 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9893 * writemask component.
9895 if (ctx
->options
->chip_class
== GFX6
&&
9896 ctx
->options
->family
!= CHIP_OLAND
&&
9897 ctx
->options
->family
!= CHIP_HAINAN
) {
9898 enabled_channels
|= 0x1;
9901 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9902 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9907 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9909 Builder
bld(ctx
->program
, ctx
->block
);
9910 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9913 for (unsigned i
= 0; i
< 4; ++i
) {
9914 if (write_mask
& (1 << i
)) {
9915 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9917 values
[i
] = Operand(v1
);
9921 unsigned target
, col_format
;
9922 unsigned enabled_channels
= 0;
9923 aco_opcode compr_op
= (aco_opcode
)0;
9925 slot
-= FRAG_RESULT_DATA0
;
9926 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9927 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9929 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9930 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9931 bool is_16bit
= values
[0].regClass() == v2b
;
9935 case V_028714_SPI_SHADER_ZERO
:
9936 enabled_channels
= 0; /* writemask */
9937 target
= V_008DFC_SQ_EXP_NULL
;
9940 case V_028714_SPI_SHADER_32_R
:
9941 enabled_channels
= 1;
9944 case V_028714_SPI_SHADER_32_GR
:
9945 enabled_channels
= 0x3;
9948 case V_028714_SPI_SHADER_32_AR
:
9949 if (ctx
->options
->chip_class
>= GFX10
) {
9950 /* Special case: on GFX10, the outputs are different for 32_AR */
9951 enabled_channels
= 0x3;
9952 values
[1] = values
[3];
9953 values
[3] = Operand(v1
);
9955 enabled_channels
= 0x9;
9959 case V_028714_SPI_SHADER_FP16_ABGR
:
9960 enabled_channels
= 0x5;
9961 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9963 if (ctx
->options
->chip_class
>= GFX9
) {
9964 /* Pack the FP16 values together instead of converting them to
9965 * FP32 and back to FP16.
9966 * TODO: use p_create_vector and let the compiler optimizes.
9968 compr_op
= aco_opcode::v_pack_b32_f16
;
9970 for (unsigned i
= 0; i
< 4; i
++) {
9971 if ((write_mask
>> i
) & 1)
9972 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9978 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9979 enabled_channels
= 0x5;
9980 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9981 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9983 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9987 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9988 enabled_channels
= 0x5;
9989 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9990 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
9992 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9996 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9997 enabled_channels
= 0x5;
9998 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9999 if (is_int8
|| is_int10
) {
10001 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10002 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10004 for (unsigned i
= 0; i
< 4; i
++) {
10005 if ((write_mask
>> i
) & 1) {
10006 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10007 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10011 } else if (is_16bit
) {
10012 for (unsigned i
= 0; i
< 4; i
++) {
10013 if ((write_mask
>> i
) & 1) {
10014 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, false);
10015 values
[i
] = Operand(tmp
);
10022 case V_028714_SPI_SHADER_SINT16_ABGR
:
10023 enabled_channels
= 0x5;
10024 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10025 if (is_int8
|| is_int10
) {
10027 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10028 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10029 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10030 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10032 for (unsigned i
= 0; i
< 4; i
++) {
10033 if ((write_mask
>> i
) & 1) {
10034 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10035 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10037 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10038 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10042 } else if (is_16bit
) {
10043 for (unsigned i
= 0; i
< 4; i
++) {
10044 if ((write_mask
>> i
) & 1) {
10045 Temp tmp
= convert_int(bld
, values
[i
].getTemp(), 16, 32, true);
10046 values
[i
] = Operand(tmp
);
10052 case V_028714_SPI_SHADER_32_ABGR
:
10053 enabled_channels
= 0xF;
10060 if (target
== V_008DFC_SQ_EXP_NULL
)
10063 if ((bool) compr_op
) {
10064 for (int i
= 0; i
< 2; i
++) {
10065 /* check if at least one of the values to be compressed is enabled */
10066 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10068 enabled_channels
|= enabled
<< (i
*2);
10069 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10070 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10071 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10073 values
[i
] = Operand(v1
);
10076 values
[2] = Operand(v1
);
10077 values
[3] = Operand(v1
);
10079 for (int i
= 0; i
< 4; i
++)
10080 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10083 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10084 enabled_channels
, target
, (bool) compr_op
);
10088 static void create_fs_exports(isel_context
*ctx
)
10090 bool exported
= false;
10092 /* Export depth, stencil and sample mask. */
10093 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10094 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10095 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10096 exported
|= export_fs_mrt_z(ctx
);
10098 /* Export all color render targets. */
10099 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10100 if (ctx
->outputs
.mask
[i
])
10101 exported
|= export_fs_mrt_color(ctx
, i
);
10104 create_null_export(ctx
);
10107 static void write_tcs_tess_factors(isel_context
*ctx
)
10109 unsigned outer_comps
;
10110 unsigned inner_comps
;
10112 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10129 Builder
bld(ctx
->program
, ctx
->block
);
10131 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10132 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10133 bld
.sopp(aco_opcode::s_barrier
);
10135 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10136 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10138 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10139 if_context ic_invocation_id_is_zero
;
10140 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10141 bld
.reset(ctx
->block
);
10143 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10145 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10146 unsigned stride
= inner_comps
+ outer_comps
;
10147 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10151 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10153 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10155 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10156 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10157 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10159 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10160 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10162 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10163 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10164 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10165 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10168 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10169 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10170 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10171 unsigned tf_const_offset
= 0;
10173 if (ctx
->program
->chip_class
<= GFX8
) {
10174 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10175 if_context ic_rel_patch_id_is_zero
;
10176 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10177 bld
.reset(ctx
->block
);
10179 /* Store the dynamic HS control word. */
10180 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10181 bld
.mubuf(aco_opcode::buffer_store_dword
,
10182 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10183 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10184 /* disable_wqm */ false, /* glc */ true);
10185 tf_const_offset
+= 4;
10187 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10188 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10189 bld
.reset(ctx
->block
);
10192 assert(stride
== 2 || stride
== 4 || stride
== 6);
10193 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10194 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10196 /* Store to offchip for TES to read - only if TES reads them */
10197 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10198 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10199 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10201 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10202 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10204 if (likely(inner_comps
)) {
10205 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10206 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10210 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10211 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10214 static void emit_stream_output(isel_context
*ctx
,
10215 Temp
const *so_buffers
,
10216 Temp
const *so_write_offset
,
10217 const struct radv_stream_output
*output
)
10219 unsigned num_comps
= util_bitcount(output
->component_mask
);
10220 unsigned writemask
= (1 << num_comps
) - 1;
10221 unsigned loc
= output
->location
;
10222 unsigned buf
= output
->buffer
;
10224 assert(num_comps
&& num_comps
<= 4);
10225 if (!num_comps
|| num_comps
> 4)
10228 unsigned start
= ffs(output
->component_mask
) - 1;
10231 bool all_undef
= true;
10232 assert(ctx
->stage
& hw_vs
);
10233 for (unsigned i
= 0; i
< num_comps
; i
++) {
10234 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10235 all_undef
= all_undef
&& !out
[i
].id();
10240 while (writemask
) {
10242 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10243 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10244 /* GFX6 doesn't support storing vec3, split it. */
10245 writemask
|= 1u << (start
+ 2);
10249 unsigned offset
= output
->offset
+ start
* 4;
10251 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10252 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10253 for (int i
= 0; i
< count
; ++i
)
10254 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10255 vec
->definitions
[0] = Definition(write_data
);
10256 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10261 opcode
= aco_opcode::buffer_store_dword
;
10264 opcode
= aco_opcode::buffer_store_dwordx2
;
10267 opcode
= aco_opcode::buffer_store_dwordx3
;
10270 opcode
= aco_opcode::buffer_store_dwordx4
;
10273 unreachable("Unsupported dword count.");
10276 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10277 store
->operands
[0] = Operand(so_buffers
[buf
]);
10278 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10279 store
->operands
[2] = Operand((uint32_t) 0);
10280 store
->operands
[3] = Operand(write_data
);
10281 if (offset
> 4095) {
10282 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10283 Builder
bld(ctx
->program
, ctx
->block
);
10284 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10286 store
->offset
= offset
;
10288 store
->offen
= true;
10290 store
->dlc
= false;
10292 store
->can_reorder
= true;
10293 ctx
->block
->instructions
.emplace_back(std::move(store
));
10297 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10299 Builder
bld(ctx
->program
, ctx
->block
);
10301 Temp so_buffers
[4];
10302 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10303 for (unsigned i
= 0; i
< 4; i
++) {
10304 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10308 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10309 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10312 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10313 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10315 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10317 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10320 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10322 bld
.reset(ctx
->block
);
10324 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10326 Temp so_write_offset
[4];
10328 for (unsigned i
= 0; i
< 4; i
++) {
10329 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10334 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10335 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10336 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10337 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10339 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10341 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10342 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10343 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10344 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10348 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10349 struct radv_stream_output
*output
=
10350 &ctx
->program
->info
->so
.outputs
[i
];
10351 if (stream
!= output
->stream
)
10354 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10357 begin_divergent_if_else(ctx
, &ic
);
10358 end_divergent_if(ctx
, &ic
);
10361 } /* end namespace */
10363 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10365 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10366 Builder
bld(ctx
->program
, ctx
->block
);
10367 constexpr unsigned hs_idx
= 1u;
10368 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10369 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10370 Operand((8u << 16) | (hs_idx
* 8u)));
10371 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10373 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10375 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10376 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10377 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10378 ls_has_nonzero_hs_threads
);
10379 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10380 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10381 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10382 ls_has_nonzero_hs_threads
);
10383 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10384 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10385 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10386 ls_has_nonzero_hs_threads
);
10388 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10389 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10390 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10393 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10395 /* Split all arguments except for the first (ring_offsets) and the last
10396 * (exec) so that the dead channels don't stay live throughout the program.
10398 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10399 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10400 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10401 startpgm
->definitions
[i
].regClass().size());
10406 void handle_bc_optimize(isel_context
*ctx
)
10408 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10409 Builder
bld(ctx
->program
, ctx
->block
);
10410 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10411 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10412 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10413 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10414 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10415 if (uses_center
&& uses_centroid
) {
10416 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10417 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10419 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10421 for (unsigned i
= 0; i
< 2; i
++) {
10422 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10423 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10424 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10425 persp_centroid
, persp_center
, sel
);
10427 ctx
->persp_centroid
= bld
.tmp(v2
);
10428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10429 Operand(new_coord
[0]), Operand(new_coord
[1]));
10430 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10433 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10435 for (unsigned i
= 0; i
< 2; i
++) {
10436 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10437 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10438 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10439 linear_centroid
, linear_center
, sel
);
10441 ctx
->linear_centroid
= bld
.tmp(v2
);
10442 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10443 Operand(new_coord
[0]), Operand(new_coord
[1]));
10444 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10449 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10451 Program
*program
= ctx
->program
;
10453 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10455 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10456 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10457 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10458 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10459 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10461 program
->next_fp_mode
.must_flush_denorms32
=
10462 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10463 program
->next_fp_mode
.must_flush_denorms16_64
=
10464 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10465 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10467 program
->next_fp_mode
.care_about_round32
=
10468 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10470 program
->next_fp_mode
.care_about_round16_64
=
10471 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10472 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10474 /* default to preserving fp16 and fp64 denorms, since it's free */
10475 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10476 program
->next_fp_mode
.denorm16_64
= 0;
10478 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10480 /* preserving fp32 denorms is expensive, so only do it if asked */
10481 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10482 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10484 program
->next_fp_mode
.denorm32
= 0;
10486 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10487 program
->next_fp_mode
.round32
= fp_round_tz
;
10489 program
->next_fp_mode
.round32
= fp_round_ne
;
10491 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10492 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10494 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10496 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10499 void cleanup_cfg(Program
*program
)
10501 /* create linear_succs/logical_succs */
10502 for (Block
& BB
: program
->blocks
) {
10503 for (unsigned idx
: BB
.linear_preds
)
10504 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10505 for (unsigned idx
: BB
.logical_preds
)
10506 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10510 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10512 Builder
bld(ctx
->program
, ctx
->block
);
10514 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10515 Temp count
= i
== 0
10516 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10517 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10518 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10520 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10523 if (ctx
->program
->wave_size
== 64) {
10524 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10525 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10526 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10528 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10529 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10535 bool ngg_early_prim_export(isel_context
*ctx
)
10537 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10541 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10543 Builder
bld(ctx
->program
, ctx
->block
);
10545 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10546 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10548 /* Get the id of the current wave within the threadgroup (workgroup) */
10549 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10550 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10552 /* Execute the following code only on the first wave (wave id 0),
10553 * use the SCC def to tell if the wave id is zero or not.
10555 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10557 begin_uniform_if_then(ctx
, &ic
, cond
);
10558 begin_uniform_if_else(ctx
, &ic
);
10559 bld
.reset(ctx
->block
);
10561 /* Number of vertices output by VS/TES */
10562 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10563 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10564 /* Number of primitives output by VS/TES */
10565 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10566 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10568 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10569 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10570 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10572 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10573 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10575 end_uniform_if(ctx
, &ic
);
10577 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10578 bld
.reset(ctx
->block
);
10579 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10582 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10584 Builder
bld(ctx
->program
, ctx
->block
);
10586 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10587 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10590 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10593 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10594 assert(vtxindex
[i
].id());
10597 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10601 /* The initial edge flag is always false in tess eval shaders. */
10602 if (ctx
->stage
== ngg_vertex_gs
) {
10603 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10604 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10608 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10613 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10615 Builder
bld(ctx
->program
, ctx
->block
);
10616 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10618 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10619 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10620 false /* compressed */, true/* done */, false /* valid mask */);
10623 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10625 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10626 * These must always come before VS exports.
10628 * It is recommended to do these as early as possible. They can be at the beginning when
10629 * there is no SW GS and the shader doesn't write edge flags.
10633 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10634 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10636 Builder
bld(ctx
->program
, ctx
->block
);
10637 constexpr unsigned max_vertices_per_primitive
= 3;
10638 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10640 if (ctx
->stage
== ngg_vertex_gs
) {
10641 /* TODO: optimize for points & lines */
10642 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10643 if (ctx
->shader
->info
.tess
.point_mode
)
10644 num_vertices_per_primitive
= 1;
10645 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10646 num_vertices_per_primitive
= 2;
10648 unreachable("Unsupported NGG shader stage");
10651 Temp vtxindex
[max_vertices_per_primitive
];
10652 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10653 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10654 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10655 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10656 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10657 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10658 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10659 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10661 /* Export primitive data to the index buffer. */
10662 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10664 /* Export primitive ID. */
10665 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10666 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10667 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10668 Temp provoking_vtx_index
= vtxindex
[0];
10669 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10671 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10674 begin_divergent_if_else(ctx
, &ic
);
10675 end_divergent_if(ctx
, &ic
);
10678 void ngg_emit_nogs_output(isel_context
*ctx
)
10680 /* Emits NGG GS output, for stages that don't have SW GS. */
10683 Builder
bld(ctx
->program
, ctx
->block
);
10684 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10686 /* NGG streamout is currently disabled by default. */
10687 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10689 if (late_prim_export
) {
10690 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10691 create_export_phis(ctx
);
10692 /* Do what we need to do in the GS threads. */
10693 ngg_emit_nogs_gsthreads(ctx
);
10695 /* What comes next should be executed on ES threads. */
10696 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10697 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10698 bld
.reset(ctx
->block
);
10701 /* Export VS outputs */
10702 ctx
->block
->kind
|= block_kind_export_end
;
10703 create_vs_exports(ctx
);
10705 /* Export primitive ID */
10706 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10709 if (ctx
->stage
== ngg_vertex_gs
) {
10710 /* Wait for GS threads to store primitive ID in LDS. */
10711 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10712 bld
.sopp(aco_opcode::s_barrier
);
10714 /* Calculate LDS address where the GS threads stored the primitive ID. */
10715 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10716 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10717 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10718 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10719 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10720 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10722 /* Load primitive ID from LDS. */
10723 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10724 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10725 /* TES: Just use the patch ID as the primitive ID. */
10726 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10728 unreachable("unsupported NGG shader stage.");
10731 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10732 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10734 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10737 if (late_prim_export
) {
10738 begin_divergent_if_else(ctx
, &ic
);
10739 end_divergent_if(ctx
, &ic
);
10740 bld
.reset(ctx
->block
);
10744 void select_program(Program
*program
,
10745 unsigned shader_count
,
10746 struct nir_shader
*const *shaders
,
10747 ac_shader_config
* config
,
10748 struct radv_shader_args
*args
)
10750 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10751 if_context ic_merged_wave_info
;
10752 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10754 for (unsigned i
= 0; i
< shader_count
; i
++) {
10755 nir_shader
*nir
= shaders
[i
];
10756 init_context(&ctx
, nir
);
10758 setup_fp_mode(&ctx
, nir
);
10761 /* needs to be after init_context() for FS */
10762 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10763 append_logical_start(ctx
.block
);
10765 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10766 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10768 split_arguments(&ctx
, startpgm
);
10772 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10774 if (ngg_early_prim_export(&ctx
))
10775 ngg_emit_nogs_gsthreads(&ctx
);
10778 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10779 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10780 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10781 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10782 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10783 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10784 ctx
.stage
== tess_eval_geometry_gs
));
10786 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10787 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10788 if (check_merged_wave_info
) {
10789 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10790 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10794 Builder
bld(ctx
.program
, ctx
.block
);
10796 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10797 bld
.sopp(aco_opcode::s_barrier
);
10799 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10800 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10802 } else if (ctx
.stage
== geometry_gs
)
10803 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10805 if (ctx
.stage
== fragment_fs
)
10806 handle_bc_optimize(&ctx
);
10808 visit_cf_list(&ctx
, &func
->body
);
10810 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10811 emit_streamout(&ctx
, 0);
10813 if (ctx
.stage
& hw_vs
) {
10814 create_vs_exports(&ctx
);
10815 ctx
.block
->kind
|= block_kind_export_end
;
10816 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10817 ngg_emit_nogs_output(&ctx
);
10818 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10819 Builder
bld(ctx
.program
, ctx
.block
);
10820 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10821 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10822 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10823 write_tcs_tess_factors(&ctx
);
10826 if (ctx
.stage
== fragment_fs
) {
10827 create_fs_exports(&ctx
);
10828 ctx
.block
->kind
|= block_kind_export_end
;
10831 if (endif_merged_wave_info
) {
10832 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10833 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10836 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10837 ngg_emit_nogs_output(&ctx
);
10839 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10840 /* Outputs of the previous stage are inputs to the next stage */
10841 ctx
.inputs
= ctx
.outputs
;
10842 ctx
.outputs
= shader_io_state();
10846 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10848 append_logical_end(ctx
.block
);
10849 ctx
.block
->kind
|= block_kind_uniform
;
10850 Builder
bld(ctx
.program
, ctx
.block
);
10851 if (ctx
.program
->wb_smem_l1_on_end
)
10852 bld
.smem(aco_opcode::s_dcache_wb
, false);
10853 bld
.sopp(aco_opcode::s_endpgm
);
10855 cleanup_cfg(program
);
10858 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10859 ac_shader_config
* config
,
10860 struct radv_shader_args
*args
)
10862 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10864 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10865 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10866 program
->next_fp_mode
.must_flush_denorms32
= false;
10867 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10868 program
->next_fp_mode
.care_about_round32
= false;
10869 program
->next_fp_mode
.care_about_round16_64
= false;
10870 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10871 program
->next_fp_mode
.denorm32
= 0;
10872 program
->next_fp_mode
.round32
= fp_round_ne
;
10873 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10874 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10876 add_startpgm(&ctx
);
10877 append_logical_start(ctx
.block
);
10879 Builder
bld(ctx
.program
, ctx
.block
);
10881 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10883 Operand
stream_id(0u);
10884 if (args
->shader_info
->so
.num_outputs
)
10885 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10886 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10888 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10890 std::stack
<Block
> endif_blocks
;
10892 for (unsigned stream
= 0; stream
< 4; stream
++) {
10893 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10896 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10897 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10900 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10902 unsigned BB_if_idx
= ctx
.block
->index
;
10903 Block BB_endif
= Block();
10904 if (!stream_id
.isConstant()) {
10906 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10907 append_logical_end(ctx
.block
);
10908 ctx
.block
->kind
|= block_kind_uniform
;
10909 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10911 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10913 ctx
.block
= ctx
.program
->create_and_insert_block();
10914 add_edge(BB_if_idx
, ctx
.block
);
10915 bld
.reset(ctx
.block
);
10916 append_logical_start(ctx
.block
);
10919 unsigned offset
= 0;
10920 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10921 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10924 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10925 unsigned length
= util_last_bit(output_usage_mask
);
10926 for (unsigned j
= 0; j
< length
; ++j
) {
10927 if (!(output_usage_mask
& (1 << j
)))
10930 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10931 Temp voffset
= vtx_offset
;
10932 if (const_offset
>= 4096u) {
10933 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10934 const_offset
%= 4096u;
10937 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10938 mubuf
->definitions
[0] = bld
.def(v1
);
10939 mubuf
->operands
[0] = Operand(gsvs_ring
);
10940 mubuf
->operands
[1] = Operand(voffset
);
10941 mubuf
->operands
[2] = Operand(0u);
10942 mubuf
->offen
= true;
10943 mubuf
->offset
= const_offset
;
10946 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10947 mubuf
->barrier
= barrier_none
;
10948 mubuf
->can_reorder
= true;
10950 ctx
.outputs
.mask
[i
] |= 1 << j
;
10951 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10953 bld
.insert(std::move(mubuf
));
10959 if (args
->shader_info
->so
.num_outputs
) {
10960 emit_streamout(&ctx
, stream
);
10961 bld
.reset(ctx
.block
);
10965 create_vs_exports(&ctx
);
10966 ctx
.block
->kind
|= block_kind_export_end
;
10969 if (!stream_id
.isConstant()) {
10970 append_logical_end(ctx
.block
);
10972 /* branch from then block to endif block */
10973 bld
.branch(aco_opcode::p_branch
);
10974 add_edge(ctx
.block
->index
, &BB_endif
);
10975 ctx
.block
->kind
|= block_kind_uniform
;
10977 /* emit else block */
10978 ctx
.block
= ctx
.program
->create_and_insert_block();
10979 add_edge(BB_if_idx
, ctx
.block
);
10980 bld
.reset(ctx
.block
);
10981 append_logical_start(ctx
.block
);
10983 endif_blocks
.push(std::move(BB_endif
));
10987 while (!endif_blocks
.empty()) {
10988 Block BB_endif
= std::move(endif_blocks
.top());
10989 endif_blocks
.pop();
10991 Block
*BB_else
= ctx
.block
;
10993 append_logical_end(BB_else
);
10994 /* branch from else block to endif block */
10995 bld
.branch(aco_opcode::p_branch
);
10996 add_edge(BB_else
->index
, &BB_endif
);
10997 BB_else
->kind
|= block_kind_uniform
;
10999 /** emit endif merge block */
11000 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11001 bld
.reset(ctx
.block
);
11002 append_logical_start(ctx
.block
);
11005 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11007 append_logical_end(ctx
.block
);
11008 ctx
.block
->kind
|= block_kind_uniform
;
11009 bld
.sopp(aco_opcode::s_endpgm
);
11011 cleanup_cfg(program
);