2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
418 Builder
bld(ctx
->program
, ctx
->block
);
419 if (offset
.isTemp()) {
420 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
422 if (vec
.size() == 4) {
423 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
425 } else if (vec
.size() == 3) {
426 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
428 } else if (vec
.size() == 2) {
429 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
432 for (unsigned i
= 0; i
< dst
.size(); i
++)
433 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
437 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
439 offset
= Operand(0u);
442 unsigned num_components
= dst
.bytes() / component_size
;
443 if (vec
.regClass() == dst
.regClass()) {
444 assert(offset
.constantValue() == 0);
445 bld
.copy(Definition(dst
), vec
);
446 emit_split_vector(ctx
, dst
, num_components
);
450 emit_split_vector(ctx
, vec
, vec
.bytes() / component_size
);
451 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
452 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
454 assert(offset
.constantValue() % component_size
== 0);
455 unsigned skip
= offset
.constantValue() / component_size
;
456 for (unsigned i
= 0; i
< num_components
; i
++)
457 elems
[i
] = emit_extract_vector(ctx
, vec
, i
+ skip
, rc
);
459 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
460 if (dst
.type() == RegType::vgpr
) {
461 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
462 for (unsigned i
= 0; i
< num_components
; i
++)
463 create_vec
->operands
[i
] = Operand(elems
[i
]);
464 create_vec
->definitions
[0] = Definition(dst
);
465 bld
.insert(std::move(create_vec
));
467 /* if dst is sgpr - split the src, but move the original to sgpr. */
469 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
470 byte_align_scalar(ctx
, vec
, offset
, dst
);
472 assert(dst
.size() == vec
.size());
473 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
476 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
479 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
481 Builder
bld(ctx
->program
, ctx
->block
);
483 dst
= bld
.tmp(bld
.lm
);
485 assert(val
.regClass() == s1
);
486 assert(dst
.regClass() == bld
.lm
);
488 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
491 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
493 Builder
bld(ctx
->program
, ctx
->block
);
497 assert(val
.regClass() == bld
.lm
);
498 assert(dst
.regClass() == s1
);
500 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
501 Temp tmp
= bld
.tmp(s1
);
502 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
503 return emit_wqm(ctx
, tmp
, dst
);
506 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
508 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
509 return get_ssa_temp(ctx
, src
.src
.ssa
);
511 if (src
.src
.ssa
->num_components
== size
) {
512 bool identity_swizzle
= true;
513 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
514 if (src
.swizzle
[i
] != i
)
515 identity_swizzle
= false;
517 if (identity_swizzle
)
518 return get_ssa_temp(ctx
, src
.src
.ssa
);
521 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
522 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
523 assert(elem_size
> 0);
524 assert(vec
.bytes() % elem_size
== 0);
526 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
527 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
529 unsigned swizzle
= src
.swizzle
[0];
530 if (vec
.size() > 1) {
531 assert(src
.src
.ssa
->bit_size
== 16);
532 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
533 swizzle
= swizzle
& 1;
538 Temp dst
{ctx
->program
->allocateId(), s1
};
539 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
540 bfe
->operands
[0] = Operand(vec
);
541 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
542 bfe
->definitions
[0] = Definition(dst
);
543 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
544 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
548 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
550 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
553 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
554 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
555 for (unsigned i
= 0; i
< size
; ++i
) {
556 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
557 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
559 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
560 vec_instr
->definitions
[0] = Definition(dst
);
561 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
562 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
567 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
571 Builder
bld(ctx
->program
, ctx
->block
);
572 if (ptr
.type() == RegType::vgpr
)
573 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
574 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
575 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
578 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
580 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
581 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
582 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
583 sop2
->definitions
[0] = Definition(dst
);
585 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
586 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
589 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
590 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
592 Builder
bld(ctx
->program
, ctx
->block
);
593 bld
.is_precise
= instr
->exact
;
595 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
596 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
597 if (src1
.type() == RegType::sgpr
) {
598 if (commutative
&& src0
.type() == RegType::vgpr
) {
603 src1
= as_vgpr(ctx
, src1
);
607 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
608 assert(dst
.size() == 1);
609 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
610 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
612 bld
.vop2(op
, Definition(dst
), src0
, src1
);
616 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
617 aco_opcode op
, Temp dst
)
619 Builder
bld(ctx
->program
, ctx
->block
);
620 bld
.is_precise
= instr
->exact
;
622 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
623 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
625 if (src1
.type() == RegType::sgpr
) {
626 assert(src0
.type() == RegType::vgpr
);
627 std::swap(src0
, src1
);
630 Temp src00
= bld
.tmp(src0
.type(), 1);
631 Temp src01
= bld
.tmp(src0
.type(), 1);
632 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
633 Temp src10
= bld
.tmp(v1
);
634 Temp src11
= bld
.tmp(v1
);
635 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
636 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
637 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
638 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
641 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
642 bool flush_denorms
= false)
644 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
645 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
646 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
648 /* ensure that the instruction has at most 1 sgpr operand
649 * The optimizer will inline constants for us */
650 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
651 src0
= as_vgpr(ctx
, src0
);
652 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
653 src1
= as_vgpr(ctx
, src1
);
654 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
655 src2
= as_vgpr(ctx
, src2
);
657 Builder
bld(ctx
->program
, ctx
->block
);
658 bld
.is_precise
= instr
->exact
;
659 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
660 assert(dst
.size() == 1);
661 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
662 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
664 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
668 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
670 Builder
bld(ctx
->program
, ctx
->block
);
671 bld
.is_precise
= instr
->exact
;
672 if (dst
.type() == RegType::sgpr
)
673 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
674 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
676 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
679 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
682 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
683 assert(src0
.size() == src1
.size());
685 aco_ptr
<Instruction
> vopc
;
686 if (src1
.type() == RegType::sgpr
) {
687 if (src0
.type() == RegType::vgpr
) {
688 /* to swap the operands, we might also have to change the opcode */
690 case aco_opcode::v_cmp_lt_f16
:
691 op
= aco_opcode::v_cmp_gt_f16
;
693 case aco_opcode::v_cmp_ge_f16
:
694 op
= aco_opcode::v_cmp_le_f16
;
696 case aco_opcode::v_cmp_lt_i16
:
697 op
= aco_opcode::v_cmp_gt_i16
;
699 case aco_opcode::v_cmp_ge_i16
:
700 op
= aco_opcode::v_cmp_le_i16
;
702 case aco_opcode::v_cmp_lt_u16
:
703 op
= aco_opcode::v_cmp_gt_u16
;
705 case aco_opcode::v_cmp_ge_u16
:
706 op
= aco_opcode::v_cmp_le_u16
;
708 case aco_opcode::v_cmp_lt_f32
:
709 op
= aco_opcode::v_cmp_gt_f32
;
711 case aco_opcode::v_cmp_ge_f32
:
712 op
= aco_opcode::v_cmp_le_f32
;
714 case aco_opcode::v_cmp_lt_i32
:
715 op
= aco_opcode::v_cmp_gt_i32
;
717 case aco_opcode::v_cmp_ge_i32
:
718 op
= aco_opcode::v_cmp_le_i32
;
720 case aco_opcode::v_cmp_lt_u32
:
721 op
= aco_opcode::v_cmp_gt_u32
;
723 case aco_opcode::v_cmp_ge_u32
:
724 op
= aco_opcode::v_cmp_le_u32
;
726 case aco_opcode::v_cmp_lt_f64
:
727 op
= aco_opcode::v_cmp_gt_f64
;
729 case aco_opcode::v_cmp_ge_f64
:
730 op
= aco_opcode::v_cmp_le_f64
;
732 case aco_opcode::v_cmp_lt_i64
:
733 op
= aco_opcode::v_cmp_gt_i64
;
735 case aco_opcode::v_cmp_ge_i64
:
736 op
= aco_opcode::v_cmp_le_i64
;
738 case aco_opcode::v_cmp_lt_u64
:
739 op
= aco_opcode::v_cmp_gt_u64
;
741 case aco_opcode::v_cmp_ge_u64
:
742 op
= aco_opcode::v_cmp_le_u64
;
744 default: /* eq and ne are commutative */
751 src1
= as_vgpr(ctx
, src1
);
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
759 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
762 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
763 Builder
bld(ctx
->program
, ctx
->block
);
765 assert(dst
.regClass() == bld
.lm
);
766 assert(src0
.type() == RegType::sgpr
);
767 assert(src1
.type() == RegType::sgpr
);
768 assert(src0
.regClass() == src1
.regClass());
770 /* Emit the SALU comparison instruction */
771 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
772 /* Turn the result into a per-lane bool */
773 bool_to_vector_condition(ctx
, cmp
, dst
);
776 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
777 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
779 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
780 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
781 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
782 nir_dest_is_divergent(instr
->dest
.dest
) ||
783 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
784 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
785 aco_opcode op
= use_valu
? v_op
: s_op
;
786 assert(op
!= aco_opcode::num_opcodes
);
787 assert(dst
.regClass() == ctx
->program
->lane_mask
);
790 emit_vopc_instruction(ctx
, instr
, op
, dst
);
792 emit_sopc_instruction(ctx
, instr
, op
, dst
);
795 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
797 Builder
bld(ctx
->program
, ctx
->block
);
798 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
799 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
801 assert(dst
.regClass() == bld
.lm
);
802 assert(src0
.regClass() == bld
.lm
);
803 assert(src1
.regClass() == bld
.lm
);
805 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
808 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
810 Builder
bld(ctx
->program
, ctx
->block
);
811 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
812 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
813 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
815 assert(cond
.regClass() == bld
.lm
);
817 if (dst
.type() == RegType::vgpr
) {
818 aco_ptr
<Instruction
> bcsel
;
819 if (dst
.size() == 1) {
820 then
= as_vgpr(ctx
, then
);
821 els
= as_vgpr(ctx
, els
);
823 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
824 } else if (dst
.size() == 2) {
825 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
826 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
827 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
828 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
830 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
831 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
833 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
836 nir_print_instr(&instr
->instr
, stderr
);
837 fprintf(stderr
, "\n");
842 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
843 assert(dst
.regClass() == bld
.lm
);
844 assert(then
.regClass() == bld
.lm
);
845 assert(els
.regClass() == bld
.lm
);
848 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
849 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
850 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
851 assert(dst
.size() == then
.size());
852 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
853 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
855 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
856 nir_print_instr(&instr
->instr
, stderr
);
857 fprintf(stderr
, "\n");
862 /* divergent boolean bcsel
863 * this implements bcsel on bools: dst = s0 ? s1 : s2
864 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
865 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
867 if (cond
.id() != then
.id())
868 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
870 if (cond
.id() == els
.id())
871 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
873 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
874 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
877 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
878 aco_opcode op
, uint32_t undo
)
880 /* multiply by 16777216 to handle denormals */
881 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
882 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
883 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
884 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
885 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
887 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
889 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
892 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
894 if (ctx
->block
->fp_mode
.denorm32
== 0) {
895 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
899 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
902 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
904 if (ctx
->block
->fp_mode
.denorm32
== 0) {
905 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
909 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
912 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
914 if (ctx
->block
->fp_mode
.denorm32
== 0) {
915 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
919 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
922 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
924 if (ctx
->block
->fp_mode
.denorm32
== 0) {
925 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
929 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
932 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
934 if (ctx
->options
->chip_class
>= GFX7
)
935 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
937 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
938 /* TODO: create more efficient code! */
939 if (val
.type() == RegType::sgpr
)
940 val
= as_vgpr(ctx
, val
);
942 /* Split the input value. */
943 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
944 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
946 /* Extract the exponent and compute the unbiased value. */
947 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
948 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
950 /* Extract the fractional part. */
951 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
952 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
954 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
957 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
958 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
959 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
960 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
961 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
963 /* Get the sign bit. */
964 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
966 /* Decide the operation to apply depending on the unbiased exponent. */
967 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
968 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
969 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
970 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
971 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
972 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
974 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
977 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
979 if (ctx
->options
->chip_class
>= GFX7
)
980 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
982 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
983 * lowered at NIR level for precision reasons). */
984 Temp src0
= as_vgpr(ctx
, val
);
986 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
987 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
989 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
990 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
991 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
993 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
995 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
996 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
998 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
999 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1001 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1003 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1004 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1006 return add
->definitions
[0].getTemp();
1009 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
1011 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
1012 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
1014 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
1017 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
1018 return bld
.copy(Definition(dst
), src
);
1019 else if (dst
.bytes() < src
.bytes())
1020 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
1024 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
1027 } else if (src
.regClass() == s1
) {
1029 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
1031 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
1032 } else if (ctx
->options
->chip_class
>= GFX8
) {
1033 assert(src_bits
!= 8 || src
.regClass() == v1b
);
1034 assert(src_bits
!= 16 || src
.regClass() == v2b
);
1035 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
1036 sdwa
->operands
[0] = Operand(src
);
1037 sdwa
->definitions
[0] = Definition(tmp
);
1039 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
1041 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
1042 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
1043 bld
.insert(std::move(sdwa
));
1045 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
1046 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
1047 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
1050 if (dst_bits
== 64) {
1051 if (is_signed
&& dst
.regClass() == s2
) {
1052 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
1053 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1054 } else if (is_signed
&& dst
.regClass() == v2
) {
1055 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
1056 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
1058 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1065 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1067 if (!instr
->dest
.dest
.is_ssa
) {
1068 fprintf(stderr
, "nir alu dst not in ssa: ");
1069 nir_print_instr(&instr
->instr
, stderr
);
1070 fprintf(stderr
, "\n");
1073 Builder
bld(ctx
->program
, ctx
->block
);
1074 bld
.is_precise
= instr
->exact
;
1075 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1080 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1081 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1082 for (unsigned i
= 0; i
< num
; ++i
)
1083 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1085 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1086 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1087 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1088 for (unsigned i
= 0; i
< num
; ++i
) {
1089 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1090 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1092 vec
->operands
[i
] = Operand
{elems
[i
]};
1094 vec
->definitions
[0] = Definition(dst
);
1095 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1096 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1098 // TODO: that is a bit suboptimal..
1099 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1100 for (unsigned i
= 0; i
< num
- 1; ++i
)
1101 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1102 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1103 for (unsigned i
= 0; i
< num
; ++i
) {
1104 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1105 if (bit
% 32 == 0) {
1106 elems
[bit
/ 32] = elems
[i
];
1108 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1109 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1110 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1113 if (dst
.size() == 1)
1114 bld
.copy(Definition(dst
), elems
[0]);
1116 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1122 aco_ptr
<Instruction
> mov
;
1123 if (dst
.type() == RegType::sgpr
) {
1124 if (src
.type() == RegType::vgpr
)
1125 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1126 else if (src
.regClass() == s1
)
1127 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1128 else if (src
.regClass() == s2
)
1129 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1131 unreachable("wrong src register class for nir_op_imov");
1133 if (dst
.regClass() == v1
)
1134 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1135 else if (dst
.regClass() == v1b
||
1136 dst
.regClass() == v2b
||
1137 dst
.regClass() == v2
)
1138 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1140 unreachable("wrong src register class for nir_op_imov");
1145 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1146 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1147 assert(src
.regClass() == bld
.lm
);
1148 assert(dst
.regClass() == bld
.lm
);
1149 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1150 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1151 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1152 } else if (dst
.regClass() == v1
) {
1153 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1154 } else if (dst
.regClass() == v2
) {
1155 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1156 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1157 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1158 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1159 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1160 } else if (dst
.type() == RegType::sgpr
) {
1161 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1162 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1164 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1165 nir_print_instr(&instr
->instr
, stderr
);
1166 fprintf(stderr
, "\n");
1171 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1172 if (dst
.regClass() == v1
) {
1173 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1174 } else if (dst
.regClass() == s1
) {
1175 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1176 } else if (dst
.size() == 2) {
1177 Temp src0
= bld
.tmp(dst
.type(), 1);
1178 Temp src1
= bld
.tmp(dst
.type(), 1);
1179 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1181 if (dst
.regClass() == s2
) {
1182 Temp carry
= bld
.tmp(s1
);
1183 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1184 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1185 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1187 Temp lower
= bld
.tmp(v1
);
1188 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1189 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1194 nir_print_instr(&instr
->instr
, stderr
);
1195 fprintf(stderr
, "\n");
1200 if (dst
.regClass() == s1
) {
1201 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1202 } else if (dst
.regClass() == v1
) {
1203 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1204 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1206 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1207 nir_print_instr(&instr
->instr
, stderr
);
1208 fprintf(stderr
, "\n");
1212 case nir_op_isign
: {
1213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1214 if (dst
.regClass() == s1
) {
1215 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1216 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1217 } else if (dst
.regClass() == s2
) {
1218 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1220 if (ctx
->program
->chip_class
>= GFX8
)
1221 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1223 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1224 /* SCC gets zero-extended to 64 bit */
1225 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1226 } else if (dst
.regClass() == v1
) {
1227 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1228 } else if (dst
.regClass() == v2
) {
1229 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1230 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1231 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1232 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1233 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1234 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1236 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1237 nir_print_instr(&instr
->instr
, stderr
);
1238 fprintf(stderr
, "\n");
1243 if (dst
.regClass() == v1
) {
1244 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1245 } else if (dst
.regClass() == s1
) {
1246 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1248 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1249 nir_print_instr(&instr
->instr
, stderr
);
1250 fprintf(stderr
, "\n");
1255 if (dst
.regClass() == v1
) {
1256 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1257 } else if (dst
.regClass() == s1
) {
1258 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1267 if (dst
.regClass() == v1
) {
1268 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1269 } else if (dst
.regClass() == s1
) {
1270 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1272 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1273 nir_print_instr(&instr
->instr
, stderr
);
1274 fprintf(stderr
, "\n");
1279 if (dst
.regClass() == v1
) {
1280 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1281 } else if (dst
.regClass() == s1
) {
1282 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1284 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1285 nir_print_instr(&instr
->instr
, stderr
);
1286 fprintf(stderr
, "\n");
1291 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1292 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1293 } else if (dst
.regClass() == v1
) {
1294 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1295 } else if (dst
.regClass() == v2
) {
1296 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1297 } else if (dst
.regClass() == s1
) {
1298 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1299 } else if (dst
.regClass() == s2
) {
1300 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1302 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1303 nir_print_instr(&instr
->instr
, stderr
);
1304 fprintf(stderr
, "\n");
1309 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1310 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1311 } else if (dst
.regClass() == v1
) {
1312 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1313 } else if (dst
.regClass() == v2
) {
1314 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1315 } else if (dst
.regClass() == s1
) {
1316 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1317 } else if (dst
.regClass() == s2
) {
1318 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1320 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1321 nir_print_instr(&instr
->instr
, stderr
);
1322 fprintf(stderr
, "\n");
1327 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1328 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1329 } else if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1331 } else if (dst
.regClass() == v2
) {
1332 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1333 } else if (dst
.regClass() == s1
) {
1334 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1335 } else if (dst
.regClass() == s2
) {
1336 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1345 if (dst
.regClass() == v1
) {
1346 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1347 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1348 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1349 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1350 } else if (dst
.regClass() == v2
) {
1351 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1352 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1353 } else if (dst
.regClass() == s2
) {
1354 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1358 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1359 nir_print_instr(&instr
->instr
, stderr
);
1360 fprintf(stderr
, "\n");
1365 if (dst
.regClass() == v1
) {
1366 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1367 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1368 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1369 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1370 } else if (dst
.regClass() == v2
) {
1371 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1372 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1373 } else if (dst
.regClass() == s1
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1375 } else if (dst
.regClass() == s2
) {
1376 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1378 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1379 nir_print_instr(&instr
->instr
, stderr
);
1380 fprintf(stderr
, "\n");
1385 if (dst
.regClass() == v1
) {
1386 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1387 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1388 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1389 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1390 } else if (dst
.regClass() == v2
) {
1391 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1392 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1393 } else if (dst
.regClass() == s1
) {
1394 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1395 } else if (dst
.regClass() == s2
) {
1396 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1398 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1399 nir_print_instr(&instr
->instr
, stderr
);
1400 fprintf(stderr
, "\n");
1404 case nir_op_find_lsb
: {
1405 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1406 if (src
.regClass() == s1
) {
1407 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1408 } else if (src
.regClass() == v1
) {
1409 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1410 } else if (src
.regClass() == s2
) {
1411 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1413 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1414 nir_print_instr(&instr
->instr
, stderr
);
1415 fprintf(stderr
, "\n");
1419 case nir_op_ufind_msb
:
1420 case nir_op_ifind_msb
: {
1421 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1422 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1423 aco_opcode op
= src
.regClass() == s2
?
1424 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1425 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1426 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1428 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1429 Operand(src
.size() * 32u - 1u), msb_rev
);
1430 Temp msb
= sub
.def(0).getTemp();
1431 Temp carry
= sub
.def(1).getTemp();
1433 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1434 } else if (src
.regClass() == v1
) {
1435 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1436 Temp msb_rev
= bld
.tmp(v1
);
1437 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1438 Temp msb
= bld
.tmp(v1
);
1439 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1440 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_bitfield_reverse
: {
1449 if (dst
.regClass() == s1
) {
1450 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1451 } else if (dst
.regClass() == v1
) {
1452 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1454 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1455 nir_print_instr(&instr
->instr
, stderr
);
1456 fprintf(stderr
, "\n");
1461 if (dst
.regClass() == s1
) {
1462 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1466 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1467 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1468 if (dst
.regClass() == v1
) {
1469 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1473 assert(src0
.size() == 2 && src1
.size() == 2);
1474 Temp src00
= bld
.tmp(src0
.type(), 1);
1475 Temp src01
= bld
.tmp(dst
.type(), 1);
1476 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1477 Temp src10
= bld
.tmp(src1
.type(), 1);
1478 Temp src11
= bld
.tmp(dst
.type(), 1);
1479 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1481 if (dst
.regClass() == s2
) {
1482 Temp carry
= bld
.tmp(s1
);
1483 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1484 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1485 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1486 } else if (dst
.regClass() == v2
) {
1487 Temp dst0
= bld
.tmp(v1
);
1488 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1489 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1490 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1492 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1493 nir_print_instr(&instr
->instr
, stderr
);
1494 fprintf(stderr
, "\n");
1498 case nir_op_uadd_sat
: {
1499 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1500 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1501 if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1503 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1505 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1506 } else if (dst
.regClass() == v1
) {
1507 if (ctx
->options
->chip_class
>= GFX9
) {
1508 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1509 add
->operands
[0] = Operand(src0
);
1510 add
->operands
[1] = Operand(src1
);
1511 add
->definitions
[0] = Definition(dst
);
1513 ctx
->block
->instructions
.emplace_back(std::move(add
));
1515 if (src1
.regClass() != v1
)
1516 std::swap(src0
, src1
);
1517 assert(src1
.regClass() == v1
);
1518 Temp tmp
= bld
.tmp(v1
);
1519 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1520 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1523 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1524 nir_print_instr(&instr
->instr
, stderr
);
1525 fprintf(stderr
, "\n");
1529 case nir_op_uadd_carry
: {
1530 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1531 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1532 if (dst
.regClass() == s1
) {
1533 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1536 if (dst
.regClass() == v1
) {
1537 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1538 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1542 Temp src00
= bld
.tmp(src0
.type(), 1);
1543 Temp src01
= bld
.tmp(dst
.type(), 1);
1544 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1545 Temp src10
= bld
.tmp(src1
.type(), 1);
1546 Temp src11
= bld
.tmp(dst
.type(), 1);
1547 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1548 if (dst
.regClass() == s2
) {
1549 Temp carry
= bld
.tmp(s1
);
1550 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1551 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1552 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1553 } else if (dst
.regClass() == v2
) {
1554 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1555 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1556 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1557 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1559 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1560 nir_print_instr(&instr
->instr
, stderr
);
1561 fprintf(stderr
, "\n");
1566 if (dst
.regClass() == s1
) {
1567 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1571 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1572 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1573 if (dst
.regClass() == v1
) {
1574 bld
.vsub32(Definition(dst
), src0
, src1
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1589 } else if (dst
.regClass() == v2
) {
1590 Temp lower
= bld
.tmp(v1
);
1591 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1592 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1595 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1596 nir_print_instr(&instr
->instr
, stderr
);
1597 fprintf(stderr
, "\n");
1601 case nir_op_usub_borrow
: {
1602 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1603 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1604 if (dst
.regClass() == s1
) {
1605 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1607 } else if (dst
.regClass() == v1
) {
1608 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1609 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1613 Temp src00
= bld
.tmp(src0
.type(), 1);
1614 Temp src01
= bld
.tmp(dst
.type(), 1);
1615 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1616 Temp src10
= bld
.tmp(src1
.type(), 1);
1617 Temp src11
= bld
.tmp(dst
.type(), 1);
1618 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1619 if (dst
.regClass() == s2
) {
1620 Temp borrow
= bld
.tmp(s1
);
1621 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1622 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1623 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1624 } else if (dst
.regClass() == v2
) {
1625 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1626 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1627 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1628 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1630 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1631 nir_print_instr(&instr
->instr
, stderr
);
1632 fprintf(stderr
, "\n");
1637 if (dst
.regClass() == v1
) {
1638 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1639 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1640 } else if (dst
.regClass() == s1
) {
1641 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1643 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1644 nir_print_instr(&instr
->instr
, stderr
);
1645 fprintf(stderr
, "\n");
1649 case nir_op_umul_high
: {
1650 if (dst
.regClass() == v1
) {
1651 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1652 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1653 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1654 } else if (dst
.regClass() == s1
) {
1655 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1656 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1657 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1659 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1660 nir_print_instr(&instr
->instr
, stderr
);
1661 fprintf(stderr
, "\n");
1665 case nir_op_imul_high
: {
1666 if (dst
.regClass() == v1
) {
1667 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1668 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1669 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1672 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1673 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1675 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1676 nir_print_instr(&instr
->instr
, stderr
);
1677 fprintf(stderr
, "\n");
1682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1683 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1684 if (dst
.regClass() == v2b
) {
1685 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1686 } else if (dst
.regClass() == v1
) {
1687 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1688 } else if (dst
.regClass() == v2
) {
1689 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1698 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1699 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1700 if (dst
.regClass() == v2b
) {
1701 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1702 } else if (dst
.regClass() == v1
) {
1703 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1704 } else if (dst
.regClass() == v2
) {
1705 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1714 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1715 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1716 if (dst
.regClass() == v2b
) {
1717 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1718 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1720 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1721 } else if (dst
.regClass() == v1
) {
1722 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1728 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1729 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1732 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1733 nir_print_instr(&instr
->instr
, stderr
);
1734 fprintf(stderr
, "\n");
1739 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1740 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1741 if (dst
.regClass() == v2b
) {
1742 // TODO: check fp_mode.must_flush_denorms16_64
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1744 } else if (dst
.regClass() == v1
) {
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1746 } else if (dst
.regClass() == v2
) {
1747 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1748 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1749 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1751 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1754 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1755 nir_print_instr(&instr
->instr
, stderr
);
1756 fprintf(stderr
, "\n");
1761 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1762 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1763 if (dst
.regClass() == v2b
) {
1764 // TODO: check fp_mode.must_flush_denorms16_64
1765 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1766 } else if (dst
.regClass() == v1
) {
1767 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1768 } else if (dst
.regClass() == v2
) {
1769 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1770 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1771 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1773 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1776 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1777 nir_print_instr(&instr
->instr
, stderr
);
1778 fprintf(stderr
, "\n");
1782 case nir_op_fmax3
: {
1783 if (dst
.regClass() == v2b
) {
1784 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1785 } else if (dst
.regClass() == v1
) {
1786 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1788 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1789 nir_print_instr(&instr
->instr
, stderr
);
1790 fprintf(stderr
, "\n");
1794 case nir_op_fmin3
: {
1795 if (dst
.regClass() == v2b
) {
1796 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1797 } else if (dst
.regClass() == v1
) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_fmed3
: {
1807 if (dst
.regClass() == v2b
) {
1808 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1809 } else if (dst
.regClass() == v1
) {
1810 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1812 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1813 nir_print_instr(&instr
->instr
, stderr
);
1814 fprintf(stderr
, "\n");
1818 case nir_op_umax3
: {
1819 if (dst
.size() == 1) {
1820 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1822 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1823 nir_print_instr(&instr
->instr
, stderr
);
1824 fprintf(stderr
, "\n");
1828 case nir_op_umin3
: {
1829 if (dst
.size() == 1) {
1830 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1832 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1833 nir_print_instr(&instr
->instr
, stderr
);
1834 fprintf(stderr
, "\n");
1838 case nir_op_umed3
: {
1839 if (dst
.size() == 1) {
1840 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1848 case nir_op_imax3
: {
1849 if (dst
.size() == 1) {
1850 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1858 case nir_op_imin3
: {
1859 if (dst
.size() == 1) {
1860 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1862 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1863 nir_print_instr(&instr
->instr
, stderr
);
1864 fprintf(stderr
, "\n");
1868 case nir_op_imed3
: {
1869 if (dst
.size() == 1) {
1870 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1872 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1873 nir_print_instr(&instr
->instr
, stderr
);
1874 fprintf(stderr
, "\n");
1878 case nir_op_cube_face_coord
: {
1879 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1880 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1881 emit_extract_vector(ctx
, in
, 1, v1
),
1882 emit_extract_vector(ctx
, in
, 2, v1
) };
1883 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1884 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1885 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1886 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1887 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1888 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1889 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1892 case nir_op_cube_face_index
: {
1893 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1894 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1895 emit_extract_vector(ctx
, in
, 1, v1
),
1896 emit_extract_vector(ctx
, in
, 2, v1
) };
1897 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1900 case nir_op_bcsel
: {
1901 emit_bcsel(ctx
, instr
, dst
);
1905 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1906 if (dst
.regClass() == v2b
) {
1907 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1908 } else if (dst
.regClass() == v1
) {
1909 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1910 } else if (dst
.regClass() == v2
) {
1911 /* Lowered at NIR level for precision reasons. */
1912 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1915 nir_print_instr(&instr
->instr
, stderr
);
1916 fprintf(stderr
, "\n");
1921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1922 if (dst
.regClass() == v2b
) {
1923 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1924 } else if (dst
.regClass() == v1
) {
1925 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1926 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1927 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1928 } else if (dst
.regClass() == v2
) {
1929 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1930 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1931 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1933 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1934 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1936 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1937 nir_print_instr(&instr
->instr
, stderr
);
1938 fprintf(stderr
, "\n");
1943 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1944 if (dst
.regClass() == v2b
) {
1945 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1946 } else if (dst
.regClass() == v1
) {
1947 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1948 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1949 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1950 } else if (dst
.regClass() == v2
) {
1951 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1952 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1953 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1954 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1955 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1956 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1958 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1959 nir_print_instr(&instr
->instr
, stderr
);
1960 fprintf(stderr
, "\n");
1965 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1966 if (dst
.regClass() == v2b
) {
1967 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1968 } else if (dst
.regClass() == v1
) {
1969 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1970 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1971 // TODO: confirm that this holds under any circumstances
1972 } else if (dst
.regClass() == v2
) {
1973 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1974 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1977 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1978 nir_print_instr(&instr
->instr
, stderr
);
1979 fprintf(stderr
, "\n");
1983 case nir_op_flog2
: {
1984 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1985 if (dst
.regClass() == v2b
) {
1986 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1987 } else if (dst
.regClass() == v1
) {
1988 emit_log2(ctx
, bld
, Definition(dst
), src
);
1990 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1991 nir_print_instr(&instr
->instr
, stderr
);
1992 fprintf(stderr
, "\n");
1997 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1998 if (dst
.regClass() == v2b
) {
1999 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
2000 } else if (dst
.regClass() == v1
) {
2001 emit_rcp(ctx
, bld
, Definition(dst
), src
);
2002 } else if (dst
.regClass() == v2
) {
2003 /* Lowered at NIR level for precision reasons. */
2004 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
2006 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2007 nir_print_instr(&instr
->instr
, stderr
);
2008 fprintf(stderr
, "\n");
2012 case nir_op_fexp2
: {
2013 if (dst
.regClass() == v2b
) {
2014 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
2015 } else if (dst
.regClass() == v1
) {
2016 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
2018 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2019 nir_print_instr(&instr
->instr
, stderr
);
2020 fprintf(stderr
, "\n");
2024 case nir_op_fsqrt
: {
2025 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2026 if (dst
.regClass() == v2b
) {
2027 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
2028 } else if (dst
.regClass() == v1
) {
2029 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
2030 } else if (dst
.regClass() == v2
) {
2031 /* Lowered at NIR level for precision reasons. */
2032 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
2034 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2035 nir_print_instr(&instr
->instr
, stderr
);
2036 fprintf(stderr
, "\n");
2040 case nir_op_ffract
: {
2041 if (dst
.regClass() == v2b
) {
2042 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
2043 } else if (dst
.regClass() == v1
) {
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
2045 } else if (dst
.regClass() == v2
) {
2046 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
2048 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2049 nir_print_instr(&instr
->instr
, stderr
);
2050 fprintf(stderr
, "\n");
2054 case nir_op_ffloor
: {
2055 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2056 if (dst
.regClass() == v2b
) {
2057 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
2058 } else if (dst
.regClass() == v1
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
2060 } else if (dst
.regClass() == v2
) {
2061 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2063 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2064 nir_print_instr(&instr
->instr
, stderr
);
2065 fprintf(stderr
, "\n");
2069 case nir_op_fceil
: {
2070 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2071 if (dst
.regClass() == v2b
) {
2072 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
2073 } else if (dst
.regClass() == v1
) {
2074 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2075 } else if (dst
.regClass() == v2
) {
2076 if (ctx
->options
->chip_class
>= GFX7
) {
2077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2079 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2080 /* trunc = trunc(src0)
2081 * if (src0 > 0.0 && src0 != trunc)
2084 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2085 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2086 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2087 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2088 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2089 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2090 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2093 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2094 nir_print_instr(&instr
->instr
, stderr
);
2095 fprintf(stderr
, "\n");
2099 case nir_op_ftrunc
: {
2100 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2101 if (dst
.regClass() == v2b
) {
2102 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2103 } else if (dst
.regClass() == v1
) {
2104 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2105 } else if (dst
.regClass() == v2
) {
2106 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2108 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2109 nir_print_instr(&instr
->instr
, stderr
);
2110 fprintf(stderr
, "\n");
2114 case nir_op_fround_even
: {
2115 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2116 if (dst
.regClass() == v2b
) {
2117 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2118 } else if (dst
.regClass() == v1
) {
2119 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2120 } else if (dst
.regClass() == v2
) {
2121 if (ctx
->options
->chip_class
>= GFX7
) {
2122 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2124 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2125 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2128 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2129 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2130 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2131 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2132 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2133 tmp
= sub
->definitions
[0].getTemp();
2135 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2136 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2137 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2138 Temp cond
= vop3
->definitions
[0].getTemp();
2140 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2141 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2142 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2143 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2145 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2156 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2157 aco_ptr
<Instruction
> norm
;
2158 if (dst
.regClass() == v2b
) {
2159 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2160 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2161 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2162 bld
.vop1(opcode
, Definition(dst
), tmp
);
2163 } else if (dst
.regClass() == v1
) {
2164 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2165 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2167 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2168 if (ctx
->options
->chip_class
< GFX9
)
2169 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2171 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2172 bld
.vop1(opcode
, Definition(dst
), tmp
);
2174 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2175 nir_print_instr(&instr
->instr
, stderr
);
2176 fprintf(stderr
, "\n");
2180 case nir_op_ldexp
: {
2181 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2182 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2183 if (dst
.regClass() == v2b
) {
2184 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2185 } else if (dst
.regClass() == v1
) {
2186 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2187 } else if (dst
.regClass() == v2
) {
2188 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2191 nir_print_instr(&instr
->instr
, stderr
);
2192 fprintf(stderr
, "\n");
2196 case nir_op_frexp_sig
: {
2197 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2198 if (dst
.regClass() == v2b
) {
2199 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2200 } else if (dst
.regClass() == v1
) {
2201 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2202 } else if (dst
.regClass() == v2
) {
2203 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2206 nir_print_instr(&instr
->instr
, stderr
);
2207 fprintf(stderr
, "\n");
2211 case nir_op_frexp_exp
: {
2212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2213 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2214 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2215 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2216 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2217 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2218 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2219 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2220 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2222 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2223 nir_print_instr(&instr
->instr
, stderr
);
2224 fprintf(stderr
, "\n");
2228 case nir_op_fsign
: {
2229 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2230 if (dst
.regClass() == v2b
) {
2231 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2232 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2233 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2234 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2235 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2236 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2237 } else if (dst
.regClass() == v1
) {
2238 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2239 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2240 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2241 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2242 } else if (dst
.regClass() == v2
) {
2243 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2244 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2245 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2247 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2248 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2249 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2251 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2253 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2254 nir_print_instr(&instr
->instr
, stderr
);
2255 fprintf(stderr
, "\n");
2260 case nir_op_f2f16_rtne
: {
2261 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2262 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2263 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2264 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2267 case nir_op_f2f16_rtz
: {
2268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2269 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2270 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2271 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2274 case nir_op_f2f32
: {
2275 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2276 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2277 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2278 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2280 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2281 nir_print_instr(&instr
->instr
, stderr
);
2282 fprintf(stderr
, "\n");
2286 case nir_op_f2f64
: {
2287 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2288 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2289 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2290 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2293 case nir_op_i2f16
: {
2294 assert(dst
.regClass() == v2b
);
2295 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2296 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2297 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2298 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2299 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2300 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2303 case nir_op_i2f32
: {
2304 assert(dst
.size() == 1);
2305 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2306 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2307 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2308 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2311 case nir_op_i2f64
: {
2312 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2313 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2314 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2315 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2316 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2318 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2319 RegClass rc
= RegClass(src
.type(), 1);
2320 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2321 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2322 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2323 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2324 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2325 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2328 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2329 nir_print_instr(&instr
->instr
, stderr
);
2330 fprintf(stderr
, "\n");
2334 case nir_op_u2f16
: {
2335 assert(dst
.regClass() == v2b
);
2336 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2337 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2338 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2339 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2340 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2341 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2344 case nir_op_u2f32
: {
2345 assert(dst
.size() == 1);
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2348 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2350 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2351 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2352 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2356 case nir_op_u2f64
: {
2357 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2358 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2359 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2360 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2361 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2362 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2363 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2364 RegClass rc
= RegClass(src
.type(), 1);
2365 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2366 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2367 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2368 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2369 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2370 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2372 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2373 nir_print_instr(&instr
->instr
, stderr
);
2374 fprintf(stderr
, "\n");
2379 case nir_op_f2i16
: {
2380 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2381 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2382 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2383 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2385 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2389 case nir_op_f2u16
: {
2390 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2391 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2392 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2393 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2395 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2398 case nir_op_f2i32
: {
2399 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2400 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2401 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2402 if (dst
.type() == RegType::vgpr
) {
2403 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2405 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2406 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2408 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2409 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2410 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2411 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2413 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2414 nir_print_instr(&instr
->instr
, stderr
);
2415 fprintf(stderr
, "\n");
2419 case nir_op_f2u32
: {
2420 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2421 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2422 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2423 if (dst
.type() == RegType::vgpr
) {
2424 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2426 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2427 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2429 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2430 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2431 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2432 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2434 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2435 nir_print_instr(&instr
->instr
, stderr
);
2436 fprintf(stderr
, "\n");
2440 case nir_op_f2i64
: {
2441 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2442 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2443 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2445 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2446 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2447 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2448 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2449 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2450 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2451 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2452 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2453 Temp new_exponent
= bld
.tmp(v1
);
2454 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2455 if (ctx
->program
->chip_class
>= GFX8
)
2456 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2458 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2459 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2460 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2461 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2462 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2463 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2464 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2465 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2466 Temp new_lower
= bld
.tmp(v1
);
2467 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2468 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2471 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2472 if (src
.type() == RegType::vgpr
)
2473 src
= bld
.as_uniform(src
);
2474 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2475 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2476 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2477 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2478 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2479 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2480 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2481 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2482 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2483 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2484 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2485 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2486 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2487 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2488 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2489 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2490 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2491 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2492 Temp borrow
= bld
.tmp(s1
);
2493 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2494 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2495 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2498 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2499 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2500 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2501 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2502 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2503 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2504 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2505 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2506 if (dst
.type() == RegType::sgpr
) {
2507 lower
= bld
.as_uniform(lower
);
2508 upper
= bld
.as_uniform(upper
);
2510 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2513 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2514 nir_print_instr(&instr
->instr
, stderr
);
2515 fprintf(stderr
, "\n");
2519 case nir_op_f2u64
: {
2520 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2521 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2522 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2524 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2525 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2526 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2527 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2528 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2529 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2530 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2531 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2532 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2533 Temp new_exponent
= bld
.tmp(v1
);
2534 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2535 if (ctx
->program
->chip_class
>= GFX8
)
2536 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2538 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2539 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2541 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2542 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2543 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2544 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2545 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2547 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2548 if (src
.type() == RegType::vgpr
)
2549 src
= bld
.as_uniform(src
);
2550 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2551 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2552 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2553 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2554 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2555 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2556 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2557 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2558 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2559 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2560 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2561 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2562 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2563 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2564 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2565 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2566 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2567 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2569 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2570 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2571 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2572 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2573 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2574 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2575 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2576 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2577 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2578 if (dst
.type() == RegType::sgpr
) {
2579 lower
= bld
.as_uniform(lower
);
2580 upper
= bld
.as_uniform(upper
);
2582 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2585 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2586 nir_print_instr(&instr
->instr
, stderr
);
2587 fprintf(stderr
, "\n");
2591 case nir_op_b2f16
: {
2592 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2593 assert(src
.regClass() == bld
.lm
);
2595 if (dst
.regClass() == s1
) {
2596 src
= bool_to_scalar_condition(ctx
, src
);
2597 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2598 } else if (dst
.regClass() == v2b
) {
2599 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2600 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2602 unreachable("Wrong destination register class for nir_op_b2f16.");
2606 case nir_op_b2f32
: {
2607 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2608 assert(src
.regClass() == bld
.lm
);
2610 if (dst
.regClass() == s1
) {
2611 src
= bool_to_scalar_condition(ctx
, src
);
2612 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2613 } else if (dst
.regClass() == v1
) {
2614 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2616 unreachable("Wrong destination register class for nir_op_b2f32.");
2620 case nir_op_b2f64
: {
2621 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2622 assert(src
.regClass() == bld
.lm
);
2624 if (dst
.regClass() == s2
) {
2625 src
= bool_to_scalar_condition(ctx
, src
);
2626 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2627 } else if (dst
.regClass() == v2
) {
2628 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2629 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2630 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2632 unreachable("Wrong destination register class for nir_op_b2f64.");
2639 case nir_op_i2i64
: {
2640 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2641 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2647 case nir_op_u2u64
: {
2648 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2649 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2653 case nir_op_b2i32
: {
2654 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2655 assert(src
.regClass() == bld
.lm
);
2657 if (dst
.regClass() == s1
) {
2658 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2659 bool_to_scalar_condition(ctx
, src
, dst
);
2660 } else if (dst
.regClass() == v1
) {
2661 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2663 unreachable("Invalid register class for b2i32");
2669 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2670 assert(dst
.regClass() == bld
.lm
);
2672 if (src
.type() == RegType::vgpr
) {
2673 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2674 assert(dst
.regClass() == bld
.lm
);
2675 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2676 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2678 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2680 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2681 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2683 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2684 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2686 bool_to_vector_condition(ctx
, tmp
, dst
);
2690 case nir_op_pack_64_2x32_split
: {
2691 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2692 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2694 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2697 case nir_op_unpack_64_2x32_split_x
:
2698 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2700 case nir_op_unpack_64_2x32_split_y
:
2701 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2703 case nir_op_unpack_32_2x16_split_x
:
2704 if (dst
.type() == RegType::vgpr
) {
2705 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2707 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2710 case nir_op_unpack_32_2x16_split_y
:
2711 if (dst
.type() == RegType::vgpr
) {
2712 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2714 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2717 case nir_op_pack_32_2x16_split
: {
2718 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2719 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2720 if (dst
.regClass() == v1
) {
2721 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2722 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2723 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2725 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2726 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2727 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2731 case nir_op_pack_half_2x16
: {
2732 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2734 if (dst
.regClass() == v1
) {
2735 Temp src0
= bld
.tmp(v1
);
2736 Temp src1
= bld
.tmp(v1
);
2737 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2738 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2739 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2741 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2742 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2743 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2745 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2746 nir_print_instr(&instr
->instr
, stderr
);
2747 fprintf(stderr
, "\n");
2751 case nir_op_unpack_half_2x16_split_x
: {
2752 if (dst
.regClass() == v1
) {
2753 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2755 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2756 nir_print_instr(&instr
->instr
, stderr
);
2757 fprintf(stderr
, "\n");
2761 case nir_op_unpack_half_2x16_split_y
: {
2762 if (dst
.regClass() == v1
) {
2763 /* TODO: use SDWA here */
2764 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2765 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2768 nir_print_instr(&instr
->instr
, stderr
);
2769 fprintf(stderr
, "\n");
2773 case nir_op_fquantize2f16
: {
2774 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2775 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2778 if (ctx
->program
->chip_class
>= GFX8
) {
2779 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2780 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2781 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2783 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2784 * so compare the result and flush to 0 if it's smaller.
2786 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2787 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2788 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2789 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2790 cmp_res
= vop3
->definitions
[0].getTemp();
2793 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2794 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2795 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2797 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2802 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2803 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2805 if (dst
.regClass() == s1
) {
2806 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2807 } else if (dst
.regClass() == v1
) {
2808 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2810 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2811 nir_print_instr(&instr
->instr
, stderr
);
2812 fprintf(stderr
, "\n");
2816 case nir_op_bitfield_select
: {
2817 /* (mask & insert) | (~mask & base) */
2818 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2819 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2820 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2822 /* dst = (insert & bitmask) | (base & ~bitmask) */
2823 if (dst
.regClass() == s1
) {
2824 aco_ptr
<Instruction
> sop2
;
2825 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2826 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2828 if (const_insert
&& const_bitmask
) {
2829 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2831 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2832 lhs
= Operand(insert
);
2836 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2837 if (const_base
&& const_bitmask
) {
2838 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2840 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2841 rhs
= Operand(base
);
2844 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2846 } else if (dst
.regClass() == v1
) {
2847 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2848 base
= as_vgpr(ctx
, base
);
2849 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2850 insert
= as_vgpr(ctx
, insert
);
2852 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2855 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2856 nir_print_instr(&instr
->instr
, stderr
);
2857 fprintf(stderr
, "\n");
2863 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2864 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2865 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2867 if (dst
.type() == RegType::sgpr
) {
2869 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2870 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2871 if (const_offset
&& const_bits
) {
2872 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2873 extract
= Operand(const_extract
);
2877 width
= Operand(const_bits
->u32
<< 16);
2879 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2881 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2885 if (dst
.regClass() == s1
) {
2886 if (instr
->op
== nir_op_ubfe
)
2887 opcode
= aco_opcode::s_bfe_u32
;
2889 opcode
= aco_opcode::s_bfe_i32
;
2890 } else if (dst
.regClass() == s2
) {
2891 if (instr
->op
== nir_op_ubfe
)
2892 opcode
= aco_opcode::s_bfe_u64
;
2894 opcode
= aco_opcode::s_bfe_i64
;
2896 unreachable("Unsupported BFE bit size");
2899 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2903 if (dst
.regClass() == v1
) {
2904 if (instr
->op
== nir_op_ubfe
)
2905 opcode
= aco_opcode::v_bfe_u32
;
2907 opcode
= aco_opcode::v_bfe_i32
;
2909 unreachable("Unsupported BFE bit size");
2912 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2916 case nir_op_bit_count
: {
2917 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2918 if (src
.regClass() == s1
) {
2919 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2920 } else if (src
.regClass() == v1
) {
2921 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2922 } else if (src
.regClass() == v2
) {
2923 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2924 emit_extract_vector(ctx
, src
, 1, v1
),
2925 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2926 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2927 } else if (src
.regClass() == s2
) {
2928 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2930 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2931 nir_print_instr(&instr
->instr
, stderr
);
2932 fprintf(stderr
, "\n");
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2941 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2945 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2949 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2953 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2957 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2961 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2962 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2964 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2965 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2969 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2970 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2972 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2973 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2977 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2981 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2986 case nir_op_fddx_fine
:
2987 case nir_op_fddy_fine
:
2988 case nir_op_fddx_coarse
:
2989 case nir_op_fddy_coarse
: {
2990 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2991 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2992 if (instr
->op
== nir_op_fddx_fine
) {
2993 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2994 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2995 } else if (instr
->op
== nir_op_fddy_fine
) {
2996 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2997 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2999 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
3000 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
3001 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
3003 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
3007 if (ctx
->program
->chip_class
>= GFX8
) {
3008 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
3009 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
3011 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
3012 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
3013 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
3015 emit_wqm(ctx
, tmp
, dst
, true);
3019 fprintf(stderr
, "Unknown NIR ALU instr: ");
3020 nir_print_instr(&instr
->instr
, stderr
);
3021 fprintf(stderr
, "\n");
3025 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3027 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3029 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3030 // which get truncated the lsb if double and msb if int
3031 // for now, we only use s_mov_b64 with 64bit inline constants
3032 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3033 assert(dst
.type() == RegType::sgpr
);
3035 Builder
bld(ctx
->program
, ctx
->block
);
3037 if (instr
->def
.bit_size
== 1) {
3038 assert(dst
.regClass() == bld
.lm
);
3039 int val
= instr
->value
[0].b
? -1 : 0;
3040 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3041 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3042 } else if (instr
->def
.bit_size
== 8) {
3043 /* ensure that the value is correctly represented in the low byte of the register */
3044 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3045 } else if (instr
->def
.bit_size
== 16) {
3046 /* ensure that the value is correctly represented in the low half of the register */
3047 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3048 } else if (dst
.size() == 1) {
3049 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3051 assert(dst
.size() != 1);
3052 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3053 if (instr
->def
.bit_size
== 64)
3054 for (unsigned i
= 0; i
< dst
.size(); i
++)
3055 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3057 for (unsigned i
= 0; i
< dst
.size(); i
++)
3058 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3060 vec
->definitions
[0] = Definition(dst
);
3061 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3065 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3067 uint32_t new_mask
= 0;
3068 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3069 if (mask
& (1u << i
))
3070 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3074 struct LoadEmitInfo
{
3077 unsigned num_components
;
3078 unsigned component_size
;
3079 Temp resource
= Temp(0, s1
);
3080 unsigned component_stride
= 0;
3081 unsigned const_offset
= 0;
3082 unsigned align_mul
= 0;
3083 unsigned align_offset
= 0;
3086 unsigned swizzle_component_size
= 0;
3087 barrier_interaction barrier
= barrier_none
;
3088 bool can_reorder
= true;
3089 Temp soffset
= Temp(0, s1
);
3092 using LoadCallback
= Temp(*)(
3093 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3094 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3096 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3097 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3099 unsigned load_size
= info
->num_components
* info
->component_size
;
3100 unsigned component_size
= info
->component_size
;
3102 unsigned num_vals
= 0;
3103 Temp vals
[info
->dst
.bytes()];
3105 unsigned const_offset
= info
->const_offset
;
3107 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3108 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3110 unsigned bytes_read
= 0;
3111 while (bytes_read
< load_size
) {
3112 unsigned bytes_needed
= load_size
- bytes_read
;
3114 /* add buffer for unaligned loads */
3115 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3118 if ((bytes_needed
> 2 ||
3119 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
3120 !supports_8bit_16bit_loads
) && byte_align_loads
) {
3121 if (info
->component_stride
) {
3122 assert(supports_8bit_16bit_loads
&& "unimplemented");
3126 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3127 bytes_needed
= align(bytes_needed
, 4);
3134 if (info
->swizzle_component_size
)
3135 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3136 if (info
->component_stride
)
3137 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3139 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3141 /* reduce constant offset */
3142 Operand offset
= info
->offset
;
3143 unsigned reduced_const_offset
= const_offset
;
3144 bool remove_const_offset_completely
= need_to_align_offset
;
3145 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3146 unsigned to_add
= const_offset
;
3147 if (remove_const_offset_completely
) {
3148 reduced_const_offset
= 0;
3150 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3151 reduced_const_offset
%= max_const_offset_plus_one
;
3153 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3154 if (offset
.isConstant()) {
3155 offset
= Operand(offset
.constantValue() + to_add
);
3156 } else if (offset_tmp
.regClass() == s1
) {
3157 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3158 offset_tmp
, Operand(to_add
));
3159 } else if (offset_tmp
.regClass() == v1
) {
3160 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3162 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3163 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3164 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3166 if (offset_tmp
.regClass() == s2
) {
3167 Temp carry
= bld
.tmp(s1
);
3168 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3169 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3170 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3172 Temp new_lo
= bld
.tmp(v1
);
3173 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3174 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3175 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3180 /* align offset down if needed */
3181 Operand aligned_offset
= offset
;
3182 if (need_to_align_offset
) {
3183 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3184 if (offset
.isConstant()) {
3185 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3186 } else if (offset_tmp
.regClass() == s1
) {
3187 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3188 } else if (offset_tmp
.regClass() == s2
) {
3189 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3190 } else if (offset_tmp
.regClass() == v1
) {
3191 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3192 } else if (offset_tmp
.regClass() == v2
) {
3193 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3194 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3195 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3196 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3199 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3200 bld
.copy(bld
.def(s1
), aligned_offset
);
3202 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3203 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3204 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3206 /* the callback wrote directly to dst */
3207 if (val
== info
->dst
) {
3208 assert(num_vals
== 0);
3209 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3213 /* shift result right if needed */
3214 if (info
->component_size
< 4 && byte_align_loads
) {
3215 Operand
align((uint32_t)byte_align
);
3216 if (byte_align
== -1) {
3217 if (offset
.isConstant())
3218 align
= Operand(offset
.constantValue() % 4u);
3219 else if (offset
.size() == 2)
3220 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3225 assert(val
.bytes() >= load_size
&& "unimplemented");
3226 if (val
.type() == RegType::sgpr
)
3227 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3229 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3233 /* add result to list and advance */
3234 if (info
->component_stride
) {
3235 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3236 const_offset
+= info
->component_stride
;
3237 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3239 const_offset
+= val
.bytes();
3240 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3242 bytes_read
+= val
.bytes();
3243 vals
[num_vals
++] = val
;
3246 /* create array of components */
3247 unsigned components_split
= 0;
3248 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3249 bool has_vgprs
= false;
3250 for (unsigned i
= 0; i
< num_vals
;) {
3252 unsigned num_tmps
= 0;
3253 unsigned tmp_size
= 0;
3254 RegType reg_type
= RegType::sgpr
;
3255 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3256 if (vals
[i
].type() == RegType::vgpr
)
3257 reg_type
= RegType::vgpr
;
3258 tmp_size
+= vals
[i
].bytes();
3259 tmp
[num_tmps
++] = vals
[i
++];
3262 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3263 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3264 for (unsigned i
= 0; i
< num_vals
; i
++)
3265 vec
->operands
[i
] = Operand(tmp
[i
]);
3266 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3267 vec
->definitions
[0] = Definition(tmp
[0]);
3268 bld
.insert(std::move(vec
));
3271 if (tmp
[0].bytes() % component_size
) {
3273 assert(i
== num_vals
);
3274 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3275 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3278 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3280 unsigned start
= components_split
;
3282 if (tmp_size
== elem_rc
.bytes()) {
3283 allocated_vec
[components_split
++] = tmp
[0];
3285 assert(tmp_size
% elem_rc
.bytes() == 0);
3286 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3287 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3288 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3289 Temp component
= bld
.tmp(elem_rc
);
3290 allocated_vec
[components_split
++] = component
;
3291 split
->definitions
[i
] = Definition(component
);
3293 split
->operands
[0] = Operand(tmp
[0]);
3294 bld
.insert(std::move(split
));
3297 /* try to p_as_uniform early so we can create more optimizable code and
3298 * also update allocated_vec */
3299 for (unsigned j
= start
; j
< components_split
; j
++) {
3300 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3301 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3302 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3306 /* concatenate components and p_as_uniform() result if needed */
3307 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3308 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3310 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3312 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3313 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3314 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3315 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3317 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3318 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3319 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3320 vec
->definitions
[0] = Definition(tmp
);
3321 bld
.insert(std::move(vec
));
3322 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3324 vec
->definitions
[0] = Definition(info
->dst
);
3325 bld
.insert(std::move(vec
));
3329 Operand
load_lds_size_m0(Builder
& bld
)
3331 /* TODO: m0 does not need to be initialized on GFX9+ */
3332 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3335 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3336 Temp offset
, unsigned bytes_needed
,
3337 unsigned align
, unsigned const_offset
,
3340 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3342 Operand m
= load_lds_size_m0(bld
);
3344 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3345 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3350 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3351 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3353 op
= aco_opcode::ds_read_b128
;
3354 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3357 op
= aco_opcode::ds_read2_b64
;
3358 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3360 op
= aco_opcode::ds_read_b96
;
3361 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3363 op
= aco_opcode::ds_read_b64
;
3364 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3367 op
= aco_opcode::ds_read2_b32
;
3368 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3370 op
= aco_opcode::ds_read_b32
;
3371 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3373 op
= aco_opcode::ds_read_u16
;
3376 op
= aco_opcode::ds_read_u8
;
3379 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3380 if (const_offset
>= max_offset_plus_one
) {
3381 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3382 const_offset
%= max_offset_plus_one
;
3386 const_offset
/= (size
/ 2u);
3388 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3389 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3391 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3393 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3396 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3401 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3403 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3404 Temp offset
, unsigned bytes_needed
,
3405 unsigned align
, unsigned const_offset
,
3410 if (bytes_needed
<= 4) {
3412 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3413 } else if (bytes_needed
<= 8) {
3415 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3416 } else if (bytes_needed
<= 16) {
3418 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3419 } else if (bytes_needed
<= 32) {
3421 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3424 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3426 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3427 if (info
->resource
.id()) {
3428 load
->operands
[0] = Operand(info
->resource
);
3429 load
->operands
[1] = Operand(offset
);
3431 load
->operands
[0] = Operand(offset
);
3432 load
->operands
[1] = Operand(0u);
3434 RegClass
rc(RegType::sgpr
, size
);
3435 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3436 load
->definitions
[0] = Definition(val
);
3437 load
->glc
= info
->glc
;
3438 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3439 load
->barrier
= info
->barrier
;
3440 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3441 bld
.insert(std::move(load
));
3445 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3447 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3448 Temp offset
, unsigned bytes_needed
,
3449 unsigned align_
, unsigned const_offset
,
3452 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3453 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3455 if (info
->soffset
.id()) {
3456 if (soffset
.isTemp())
3457 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3458 soffset
= Operand(info
->soffset
);
3461 unsigned bytes_size
= 0;
3463 if (bytes_needed
== 1) {
3465 op
= aco_opcode::buffer_load_ubyte
;
3466 } else if (bytes_needed
== 2) {
3468 op
= aco_opcode::buffer_load_ushort
;
3469 } else if (bytes_needed
<= 4) {
3471 op
= aco_opcode::buffer_load_dword
;
3472 } else if (bytes_needed
<= 8) {
3474 op
= aco_opcode::buffer_load_dwordx2
;
3475 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3477 op
= aco_opcode::buffer_load_dwordx3
;
3480 op
= aco_opcode::buffer_load_dwordx4
;
3482 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3483 mubuf
->operands
[0] = Operand(info
->resource
);
3484 mubuf
->operands
[1] = vaddr
;
3485 mubuf
->operands
[2] = soffset
;
3486 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3487 mubuf
->glc
= info
->glc
;
3488 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3489 mubuf
->barrier
= info
->barrier
;
3490 mubuf
->can_reorder
= info
->can_reorder
;
3491 mubuf
->offset
= const_offset
;
3492 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3493 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3494 mubuf
->definitions
[0] = Definition(val
);
3495 bld
.insert(std::move(mubuf
));
3500 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3502 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3504 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3505 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3507 if (addr
.type() == RegType::vgpr
)
3508 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3509 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3512 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3513 Temp offset
, unsigned bytes_needed
,
3514 unsigned align_
, unsigned const_offset
,
3517 unsigned bytes_size
= 0;
3518 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3519 bool global
= bld
.program
->chip_class
>= GFX9
;
3521 if (bytes_needed
== 1) {
3523 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3524 } else if (bytes_needed
== 2) {
3526 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3527 } else if (bytes_needed
<= 4) {
3529 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3530 } else if (bytes_needed
<= 8) {
3532 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3533 } else if (bytes_needed
<= 12 && !mubuf
) {
3535 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3538 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3540 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3541 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3543 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3544 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3545 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3546 mubuf
->operands
[2] = Operand(0u);
3547 mubuf
->glc
= info
->glc
;
3550 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3551 mubuf
->disable_wqm
= false;
3552 mubuf
->barrier
= info
->barrier
;
3553 mubuf
->definitions
[0] = Definition(val
);
3554 bld
.insert(std::move(mubuf
));
3556 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3558 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3559 flat
->operands
[0] = Operand(offset
);
3560 flat
->operands
[1] = Operand(s1
);
3561 flat
->glc
= info
->glc
;
3562 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3563 flat
->barrier
= info
->barrier
;
3565 flat
->definitions
[0] = Definition(val
);
3566 bld
.insert(std::move(flat
));
3572 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3574 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3575 Temp address
, unsigned base_offset
, unsigned align
)
3577 assert(util_is_power_of_two_nonzero(align
));
3579 Builder
bld(ctx
->program
, ctx
->block
);
3581 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3582 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3583 info
.align_mul
= align
;
3584 info
.align_offset
= 0;
3585 info
.barrier
= barrier_shared
;
3586 info
.can_reorder
= false;
3587 info
.const_offset
= base_offset
;
3588 emit_lds_load(ctx
, bld
, &info
);
3593 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3598 Builder
bld(ctx
->program
, ctx
->block
);
3600 ASSERTED
bool is_subdword
= false;
3601 for (unsigned i
= 0; i
< count
; i
++)
3602 is_subdword
|= offsets
[i
] % 4;
3603 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3604 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3606 /* count == 1 fast path */
3608 if (dst_type
== RegType::sgpr
)
3609 dst
[0] = bld
.as_uniform(src
);
3611 dst
[0] = as_vgpr(ctx
, src
);
3615 for (unsigned i
= 0; i
< count
- 1; i
++)
3616 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3617 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3619 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3620 src
= as_vgpr(ctx
, src
);
3622 /* use allocated_vec if possible */
3623 auto it
= ctx
->allocated_vec
.find(src
.id());
3624 if (it
!= ctx
->allocated_vec
.end()) {
3625 unsigned total_size
= 0;
3626 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3627 total_size
+= it
->second
[i
].bytes();
3628 if (total_size
!= src
.bytes())
3631 unsigned elem_size
= it
->second
[0].bytes();
3633 for (unsigned i
= 0; i
< count
; i
++) {
3634 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3638 for (unsigned i
= 0; i
< count
; i
++) {
3639 unsigned start_idx
= offsets
[i
] / elem_size
;
3640 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3641 if (op_count
== 1) {
3642 if (dst_type
== RegType::sgpr
)
3643 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3645 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3649 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3650 for (unsigned j
= 0; j
< op_count
; j
++) {
3651 Temp tmp
= it
->second
[start_idx
+ j
];
3652 if (dst_type
== RegType::sgpr
)
3653 tmp
= bld
.as_uniform(tmp
);
3654 vec
->operands
[j
] = Operand(tmp
);
3656 vec
->definitions
[0] = Definition(dst
[i
]);
3657 bld
.insert(std::move(vec
));
3663 if (dst_type
== RegType::sgpr
)
3664 src
= bld
.as_uniform(src
);
3668 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3669 split
->operands
[0] = Operand(src
);
3670 for (unsigned i
= 0; i
< count
; i
++)
3671 split
->definitions
[i
] = Definition(dst
[i
]);
3672 bld
.insert(std::move(split
));
3675 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3676 int *start
, int *count
)
3678 unsigned start_elem
= ffs(todo_mask
) - 1;
3679 bool skip
= !(mask
& (1 << start_elem
));
3681 mask
= ~mask
& todo_mask
;
3685 u_bit_scan_consecutive_range(&mask
, start
, count
);
3690 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3692 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3695 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3696 Temp address
, unsigned base_offset
, unsigned align
)
3698 assert(util_is_power_of_two_nonzero(align
));
3699 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3701 Builder
bld(ctx
->program
, ctx
->block
);
3702 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3703 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3705 unsigned write_count
= 0;
3706 Temp write_datas
[32];
3707 unsigned offsets
[32];
3708 aco_opcode opcodes
[32];
3710 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3712 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3715 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3716 offsets
[write_count
] = offset
;
3717 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3719 advance_write_mask(&todo
, offset
, bytes
);
3723 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3724 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3725 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3726 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3728 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3729 aco_opcode op
= aco_opcode::num_opcodes
;
3730 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3731 op
= aco_opcode::ds_write_b128
;
3733 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3734 op
= aco_opcode::ds_write_b96
;
3736 } else if (bytes
>= 8 && aligned8
) {
3737 op
= aco_opcode::ds_write_b64
;
3739 } else if (bytes
>= 4 && aligned4
) {
3740 op
= aco_opcode::ds_write_b32
;
3742 } else if (bytes
>= 2 && aligned2
) {
3743 op
= aco_opcode::ds_write_b16
;
3745 } else if (bytes
>= 1) {
3746 op
= aco_opcode::ds_write_b8
;
3752 offsets
[write_count
] = offset
;
3753 opcodes
[write_count
] = op
;
3755 advance_write_mask(&todo
, offset
, bytes
);
3758 Operand m
= load_lds_size_m0(bld
);
3760 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3762 for (unsigned i
= 0; i
< write_count
; i
++) {
3763 aco_opcode op
= opcodes
[i
];
3764 if (op
== aco_opcode::num_opcodes
)
3767 Temp data
= write_datas
[i
];
3769 unsigned second
= write_count
;
3770 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3771 for (second
= i
+ 1; second
< write_count
; second
++) {
3772 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3773 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3774 opcodes
[second
] = aco_opcode::num_opcodes
;
3780 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3781 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3783 unsigned inline_offset
= base_offset
+ offsets
[i
];
3784 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3785 Temp address_offset
= address
;
3786 if (inline_offset
> max_offset
) {
3787 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3788 inline_offset
= offsets
[i
];
3790 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3793 Temp second_data
= write_datas
[second
];
3794 inline_offset
/= data
.bytes();
3795 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3797 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3802 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3804 unsigned align
= 16;
3806 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3812 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3817 return aco_opcode::buffer_store_byte
;
3820 return aco_opcode::buffer_store_short
;
3822 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3824 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3827 return aco_opcode::buffer_store_dwordx3
;
3829 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3831 unreachable("Unexpected store size");
3832 return aco_opcode::num_opcodes
;
3835 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3836 Temp data
, unsigned writemask
, int swizzle_element_size
,
3837 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3839 unsigned write_count_with_skips
= 0;
3842 /* determine how to split the data */
3843 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3846 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3847 offsets
[write_count_with_skips
] = offset
;
3848 if (skips
[write_count_with_skips
]) {
3849 advance_write_mask(&todo
, offset
, bytes
);
3850 write_count_with_skips
++;
3854 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3855 * larger than swizzle_element_size */
3856 bytes
= MIN2(bytes
, swizzle_element_size
);
3858 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3860 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3861 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3864 /* dword or larger stores have to be dword-aligned */
3865 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3866 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3867 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3869 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3871 advance_write_mask(&todo
, offset
, bytes
);
3872 write_count_with_skips
++;
3875 /* actually split data */
3876 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3879 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3882 write_datas
[*write_count
] = write_datas
[i
];
3883 offsets
[*write_count
] = offsets
[i
];
3888 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3889 unsigned split_cnt
= 0u, Temp dst
= Temp())
3891 Builder
bld(ctx
->program
, ctx
->block
);
3892 unsigned dword_size
= elem_size_bytes
/ 4;
3895 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3897 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3898 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3899 instr
->definitions
[0] = Definition(dst
);
3901 for (unsigned i
= 0; i
< cnt
; ++i
) {
3903 assert(arr
[i
].size() == dword_size
);
3904 allocated_vec
[i
] = arr
[i
];
3905 instr
->operands
[i
] = Operand(arr
[i
]);
3907 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3908 allocated_vec
[i
] = zero
;
3909 instr
->operands
[i
] = Operand(zero
);
3913 bld
.insert(std::move(instr
));
3916 emit_split_vector(ctx
, dst
, split_cnt
);
3918 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3923 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3925 if (const_offset
>= 4096) {
3926 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3927 const_offset
%= 4096u;
3930 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3931 else if (unlikely(voffset
.regClass() == s1
))
3932 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3933 else if (likely(voffset
.regClass() == v1
))
3934 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3936 unreachable("Unsupported register class of voffset");
3939 return const_offset
;
3942 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3943 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3946 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3947 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3949 Builder
bld(ctx
->program
, ctx
->block
);
3950 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3951 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3953 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3954 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3955 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3956 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3957 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3959 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3962 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3963 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3964 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3966 Builder
bld(ctx
->program
, ctx
->block
);
3967 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3969 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3971 unsigned write_count
= 0;
3972 Temp write_datas
[32];
3973 unsigned offsets
[32];
3974 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3975 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3977 for (unsigned i
= 0; i
< write_count
; i
++) {
3978 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3979 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3983 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3984 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3985 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3987 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3988 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3989 assert(!!stride
!= allow_combining
);
3991 Builder
bld(ctx
->program
, ctx
->block
);
3993 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3994 info
.component_stride
= allow_combining
? 0 : stride
;
3996 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3997 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3998 info
.align_offset
= 0;
3999 info
.soffset
= soffset
;
4000 info
.const_offset
= base_const_offset
;
4001 emit_mubuf_load(ctx
, bld
, &info
);
4004 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
4006 Builder
bld(ctx
->program
, ctx
->block
);
4007 Temp offset
= base_offset
.first
;
4008 unsigned const_offset
= base_offset
.second
;
4010 if (!nir_src_is_const(*off_src
)) {
4011 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4014 /* Calculate indirect offset with stride */
4015 if (likely(indirect_offset_arg
.regClass() == v1
))
4016 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4017 else if (indirect_offset_arg
.regClass() == s1
)
4018 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4020 unreachable("Unsupported register class of indirect offset");
4022 /* Add to the supplied base offset */
4023 if (offset
.id() == 0)
4024 offset
= with_stride
;
4025 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4026 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4027 else if (offset
.size() == 1 && with_stride
.size() == 1)
4028 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4030 unreachable("Unsupported register class of indirect offset");
4032 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4033 const_offset
+= const_offset_arg
* stride
;
4036 return std::make_pair(offset
, const_offset
);
4039 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4041 Builder
bld(ctx
->program
, ctx
->block
);
4044 if (off1
.first
.id() && off2
.first
.id()) {
4045 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4046 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4047 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4048 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4050 unreachable("Unsupported register class of indirect offset");
4052 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4055 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4058 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4060 Builder
bld(ctx
->program
, ctx
->block
);
4061 unsigned const_offset
= offs
.second
* multiplier
;
4063 if (!offs
.first
.id())
4064 return std::make_pair(offs
.first
, const_offset
);
4066 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4067 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4068 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4070 return std::make_pair(offset
, const_offset
);
4073 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4075 Builder
bld(ctx
->program
, ctx
->block
);
4077 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4078 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4079 /* component is in bytes */
4080 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4082 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4083 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4084 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4087 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4089 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4092 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4094 Builder
bld(ctx
->program
, ctx
->block
);
4096 switch (ctx
->shader
->info
.stage
) {
4097 case MESA_SHADER_TESS_CTRL
:
4098 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4099 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4100 case MESA_SHADER_TESS_EVAL
:
4101 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4103 unreachable("Unsupported stage in get_tess_rel_patch_id");
4107 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4109 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4110 Builder
bld(ctx
->program
, ctx
->block
);
4112 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4113 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4115 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4117 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4118 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4120 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4121 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4122 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4124 return offset_mul(ctx
, offs
, 4u);
4127 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4129 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4130 Builder
bld(ctx
->program
, ctx
->block
);
4132 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4133 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4134 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4135 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4137 std::pair
<Temp
, unsigned> offs
= instr
4138 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4139 : std::make_pair(Temp(), 0u);
4141 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4142 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4147 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4148 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4150 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4151 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4153 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4154 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4160 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4162 Builder
bld(ctx
->program
, ctx
->block
);
4164 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4165 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4167 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4169 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4170 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4171 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4173 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4174 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4179 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4181 Builder
bld(ctx
->program
, ctx
->block
);
4183 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4184 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4185 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4186 unsigned attr_stride
= ctx
->tcs_num_patches
;
4188 std::pair
<Temp
, unsigned> offs
= instr
4189 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4190 : std::make_pair(Temp(), 0u);
4192 if (const_base_offset
)
4193 offs
.second
+= const_base_offset
* attr_stride
;
4195 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4196 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4197 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4202 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4204 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4209 unsigned drv_loc
= nir_intrinsic_base(instr
);
4210 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4212 if (!nir_src_is_const(*off_src
)) {
4218 uint64_t slot
= per_vertex
4219 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4220 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4221 return (((uint64_t) 1) << slot
) & mask
;
4224 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4226 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4227 unsigned component
= nir_intrinsic_component(instr
);
4228 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4230 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4231 if (off_instr
->type
!= nir_instr_type_load_const
)
4234 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4235 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4237 if (instr
->src
[0].ssa
->bit_size
== 64)
4238 write_mask
= widen_mask(write_mask
, 2);
4240 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4242 for (unsigned i
= 0; i
< 8; ++i
) {
4243 if (write_mask
& (1 << i
)) {
4244 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4245 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4253 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4255 /* Only TCS per-vertex inputs are supported by this function.
4256 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4258 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4261 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4262 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4263 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4264 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4265 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4266 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4271 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4272 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4273 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4278 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4280 Builder
bld(ctx
->program
, ctx
->block
);
4282 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4283 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4284 bool indirect_write
;
4285 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4286 if (temp_only_input
&& !indirect_write
)
4290 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4291 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4292 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4293 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4295 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4296 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4297 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4298 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4299 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4303 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4304 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4305 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4306 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4307 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4308 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4309 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4310 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4311 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4312 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4313 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4314 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4315 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4317 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4318 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4320 unreachable("Invalid LS or ES stage");
4323 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4324 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4325 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4329 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4334 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4335 return off
== ctx
->tcs_tess_lvl_out_loc
||
4336 off
== ctx
->tcs_tess_lvl_in_loc
;
4340 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4342 uint64_t mask
= per_vertex
4343 ? ctx
->program
->info
->tcs
.tes_inputs_read
4344 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4346 bool indirect_write
= false;
4347 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4348 return indirect_write
|| output_read_by_tes
;
4351 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4353 uint64_t mask
= per_vertex
4354 ? ctx
->shader
->info
.outputs_read
4355 : ctx
->shader
->info
.patch_outputs_read
;
4357 bool indirect_write
= false;
4358 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4359 return indirect_write
|| output_read
;
4362 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4364 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4365 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4367 Builder
bld(ctx
->program
, ctx
->block
);
4369 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4370 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4371 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4373 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4374 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4375 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4377 if (write_to_vmem
) {
4378 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4379 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4380 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4382 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4383 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4384 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4388 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4389 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4390 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4394 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4396 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4397 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4399 Builder
bld(ctx
->program
, ctx
->block
);
4401 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4402 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4403 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4404 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4406 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4409 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4411 if (ctx
->stage
== vertex_vs
||
4412 ctx
->stage
== tess_eval_vs
||
4413 ctx
->stage
== fragment_fs
||
4414 ctx
->stage
== ngg_vertex_gs
||
4415 ctx
->stage
== ngg_tess_eval_gs
||
4416 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4417 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4418 if (!stored_to_temps
) {
4419 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4420 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4421 fprintf(stderr
, "\n");
4424 } else if (ctx
->stage
== vertex_es
||
4425 ctx
->stage
== vertex_ls
||
4426 ctx
->stage
== tess_eval_es
||
4427 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4428 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4429 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4430 visit_store_ls_or_es_output(ctx
, instr
);
4431 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4432 visit_store_tcs_output(ctx
, instr
, false);
4434 unreachable("Shader stage not implemented");
4438 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4440 visit_load_tcs_output(ctx
, instr
, false);
4443 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4445 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4446 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4448 Builder
bld(ctx
->program
, ctx
->block
);
4450 if (dst
.regClass() == v2b
) {
4451 if (ctx
->program
->has_16bank_lds
) {
4452 assert(ctx
->options
->chip_class
<= GFX8
);
4453 Builder::Result interp_p1
=
4454 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4455 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4456 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4457 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4458 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4459 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4461 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4463 if (ctx
->options
->chip_class
== GFX8
)
4464 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4466 Builder::Result interp_p1
=
4467 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4468 coord1
, bld
.m0(prim_mask
), idx
, component
);
4469 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4470 interp_p1
, idx
, component
);
4473 Builder::Result interp_p1
=
4474 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4475 bld
.m0(prim_mask
), idx
, component
);
4477 if (ctx
->program
->has_16bank_lds
)
4478 interp_p1
.instr
->operands
[0].setLateKill(true);
4480 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4481 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4485 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4487 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4488 for (unsigned i
= 0; i
< num_components
; i
++)
4489 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4490 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4491 assert(num_components
== 4);
4492 Builder
bld(ctx
->program
, ctx
->block
);
4493 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4496 for (Operand
& op
: vec
->operands
)
4497 op
= op
.isUndefined() ? Operand(0u) : op
;
4499 vec
->definitions
[0] = Definition(dst
);
4500 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4501 emit_split_vector(ctx
, dst
, num_components
);
4505 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4507 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4508 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4509 unsigned idx
= nir_intrinsic_base(instr
);
4510 unsigned component
= nir_intrinsic_component(instr
);
4511 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4513 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4515 assert(offset
->u32
== 0);
4517 /* the lower 15bit of the prim_mask contain the offset into LDS
4518 * while the upper bits contain the number of prims */
4519 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4520 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4521 Builder
bld(ctx
->program
, ctx
->block
);
4522 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4523 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4524 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4525 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4526 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4529 if (instr
->dest
.ssa
.num_components
== 1) {
4530 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4532 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4533 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4535 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4536 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4537 vec
->operands
[i
] = Operand(tmp
);
4539 vec
->definitions
[0] = Definition(dst
);
4540 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4544 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4545 unsigned offset
, unsigned stride
, unsigned channels
)
4547 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4548 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4550 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4551 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4554 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4555 unsigned offset
, unsigned stride
, unsigned *channels
)
4557 if (!vtx_info
->chan_byte_size
) {
4558 *channels
= vtx_info
->num_channels
;
4559 return vtx_info
->chan_format
;
4562 unsigned num_channels
= *channels
;
4563 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4564 unsigned new_channels
= num_channels
+ 1;
4565 /* first, assume more loads is worse and try using a larger data format */
4566 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4568 /* don't make the attribute potentially out-of-bounds */
4569 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4573 if (new_channels
== 5) {
4574 /* then try decreasing load size (at the cost of more loads) */
4575 new_channels
= *channels
;
4576 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4580 if (new_channels
< *channels
)
4581 *channels
= new_channels
;
4582 num_channels
= new_channels
;
4585 switch (vtx_info
->chan_format
) {
4586 case V_008F0C_BUF_DATA_FORMAT_8
:
4587 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4588 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4589 case V_008F0C_BUF_DATA_FORMAT_16
:
4590 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4591 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4592 case V_008F0C_BUF_DATA_FORMAT_32
:
4593 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4594 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4596 unreachable("shouldn't reach here");
4597 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4600 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4601 * so we may need to fix it up. */
4602 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4604 Builder
bld(ctx
->program
, ctx
->block
);
4606 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4607 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4609 /* For the integer-like cases, do a natural sign extension.
4611 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4612 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4615 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4616 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4618 /* Convert back to the right type. */
4619 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4620 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4621 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4622 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4623 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4624 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4630 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4632 Builder
bld(ctx
->program
, ctx
->block
);
4633 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4634 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4636 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4637 if (off_instr
->type
!= nir_instr_type_load_const
) {
4638 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4639 nir_print_instr(off_instr
, stderr
);
4640 fprintf(stderr
, "\n");
4642 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4644 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4646 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4647 unsigned component
= nir_intrinsic_component(instr
);
4648 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4649 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4650 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4651 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4652 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4654 unsigned dfmt
= attrib_format
& 0xf;
4655 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4656 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4658 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4659 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4660 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4661 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4663 num_channels
= MAX2(num_channels
, 3);
4665 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4666 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4669 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4670 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4671 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4673 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4675 Temp divided
= bld
.tmp(v1
);
4676 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4677 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4679 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4682 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4685 index
= bld
.vadd32(bld
.def(v1
),
4686 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4687 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4690 Temp channels
[num_channels
];
4691 unsigned channel_start
= 0;
4692 bool direct_fetch
= false;
4694 /* skip unused channels at the start */
4695 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4696 channel_start
= ffs(mask
) - 1;
4697 for (unsigned i
= 0; i
< channel_start
; i
++)
4698 channels
[i
] = Temp(0, s1
);
4699 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4700 num_channels
= 3 - (ffs(mask
) - 1);
4704 while (channel_start
< num_channels
) {
4705 unsigned fetch_component
= num_channels
- channel_start
;
4706 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4707 bool expanded
= false;
4709 /* use MUBUF when possible to avoid possible alignment issues */
4710 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4711 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4712 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4713 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4714 vtx_info
->chan_byte_size
== 4;
4715 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4717 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4719 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4720 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4721 fetch_component
= 4;
4726 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4728 Temp fetch_index
= index
;
4729 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4730 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4731 fetch_offset
= fetch_offset
% attrib_stride
;
4734 Operand
soffset(0u);
4735 if (fetch_offset
>= 4096) {
4736 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4737 fetch_offset
%= 4096;
4741 switch (fetch_bytes
) {
4743 assert(!use_mubuf
&& bitsize
== 16);
4744 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4747 if (bitsize
== 16) {
4749 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4751 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4755 assert(!use_mubuf
&& bitsize
== 16);
4756 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4759 if (bitsize
== 16) {
4761 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4763 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4767 assert(ctx
->options
->chip_class
>= GFX7
||
4768 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4769 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4772 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4775 unreachable("Unimplemented load_input vector size");
4779 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4780 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4781 num_channels
<= 3)) {
4782 direct_fetch
= true;
4785 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4789 Instruction
*mubuf
= bld
.mubuf(opcode
,
4790 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4791 fetch_offset
, false, true).instr
;
4792 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4794 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4795 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4796 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4797 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4800 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4802 if (fetch_component
== 1) {
4803 channels
[channel_start
] = fetch_dst
;
4805 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4806 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4807 bitsize
== 16 ? v2b
: v1
);
4810 channel_start
+= fetch_component
;
4813 if (!direct_fetch
) {
4814 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4815 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4817 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4818 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4819 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4821 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4822 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4823 unsigned num_temp
= 0;
4824 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4825 unsigned idx
= i
+ component
;
4826 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4827 Temp channel
= channels
[swizzle
[idx
]];
4828 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4829 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4830 vec
->operands
[i
] = Operand(channel
);
4834 } else if (is_float
&& idx
== 3) {
4835 vec
->operands
[i
] = Operand(0x3f800000u
);
4836 } else if (!is_float
&& idx
== 3) {
4837 vec
->operands
[i
] = Operand(1u);
4839 vec
->operands
[i
] = Operand(0u);
4842 vec
->definitions
[0] = Definition(dst
);
4843 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4844 emit_split_vector(ctx
, dst
, dst
.size());
4846 if (num_temp
== dst
.size())
4847 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4849 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4850 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4851 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4852 if (off_instr
->type
!= nir_instr_type_load_const
||
4853 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4854 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4855 nir_print_instr(off_instr
, stderr
);
4856 fprintf(stderr
, "\n");
4859 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4860 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4862 assert(offset
->u32
== 0);
4864 /* the lower 15bit of the prim_mask contain the offset into LDS
4865 * while the upper bits contain the number of prims */
4866 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4867 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4868 Builder
bld(ctx
->program
, ctx
->block
);
4869 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4870 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4871 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4872 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4873 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4876 unsigned idx
= nir_intrinsic_base(instr
);
4877 unsigned component
= nir_intrinsic_component(instr
);
4878 unsigned vertex_id
= 2; /* P0 */
4880 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4881 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4882 switch (src0
->u32
) {
4884 vertex_id
= 2; /* P0 */
4887 vertex_id
= 0; /* P10 */
4890 vertex_id
= 1; /* P20 */
4893 unreachable("invalid vertex index");
4897 if (dst
.size() == 1) {
4898 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4900 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4901 for (unsigned i
= 0; i
< dst
.size(); i
++)
4902 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4903 vec
->definitions
[0] = Definition(dst
);
4904 bld
.insert(std::move(vec
));
4907 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4908 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4909 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4910 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4911 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4913 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4915 unreachable("Shader stage not implemented");
4919 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4921 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4923 Builder
bld(ctx
->program
, ctx
->block
);
4924 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4927 if (!nir_src_is_const(*vertex_src
)) {
4928 /* better code could be created, but this case probably doesn't happen
4929 * much in practice */
4930 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4931 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4934 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4935 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4937 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4939 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4942 if (vertex_offset
.id()) {
4943 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4944 Operand(i
), indirect_vertex
);
4945 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4947 vertex_offset
= elem
;
4951 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4952 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4954 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4955 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4956 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4957 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4958 Operand((vertex
% 2u) * 16u), Operand(16u));
4960 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4963 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4964 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4965 return offset_mul(ctx
, offs
, 4u);
4968 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4970 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4972 Builder
bld(ctx
->program
, ctx
->block
);
4973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4974 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4976 if (ctx
->stage
== geometry_gs
) {
4977 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4978 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4979 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4980 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4981 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4982 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4983 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4985 unreachable("Unsupported GS stage.");
4989 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4991 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4993 Builder
bld(ctx
->program
, ctx
->block
);
4994 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4996 if (load_input_from_temps(ctx
, instr
, dst
))
4999 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
5000 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5001 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
5003 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
5006 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5008 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5010 Builder
bld(ctx
->program
, ctx
->block
);
5012 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5013 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5014 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5016 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5017 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5019 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5022 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5024 switch (ctx
->shader
->info
.stage
) {
5025 case MESA_SHADER_GEOMETRY
:
5026 visit_load_gs_per_vertex_input(ctx
, instr
);
5028 case MESA_SHADER_TESS_CTRL
:
5029 visit_load_tcs_per_vertex_input(ctx
, instr
);
5031 case MESA_SHADER_TESS_EVAL
:
5032 visit_load_tes_per_vertex_input(ctx
, instr
);
5035 unreachable("Unimplemented shader stage");
5039 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5041 visit_load_tcs_output(ctx
, instr
, true);
5044 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5046 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5047 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5049 visit_store_tcs_output(ctx
, instr
, true);
5052 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5054 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5056 Builder
bld(ctx
->program
, ctx
->block
);
5057 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5059 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5060 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5063 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5064 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5065 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5066 tes_w
= Operand(tmp
);
5069 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5070 emit_split_vector(ctx
, tess_coord
, 3);
5073 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5075 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5076 Builder
bld(ctx
->program
, ctx
->block
);
5077 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5078 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5079 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5082 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5086 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5088 Builder
bld(ctx
->program
, ctx
->block
);
5089 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5090 if (!nir_dest_is_divergent(instr
->dest
))
5091 index
= bld
.as_uniform(index
);
5092 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5093 unsigned binding
= nir_intrinsic_binding(instr
);
5096 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5097 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5098 unsigned offset
= layout
->binding
[binding
].offset
;
5100 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5101 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5102 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5103 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5104 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5107 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5108 stride
= layout
->binding
[binding
].size
;
5111 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5112 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5114 if (nir_const_index
) {
5115 const_index
= const_index
* stride
;
5116 } else if (index
.type() == RegType::vgpr
) {
5117 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5118 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5120 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5124 if (nir_const_index
) {
5125 const_index
= const_index
+ offset
;
5126 } else if (index
.type() == RegType::vgpr
) {
5127 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5129 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5133 if (nir_const_index
&& const_index
== 0) {
5135 } else if (index
.type() == RegType::vgpr
) {
5136 index
= bld
.vadd32(bld
.def(v1
),
5137 nir_const_index
? Operand(const_index
) : Operand(index
),
5140 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5141 nir_const_index
? Operand(const_index
) : Operand(index
),
5145 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5148 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5149 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5150 bool glc
=false, bool readonly
=true, bool allow_smem
=true)
5152 Builder
bld(ctx
->program
, ctx
->block
);
5154 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5156 offset
= bld
.as_uniform(offset
);
5158 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5160 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5161 info
.can_reorder
= readonly
;
5162 info
.align_mul
= align_mul
;
5163 info
.align_offset
= align_offset
;
5165 emit_smem_load(ctx
, bld
, &info
);
5167 emit_mubuf_load(ctx
, bld
, &info
);
5170 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5172 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5173 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5175 Builder
bld(ctx
->program
, ctx
->block
);
5177 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5178 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5179 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5180 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5182 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5183 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5187 if (ctx
->options
->chip_class
>= GFX10
) {
5188 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5189 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5190 S_008F0C_RESOURCE_LEVEL(1);
5192 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5193 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5195 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5196 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5197 Operand(0xFFFFFFFFu
),
5198 Operand(desc_type
));
5199 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5200 rsrc
, upper_dwords
);
5202 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5203 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5205 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5206 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5207 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5210 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5212 Builder
bld(ctx
->program
, ctx
->block
);
5213 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5214 unsigned offset
= nir_intrinsic_base(instr
);
5215 unsigned count
= instr
->dest
.ssa
.num_components
;
5216 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5218 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5219 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5220 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5221 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5222 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5223 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5224 for (unsigned i
= 0; i
< count
; ++i
) {
5225 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5226 vec
->operands
[i
] = Operand
{elems
[i
]};
5228 vec
->definitions
[0] = Definition(dst
);
5229 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5230 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5235 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5236 if (offset
!= 0) // TODO check if index != 0 as well
5237 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5238 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5241 bool aligned
= true;
5243 if (instr
->dest
.ssa
.bit_size
== 8) {
5244 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5245 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5247 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5248 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5249 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5251 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5256 switch (vec
.size()) {
5258 op
= aco_opcode::s_load_dword
;
5261 op
= aco_opcode::s_load_dwordx2
;
5267 op
= aco_opcode::s_load_dwordx4
;
5273 op
= aco_opcode::s_load_dwordx8
;
5276 unreachable("unimplemented or forbidden load_push_constant.");
5279 bld
.smem(op
, Definition(vec
), ptr
, index
);
5282 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5283 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5288 emit_split_vector(ctx
, vec
, 4);
5289 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5290 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5291 emit_extract_vector(ctx
, vec
, 0, rc
),
5292 emit_extract_vector(ctx
, vec
, 1, rc
),
5293 emit_extract_vector(ctx
, vec
, 2, rc
));
5296 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5299 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5301 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5303 Builder
bld(ctx
->program
, ctx
->block
);
5305 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5306 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5307 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5308 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5309 if (ctx
->options
->chip_class
>= GFX10
) {
5310 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5311 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5312 S_008F0C_RESOURCE_LEVEL(1);
5314 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5315 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5318 unsigned base
= nir_intrinsic_base(instr
);
5319 unsigned range
= nir_intrinsic_range(instr
);
5321 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5322 if (base
&& offset
.type() == RegType::sgpr
)
5323 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5324 else if (base
&& offset
.type() == RegType::vgpr
)
5325 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5327 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5328 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5329 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5330 Operand(desc_type
));
5331 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5332 // TODO: get alignment information for subdword constants
5333 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5336 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5338 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5339 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5341 ctx
->program
->needs_exact
= true;
5343 // TODO: optimize uniform conditions
5344 Builder
bld(ctx
->program
, ctx
->block
);
5345 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5346 assert(src
.regClass() == bld
.lm
);
5347 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5348 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5349 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5353 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5355 Builder
bld(ctx
->program
, ctx
->block
);
5357 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5358 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5360 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5361 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5363 if (ctx
->block
->loop_nest_depth
&&
5364 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5365 /* we handle discards the same way as jump instructions */
5366 append_logical_end(ctx
->block
);
5368 /* in loops, discard behaves like break */
5369 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5370 ctx
->block
->kind
|= block_kind_discard
;
5373 /* uniform discard - loop ends here */
5374 assert(nir_instr_is_last(&instr
->instr
));
5375 ctx
->block
->kind
|= block_kind_uniform
;
5376 ctx
->cf_info
.has_branch
= true;
5377 bld
.branch(aco_opcode::p_branch
);
5378 add_linear_edge(ctx
->block
->index
, linear_target
);
5382 /* we add a break right behind the discard() instructions */
5383 ctx
->block
->kind
|= block_kind_break
;
5384 unsigned idx
= ctx
->block
->index
;
5386 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5387 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5389 /* remove critical edges from linear CFG */
5390 bld
.branch(aco_opcode::p_branch
);
5391 Block
* break_block
= ctx
->program
->create_and_insert_block();
5392 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5393 break_block
->kind
|= block_kind_uniform
;
5394 add_linear_edge(idx
, break_block
);
5395 add_linear_edge(break_block
->index
, linear_target
);
5396 bld
.reset(break_block
);
5397 bld
.branch(aco_opcode::p_branch
);
5399 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5400 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5401 add_linear_edge(idx
, continue_block
);
5402 append_logical_start(continue_block
);
5403 ctx
->block
= continue_block
;
5408 /* it can currently happen that NIR doesn't remove the unreachable code */
5409 if (!nir_instr_is_last(&instr
->instr
)) {
5410 ctx
->program
->needs_exact
= true;
5411 /* save exec somewhere temporarily so that it doesn't get
5412 * overwritten before the discard from outer exec masks */
5413 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5414 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5415 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5419 /* This condition is incorrect for uniformly branched discards in a loop
5420 * predicated by a divergent condition, but the above code catches that case
5421 * and the discard would end up turning into a discard_if.
5431 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5432 /* program just ends here */
5433 ctx
->block
->kind
|= block_kind_uniform
;
5434 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5435 0 /* enabled mask */, 9 /* dest */,
5436 false /* compressed */, true/* done */, true /* valid mask */);
5437 bld
.sopp(aco_opcode::s_endpgm
);
5438 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5440 ctx
->block
->kind
|= block_kind_discard
;
5441 /* branch and linear edge is added by visit_if() */
5445 enum aco_descriptor_type
{
5456 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5457 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5459 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5460 return dim
== ac_image_cube
||
5461 dim
== ac_image_1darray
||
5462 dim
== ac_image_2darray
||
5463 dim
== ac_image_2darraymsaa
;
5466 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5467 enum aco_descriptor_type desc_type
,
5468 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5470 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5471 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5472 if (it != ctx->tex_desc.end())
5475 Temp index
= Temp();
5476 bool index_set
= false;
5477 unsigned constant_index
= 0;
5478 unsigned descriptor_set
;
5479 unsigned base_index
;
5480 Builder
bld(ctx
->program
, ctx
->block
);
5483 assert(tex_instr
&& !image
);
5485 base_index
= tex_instr
->sampler_index
;
5487 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5488 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5492 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5493 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5495 constant_index
+= array_size
* const_value
->u32
;
5497 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5498 if (indirect
.type() == RegType::vgpr
)
5499 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5501 if (array_size
!= 1)
5502 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5508 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5512 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5514 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5515 base_index
= deref_instr
->var
->data
.binding
;
5518 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5519 list
= convert_pointer_to_64_bit(ctx
, list
);
5521 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5522 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5523 unsigned offset
= binding
->offset
;
5524 unsigned stride
= binding
->size
;
5528 assert(base_index
< layout
->binding_count
);
5530 switch (desc_type
) {
5531 case ACO_DESC_IMAGE
:
5533 opcode
= aco_opcode::s_load_dwordx8
;
5535 case ACO_DESC_FMASK
:
5537 opcode
= aco_opcode::s_load_dwordx8
;
5540 case ACO_DESC_SAMPLER
:
5542 opcode
= aco_opcode::s_load_dwordx4
;
5543 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5544 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5546 case ACO_DESC_BUFFER
:
5548 opcode
= aco_opcode::s_load_dwordx4
;
5550 case ACO_DESC_PLANE_0
:
5551 case ACO_DESC_PLANE_1
:
5553 opcode
= aco_opcode::s_load_dwordx8
;
5554 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5556 case ACO_DESC_PLANE_2
:
5558 opcode
= aco_opcode::s_load_dwordx4
;
5562 unreachable("invalid desc_type\n");
5565 offset
+= constant_index
* stride
;
5567 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5568 (!index_set
|| binding
->immutable_samplers_equal
)) {
5569 if (binding
->immutable_samplers_equal
)
5572 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5573 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5574 Operand(samplers
[constant_index
* 4 + 0]),
5575 Operand(samplers
[constant_index
* 4 + 1]),
5576 Operand(samplers
[constant_index
* 4 + 2]),
5577 Operand(samplers
[constant_index
* 4 + 3]));
5582 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5584 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5585 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5588 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5590 if (desc_type
== ACO_DESC_PLANE_2
) {
5592 for (unsigned i
= 0; i
< 8; i
++)
5593 components
[i
] = bld
.tmp(s1
);
5594 bld
.pseudo(aco_opcode::p_split_vector
,
5595 Definition(components
[0]),
5596 Definition(components
[1]),
5597 Definition(components
[2]),
5598 Definition(components
[3]),
5601 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5602 bld
.pseudo(aco_opcode::p_split_vector
,
5603 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5604 Definition(components
[4]),
5605 Definition(components
[5]),
5606 Definition(components
[6]),
5607 Definition(components
[7]),
5610 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5611 components
[0], components
[1], components
[2], components
[3],
5612 components
[4], components
[5], components
[6], components
[7]);
5618 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5621 case GLSL_SAMPLER_DIM_BUF
:
5623 case GLSL_SAMPLER_DIM_1D
:
5624 return array
? 2 : 1;
5625 case GLSL_SAMPLER_DIM_2D
:
5626 return array
? 3 : 2;
5627 case GLSL_SAMPLER_DIM_MS
:
5628 return array
? 4 : 3;
5629 case GLSL_SAMPLER_DIM_3D
:
5630 case GLSL_SAMPLER_DIM_CUBE
:
5632 case GLSL_SAMPLER_DIM_RECT
:
5633 case GLSL_SAMPLER_DIM_SUBPASS
:
5635 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5644 /* Adjust the sample index according to FMASK.
5646 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5647 * which is the identity mapping. Each nibble says which physical sample
5648 * should be fetched to get that sample.
5650 * For example, 0x11111100 means there are only 2 samples stored and
5651 * the second sample covers 3/4 of the pixel. When reading samples 0
5652 * and 1, return physical sample 0 (determined by the first two 0s
5653 * in FMASK), otherwise return physical sample 1.
5655 * The sample index should be adjusted as follows:
5656 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5658 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5660 Builder
bld(ctx
->program
, ctx
->block
);
5661 Temp fmask
= bld
.tmp(v1
);
5662 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5663 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5666 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5667 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5668 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5669 load
->operands
[0] = Operand(fmask_desc_ptr
);
5670 load
->operands
[1] = Operand(s4
); /* no sampler */
5671 load
->operands
[2] = Operand(coord
);
5672 load
->definitions
[0] = Definition(fmask
);
5679 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5680 ctx
->block
->instructions
.emplace_back(std::move(load
));
5682 Operand sample_index4
;
5683 if (sample_index
.isConstant()) {
5684 if (sample_index
.constantValue() < 16) {
5685 sample_index4
= Operand(sample_index
.constantValue() << 2);
5687 sample_index4
= Operand(0u);
5689 } else if (sample_index
.regClass() == s1
) {
5690 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5692 assert(sample_index
.regClass() == v1
);
5693 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5697 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5698 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5699 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5700 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5702 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5704 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5705 * resource descriptor is 0 (invalid),
5707 Temp compare
= bld
.tmp(bld
.lm
);
5708 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5709 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5711 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5713 /* Replace the MSAA sample index. */
5714 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5717 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5720 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5721 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5722 bool is_array
= glsl_sampler_type_is_array(type
);
5723 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5724 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5725 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5726 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5727 int count
= image_type_to_components_count(dim
, is_array
);
5728 std::vector
<Temp
> coords(count
);
5729 Builder
bld(ctx
->program
, ctx
->block
);
5733 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5734 /* get sample index */
5735 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5736 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5737 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5738 std::vector
<Temp
> fmask_load_address
;
5739 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5740 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5742 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5743 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5745 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5750 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5751 coords
.resize(coords
.size() + 1);
5752 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5754 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5756 for (int i
= 0; i
< count
; i
++)
5757 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5760 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5761 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5762 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5763 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5766 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5769 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5770 for (unsigned i
= 0; i
< coords
.size(); i
++)
5771 vec
->operands
[i
] = Operand(coords
[i
]);
5772 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5773 vec
->definitions
[0] = Definition(res
);
5774 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5779 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5781 Builder
bld(ctx
->program
, ctx
->block
);
5782 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5783 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5784 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5785 bool is_array
= glsl_sampler_type_is_array(type
);
5786 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5788 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5789 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5790 unsigned num_channels
= util_last_bit(mask
);
5791 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5792 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5795 switch (num_channels
) {
5797 opcode
= aco_opcode::buffer_load_format_x
;
5800 opcode
= aco_opcode::buffer_load_format_xy
;
5803 opcode
= aco_opcode::buffer_load_format_xyz
;
5806 opcode
= aco_opcode::buffer_load_format_xyzw
;
5809 unreachable(">4 channel buffer image load");
5811 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5812 load
->operands
[0] = Operand(rsrc
);
5813 load
->operands
[1] = Operand(vindex
);
5814 load
->operands
[2] = Operand((uint32_t) 0);
5816 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5819 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5820 load
->definitions
[0] = Definition(tmp
);
5822 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5823 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5824 load
->barrier
= barrier_image
;
5825 ctx
->block
->instructions
.emplace_back(std::move(load
));
5827 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5831 Temp coords
= get_image_coords(ctx
, instr
, type
);
5832 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5834 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5835 unsigned num_components
= util_bitcount(dmask
);
5837 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5840 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5842 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5843 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5845 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5846 load
->operands
[0] = Operand(resource
);
5847 load
->operands
[1] = Operand(s4
); /* no sampler */
5848 load
->operands
[2] = Operand(coords
);
5849 load
->definitions
[0] = Definition(tmp
);
5850 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5851 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5852 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5853 load
->dmask
= dmask
;
5855 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5856 load
->barrier
= barrier_image
;
5857 ctx
->block
->instructions
.emplace_back(std::move(load
));
5859 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5863 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5865 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5866 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5867 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5868 bool is_array
= glsl_sampler_type_is_array(type
);
5869 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5871 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5873 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5874 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5875 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5877 switch (data
.size()) {
5879 opcode
= aco_opcode::buffer_store_format_x
;
5882 opcode
= aco_opcode::buffer_store_format_xy
;
5885 opcode
= aco_opcode::buffer_store_format_xyz
;
5888 opcode
= aco_opcode::buffer_store_format_xyzw
;
5891 unreachable(">4 channel buffer image store");
5893 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5894 store
->operands
[0] = Operand(rsrc
);
5895 store
->operands
[1] = Operand(vindex
);
5896 store
->operands
[2] = Operand((uint32_t) 0);
5897 store
->operands
[3] = Operand(data
);
5898 store
->idxen
= true;
5901 store
->disable_wqm
= true;
5902 store
->barrier
= barrier_image
;
5903 ctx
->program
->needs_exact
= true;
5904 ctx
->block
->instructions
.emplace_back(std::move(store
));
5908 assert(data
.type() == RegType::vgpr
);
5909 Temp coords
= get_image_coords(ctx
, instr
, type
);
5910 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5912 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5913 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5915 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5916 store
->operands
[0] = Operand(resource
);
5917 store
->operands
[1] = Operand(data
);
5918 store
->operands
[2] = Operand(coords
);
5921 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5922 store
->dmask
= (1 << data
.size()) - 1;
5924 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5925 store
->disable_wqm
= true;
5926 store
->barrier
= barrier_image
;
5927 ctx
->program
->needs_exact
= true;
5928 ctx
->block
->instructions
.emplace_back(std::move(store
));
5932 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5934 /* return the previous value if dest is ever used */
5935 bool return_previous
= false;
5936 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5937 return_previous
= true;
5940 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5941 return_previous
= true;
5945 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5946 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5947 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5948 bool is_array
= glsl_sampler_type_is_array(type
);
5949 Builder
bld(ctx
->program
, ctx
->block
);
5951 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5952 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5954 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5955 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5957 aco_opcode buf_op
, image_op
;
5958 switch (instr
->intrinsic
) {
5959 case nir_intrinsic_image_deref_atomic_add
:
5960 buf_op
= aco_opcode::buffer_atomic_add
;
5961 image_op
= aco_opcode::image_atomic_add
;
5963 case nir_intrinsic_image_deref_atomic_umin
:
5964 buf_op
= aco_opcode::buffer_atomic_umin
;
5965 image_op
= aco_opcode::image_atomic_umin
;
5967 case nir_intrinsic_image_deref_atomic_imin
:
5968 buf_op
= aco_opcode::buffer_atomic_smin
;
5969 image_op
= aco_opcode::image_atomic_smin
;
5971 case nir_intrinsic_image_deref_atomic_umax
:
5972 buf_op
= aco_opcode::buffer_atomic_umax
;
5973 image_op
= aco_opcode::image_atomic_umax
;
5975 case nir_intrinsic_image_deref_atomic_imax
:
5976 buf_op
= aco_opcode::buffer_atomic_smax
;
5977 image_op
= aco_opcode::image_atomic_smax
;
5979 case nir_intrinsic_image_deref_atomic_and
:
5980 buf_op
= aco_opcode::buffer_atomic_and
;
5981 image_op
= aco_opcode::image_atomic_and
;
5983 case nir_intrinsic_image_deref_atomic_or
:
5984 buf_op
= aco_opcode::buffer_atomic_or
;
5985 image_op
= aco_opcode::image_atomic_or
;
5987 case nir_intrinsic_image_deref_atomic_xor
:
5988 buf_op
= aco_opcode::buffer_atomic_xor
;
5989 image_op
= aco_opcode::image_atomic_xor
;
5991 case nir_intrinsic_image_deref_atomic_exchange
:
5992 buf_op
= aco_opcode::buffer_atomic_swap
;
5993 image_op
= aco_opcode::image_atomic_swap
;
5995 case nir_intrinsic_image_deref_atomic_comp_swap
:
5996 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5997 image_op
= aco_opcode::image_atomic_cmpswap
;
6000 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
6003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6005 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
6006 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
6007 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
6008 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
6009 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6010 mubuf
->operands
[0] = Operand(resource
);
6011 mubuf
->operands
[1] = Operand(vindex
);
6012 mubuf
->operands
[2] = Operand((uint32_t)0);
6013 mubuf
->operands
[3] = Operand(data
);
6014 if (return_previous
)
6015 mubuf
->definitions
[0] = Definition(dst
);
6017 mubuf
->idxen
= true;
6018 mubuf
->glc
= return_previous
;
6019 mubuf
->dlc
= false; /* Not needed for atomics */
6020 mubuf
->disable_wqm
= true;
6021 mubuf
->barrier
= barrier_image
;
6022 ctx
->program
->needs_exact
= true;
6023 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6027 Temp coords
= get_image_coords(ctx
, instr
, type
);
6028 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6029 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6030 mimg
->operands
[0] = Operand(resource
);
6031 mimg
->operands
[1] = Operand(data
);
6032 mimg
->operands
[2] = Operand(coords
);
6033 if (return_previous
)
6034 mimg
->definitions
[0] = Definition(dst
);
6035 mimg
->glc
= return_previous
;
6036 mimg
->dlc
= false; /* Not needed for atomics */
6037 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6038 mimg
->dmask
= (1 << data
.size()) - 1;
6040 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6041 mimg
->disable_wqm
= true;
6042 mimg
->barrier
= barrier_image
;
6043 ctx
->program
->needs_exact
= true;
6044 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6048 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6050 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6051 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6052 Builder
bld(ctx
->program
, ctx
->block
);
6054 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6056 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6057 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6059 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6060 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6062 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6063 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6065 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6066 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6067 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6068 if (dst
.type() == RegType::vgpr
)
6069 bld
.copy(Definition(dst
), shr_dst
);
6071 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6073 emit_extract_vector(ctx
, desc
, 2, dst
);
6077 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6079 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6080 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6081 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6082 bool is_array
= glsl_sampler_type_is_array(type
);
6083 Builder
bld(ctx
->program
, ctx
->block
);
6085 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6086 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6087 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6091 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6094 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6096 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6098 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6099 mimg
->operands
[0] = Operand(resource
);
6100 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6101 mimg
->operands
[2] = Operand(lod
);
6102 uint8_t& dmask
= mimg
->dmask
;
6103 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6104 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6105 mimg
->da
= glsl_sampler_type_is_array(type
);
6106 mimg
->can_reorder
= true;
6107 Definition
& def
= mimg
->definitions
[0];
6108 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6110 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6111 glsl_sampler_type_is_array(type
)) {
6113 assert(instr
->dest
.ssa
.num_components
== 3);
6114 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6115 def
= Definition(tmp
);
6116 emit_split_vector(ctx
, tmp
, 3);
6118 /* divide 3rd value by 6 by multiplying with magic number */
6119 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6120 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6122 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6123 emit_extract_vector(ctx
, tmp
, 0, v1
),
6124 emit_extract_vector(ctx
, tmp
, 1, v1
),
6127 } else if (ctx
->options
->chip_class
== GFX9
&&
6128 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6129 glsl_sampler_type_is_array(type
)) {
6130 assert(instr
->dest
.ssa
.num_components
== 2);
6131 def
= Definition(dst
);
6134 def
= Definition(dst
);
6137 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6140 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6142 Builder
bld(ctx
->program
, ctx
->block
);
6143 unsigned num_components
= instr
->num_components
;
6145 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6146 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6147 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6149 unsigned access
= nir_intrinsic_access(instr
);
6150 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6151 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6153 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6154 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6155 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6157 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6158 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6160 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6161 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false, allow_smem
);
6164 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6166 Builder
bld(ctx
->program
, ctx
->block
);
6167 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6168 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6169 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6170 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6172 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6173 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6175 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6176 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6177 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6178 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6180 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6182 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6183 ctx
->options
->chip_class
>= GFX8
&&
6184 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6187 offset
= bld
.as_uniform(offset
);
6188 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6190 unsigned write_count
= 0;
6191 Temp write_datas
[32];
6192 unsigned offsets
[32];
6193 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6194 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6196 for (unsigned i
= 0; i
< write_count
; i
++) {
6197 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6198 if (smem
&& ctx
->stage
== fragment_fs
)
6199 op
= aco_opcode::p_fs_buffer_store_smem
;
6202 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6203 store
->operands
[0] = Operand(rsrc
);
6205 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6206 offset
, Operand(offsets
[i
]));
6207 store
->operands
[1] = Operand(off
);
6209 store
->operands
[1] = Operand(offset
);
6211 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6212 store
->operands
[1].setFixed(m0
);
6213 store
->operands
[2] = Operand(write_datas
[i
]);
6216 store
->disable_wqm
= true;
6217 store
->barrier
= barrier_buffer
;
6218 ctx
->block
->instructions
.emplace_back(std::move(store
));
6219 ctx
->program
->wb_smem_l1_on_end
= true;
6220 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6221 ctx
->block
->kind
|= block_kind_needs_lowering
;
6222 ctx
->program
->needs_exact
= true;
6225 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6226 store
->operands
[0] = Operand(rsrc
);
6227 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6228 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6229 store
->operands
[3] = Operand(write_datas
[i
]);
6230 store
->offset
= offsets
[i
];
6231 store
->offen
= (offset
.type() == RegType::vgpr
);
6234 store
->disable_wqm
= true;
6235 store
->barrier
= barrier_buffer
;
6236 ctx
->program
->needs_exact
= true;
6237 ctx
->block
->instructions
.emplace_back(std::move(store
));
6242 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6244 /* return the previous value if dest is ever used */
6245 bool return_previous
= false;
6246 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6247 return_previous
= true;
6250 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6251 return_previous
= true;
6255 Builder
bld(ctx
->program
, ctx
->block
);
6256 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6258 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6259 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6260 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6262 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6263 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6264 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6266 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6268 aco_opcode op32
, op64
;
6269 switch (instr
->intrinsic
) {
6270 case nir_intrinsic_ssbo_atomic_add
:
6271 op32
= aco_opcode::buffer_atomic_add
;
6272 op64
= aco_opcode::buffer_atomic_add_x2
;
6274 case nir_intrinsic_ssbo_atomic_imin
:
6275 op32
= aco_opcode::buffer_atomic_smin
;
6276 op64
= aco_opcode::buffer_atomic_smin_x2
;
6278 case nir_intrinsic_ssbo_atomic_umin
:
6279 op32
= aco_opcode::buffer_atomic_umin
;
6280 op64
= aco_opcode::buffer_atomic_umin_x2
;
6282 case nir_intrinsic_ssbo_atomic_imax
:
6283 op32
= aco_opcode::buffer_atomic_smax
;
6284 op64
= aco_opcode::buffer_atomic_smax_x2
;
6286 case nir_intrinsic_ssbo_atomic_umax
:
6287 op32
= aco_opcode::buffer_atomic_umax
;
6288 op64
= aco_opcode::buffer_atomic_umax_x2
;
6290 case nir_intrinsic_ssbo_atomic_and
:
6291 op32
= aco_opcode::buffer_atomic_and
;
6292 op64
= aco_opcode::buffer_atomic_and_x2
;
6294 case nir_intrinsic_ssbo_atomic_or
:
6295 op32
= aco_opcode::buffer_atomic_or
;
6296 op64
= aco_opcode::buffer_atomic_or_x2
;
6298 case nir_intrinsic_ssbo_atomic_xor
:
6299 op32
= aco_opcode::buffer_atomic_xor
;
6300 op64
= aco_opcode::buffer_atomic_xor_x2
;
6302 case nir_intrinsic_ssbo_atomic_exchange
:
6303 op32
= aco_opcode::buffer_atomic_swap
;
6304 op64
= aco_opcode::buffer_atomic_swap_x2
;
6306 case nir_intrinsic_ssbo_atomic_comp_swap
:
6307 op32
= aco_opcode::buffer_atomic_cmpswap
;
6308 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6311 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6313 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6314 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6315 mubuf
->operands
[0] = Operand(rsrc
);
6316 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6317 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6318 mubuf
->operands
[3] = Operand(data
);
6319 if (return_previous
)
6320 mubuf
->definitions
[0] = Definition(dst
);
6322 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6323 mubuf
->glc
= return_previous
;
6324 mubuf
->dlc
= false; /* Not needed for atomics */
6325 mubuf
->disable_wqm
= true;
6326 mubuf
->barrier
= barrier_buffer
;
6327 ctx
->program
->needs_exact
= true;
6328 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6331 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6333 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6334 Builder
bld(ctx
->program
, ctx
->block
);
6335 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6336 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6339 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6341 Builder
bld(ctx
->program
, ctx
->block
);
6342 unsigned num_components
= instr
->num_components
;
6343 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6345 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6346 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6347 num_components
, component_size
};
6348 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6349 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6350 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6351 info
.barrier
= barrier_buffer
;
6352 info
.can_reorder
= false;
6353 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6354 * it's safe to use SMEM */
6355 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6356 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6357 emit_global_load(ctx
, bld
, &info
);
6359 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6360 emit_smem_load(ctx
, bld
, &info
);
6364 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6366 Builder
bld(ctx
->program
, ctx
->block
);
6367 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6368 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6370 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6371 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6372 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6374 if (ctx
->options
->chip_class
>= GFX7
)
6375 addr
= as_vgpr(ctx
, addr
);
6377 unsigned write_count
= 0;
6378 Temp write_datas
[32];
6379 unsigned offsets
[32];
6380 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6381 16, &write_count
, write_datas
, offsets
);
6383 for (unsigned i
= 0; i
< write_count
; i
++) {
6384 if (ctx
->options
->chip_class
>= GFX7
) {
6385 unsigned offset
= offsets
[i
];
6386 Temp store_addr
= addr
;
6387 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6388 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6389 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6390 Temp carry
= bld
.tmp(bld
.lm
);
6391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6393 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6394 Operand(offset
), addr0
);
6395 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6397 carry
).def(1).setHint(vcc
);
6399 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6404 bool global
= ctx
->options
->chip_class
>= GFX9
;
6406 switch (write_datas
[i
].bytes()) {
6408 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6411 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6414 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6417 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6420 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6423 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6426 unreachable("store_global not implemented for this size.");
6429 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6430 flat
->operands
[0] = Operand(store_addr
);
6431 flat
->operands
[1] = Operand(s1
);
6432 flat
->operands
[2] = Operand(write_datas
[i
]);
6435 flat
->offset
= offset
;
6436 flat
->disable_wqm
= true;
6437 flat
->barrier
= barrier_buffer
;
6438 ctx
->program
->needs_exact
= true;
6439 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6441 assert(ctx
->options
->chip_class
== GFX6
);
6443 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6445 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6447 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6448 mubuf
->operands
[0] = Operand(rsrc
);
6449 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6450 mubuf
->operands
[2] = Operand(0u);
6451 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6454 mubuf
->offset
= offsets
[i
];
6455 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6456 mubuf
->disable_wqm
= true;
6457 mubuf
->barrier
= barrier_buffer
;
6458 ctx
->program
->needs_exact
= true;
6459 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6464 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6466 /* return the previous value if dest is ever used */
6467 bool return_previous
= false;
6468 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6469 return_previous
= true;
6472 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6473 return_previous
= true;
6477 Builder
bld(ctx
->program
, ctx
->block
);
6478 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6479 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6481 if (ctx
->options
->chip_class
>= GFX7
)
6482 addr
= as_vgpr(ctx
, addr
);
6484 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6485 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6486 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6488 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6490 aco_opcode op32
, op64
;
6492 if (ctx
->options
->chip_class
>= GFX7
) {
6493 bool global
= ctx
->options
->chip_class
>= GFX9
;
6494 switch (instr
->intrinsic
) {
6495 case nir_intrinsic_global_atomic_add
:
6496 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6497 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6499 case nir_intrinsic_global_atomic_imin
:
6500 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6501 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6503 case nir_intrinsic_global_atomic_umin
:
6504 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6505 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6507 case nir_intrinsic_global_atomic_imax
:
6508 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6509 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6511 case nir_intrinsic_global_atomic_umax
:
6512 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6513 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6515 case nir_intrinsic_global_atomic_and
:
6516 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6517 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6519 case nir_intrinsic_global_atomic_or
:
6520 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6521 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6523 case nir_intrinsic_global_atomic_xor
:
6524 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6525 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6527 case nir_intrinsic_global_atomic_exchange
:
6528 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6529 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6531 case nir_intrinsic_global_atomic_comp_swap
:
6532 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6533 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6536 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6539 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6540 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6541 flat
->operands
[0] = Operand(addr
);
6542 flat
->operands
[1] = Operand(s1
);
6543 flat
->operands
[2] = Operand(data
);
6544 if (return_previous
)
6545 flat
->definitions
[0] = Definition(dst
);
6546 flat
->glc
= return_previous
;
6547 flat
->dlc
= false; /* Not needed for atomics */
6549 flat
->disable_wqm
= true;
6550 flat
->barrier
= barrier_buffer
;
6551 ctx
->program
->needs_exact
= true;
6552 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6554 assert(ctx
->options
->chip_class
== GFX6
);
6556 switch (instr
->intrinsic
) {
6557 case nir_intrinsic_global_atomic_add
:
6558 op32
= aco_opcode::buffer_atomic_add
;
6559 op64
= aco_opcode::buffer_atomic_add_x2
;
6561 case nir_intrinsic_global_atomic_imin
:
6562 op32
= aco_opcode::buffer_atomic_smin
;
6563 op64
= aco_opcode::buffer_atomic_smin_x2
;
6565 case nir_intrinsic_global_atomic_umin
:
6566 op32
= aco_opcode::buffer_atomic_umin
;
6567 op64
= aco_opcode::buffer_atomic_umin_x2
;
6569 case nir_intrinsic_global_atomic_imax
:
6570 op32
= aco_opcode::buffer_atomic_smax
;
6571 op64
= aco_opcode::buffer_atomic_smax_x2
;
6573 case nir_intrinsic_global_atomic_umax
:
6574 op32
= aco_opcode::buffer_atomic_umax
;
6575 op64
= aco_opcode::buffer_atomic_umax_x2
;
6577 case nir_intrinsic_global_atomic_and
:
6578 op32
= aco_opcode::buffer_atomic_and
;
6579 op64
= aco_opcode::buffer_atomic_and_x2
;
6581 case nir_intrinsic_global_atomic_or
:
6582 op32
= aco_opcode::buffer_atomic_or
;
6583 op64
= aco_opcode::buffer_atomic_or_x2
;
6585 case nir_intrinsic_global_atomic_xor
:
6586 op32
= aco_opcode::buffer_atomic_xor
;
6587 op64
= aco_opcode::buffer_atomic_xor_x2
;
6589 case nir_intrinsic_global_atomic_exchange
:
6590 op32
= aco_opcode::buffer_atomic_swap
;
6591 op64
= aco_opcode::buffer_atomic_swap_x2
;
6593 case nir_intrinsic_global_atomic_comp_swap
:
6594 op32
= aco_opcode::buffer_atomic_cmpswap
;
6595 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6598 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6601 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6603 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6605 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6606 mubuf
->operands
[0] = Operand(rsrc
);
6607 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6608 mubuf
->operands
[2] = Operand(0u);
6609 mubuf
->operands
[3] = Operand(data
);
6610 if (return_previous
)
6611 mubuf
->definitions
[0] = Definition(dst
);
6612 mubuf
->glc
= return_previous
;
6615 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6616 mubuf
->disable_wqm
= true;
6617 mubuf
->barrier
= barrier_buffer
;
6618 ctx
->program
->needs_exact
= true;
6619 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6623 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6624 Builder
bld(ctx
->program
, ctx
->block
);
6625 switch(instr
->intrinsic
) {
6626 case nir_intrinsic_group_memory_barrier
:
6627 case nir_intrinsic_memory_barrier
:
6628 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6630 case nir_intrinsic_memory_barrier_buffer
:
6631 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6633 case nir_intrinsic_memory_barrier_image
:
6634 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6636 case nir_intrinsic_memory_barrier_tcs_patch
:
6637 case nir_intrinsic_memory_barrier_shared
:
6638 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6641 unreachable("Unimplemented memory barrier intrinsic");
6646 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6648 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6649 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6650 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6651 Builder
bld(ctx
->program
, ctx
->block
);
6653 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6654 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6655 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6658 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6660 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6661 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6662 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6663 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6665 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6666 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6669 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6671 unsigned offset
= nir_intrinsic_base(instr
);
6672 Builder
bld(ctx
->program
, ctx
->block
);
6673 Operand m
= load_lds_size_m0(bld
);
6674 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6675 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6677 unsigned num_operands
= 3;
6678 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6679 switch(instr
->intrinsic
) {
6680 case nir_intrinsic_shared_atomic_add
:
6681 op32
= aco_opcode::ds_add_u32
;
6682 op64
= aco_opcode::ds_add_u64
;
6683 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6684 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6686 case nir_intrinsic_shared_atomic_imin
:
6687 op32
= aco_opcode::ds_min_i32
;
6688 op64
= aco_opcode::ds_min_i64
;
6689 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6690 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6692 case nir_intrinsic_shared_atomic_umin
:
6693 op32
= aco_opcode::ds_min_u32
;
6694 op64
= aco_opcode::ds_min_u64
;
6695 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6696 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6698 case nir_intrinsic_shared_atomic_imax
:
6699 op32
= aco_opcode::ds_max_i32
;
6700 op64
= aco_opcode::ds_max_i64
;
6701 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6702 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6704 case nir_intrinsic_shared_atomic_umax
:
6705 op32
= aco_opcode::ds_max_u32
;
6706 op64
= aco_opcode::ds_max_u64
;
6707 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6708 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6710 case nir_intrinsic_shared_atomic_and
:
6711 op32
= aco_opcode::ds_and_b32
;
6712 op64
= aco_opcode::ds_and_b64
;
6713 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6714 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6716 case nir_intrinsic_shared_atomic_or
:
6717 op32
= aco_opcode::ds_or_b32
;
6718 op64
= aco_opcode::ds_or_b64
;
6719 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6720 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6722 case nir_intrinsic_shared_atomic_xor
:
6723 op32
= aco_opcode::ds_xor_b32
;
6724 op64
= aco_opcode::ds_xor_b64
;
6725 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6726 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6728 case nir_intrinsic_shared_atomic_exchange
:
6729 op32
= aco_opcode::ds_write_b32
;
6730 op64
= aco_opcode::ds_write_b64
;
6731 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6732 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6734 case nir_intrinsic_shared_atomic_comp_swap
:
6735 op32
= aco_opcode::ds_cmpst_b32
;
6736 op64
= aco_opcode::ds_cmpst_b64
;
6737 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6738 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6742 unreachable("Unhandled shared atomic intrinsic");
6745 /* return the previous value if dest is ever used */
6746 bool return_previous
= false;
6747 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6748 return_previous
= true;
6751 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6752 return_previous
= true;
6757 if (data
.size() == 1) {
6758 assert(instr
->dest
.ssa
.bit_size
== 32);
6759 op
= return_previous
? op32_rtn
: op32
;
6761 assert(instr
->dest
.ssa
.bit_size
== 64);
6762 op
= return_previous
? op64_rtn
: op64
;
6765 if (offset
> 65535) {
6766 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6770 aco_ptr
<DS_instruction
> ds
;
6771 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6772 ds
->operands
[0] = Operand(address
);
6773 ds
->operands
[1] = Operand(data
);
6774 if (num_operands
== 4)
6775 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6776 ds
->operands
[num_operands
- 1] = m
;
6777 ds
->offset0
= offset
;
6778 if (return_previous
)
6779 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6780 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6783 Temp
get_scratch_resource(isel_context
*ctx
)
6785 Builder
bld(ctx
->program
, ctx
->block
);
6786 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6787 if (ctx
->stage
!= compute_cs
)
6788 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6790 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6791 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6793 if (ctx
->program
->chip_class
>= GFX10
) {
6794 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6795 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6796 S_008F0C_RESOURCE_LEVEL(1);
6797 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6798 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6799 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6802 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6803 if (ctx
->program
->chip_class
<= GFX8
)
6804 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6806 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6809 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6810 Builder
bld(ctx
->program
, ctx
->block
);
6811 Temp rsrc
= get_scratch_resource(ctx
);
6812 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6813 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6815 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6816 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6817 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6818 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6819 info
.swizzle_component_size
= 16;
6820 info
.can_reorder
= false;
6821 info
.soffset
= ctx
->program
->scratch_offset
;
6822 emit_mubuf_load(ctx
, bld
, &info
);
6825 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6826 Builder
bld(ctx
->program
, ctx
->block
);
6827 Temp rsrc
= get_scratch_resource(ctx
);
6828 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6829 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6831 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6832 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6834 unsigned write_count
= 0;
6835 Temp write_datas
[32];
6836 unsigned offsets
[32];
6837 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6838 16, &write_count
, write_datas
, offsets
);
6840 for (unsigned i
= 0; i
< write_count
; i
++) {
6841 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6842 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6846 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6847 uint8_t log2_ps_iter_samples
;
6848 if (ctx
->program
->info
->ps
.force_persample
) {
6849 log2_ps_iter_samples
=
6850 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6852 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6855 /* The bit pattern matches that used by fixed function fragment
6857 static const unsigned ps_iter_masks
[] = {
6858 0xffff, /* not used */
6864 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6866 Builder
bld(ctx
->program
, ctx
->block
);
6868 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6869 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6870 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6871 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6872 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6873 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6876 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6877 Builder
bld(ctx
->program
, ctx
->block
);
6879 unsigned stream
= nir_intrinsic_stream_id(instr
);
6880 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6881 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6882 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6885 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6887 unsigned num_components
=
6888 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6889 assert(num_components
);
6891 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6892 unsigned stream_offset
= 0;
6893 for (unsigned i
= 0; i
< stream
; i
++) {
6894 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6895 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6898 /* Limit on the stride field for <= GFX7. */
6899 assert(stride
< (1 << 14));
6901 Temp gsvs_dwords
[4];
6902 for (unsigned i
= 0; i
< 4; i
++)
6903 gsvs_dwords
[i
] = bld
.tmp(s1
);
6904 bld
.pseudo(aco_opcode::p_split_vector
,
6905 Definition(gsvs_dwords
[0]),
6906 Definition(gsvs_dwords
[1]),
6907 Definition(gsvs_dwords
[2]),
6908 Definition(gsvs_dwords
[3]),
6911 if (stream_offset
) {
6912 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6914 Temp carry
= bld
.tmp(s1
);
6915 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6916 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6919 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6920 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6922 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6923 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6925 unsigned offset
= 0;
6926 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6927 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6930 for (unsigned j
= 0; j
< 4; j
++) {
6931 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6934 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6935 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6936 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6937 if (const_offset
>= 4096u) {
6938 if (vaddr_offset
.isUndefined())
6939 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6941 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6942 const_offset
%= 4096u;
6945 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6946 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6947 mtbuf
->operands
[1] = vaddr_offset
;
6948 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6949 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6950 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6951 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6952 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6953 mtbuf
->offset
= const_offset
;
6956 mtbuf
->barrier
= barrier_gs_data
;
6957 mtbuf
->can_reorder
= true;
6958 bld
.insert(std::move(mtbuf
));
6961 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6964 /* outputs for the next vertex are undefined and keeping them around can
6965 * create invalid IR with control flow */
6966 ctx
->outputs
.mask
[i
] = 0;
6969 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6972 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6974 Builder
bld(ctx
->program
, ctx
->block
);
6976 if (cluster_size
== 1) {
6978 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6979 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6980 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6981 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6982 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6983 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6984 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6985 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6986 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6987 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6988 //subgroupAnd(val) -> (exec & ~val) == 0
6989 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6990 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6991 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6992 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6993 //subgroupOr(val) -> (val & exec) != 0
6994 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6995 return bool_to_vector_condition(ctx
, tmp
);
6996 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6997 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6998 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6999 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7000 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7001 return bool_to_vector_condition(ctx
, tmp
);
7003 //subgroupClustered{And,Or,Xor}(val, n) ->
7004 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7005 //cluster_offset = ~(n - 1) & lane_id
7006 //cluster_mask = ((1 << n) - 1)
7007 //subgroupClusteredAnd():
7008 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7009 //subgroupClusteredOr():
7010 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7011 //subgroupClusteredXor():
7012 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7013 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7014 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7017 if (op
== nir_op_iand
)
7018 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7020 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7022 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7024 if (ctx
->program
->chip_class
<= GFX7
)
7025 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7026 else if (ctx
->program
->wave_size
== 64)
7027 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7029 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7030 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7031 if (cluster_mask
!= 0xffffffff)
7032 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7034 Definition cmp_def
= Definition();
7035 if (op
== nir_op_iand
) {
7036 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7037 } else if (op
== nir_op_ior
) {
7038 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7039 } else if (op
== nir_op_ixor
) {
7040 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7041 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7042 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7044 cmp_def
.setHint(vcc
);
7045 return cmp_def
.getTemp();
7049 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7051 Builder
bld(ctx
->program
, ctx
->block
);
7053 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7054 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7055 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7057 if (op
== nir_op_iand
)
7058 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7060 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7062 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7063 Temp lo
= lohi
.def(0).getTemp();
7064 Temp hi
= lohi
.def(1).getTemp();
7065 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7067 Definition cmp_def
= Definition();
7068 if (op
== nir_op_iand
)
7069 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7070 else if (op
== nir_op_ior
)
7071 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7072 else if (op
== nir_op_ixor
)
7073 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7074 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7075 cmp_def
.setHint(vcc
);
7076 return cmp_def
.getTemp();
7079 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7081 Builder
bld(ctx
->program
, ctx
->block
);
7083 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7084 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7085 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7086 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7087 if (op
== nir_op_iand
)
7088 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7089 else if (op
== nir_op_ior
)
7090 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7091 else if (op
== nir_op_ixor
)
7092 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7098 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7100 Builder
bld(ctx
->program
, ctx
->block
);
7101 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7102 if (src
.regClass().type() == RegType::vgpr
) {
7103 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7104 } else if (src
.regClass() == s1
) {
7105 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7106 } else if (src
.regClass() == s2
) {
7107 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7109 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7110 nir_print_instr(&instr
->instr
, stderr
);
7111 fprintf(stderr
, "\n");
7115 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7117 Builder
bld(ctx
->program
, ctx
->block
);
7118 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7119 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7120 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7122 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7123 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7124 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7125 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7128 if (ctx
->program
->chip_class
>= GFX8
) {
7129 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7130 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7131 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7132 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7133 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7134 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7136 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7137 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7138 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7139 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7140 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7141 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7142 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7143 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7144 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7145 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7148 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7149 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7150 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7151 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7152 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7153 Temp wqm1
= bld
.tmp(v1
);
7154 emit_wqm(ctx
, tmp1
, wqm1
, true);
7155 Temp wqm2
= bld
.tmp(v1
);
7156 emit_wqm(ctx
, tmp2
, wqm2
, true);
7157 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7161 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7163 Builder
bld(ctx
->program
, ctx
->block
);
7164 switch(instr
->intrinsic
) {
7165 case nir_intrinsic_load_barycentric_sample
:
7166 case nir_intrinsic_load_barycentric_pixel
:
7167 case nir_intrinsic_load_barycentric_centroid
: {
7168 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7169 Temp bary
= Temp(0, s2
);
7171 case INTERP_MODE_SMOOTH
:
7172 case INTERP_MODE_NONE
:
7173 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7174 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7175 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7176 bary
= ctx
->persp_centroid
;
7177 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7178 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7180 case INTERP_MODE_NOPERSPECTIVE
:
7181 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7182 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7183 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7184 bary
= ctx
->linear_centroid
;
7185 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7186 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7191 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7192 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7193 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7194 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7195 Operand(p1
), Operand(p2
));
7196 emit_split_vector(ctx
, dst
, 2);
7199 case nir_intrinsic_load_barycentric_model
: {
7200 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7202 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7203 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7204 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7205 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7206 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7207 Operand(p1
), Operand(p2
), Operand(p3
));
7208 emit_split_vector(ctx
, dst
, 3);
7211 case nir_intrinsic_load_barycentric_at_sample
: {
7212 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7213 switch (ctx
->options
->key
.fs
.num_samples
) {
7214 case 2: sample_pos_offset
+= 1 << 3; break;
7215 case 4: sample_pos_offset
+= 3 << 3; break;
7216 case 8: sample_pos_offset
+= 7 << 3; break;
7220 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7221 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7222 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7223 if (addr
.type() == RegType::sgpr
) {
7226 sample_pos_offset
+= const_addr
->u32
<< 3;
7227 offset
= Operand(sample_pos_offset
);
7228 } else if (ctx
->options
->chip_class
>= GFX9
) {
7229 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7231 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7232 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7235 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7236 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7238 } else if (ctx
->options
->chip_class
>= GFX9
) {
7239 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7240 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7241 } else if (ctx
->options
->chip_class
>= GFX7
) {
7242 /* addr += private_segment_buffer + sample_pos_offset */
7243 Temp tmp0
= bld
.tmp(s1
);
7244 Temp tmp1
= bld
.tmp(s1
);
7245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7246 Definition scc_tmp
= bld
.def(s1
, scc
);
7247 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7248 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7249 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7250 Temp pck0
= bld
.tmp(v1
);
7251 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7252 tmp1
= as_vgpr(ctx
, tmp1
);
7253 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7254 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7256 /* sample_pos = flat_load_dwordx2 addr */
7257 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7259 assert(ctx
->options
->chip_class
== GFX6
);
7261 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7262 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7263 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7265 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7266 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7268 sample_pos
= bld
.tmp(v2
);
7270 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7271 load
->definitions
[0] = Definition(sample_pos
);
7272 load
->operands
[0] = Operand(rsrc
);
7273 load
->operands
[1] = Operand(addr
);
7274 load
->operands
[2] = Operand(0u);
7275 load
->offset
= sample_pos_offset
;
7277 load
->addr64
= true;
7280 load
->disable_wqm
= false;
7281 load
->barrier
= barrier_none
;
7282 load
->can_reorder
= true;
7283 ctx
->block
->instructions
.emplace_back(std::move(load
));
7286 /* sample_pos -= 0.5 */
7287 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7288 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7289 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7290 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7291 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7293 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7296 case nir_intrinsic_load_barycentric_at_offset
: {
7297 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7298 RegClass rc
= RegClass(offset
.type(), 1);
7299 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7300 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7301 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7304 case nir_intrinsic_load_front_face
: {
7305 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7306 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7309 case nir_intrinsic_load_view_index
: {
7310 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7311 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7312 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7318 case nir_intrinsic_load_layer_id
: {
7319 unsigned idx
= nir_intrinsic_base(instr
);
7320 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7321 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7324 case nir_intrinsic_load_frag_coord
: {
7325 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7328 case nir_intrinsic_load_sample_pos
: {
7329 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7330 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7331 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7332 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7333 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7336 case nir_intrinsic_load_tess_coord
:
7337 visit_load_tess_coord(ctx
, instr
);
7339 case nir_intrinsic_load_interpolated_input
:
7340 visit_load_interpolated_input(ctx
, instr
);
7342 case nir_intrinsic_store_output
:
7343 visit_store_output(ctx
, instr
);
7345 case nir_intrinsic_load_input
:
7346 case nir_intrinsic_load_input_vertex
:
7347 visit_load_input(ctx
, instr
);
7349 case nir_intrinsic_load_output
:
7350 visit_load_output(ctx
, instr
);
7352 case nir_intrinsic_load_per_vertex_input
:
7353 visit_load_per_vertex_input(ctx
, instr
);
7355 case nir_intrinsic_load_per_vertex_output
:
7356 visit_load_per_vertex_output(ctx
, instr
);
7358 case nir_intrinsic_store_per_vertex_output
:
7359 visit_store_per_vertex_output(ctx
, instr
);
7361 case nir_intrinsic_load_ubo
:
7362 visit_load_ubo(ctx
, instr
);
7364 case nir_intrinsic_load_push_constant
:
7365 visit_load_push_constant(ctx
, instr
);
7367 case nir_intrinsic_load_constant
:
7368 visit_load_constant(ctx
, instr
);
7370 case nir_intrinsic_vulkan_resource_index
:
7371 visit_load_resource(ctx
, instr
);
7373 case nir_intrinsic_discard
:
7374 visit_discard(ctx
, instr
);
7376 case nir_intrinsic_discard_if
:
7377 visit_discard_if(ctx
, instr
);
7379 case nir_intrinsic_load_shared
:
7380 visit_load_shared(ctx
, instr
);
7382 case nir_intrinsic_store_shared
:
7383 visit_store_shared(ctx
, instr
);
7385 case nir_intrinsic_shared_atomic_add
:
7386 case nir_intrinsic_shared_atomic_imin
:
7387 case nir_intrinsic_shared_atomic_umin
:
7388 case nir_intrinsic_shared_atomic_imax
:
7389 case nir_intrinsic_shared_atomic_umax
:
7390 case nir_intrinsic_shared_atomic_and
:
7391 case nir_intrinsic_shared_atomic_or
:
7392 case nir_intrinsic_shared_atomic_xor
:
7393 case nir_intrinsic_shared_atomic_exchange
:
7394 case nir_intrinsic_shared_atomic_comp_swap
:
7395 visit_shared_atomic(ctx
, instr
);
7397 case nir_intrinsic_image_deref_load
:
7398 visit_image_load(ctx
, instr
);
7400 case nir_intrinsic_image_deref_store
:
7401 visit_image_store(ctx
, instr
);
7403 case nir_intrinsic_image_deref_atomic_add
:
7404 case nir_intrinsic_image_deref_atomic_umin
:
7405 case nir_intrinsic_image_deref_atomic_imin
:
7406 case nir_intrinsic_image_deref_atomic_umax
:
7407 case nir_intrinsic_image_deref_atomic_imax
:
7408 case nir_intrinsic_image_deref_atomic_and
:
7409 case nir_intrinsic_image_deref_atomic_or
:
7410 case nir_intrinsic_image_deref_atomic_xor
:
7411 case nir_intrinsic_image_deref_atomic_exchange
:
7412 case nir_intrinsic_image_deref_atomic_comp_swap
:
7413 visit_image_atomic(ctx
, instr
);
7415 case nir_intrinsic_image_deref_size
:
7416 visit_image_size(ctx
, instr
);
7418 case nir_intrinsic_load_ssbo
:
7419 visit_load_ssbo(ctx
, instr
);
7421 case nir_intrinsic_store_ssbo
:
7422 visit_store_ssbo(ctx
, instr
);
7424 case nir_intrinsic_load_global
:
7425 visit_load_global(ctx
, instr
);
7427 case nir_intrinsic_store_global
:
7428 visit_store_global(ctx
, instr
);
7430 case nir_intrinsic_global_atomic_add
:
7431 case nir_intrinsic_global_atomic_imin
:
7432 case nir_intrinsic_global_atomic_umin
:
7433 case nir_intrinsic_global_atomic_imax
:
7434 case nir_intrinsic_global_atomic_umax
:
7435 case nir_intrinsic_global_atomic_and
:
7436 case nir_intrinsic_global_atomic_or
:
7437 case nir_intrinsic_global_atomic_xor
:
7438 case nir_intrinsic_global_atomic_exchange
:
7439 case nir_intrinsic_global_atomic_comp_swap
:
7440 visit_global_atomic(ctx
, instr
);
7442 case nir_intrinsic_ssbo_atomic_add
:
7443 case nir_intrinsic_ssbo_atomic_imin
:
7444 case nir_intrinsic_ssbo_atomic_umin
:
7445 case nir_intrinsic_ssbo_atomic_imax
:
7446 case nir_intrinsic_ssbo_atomic_umax
:
7447 case nir_intrinsic_ssbo_atomic_and
:
7448 case nir_intrinsic_ssbo_atomic_or
:
7449 case nir_intrinsic_ssbo_atomic_xor
:
7450 case nir_intrinsic_ssbo_atomic_exchange
:
7451 case nir_intrinsic_ssbo_atomic_comp_swap
:
7452 visit_atomic_ssbo(ctx
, instr
);
7454 case nir_intrinsic_load_scratch
:
7455 visit_load_scratch(ctx
, instr
);
7457 case nir_intrinsic_store_scratch
:
7458 visit_store_scratch(ctx
, instr
);
7460 case nir_intrinsic_get_buffer_size
:
7461 visit_get_buffer_size(ctx
, instr
);
7463 case nir_intrinsic_control_barrier
: {
7464 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7465 /* GFX6 only (thanks to a hw bug workaround):
7466 * The real barrier instruction isn’t needed, because an entire patch
7467 * always fits into a single wave.
7472 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7473 bld
.sopp(aco_opcode::s_barrier
);
7477 case nir_intrinsic_memory_barrier_tcs_patch
:
7478 case nir_intrinsic_group_memory_barrier
:
7479 case nir_intrinsic_memory_barrier
:
7480 case nir_intrinsic_memory_barrier_buffer
:
7481 case nir_intrinsic_memory_barrier_image
:
7482 case nir_intrinsic_memory_barrier_shared
:
7483 emit_memory_barrier(ctx
, instr
);
7485 case nir_intrinsic_load_num_work_groups
: {
7486 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7487 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7488 emit_split_vector(ctx
, dst
, 3);
7491 case nir_intrinsic_load_local_invocation_id
: {
7492 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7493 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7494 emit_split_vector(ctx
, dst
, 3);
7497 case nir_intrinsic_load_work_group_id
: {
7498 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7499 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7501 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7502 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7503 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7504 emit_split_vector(ctx
, dst
, 3);
7507 case nir_intrinsic_load_local_invocation_index
: {
7508 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7510 /* The tg_size bits [6:11] contain the subgroup id,
7511 * we need this multiplied by the wave size, and then OR the thread id to it.
7513 if (ctx
->program
->wave_size
== 64) {
7514 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7515 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7516 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7517 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7519 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7520 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7521 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7522 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7526 case nir_intrinsic_load_subgroup_id
: {
7527 if (ctx
->stage
== compute_cs
) {
7528 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7529 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7531 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7535 case nir_intrinsic_load_subgroup_invocation
: {
7536 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7539 case nir_intrinsic_load_num_subgroups
: {
7540 if (ctx
->stage
== compute_cs
)
7541 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7542 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7544 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7547 case nir_intrinsic_ballot
: {
7548 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7549 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7550 Definition tmp
= bld
.def(dst
.regClass());
7551 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7552 if (instr
->src
[0].ssa
->bit_size
== 1) {
7553 assert(src
.regClass() == bld
.lm
);
7554 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7555 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7556 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7557 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7558 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7560 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7561 nir_print_instr(&instr
->instr
, stderr
);
7562 fprintf(stderr
, "\n");
7564 if (dst
.size() != bld
.lm
.size()) {
7565 /* Wave32 with ballot size set to 64 */
7566 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7568 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7571 case nir_intrinsic_shuffle
:
7572 case nir_intrinsic_read_invocation
: {
7573 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7574 if (!nir_src_is_divergent(instr
->src
[0])) {
7575 emit_uniform_subgroup(ctx
, instr
, src
);
7577 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7578 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7579 tid
= bld
.as_uniform(tid
);
7580 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7581 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7582 Temp tmp
= bld
.tmp(v1
);
7583 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7584 if (dst
.type() == RegType::vgpr
)
7585 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7587 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7588 } else if (src
.regClass() == v1
) {
7589 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7590 } else if (src
.regClass() == v2
) {
7591 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7592 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7593 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7594 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7595 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7596 emit_split_vector(ctx
, dst
, 2);
7597 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7598 assert(src
.regClass() == bld
.lm
);
7599 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7600 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7601 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7602 assert(src
.regClass() == bld
.lm
);
7604 if (ctx
->program
->chip_class
<= GFX7
)
7605 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7606 else if (ctx
->program
->wave_size
== 64)
7607 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7609 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7610 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7611 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7612 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7614 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7615 nir_print_instr(&instr
->instr
, stderr
);
7616 fprintf(stderr
, "\n");
7621 case nir_intrinsic_load_sample_id
: {
7622 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7623 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7626 case nir_intrinsic_load_sample_mask_in
: {
7627 visit_load_sample_mask_in(ctx
, instr
);
7630 case nir_intrinsic_read_first_invocation
: {
7631 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7632 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7633 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7635 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7637 } else if (src
.regClass() == v2
) {
7638 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7639 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7640 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7641 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7642 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7643 emit_split_vector(ctx
, dst
, 2);
7644 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7645 assert(src
.regClass() == bld
.lm
);
7646 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7647 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7648 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7649 } else if (src
.regClass() == s1
) {
7650 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7651 } else if (src
.regClass() == s2
) {
7652 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7654 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7655 nir_print_instr(&instr
->instr
, stderr
);
7656 fprintf(stderr
, "\n");
7660 case nir_intrinsic_vote_all
: {
7661 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7662 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7663 assert(src
.regClass() == bld
.lm
);
7664 assert(dst
.regClass() == bld
.lm
);
7666 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7667 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7668 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7671 case nir_intrinsic_vote_any
: {
7672 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7673 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7674 assert(src
.regClass() == bld
.lm
);
7675 assert(dst
.regClass() == bld
.lm
);
7677 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7678 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7681 case nir_intrinsic_reduce
:
7682 case nir_intrinsic_inclusive_scan
:
7683 case nir_intrinsic_exclusive_scan
: {
7684 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7685 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7686 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7687 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7688 nir_intrinsic_cluster_size(instr
) : 0;
7689 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7691 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7692 emit_uniform_subgroup(ctx
, instr
, src
);
7693 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7694 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7696 else if (op
== nir_op_iadd
)
7698 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7700 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7702 switch (instr
->intrinsic
) {
7703 case nir_intrinsic_reduce
:
7704 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7706 case nir_intrinsic_exclusive_scan
:
7707 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7709 case nir_intrinsic_inclusive_scan
:
7710 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7715 } else if (cluster_size
== 1) {
7716 bld
.copy(Definition(dst
), src
);
7718 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7720 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7724 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7725 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7740 unreachable("unknown reduction op");
7746 switch (instr
->intrinsic
) {
7747 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7748 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7749 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7751 unreachable("unknown reduce intrinsic");
7754 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7755 reduce
->operands
[0] = Operand(src
);
7756 // filled in by aco_reduce_assign.cpp, used internally as part of the
7758 assert(dst
.size() == 1 || dst
.size() == 2);
7759 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7760 reduce
->operands
[2] = Operand(v1
.as_linear());
7762 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7763 reduce
->definitions
[0] = Definition(tmp_dst
);
7764 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7765 reduce
->definitions
[2] = Definition();
7766 reduce
->definitions
[3] = Definition(scc
, s1
);
7767 reduce
->definitions
[4] = Definition();
7768 reduce
->reduce_op
= reduce_op
;
7769 reduce
->cluster_size
= cluster_size
;
7770 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7772 emit_wqm(ctx
, tmp_dst
, dst
);
7776 case nir_intrinsic_quad_broadcast
: {
7777 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7778 if (!nir_dest_is_divergent(instr
->dest
)) {
7779 emit_uniform_subgroup(ctx
, instr
, src
);
7781 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7782 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7783 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7785 if (instr
->dest
.ssa
.bit_size
== 1) {
7786 assert(src
.regClass() == bld
.lm
);
7787 assert(dst
.regClass() == bld
.lm
);
7788 uint32_t half_mask
= 0x11111111u
<< lane
;
7789 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7790 Temp tmp
= bld
.tmp(bld
.lm
);
7791 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7792 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7793 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7794 emit_wqm(ctx
, tmp
, dst
);
7795 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7796 Temp tmp
= bld
.tmp(v1
);
7797 if (ctx
->program
->chip_class
>= GFX8
)
7798 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7800 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7801 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7802 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7803 Temp tmp
= bld
.tmp(v1
);
7804 if (ctx
->program
->chip_class
>= GFX8
)
7805 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7807 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7808 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7809 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7810 if (ctx
->program
->chip_class
>= GFX8
)
7811 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7813 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7814 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7815 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7816 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7817 if (ctx
->program
->chip_class
>= GFX8
) {
7818 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7819 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7821 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7822 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7824 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7825 emit_split_vector(ctx
, dst
, 2);
7827 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7828 nir_print_instr(&instr
->instr
, stderr
);
7829 fprintf(stderr
, "\n");
7834 case nir_intrinsic_quad_swap_horizontal
:
7835 case nir_intrinsic_quad_swap_vertical
:
7836 case nir_intrinsic_quad_swap_diagonal
:
7837 case nir_intrinsic_quad_swizzle_amd
: {
7838 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7839 if (!nir_dest_is_divergent(instr
->dest
)) {
7840 emit_uniform_subgroup(ctx
, instr
, src
);
7843 uint16_t dpp_ctrl
= 0;
7844 switch (instr
->intrinsic
) {
7845 case nir_intrinsic_quad_swap_horizontal
:
7846 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7848 case nir_intrinsic_quad_swap_vertical
:
7849 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7851 case nir_intrinsic_quad_swap_diagonal
:
7852 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7854 case nir_intrinsic_quad_swizzle_amd
:
7855 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7860 if (ctx
->program
->chip_class
< GFX8
)
7861 dpp_ctrl
|= (1 << 15);
7863 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7864 if (instr
->dest
.ssa
.bit_size
== 1) {
7865 assert(src
.regClass() == bld
.lm
);
7866 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7867 if (ctx
->program
->chip_class
>= GFX8
)
7868 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7870 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7871 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7872 emit_wqm(ctx
, tmp
, dst
);
7873 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7874 Temp tmp
= bld
.tmp(v1
);
7875 if (ctx
->program
->chip_class
>= GFX8
)
7876 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7878 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7879 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7880 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7881 Temp tmp
= bld
.tmp(v1
);
7882 if (ctx
->program
->chip_class
>= GFX8
)
7883 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7885 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7886 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7887 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7889 if (ctx
->program
->chip_class
>= GFX8
)
7890 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7892 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7893 emit_wqm(ctx
, tmp
, dst
);
7894 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7895 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7896 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7897 if (ctx
->program
->chip_class
>= GFX8
) {
7898 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7899 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7901 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7902 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7904 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7905 emit_split_vector(ctx
, dst
, 2);
7907 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7908 nir_print_instr(&instr
->instr
, stderr
);
7909 fprintf(stderr
, "\n");
7913 case nir_intrinsic_masked_swizzle_amd
: {
7914 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7915 if (!nir_dest_is_divergent(instr
->dest
)) {
7916 emit_uniform_subgroup(ctx
, instr
, src
);
7919 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7920 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7921 if (dst
.regClass() == v1
) {
7923 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7925 } else if (dst
.regClass() == v2
) {
7926 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7927 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7928 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7929 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7930 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7931 emit_split_vector(ctx
, dst
, 2);
7933 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7934 nir_print_instr(&instr
->instr
, stderr
);
7935 fprintf(stderr
, "\n");
7939 case nir_intrinsic_write_invocation_amd
: {
7940 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7941 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7942 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7943 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7944 if (dst
.regClass() == v1
) {
7945 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7946 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7947 } else if (dst
.regClass() == v2
) {
7948 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7949 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7950 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7951 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7952 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7953 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7954 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7955 emit_split_vector(ctx
, dst
, 2);
7957 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7958 nir_print_instr(&instr
->instr
, stderr
);
7959 fprintf(stderr
, "\n");
7963 case nir_intrinsic_mbcnt_amd
: {
7964 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7965 RegClass rc
= RegClass(src
.type(), 1);
7966 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7967 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7968 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7969 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7970 emit_wqm(ctx
, wqm_tmp
, dst
);
7973 case nir_intrinsic_load_helper_invocation
: {
7974 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7975 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7976 ctx
->block
->kind
|= block_kind_needs_lowering
;
7977 ctx
->program
->needs_exact
= true;
7980 case nir_intrinsic_is_helper_invocation
: {
7981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7982 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7983 ctx
->block
->kind
|= block_kind_needs_lowering
;
7984 ctx
->program
->needs_exact
= true;
7987 case nir_intrinsic_demote
:
7988 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7990 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7991 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7992 ctx
->block
->kind
|= block_kind_uses_demote
;
7993 ctx
->program
->needs_exact
= true;
7995 case nir_intrinsic_demote_if
: {
7996 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7997 assert(src
.regClass() == bld
.lm
);
7998 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7999 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8001 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8002 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8003 ctx
->block
->kind
|= block_kind_uses_demote
;
8004 ctx
->program
->needs_exact
= true;
8007 case nir_intrinsic_first_invocation
: {
8008 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8009 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8012 case nir_intrinsic_shader_clock
: {
8014 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
8015 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
8016 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8017 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8020 case nir_intrinsic_load_vertex_id_zero_base
: {
8021 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8022 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8025 case nir_intrinsic_load_first_vertex
: {
8026 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8027 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8030 case nir_intrinsic_load_base_instance
: {
8031 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8032 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8035 case nir_intrinsic_load_instance_id
: {
8036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8037 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8040 case nir_intrinsic_load_draw_id
: {
8041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8042 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8045 case nir_intrinsic_load_invocation_id
: {
8046 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8048 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8049 if (ctx
->options
->chip_class
>= GFX10
)
8050 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8052 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8053 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8054 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8055 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8057 unreachable("Unsupported stage for load_invocation_id");
8062 case nir_intrinsic_load_primitive_id
: {
8063 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8065 switch (ctx
->shader
->info
.stage
) {
8066 case MESA_SHADER_GEOMETRY
:
8067 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8069 case MESA_SHADER_TESS_CTRL
:
8070 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8072 case MESA_SHADER_TESS_EVAL
:
8073 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8076 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8081 case nir_intrinsic_load_patch_vertices_in
: {
8082 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8083 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8085 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8086 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8089 case nir_intrinsic_emit_vertex_with_counter
: {
8090 visit_emit_vertex_with_counter(ctx
, instr
);
8093 case nir_intrinsic_end_primitive_with_counter
: {
8094 unsigned stream
= nir_intrinsic_stream_id(instr
);
8095 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8098 case nir_intrinsic_set_vertex_count
: {
8099 /* unused, the HW keeps track of this for us */
8103 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8104 nir_print_instr(&instr
->instr
, stderr
);
8105 fprintf(stderr
, "\n");
8113 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8114 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8115 enum glsl_base_type
*stype
)
8117 nir_deref_instr
*texture_deref_instr
= NULL
;
8118 nir_deref_instr
*sampler_deref_instr
= NULL
;
8121 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8122 switch (instr
->src
[i
].src_type
) {
8123 case nir_tex_src_texture_deref
:
8124 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8126 case nir_tex_src_sampler_deref
:
8127 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8129 case nir_tex_src_plane
:
8130 plane
= nir_src_as_int(instr
->src
[i
].src
);
8137 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8139 if (!sampler_deref_instr
)
8140 sampler_deref_instr
= texture_deref_instr
;
8143 assert(instr
->op
!= nir_texop_txf_ms
&&
8144 instr
->op
!= nir_texop_samples_identical
);
8145 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8146 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8147 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8148 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8149 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8150 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8152 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8155 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8157 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8158 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8159 Builder
bld(ctx
->program
, ctx
->block
);
8161 /* to avoid unnecessary moves, we split and recombine sampler and image */
8162 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8163 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8164 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8165 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8166 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8167 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8168 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8169 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8171 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8172 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8173 img
[0], img
[1], img
[2], img
[3],
8174 img
[4], img
[5], img
[6], img
[7]);
8175 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8176 samp
[0], samp
[1], samp
[2], samp
[3]);
8179 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8180 instr
->op
== nir_texop_samples_identical
))
8181 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8184 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8185 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8187 Builder
bld(ctx
->program
, ctx
->block
);
8189 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8190 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8191 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8193 Operand
neg_one(0xbf800000u
);
8194 Operand
one(0x3f800000u
);
8195 Operand
two(0x40000000u
);
8196 Operand
four(0x40800000u
);
8198 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8199 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8200 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8202 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8203 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8204 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8205 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8208 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8209 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8210 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8212 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8215 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8216 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8217 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8220 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8221 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8223 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8224 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8227 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8229 Builder
bld(ctx
->program
, ctx
->block
);
8230 Temp ma
, tc
, sc
, id
;
8233 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8235 // see comment in ac_prepare_cube_coords()
8236 if (ctx
->options
->chip_class
<= GFX8
)
8237 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8240 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8242 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8243 vop3a
->operands
[0] = Operand(ma
);
8244 vop3a
->abs
[0] = true;
8245 Temp invma
= bld
.tmp(v1
);
8246 vop3a
->definitions
[0] = Definition(invma
);
8247 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8249 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8251 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8253 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8255 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8257 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8260 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8261 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8263 for (unsigned i
= 0; i
< 2; i
++) {
8264 // see comment in ac_prepare_cube_coords()
8266 Temp deriv_sc
, deriv_tc
;
8267 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8268 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8270 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8272 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8273 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8274 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8275 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8276 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8277 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8278 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8281 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8282 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8286 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8293 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8295 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8297 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8298 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8301 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8302 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8303 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8307 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8309 Builder
bld(ctx
->program
, ctx
->block
);
8310 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8311 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8312 has_clamped_lod
= false;
8313 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8314 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8315 clamped_lod
= Temp();
8316 std::vector
<Temp
> coords
;
8317 std::vector
<Temp
> derivs
;
8318 nir_const_value
*sample_index_cv
= NULL
;
8319 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8320 enum glsl_base_type stype
;
8321 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8323 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8324 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8325 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8326 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8328 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8329 switch (instr
->src
[i
].src_type
) {
8330 case nir_tex_src_coord
: {
8331 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8332 for (unsigned i
= 0; i
< coord
.size(); i
++)
8333 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8336 case nir_tex_src_bias
:
8337 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8340 case nir_tex_src_lod
: {
8341 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8343 if (val
&& val
->f32
<= 0.0) {
8346 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8351 case nir_tex_src_min_lod
:
8352 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8353 has_clamped_lod
= true;
8355 case nir_tex_src_comparator
:
8356 if (instr
->is_shadow
) {
8357 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8361 case nir_tex_src_offset
:
8362 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8363 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8366 case nir_tex_src_ddx
:
8367 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8370 case nir_tex_src_ddy
:
8371 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8374 case nir_tex_src_ms_index
:
8375 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8376 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8377 has_sample_index
= true;
8379 case nir_tex_src_texture_offset
:
8380 case nir_tex_src_sampler_offset
:
8386 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8387 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8389 if (instr
->op
== nir_texop_texture_samples
) {
8390 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8392 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8393 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8394 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8396 Operand default_sample
= Operand(1u);
8397 if (ctx
->options
->robust_buffer_access
) {
8398 /* Extract the second dword of the descriptor, if it's
8399 * all zero, then it's a null descriptor.
8401 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8402 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8403 default_sample
= Operand(is_non_null_descriptor
);
8406 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8407 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8408 samples
, default_sample
, bld
.scc(is_msaa
));
8412 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8413 aco_ptr
<Instruction
> tmp_instr
;
8414 Temp acc
, pack
= Temp();
8416 uint32_t pack_const
= 0;
8417 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8418 if (!const_offset
[i
])
8420 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8423 if (offset
.type() == RegType::sgpr
) {
8424 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8425 if (const_offset
[i
])
8428 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8429 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8432 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8435 if (pack
== Temp()) {
8438 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8442 if (pack_const
&& pack
!= Temp())
8443 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8445 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8446 if (const_offset
[i
])
8449 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8450 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8453 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8456 if (pack
== Temp()) {
8459 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8463 if (pack_const
&& pack
!= Temp())
8464 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8466 if (pack_const
&& pack
== Temp())
8467 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8468 else if (pack
== Temp())
8474 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8475 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8477 /* pack derivatives */
8478 if (has_ddx
|| has_ddy
) {
8479 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8480 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8481 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8482 derivs
= {ddx
, zero
, ddy
, zero
};
8484 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8485 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8486 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8487 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8492 if (instr
->coord_components
> 1 &&
8493 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8495 instr
->op
!= nir_texop_txf
)
8496 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8498 if (instr
->coord_components
> 2 &&
8499 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8500 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8501 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8502 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8504 instr
->op
!= nir_texop_txf
&&
8505 instr
->op
!= nir_texop_txf_ms
&&
8506 instr
->op
!= nir_texop_fragment_fetch
&&
8507 instr
->op
!= nir_texop_fragment_mask_fetch
)
8508 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8510 if (ctx
->options
->chip_class
== GFX9
&&
8511 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8512 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8513 assert(coords
.size() > 0 && coords
.size() < 3);
8515 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8516 Operand((uint32_t) 0) :
8517 Operand((uint32_t) 0x3f000000)));
8520 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8522 if (instr
->op
== nir_texop_samples_identical
)
8523 resource
= fmask_ptr
;
8525 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8526 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8527 instr
->op
!= nir_texop_txs
&&
8528 instr
->op
!= nir_texop_fragment_fetch
&&
8529 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8530 assert(has_sample_index
);
8531 Operand
op(sample_index
);
8532 if (sample_index_cv
)
8533 op
= Operand(sample_index_cv
->u32
);
8534 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8537 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8538 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8539 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8540 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8545 /* Build tex instruction */
8546 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8547 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8548 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8550 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8553 /* gather4 selects the component by dmask and always returns vec4 */
8554 if (instr
->op
== nir_texop_tg4
) {
8555 assert(instr
->dest
.ssa
.num_components
== 4);
8556 if (instr
->is_shadow
)
8559 dmask
= 1 << instr
->component
;
8560 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8561 tmp_dst
= bld
.tmp(v4
);
8562 } else if (instr
->op
== nir_texop_samples_identical
) {
8563 tmp_dst
= bld
.tmp(v1
);
8564 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8565 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8568 aco_ptr
<MIMG_instruction
> tex
;
8569 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8571 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8573 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8574 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8577 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8578 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8580 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8581 tex
->operands
[0] = Operand(resource
);
8582 tex
->operands
[1] = Operand(s4
); /* no sampler */
8583 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8584 if (ctx
->options
->chip_class
== GFX9
&&
8585 instr
->op
== nir_texop_txs
&&
8586 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8588 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8589 } else if (instr
->op
== nir_texop_query_levels
) {
8590 tex
->dmask
= 1 << 3;
8595 tex
->definitions
[0] = Definition(tmp_dst
);
8597 tex
->can_reorder
= true;
8598 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8601 /* divide 3rd value by 6 by multiplying with magic number */
8602 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8603 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8604 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8605 assert(instr
->dest
.ssa
.num_components
== 3);
8606 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8607 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8608 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8609 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8614 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8618 Temp tg4_compare_cube_wa64
= Temp();
8620 if (tg4_integer_workarounds
) {
8621 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8622 tex
->operands
[0] = Operand(resource
);
8623 tex
->operands
[1] = Operand(s4
); /* no sampler */
8624 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8628 Temp size
= bld
.tmp(v2
);
8629 tex
->definitions
[0] = Definition(size
);
8630 tex
->can_reorder
= true;
8631 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8632 emit_split_vector(ctx
, size
, size
.size());
8635 for (unsigned i
= 0; i
< 2; i
++) {
8636 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8637 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8638 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8639 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8642 Temp new_coords
[2] = {
8643 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8644 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8647 if (tg4_integer_cube_workaround
) {
8648 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8649 Temp desc
[resource
.size()];
8650 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8651 Format::PSEUDO
, 1, resource
.size())};
8652 split
->operands
[0] = Operand(resource
);
8653 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8654 desc
[i
] = bld
.tmp(s1
);
8655 split
->definitions
[i
] = Definition(desc
[i
]);
8657 ctx
->block
->instructions
.emplace_back(std::move(split
));
8659 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8660 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8661 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8664 if (stype
== GLSL_TYPE_UINT
) {
8665 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8666 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8667 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8668 bld
.scc(compare_cube_wa
));
8670 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8671 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8672 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8673 bld
.scc(compare_cube_wa
));
8675 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8676 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8678 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8680 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8681 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8682 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8684 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8685 Format::PSEUDO
, resource
.size(), 1)};
8686 for (unsigned i
= 0; i
< resource
.size(); i
++)
8687 vec
->operands
[i
] = Operand(desc
[i
]);
8688 resource
= bld
.tmp(resource
.regClass());
8689 vec
->definitions
[0] = Definition(resource
);
8690 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8692 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8693 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8694 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8695 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8697 coords
[0] = new_coords
[0];
8698 coords
[1] = new_coords
[1];
8701 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8702 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8704 assert(coords
.size() == 1);
8705 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8709 op
= aco_opcode::buffer_load_format_x
; break;
8711 op
= aco_opcode::buffer_load_format_xy
; break;
8713 op
= aco_opcode::buffer_load_format_xyz
; break;
8715 op
= aco_opcode::buffer_load_format_xyzw
; break;
8717 unreachable("Tex instruction loads more than 4 components.");
8720 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8721 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8724 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8726 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8727 mubuf
->operands
[0] = Operand(resource
);
8728 mubuf
->operands
[1] = Operand(coords
[0]);
8729 mubuf
->operands
[2] = Operand((uint32_t) 0);
8730 mubuf
->definitions
[0] = Definition(tmp_dst
);
8731 mubuf
->idxen
= true;
8732 mubuf
->can_reorder
= true;
8733 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8735 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8739 /* gather MIMG address components */
8740 std::vector
<Temp
> args
;
8742 args
.emplace_back(offset
);
8744 args
.emplace_back(bias
);
8746 args
.emplace_back(compare
);
8748 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8750 args
.insert(args
.end(), coords
.begin(), coords
.end());
8751 if (has_sample_index
)
8752 args
.emplace_back(sample_index
);
8754 args
.emplace_back(lod
);
8755 if (has_clamped_lod
)
8756 args
.emplace_back(clamped_lod
);
8758 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8759 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8760 vec
->definitions
[0] = Definition(arg
);
8761 for (unsigned i
= 0; i
< args
.size(); i
++)
8762 vec
->operands
[i
] = Operand(args
[i
]);
8763 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8766 if (instr
->op
== nir_texop_txf
||
8767 instr
->op
== nir_texop_txf_ms
||
8768 instr
->op
== nir_texop_samples_identical
||
8769 instr
->op
== nir_texop_fragment_fetch
||
8770 instr
->op
== nir_texop_fragment_mask_fetch
) {
8771 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8772 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8773 tex
->operands
[0] = Operand(resource
);
8774 tex
->operands
[1] = Operand(s4
); /* no sampler */
8775 tex
->operands
[2] = Operand(arg
);
8780 tex
->definitions
[0] = Definition(tmp_dst
);
8781 tex
->can_reorder
= true;
8782 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8784 if (instr
->op
== nir_texop_samples_identical
) {
8785 assert(dmask
== 1 && dst
.regClass() == v1
);
8786 assert(dst
.id() != tmp_dst
.id());
8788 Temp tmp
= bld
.tmp(bld
.lm
);
8789 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8790 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8793 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8798 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8799 aco_opcode opcode
= aco_opcode::image_sample
;
8800 if (has_offset
) { /* image_sample_*_o */
8801 if (has_clamped_lod
) {
8803 opcode
= aco_opcode::image_sample_c_cl_o
;
8805 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8807 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8809 opcode
= aco_opcode::image_sample_cl_o
;
8811 opcode
= aco_opcode::image_sample_d_cl_o
;
8813 opcode
= aco_opcode::image_sample_b_cl_o
;
8815 } else if (has_compare
) {
8816 opcode
= aco_opcode::image_sample_c_o
;
8818 opcode
= aco_opcode::image_sample_c_d_o
;
8820 opcode
= aco_opcode::image_sample_c_b_o
;
8822 opcode
= aco_opcode::image_sample_c_lz_o
;
8824 opcode
= aco_opcode::image_sample_c_l_o
;
8826 opcode
= aco_opcode::image_sample_o
;
8828 opcode
= aco_opcode::image_sample_d_o
;
8830 opcode
= aco_opcode::image_sample_b_o
;
8832 opcode
= aco_opcode::image_sample_lz_o
;
8834 opcode
= aco_opcode::image_sample_l_o
;
8836 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8838 opcode
= aco_opcode::image_sample_c_cl
;
8840 opcode
= aco_opcode::image_sample_c_d_cl
;
8842 opcode
= aco_opcode::image_sample_c_b_cl
;
8844 opcode
= aco_opcode::image_sample_cl
;
8846 opcode
= aco_opcode::image_sample_d_cl
;
8848 opcode
= aco_opcode::image_sample_b_cl
;
8850 } else { /* no offset */
8852 opcode
= aco_opcode::image_sample_c
;
8854 opcode
= aco_opcode::image_sample_c_d
;
8856 opcode
= aco_opcode::image_sample_c_b
;
8858 opcode
= aco_opcode::image_sample_c_lz
;
8860 opcode
= aco_opcode::image_sample_c_l
;
8862 opcode
= aco_opcode::image_sample
;
8864 opcode
= aco_opcode::image_sample_d
;
8866 opcode
= aco_opcode::image_sample_b
;
8868 opcode
= aco_opcode::image_sample_lz
;
8870 opcode
= aco_opcode::image_sample_l
;
8874 if (instr
->op
== nir_texop_tg4
) {
8875 if (has_offset
) { /* image_gather4_*_o */
8877 opcode
= aco_opcode::image_gather4_c_lz_o
;
8879 opcode
= aco_opcode::image_gather4_c_l_o
;
8881 opcode
= aco_opcode::image_gather4_c_b_o
;
8883 opcode
= aco_opcode::image_gather4_lz_o
;
8885 opcode
= aco_opcode::image_gather4_l_o
;
8887 opcode
= aco_opcode::image_gather4_b_o
;
8891 opcode
= aco_opcode::image_gather4_c_lz
;
8893 opcode
= aco_opcode::image_gather4_c_l
;
8895 opcode
= aco_opcode::image_gather4_c_b
;
8897 opcode
= aco_opcode::image_gather4_lz
;
8899 opcode
= aco_opcode::image_gather4_l
;
8901 opcode
= aco_opcode::image_gather4_b
;
8904 } else if (instr
->op
== nir_texop_lod
) {
8905 opcode
= aco_opcode::image_get_lod
;
8908 /* we don't need the bias, sample index, compare value or offset to be
8909 * computed in WQM but if the p_create_vector copies the coordinates, then it
8910 * needs to be in WQM */
8911 if (ctx
->stage
== fragment_fs
&&
8912 !has_derivs
&& !has_lod
&& !level_zero
&&
8913 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8914 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8915 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8917 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8918 tex
->operands
[0] = Operand(resource
);
8919 tex
->operands
[1] = Operand(sampler
);
8920 tex
->operands
[2] = Operand(arg
);
8924 tex
->definitions
[0] = Definition(tmp_dst
);
8925 tex
->can_reorder
= true;
8926 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8928 if (tg4_integer_cube_workaround
) {
8929 assert(tmp_dst
.id() != dst
.id());
8930 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8932 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8934 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8935 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8937 if (stype
== GLSL_TYPE_UINT
)
8938 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8940 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8941 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8943 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8944 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8945 val
[0], val
[1], val
[2], val
[3]);
8947 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8948 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8953 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
)
8955 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8956 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8959 return Operand(tmp
);
8962 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8964 aco_ptr
<Pseudo_instruction
> phi
;
8965 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8966 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8968 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8969 logical
|= ctx
->block
->kind
& block_kind_merge
;
8970 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8972 /* we want a sorted list of sources, since the predecessor list is also sorted */
8973 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8974 nir_foreach_phi_src(src
, instr
)
8975 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8977 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8978 unsigned num_operands
= 0;
8979 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8980 unsigned num_defined
= 0;
8981 unsigned cur_pred_idx
= 0;
8982 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8983 if (cur_pred_idx
< preds
.size()) {
8984 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8985 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8986 unsigned skipped
= 0;
8987 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8989 if (cur_pred_idx
+ skipped
< preds
.size()) {
8990 for (unsigned i
= 0; i
< skipped
; i
++)
8991 operands
[num_operands
++] = Operand(dst
.regClass());
8992 cur_pred_idx
+= skipped
;
8997 /* Handle missing predecessors at the end. This shouldn't happen with loop
8998 * headers and we can't ignore these sources for loop header phis. */
8999 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
9002 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass());
9003 operands
[num_operands
++] = op
;
9004 num_defined
+= !op
.isUndefined();
9006 /* handle block_kind_continue_or_break at loop exit blocks */
9007 while (cur_pred_idx
++ < preds
.size())
9008 operands
[num_operands
++] = Operand(dst
.regClass());
9010 /* If the loop ends with a break, still add a linear continue edge in case
9011 * that break is divergent or continue_or_break is used. We'll either remove
9012 * this operand later in visit_loop() if it's not necessary or replace the
9013 * undef with something correct. */
9014 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
9015 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
9016 nir_block
*last
= nir_loop_last_block(loop
);
9017 if (last
->successors
[0] != instr
->instr
.block
)
9018 operands
[num_operands
++] = Operand(RegClass());
9021 if (num_defined
== 0) {
9022 Builder
bld(ctx
->program
, ctx
->block
);
9023 if (dst
.regClass() == s1
) {
9024 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
9025 } else if (dst
.regClass() == v1
) {
9026 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
9028 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9029 for (unsigned i
= 0; i
< dst
.size(); i
++)
9030 vec
->operands
[i
] = Operand(0u);
9031 vec
->definitions
[0] = Definition(dst
);
9032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9037 /* we can use a linear phi in some cases if one src is undef */
9038 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9039 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9041 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9042 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9043 assert(invert
->kind
& block_kind_invert
);
9045 unsigned then_block
= invert
->linear_preds
[0];
9047 Block
* insert_block
= NULL
;
9048 for (unsigned i
= 0; i
< num_operands
; i
++) {
9049 Operand op
= operands
[i
];
9050 if (op
.isUndefined())
9052 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9053 phi
->operands
[0] = op
;
9056 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9057 phi
->operands
[1] = Operand(dst
.regClass());
9058 phi
->definitions
[0] = Definition(dst
);
9059 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9063 /* try to scalarize vector phis */
9064 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9065 // TODO: scalarize linear phis on divergent ifs
9066 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9067 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9068 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9069 Operand src
= operands
[i
];
9070 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9071 can_scalarize
= false;
9073 if (can_scalarize
) {
9074 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9075 assert(dst
.size() % num_components
== 0);
9076 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9078 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9079 for (unsigned k
= 0; k
< num_components
; k
++) {
9080 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9081 for (unsigned i
= 0; i
< num_operands
; i
++) {
9082 Operand src
= operands
[i
];
9083 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9085 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9086 phi
->definitions
[0] = Definition(phi_dst
);
9087 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9088 new_vec
[k
] = phi_dst
;
9089 vec
->operands
[k
] = Operand(phi_dst
);
9091 vec
->definitions
[0] = Definition(dst
);
9092 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9093 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9098 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9099 for (unsigned i
= 0; i
< num_operands
; i
++)
9100 phi
->operands
[i
] = operands
[i
];
9101 phi
->definitions
[0] = Definition(dst
);
9102 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9106 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9108 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9110 assert(dst
.type() == RegType::sgpr
);
9112 if (dst
.size() == 1) {
9113 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9115 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9116 for (unsigned i
= 0; i
< dst
.size(); i
++)
9117 vec
->operands
[i
] = Operand(0u);
9118 vec
->definitions
[0] = Definition(dst
);
9119 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9123 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9125 Builder
bld(ctx
->program
, ctx
->block
);
9126 Block
*logical_target
;
9127 append_logical_end(ctx
->block
);
9128 unsigned idx
= ctx
->block
->index
;
9130 switch (instr
->type
) {
9131 case nir_jump_break
:
9132 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9133 add_logical_edge(idx
, logical_target
);
9134 ctx
->block
->kind
|= block_kind_break
;
9136 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9137 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9138 /* uniform break - directly jump out of the loop */
9139 ctx
->block
->kind
|= block_kind_uniform
;
9140 ctx
->cf_info
.has_branch
= true;
9141 bld
.branch(aco_opcode::p_branch
);
9142 add_linear_edge(idx
, logical_target
);
9145 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9146 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9148 case nir_jump_continue
:
9149 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9150 add_logical_edge(idx
, logical_target
);
9151 ctx
->block
->kind
|= block_kind_continue
;
9153 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9154 /* for potential uniform breaks after this continue,
9155 we must ensure that they are handled correctly */
9156 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9157 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9158 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9160 /* uniform continue - directly jump to the loop header */
9161 ctx
->block
->kind
|= block_kind_uniform
;
9162 ctx
->cf_info
.has_branch
= true;
9163 bld
.branch(aco_opcode::p_branch
);
9164 add_linear_edge(idx
, logical_target
);
9169 fprintf(stderr
, "Unknown NIR jump instr: ");
9170 nir_print_instr(&instr
->instr
, stderr
);
9171 fprintf(stderr
, "\n");
9175 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9176 ctx
->cf_info
.exec_potentially_empty_break
= true;
9177 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9180 /* remove critical edges from linear CFG */
9181 bld
.branch(aco_opcode::p_branch
);
9182 Block
* break_block
= ctx
->program
->create_and_insert_block();
9183 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9184 break_block
->kind
|= block_kind_uniform
;
9185 add_linear_edge(idx
, break_block
);
9186 /* the loop_header pointer might be invalidated by this point */
9187 if (instr
->type
== nir_jump_continue
)
9188 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9189 add_linear_edge(break_block
->index
, logical_target
);
9190 bld
.reset(break_block
);
9191 bld
.branch(aco_opcode::p_branch
);
9193 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9194 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9195 add_linear_edge(idx
, continue_block
);
9196 append_logical_start(continue_block
);
9197 ctx
->block
= continue_block
;
9201 void visit_block(isel_context
*ctx
, nir_block
*block
)
9203 nir_foreach_instr(instr
, block
) {
9204 switch (instr
->type
) {
9205 case nir_instr_type_alu
:
9206 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9208 case nir_instr_type_load_const
:
9209 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9211 case nir_instr_type_intrinsic
:
9212 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9214 case nir_instr_type_tex
:
9215 visit_tex(ctx
, nir_instr_as_tex(instr
));
9217 case nir_instr_type_phi
:
9218 visit_phi(ctx
, nir_instr_as_phi(instr
));
9220 case nir_instr_type_ssa_undef
:
9221 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9223 case nir_instr_type_deref
:
9225 case nir_instr_type_jump
:
9226 visit_jump(ctx
, nir_instr_as_jump(instr
));
9229 fprintf(stderr
, "Unknown NIR instr type: ");
9230 nir_print_instr(instr
, stderr
);
9231 fprintf(stderr
, "\n");
9236 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9237 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9242 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9243 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9245 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9246 RegClass rc
= vals
[0].regClass();
9248 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9250 unsigned next_pred
= 1;
9252 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9253 Block
& block
= ctx
->program
->blocks
[idx
];
9254 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9255 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9259 if (block
.kind
& block_kind_continue
) {
9260 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9265 bool all_same
= true;
9266 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9267 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9271 val
= vals
[block
.linear_preds
[0] - first
];
9273 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9274 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9275 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9276 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9277 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9278 phi
->definitions
[0] = Definition(val
.getTemp());
9279 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9281 vals
[idx
- first
] = val
;
9284 return vals
[last
- first
];
9287 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9289 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9290 append_logical_end(ctx
->block
);
9291 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9292 Builder
bld(ctx
->program
, ctx
->block
);
9293 bld
.branch(aco_opcode::p_branch
);
9294 unsigned loop_preheader_idx
= ctx
->block
->index
;
9296 Block loop_exit
= Block();
9297 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9298 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9300 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9301 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9302 loop_header
->kind
|= block_kind_loop_header
;
9303 add_edge(loop_preheader_idx
, loop_header
);
9304 ctx
->block
= loop_header
;
9306 /* emit loop body */
9307 unsigned loop_header_idx
= loop_header
->index
;
9308 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9309 append_logical_start(ctx
->block
);
9310 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9312 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9313 if (!ctx
->cf_info
.has_branch
) {
9314 append_logical_end(ctx
->block
);
9315 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9316 /* Discards can result in code running with an empty exec mask.
9317 * This would result in divergent breaks not ever being taken. As a
9318 * workaround, break the loop when the loop mask is empty instead of
9319 * always continuing. */
9320 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9321 unsigned block_idx
= ctx
->block
->index
;
9323 /* create helper blocks to avoid critical edges */
9324 Block
*break_block
= ctx
->program
->create_and_insert_block();
9325 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9326 break_block
->kind
= block_kind_uniform
;
9327 bld
.reset(break_block
);
9328 bld
.branch(aco_opcode::p_branch
);
9329 add_linear_edge(block_idx
, break_block
);
9330 add_linear_edge(break_block
->index
, &loop_exit
);
9332 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9333 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9334 continue_block
->kind
= block_kind_uniform
;
9335 bld
.reset(continue_block
);
9336 bld
.branch(aco_opcode::p_branch
);
9337 add_linear_edge(block_idx
, continue_block
);
9338 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9340 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9341 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9342 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9344 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9345 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9346 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9348 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9351 bld
.reset(ctx
->block
);
9352 bld
.branch(aco_opcode::p_branch
);
9355 /* Fixup phis in loop header from unreachable blocks.
9356 * has_branch/has_divergent_branch also indicates if the loop ends with a
9357 * break/continue instruction, but we don't emit those if unreachable=true */
9359 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9360 bool linear
= ctx
->cf_info
.has_branch
;
9361 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9362 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9363 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9364 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9365 /* the last operand should be the one that needs to be removed */
9366 instr
->operands
.pop_back();
9367 } else if (!is_phi(instr
)) {
9373 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9374 * and the previous one shouldn't both happen at once because a break in the
9375 * merge block would get CSE'd */
9376 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9377 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9378 Operand vals
[num_vals
];
9379 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9380 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9381 if (ctx
->cf_info
.has_branch
)
9382 instr
->operands
.pop_back();
9384 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9385 } else if (!is_phi(instr
)) {
9391 ctx
->cf_info
.has_branch
= false;
9393 // TODO: if the loop has not a single exit, we must add one °°
9394 /* emit loop successor block */
9395 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9396 append_logical_start(ctx
->block
);
9399 // TODO: check if it is beneficial to not branch on continues
9400 /* trim linear phis in loop header */
9401 for (auto&& instr
: loop_entry
->instructions
) {
9402 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9403 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9404 new_phi
->definitions
[0] = instr
->definitions
[0];
9405 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9406 new_phi
->operands
[i
] = instr
->operands
[i
];
9407 /* check that the remaining operands are all the same */
9408 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9409 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9410 instr
.swap(new_phi
);
9411 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9420 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9424 append_logical_end(ctx
->block
);
9425 ctx
->block
->kind
|= block_kind_branch
;
9427 /* branch to linear then block */
9428 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9429 aco_ptr
<Pseudo_branch_instruction
> branch
;
9430 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9431 branch
->operands
[0] = Operand(cond
);
9432 ctx
->block
->instructions
.push_back(std::move(branch
));
9434 ic
->BB_if_idx
= ctx
->block
->index
;
9435 ic
->BB_invert
= Block();
9436 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9437 /* Invert blocks are intentionally not marked as top level because they
9438 * are not part of the logical cfg. */
9439 ic
->BB_invert
.kind
|= block_kind_invert
;
9440 ic
->BB_endif
= Block();
9441 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9442 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9444 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9445 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9446 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9447 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9448 ctx
->cf_info
.parent_if
.is_divergent
= true;
9450 /* divergent branches use cbranch_execz */
9451 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9452 ctx
->cf_info
.exec_potentially_empty_break
= false;
9453 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9455 /** emit logical then block */
9456 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9457 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9458 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9459 ctx
->block
= BB_then_logical
;
9460 append_logical_start(BB_then_logical
);
9463 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9465 Block
*BB_then_logical
= ctx
->block
;
9466 append_logical_end(BB_then_logical
);
9467 /* branch from logical then block to invert block */
9468 aco_ptr
<Pseudo_branch_instruction
> branch
;
9469 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9470 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9471 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9472 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9473 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9474 BB_then_logical
->kind
|= block_kind_uniform
;
9475 assert(!ctx
->cf_info
.has_branch
);
9476 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9477 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9479 /** emit linear then block */
9480 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9481 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9482 BB_then_linear
->kind
|= block_kind_uniform
;
9483 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9484 /* branch from linear then block to invert block */
9485 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9486 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9487 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9489 /** emit invert merge block */
9490 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9491 ic
->invert_idx
= ctx
->block
->index
;
9493 /* branch to linear else block (skip else) */
9494 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9495 branch
->operands
[0] = Operand(ic
->cond
);
9496 ctx
->block
->instructions
.push_back(std::move(branch
));
9498 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9499 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9500 ic
->exec_potentially_empty_break_depth_old
=
9501 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9502 /* divergent branches use cbranch_execz */
9503 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9504 ctx
->cf_info
.exec_potentially_empty_break
= false;
9505 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9507 /** emit logical else block */
9508 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9509 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9510 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9511 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9512 ctx
->block
= BB_else_logical
;
9513 append_logical_start(BB_else_logical
);
9516 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9518 Block
*BB_else_logical
= ctx
->block
;
9519 append_logical_end(BB_else_logical
);
9521 /* branch from logical else block to endif block */
9522 aco_ptr
<Pseudo_branch_instruction
> branch
;
9523 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9524 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9525 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9526 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9527 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9528 BB_else_logical
->kind
|= block_kind_uniform
;
9530 assert(!ctx
->cf_info
.has_branch
);
9531 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9534 /** emit linear else block */
9535 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9536 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9537 BB_else_linear
->kind
|= block_kind_uniform
;
9538 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9540 /* branch from linear else block to endif block */
9541 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9542 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9543 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9546 /** emit endif merge block */
9547 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9548 append_logical_start(ctx
->block
);
9551 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9552 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9553 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9554 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9555 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9556 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9557 !ctx
->cf_info
.parent_if
.is_divergent
) {
9558 ctx
->cf_info
.exec_potentially_empty_break
= false;
9559 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9561 /* uniform control flow never has an empty exec-mask */
9562 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9563 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9564 ctx
->cf_info
.exec_potentially_empty_break
= false;
9565 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9569 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9571 assert(cond
.regClass() == s1
);
9573 append_logical_end(ctx
->block
);
9574 ctx
->block
->kind
|= block_kind_uniform
;
9576 aco_ptr
<Pseudo_branch_instruction
> branch
;
9577 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9578 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9579 branch
->operands
[0] = Operand(cond
);
9580 branch
->operands
[0].setFixed(scc
);
9581 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9583 ic
->BB_if_idx
= ctx
->block
->index
;
9584 ic
->BB_endif
= Block();
9585 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9586 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9588 ctx
->cf_info
.has_branch
= false;
9589 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9591 /** emit then block */
9592 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9593 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9594 add_edge(ic
->BB_if_idx
, BB_then
);
9595 append_logical_start(BB_then
);
9596 ctx
->block
= BB_then
;
9599 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9601 Block
*BB_then
= ctx
->block
;
9603 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9604 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9606 if (!ic
->uniform_has_then_branch
) {
9607 append_logical_end(BB_then
);
9608 /* branch from then block to endif block */
9609 aco_ptr
<Pseudo_branch_instruction
> branch
;
9610 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9611 BB_then
->instructions
.emplace_back(std::move(branch
));
9612 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9613 if (!ic
->then_branch_divergent
)
9614 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9615 BB_then
->kind
|= block_kind_uniform
;
9618 ctx
->cf_info
.has_branch
= false;
9619 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9621 /** emit else block */
9622 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9623 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9624 add_edge(ic
->BB_if_idx
, BB_else
);
9625 append_logical_start(BB_else
);
9626 ctx
->block
= BB_else
;
9629 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9631 Block
*BB_else
= ctx
->block
;
9633 if (!ctx
->cf_info
.has_branch
) {
9634 append_logical_end(BB_else
);
9635 /* branch from then block to endif block */
9636 aco_ptr
<Pseudo_branch_instruction
> branch
;
9637 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9638 BB_else
->instructions
.emplace_back(std::move(branch
));
9639 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9640 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9641 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9642 BB_else
->kind
|= block_kind_uniform
;
9645 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9646 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9648 /** emit endif merge block */
9649 if (!ctx
->cf_info
.has_branch
) {
9650 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9651 append_logical_start(ctx
->block
);
9655 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9657 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9658 Builder
bld(ctx
->program
, ctx
->block
);
9659 aco_ptr
<Pseudo_branch_instruction
> branch
;
9662 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9664 * Uniform conditionals are represented in the following way*) :
9666 * The linear and logical CFG:
9669 * BB_THEN (logical) BB_ELSE (logical)
9673 * *) Exceptions may be due to break and continue statements within loops
9674 * If a break/continue happens within uniform control flow, it branches
9675 * to the loop exit/entry block. Otherwise, it branches to the next
9679 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9680 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9681 cond
= bool_to_scalar_condition(ctx
, cond
);
9683 begin_uniform_if_then(ctx
, &ic
, cond
);
9684 visit_cf_list(ctx
, &if_stmt
->then_list
);
9686 begin_uniform_if_else(ctx
, &ic
);
9687 visit_cf_list(ctx
, &if_stmt
->else_list
);
9689 end_uniform_if(ctx
, &ic
);
9690 } else { /* non-uniform condition */
9692 * To maintain a logical and linear CFG without critical edges,
9693 * non-uniform conditionals are represented in the following way*) :
9698 * BB_THEN (logical) BB_THEN (linear)
9700 * BB_INVERT (linear)
9702 * BB_ELSE (logical) BB_ELSE (linear)
9709 * BB_THEN (logical) BB_ELSE (logical)
9713 * *) Exceptions may be due to break and continue statements within loops
9716 begin_divergent_if_then(ctx
, &ic
, cond
);
9717 visit_cf_list(ctx
, &if_stmt
->then_list
);
9719 begin_divergent_if_else(ctx
, &ic
);
9720 visit_cf_list(ctx
, &if_stmt
->else_list
);
9722 end_divergent_if(ctx
, &ic
);
9725 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9728 static bool visit_cf_list(isel_context
*ctx
,
9729 struct exec_list
*list
)
9731 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9732 switch (node
->type
) {
9733 case nir_cf_node_block
:
9734 visit_block(ctx
, nir_cf_node_as_block(node
));
9736 case nir_cf_node_if
:
9737 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9740 case nir_cf_node_loop
:
9741 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9744 unreachable("unimplemented cf list type");
9750 static void create_null_export(isel_context
*ctx
)
9752 /* Some shader stages always need to have exports.
9753 * So when there is none, we need to add a null export.
9756 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9757 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9758 Builder
bld(ctx
->program
, ctx
->block
);
9759 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9760 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9763 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9765 assert(ctx
->stage
== vertex_vs
||
9766 ctx
->stage
== tess_eval_vs
||
9767 ctx
->stage
== gs_copy_vs
||
9768 ctx
->stage
== ngg_vertex_gs
||
9769 ctx
->stage
== ngg_tess_eval_gs
);
9771 int offset
= (ctx
->stage
& sw_tes
)
9772 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9773 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9774 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9775 if (!is_pos
&& !mask
)
9777 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9779 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9780 exp
->enabled_mask
= mask
;
9781 for (unsigned i
= 0; i
< 4; ++i
) {
9782 if (mask
& (1 << i
))
9783 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9785 exp
->operands
[i
] = Operand(v1
);
9787 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9788 * Setting valid_mask=1 prevents it and has no other effect.
9790 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9792 exp
->compressed
= false;
9794 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9796 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9797 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9802 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9804 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9805 exp
->enabled_mask
= 0;
9806 for (unsigned i
= 0; i
< 4; ++i
)
9807 exp
->operands
[i
] = Operand(v1
);
9808 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9809 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9810 exp
->enabled_mask
|= 0x1;
9812 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9813 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9814 exp
->enabled_mask
|= 0x4;
9816 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9817 if (ctx
->options
->chip_class
< GFX9
) {
9818 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9819 exp
->enabled_mask
|= 0x8;
9821 Builder
bld(ctx
->program
, ctx
->block
);
9823 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9824 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9825 if (exp
->operands
[2].isTemp())
9826 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9828 exp
->operands
[2] = Operand(out
);
9829 exp
->enabled_mask
|= 0x4;
9832 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9834 exp
->compressed
= false;
9835 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9836 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9839 static void create_export_phis(isel_context
*ctx
)
9841 /* Used when exports are needed, but the output temps are defined in a preceding block.
9842 * This function will set up phis in order to access the outputs in the next block.
9845 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9846 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9847 ctx
->block
->instructions
.pop_back();
9849 Builder
bld(ctx
->program
, ctx
->block
);
9851 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9852 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9853 for (unsigned i
= 0; i
< 4; ++i
) {
9854 if (!(mask
& (1 << i
)))
9857 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9858 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9859 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9863 bld
.insert(std::move(logical_start
));
9866 static void create_vs_exports(isel_context
*ctx
)
9868 assert(ctx
->stage
== vertex_vs
||
9869 ctx
->stage
== tess_eval_vs
||
9870 ctx
->stage
== gs_copy_vs
||
9871 ctx
->stage
== ngg_vertex_gs
||
9872 ctx
->stage
== ngg_tess_eval_gs
);
9874 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9875 ? &ctx
->program
->info
->tes
.outinfo
9876 : &ctx
->program
->info
->vs
.outinfo
;
9878 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9879 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9880 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9883 if (ctx
->options
->key
.has_multiview_view_index
) {
9884 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9885 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9888 /* the order these position exports are created is important */
9890 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9891 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9892 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9893 exported_pos
= true;
9895 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9896 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9897 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9898 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9900 if (ctx
->export_clip_dists
) {
9901 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9902 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9903 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9904 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9907 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9908 if (i
< VARYING_SLOT_VAR0
&&
9909 i
!= VARYING_SLOT_LAYER
&&
9910 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9911 i
!= VARYING_SLOT_VIEWPORT
)
9914 export_vs_varying(ctx
, i
, false, NULL
);
9918 create_null_export(ctx
);
9921 static bool export_fs_mrt_z(isel_context
*ctx
)
9923 Builder
bld(ctx
->program
, ctx
->block
);
9924 unsigned enabled_channels
= 0;
9928 for (unsigned i
= 0; i
< 4; ++i
) {
9929 values
[i
] = Operand(v1
);
9932 /* Both stencil and sample mask only need 16-bits. */
9933 if (!ctx
->program
->info
->ps
.writes_z
&&
9934 (ctx
->program
->info
->ps
.writes_stencil
||
9935 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9936 compr
= true; /* COMPR flag */
9938 if (ctx
->program
->info
->ps
.writes_stencil
) {
9939 /* Stencil should be in X[23:16]. */
9940 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9941 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9942 enabled_channels
|= 0x3;
9945 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9946 /* SampleMask should be in Y[15:0]. */
9947 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9948 enabled_channels
|= 0xc;
9951 if (ctx
->program
->info
->ps
.writes_z
) {
9952 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9953 enabled_channels
|= 0x1;
9956 if (ctx
->program
->info
->ps
.writes_stencil
) {
9957 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9958 enabled_channels
|= 0x2;
9961 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9962 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9963 enabled_channels
|= 0x4;
9967 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9968 * writemask component.
9970 if (ctx
->options
->chip_class
== GFX6
&&
9971 ctx
->options
->family
!= CHIP_OLAND
&&
9972 ctx
->options
->family
!= CHIP_HAINAN
) {
9973 enabled_channels
|= 0x1;
9976 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9977 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9982 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9984 Builder
bld(ctx
->program
, ctx
->block
);
9985 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9988 for (unsigned i
= 0; i
< 4; ++i
) {
9989 if (write_mask
& (1 << i
)) {
9990 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9992 values
[i
] = Operand(v1
);
9996 unsigned target
, col_format
;
9997 unsigned enabled_channels
= 0;
9998 aco_opcode compr_op
= (aco_opcode
)0;
10000 slot
-= FRAG_RESULT_DATA0
;
10001 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
10002 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
10004 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
10005 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
10006 bool is_16bit
= values
[0].regClass() == v2b
;
10008 switch (col_format
)
10010 case V_028714_SPI_SHADER_ZERO
:
10011 enabled_channels
= 0; /* writemask */
10012 target
= V_008DFC_SQ_EXP_NULL
;
10015 case V_028714_SPI_SHADER_32_R
:
10016 enabled_channels
= 1;
10019 case V_028714_SPI_SHADER_32_GR
:
10020 enabled_channels
= 0x3;
10023 case V_028714_SPI_SHADER_32_AR
:
10024 if (ctx
->options
->chip_class
>= GFX10
) {
10025 /* Special case: on GFX10, the outputs are different for 32_AR */
10026 enabled_channels
= 0x3;
10027 values
[1] = values
[3];
10028 values
[3] = Operand(v1
);
10030 enabled_channels
= 0x9;
10034 case V_028714_SPI_SHADER_FP16_ABGR
:
10035 enabled_channels
= 0x5;
10036 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10038 if (ctx
->options
->chip_class
>= GFX9
) {
10039 /* Pack the FP16 values together instead of converting them to
10040 * FP32 and back to FP16.
10041 * TODO: use p_create_vector and let the compiler optimizes.
10043 compr_op
= aco_opcode::v_pack_b32_f16
;
10045 for (unsigned i
= 0; i
< 4; i
++) {
10046 if ((write_mask
>> i
) & 1)
10047 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10053 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10054 enabled_channels
= 0x5;
10055 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10056 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10058 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10062 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10063 enabled_channels
= 0x5;
10064 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10065 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10067 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10071 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10072 enabled_channels
= 0x5;
10073 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10074 if (is_int8
|| is_int10
) {
10076 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10077 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10079 for (unsigned i
= 0; i
< 4; i
++) {
10080 if ((write_mask
>> i
) & 1) {
10081 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10082 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10086 } else if (is_16bit
) {
10087 for (unsigned i
= 0; i
< 4; i
++) {
10088 if ((write_mask
>> i
) & 1) {
10089 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10090 values
[i
] = Operand(tmp
);
10097 case V_028714_SPI_SHADER_SINT16_ABGR
:
10098 enabled_channels
= 0x5;
10099 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10100 if (is_int8
|| is_int10
) {
10102 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10103 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10104 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10105 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10107 for (unsigned i
= 0; i
< 4; i
++) {
10108 if ((write_mask
>> i
) & 1) {
10109 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10110 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10112 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10113 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10117 } else if (is_16bit
) {
10118 for (unsigned i
= 0; i
< 4; i
++) {
10119 if ((write_mask
>> i
) & 1) {
10120 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10121 values
[i
] = Operand(tmp
);
10127 case V_028714_SPI_SHADER_32_ABGR
:
10128 enabled_channels
= 0xF;
10135 if (target
== V_008DFC_SQ_EXP_NULL
)
10138 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10139 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10141 (col_format
== V_028714_SPI_SHADER_32_R
||
10142 col_format
== V_028714_SPI_SHADER_32_GR
||
10143 col_format
== V_028714_SPI_SHADER_32_AR
||
10144 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10145 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10146 for (int i
= 0; i
< 4; i
++) {
10147 if (!(write_mask
& (1 << i
)))
10150 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10151 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10152 bld
.copy(bld
.def(v1
), Operand(3u)));
10153 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10154 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10158 if ((bool) compr_op
) {
10159 for (int i
= 0; i
< 2; i
++) {
10160 /* check if at least one of the values to be compressed is enabled */
10161 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10163 enabled_channels
|= enabled
<< (i
*2);
10164 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10165 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10166 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10168 values
[i
] = Operand(v1
);
10171 values
[2] = Operand(v1
);
10172 values
[3] = Operand(v1
);
10174 for (int i
= 0; i
< 4; i
++)
10175 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10178 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10179 enabled_channels
, target
, (bool) compr_op
);
10183 static void create_fs_exports(isel_context
*ctx
)
10185 bool exported
= false;
10187 /* Export depth, stencil and sample mask. */
10188 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10189 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10190 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10191 exported
|= export_fs_mrt_z(ctx
);
10193 /* Export all color render targets. */
10194 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10195 if (ctx
->outputs
.mask
[i
])
10196 exported
|= export_fs_mrt_color(ctx
, i
);
10199 create_null_export(ctx
);
10202 static void write_tcs_tess_factors(isel_context
*ctx
)
10204 unsigned outer_comps
;
10205 unsigned inner_comps
;
10207 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10224 Builder
bld(ctx
->program
, ctx
->block
);
10226 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10227 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10228 bld
.sopp(aco_opcode::s_barrier
);
10230 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10231 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10233 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10234 if_context ic_invocation_id_is_zero
;
10235 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10236 bld
.reset(ctx
->block
);
10238 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10240 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10241 unsigned stride
= inner_comps
+ outer_comps
;
10242 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10246 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10248 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10250 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10251 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10252 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10254 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10255 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10257 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10258 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10259 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10260 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10263 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10264 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10265 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10266 unsigned tf_const_offset
= 0;
10268 if (ctx
->program
->chip_class
<= GFX8
) {
10269 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10270 if_context ic_rel_patch_id_is_zero
;
10271 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10272 bld
.reset(ctx
->block
);
10274 /* Store the dynamic HS control word. */
10275 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10276 bld
.mubuf(aco_opcode::buffer_store_dword
,
10277 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10278 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10279 /* disable_wqm */ false, /* glc */ true);
10280 tf_const_offset
+= 4;
10282 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10283 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10284 bld
.reset(ctx
->block
);
10287 assert(stride
== 2 || stride
== 4 || stride
== 6);
10288 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10289 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10291 /* Store to offchip for TES to read - only if TES reads them */
10292 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10293 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10294 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10296 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10297 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10299 if (likely(inner_comps
)) {
10300 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10301 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10305 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10306 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10309 static void emit_stream_output(isel_context
*ctx
,
10310 Temp
const *so_buffers
,
10311 Temp
const *so_write_offset
,
10312 const struct radv_stream_output
*output
)
10314 unsigned num_comps
= util_bitcount(output
->component_mask
);
10315 unsigned writemask
= (1 << num_comps
) - 1;
10316 unsigned loc
= output
->location
;
10317 unsigned buf
= output
->buffer
;
10319 assert(num_comps
&& num_comps
<= 4);
10320 if (!num_comps
|| num_comps
> 4)
10323 unsigned start
= ffs(output
->component_mask
) - 1;
10326 bool all_undef
= true;
10327 assert(ctx
->stage
& hw_vs
);
10328 for (unsigned i
= 0; i
< num_comps
; i
++) {
10329 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10330 all_undef
= all_undef
&& !out
[i
].id();
10335 while (writemask
) {
10337 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10338 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10339 /* GFX6 doesn't support storing vec3, split it. */
10340 writemask
|= 1u << (start
+ 2);
10344 unsigned offset
= output
->offset
+ start
* 4;
10346 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10347 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10348 for (int i
= 0; i
< count
; ++i
)
10349 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10350 vec
->definitions
[0] = Definition(write_data
);
10351 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10356 opcode
= aco_opcode::buffer_store_dword
;
10359 opcode
= aco_opcode::buffer_store_dwordx2
;
10362 opcode
= aco_opcode::buffer_store_dwordx3
;
10365 opcode
= aco_opcode::buffer_store_dwordx4
;
10368 unreachable("Unsupported dword count.");
10371 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10372 store
->operands
[0] = Operand(so_buffers
[buf
]);
10373 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10374 store
->operands
[2] = Operand((uint32_t) 0);
10375 store
->operands
[3] = Operand(write_data
);
10376 if (offset
> 4095) {
10377 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10378 Builder
bld(ctx
->program
, ctx
->block
);
10379 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10381 store
->offset
= offset
;
10383 store
->offen
= true;
10385 store
->dlc
= false;
10387 store
->can_reorder
= true;
10388 ctx
->block
->instructions
.emplace_back(std::move(store
));
10392 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10394 Builder
bld(ctx
->program
, ctx
->block
);
10396 Temp so_buffers
[4];
10397 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10398 for (unsigned i
= 0; i
< 4; i
++) {
10399 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10403 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10404 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10407 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10408 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10410 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10412 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10415 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10417 bld
.reset(ctx
->block
);
10419 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10421 Temp so_write_offset
[4];
10423 for (unsigned i
= 0; i
< 4; i
++) {
10424 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10429 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10430 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10431 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10432 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10434 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10436 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10437 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10438 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10439 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10443 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10444 struct radv_stream_output
*output
=
10445 &ctx
->program
->info
->so
.outputs
[i
];
10446 if (stream
!= output
->stream
)
10449 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10452 begin_divergent_if_else(ctx
, &ic
);
10453 end_divergent_if(ctx
, &ic
);
10456 } /* end namespace */
10458 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10460 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10461 Builder
bld(ctx
->program
, ctx
->block
);
10462 constexpr unsigned hs_idx
= 1u;
10463 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10464 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10465 Operand((8u << 16) | (hs_idx
* 8u)));
10466 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10468 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10470 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10471 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10472 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10473 ls_has_nonzero_hs_threads
);
10474 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10475 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10476 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10477 ls_has_nonzero_hs_threads
);
10478 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10479 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10480 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10481 ls_has_nonzero_hs_threads
);
10483 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10484 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10485 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10488 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10490 /* Split all arguments except for the first (ring_offsets) and the last
10491 * (exec) so that the dead channels don't stay live throughout the program.
10493 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10494 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10495 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10496 startpgm
->definitions
[i
].regClass().size());
10501 void handle_bc_optimize(isel_context
*ctx
)
10503 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10504 Builder
bld(ctx
->program
, ctx
->block
);
10505 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10506 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10507 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10508 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10509 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10510 if (uses_center
&& uses_centroid
) {
10511 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10512 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10514 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10516 for (unsigned i
= 0; i
< 2; i
++) {
10517 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10518 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10519 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10520 persp_centroid
, persp_center
, sel
);
10522 ctx
->persp_centroid
= bld
.tmp(v2
);
10523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10524 Operand(new_coord
[0]), Operand(new_coord
[1]));
10525 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10528 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10530 for (unsigned i
= 0; i
< 2; i
++) {
10531 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10532 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10533 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10534 linear_centroid
, linear_center
, sel
);
10536 ctx
->linear_centroid
= bld
.tmp(v2
);
10537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10538 Operand(new_coord
[0]), Operand(new_coord
[1]));
10539 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10544 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10546 Program
*program
= ctx
->program
;
10548 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10550 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10551 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10552 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10553 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10554 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10556 program
->next_fp_mode
.must_flush_denorms32
=
10557 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10558 program
->next_fp_mode
.must_flush_denorms16_64
=
10559 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10560 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10562 program
->next_fp_mode
.care_about_round32
=
10563 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10565 program
->next_fp_mode
.care_about_round16_64
=
10566 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10567 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10569 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10570 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10571 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10572 program
->next_fp_mode
.denorm16_64
= 0;
10574 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10576 /* preserving fp32 denorms is expensive, so only do it if asked */
10577 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10578 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10580 program
->next_fp_mode
.denorm32
= 0;
10582 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10583 program
->next_fp_mode
.round32
= fp_round_tz
;
10585 program
->next_fp_mode
.round32
= fp_round_ne
;
10587 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10588 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10590 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10592 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10595 void cleanup_cfg(Program
*program
)
10597 /* create linear_succs/logical_succs */
10598 for (Block
& BB
: program
->blocks
) {
10599 for (unsigned idx
: BB
.linear_preds
)
10600 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10601 for (unsigned idx
: BB
.logical_preds
)
10602 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10606 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10608 Builder
bld(ctx
->program
, ctx
->block
);
10610 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10611 Temp count
= i
== 0
10612 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10613 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10614 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10616 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10619 if (ctx
->program
->wave_size
== 64) {
10620 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10621 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10622 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10624 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10625 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10631 bool ngg_early_prim_export(isel_context
*ctx
)
10633 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10637 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10639 Builder
bld(ctx
->program
, ctx
->block
);
10641 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10642 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10644 /* Get the id of the current wave within the threadgroup (workgroup) */
10645 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10646 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10648 /* Execute the following code only on the first wave (wave id 0),
10649 * use the SCC def to tell if the wave id is zero or not.
10651 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10653 begin_uniform_if_then(ctx
, &ic
, cond
);
10654 begin_uniform_if_else(ctx
, &ic
);
10655 bld
.reset(ctx
->block
);
10657 /* Number of vertices output by VS/TES */
10658 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10659 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10660 /* Number of primitives output by VS/TES */
10661 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10662 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10664 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10665 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10666 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10668 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10669 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10671 end_uniform_if(ctx
, &ic
);
10673 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10674 bld
.reset(ctx
->block
);
10675 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10678 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10680 Builder
bld(ctx
->program
, ctx
->block
);
10682 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10683 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10686 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10689 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10690 assert(vtxindex
[i
].id());
10693 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10697 /* The initial edge flag is always false in tess eval shaders. */
10698 if (ctx
->stage
== ngg_vertex_gs
) {
10699 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10700 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10704 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10709 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10711 Builder
bld(ctx
->program
, ctx
->block
);
10712 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10714 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10715 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10716 false /* compressed */, true/* done */, false /* valid mask */);
10719 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10721 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10722 * These must always come before VS exports.
10724 * It is recommended to do these as early as possible. They can be at the beginning when
10725 * there is no SW GS and the shader doesn't write edge flags.
10729 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10730 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10732 Builder
bld(ctx
->program
, ctx
->block
);
10733 constexpr unsigned max_vertices_per_primitive
= 3;
10734 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10736 if (ctx
->stage
== ngg_vertex_gs
) {
10737 /* TODO: optimize for points & lines */
10738 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10739 if (ctx
->shader
->info
.tess
.point_mode
)
10740 num_vertices_per_primitive
= 1;
10741 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10742 num_vertices_per_primitive
= 2;
10744 unreachable("Unsupported NGG shader stage");
10747 Temp vtxindex
[max_vertices_per_primitive
];
10748 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10749 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10750 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10751 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10752 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10753 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10754 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10755 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10757 /* Export primitive data to the index buffer. */
10758 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10760 /* Export primitive ID. */
10761 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10762 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10763 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10764 Temp provoking_vtx_index
= vtxindex
[0];
10765 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10767 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10770 begin_divergent_if_else(ctx
, &ic
);
10771 end_divergent_if(ctx
, &ic
);
10774 void ngg_emit_nogs_output(isel_context
*ctx
)
10776 /* Emits NGG GS output, for stages that don't have SW GS. */
10779 Builder
bld(ctx
->program
, ctx
->block
);
10780 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10782 /* NGG streamout is currently disabled by default. */
10783 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10785 if (late_prim_export
) {
10786 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10787 create_export_phis(ctx
);
10788 /* Do what we need to do in the GS threads. */
10789 ngg_emit_nogs_gsthreads(ctx
);
10791 /* What comes next should be executed on ES threads. */
10792 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10793 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10794 bld
.reset(ctx
->block
);
10797 /* Export VS outputs */
10798 ctx
->block
->kind
|= block_kind_export_end
;
10799 create_vs_exports(ctx
);
10801 /* Export primitive ID */
10802 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10805 if (ctx
->stage
== ngg_vertex_gs
) {
10806 /* Wait for GS threads to store primitive ID in LDS. */
10807 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10808 bld
.sopp(aco_opcode::s_barrier
);
10810 /* Calculate LDS address where the GS threads stored the primitive ID. */
10811 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10812 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10813 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10814 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10815 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10816 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10818 /* Load primitive ID from LDS. */
10819 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10820 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10821 /* TES: Just use the patch ID as the primitive ID. */
10822 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10824 unreachable("unsupported NGG shader stage.");
10827 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10828 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10830 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10833 if (late_prim_export
) {
10834 begin_divergent_if_else(ctx
, &ic
);
10835 end_divergent_if(ctx
, &ic
);
10836 bld
.reset(ctx
->block
);
10840 void select_program(Program
*program
,
10841 unsigned shader_count
,
10842 struct nir_shader
*const *shaders
,
10843 ac_shader_config
* config
,
10844 struct radv_shader_args
*args
)
10846 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10847 if_context ic_merged_wave_info
;
10848 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10850 for (unsigned i
= 0; i
< shader_count
; i
++) {
10851 nir_shader
*nir
= shaders
[i
];
10852 init_context(&ctx
, nir
);
10854 setup_fp_mode(&ctx
, nir
);
10857 /* needs to be after init_context() for FS */
10858 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10859 append_logical_start(ctx
.block
);
10861 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10862 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10864 split_arguments(&ctx
, startpgm
);
10868 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10870 if (ngg_early_prim_export(&ctx
))
10871 ngg_emit_nogs_gsthreads(&ctx
);
10874 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10875 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10876 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10877 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10878 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10879 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10880 ctx
.stage
== tess_eval_geometry_gs
));
10882 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10883 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10884 if (check_merged_wave_info
) {
10885 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10886 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10890 Builder
bld(ctx
.program
, ctx
.block
);
10892 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10893 bld
.sopp(aco_opcode::s_barrier
);
10895 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10896 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10898 } else if (ctx
.stage
== geometry_gs
)
10899 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10901 if (ctx
.stage
== fragment_fs
)
10902 handle_bc_optimize(&ctx
);
10904 visit_cf_list(&ctx
, &func
->body
);
10906 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10907 emit_streamout(&ctx
, 0);
10909 if (ctx
.stage
& hw_vs
) {
10910 create_vs_exports(&ctx
);
10911 ctx
.block
->kind
|= block_kind_export_end
;
10912 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10913 ngg_emit_nogs_output(&ctx
);
10914 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10915 Builder
bld(ctx
.program
, ctx
.block
);
10916 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10917 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10918 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10919 write_tcs_tess_factors(&ctx
);
10922 if (ctx
.stage
== fragment_fs
) {
10923 create_fs_exports(&ctx
);
10924 ctx
.block
->kind
|= block_kind_export_end
;
10927 if (endif_merged_wave_info
) {
10928 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10929 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10932 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10933 ngg_emit_nogs_output(&ctx
);
10935 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10936 /* Outputs of the previous stage are inputs to the next stage */
10937 ctx
.inputs
= ctx
.outputs
;
10938 ctx
.outputs
= shader_io_state();
10942 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10944 append_logical_end(ctx
.block
);
10945 ctx
.block
->kind
|= block_kind_uniform
;
10946 Builder
bld(ctx
.program
, ctx
.block
);
10947 if (ctx
.program
->wb_smem_l1_on_end
)
10948 bld
.smem(aco_opcode::s_dcache_wb
, false);
10949 bld
.sopp(aco_opcode::s_endpgm
);
10951 cleanup_cfg(program
);
10954 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10955 ac_shader_config
* config
,
10956 struct radv_shader_args
*args
)
10958 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10960 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10961 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10962 program
->next_fp_mode
.must_flush_denorms32
= false;
10963 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10964 program
->next_fp_mode
.care_about_round32
= false;
10965 program
->next_fp_mode
.care_about_round16_64
= false;
10966 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10967 program
->next_fp_mode
.denorm32
= 0;
10968 program
->next_fp_mode
.round32
= fp_round_ne
;
10969 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10970 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10972 add_startpgm(&ctx
);
10973 append_logical_start(ctx
.block
);
10975 Builder
bld(ctx
.program
, ctx
.block
);
10977 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10979 Operand
stream_id(0u);
10980 if (args
->shader_info
->so
.num_outputs
)
10981 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10982 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10984 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10986 std::stack
<Block
> endif_blocks
;
10988 for (unsigned stream
= 0; stream
< 4; stream
++) {
10989 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10992 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10993 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10996 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10998 unsigned BB_if_idx
= ctx
.block
->index
;
10999 Block BB_endif
= Block();
11000 if (!stream_id
.isConstant()) {
11002 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
11003 append_logical_end(ctx
.block
);
11004 ctx
.block
->kind
|= block_kind_uniform
;
11005 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
11007 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
11009 ctx
.block
= ctx
.program
->create_and_insert_block();
11010 add_edge(BB_if_idx
, ctx
.block
);
11011 bld
.reset(ctx
.block
);
11012 append_logical_start(ctx
.block
);
11015 unsigned offset
= 0;
11016 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
11017 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
11020 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
11021 unsigned length
= util_last_bit(output_usage_mask
);
11022 for (unsigned j
= 0; j
< length
; ++j
) {
11023 if (!(output_usage_mask
& (1 << j
)))
11026 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
11027 Temp voffset
= vtx_offset
;
11028 if (const_offset
>= 4096u) {
11029 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
11030 const_offset
%= 4096u;
11033 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
11034 mubuf
->definitions
[0] = bld
.def(v1
);
11035 mubuf
->operands
[0] = Operand(gsvs_ring
);
11036 mubuf
->operands
[1] = Operand(voffset
);
11037 mubuf
->operands
[2] = Operand(0u);
11038 mubuf
->offen
= true;
11039 mubuf
->offset
= const_offset
;
11042 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
11043 mubuf
->barrier
= barrier_none
;
11044 mubuf
->can_reorder
= true;
11046 ctx
.outputs
.mask
[i
] |= 1 << j
;
11047 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
11049 bld
.insert(std::move(mubuf
));
11055 if (args
->shader_info
->so
.num_outputs
) {
11056 emit_streamout(&ctx
, stream
);
11057 bld
.reset(ctx
.block
);
11061 create_vs_exports(&ctx
);
11062 ctx
.block
->kind
|= block_kind_export_end
;
11065 if (!stream_id
.isConstant()) {
11066 append_logical_end(ctx
.block
);
11068 /* branch from then block to endif block */
11069 bld
.branch(aco_opcode::p_branch
);
11070 add_edge(ctx
.block
->index
, &BB_endif
);
11071 ctx
.block
->kind
|= block_kind_uniform
;
11073 /* emit else block */
11074 ctx
.block
= ctx
.program
->create_and_insert_block();
11075 add_edge(BB_if_idx
, ctx
.block
);
11076 bld
.reset(ctx
.block
);
11077 append_logical_start(ctx
.block
);
11079 endif_blocks
.push(std::move(BB_endif
));
11083 while (!endif_blocks
.empty()) {
11084 Block BB_endif
= std::move(endif_blocks
.top());
11085 endif_blocks
.pop();
11087 Block
*BB_else
= ctx
.block
;
11089 append_logical_end(BB_else
);
11090 /* branch from else block to endif block */
11091 bld
.branch(aco_opcode::p_branch
);
11092 add_edge(BB_else
->index
, &BB_endif
);
11093 BB_else
->kind
|= block_kind_uniform
;
11095 /** emit endif merge block */
11096 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11097 bld
.reset(ctx
.block
);
11098 append_logical_start(ctx
.block
);
11101 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11103 append_logical_end(ctx
.block
);
11104 ctx
.block
->kind
|= block_kind_uniform
;
11105 bld
.sopp(aco_opcode::s_endpgm
);
11107 cleanup_cfg(program
);