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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
564 } else if (src0
.type() == RegType::vgpr
&&
565 op
!= aco_opcode::v_madmk_f32
&&
566 op
!= aco_opcode::v_madak_f32
&&
567 op
!= aco_opcode::v_madmk_f16
&&
568 op
!= aco_opcode::v_madak_f16
) {
569 /* If the instruction is not commutative, we emit a VOP3A instruction */
570 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
573 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f32
:
630 op
= aco_opcode::v_cmp_gt_f32
;
632 case aco_opcode::v_cmp_ge_f32
:
633 op
= aco_opcode::v_cmp_le_f32
;
635 case aco_opcode::v_cmp_lt_i32
:
636 op
= aco_opcode::v_cmp_gt_i32
;
638 case aco_opcode::v_cmp_ge_i32
:
639 op
= aco_opcode::v_cmp_le_i32
;
641 case aco_opcode::v_cmp_lt_u32
:
642 op
= aco_opcode::v_cmp_gt_u32
;
644 case aco_opcode::v_cmp_ge_u32
:
645 op
= aco_opcode::v_cmp_le_u32
;
647 case aco_opcode::v_cmp_lt_f64
:
648 op
= aco_opcode::v_cmp_gt_f64
;
650 case aco_opcode::v_cmp_ge_f64
:
651 op
= aco_opcode::v_cmp_le_f64
;
653 case aco_opcode::v_cmp_lt_i64
:
654 op
= aco_opcode::v_cmp_gt_i64
;
656 case aco_opcode::v_cmp_ge_i64
:
657 op
= aco_opcode::v_cmp_le_i64
;
659 case aco_opcode::v_cmp_lt_u64
:
660 op
= aco_opcode::v_cmp_gt_u64
;
662 case aco_opcode::v_cmp_ge_u64
:
663 op
= aco_opcode::v_cmp_le_u64
;
665 default: /* eq and ne are commutative */
672 src1
= as_vgpr(ctx
, src1
);
676 Builder
bld(ctx
->program
, ctx
->block
);
677 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
680 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
682 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
683 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
684 Builder
bld(ctx
->program
, ctx
->block
);
686 assert(dst
.regClass() == bld
.lm
);
687 assert(src0
.type() == RegType::sgpr
);
688 assert(src1
.type() == RegType::sgpr
);
689 assert(src0
.regClass() == src1
.regClass());
691 /* Emit the SALU comparison instruction */
692 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
693 /* Turn the result into a per-lane bool */
694 bool_to_vector_condition(ctx
, cmp
, dst
);
697 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
698 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
700 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
701 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
702 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
703 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
705 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
706 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
707 aco_opcode op
= use_valu
? v_op
: s_op
;
708 assert(op
!= aco_opcode::num_opcodes
);
709 assert(dst
.regClass() == ctx
->program
->lane_mask
);
712 emit_vopc_instruction(ctx
, instr
, op
, dst
);
714 emit_sopc_instruction(ctx
, instr
, op
, dst
);
717 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
719 Builder
bld(ctx
->program
, ctx
->block
);
720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
721 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
723 assert(dst
.regClass() == bld
.lm
);
724 assert(src0
.regClass() == bld
.lm
);
725 assert(src1
.regClass() == bld
.lm
);
727 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
730 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
732 Builder
bld(ctx
->program
, ctx
->block
);
733 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
734 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
735 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
737 assert(cond
.regClass() == bld
.lm
);
739 if (dst
.type() == RegType::vgpr
) {
740 aco_ptr
<Instruction
> bcsel
;
741 if (dst
.size() == 1) {
742 then
= as_vgpr(ctx
, then
);
743 els
= as_vgpr(ctx
, els
);
745 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
746 } else if (dst
.size() == 2) {
747 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
748 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
749 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
750 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
752 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
753 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
755 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
758 nir_print_instr(&instr
->instr
, stderr
);
759 fprintf(stderr
, "\n");
764 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
765 assert(dst
.regClass() == bld
.lm
);
766 assert(then
.regClass() == bld
.lm
);
767 assert(els
.regClass() == bld
.lm
);
770 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
771 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
772 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
773 assert(dst
.size() == then
.size());
774 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
775 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
777 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
778 nir_print_instr(&instr
->instr
, stderr
);
779 fprintf(stderr
, "\n");
784 /* divergent boolean bcsel
785 * this implements bcsel on bools: dst = s0 ? s1 : s2
786 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
787 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
789 if (cond
.id() != then
.id())
790 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
792 if (cond
.id() == els
.id())
793 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
795 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
796 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
799 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
800 aco_opcode op
, uint32_t undo
)
802 /* multiply by 16777216 to handle denormals */
803 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
804 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
805 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
806 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
807 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
809 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
811 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
814 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
816 if (ctx
->block
->fp_mode
.denorm32
== 0) {
817 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
821 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
824 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
826 if (ctx
->block
->fp_mode
.denorm32
== 0) {
827 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
831 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
834 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
836 if (ctx
->block
->fp_mode
.denorm32
== 0) {
837 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
841 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
844 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
846 if (ctx
->block
->fp_mode
.denorm32
== 0) {
847 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
851 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
854 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
856 if (ctx
->options
->chip_class
>= GFX7
)
857 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
859 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
860 /* TODO: create more efficient code! */
861 if (val
.type() == RegType::sgpr
)
862 val
= as_vgpr(ctx
, val
);
864 /* Split the input value. */
865 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
866 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
868 /* Extract the exponent and compute the unbiased value. */
869 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
871 /* Extract the fractional part. */
872 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
873 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
875 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
878 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
879 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
880 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
881 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
882 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
884 /* Get the sign bit. */
885 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
887 /* Decide the operation to apply depending on the unbiased exponent. */
888 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
889 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
890 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
891 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
892 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
893 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
895 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
898 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
900 if (ctx
->options
->chip_class
>= GFX7
)
901 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
903 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
904 Temp src0
= as_vgpr(ctx
, val
);
906 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
907 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
909 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
910 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
911 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
913 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
914 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
915 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
916 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
918 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
919 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
921 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
923 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
924 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
926 return add
->definitions
[0].getTemp();
929 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
931 if (!instr
->dest
.dest
.is_ssa
) {
932 fprintf(stderr
, "nir alu dst not in ssa: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
937 Builder
bld(ctx
->program
, ctx
->block
);
938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
943 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
944 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
945 for (unsigned i
= 0; i
< num
; ++i
)
946 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
948 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
949 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
950 for (unsigned i
= 0; i
< num
; ++i
)
951 vec
->operands
[i
] = Operand
{elems
[i
]};
952 vec
->definitions
[0] = Definition(dst
);
953 ctx
->block
->instructions
.emplace_back(std::move(vec
));
954 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
956 // TODO: that is a bit suboptimal..
957 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
958 for (unsigned i
= 0; i
< num
- 1; ++i
)
959 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
960 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
961 for (unsigned i
= 0; i
< num
; ++i
) {
962 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
964 elems
[bit
/ 32] = elems
[i
];
966 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
967 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
968 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
972 bld
.copy(Definition(dst
), elems
[0]);
974 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
979 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
980 aco_ptr
<Instruction
> mov
;
981 if (dst
.type() == RegType::sgpr
) {
982 if (src
.type() == RegType::vgpr
)
983 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
984 else if (src
.regClass() == s1
)
985 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
986 else if (src
.regClass() == s2
)
987 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
989 unreachable("wrong src register class for nir_op_imov");
990 } else if (dst
.regClass() == v1
) {
991 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
992 } else if (dst
.regClass() == v2
) {
993 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
995 nir_print_instr(&instr
->instr
, stderr
);
996 unreachable("Should have been lowered to scalar.");
1001 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1002 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1003 assert(src
.regClass() == bld
.lm
);
1004 assert(dst
.regClass() == bld
.lm
);
1005 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1006 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1007 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1008 } else if (dst
.regClass() == v1
) {
1009 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1010 } else if (dst
.type() == RegType::sgpr
) {
1011 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1012 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1021 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1022 if (dst
.regClass() == v1
) {
1023 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1024 } else if (dst
.regClass() == s1
) {
1025 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1026 } else if (dst
.size() == 2) {
1027 Temp src0
= bld
.tmp(dst
.type(), 1);
1028 Temp src1
= bld
.tmp(dst
.type(), 1);
1029 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1031 if (dst
.regClass() == s2
) {
1032 Temp carry
= bld
.tmp(s1
);
1033 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1034 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1035 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1037 Temp lower
= bld
.tmp(v1
);
1038 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1039 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1040 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1054 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1056 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1057 nir_print_instr(&instr
->instr
, stderr
);
1058 fprintf(stderr
, "\n");
1062 case nir_op_isign
: {
1063 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1064 if (dst
.regClass() == s1
) {
1065 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1066 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
1067 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
1068 } else if (dst
.regClass() == s2
) {
1069 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1071 if (ctx
->program
->chip_class
>= GFX8
)
1072 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1074 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1075 /* SCC gets zero-extended to 64 bit */
1076 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1077 } else if (dst
.regClass() == v1
) {
1078 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1079 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1080 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
1081 } else if (dst
.regClass() == v2
) {
1082 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1083 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1084 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1085 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1086 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1087 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1089 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1090 nir_print_instr(&instr
->instr
, stderr
);
1091 fprintf(stderr
, "\n");
1096 if (dst
.regClass() == v1
) {
1097 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1098 } else if (dst
.regClass() == s1
) {
1099 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1101 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1102 nir_print_instr(&instr
->instr
, stderr
);
1103 fprintf(stderr
, "\n");
1108 if (dst
.regClass() == v1
) {
1109 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1110 } else if (dst
.regClass() == s1
) {
1111 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1113 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1114 nir_print_instr(&instr
->instr
, stderr
);
1115 fprintf(stderr
, "\n");
1120 if (dst
.regClass() == v1
) {
1121 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1122 } else if (dst
.regClass() == s1
) {
1123 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1125 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1126 nir_print_instr(&instr
->instr
, stderr
);
1127 fprintf(stderr
, "\n");
1132 if (dst
.regClass() == v1
) {
1133 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1134 } else if (dst
.regClass() == s1
) {
1135 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1144 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1145 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1146 } else if (dst
.regClass() == v1
) {
1147 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1148 } else if (dst
.regClass() == s1
) {
1149 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1150 } else if (dst
.regClass() == s2
) {
1151 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1153 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1154 nir_print_instr(&instr
->instr
, stderr
);
1155 fprintf(stderr
, "\n");
1160 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1161 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1162 } else if (dst
.regClass() == v1
) {
1163 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1164 } else if (dst
.regClass() == s1
) {
1165 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1166 } else if (dst
.regClass() == s2
) {
1167 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1169 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1170 nir_print_instr(&instr
->instr
, stderr
);
1171 fprintf(stderr
, "\n");
1176 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1177 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1178 } else if (dst
.regClass() == v1
) {
1179 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1180 } else if (dst
.regClass() == s1
) {
1181 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1182 } else if (dst
.regClass() == s2
) {
1183 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1185 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1186 nir_print_instr(&instr
->instr
, stderr
);
1187 fprintf(stderr
, "\n");
1192 if (dst
.regClass() == v1
) {
1193 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1194 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1195 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1196 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1197 } else if (dst
.regClass() == v2
) {
1198 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1199 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1200 } else if (dst
.regClass() == s2
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1202 } else if (dst
.regClass() == s1
) {
1203 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1205 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1206 nir_print_instr(&instr
->instr
, stderr
);
1207 fprintf(stderr
, "\n");
1212 if (dst
.regClass() == v1
) {
1213 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1214 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1215 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1216 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1217 } else if (dst
.regClass() == v2
) {
1218 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1219 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1220 } else if (dst
.regClass() == s1
) {
1221 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1222 } else if (dst
.regClass() == s2
) {
1223 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1225 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1226 nir_print_instr(&instr
->instr
, stderr
);
1227 fprintf(stderr
, "\n");
1232 if (dst
.regClass() == v1
) {
1233 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1234 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1235 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1236 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1237 } else if (dst
.regClass() == v2
) {
1238 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1239 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1240 } else if (dst
.regClass() == s1
) {
1241 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1242 } else if (dst
.regClass() == s2
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1245 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1246 nir_print_instr(&instr
->instr
, stderr
);
1247 fprintf(stderr
, "\n");
1251 case nir_op_find_lsb
: {
1252 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1253 if (src
.regClass() == s1
) {
1254 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1255 } else if (src
.regClass() == v1
) {
1256 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1257 } else if (src
.regClass() == s2
) {
1258 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_ufind_msb
:
1267 case nir_op_ifind_msb
: {
1268 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1269 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1270 aco_opcode op
= src
.regClass() == s2
?
1271 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1272 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1273 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1275 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1276 Operand(src
.size() * 32u - 1u), msb_rev
);
1277 Temp msb
= sub
.def(0).getTemp();
1278 Temp carry
= sub
.def(1).getTemp();
1280 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1281 } else if (src
.regClass() == v1
) {
1282 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1283 Temp msb_rev
= bld
.tmp(v1
);
1284 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1285 Temp msb
= bld
.tmp(v1
);
1286 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1287 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1295 case nir_op_bitfield_reverse
: {
1296 if (dst
.regClass() == s1
) {
1297 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1298 } else if (dst
.regClass() == v1
) {
1299 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1301 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1302 nir_print_instr(&instr
->instr
, stderr
);
1303 fprintf(stderr
, "\n");
1308 if (dst
.regClass() == s1
) {
1309 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1313 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1314 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1315 if (dst
.regClass() == v1
) {
1316 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1320 assert(src0
.size() == 2 && src1
.size() == 2);
1321 Temp src00
= bld
.tmp(src0
.type(), 1);
1322 Temp src01
= bld
.tmp(dst
.type(), 1);
1323 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1324 Temp src10
= bld
.tmp(src1
.type(), 1);
1325 Temp src11
= bld
.tmp(dst
.type(), 1);
1326 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1328 if (dst
.regClass() == s2
) {
1329 Temp carry
= bld
.tmp(s1
);
1330 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1331 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1332 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1333 } else if (dst
.regClass() == v2
) {
1334 Temp dst0
= bld
.tmp(v1
);
1335 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1336 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1337 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1340 nir_print_instr(&instr
->instr
, stderr
);
1341 fprintf(stderr
, "\n");
1345 case nir_op_uadd_sat
: {
1346 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1347 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1348 if (dst
.regClass() == s1
) {
1349 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1350 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1352 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1353 } else if (dst
.regClass() == v1
) {
1354 if (ctx
->options
->chip_class
>= GFX9
) {
1355 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1356 add
->operands
[0] = Operand(src0
);
1357 add
->operands
[1] = Operand(src1
);
1358 add
->definitions
[0] = Definition(dst
);
1360 ctx
->block
->instructions
.emplace_back(std::move(add
));
1362 if (src1
.regClass() != v1
)
1363 std::swap(src0
, src1
);
1364 assert(src1
.regClass() == v1
);
1365 Temp tmp
= bld
.tmp(v1
);
1366 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1367 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1370 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1371 nir_print_instr(&instr
->instr
, stderr
);
1372 fprintf(stderr
, "\n");
1376 case nir_op_uadd_carry
: {
1377 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1378 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1379 if (dst
.regClass() == s1
) {
1380 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1383 if (dst
.regClass() == v1
) {
1384 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1385 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1389 Temp src00
= bld
.tmp(src0
.type(), 1);
1390 Temp src01
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1392 Temp src10
= bld
.tmp(src1
.type(), 1);
1393 Temp src11
= bld
.tmp(dst
.type(), 1);
1394 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1395 if (dst
.regClass() == s2
) {
1396 Temp carry
= bld
.tmp(s1
);
1397 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1398 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1399 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1400 } else if (dst
.regClass() == v2
) {
1401 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1402 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1403 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1406 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1407 nir_print_instr(&instr
->instr
, stderr
);
1408 fprintf(stderr
, "\n");
1413 if (dst
.regClass() == s1
) {
1414 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1418 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1419 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1420 if (dst
.regClass() == v1
) {
1421 bld
.vsub32(Definition(dst
), src0
, src1
);
1425 Temp src00
= bld
.tmp(src0
.type(), 1);
1426 Temp src01
= bld
.tmp(dst
.type(), 1);
1427 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1428 Temp src10
= bld
.tmp(src1
.type(), 1);
1429 Temp src11
= bld
.tmp(dst
.type(), 1);
1430 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1431 if (dst
.regClass() == s2
) {
1432 Temp carry
= bld
.tmp(s1
);
1433 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1434 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1435 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1436 } else if (dst
.regClass() == v2
) {
1437 Temp lower
= bld
.tmp(v1
);
1438 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1439 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1442 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1443 nir_print_instr(&instr
->instr
, stderr
);
1444 fprintf(stderr
, "\n");
1448 case nir_op_usub_borrow
: {
1449 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1450 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1451 if (dst
.regClass() == s1
) {
1452 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1454 } else if (dst
.regClass() == v1
) {
1455 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1456 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1460 Temp src00
= bld
.tmp(src0
.type(), 1);
1461 Temp src01
= bld
.tmp(dst
.type(), 1);
1462 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1463 Temp src10
= bld
.tmp(src1
.type(), 1);
1464 Temp src11
= bld
.tmp(dst
.type(), 1);
1465 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1466 if (dst
.regClass() == s2
) {
1467 Temp borrow
= bld
.tmp(s1
);
1468 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1469 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1470 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1471 } else if (dst
.regClass() == v2
) {
1472 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1473 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1474 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1475 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1477 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1478 nir_print_instr(&instr
->instr
, stderr
);
1479 fprintf(stderr
, "\n");
1484 if (dst
.regClass() == v1
) {
1485 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1486 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1487 } else if (dst
.regClass() == s1
) {
1488 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1491 nir_print_instr(&instr
->instr
, stderr
);
1492 fprintf(stderr
, "\n");
1496 case nir_op_umul_high
: {
1497 if (dst
.regClass() == v1
) {
1498 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1499 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1500 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1501 } else if (dst
.regClass() == s1
) {
1502 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1503 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1504 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1506 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1507 nir_print_instr(&instr
->instr
, stderr
);
1508 fprintf(stderr
, "\n");
1512 case nir_op_imul_high
: {
1513 if (dst
.regClass() == v1
) {
1514 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1515 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1516 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1517 } else if (dst
.regClass() == s1
) {
1518 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1519 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1520 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1522 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1523 nir_print_instr(&instr
->instr
, stderr
);
1524 fprintf(stderr
, "\n");
1529 if (dst
.size() == 1) {
1530 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1531 } else if (dst
.size() == 2) {
1532 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1533 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1536 nir_print_instr(&instr
->instr
, stderr
);
1537 fprintf(stderr
, "\n");
1542 if (dst
.size() == 1) {
1543 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1544 } else if (dst
.size() == 2) {
1545 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1546 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1548 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1549 nir_print_instr(&instr
->instr
, stderr
);
1550 fprintf(stderr
, "\n");
1555 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1556 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1557 if (dst
.size() == 1) {
1558 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1559 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1561 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1562 } else if (dst
.size() == 2) {
1563 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]),
1565 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1566 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1569 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1570 nir_print_instr(&instr
->instr
, stderr
);
1571 fprintf(stderr
, "\n");
1576 if (dst
.size() == 1) {
1577 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1578 } else if (dst
.size() == 2) {
1579 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
),
1581 get_alu_src(ctx
, instr
->src
[0]),
1582 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1583 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1585 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1586 get_alu_src(ctx
, instr
->src
[0]),
1587 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1597 if (dst
.size() == 1) {
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1599 } else if (dst
.size() == 2) {
1600 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1601 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
),
1602 get_alu_src(ctx
, instr
->src
[0]),
1603 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1604 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1606 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1607 get_alu_src(ctx
, instr
->src
[0]),
1608 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1611 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1612 nir_print_instr(&instr
->instr
, stderr
);
1613 fprintf(stderr
, "\n");
1617 case nir_op_fmax3
: {
1618 if (dst
.size() == 1) {
1619 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1621 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1622 nir_print_instr(&instr
->instr
, stderr
);
1623 fprintf(stderr
, "\n");
1627 case nir_op_fmin3
: {
1628 if (dst
.size() == 1) {
1629 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1631 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1632 nir_print_instr(&instr
->instr
, stderr
);
1633 fprintf(stderr
, "\n");
1637 case nir_op_fmed3
: {
1638 if (dst
.size() == 1) {
1639 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1641 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1642 nir_print_instr(&instr
->instr
, stderr
);
1643 fprintf(stderr
, "\n");
1647 case nir_op_umax3
: {
1648 if (dst
.size() == 1) {
1649 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1652 nir_print_instr(&instr
->instr
, stderr
);
1653 fprintf(stderr
, "\n");
1657 case nir_op_umin3
: {
1658 if (dst
.size() == 1) {
1659 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1661 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1662 nir_print_instr(&instr
->instr
, stderr
);
1663 fprintf(stderr
, "\n");
1667 case nir_op_umed3
: {
1668 if (dst
.size() == 1) {
1669 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1671 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1672 nir_print_instr(&instr
->instr
, stderr
);
1673 fprintf(stderr
, "\n");
1677 case nir_op_imax3
: {
1678 if (dst
.size() == 1) {
1679 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1681 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1682 nir_print_instr(&instr
->instr
, stderr
);
1683 fprintf(stderr
, "\n");
1687 case nir_op_imin3
: {
1688 if (dst
.size() == 1) {
1689 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1691 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1692 nir_print_instr(&instr
->instr
, stderr
);
1693 fprintf(stderr
, "\n");
1697 case nir_op_imed3
: {
1698 if (dst
.size() == 1) {
1699 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_cube_face_coord
: {
1708 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1709 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1710 emit_extract_vector(ctx
, in
, 1, v1
),
1711 emit_extract_vector(ctx
, in
, 2, v1
) };
1712 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1713 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1714 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1715 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1716 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1717 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1718 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1721 case nir_op_cube_face_index
: {
1722 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1723 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1724 emit_extract_vector(ctx
, in
, 1, v1
),
1725 emit_extract_vector(ctx
, in
, 2, v1
) };
1726 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1729 case nir_op_bcsel
: {
1730 emit_bcsel(ctx
, instr
, dst
);
1734 if (dst
.size() == 1) {
1735 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1736 } else if (dst
.size() == 2) {
1737 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1739 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1740 nir_print_instr(&instr
->instr
, stderr
);
1741 fprintf(stderr
, "\n");
1746 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1747 if (dst
.size() == 1) {
1748 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1749 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1750 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1751 } else if (dst
.size() == 2) {
1752 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1753 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1754 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1755 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1756 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1757 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1759 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1760 nir_print_instr(&instr
->instr
, stderr
);
1761 fprintf(stderr
, "\n");
1766 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1767 if (dst
.size() == 1) {
1768 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1769 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1770 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1771 } else if (dst
.size() == 2) {
1772 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1773 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1774 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1775 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1776 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1777 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1779 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1780 nir_print_instr(&instr
->instr
, stderr
);
1781 fprintf(stderr
, "\n");
1786 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1787 if (dst
.size() == 1) {
1788 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1789 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1790 // TODO: confirm that this holds under any circumstances
1791 } else if (dst
.size() == 2) {
1792 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1793 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1796 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1797 nir_print_instr(&instr
->instr
, stderr
);
1798 fprintf(stderr
, "\n");
1802 case nir_op_flog2
: {
1803 if (dst
.size() == 1) {
1804 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1806 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1807 nir_print_instr(&instr
->instr
, stderr
);
1808 fprintf(stderr
, "\n");
1813 if (dst
.size() == 1) {
1814 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1815 } else if (dst
.size() == 2) {
1816 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1818 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1819 nir_print_instr(&instr
->instr
, stderr
);
1820 fprintf(stderr
, "\n");
1824 case nir_op_fexp2
: {
1825 if (dst
.size() == 1) {
1826 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1828 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1829 nir_print_instr(&instr
->instr
, stderr
);
1830 fprintf(stderr
, "\n");
1834 case nir_op_fsqrt
: {
1835 if (dst
.size() == 1) {
1836 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1837 } else if (dst
.size() == 2) {
1838 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1840 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1841 nir_print_instr(&instr
->instr
, stderr
);
1842 fprintf(stderr
, "\n");
1846 case nir_op_ffract
: {
1847 if (dst
.size() == 1) {
1848 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1849 } else if (dst
.size() == 2) {
1850 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1853 nir_print_instr(&instr
->instr
, stderr
);
1854 fprintf(stderr
, "\n");
1858 case nir_op_ffloor
: {
1859 if (dst
.size() == 1) {
1860 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1861 } else if (dst
.size() == 2) {
1862 emit_floor_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1864 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1865 nir_print_instr(&instr
->instr
, stderr
);
1866 fprintf(stderr
, "\n");
1870 case nir_op_fceil
: {
1871 if (dst
.size() == 1) {
1872 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1873 } else if (dst
.size() == 2) {
1874 if (ctx
->options
->chip_class
>= GFX7
) {
1875 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1877 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1878 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1880 /* trunc = trunc(src0)
1881 * if (src0 > 0.0 && src0 != trunc)
1884 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1885 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1886 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1887 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1888 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1889 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1890 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1893 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1894 nir_print_instr(&instr
->instr
, stderr
);
1895 fprintf(stderr
, "\n");
1899 case nir_op_ftrunc
: {
1900 if (dst
.size() == 1) {
1901 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1902 } else if (dst
.size() == 2) {
1903 emit_trunc_f64(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1905 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1906 nir_print_instr(&instr
->instr
, stderr
);
1907 fprintf(stderr
, "\n");
1911 case nir_op_fround_even
: {
1912 if (dst
.size() == 1) {
1913 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1914 } else if (dst
.size() == 2) {
1915 if (ctx
->options
->chip_class
>= GFX7
) {
1916 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1918 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1919 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1921 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
1922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
1924 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
1925 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
1926 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1927 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
1928 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
1929 tmp
= sub
->definitions
[0].getTemp();
1931 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
1932 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
1933 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
1934 Temp cond
= vop3
->definitions
[0].getTemp();
1936 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
1937 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
1938 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
1939 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
1941 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1944 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1945 nir_print_instr(&instr
->instr
, stderr
);
1946 fprintf(stderr
, "\n");
1952 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1953 aco_ptr
<Instruction
> norm
;
1954 if (dst
.size() == 1) {
1955 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
1956 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, as_vgpr(ctx
, src
));
1958 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1959 if (ctx
->options
->chip_class
< GFX9
)
1960 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1962 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1963 bld
.vop1(opcode
, Definition(dst
), tmp
);
1965 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1966 nir_print_instr(&instr
->instr
, stderr
);
1967 fprintf(stderr
, "\n");
1971 case nir_op_ldexp
: {
1972 if (dst
.size() == 1) {
1973 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1974 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1975 get_alu_src(ctx
, instr
->src
[1]));
1976 } else if (dst
.size() == 2) {
1977 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1978 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1979 get_alu_src(ctx
, instr
->src
[1]));
1981 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1982 nir_print_instr(&instr
->instr
, stderr
);
1983 fprintf(stderr
, "\n");
1987 case nir_op_frexp_sig
: {
1988 if (dst
.size() == 1) {
1989 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1990 get_alu_src(ctx
, instr
->src
[0]));
1991 } else if (dst
.size() == 2) {
1992 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1993 get_alu_src(ctx
, instr
->src
[0]));
1995 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1996 nir_print_instr(&instr
->instr
, stderr
);
1997 fprintf(stderr
, "\n");
2001 case nir_op_frexp_exp
: {
2002 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2003 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
2004 get_alu_src(ctx
, instr
->src
[0]));
2005 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2006 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
2007 get_alu_src(ctx
, instr
->src
[0]));
2009 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2010 nir_print_instr(&instr
->instr
, stderr
);
2011 fprintf(stderr
, "\n");
2015 case nir_op_fsign
: {
2016 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2017 if (dst
.size() == 1) {
2018 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2019 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2020 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2021 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2022 } else if (dst
.size() == 2) {
2023 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2024 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2025 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2027 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2028 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2029 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2031 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2033 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2034 nir_print_instr(&instr
->instr
, stderr
);
2035 fprintf(stderr
, "\n");
2040 case nir_op_f2f16_rtne
: {
2041 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2042 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2043 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2044 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2045 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2048 case nir_op_f2f16_rtz
: {
2049 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2050 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2051 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2052 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2053 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2056 case nir_op_f2f32
: {
2057 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2058 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2059 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2060 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2062 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2063 nir_print_instr(&instr
->instr
, stderr
);
2064 fprintf(stderr
, "\n");
2068 case nir_op_f2f64
: {
2069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2070 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2071 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2072 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2075 case nir_op_i2f32
: {
2076 assert(dst
.size() == 1);
2077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
2080 case nir_op_i2f64
: {
2081 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2082 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
2083 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2084 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2085 RegClass rc
= RegClass(src
.type(), 1);
2086 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2088 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2089 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2090 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2091 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2094 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2095 nir_print_instr(&instr
->instr
, stderr
);
2096 fprintf(stderr
, "\n");
2100 case nir_op_u2f32
: {
2101 assert(dst
.size() == 1);
2102 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
2105 case nir_op_u2f64
: {
2106 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2107 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
2108 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2109 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2110 RegClass rc
= RegClass(src
.type(), 1);
2111 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2112 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2113 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2114 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2115 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2116 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2118 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2119 nir_print_instr(&instr
->instr
, stderr
);
2120 fprintf(stderr
, "\n");
2124 case nir_op_f2i16
: {
2125 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2126 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2127 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2128 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2129 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2131 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2133 if (dst
.type() == RegType::vgpr
)
2134 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2136 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2139 case nir_op_f2u16
: {
2140 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2141 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2142 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2143 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2144 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2146 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2148 if (dst
.type() == RegType::vgpr
)
2149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2151 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2154 case nir_op_f2i32
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2157 if (dst
.type() == RegType::vgpr
)
2158 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2160 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2161 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2163 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2164 if (dst
.type() == RegType::vgpr
)
2165 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2167 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2168 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2171 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2172 nir_print_instr(&instr
->instr
, stderr
);
2173 fprintf(stderr
, "\n");
2177 case nir_op_f2u32
: {
2178 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2179 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2180 if (dst
.type() == RegType::vgpr
)
2181 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2183 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2184 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2186 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2187 if (dst
.type() == RegType::vgpr
)
2188 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2190 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2191 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2194 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2195 nir_print_instr(&instr
->instr
, stderr
);
2196 fprintf(stderr
, "\n");
2200 case nir_op_f2i64
: {
2201 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2202 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2203 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2204 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2205 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2206 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2207 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2208 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2209 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2210 Temp new_exponent
= bld
.tmp(v1
);
2211 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2212 if (ctx
->program
->chip_class
>= GFX8
)
2213 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2215 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2216 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2217 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2218 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2219 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2220 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2221 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2222 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2223 Temp new_lower
= bld
.tmp(v1
);
2224 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2225 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2226 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2228 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2229 if (src
.type() == RegType::vgpr
)
2230 src
= bld
.as_uniform(src
);
2231 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2232 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2233 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2234 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2235 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2236 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2237 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2238 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2239 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2240 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2241 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2242 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2243 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2244 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2245 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2246 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2247 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2248 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2249 Temp borrow
= bld
.tmp(s1
);
2250 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2251 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2252 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2254 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2255 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2256 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2257 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2258 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2259 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2260 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2261 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2262 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2263 if (dst
.type() == RegType::sgpr
) {
2264 lower
= bld
.as_uniform(lower
);
2265 upper
= bld
.as_uniform(upper
);
2267 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2271 nir_print_instr(&instr
->instr
, stderr
);
2272 fprintf(stderr
, "\n");
2276 case nir_op_f2u64
: {
2277 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2278 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
2279 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2280 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2281 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2282 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2283 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2284 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2285 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2286 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2287 Temp new_exponent
= bld
.tmp(v1
);
2288 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2289 if (ctx
->program
->chip_class
>= GFX8
)
2290 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2292 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2293 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2294 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2295 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2296 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2297 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2298 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2299 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2301 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
2302 if (src
.type() == RegType::vgpr
)
2303 src
= bld
.as_uniform(src
);
2304 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2305 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2306 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2307 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2308 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2309 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2310 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2311 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2312 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2313 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2314 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2315 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2316 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2317 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2318 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2319 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2320 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2321 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2323 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2324 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2325 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2326 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2327 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2328 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2329 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2330 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2331 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2332 if (dst
.type() == RegType::sgpr
) {
2333 lower
= bld
.as_uniform(lower
);
2334 upper
= bld
.as_uniform(upper
);
2336 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2339 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2340 nir_print_instr(&instr
->instr
, stderr
);
2341 fprintf(stderr
, "\n");
2345 case nir_op_b2f32
: {
2346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2347 assert(src
.regClass() == bld
.lm
);
2349 if (dst
.regClass() == s1
) {
2350 src
= bool_to_scalar_condition(ctx
, src
);
2351 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2352 } else if (dst
.regClass() == v1
) {
2353 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2355 unreachable("Wrong destination register class for nir_op_b2f32.");
2359 case nir_op_b2f64
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 assert(src
.regClass() == bld
.lm
);
2363 if (dst
.regClass() == s2
) {
2364 src
= bool_to_scalar_condition(ctx
, src
);
2365 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2366 } else if (dst
.regClass() == v2
) {
2367 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2368 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2369 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2371 unreachable("Wrong destination register class for nir_op_b2f64.");
2377 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2378 /* we can actually just say dst = src */
2379 if (src
.regClass() == s1
)
2380 bld
.copy(Definition(dst
), src
);
2382 emit_extract_vector(ctx
, src
, 0, dst
);
2385 case nir_op_i2i16
: {
2386 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2387 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2388 if (dst
.regClass() == s1
) {
2389 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2391 assert(src
.regClass() == v1b
);
2392 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2393 sdwa
->operands
[0] = Operand(src
);
2394 sdwa
->definitions
[0] = Definition(dst
);
2395 sdwa
->sel
[0] = sdwa_sbyte
;
2396 sdwa
->dst_sel
= sdwa_sword
;
2397 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2400 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2401 /* we can actually just say dst = src */
2402 if (src
.regClass() == s1
)
2403 bld
.copy(Definition(dst
), src
);
2405 emit_extract_vector(ctx
, src
, 0, dst
);
2409 case nir_op_u2u16
: {
2410 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2411 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2412 if (dst
.regClass() == s1
)
2413 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2415 assert(src
.regClass() == v1b
);
2416 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2417 sdwa
->operands
[0] = Operand(src
);
2418 sdwa
->definitions
[0] = Definition(dst
);
2419 sdwa
->sel
[0] = sdwa_ubyte
;
2420 sdwa
->dst_sel
= sdwa_uword
;
2421 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2424 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2425 /* we can actually just say dst = src */
2426 if (src
.regClass() == s1
)
2427 bld
.copy(Definition(dst
), src
);
2429 emit_extract_vector(ctx
, src
, 0, dst
);
2433 case nir_op_i2i32
: {
2434 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2435 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2436 if (dst
.regClass() == s1
) {
2437 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(dst
), Operand(src
));
2439 assert(src
.regClass() == v1b
);
2440 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2441 sdwa
->operands
[0] = Operand(src
);
2442 sdwa
->definitions
[0] = Definition(dst
);
2443 sdwa
->sel
[0] = sdwa_sbyte
;
2444 sdwa
->dst_sel
= sdwa_sdword
;
2445 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2447 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2448 if (dst
.regClass() == s1
) {
2449 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(dst
), Operand(src
));
2451 assert(src
.regClass() == v2b
);
2452 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2453 sdwa
->operands
[0] = Operand(src
);
2454 sdwa
->definitions
[0] = Definition(dst
);
2455 sdwa
->sel
[0] = sdwa_sword
;
2456 sdwa
->dst_sel
= sdwa_udword
;
2457 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2459 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2460 /* we can actually just say dst = src, as it would map the lower register */
2461 emit_extract_vector(ctx
, src
, 0, dst
);
2463 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2464 nir_print_instr(&instr
->instr
, stderr
);
2465 fprintf(stderr
, "\n");
2469 case nir_op_u2u32
: {
2470 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2471 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2472 if (dst
.regClass() == s1
)
2473 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFu
), src
);
2475 assert(src
.regClass() == v1b
);
2476 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2477 sdwa
->operands
[0] = Operand(src
);
2478 sdwa
->definitions
[0] = Definition(dst
);
2479 sdwa
->sel
[0] = sdwa_ubyte
;
2480 sdwa
->dst_sel
= sdwa_udword
;
2481 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2483 } else if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2484 if (dst
.regClass() == s1
) {
2485 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2487 assert(src
.regClass() == v2b
);
2488 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
2489 sdwa
->operands
[0] = Operand(src
);
2490 sdwa
->definitions
[0] = Definition(dst
);
2491 sdwa
->sel
[0] = sdwa_uword
;
2492 sdwa
->dst_sel
= sdwa_udword
;
2493 ctx
->block
->instructions
.emplace_back(std::move(sdwa
));
2495 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2496 /* we can actually just say dst = src, as it would map the lower register */
2497 emit_extract_vector(ctx
, src
, 0, dst
);
2499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2500 nir_print_instr(&instr
->instr
, stderr
);
2501 fprintf(stderr
, "\n");
2505 case nir_op_i2i64
: {
2506 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2507 if (src
.regClass() == s1
) {
2508 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2509 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2510 } else if (src
.regClass() == v1
) {
2511 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2514 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2515 nir_print_instr(&instr
->instr
, stderr
);
2516 fprintf(stderr
, "\n");
2520 case nir_op_u2u64
: {
2521 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2522 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2523 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2525 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2526 nir_print_instr(&instr
->instr
, stderr
);
2527 fprintf(stderr
, "\n");
2532 case nir_op_b2i32
: {
2533 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2534 assert(src
.regClass() == bld
.lm
);
2536 if (dst
.regClass() == s1
) {
2537 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2538 bool_to_scalar_condition(ctx
, src
, dst
);
2539 } else if (dst
.regClass() == v1
) {
2540 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2542 unreachable("Invalid register class for b2i32");
2548 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2549 assert(dst
.regClass() == bld
.lm
);
2551 if (src
.type() == RegType::vgpr
) {
2552 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2553 assert(dst
.regClass() == bld
.lm
);
2554 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2555 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2557 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2559 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2560 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2562 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2563 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2565 bool_to_vector_condition(ctx
, tmp
, dst
);
2569 case nir_op_pack_64_2x32_split
: {
2570 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2571 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2573 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2576 case nir_op_unpack_64_2x32_split_x
:
2577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2579 case nir_op_unpack_64_2x32_split_y
:
2580 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2582 case nir_op_unpack_32_2x16_split_x
:
2583 if (dst
.type() == RegType::vgpr
) {
2584 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2586 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2589 case nir_op_unpack_32_2x16_split_y
:
2590 if (dst
.type() == RegType::vgpr
) {
2591 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2593 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2596 case nir_op_pack_32_2x16_split
: {
2597 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2598 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2599 if (dst
.regClass() == v1
) {
2600 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2602 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2603 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2604 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2608 case nir_op_pack_half_2x16
: {
2609 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2611 if (dst
.regClass() == v1
) {
2612 Temp src0
= bld
.tmp(v1
);
2613 Temp src1
= bld
.tmp(v1
);
2614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2615 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2616 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2618 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2619 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2620 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2622 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2623 nir_print_instr(&instr
->instr
, stderr
);
2624 fprintf(stderr
, "\n");
2628 case nir_op_unpack_half_2x16_split_x
: {
2629 if (dst
.regClass() == v1
) {
2630 Builder
bld(ctx
->program
, ctx
->block
);
2631 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2633 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2634 nir_print_instr(&instr
->instr
, stderr
);
2635 fprintf(stderr
, "\n");
2639 case nir_op_unpack_half_2x16_split_y
: {
2640 if (dst
.regClass() == v1
) {
2641 Builder
bld(ctx
->program
, ctx
->block
);
2642 /* TODO: use SDWA here */
2643 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2644 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2646 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2647 nir_print_instr(&instr
->instr
, stderr
);
2648 fprintf(stderr
, "\n");
2652 case nir_op_fquantize2f16
: {
2653 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2654 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2657 if (ctx
->program
->chip_class
>= GFX8
) {
2658 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2659 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2660 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2662 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2663 * so compare the result and flush to 0 if it's smaller.
2665 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2666 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2667 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2668 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2669 cmp_res
= vop3
->definitions
[0].getTemp();
2672 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2673 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2674 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2676 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2681 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2682 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2684 if (dst
.regClass() == s1
) {
2685 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2686 } else if (dst
.regClass() == v1
) {
2687 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2689 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2690 nir_print_instr(&instr
->instr
, stderr
);
2691 fprintf(stderr
, "\n");
2695 case nir_op_bitfield_select
: {
2696 /* (mask & insert) | (~mask & base) */
2697 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2698 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2699 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2701 /* dst = (insert & bitmask) | (base & ~bitmask) */
2702 if (dst
.regClass() == s1
) {
2703 aco_ptr
<Instruction
> sop2
;
2704 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2705 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2707 if (const_insert
&& const_bitmask
) {
2708 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2710 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2711 lhs
= Operand(insert
);
2715 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2716 if (const_base
&& const_bitmask
) {
2717 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2719 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2720 rhs
= Operand(base
);
2723 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2725 } else if (dst
.regClass() == v1
) {
2726 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2727 base
= as_vgpr(ctx
, base
);
2728 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2729 insert
= as_vgpr(ctx
, insert
);
2731 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2742 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2743 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2744 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2746 if (dst
.type() == RegType::sgpr
) {
2748 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2749 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2750 if (const_offset
&& const_bits
) {
2751 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2752 extract
= Operand(const_extract
);
2756 width
= Operand(const_bits
->u32
<< 16);
2758 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2760 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2764 if (dst
.regClass() == s1
) {
2765 if (instr
->op
== nir_op_ubfe
)
2766 opcode
= aco_opcode::s_bfe_u32
;
2768 opcode
= aco_opcode::s_bfe_i32
;
2769 } else if (dst
.regClass() == s2
) {
2770 if (instr
->op
== nir_op_ubfe
)
2771 opcode
= aco_opcode::s_bfe_u64
;
2773 opcode
= aco_opcode::s_bfe_i64
;
2775 unreachable("Unsupported BFE bit size");
2778 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2782 if (dst
.regClass() == v1
) {
2783 if (instr
->op
== nir_op_ubfe
)
2784 opcode
= aco_opcode::v_bfe_u32
;
2786 opcode
= aco_opcode::v_bfe_i32
;
2788 unreachable("Unsupported BFE bit size");
2791 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2795 case nir_op_bit_count
: {
2796 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2797 if (src
.regClass() == s1
) {
2798 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2799 } else if (src
.regClass() == v1
) {
2800 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2801 } else if (src
.regClass() == v2
) {
2802 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2803 emit_extract_vector(ctx
, src
, 1, v1
),
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2805 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2806 } else if (src
.regClass() == s2
) {
2807 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2809 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2810 nir_print_instr(&instr
->instr
, stderr
);
2811 fprintf(stderr
, "\n");
2816 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2820 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2824 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2828 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2832 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2836 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2840 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2841 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2843 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2844 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2848 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2849 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2851 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2852 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2856 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2860 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2865 case nir_op_fddx_fine
:
2866 case nir_op_fddy_fine
:
2867 case nir_op_fddx_coarse
:
2868 case nir_op_fddy_coarse
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2871 if (instr
->op
== nir_op_fddx_fine
) {
2872 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2873 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2874 } else if (instr
->op
== nir_op_fddy_fine
) {
2875 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2876 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2878 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2879 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2880 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2882 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2886 if (ctx
->program
->chip_class
>= GFX8
) {
2887 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2888 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2890 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2891 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2892 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2894 emit_wqm(ctx
, tmp
, dst
, true);
2898 fprintf(stderr
, "Unknown NIR ALU instr: ");
2899 nir_print_instr(&instr
->instr
, stderr
);
2900 fprintf(stderr
, "\n");
2904 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2906 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2908 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2909 // which get truncated the lsb if double and msb if int
2910 // for now, we only use s_mov_b64 with 64bit inline constants
2911 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2912 assert(dst
.type() == RegType::sgpr
);
2914 Builder
bld(ctx
->program
, ctx
->block
);
2916 if (instr
->def
.bit_size
== 1) {
2917 assert(dst
.regClass() == bld
.lm
);
2918 int val
= instr
->value
[0].b
? -1 : 0;
2919 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2920 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2921 } else if (dst
.size() == 1) {
2922 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2924 assert(dst
.size() != 1);
2925 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2926 if (instr
->def
.bit_size
== 64)
2927 for (unsigned i
= 0; i
< dst
.size(); i
++)
2928 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2930 for (unsigned i
= 0; i
< dst
.size(); i
++)
2931 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2933 vec
->definitions
[0] = Definition(dst
);
2934 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2938 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2940 uint32_t new_mask
= 0;
2941 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2942 if (mask
& (1u << i
))
2943 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2947 Operand
load_lds_size_m0(isel_context
*ctx
)
2949 /* TODO: m0 does not need to be initialized on GFX9+ */
2950 Builder
bld(ctx
->program
, ctx
->block
);
2951 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2954 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2955 Temp address
, unsigned base_offset
, unsigned align
)
2957 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2959 Builder
bld(ctx
->program
, ctx
->block
);
2961 Operand m
= load_lds_size_m0(ctx
);
2963 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2964 unsigned bytes_read
= 0;
2965 unsigned result_size
= 0;
2966 unsigned total_bytes
= num_components
* elem_size_bytes
;
2967 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> result
;
2968 bool large_ds_read
= ctx
->options
->chip_class
>= GFX7
;
2969 bool usable_read2
= ctx
->options
->chip_class
>= GFX7
;
2971 while (bytes_read
< total_bytes
) {
2972 unsigned todo
= total_bytes
- bytes_read
;
2973 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2974 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2976 aco_opcode op
= aco_opcode::last_opcode
;
2978 if (todo
>= 16 && aligned16
&& large_ds_read
) {
2979 op
= aco_opcode::ds_read_b128
;
2981 } else if (todo
>= 16 && aligned8
&& usable_read2
) {
2982 op
= aco_opcode::ds_read2_b64
;
2985 } else if (todo
>= 12 && aligned16
&& large_ds_read
) {
2986 op
= aco_opcode::ds_read_b96
;
2988 } else if (todo
>= 8 && aligned8
) {
2989 op
= aco_opcode::ds_read_b64
;
2991 } else if (todo
>= 8 && usable_read2
) {
2992 op
= aco_opcode::ds_read2_b32
;
2995 } else if (todo
>= 4) {
2996 op
= aco_opcode::ds_read_b32
;
3001 assert(todo
% elem_size_bytes
== 0);
3002 unsigned num_elements
= todo
/ elem_size_bytes
;
3003 unsigned offset
= base_offset
+ bytes_read
;
3004 unsigned max_offset
= read2
? 1019 : 65535;
3006 Temp address_offset
= address
;
3007 if (offset
> max_offset
) {
3008 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3009 offset
= bytes_read
;
3011 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
3014 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
3017 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
3020 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
/ (todo
/ 2), (offset
/ (todo
/ 2)) + 1);
3022 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
3024 if (num_components
== 1) {
3025 assert(todo
== total_bytes
);
3026 if (dst
.type() == RegType::sgpr
)
3027 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
3031 if (dst
.type() == RegType::sgpr
) {
3032 Temp new_res
= bld
.tmp(RegType::sgpr
, res
.size());
3033 expand_vector(ctx
, res
, new_res
, res
.size(), (1 << res
.size()) - 1);
3037 if (num_elements
== 1) {
3038 result
[result_size
++] = res
;
3040 assert(res
!= dst
&& res
.size() % num_elements
== 0);
3041 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
3042 split
->operands
[0] = Operand(res
);
3043 for (unsigned i
= 0; i
< num_elements
; i
++)
3044 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
3045 ctx
->block
->instructions
.emplace_back(std::move(split
));
3051 assert(result_size
== num_components
&& result_size
> 1);
3052 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
3053 for (unsigned i
= 0; i
< result_size
; i
++)
3054 vec
->operands
[i
] = Operand(result
[i
]);
3055 vec
->definitions
[0] = Definition(dst
);
3056 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3057 ctx
->allocated_vec
.emplace(dst
.id(), result
);
3062 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
3064 if (start
== 0 && size
== data
.size())
3065 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
3067 unsigned size_hint
= 1;
3068 auto it
= ctx
->allocated_vec
.find(data
.id());
3069 if (it
!= ctx
->allocated_vec
.end())
3070 size_hint
= it
->second
[0].size();
3071 if (size
% size_hint
|| start
% size_hint
)
3078 for (unsigned i
= 0; i
< size
; i
++)
3079 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
3082 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
3084 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
3085 for (unsigned i
= 0; i
< size
; i
++)
3086 vec
->operands
[i
] = Operand(elems
[i
]);
3087 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
3088 vec
->definitions
[0] = Definition(res
);
3089 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3093 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
3095 Builder
bld(ctx
->program
, ctx
->block
);
3096 unsigned bytes_written
= 0;
3097 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3098 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3100 while (bytes_written
< total_size
* 4) {
3101 unsigned todo
= total_size
* 4 - bytes_written
;
3102 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
3103 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
3105 aco_opcode op
= aco_opcode::last_opcode
;
3106 bool write2
= false;
3108 if (todo
>= 16 && aligned16
&& large_ds_write
) {
3109 op
= aco_opcode::ds_write_b128
;
3111 } else if (todo
>= 16 && aligned8
&& usable_write2
) {
3112 op
= aco_opcode::ds_write2_b64
;
3115 } else if (todo
>= 12 && aligned16
&& large_ds_write
) {
3116 op
= aco_opcode::ds_write_b96
;
3118 } else if (todo
>= 8 && aligned8
) {
3119 op
= aco_opcode::ds_write_b64
;
3121 } else if (todo
>= 8 && usable_write2
) {
3122 op
= aco_opcode::ds_write2_b32
;
3125 } else if (todo
>= 4) {
3126 op
= aco_opcode::ds_write_b32
;
3132 unsigned offset
= offset0
+ offset1
+ bytes_written
;
3133 unsigned max_offset
= write2
? 1020 : 65535;
3134 Temp address_offset
= address
;
3135 if (offset
> max_offset
) {
3136 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
3137 offset
= offset1
+ bytes_written
;
3139 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
3142 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
3143 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
3144 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
/ size
/ 2, (offset
/ size
/ 2) + 1);
3146 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
3147 bld
.ds(op
, address_offset
, val
, m
, offset
);
3150 bytes_written
+= size
* 4;
3154 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3155 Temp address
, unsigned base_offset
, unsigned align
)
3157 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
3158 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3160 Operand m
= load_lds_size_m0(ctx
);
3162 /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
3163 assert(wrmask
<= 0x0f);
3164 int start
[2], count
[2];
3165 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
3166 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
3167 assert(wrmask
== 0);
3169 /* one combined store is sufficient */
3170 if (count
[0] == count
[1] && (align
% elem_size_bytes
) == 0 && (base_offset
% elem_size_bytes
) == 0) {
3171 Builder
bld(ctx
->program
, ctx
->block
);
3173 Temp address_offset
= address
;
3174 if ((base_offset
/ elem_size_bytes
) + start
[1] > 255) {
3175 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3179 assert(count
[0] == 1);
3180 RegClass
xtract_rc(RegType::vgpr
, elem_size_bytes
/ 4);
3182 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], xtract_rc
);
3183 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], xtract_rc
);
3184 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3185 base_offset
= base_offset
/ elem_size_bytes
;
3186 bld
.ds(op
, address_offset
, val0
, val1
, m
,
3187 base_offset
+ start
[0], base_offset
+ start
[1]);
3191 for (unsigned i
= 0; i
< 2; i
++) {
3195 unsigned elem_size_words
= elem_size_bytes
/ 4;
3196 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
3197 base_offset
, start
[i
] * elem_size_bytes
, align
);
3202 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3204 unsigned align
= 16;
3206 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3212 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3213 unsigned split_cnt
= 0u, Temp dst
= Temp())
3215 Builder
bld(ctx
->program
, ctx
->block
);
3216 unsigned dword_size
= elem_size_bytes
/ 4;
3219 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3221 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3222 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3223 instr
->definitions
[0] = Definition(dst
);
3225 for (unsigned i
= 0; i
< cnt
; ++i
) {
3227 assert(arr
[i
].size() == dword_size
);
3228 allocated_vec
[i
] = arr
[i
];
3229 instr
->operands
[i
] = Operand(arr
[i
]);
3231 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3232 allocated_vec
[i
] = zero
;
3233 instr
->operands
[i
] = Operand(zero
);
3237 bld
.insert(std::move(instr
));
3240 emit_split_vector(ctx
, dst
, split_cnt
);
3242 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3247 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3249 if (const_offset
>= 4096) {
3250 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3251 const_offset
%= 4096u;
3254 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3255 else if (unlikely(voffset
.regClass() == s1
))
3256 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3257 else if (likely(voffset
.regClass() == v1
))
3258 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3260 unreachable("Unsupported register class of voffset");
3263 return const_offset
;
3266 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3267 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3270 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3271 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3273 Builder
bld(ctx
->program
, ctx
->block
);
3274 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3275 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3277 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3278 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3279 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3280 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3281 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3283 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3286 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3287 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3288 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3290 Builder
bld(ctx
->program
, ctx
->block
);
3291 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3294 if (elem_size_bytes
== 8) {
3295 elem_size_bytes
= 4;
3296 write_mask
= widen_mask(write_mask
, 2);
3299 while (write_mask
) {
3302 u_bit_scan_consecutive_range(&write_mask
, &start
, &count
);
3307 unsigned sub_count
= allow_combining
? MIN2(count
, 4) : 1;
3308 unsigned const_offset
= (unsigned) start
* elem_size_bytes
+ base_const_offset
;
3310 /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
3311 if (unlikely(ctx
->program
->chip_class
== GFX6
&& sub_count
== 3))
3314 Temp elem
= extract_subvector(ctx
, src
, start
, sub_count
, RegType::vgpr
);
3315 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, elem
, const_offset
, reorder
, slc
);
3325 Temp
emit_single_mubuf_load(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
,
3326 unsigned const_offset
, unsigned size_dwords
, bool allow_reorder
= true)
3328 assert(size_dwords
!= 3 || ctx
->program
->chip_class
!= GFX6
);
3329 assert(size_dwords
>= 1 && size_dwords
<= 4);
3331 Builder
bld(ctx
->program
, ctx
->block
);
3332 Temp vdata
= bld
.tmp(RegClass(RegType::vgpr
, size_dwords
));
3333 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_load_dword
+ size_dwords
- 1);
3334 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3336 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3337 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3338 Builder::Result r
= bld
.mubuf(op
, Definition(vdata
), Operand(descriptor
), voffset_op
, soffset_op
, const_offset
,
3339 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3340 /* disable_wqm */ false, /* glc */ true,
3341 /* dlc*/ ctx
->program
->chip_class
>= GFX10
, /* slc */ false);
3343 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3348 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3349 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3350 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3352 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3353 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3354 assert(!!stride
!= allow_combining
);
3356 Builder
bld(ctx
->program
, ctx
->block
);
3357 unsigned split_cnt
= num_components
;
3359 if (elem_size_bytes
== 8) {
3360 elem_size_bytes
= 4;
3361 num_components
*= 2;
3365 stride
= elem_size_bytes
;
3367 unsigned load_size
= 1;
3368 if (allow_combining
) {
3369 if ((num_components
% 4) == 0)
3371 else if ((num_components
% 3) == 0 && ctx
->program
->chip_class
!= GFX6
)
3373 else if ((num_components
% 2) == 0)
3377 unsigned num_loads
= num_components
/ load_size
;
3378 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
3380 for (unsigned i
= 0; i
< num_loads
; ++i
) {
3381 unsigned const_offset
= i
* stride
* load_size
+ base_const_offset
;
3382 elems
[i
] = emit_single_mubuf_load(ctx
, descriptor
, voffset
, soffset
, const_offset
, load_size
, allow_reorder
);
3385 create_vec_from_array(ctx
, elems
.data(), num_loads
, RegType::vgpr
, load_size
* 4u, split_cnt
, dst
);
3388 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3390 Builder
bld(ctx
->program
, ctx
->block
);
3391 Temp offset
= base_offset
.first
;
3392 unsigned const_offset
= base_offset
.second
;
3394 if (!nir_src_is_const(*off_src
)) {
3395 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3398 /* Calculate indirect offset with stride */
3399 if (likely(indirect_offset_arg
.regClass() == v1
))
3400 with_stride
= bld
.v_mul_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3401 else if (indirect_offset_arg
.regClass() == s1
)
3402 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3404 unreachable("Unsupported register class of indirect offset");
3406 /* Add to the supplied base offset */
3407 if (offset
.id() == 0)
3408 offset
= with_stride
;
3409 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3410 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3411 else if (offset
.size() == 1 && with_stride
.size() == 1)
3412 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3414 unreachable("Unsupported register class of indirect offset");
3416 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3417 const_offset
+= const_offset_arg
* stride
;
3420 return std::make_pair(offset
, const_offset
);
3423 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3425 Builder
bld(ctx
->program
, ctx
->block
);
3428 if (off1
.first
.id() && off2
.first
.id()) {
3429 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3430 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3431 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3432 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3434 unreachable("Unsupported register class of indirect offset");
3436 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3439 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3442 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3444 Builder
bld(ctx
->program
, ctx
->block
);
3445 unsigned const_offset
= offs
.second
* multiplier
;
3447 if (!offs
.first
.id())
3448 return std::make_pair(offs
.first
, const_offset
);
3450 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3451 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3452 : bld
.v_mul_imm(bld
.def(v1
), offs
.first
, multiplier
);
3454 return std::make_pair(offset
, const_offset
);
3457 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3459 Builder
bld(ctx
->program
, ctx
->block
);
3461 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3462 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3463 /* component is in bytes */
3464 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3466 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3467 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3468 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3471 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3473 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3476 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3478 Builder
bld(ctx
->program
, ctx
->block
);
3480 switch (ctx
->shader
->info
.stage
) {
3481 case MESA_SHADER_TESS_CTRL
:
3482 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3483 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3484 case MESA_SHADER_TESS_EVAL
:
3485 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3487 unreachable("Unsupported stage in get_tess_rel_patch_id");
3491 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3493 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3494 Builder
bld(ctx
->program
, ctx
->block
);
3496 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
3497 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
3499 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
3501 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3502 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
3504 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3505 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
3506 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
3508 return offset_mul(ctx
, offs
, 4u);
3511 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
3513 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3514 Builder
bld(ctx
->program
, ctx
->block
);
3516 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
3517 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
3518 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
3519 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
3520 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3521 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
3523 std::pair
<Temp
, unsigned> offs
= instr
3524 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
3525 : std::make_pair(Temp(), 0u);
3527 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3528 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
3533 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3534 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
3536 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
3537 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
3539 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
3540 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
3546 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3548 Builder
bld(ctx
->program
, ctx
->block
);
3550 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
3551 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
3553 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
3555 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3556 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
3557 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
3559 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3560 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
3565 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
3567 Builder
bld(ctx
->program
, ctx
->block
);
3569 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
3570 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
3571 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
3573 unsigned output_vertex_size
= num_tcs_outputs
* 16;
3574 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
3575 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
3576 unsigned attr_stride
= ctx
->tcs_num_patches
;
3578 std::pair
<Temp
, unsigned> offs
= instr
3579 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
3580 : std::make_pair(Temp(), 0u);
3582 if (const_base_offset
)
3583 offs
.second
+= const_base_offset
* attr_stride
;
3585 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
3586 Temp patch_off
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, 16u);
3587 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
3592 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
3594 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3595 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3597 if (!nir_src_is_const(*off_src
)) {
3603 off
+= nir_src_as_uint(*off_src
) * 16u;
3606 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
3607 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
3614 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3616 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3617 unsigned component
= nir_intrinsic_component(instr
);
3618 unsigned idx
= nir_intrinsic_base(instr
) + component
;
3620 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
3621 if (off_instr
->type
!= nir_instr_type_load_const
)
3624 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3625 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
3627 if (instr
->src
[0].ssa
->bit_size
== 64)
3628 write_mask
= widen_mask(write_mask
, 2);
3630 for (unsigned i
= 0; i
< 8; ++i
) {
3631 if (write_mask
& (1 << i
)) {
3632 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
3633 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
3641 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
3643 /* Only TCS per-vertex inputs are supported by this function.
3644 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
3646 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
3649 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3650 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
3651 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
3652 bool can_use_temps
= nir_src_is_const(*off_src
) &&
3653 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
3654 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
3659 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
3660 Temp
*src
= &ctx
->inputs
.temps
[idx
];
3661 Temp vec
= create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u);
3662 assert(vec
.size() == dst
.size());
3664 Builder
bld(ctx
->program
, ctx
->block
);
3665 bld
.copy(Definition(dst
), vec
);
3669 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3671 Builder
bld(ctx
->program
, ctx
->block
);
3673 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
3674 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3675 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3676 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
3678 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
3679 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
3680 bool indirect_write
;
3681 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
3682 if (temp_only_input
&& !indirect_write
)
3686 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
3687 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3688 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
3689 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
3690 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
3694 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
3695 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3696 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
3697 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
3698 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
3699 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
3700 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
3701 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
3702 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
3703 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
3704 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
3705 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3706 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3708 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
3709 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
3710 lds_base
= bld
.v_mul_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
3712 unreachable("Invalid LS or ES stage");
3715 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
3716 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
3717 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
3721 bool should_write_tcs_patch_output_to_vmem(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3723 unsigned off
= nir_intrinsic_base(instr
) * 4u;
3724 return off
!= ctx
->tcs_tess_lvl_out_loc
&&
3725 off
!= ctx
->tcs_tess_lvl_in_loc
;
3728 bool should_write_tcs_output_to_lds(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3730 /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3731 if (per_vertex
? ctx
->shader
->info
.outputs_read
== 0U : ctx
->shader
->info
.patch_outputs_read
== 0u)
3734 uint64_t mask
= per_vertex
3735 ? ctx
->shader
->info
.outputs_read
3736 : ctx
->shader
->info
.patch_outputs_read
;
3737 bool indirect_write
;
3738 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
3739 return indirect_write
|| output_read
;
3742 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3744 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3745 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3747 Builder
bld(ctx
->program
, ctx
->block
);
3749 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3750 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3751 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
3753 /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3754 bool write_to_vmem
= per_vertex
|| should_write_tcs_patch_output_to_vmem(ctx
, instr
);
3755 /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3756 bool write_to_lds
= !write_to_vmem
|| should_write_tcs_output_to_lds(ctx
, instr
, per_vertex
);
3758 if (write_to_vmem
) {
3759 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
3760 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
3761 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
3763 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
3764 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
3765 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
3769 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3770 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3771 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3775 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
3777 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
3778 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3780 Builder
bld(ctx
->program
, ctx
->block
);
3782 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3783 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
3784 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
3785 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
3787 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
3790 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3792 if (ctx
->stage
== vertex_vs
||
3793 ctx
->stage
== tess_eval_vs
||
3794 ctx
->stage
== fragment_fs
||
3795 ctx
->stage
== ngg_vertex_gs
||
3796 ctx
->stage
== ngg_tess_eval_gs
||
3797 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
3798 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
3799 if (!stored_to_temps
) {
3800 fprintf(stderr
, "Unimplemented output offset instruction:\n");
3801 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
3802 fprintf(stderr
, "\n");
3805 } else if (ctx
->stage
== vertex_es
||
3806 ctx
->stage
== vertex_ls
||
3807 ctx
->stage
== tess_eval_es
||
3808 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3809 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
3810 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
3811 visit_store_ls_or_es_output(ctx
, instr
);
3812 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
3813 visit_store_tcs_output(ctx
, instr
, false);
3815 unreachable("Shader stage not implemented");
3819 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3821 visit_load_tcs_output(ctx
, instr
, false);
3824 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
3826 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
3827 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
3829 Builder
bld(ctx
->program
, ctx
->block
);
3830 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
3831 if (ctx
->program
->has_16bank_lds
)
3832 interp_p1
.instr
->operands
[0].setLateKill(true);
3833 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
3836 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
3838 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
3839 for (unsigned i
= 0; i
< num_components
; i
++)
3840 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
3841 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
3842 assert(num_components
== 4);
3843 Builder
bld(ctx
->program
, ctx
->block
);
3844 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
3847 for (Operand
& op
: vec
->operands
)
3848 op
= op
.isUndefined() ? Operand(0u) : op
;
3850 vec
->definitions
[0] = Definition(dst
);
3851 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3852 emit_split_vector(ctx
, dst
, num_components
);
3856 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3858 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3859 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3860 unsigned idx
= nir_intrinsic_base(instr
);
3861 unsigned component
= nir_intrinsic_component(instr
);
3862 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3864 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
3866 assert(offset
->u32
== 0);
3868 /* the lower 15bit of the prim_mask contain the offset into LDS
3869 * while the upper bits contain the number of prims */
3870 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3871 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3872 Builder
bld(ctx
->program
, ctx
->block
);
3873 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3874 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3875 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3876 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3877 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3880 if (instr
->dest
.ssa
.num_components
== 1) {
3881 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
3883 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
3884 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
3886 Temp tmp
= {ctx
->program
->allocateId(), v1
};
3887 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
3888 vec
->operands
[i
] = Operand(tmp
);
3890 vec
->definitions
[0] = Definition(dst
);
3891 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3895 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3896 unsigned offset
, unsigned stride
, unsigned channels
)
3898 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
3899 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
3901 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
3902 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
3905 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
3906 unsigned offset
, unsigned stride
, unsigned *channels
)
3908 if (!vtx_info
->chan_byte_size
) {
3909 *channels
= vtx_info
->num_channels
;
3910 return vtx_info
->chan_format
;
3913 unsigned num_channels
= *channels
;
3914 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
3915 unsigned new_channels
= num_channels
+ 1;
3916 /* first, assume more loads is worse and try using a larger data format */
3917 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
3919 /* don't make the attribute potentially out-of-bounds */
3920 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
3924 if (new_channels
== 5) {
3925 /* then try decreasing load size (at the cost of more loads) */
3926 new_channels
= *channels
;
3927 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
3931 if (new_channels
< *channels
)
3932 *channels
= new_channels
;
3933 num_channels
= new_channels
;
3936 switch (vtx_info
->chan_format
) {
3937 case V_008F0C_BUF_DATA_FORMAT_8
:
3938 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
3939 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
3940 case V_008F0C_BUF_DATA_FORMAT_16
:
3941 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
3942 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
3943 case V_008F0C_BUF_DATA_FORMAT_32
:
3944 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
3945 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
3947 unreachable("shouldn't reach here");
3948 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
3951 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3952 * so we may need to fix it up. */
3953 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3955 Builder
bld(ctx
->program
, ctx
->block
);
3957 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3958 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3960 /* For the integer-like cases, do a natural sign extension.
3962 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3963 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3966 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3967 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3969 /* Convert back to the right type. */
3970 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3971 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3972 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3973 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3974 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3975 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3981 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3983 Builder
bld(ctx
->program
, ctx
->block
);
3984 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3985 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
3987 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3988 if (off_instr
->type
!= nir_instr_type_load_const
) {
3989 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3990 nir_print_instr(off_instr
, stderr
);
3991 fprintf(stderr
, "\n");
3993 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3995 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3997 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3998 unsigned component
= nir_intrinsic_component(instr
);
3999 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4000 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4001 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4002 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4004 unsigned dfmt
= attrib_format
& 0xf;
4005 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4006 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4008 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4009 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4010 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4011 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4013 num_channels
= MAX2(num_channels
, 3);
4015 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4016 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4019 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4020 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4021 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4023 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4025 Temp divided
= bld
.tmp(v1
);
4026 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4027 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4029 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4032 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4035 index
= bld
.vadd32(bld
.def(v1
),
4036 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4037 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4040 Temp channels
[num_channels
];
4041 unsigned channel_start
= 0;
4042 bool direct_fetch
= false;
4044 /* skip unused channels at the start */
4045 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4046 channel_start
= ffs(mask
) - 1;
4047 for (unsigned i
= 0; i
< channel_start
; i
++)
4048 channels
[i
] = Temp(0, s1
);
4049 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4050 num_channels
= 3 - (ffs(mask
) - 1);
4054 while (channel_start
< num_channels
) {
4055 unsigned fetch_size
= num_channels
- channel_start
;
4056 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4057 bool expanded
= false;
4059 /* use MUBUF when possible to avoid possible alignment issues */
4060 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4061 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4062 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4063 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4064 vtx_info
->chan_byte_size
== 4;
4065 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4067 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4069 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4070 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4076 Temp fetch_index
= index
;
4077 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4078 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4079 fetch_offset
= fetch_offset
% attrib_stride
;
4082 Operand
soffset(0u);
4083 if (fetch_offset
>= 4096) {
4084 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4085 fetch_offset
%= 4096;
4089 switch (fetch_size
) {
4091 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4094 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4097 assert(ctx
->options
->chip_class
>= GFX7
||
4098 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4099 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4102 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4105 unreachable("Unimplemented load_input vector size");
4109 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4110 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4111 num_channels
<= 3)) {
4112 direct_fetch
= true;
4115 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4119 Instruction
*mubuf
= bld
.mubuf(opcode
,
4120 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4121 fetch_offset
, false, true).instr
;
4122 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4124 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4125 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4126 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4127 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4130 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4132 if (fetch_size
== 1) {
4133 channels
[channel_start
] = fetch_dst
;
4135 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4136 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4139 channel_start
+= fetch_size
;
4142 if (!direct_fetch
) {
4143 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4144 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4146 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4147 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4148 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4150 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4151 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4152 unsigned num_temp
= 0;
4153 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4154 unsigned idx
= i
+ component
;
4155 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4156 Temp channel
= channels
[swizzle
[idx
]];
4157 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4158 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4159 vec
->operands
[i
] = Operand(channel
);
4163 } else if (is_float
&& idx
== 3) {
4164 vec
->operands
[i
] = Operand(0x3f800000u
);
4165 } else if (!is_float
&& idx
== 3) {
4166 vec
->operands
[i
] = Operand(1u);
4168 vec
->operands
[i
] = Operand(0u);
4171 vec
->definitions
[0] = Definition(dst
);
4172 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4173 emit_split_vector(ctx
, dst
, dst
.size());
4175 if (num_temp
== dst
.size())
4176 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4178 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4179 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4180 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4181 if (off_instr
->type
!= nir_instr_type_load_const
||
4182 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4183 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4184 nir_print_instr(off_instr
, stderr
);
4185 fprintf(stderr
, "\n");
4188 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4189 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4191 assert(offset
->u32
== 0);
4193 /* the lower 15bit of the prim_mask contain the offset into LDS
4194 * while the upper bits contain the number of prims */
4195 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4196 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4197 Builder
bld(ctx
->program
, ctx
->block
);
4198 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4199 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4200 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4201 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4202 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4205 unsigned idx
= nir_intrinsic_base(instr
);
4206 unsigned component
= nir_intrinsic_component(instr
);
4207 unsigned vertex_id
= 2; /* P0 */
4209 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4210 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4211 switch (src0
->u32
) {
4213 vertex_id
= 2; /* P0 */
4216 vertex_id
= 0; /* P10 */
4219 vertex_id
= 1; /* P20 */
4222 unreachable("invalid vertex index");
4226 if (dst
.size() == 1) {
4227 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4229 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4230 for (unsigned i
= 0; i
< dst
.size(); i
++)
4231 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4232 vec
->definitions
[0] = Definition(dst
);
4233 bld
.insert(std::move(vec
));
4236 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4237 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4238 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4239 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4240 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4242 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4244 unreachable("Shader stage not implemented");
4248 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4250 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4252 Builder
bld(ctx
->program
, ctx
->block
);
4253 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4256 if (!nir_src_is_const(*vertex_src
)) {
4257 /* better code could be created, but this case probably doesn't happen
4258 * much in practice */
4259 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4260 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4263 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4264 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4266 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4268 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4271 if (vertex_offset
.id()) {
4272 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4273 Operand(i
), indirect_vertex
);
4274 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4276 vertex_offset
= elem
;
4280 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4281 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4283 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4284 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4285 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4286 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4287 Operand((vertex
% 2u) * 16u), Operand(16u));
4289 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4292 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4293 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4294 return offset_mul(ctx
, offs
, 4u);
4297 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4299 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4301 Builder
bld(ctx
->program
, ctx
->block
);
4302 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4303 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4305 if (ctx
->stage
== geometry_gs
) {
4306 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4307 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4308 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4309 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4310 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4311 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4312 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4314 unreachable("Unsupported GS stage.");
4318 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4320 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4322 Builder
bld(ctx
->program
, ctx
->block
);
4323 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4325 if (load_input_from_temps(ctx
, instr
, dst
))
4328 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4329 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4330 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4332 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4335 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4337 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4339 Builder
bld(ctx
->program
, ctx
->block
);
4341 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4342 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4343 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4345 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4346 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4348 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4351 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4353 switch (ctx
->shader
->info
.stage
) {
4354 case MESA_SHADER_GEOMETRY
:
4355 visit_load_gs_per_vertex_input(ctx
, instr
);
4357 case MESA_SHADER_TESS_CTRL
:
4358 visit_load_tcs_per_vertex_input(ctx
, instr
);
4360 case MESA_SHADER_TESS_EVAL
:
4361 visit_load_tes_per_vertex_input(ctx
, instr
);
4364 unreachable("Unimplemented shader stage");
4368 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4370 visit_load_tcs_output(ctx
, instr
, true);
4373 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4375 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4376 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4378 visit_store_tcs_output(ctx
, instr
, true);
4381 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4383 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4385 Builder
bld(ctx
->program
, ctx
->block
);
4386 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4388 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4389 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4392 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4393 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4394 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4395 tes_w
= Operand(tmp
);
4398 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4399 emit_split_vector(ctx
, tess_coord
, 3);
4402 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4404 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4405 Builder
bld(ctx
->program
, ctx
->block
);
4406 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4407 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4408 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4411 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4415 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4417 Builder
bld(ctx
->program
, ctx
->block
);
4418 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4419 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
4420 index
= bld
.as_uniform(index
);
4421 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4422 unsigned binding
= nir_intrinsic_binding(instr
);
4425 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4426 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4427 unsigned offset
= layout
->binding
[binding
].offset
;
4429 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4430 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4431 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4432 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4433 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4436 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4437 stride
= layout
->binding
[binding
].size
;
4440 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4441 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4443 if (nir_const_index
) {
4444 const_index
= const_index
* stride
;
4445 } else if (index
.type() == RegType::vgpr
) {
4446 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4447 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
4449 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
4453 if (nir_const_index
) {
4454 const_index
= const_index
+ offset
;
4455 } else if (index
.type() == RegType::vgpr
) {
4456 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
4458 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
4462 if (nir_const_index
&& const_index
== 0) {
4464 } else if (index
.type() == RegType::vgpr
) {
4465 index
= bld
.vadd32(bld
.def(v1
),
4466 nir_const_index
? Operand(const_index
) : Operand(index
),
4469 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4470 nir_const_index
? Operand(const_index
) : Operand(index
),
4474 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
4477 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
4478 Temp dst
, Temp rsrc
, Temp offset
, int byte_align
,
4479 bool glc
=false, bool readonly
=true)
4481 Builder
bld(ctx
->program
, ctx
->block
);
4482 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4483 unsigned num_bytes
= num_components
* component_size
;
4486 if (dst
.type() == RegType::vgpr
|| ((ctx
->options
->chip_class
< GFX8
|| component_size
< 4) && !readonly
)) {
4487 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4488 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4489 unsigned const_offset
= 0;
4491 /* for small bit sizes add buffer for unaligned loads */
4494 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4499 Temp lower
= Temp();
4500 if (num_bytes
> 16) {
4501 assert(num_components
== 3 || num_components
== 4);
4502 op
= aco_opcode::buffer_load_dwordx4
;
4503 lower
= bld
.tmp(v4
);
4504 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4505 mubuf
->definitions
[0] = Definition(lower
);
4506 mubuf
->operands
[0] = Operand(rsrc
);
4507 mubuf
->operands
[1] = vaddr
;
4508 mubuf
->operands
[2] = soffset
;
4509 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4512 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4513 mubuf
->can_reorder
= readonly
;
4514 bld
.insert(std::move(mubuf
));
4515 emit_split_vector(ctx
, lower
, 2);
4518 } else if (num_bytes
== 12 && ctx
->options
->chip_class
== GFX6
) {
4519 /* GFX6 doesn't support loading vec3, expand to vec4. */
4523 switch (num_bytes
) {
4525 op
= aco_opcode::buffer_load_ubyte
;
4528 op
= aco_opcode::buffer_load_ushort
;
4532 op
= aco_opcode::buffer_load_dword
;
4538 op
= aco_opcode::buffer_load_dwordx2
;
4542 assert(ctx
->options
->chip_class
> GFX6
);
4543 op
= aco_opcode::buffer_load_dwordx3
;
4546 op
= aco_opcode::buffer_load_dwordx4
;
4549 unreachable("Load SSBO not implemented for this size.");
4551 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
4552 mubuf
->operands
[0] = Operand(rsrc
);
4553 mubuf
->operands
[1] = vaddr
;
4554 mubuf
->operands
[2] = soffset
;
4555 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4558 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4559 mubuf
->can_reorder
= readonly
;
4560 mubuf
->offset
= const_offset
;
4561 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
4563 if (component_size
< 4) {
4564 Temp vec
= num_bytes
<= 4 ? bld
.tmp(v1
) : num_bytes
<= 8 ? bld
.tmp(v2
) : bld
.tmp(v3
);
4565 instr
->definitions
[0] = Definition(vec
);
4566 bld
.insert(std::move(instr
));
4568 if (byte_align
== -1 || (byte_align
&& dst
.type() == RegType::sgpr
)) {
4569 Operand align
= byte_align
== -1 ? Operand(offset
) : Operand((uint32_t)byte_align
);
4570 Temp tmp
[3] = {vec
, vec
, vec
};
4572 if (vec
.size() == 3) {
4573 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
4574 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
4575 } else if (vec
.size() == 2) {
4576 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
4577 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
4579 for (unsigned i
= 0; i
< dst
.size(); i
++)
4580 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], align
);
4583 if (dst
.size() == 2)
4584 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
4589 if (dst
.type() == RegType::vgpr
&& num_components
== 1) {
4590 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), vec
, Operand(byte_align
/ component_size
));
4592 trim_subdword_vector(ctx
, vec
, dst
, 4 * vec
.size() / component_size
, ((1 << num_components
) - 1) << byte_align
/ component_size
);
4597 } else if (dst
.size() > 4) {
4598 assert(lower
!= Temp());
4599 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
4600 instr
->definitions
[0] = Definition(upper
);
4601 bld
.insert(std::move(instr
));
4602 if (dst
.size() == 8)
4603 emit_split_vector(ctx
, upper
, 2);
4604 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
4605 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
4606 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
4607 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
4608 if (dst
.size() == 8)
4609 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
4610 } else if (dst
.size() == 3 && ctx
->options
->chip_class
== GFX6
) {
4611 Temp vec
= bld
.tmp(v4
);
4612 instr
->definitions
[0] = Definition(vec
);
4613 bld
.insert(std::move(instr
));
4614 emit_split_vector(ctx
, vec
, 4);
4616 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
4617 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
4618 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
4619 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
4622 if (dst
.type() == RegType::sgpr
) {
4623 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4624 instr
->definitions
[0] = Definition(vec
);
4625 bld
.insert(std::move(instr
));
4626 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
4628 instr
->definitions
[0] = Definition(dst
);
4629 bld
.insert(std::move(instr
));
4630 emit_split_vector(ctx
, dst
, num_components
);
4633 /* for small bit sizes add buffer for unaligned loads */
4635 num_bytes
+= byte_align
== -1 ? 4 - component_size
: byte_align
;
4637 switch (num_bytes
) {
4642 op
= aco_opcode::s_buffer_load_dword
;
4648 op
= aco_opcode::s_buffer_load_dwordx2
;
4653 op
= aco_opcode::s_buffer_load_dwordx4
;
4657 op
= aco_opcode::s_buffer_load_dwordx8
;
4660 unreachable("Load SSBO not implemented for this size.");
4662 offset
= bld
.as_uniform(offset
);
4663 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4664 load
->operands
[0] = Operand(rsrc
);
4665 load
->operands
[1] = Operand(offset
);
4666 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
4667 load
->definitions
[0] = Definition(dst
);
4670 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
4671 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4672 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4674 /* adjust misaligned small bit size loads */
4676 Temp vec
= num_bytes
<= 4 ? bld
.tmp(s1
) : num_bytes
<= 8 ? bld
.tmp(s2
) : bld
.tmp(s4
);
4677 load
->definitions
[0] = Definition(vec
);
4678 bld
.insert(std::move(load
));
4679 Operand byte_offset
= byte_align
> 0 ? Operand(uint32_t(byte_align
)) : Operand(offset
);
4680 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4683 } else if (dst
.size() == 3) {
4684 Temp vec
= bld
.tmp(s4
);
4685 load
->definitions
[0] = Definition(vec
);
4686 bld
.insert(std::move(load
));
4687 emit_split_vector(ctx
, vec
, 4);
4689 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4690 emit_extract_vector(ctx
, vec
, 0, s1
),
4691 emit_extract_vector(ctx
, vec
, 1, s1
),
4692 emit_extract_vector(ctx
, vec
, 2, s1
));
4693 } else if (dst
.size() == 6) {
4694 Temp vec
= bld
.tmp(s8
);
4695 load
->definitions
[0] = Definition(vec
);
4696 bld
.insert(std::move(load
));
4697 emit_split_vector(ctx
, vec
, 4);
4699 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4700 emit_extract_vector(ctx
, vec
, 0, s2
),
4701 emit_extract_vector(ctx
, vec
, 1, s2
),
4702 emit_extract_vector(ctx
, vec
, 2, s2
));
4704 bld
.insert(std::move(load
));
4706 emit_split_vector(ctx
, dst
, num_components
);
4710 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4712 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4713 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4715 Builder
bld(ctx
->program
, ctx
->block
);
4717 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
4718 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
4719 unsigned binding
= nir_intrinsic_binding(idx_instr
);
4720 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
4722 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
4723 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4724 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4725 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4726 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4727 if (ctx
->options
->chip_class
>= GFX10
) {
4728 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4729 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4730 S_008F0C_RESOURCE_LEVEL(1);
4732 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4733 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4735 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
4736 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
4737 Operand(0xFFFFFFFFu
),
4738 Operand(desc_type
));
4739 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4740 rsrc
, upper_dwords
);
4742 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
4743 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4745 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4748 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
4749 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
4750 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
4752 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
);
4755 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4757 Builder
bld(ctx
->program
, ctx
->block
);
4758 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4759 unsigned offset
= nir_intrinsic_base(instr
);
4760 unsigned count
= instr
->dest
.ssa
.num_components
;
4761 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
4763 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
4764 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
4765 start
-= ctx
->args
->ac
.base_inline_push_consts
;
4766 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
4767 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4768 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4769 for (unsigned i
= 0; i
< count
; ++i
) {
4770 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
4771 vec
->operands
[i
] = Operand
{elems
[i
]};
4773 vec
->definitions
[0] = Definition(dst
);
4774 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4775 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4780 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4781 if (offset
!= 0) // TODO check if index != 0 as well
4782 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
4783 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
4786 bool aligned
= true;
4788 if (instr
->dest
.ssa
.bit_size
== 8) {
4789 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4790 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
4792 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
4793 } else if (instr
->dest
.ssa
.bit_size
== 16) {
4794 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
4796 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
4801 switch (vec
.size()) {
4803 op
= aco_opcode::s_load_dword
;
4806 op
= aco_opcode::s_load_dwordx2
;
4812 op
= aco_opcode::s_load_dwordx4
;
4818 op
= aco_opcode::s_load_dwordx8
;
4821 unreachable("unimplemented or forbidden load_push_constant.");
4824 bld
.smem(op
, Definition(vec
), ptr
, index
);
4827 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
4828 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
4833 emit_split_vector(ctx
, vec
, 4);
4834 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
4835 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4836 emit_extract_vector(ctx
, vec
, 0, rc
),
4837 emit_extract_vector(ctx
, vec
, 1, rc
),
4838 emit_extract_vector(ctx
, vec
, 2, rc
));
4841 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4844 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4846 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4848 Builder
bld(ctx
->program
, ctx
->block
);
4850 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
4851 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
4852 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
4853 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
4854 if (ctx
->options
->chip_class
>= GFX10
) {
4855 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
4856 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
4857 S_008F0C_RESOURCE_LEVEL(1);
4859 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
4860 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
4863 unsigned base
= nir_intrinsic_base(instr
);
4864 unsigned range
= nir_intrinsic_range(instr
);
4866 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4867 if (base
&& offset
.type() == RegType::sgpr
)
4868 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
4869 else if (base
&& offset
.type() == RegType::vgpr
)
4870 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
4872 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
4873 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
4874 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
4875 Operand(desc_type
));
4876 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
4877 // TODO: get alignment information for subdword constants
4878 unsigned byte_align
= size
< 4 ? -1 : 0;
4879 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, byte_align
);
4882 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4884 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4885 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4887 ctx
->program
->needs_exact
= true;
4889 // TODO: optimize uniform conditions
4890 Builder
bld(ctx
->program
, ctx
->block
);
4891 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4892 assert(src
.regClass() == bld
.lm
);
4893 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
4894 bld
.pseudo(aco_opcode::p_discard_if
, src
);
4895 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4899 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
4901 Builder
bld(ctx
->program
, ctx
->block
);
4903 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
4904 ctx
->cf_info
.exec_potentially_empty_discard
= true;
4906 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
4907 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
4909 if (ctx
->block
->loop_nest_depth
&&
4910 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
4911 /* we handle discards the same way as jump instructions */
4912 append_logical_end(ctx
->block
);
4914 /* in loops, discard behaves like break */
4915 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
4916 ctx
->block
->kind
|= block_kind_discard
;
4919 /* uniform discard - loop ends here */
4920 assert(nir_instr_is_last(&instr
->instr
));
4921 ctx
->block
->kind
|= block_kind_uniform
;
4922 ctx
->cf_info
.has_branch
= true;
4923 bld
.branch(aco_opcode::p_branch
);
4924 add_linear_edge(ctx
->block
->index
, linear_target
);
4928 /* we add a break right behind the discard() instructions */
4929 ctx
->block
->kind
|= block_kind_break
;
4930 unsigned idx
= ctx
->block
->index
;
4932 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
4933 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
4935 /* remove critical edges from linear CFG */
4936 bld
.branch(aco_opcode::p_branch
);
4937 Block
* break_block
= ctx
->program
->create_and_insert_block();
4938 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4939 break_block
->kind
|= block_kind_uniform
;
4940 add_linear_edge(idx
, break_block
);
4941 add_linear_edge(break_block
->index
, linear_target
);
4942 bld
.reset(break_block
);
4943 bld
.branch(aco_opcode::p_branch
);
4945 Block
* continue_block
= ctx
->program
->create_and_insert_block();
4946 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
4947 add_linear_edge(idx
, continue_block
);
4948 append_logical_start(continue_block
);
4949 ctx
->block
= continue_block
;
4954 /* it can currently happen that NIR doesn't remove the unreachable code */
4955 if (!nir_instr_is_last(&instr
->instr
)) {
4956 ctx
->program
->needs_exact
= true;
4957 /* save exec somewhere temporarily so that it doesn't get
4958 * overwritten before the discard from outer exec masks */
4959 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
4960 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
4961 ctx
->block
->kind
|= block_kind_uses_discard_if
;
4965 /* This condition is incorrect for uniformly branched discards in a loop
4966 * predicated by a divergent condition, but the above code catches that case
4967 * and the discard would end up turning into a discard_if.
4977 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
4978 /* program just ends here */
4979 ctx
->block
->kind
|= block_kind_uniform
;
4980 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
4981 0 /* enabled mask */, 9 /* dest */,
4982 false /* compressed */, true/* done */, true /* valid mask */);
4983 bld
.sopp(aco_opcode::s_endpgm
);
4984 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4986 ctx
->block
->kind
|= block_kind_discard
;
4987 /* branch and linear edge is added by visit_if() */
4991 enum aco_descriptor_type
{
5002 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5003 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5005 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5006 return dim
== ac_image_cube
||
5007 dim
== ac_image_1darray
||
5008 dim
== ac_image_2darray
||
5009 dim
== ac_image_2darraymsaa
;
5012 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5013 enum aco_descriptor_type desc_type
,
5014 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5016 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5017 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5018 if (it != ctx->tex_desc.end())
5021 Temp index
= Temp();
5022 bool index_set
= false;
5023 unsigned constant_index
= 0;
5024 unsigned descriptor_set
;
5025 unsigned base_index
;
5026 Builder
bld(ctx
->program
, ctx
->block
);
5029 assert(tex_instr
&& !image
);
5031 base_index
= tex_instr
->sampler_index
;
5033 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5034 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5038 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5039 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5041 constant_index
+= array_size
* const_value
->u32
;
5043 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5044 if (indirect
.type() == RegType::vgpr
)
5045 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5047 if (array_size
!= 1)
5048 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5054 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5058 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5060 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5061 base_index
= deref_instr
->var
->data
.binding
;
5064 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5065 list
= convert_pointer_to_64_bit(ctx
, list
);
5067 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5068 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5069 unsigned offset
= binding
->offset
;
5070 unsigned stride
= binding
->size
;
5074 assert(base_index
< layout
->binding_count
);
5076 switch (desc_type
) {
5077 case ACO_DESC_IMAGE
:
5079 opcode
= aco_opcode::s_load_dwordx8
;
5081 case ACO_DESC_FMASK
:
5083 opcode
= aco_opcode::s_load_dwordx8
;
5086 case ACO_DESC_SAMPLER
:
5088 opcode
= aco_opcode::s_load_dwordx4
;
5089 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5090 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5092 case ACO_DESC_BUFFER
:
5094 opcode
= aco_opcode::s_load_dwordx4
;
5096 case ACO_DESC_PLANE_0
:
5097 case ACO_DESC_PLANE_1
:
5099 opcode
= aco_opcode::s_load_dwordx8
;
5100 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5102 case ACO_DESC_PLANE_2
:
5104 opcode
= aco_opcode::s_load_dwordx4
;
5108 unreachable("invalid desc_type\n");
5111 offset
+= constant_index
* stride
;
5113 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5114 (!index_set
|| binding
->immutable_samplers_equal
)) {
5115 if (binding
->immutable_samplers_equal
)
5118 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5119 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5120 Operand(samplers
[constant_index
* 4 + 0]),
5121 Operand(samplers
[constant_index
* 4 + 1]),
5122 Operand(samplers
[constant_index
* 4 + 2]),
5123 Operand(samplers
[constant_index
* 4 + 3]));
5128 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5130 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5131 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5134 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5136 if (desc_type
== ACO_DESC_PLANE_2
) {
5138 for (unsigned i
= 0; i
< 8; i
++)
5139 components
[i
] = bld
.tmp(s1
);
5140 bld
.pseudo(aco_opcode::p_split_vector
,
5141 Definition(components
[0]),
5142 Definition(components
[1]),
5143 Definition(components
[2]),
5144 Definition(components
[3]),
5147 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5148 bld
.pseudo(aco_opcode::p_split_vector
,
5149 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5150 Definition(components
[4]),
5151 Definition(components
[5]),
5152 Definition(components
[6]),
5153 Definition(components
[7]),
5156 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5157 components
[0], components
[1], components
[2], components
[3],
5158 components
[4], components
[5], components
[6], components
[7]);
5164 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5167 case GLSL_SAMPLER_DIM_BUF
:
5169 case GLSL_SAMPLER_DIM_1D
:
5170 return array
? 2 : 1;
5171 case GLSL_SAMPLER_DIM_2D
:
5172 return array
? 3 : 2;
5173 case GLSL_SAMPLER_DIM_MS
:
5174 return array
? 4 : 3;
5175 case GLSL_SAMPLER_DIM_3D
:
5176 case GLSL_SAMPLER_DIM_CUBE
:
5178 case GLSL_SAMPLER_DIM_RECT
:
5179 case GLSL_SAMPLER_DIM_SUBPASS
:
5181 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5190 /* Adjust the sample index according to FMASK.
5192 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5193 * which is the identity mapping. Each nibble says which physical sample
5194 * should be fetched to get that sample.
5196 * For example, 0x11111100 means there are only 2 samples stored and
5197 * the second sample covers 3/4 of the pixel. When reading samples 0
5198 * and 1, return physical sample 0 (determined by the first two 0s
5199 * in FMASK), otherwise return physical sample 1.
5201 * The sample index should be adjusted as follows:
5202 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5204 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5206 Builder
bld(ctx
->program
, ctx
->block
);
5207 Temp fmask
= bld
.tmp(v1
);
5208 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5209 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5212 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5213 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5214 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5215 load
->operands
[0] = Operand(fmask_desc_ptr
);
5216 load
->operands
[1] = Operand(s4
); /* no sampler */
5217 load
->operands
[2] = Operand(coord
);
5218 load
->definitions
[0] = Definition(fmask
);
5225 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5226 ctx
->block
->instructions
.emplace_back(std::move(load
));
5228 Operand sample_index4
;
5229 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5230 sample_index4
= Operand(sample_index
.constantValue() << 2);
5231 } else if (sample_index
.regClass() == s1
) {
5232 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5234 assert(sample_index
.regClass() == v1
);
5235 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5239 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5240 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5241 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5242 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5244 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5246 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5247 * resource descriptor is 0 (invalid),
5249 Temp compare
= bld
.tmp(bld
.lm
);
5250 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5251 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5253 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5255 /* Replace the MSAA sample index. */
5256 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5259 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5262 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5263 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5264 bool is_array
= glsl_sampler_type_is_array(type
);
5265 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5266 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5267 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5268 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5269 int count
= image_type_to_components_count(dim
, is_array
);
5270 std::vector
<Temp
> coords(count
);
5271 Builder
bld(ctx
->program
, ctx
->block
);
5275 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5276 /* get sample index */
5277 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5278 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5279 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5280 std::vector
<Temp
> fmask_load_address
;
5281 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5282 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5284 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5285 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5287 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5292 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5293 coords
.resize(coords
.size() + 1);
5294 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5296 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5298 for (int i
= 0; i
< count
; i
++)
5299 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5302 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5303 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5304 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5305 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5308 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5311 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5312 for (unsigned i
= 0; i
< coords
.size(); i
++)
5313 vec
->operands
[i
] = Operand(coords
[i
]);
5314 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5315 vec
->definitions
[0] = Definition(res
);
5316 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5321 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5323 Builder
bld(ctx
->program
, ctx
->block
);
5324 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5325 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5326 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5327 bool is_array
= glsl_sampler_type_is_array(type
);
5328 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5330 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5331 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5332 unsigned num_channels
= util_last_bit(mask
);
5333 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5334 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5337 switch (num_channels
) {
5339 opcode
= aco_opcode::buffer_load_format_x
;
5342 opcode
= aco_opcode::buffer_load_format_xy
;
5345 opcode
= aco_opcode::buffer_load_format_xyz
;
5348 opcode
= aco_opcode::buffer_load_format_xyzw
;
5351 unreachable(">4 channel buffer image load");
5353 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5354 load
->operands
[0] = Operand(rsrc
);
5355 load
->operands
[1] = Operand(vindex
);
5356 load
->operands
[2] = Operand((uint32_t) 0);
5358 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5361 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5362 load
->definitions
[0] = Definition(tmp
);
5364 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5365 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5366 load
->barrier
= barrier_image
;
5367 ctx
->block
->instructions
.emplace_back(std::move(load
));
5369 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5373 Temp coords
= get_image_coords(ctx
, instr
, type
);
5374 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5376 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5377 unsigned num_components
= util_bitcount(dmask
);
5379 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5382 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5384 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5385 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5387 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5388 load
->operands
[0] = Operand(resource
);
5389 load
->operands
[1] = Operand(s4
); /* no sampler */
5390 load
->operands
[2] = Operand(coords
);
5391 load
->definitions
[0] = Definition(tmp
);
5392 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5393 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5394 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5395 load
->dmask
= dmask
;
5397 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5398 load
->barrier
= barrier_image
;
5399 ctx
->block
->instructions
.emplace_back(std::move(load
));
5401 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5405 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5407 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5408 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5409 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5410 bool is_array
= glsl_sampler_type_is_array(type
);
5411 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5413 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5415 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5416 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5417 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5419 switch (data
.size()) {
5421 opcode
= aco_opcode::buffer_store_format_x
;
5424 opcode
= aco_opcode::buffer_store_format_xy
;
5427 opcode
= aco_opcode::buffer_store_format_xyz
;
5430 opcode
= aco_opcode::buffer_store_format_xyzw
;
5433 unreachable(">4 channel buffer image store");
5435 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5436 store
->operands
[0] = Operand(rsrc
);
5437 store
->operands
[1] = Operand(vindex
);
5438 store
->operands
[2] = Operand((uint32_t) 0);
5439 store
->operands
[3] = Operand(data
);
5440 store
->idxen
= true;
5443 store
->disable_wqm
= true;
5444 store
->barrier
= barrier_image
;
5445 ctx
->program
->needs_exact
= true;
5446 ctx
->block
->instructions
.emplace_back(std::move(store
));
5450 assert(data
.type() == RegType::vgpr
);
5451 Temp coords
= get_image_coords(ctx
, instr
, type
);
5452 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5454 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5455 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5457 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5458 store
->operands
[0] = Operand(resource
);
5459 store
->operands
[1] = Operand(data
);
5460 store
->operands
[2] = Operand(coords
);
5463 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5464 store
->dmask
= (1 << data
.size()) - 1;
5466 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5467 store
->disable_wqm
= true;
5468 store
->barrier
= barrier_image
;
5469 ctx
->program
->needs_exact
= true;
5470 ctx
->block
->instructions
.emplace_back(std::move(store
));
5474 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5476 /* return the previous value if dest is ever used */
5477 bool return_previous
= false;
5478 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5479 return_previous
= true;
5482 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5483 return_previous
= true;
5487 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5488 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5489 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5490 bool is_array
= glsl_sampler_type_is_array(type
);
5491 Builder
bld(ctx
->program
, ctx
->block
);
5493 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5494 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5496 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5497 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5499 aco_opcode buf_op
, image_op
;
5500 switch (instr
->intrinsic
) {
5501 case nir_intrinsic_image_deref_atomic_add
:
5502 buf_op
= aco_opcode::buffer_atomic_add
;
5503 image_op
= aco_opcode::image_atomic_add
;
5505 case nir_intrinsic_image_deref_atomic_umin
:
5506 buf_op
= aco_opcode::buffer_atomic_umin
;
5507 image_op
= aco_opcode::image_atomic_umin
;
5509 case nir_intrinsic_image_deref_atomic_imin
:
5510 buf_op
= aco_opcode::buffer_atomic_smin
;
5511 image_op
= aco_opcode::image_atomic_smin
;
5513 case nir_intrinsic_image_deref_atomic_umax
:
5514 buf_op
= aco_opcode::buffer_atomic_umax
;
5515 image_op
= aco_opcode::image_atomic_umax
;
5517 case nir_intrinsic_image_deref_atomic_imax
:
5518 buf_op
= aco_opcode::buffer_atomic_smax
;
5519 image_op
= aco_opcode::image_atomic_smax
;
5521 case nir_intrinsic_image_deref_atomic_and
:
5522 buf_op
= aco_opcode::buffer_atomic_and
;
5523 image_op
= aco_opcode::image_atomic_and
;
5525 case nir_intrinsic_image_deref_atomic_or
:
5526 buf_op
= aco_opcode::buffer_atomic_or
;
5527 image_op
= aco_opcode::image_atomic_or
;
5529 case nir_intrinsic_image_deref_atomic_xor
:
5530 buf_op
= aco_opcode::buffer_atomic_xor
;
5531 image_op
= aco_opcode::image_atomic_xor
;
5533 case nir_intrinsic_image_deref_atomic_exchange
:
5534 buf_op
= aco_opcode::buffer_atomic_swap
;
5535 image_op
= aco_opcode::image_atomic_swap
;
5537 case nir_intrinsic_image_deref_atomic_comp_swap
:
5538 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5539 image_op
= aco_opcode::image_atomic_cmpswap
;
5542 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5545 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5547 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5548 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5549 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5550 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5551 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5552 mubuf
->operands
[0] = Operand(resource
);
5553 mubuf
->operands
[1] = Operand(vindex
);
5554 mubuf
->operands
[2] = Operand((uint32_t)0);
5555 mubuf
->operands
[3] = Operand(data
);
5556 if (return_previous
)
5557 mubuf
->definitions
[0] = Definition(dst
);
5559 mubuf
->idxen
= true;
5560 mubuf
->glc
= return_previous
;
5561 mubuf
->dlc
= false; /* Not needed for atomics */
5562 mubuf
->disable_wqm
= true;
5563 mubuf
->barrier
= barrier_image
;
5564 ctx
->program
->needs_exact
= true;
5565 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5569 Temp coords
= get_image_coords(ctx
, instr
, type
);
5570 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5571 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5572 mimg
->operands
[0] = Operand(resource
);
5573 mimg
->operands
[1] = Operand(data
);
5574 mimg
->operands
[2] = Operand(coords
);
5575 if (return_previous
)
5576 mimg
->definitions
[0] = Definition(dst
);
5577 mimg
->glc
= return_previous
;
5578 mimg
->dlc
= false; /* Not needed for atomics */
5579 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5580 mimg
->dmask
= (1 << data
.size()) - 1;
5582 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5583 mimg
->disable_wqm
= true;
5584 mimg
->barrier
= barrier_image
;
5585 ctx
->program
->needs_exact
= true;
5586 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5590 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5592 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5593 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5594 Builder
bld(ctx
->program
, ctx
->block
);
5596 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5598 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5599 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5601 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5602 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5604 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5605 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5607 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5608 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5609 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5610 if (dst
.type() == RegType::vgpr
)
5611 bld
.copy(Definition(dst
), shr_dst
);
5613 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5615 emit_extract_vector(ctx
, desc
, 2, dst
);
5619 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5621 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5622 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5623 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5624 bool is_array
= glsl_sampler_type_is_array(type
);
5625 Builder
bld(ctx
->program
, ctx
->block
);
5627 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5628 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5629 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5633 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5636 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5638 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5640 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
5641 mimg
->operands
[0] = Operand(resource
);
5642 mimg
->operands
[1] = Operand(s4
); /* no sampler */
5643 mimg
->operands
[2] = Operand(lod
);
5644 uint8_t& dmask
= mimg
->dmask
;
5645 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5646 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
5647 mimg
->da
= glsl_sampler_type_is_array(type
);
5648 mimg
->can_reorder
= true;
5649 Definition
& def
= mimg
->definitions
[0];
5650 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5652 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
5653 glsl_sampler_type_is_array(type
)) {
5655 assert(instr
->dest
.ssa
.num_components
== 3);
5656 Temp tmp
= {ctx
->program
->allocateId(), v3
};
5657 def
= Definition(tmp
);
5658 emit_split_vector(ctx
, tmp
, 3);
5660 /* divide 3rd value by 6 by multiplying with magic number */
5661 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
5662 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
5664 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5665 emit_extract_vector(ctx
, tmp
, 0, v1
),
5666 emit_extract_vector(ctx
, tmp
, 1, v1
),
5669 } else if (ctx
->options
->chip_class
== GFX9
&&
5670 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
5671 glsl_sampler_type_is_array(type
)) {
5672 assert(instr
->dest
.ssa
.num_components
== 2);
5673 def
= Definition(dst
);
5676 def
= Definition(dst
);
5679 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5682 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5684 Builder
bld(ctx
->program
, ctx
->block
);
5685 unsigned num_components
= instr
->num_components
;
5687 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5688 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5689 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5691 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5692 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5695 unsigned align_mul
= nir_intrinsic_align_mul(instr
);
5696 unsigned align_offset
= nir_intrinsic_align_offset(instr
);
5697 byte_align
= align_mul
% 4 == 0 ? align_offset
: -1;
5699 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), byte_align
, glc
, false);
5702 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5704 Builder
bld(ctx
->program
, ctx
->block
);
5705 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5706 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5707 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5708 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5710 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5711 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5713 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
5714 ctx
->options
->chip_class
>= GFX8
&&
5715 elem_size_bytes
>= 4;
5717 offset
= bld
.as_uniform(offset
);
5718 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
5722 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5723 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
5724 /* GFX6 doesn't support storing vec3, split it. */
5725 writemask
|= 1u << (start
+ 2);
5728 int num_bytes
= count
* elem_size_bytes
;
5730 /* dword or larger stores have to be dword-aligned */
5731 if (elem_size_bytes
< 4 && num_bytes
> 2) {
5732 // TODO: improve alignment check of sub-dword stores
5733 unsigned count_new
= 2 / elem_size_bytes
;
5734 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
5739 if (num_bytes
> 16) {
5740 assert(elem_size_bytes
== 8);
5741 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5747 if (elem_size_bytes
< 4) {
5748 if (data
.type() == RegType::sgpr
) {
5749 data
= as_vgpr(ctx
, data
);
5750 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
5752 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
5753 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5754 for (int i
= 0; i
< count
; i
++)
5755 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
5756 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
5757 vec
->definitions
[0] = Definition(write_data
);
5758 bld
.insert(std::move(vec
));
5759 } else if (count
!= instr
->num_components
) {
5760 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5761 for (int i
= 0; i
< count
; i
++) {
5762 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
5763 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
5765 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
5766 vec
->definitions
[0] = Definition(write_data
);
5767 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5768 } else if (!smem
&& data
.type() != RegType::vgpr
) {
5769 assert(num_bytes
% 4 == 0);
5770 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
5771 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
5772 assert(num_bytes
% 4 == 0);
5773 write_data
= bld
.as_uniform(data
);
5778 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
5779 switch (num_bytes
) {
5781 vmem_op
= aco_opcode::buffer_store_byte
;
5784 vmem_op
= aco_opcode::buffer_store_short
;
5787 vmem_op
= aco_opcode::buffer_store_dword
;
5788 smem_op
= aco_opcode::s_buffer_store_dword
;
5791 vmem_op
= aco_opcode::buffer_store_dwordx2
;
5792 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
5795 vmem_op
= aco_opcode::buffer_store_dwordx3
;
5796 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
5799 vmem_op
= aco_opcode::buffer_store_dwordx4
;
5800 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
5803 unreachable("Store SSBO not implemented for this size.");
5805 if (ctx
->stage
== fragment_fs
)
5806 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
5809 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
5810 store
->operands
[0] = Operand(rsrc
);
5812 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5813 offset
, Operand(start
* elem_size_bytes
));
5814 store
->operands
[1] = Operand(off
);
5816 store
->operands
[1] = Operand(offset
);
5818 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
5819 store
->operands
[1].setFixed(m0
);
5820 store
->operands
[2] = Operand(write_data
);
5821 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5823 store
->disable_wqm
= true;
5824 store
->barrier
= barrier_buffer
;
5825 ctx
->block
->instructions
.emplace_back(std::move(store
));
5826 ctx
->program
->wb_smem_l1_on_end
= true;
5827 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
5828 ctx
->block
->kind
|= block_kind_needs_lowering
;
5829 ctx
->program
->needs_exact
= true;
5832 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
5833 store
->operands
[0] = Operand(rsrc
);
5834 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5835 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5836 store
->operands
[3] = Operand(write_data
);
5837 store
->offset
= start
* elem_size_bytes
;
5838 store
->offen
= (offset
.type() == RegType::vgpr
);
5839 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
5841 store
->disable_wqm
= true;
5842 store
->barrier
= barrier_buffer
;
5843 ctx
->program
->needs_exact
= true;
5844 ctx
->block
->instructions
.emplace_back(std::move(store
));
5849 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5851 /* return the previous value if dest is ever used */
5852 bool return_previous
= false;
5853 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5854 return_previous
= true;
5857 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5858 return_previous
= true;
5862 Builder
bld(ctx
->program
, ctx
->block
);
5863 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5865 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
5866 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
5867 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
5869 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5870 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5871 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5873 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5875 aco_opcode op32
, op64
;
5876 switch (instr
->intrinsic
) {
5877 case nir_intrinsic_ssbo_atomic_add
:
5878 op32
= aco_opcode::buffer_atomic_add
;
5879 op64
= aco_opcode::buffer_atomic_add_x2
;
5881 case nir_intrinsic_ssbo_atomic_imin
:
5882 op32
= aco_opcode::buffer_atomic_smin
;
5883 op64
= aco_opcode::buffer_atomic_smin_x2
;
5885 case nir_intrinsic_ssbo_atomic_umin
:
5886 op32
= aco_opcode::buffer_atomic_umin
;
5887 op64
= aco_opcode::buffer_atomic_umin_x2
;
5889 case nir_intrinsic_ssbo_atomic_imax
:
5890 op32
= aco_opcode::buffer_atomic_smax
;
5891 op64
= aco_opcode::buffer_atomic_smax_x2
;
5893 case nir_intrinsic_ssbo_atomic_umax
:
5894 op32
= aco_opcode::buffer_atomic_umax
;
5895 op64
= aco_opcode::buffer_atomic_umax_x2
;
5897 case nir_intrinsic_ssbo_atomic_and
:
5898 op32
= aco_opcode::buffer_atomic_and
;
5899 op64
= aco_opcode::buffer_atomic_and_x2
;
5901 case nir_intrinsic_ssbo_atomic_or
:
5902 op32
= aco_opcode::buffer_atomic_or
;
5903 op64
= aco_opcode::buffer_atomic_or_x2
;
5905 case nir_intrinsic_ssbo_atomic_xor
:
5906 op32
= aco_opcode::buffer_atomic_xor
;
5907 op64
= aco_opcode::buffer_atomic_xor_x2
;
5909 case nir_intrinsic_ssbo_atomic_exchange
:
5910 op32
= aco_opcode::buffer_atomic_swap
;
5911 op64
= aco_opcode::buffer_atomic_swap_x2
;
5913 case nir_intrinsic_ssbo_atomic_comp_swap
:
5914 op32
= aco_opcode::buffer_atomic_cmpswap
;
5915 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
5918 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5920 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
5921 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5922 mubuf
->operands
[0] = Operand(rsrc
);
5923 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
5924 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
5925 mubuf
->operands
[3] = Operand(data
);
5926 if (return_previous
)
5927 mubuf
->definitions
[0] = Definition(dst
);
5929 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
5930 mubuf
->glc
= return_previous
;
5931 mubuf
->dlc
= false; /* Not needed for atomics */
5932 mubuf
->disable_wqm
= true;
5933 mubuf
->barrier
= barrier_buffer
;
5934 ctx
->program
->needs_exact
= true;
5935 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5938 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5940 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5941 Builder
bld(ctx
->program
, ctx
->block
);
5942 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
5943 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
5946 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
5948 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5949 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5951 if (addr
.type() == RegType::vgpr
)
5952 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
5953 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
5956 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5958 Builder
bld(ctx
->program
, ctx
->block
);
5959 unsigned num_components
= instr
->num_components
;
5960 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
5962 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5963 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5965 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5966 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
5968 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
5969 bool global
= ctx
->options
->chip_class
>= GFX9
;
5971 if (ctx
->options
->chip_class
>= GFX7
) {
5973 switch (num_bytes
) {
5975 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
5978 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
5981 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
5984 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
5987 unreachable("load_global not implemented for this size.");
5990 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
5991 flat
->operands
[0] = Operand(addr
);
5992 flat
->operands
[1] = Operand(s1
);
5995 flat
->barrier
= barrier_buffer
;
5997 if (dst
.type() == RegType::sgpr
) {
5998 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
5999 flat
->definitions
[0] = Definition(vec
);
6000 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6001 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6003 flat
->definitions
[0] = Definition(dst
);
6004 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6006 emit_split_vector(ctx
, dst
, num_components
);
6008 assert(ctx
->options
->chip_class
== GFX6
);
6010 /* GFX6 doesn't support loading vec3, expand to vec4. */
6011 num_bytes
= num_bytes
== 12 ? 16 : num_bytes
;
6014 switch (num_bytes
) {
6016 op
= aco_opcode::buffer_load_dword
;
6019 op
= aco_opcode::buffer_load_dwordx2
;
6022 op
= aco_opcode::buffer_load_dwordx4
;
6025 unreachable("load_global not implemented for this size.");
6028 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6030 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6031 mubuf
->operands
[0] = Operand(rsrc
);
6032 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6033 mubuf
->operands
[2] = Operand(0u);
6037 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6038 mubuf
->disable_wqm
= false;
6039 mubuf
->barrier
= barrier_buffer
;
6040 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
6043 if (dst
.size() == 3) {
6044 Temp vec
= bld
.tmp(v4
);
6045 instr
->definitions
[0] = Definition(vec
);
6046 bld
.insert(std::move(instr
));
6047 emit_split_vector(ctx
, vec
, 4);
6049 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, 3, 1));
6050 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, vec
, 0, v1
));
6051 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, vec
, 1, v1
));
6052 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, vec
, 2, v1
));
6055 if (dst
.type() == RegType::sgpr
) {
6056 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
6057 instr
->definitions
[0] = Definition(vec
);
6058 bld
.insert(std::move(instr
));
6059 expand_vector(ctx
, vec
, dst
, num_components
, (1 << num_components
) - 1);
6060 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
6062 instr
->definitions
[0] = Definition(dst
);
6063 bld
.insert(std::move(instr
));
6064 emit_split_vector(ctx
, dst
, num_components
);
6068 switch (num_bytes
) {
6070 op
= aco_opcode::s_load_dword
;
6073 op
= aco_opcode::s_load_dwordx2
;
6077 op
= aco_opcode::s_load_dwordx4
;
6080 unreachable("load_global not implemented for this size.");
6082 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
6083 load
->operands
[0] = Operand(addr
);
6084 load
->operands
[1] = Operand(0u);
6085 load
->definitions
[0] = Definition(dst
);
6088 load
->barrier
= barrier_buffer
;
6089 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
6091 if (dst
.size() == 3) {
6093 Temp vec
= bld
.tmp(s4
);
6094 load
->definitions
[0] = Definition(vec
);
6095 ctx
->block
->instructions
.emplace_back(std::move(load
));
6096 emit_split_vector(ctx
, vec
, 4);
6098 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6099 emit_extract_vector(ctx
, vec
, 0, s1
),
6100 emit_extract_vector(ctx
, vec
, 1, s1
),
6101 emit_extract_vector(ctx
, vec
, 2, s1
));
6103 ctx
->block
->instructions
.emplace_back(std::move(load
));
6108 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6110 Builder
bld(ctx
->program
, ctx
->block
);
6111 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6113 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6114 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6116 if (ctx
->options
->chip_class
>= GFX7
)
6117 addr
= as_vgpr(ctx
, addr
);
6119 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6122 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6123 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6124 /* GFX6 doesn't support storing vec3, split it. */
6125 writemask
|= 1u << (start
+ 2);
6128 unsigned num_bytes
= count
* elem_size_bytes
;
6130 Temp write_data
= data
;
6131 if (count
!= instr
->num_components
) {
6132 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6133 for (int i
= 0; i
< count
; i
++)
6134 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6135 write_data
= bld
.tmp(RegType::vgpr
, count
);
6136 vec
->definitions
[0] = Definition(write_data
);
6137 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6140 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6141 unsigned offset
= start
* elem_size_bytes
;
6143 if (ctx
->options
->chip_class
>= GFX7
) {
6144 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6145 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6146 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6147 Temp carry
= bld
.tmp(bld
.lm
);
6148 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6150 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6151 Operand(offset
), addr0
);
6152 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6154 carry
).def(1).setHint(vcc
);
6156 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6161 bool global
= ctx
->options
->chip_class
>= GFX9
;
6163 switch (num_bytes
) {
6165 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6168 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6171 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6174 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6177 unreachable("store_global not implemented for this size.");
6180 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6181 flat
->operands
[0] = Operand(addr
);
6182 flat
->operands
[1] = Operand(s1
);
6183 flat
->operands
[2] = Operand(data
);
6186 flat
->offset
= offset
;
6187 flat
->disable_wqm
= true;
6188 flat
->barrier
= barrier_buffer
;
6189 ctx
->program
->needs_exact
= true;
6190 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6192 assert(ctx
->options
->chip_class
== GFX6
);
6195 switch (num_bytes
) {
6197 op
= aco_opcode::buffer_store_dword
;
6200 op
= aco_opcode::buffer_store_dwordx2
;
6203 op
= aco_opcode::buffer_store_dwordx4
;
6206 unreachable("store_global not implemented for this size.");
6209 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6211 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6212 mubuf
->operands
[0] = Operand(rsrc
);
6213 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6214 mubuf
->operands
[2] = Operand(0u);
6215 mubuf
->operands
[3] = Operand(write_data
);
6218 mubuf
->offset
= offset
;
6219 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6220 mubuf
->disable_wqm
= true;
6221 mubuf
->barrier
= barrier_buffer
;
6222 ctx
->program
->needs_exact
= true;
6223 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6228 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6230 /* return the previous value if dest is ever used */
6231 bool return_previous
= false;
6232 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6233 return_previous
= true;
6236 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6237 return_previous
= true;
6241 Builder
bld(ctx
->program
, ctx
->block
);
6242 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6243 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6245 if (ctx
->options
->chip_class
>= GFX7
)
6246 addr
= as_vgpr(ctx
, addr
);
6248 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6249 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6250 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6252 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6254 aco_opcode op32
, op64
;
6256 if (ctx
->options
->chip_class
>= GFX7
) {
6257 bool global
= ctx
->options
->chip_class
>= GFX9
;
6258 switch (instr
->intrinsic
) {
6259 case nir_intrinsic_global_atomic_add
:
6260 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6261 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6263 case nir_intrinsic_global_atomic_imin
:
6264 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6265 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6267 case nir_intrinsic_global_atomic_umin
:
6268 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6269 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6271 case nir_intrinsic_global_atomic_imax
:
6272 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6273 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6275 case nir_intrinsic_global_atomic_umax
:
6276 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6277 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6279 case nir_intrinsic_global_atomic_and
:
6280 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6281 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6283 case nir_intrinsic_global_atomic_or
:
6284 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6285 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6287 case nir_intrinsic_global_atomic_xor
:
6288 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6289 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6291 case nir_intrinsic_global_atomic_exchange
:
6292 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6293 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6295 case nir_intrinsic_global_atomic_comp_swap
:
6296 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6297 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6300 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6303 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6304 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6305 flat
->operands
[0] = Operand(addr
);
6306 flat
->operands
[1] = Operand(s1
);
6307 flat
->operands
[2] = Operand(data
);
6308 if (return_previous
)
6309 flat
->definitions
[0] = Definition(dst
);
6310 flat
->glc
= return_previous
;
6311 flat
->dlc
= false; /* Not needed for atomics */
6313 flat
->disable_wqm
= true;
6314 flat
->barrier
= barrier_buffer
;
6315 ctx
->program
->needs_exact
= true;
6316 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6318 assert(ctx
->options
->chip_class
== GFX6
);
6320 switch (instr
->intrinsic
) {
6321 case nir_intrinsic_global_atomic_add
:
6322 op32
= aco_opcode::buffer_atomic_add
;
6323 op64
= aco_opcode::buffer_atomic_add_x2
;
6325 case nir_intrinsic_global_atomic_imin
:
6326 op32
= aco_opcode::buffer_atomic_smin
;
6327 op64
= aco_opcode::buffer_atomic_smin_x2
;
6329 case nir_intrinsic_global_atomic_umin
:
6330 op32
= aco_opcode::buffer_atomic_umin
;
6331 op64
= aco_opcode::buffer_atomic_umin_x2
;
6333 case nir_intrinsic_global_atomic_imax
:
6334 op32
= aco_opcode::buffer_atomic_smax
;
6335 op64
= aco_opcode::buffer_atomic_smax_x2
;
6337 case nir_intrinsic_global_atomic_umax
:
6338 op32
= aco_opcode::buffer_atomic_umax
;
6339 op64
= aco_opcode::buffer_atomic_umax_x2
;
6341 case nir_intrinsic_global_atomic_and
:
6342 op32
= aco_opcode::buffer_atomic_and
;
6343 op64
= aco_opcode::buffer_atomic_and_x2
;
6345 case nir_intrinsic_global_atomic_or
:
6346 op32
= aco_opcode::buffer_atomic_or
;
6347 op64
= aco_opcode::buffer_atomic_or_x2
;
6349 case nir_intrinsic_global_atomic_xor
:
6350 op32
= aco_opcode::buffer_atomic_xor
;
6351 op64
= aco_opcode::buffer_atomic_xor_x2
;
6353 case nir_intrinsic_global_atomic_exchange
:
6354 op32
= aco_opcode::buffer_atomic_swap
;
6355 op64
= aco_opcode::buffer_atomic_swap_x2
;
6357 case nir_intrinsic_global_atomic_comp_swap
:
6358 op32
= aco_opcode::buffer_atomic_cmpswap
;
6359 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6362 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6365 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6367 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6369 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6370 mubuf
->operands
[0] = Operand(rsrc
);
6371 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6372 mubuf
->operands
[2] = Operand(0u);
6373 mubuf
->operands
[3] = Operand(data
);
6374 if (return_previous
)
6375 mubuf
->definitions
[0] = Definition(dst
);
6376 mubuf
->glc
= return_previous
;
6379 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6380 mubuf
->disable_wqm
= true;
6381 mubuf
->barrier
= barrier_buffer
;
6382 ctx
->program
->needs_exact
= true;
6383 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6387 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6388 Builder
bld(ctx
->program
, ctx
->block
);
6389 switch(instr
->intrinsic
) {
6390 case nir_intrinsic_group_memory_barrier
:
6391 case nir_intrinsic_memory_barrier
:
6392 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6394 case nir_intrinsic_memory_barrier_buffer
:
6395 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6397 case nir_intrinsic_memory_barrier_image
:
6398 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6400 case nir_intrinsic_memory_barrier_tcs_patch
:
6401 case nir_intrinsic_memory_barrier_shared
:
6402 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6405 unreachable("Unimplemented memory barrier intrinsic");
6410 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6412 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6413 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6414 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6415 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6416 Builder
bld(ctx
->program
, ctx
->block
);
6418 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6419 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6420 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6423 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6425 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6426 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6427 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6428 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6429 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6431 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6432 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6435 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6437 unsigned offset
= nir_intrinsic_base(instr
);
6438 Operand m
= load_lds_size_m0(ctx
);
6439 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6440 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6442 unsigned num_operands
= 3;
6443 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6444 switch(instr
->intrinsic
) {
6445 case nir_intrinsic_shared_atomic_add
:
6446 op32
= aco_opcode::ds_add_u32
;
6447 op64
= aco_opcode::ds_add_u64
;
6448 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6449 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6451 case nir_intrinsic_shared_atomic_imin
:
6452 op32
= aco_opcode::ds_min_i32
;
6453 op64
= aco_opcode::ds_min_i64
;
6454 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6455 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6457 case nir_intrinsic_shared_atomic_umin
:
6458 op32
= aco_opcode::ds_min_u32
;
6459 op64
= aco_opcode::ds_min_u64
;
6460 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6461 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6463 case nir_intrinsic_shared_atomic_imax
:
6464 op32
= aco_opcode::ds_max_i32
;
6465 op64
= aco_opcode::ds_max_i64
;
6466 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6467 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6469 case nir_intrinsic_shared_atomic_umax
:
6470 op32
= aco_opcode::ds_max_u32
;
6471 op64
= aco_opcode::ds_max_u64
;
6472 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6473 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6475 case nir_intrinsic_shared_atomic_and
:
6476 op32
= aco_opcode::ds_and_b32
;
6477 op64
= aco_opcode::ds_and_b64
;
6478 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6479 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6481 case nir_intrinsic_shared_atomic_or
:
6482 op32
= aco_opcode::ds_or_b32
;
6483 op64
= aco_opcode::ds_or_b64
;
6484 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6485 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6487 case nir_intrinsic_shared_atomic_xor
:
6488 op32
= aco_opcode::ds_xor_b32
;
6489 op64
= aco_opcode::ds_xor_b64
;
6490 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6491 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6493 case nir_intrinsic_shared_atomic_exchange
:
6494 op32
= aco_opcode::ds_write_b32
;
6495 op64
= aco_opcode::ds_write_b64
;
6496 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6497 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6499 case nir_intrinsic_shared_atomic_comp_swap
:
6500 op32
= aco_opcode::ds_cmpst_b32
;
6501 op64
= aco_opcode::ds_cmpst_b64
;
6502 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6503 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6507 unreachable("Unhandled shared atomic intrinsic");
6510 /* return the previous value if dest is ever used */
6511 bool return_previous
= false;
6512 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6513 return_previous
= true;
6516 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6517 return_previous
= true;
6522 if (data
.size() == 1) {
6523 assert(instr
->dest
.ssa
.bit_size
== 32);
6524 op
= return_previous
? op32_rtn
: op32
;
6526 assert(instr
->dest
.ssa
.bit_size
== 64);
6527 op
= return_previous
? op64_rtn
: op64
;
6530 if (offset
> 65535) {
6531 Builder
bld(ctx
->program
, ctx
->block
);
6532 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6536 aco_ptr
<DS_instruction
> ds
;
6537 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6538 ds
->operands
[0] = Operand(address
);
6539 ds
->operands
[1] = Operand(data
);
6540 if (num_operands
== 4)
6541 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6542 ds
->operands
[num_operands
- 1] = m
;
6543 ds
->offset0
= offset
;
6544 if (return_previous
)
6545 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6546 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6549 Temp
get_scratch_resource(isel_context
*ctx
)
6551 Builder
bld(ctx
->program
, ctx
->block
);
6552 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6553 if (ctx
->stage
!= compute_cs
)
6554 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6556 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6557 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6559 if (ctx
->program
->chip_class
>= GFX10
) {
6560 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6561 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6562 S_008F0C_RESOURCE_LEVEL(1);
6563 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6564 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6565 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6568 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6569 if (ctx
->program
->chip_class
<= GFX8
)
6570 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6572 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6575 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6576 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
6577 Builder
bld(ctx
->program
, ctx
->block
);
6578 Temp rsrc
= get_scratch_resource(ctx
);
6579 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6580 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6583 switch (dst
.size()) {
6585 op
= aco_opcode::buffer_load_dword
;
6588 op
= aco_opcode::buffer_load_dwordx2
;
6591 op
= aco_opcode::buffer_load_dwordx3
;
6594 op
= aco_opcode::buffer_load_dwordx4
;
6598 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
6599 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
6600 bld
.def(v4
), rsrc
, offset
,
6601 ctx
->program
->scratch_offset
, 0, true);
6602 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
6603 aco_opcode::buffer_load_dwordx4
,
6604 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
6605 rsrc
, offset
, ctx
->program
->scratch_offset
, 16, true);
6606 emit_split_vector(ctx
, lower
, 2);
6607 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
6608 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
6609 if (dst
.size() == 8) {
6610 emit_split_vector(ctx
, upper
, 2);
6611 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
6612 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
6617 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6618 Format::PSEUDO
, dst
.size() / 2, 1)};
6619 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
6620 vec
->operands
[i
] = Operand(elems
[i
]);
6621 vec
->definitions
[0] = Definition(dst
);
6622 bld
.insert(std::move(vec
));
6623 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
6627 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6630 bld
.mubuf(op
, Definition(dst
), rsrc
, offset
, ctx
->program
->scratch_offset
, 0, true);
6631 emit_split_vector(ctx
, dst
, instr
->num_components
);
6634 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6635 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6636 Builder
bld(ctx
->program
, ctx
->block
);
6637 Temp rsrc
= get_scratch_resource(ctx
);
6638 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6639 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6641 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6642 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6646 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6647 int num_bytes
= count
* elem_size_bytes
;
6649 if (num_bytes
> 16) {
6650 assert(elem_size_bytes
== 8);
6651 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6656 // TODO: check alignment of sub-dword stores
6657 // TODO: split 3 bytes. there is no store instruction for that
6660 if (count
!= instr
->num_components
) {
6661 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6662 for (int i
= 0; i
< count
; i
++) {
6663 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6664 vec
->operands
[i
] = Operand(elem
);
6666 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6667 vec
->definitions
[0] = Definition(write_data
);
6668 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6674 switch (num_bytes
) {
6676 op
= aco_opcode::buffer_store_dword
;
6679 op
= aco_opcode::buffer_store_dwordx2
;
6682 op
= aco_opcode::buffer_store_dwordx3
;
6685 op
= aco_opcode::buffer_store_dwordx4
;
6688 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6691 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6695 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6696 uint8_t log2_ps_iter_samples
;
6697 if (ctx
->program
->info
->ps
.force_persample
) {
6698 log2_ps_iter_samples
=
6699 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6701 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6704 /* The bit pattern matches that used by fixed function fragment
6706 static const unsigned ps_iter_masks
[] = {
6707 0xffff, /* not used */
6713 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6715 Builder
bld(ctx
->program
, ctx
->block
);
6717 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6718 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6719 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6720 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6721 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6722 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6725 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6726 Builder
bld(ctx
->program
, ctx
->block
);
6728 unsigned stream
= nir_intrinsic_stream_id(instr
);
6729 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6730 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6731 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6734 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6736 unsigned num_components
=
6737 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6738 assert(num_components
);
6740 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6741 unsigned stream_offset
= 0;
6742 for (unsigned i
= 0; i
< stream
; i
++) {
6743 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6744 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6747 /* Limit on the stride field for <= GFX7. */
6748 assert(stride
< (1 << 14));
6750 Temp gsvs_dwords
[4];
6751 for (unsigned i
= 0; i
< 4; i
++)
6752 gsvs_dwords
[i
] = bld
.tmp(s1
);
6753 bld
.pseudo(aco_opcode::p_split_vector
,
6754 Definition(gsvs_dwords
[0]),
6755 Definition(gsvs_dwords
[1]),
6756 Definition(gsvs_dwords
[2]),
6757 Definition(gsvs_dwords
[3]),
6760 if (stream_offset
) {
6761 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6763 Temp carry
= bld
.tmp(s1
);
6764 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6765 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6768 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6769 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6771 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6772 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6774 unsigned offset
= 0;
6775 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6776 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6779 for (unsigned j
= 0; j
< 4; j
++) {
6780 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6783 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6784 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6785 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6786 if (const_offset
>= 4096u) {
6787 if (vaddr_offset
.isUndefined())
6788 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6790 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6791 const_offset
%= 4096u;
6794 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6795 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6796 mtbuf
->operands
[1] = vaddr_offset
;
6797 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6798 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6799 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6800 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6801 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6802 mtbuf
->offset
= const_offset
;
6805 mtbuf
->barrier
= barrier_gs_data
;
6806 mtbuf
->can_reorder
= true;
6807 bld
.insert(std::move(mtbuf
));
6810 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6813 /* outputs for the next vertex are undefined and keeping them around can
6814 * create invalid IR with control flow */
6815 ctx
->outputs
.mask
[i
] = 0;
6818 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6821 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6823 Builder
bld(ctx
->program
, ctx
->block
);
6825 if (cluster_size
== 1) {
6827 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6828 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6829 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6830 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6831 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6832 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6833 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6834 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6835 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6836 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6837 //subgroupAnd(val) -> (exec & ~val) == 0
6838 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6839 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6840 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6841 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6842 //subgroupOr(val) -> (val & exec) != 0
6843 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6844 return bool_to_vector_condition(ctx
, tmp
);
6845 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6846 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6847 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6848 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6849 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6850 return bool_to_vector_condition(ctx
, tmp
);
6852 //subgroupClustered{And,Or,Xor}(val, n) ->
6853 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6854 //cluster_offset = ~(n - 1) & lane_id
6855 //cluster_mask = ((1 << n) - 1)
6856 //subgroupClusteredAnd():
6857 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6858 //subgroupClusteredOr():
6859 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6860 //subgroupClusteredXor():
6861 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6862 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6863 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6866 if (op
== nir_op_iand
)
6867 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6869 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6871 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6873 if (ctx
->program
->chip_class
<= GFX7
)
6874 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6875 else if (ctx
->program
->wave_size
== 64)
6876 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6878 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6879 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6880 if (cluster_mask
!= 0xffffffff)
6881 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6883 Definition cmp_def
= Definition();
6884 if (op
== nir_op_iand
) {
6885 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6886 } else if (op
== nir_op_ior
) {
6887 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6888 } else if (op
== nir_op_ixor
) {
6889 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6890 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6891 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6893 cmp_def
.setHint(vcc
);
6894 return cmp_def
.getTemp();
6898 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6900 Builder
bld(ctx
->program
, ctx
->block
);
6902 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6903 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6904 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6906 if (op
== nir_op_iand
)
6907 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6909 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6911 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6912 Temp lo
= lohi
.def(0).getTemp();
6913 Temp hi
= lohi
.def(1).getTemp();
6914 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
6916 Definition cmp_def
= Definition();
6917 if (op
== nir_op_iand
)
6918 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6919 else if (op
== nir_op_ior
)
6920 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
6921 else if (op
== nir_op_ixor
)
6922 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
6923 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
6924 cmp_def
.setHint(vcc
);
6925 return cmp_def
.getTemp();
6928 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6930 Builder
bld(ctx
->program
, ctx
->block
);
6932 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6933 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6934 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6935 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
6936 if (op
== nir_op_iand
)
6937 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6938 else if (op
== nir_op_ior
)
6939 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6940 else if (op
== nir_op_ixor
)
6941 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
6947 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
6949 Builder
bld(ctx
->program
, ctx
->block
);
6950 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6951 if (src
.regClass().type() == RegType::vgpr
) {
6952 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
6953 } else if (src
.regClass() == s1
) {
6954 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
6955 } else if (src
.regClass() == s2
) {
6956 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
6958 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6959 nir_print_instr(&instr
->instr
, stderr
);
6960 fprintf(stderr
, "\n");
6964 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
6966 Builder
bld(ctx
->program
, ctx
->block
);
6967 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
6968 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
6969 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
6971 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
6972 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
6973 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
6974 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
6977 if (ctx
->program
->chip_class
>= GFX8
) {
6978 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
6979 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
6980 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
6981 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
6982 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
6983 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
6985 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
6986 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
6987 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
6988 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
6989 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
6990 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
6991 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
6992 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
6993 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
6994 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
6997 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6998 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
6999 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7000 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7001 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7002 Temp wqm1
= bld
.tmp(v1
);
7003 emit_wqm(ctx
, tmp1
, wqm1
, true);
7004 Temp wqm2
= bld
.tmp(v1
);
7005 emit_wqm(ctx
, tmp2
, wqm2
, true);
7006 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7010 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7012 Builder
bld(ctx
->program
, ctx
->block
);
7013 switch(instr
->intrinsic
) {
7014 case nir_intrinsic_load_barycentric_sample
:
7015 case nir_intrinsic_load_barycentric_pixel
:
7016 case nir_intrinsic_load_barycentric_centroid
: {
7017 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7018 Temp bary
= Temp(0, s2
);
7020 case INTERP_MODE_SMOOTH
:
7021 case INTERP_MODE_NONE
:
7022 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7023 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7024 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7025 bary
= ctx
->persp_centroid
;
7026 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7027 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7029 case INTERP_MODE_NOPERSPECTIVE
:
7030 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7031 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7032 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7033 bary
= ctx
->linear_centroid
;
7034 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7035 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7040 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7041 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7042 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7043 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7044 Operand(p1
), Operand(p2
));
7045 emit_split_vector(ctx
, dst
, 2);
7048 case nir_intrinsic_load_barycentric_model
: {
7049 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7052 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7053 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7054 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7055 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7056 Operand(p1
), Operand(p2
), Operand(p3
));
7057 emit_split_vector(ctx
, dst
, 3);
7060 case nir_intrinsic_load_barycentric_at_sample
: {
7061 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7062 switch (ctx
->options
->key
.fs
.num_samples
) {
7063 case 2: sample_pos_offset
+= 1 << 3; break;
7064 case 4: sample_pos_offset
+= 3 << 3; break;
7065 case 8: sample_pos_offset
+= 7 << 3; break;
7069 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7070 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7071 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7072 if (addr
.type() == RegType::sgpr
) {
7075 sample_pos_offset
+= const_addr
->u32
<< 3;
7076 offset
= Operand(sample_pos_offset
);
7077 } else if (ctx
->options
->chip_class
>= GFX9
) {
7078 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7080 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7081 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7084 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7085 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7087 } else if (ctx
->options
->chip_class
>= GFX9
) {
7088 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7089 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7090 } else if (ctx
->options
->chip_class
>= GFX7
) {
7091 /* addr += private_segment_buffer + sample_pos_offset */
7092 Temp tmp0
= bld
.tmp(s1
);
7093 Temp tmp1
= bld
.tmp(s1
);
7094 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7095 Definition scc_tmp
= bld
.def(s1
, scc
);
7096 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7097 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7098 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7099 Temp pck0
= bld
.tmp(v1
);
7100 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7101 tmp1
= as_vgpr(ctx
, tmp1
);
7102 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7103 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7105 /* sample_pos = flat_load_dwordx2 addr */
7106 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7108 assert(ctx
->options
->chip_class
== GFX6
);
7110 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7111 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7112 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7114 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7115 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7117 sample_pos
= bld
.tmp(v2
);
7119 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7120 load
->definitions
[0] = Definition(sample_pos
);
7121 load
->operands
[0] = Operand(rsrc
);
7122 load
->operands
[1] = Operand(addr
);
7123 load
->operands
[2] = Operand(0u);
7124 load
->offset
= sample_pos_offset
;
7126 load
->addr64
= true;
7129 load
->disable_wqm
= false;
7130 load
->barrier
= barrier_none
;
7131 load
->can_reorder
= true;
7132 ctx
->block
->instructions
.emplace_back(std::move(load
));
7135 /* sample_pos -= 0.5 */
7136 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7137 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7138 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7139 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7140 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7142 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7145 case nir_intrinsic_load_barycentric_at_offset
: {
7146 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7147 RegClass rc
= RegClass(offset
.type(), 1);
7148 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7149 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7150 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7153 case nir_intrinsic_load_front_face
: {
7154 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7155 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7158 case nir_intrinsic_load_view_index
: {
7159 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7160 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7161 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7167 case nir_intrinsic_load_layer_id
: {
7168 unsigned idx
= nir_intrinsic_base(instr
);
7169 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7170 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7173 case nir_intrinsic_load_frag_coord
: {
7174 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7177 case nir_intrinsic_load_sample_pos
: {
7178 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7179 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7180 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7181 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7182 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7185 case nir_intrinsic_load_tess_coord
:
7186 visit_load_tess_coord(ctx
, instr
);
7188 case nir_intrinsic_load_interpolated_input
:
7189 visit_load_interpolated_input(ctx
, instr
);
7191 case nir_intrinsic_store_output
:
7192 visit_store_output(ctx
, instr
);
7194 case nir_intrinsic_load_input
:
7195 case nir_intrinsic_load_input_vertex
:
7196 visit_load_input(ctx
, instr
);
7198 case nir_intrinsic_load_output
:
7199 visit_load_output(ctx
, instr
);
7201 case nir_intrinsic_load_per_vertex_input
:
7202 visit_load_per_vertex_input(ctx
, instr
);
7204 case nir_intrinsic_load_per_vertex_output
:
7205 visit_load_per_vertex_output(ctx
, instr
);
7207 case nir_intrinsic_store_per_vertex_output
:
7208 visit_store_per_vertex_output(ctx
, instr
);
7210 case nir_intrinsic_load_ubo
:
7211 visit_load_ubo(ctx
, instr
);
7213 case nir_intrinsic_load_push_constant
:
7214 visit_load_push_constant(ctx
, instr
);
7216 case nir_intrinsic_load_constant
:
7217 visit_load_constant(ctx
, instr
);
7219 case nir_intrinsic_vulkan_resource_index
:
7220 visit_load_resource(ctx
, instr
);
7222 case nir_intrinsic_discard
:
7223 visit_discard(ctx
, instr
);
7225 case nir_intrinsic_discard_if
:
7226 visit_discard_if(ctx
, instr
);
7228 case nir_intrinsic_load_shared
:
7229 visit_load_shared(ctx
, instr
);
7231 case nir_intrinsic_store_shared
:
7232 visit_store_shared(ctx
, instr
);
7234 case nir_intrinsic_shared_atomic_add
:
7235 case nir_intrinsic_shared_atomic_imin
:
7236 case nir_intrinsic_shared_atomic_umin
:
7237 case nir_intrinsic_shared_atomic_imax
:
7238 case nir_intrinsic_shared_atomic_umax
:
7239 case nir_intrinsic_shared_atomic_and
:
7240 case nir_intrinsic_shared_atomic_or
:
7241 case nir_intrinsic_shared_atomic_xor
:
7242 case nir_intrinsic_shared_atomic_exchange
:
7243 case nir_intrinsic_shared_atomic_comp_swap
:
7244 visit_shared_atomic(ctx
, instr
);
7246 case nir_intrinsic_image_deref_load
:
7247 visit_image_load(ctx
, instr
);
7249 case nir_intrinsic_image_deref_store
:
7250 visit_image_store(ctx
, instr
);
7252 case nir_intrinsic_image_deref_atomic_add
:
7253 case nir_intrinsic_image_deref_atomic_umin
:
7254 case nir_intrinsic_image_deref_atomic_imin
:
7255 case nir_intrinsic_image_deref_atomic_umax
:
7256 case nir_intrinsic_image_deref_atomic_imax
:
7257 case nir_intrinsic_image_deref_atomic_and
:
7258 case nir_intrinsic_image_deref_atomic_or
:
7259 case nir_intrinsic_image_deref_atomic_xor
:
7260 case nir_intrinsic_image_deref_atomic_exchange
:
7261 case nir_intrinsic_image_deref_atomic_comp_swap
:
7262 visit_image_atomic(ctx
, instr
);
7264 case nir_intrinsic_image_deref_size
:
7265 visit_image_size(ctx
, instr
);
7267 case nir_intrinsic_load_ssbo
:
7268 visit_load_ssbo(ctx
, instr
);
7270 case nir_intrinsic_store_ssbo
:
7271 visit_store_ssbo(ctx
, instr
);
7273 case nir_intrinsic_load_global
:
7274 visit_load_global(ctx
, instr
);
7276 case nir_intrinsic_store_global
:
7277 visit_store_global(ctx
, instr
);
7279 case nir_intrinsic_global_atomic_add
:
7280 case nir_intrinsic_global_atomic_imin
:
7281 case nir_intrinsic_global_atomic_umin
:
7282 case nir_intrinsic_global_atomic_imax
:
7283 case nir_intrinsic_global_atomic_umax
:
7284 case nir_intrinsic_global_atomic_and
:
7285 case nir_intrinsic_global_atomic_or
:
7286 case nir_intrinsic_global_atomic_xor
:
7287 case nir_intrinsic_global_atomic_exchange
:
7288 case nir_intrinsic_global_atomic_comp_swap
:
7289 visit_global_atomic(ctx
, instr
);
7291 case nir_intrinsic_ssbo_atomic_add
:
7292 case nir_intrinsic_ssbo_atomic_imin
:
7293 case nir_intrinsic_ssbo_atomic_umin
:
7294 case nir_intrinsic_ssbo_atomic_imax
:
7295 case nir_intrinsic_ssbo_atomic_umax
:
7296 case nir_intrinsic_ssbo_atomic_and
:
7297 case nir_intrinsic_ssbo_atomic_or
:
7298 case nir_intrinsic_ssbo_atomic_xor
:
7299 case nir_intrinsic_ssbo_atomic_exchange
:
7300 case nir_intrinsic_ssbo_atomic_comp_swap
:
7301 visit_atomic_ssbo(ctx
, instr
);
7303 case nir_intrinsic_load_scratch
:
7304 visit_load_scratch(ctx
, instr
);
7306 case nir_intrinsic_store_scratch
:
7307 visit_store_scratch(ctx
, instr
);
7309 case nir_intrinsic_get_buffer_size
:
7310 visit_get_buffer_size(ctx
, instr
);
7312 case nir_intrinsic_control_barrier
: {
7313 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7314 /* GFX6 only (thanks to a hw bug workaround):
7315 * The real barrier instruction isn’t needed, because an entire patch
7316 * always fits into a single wave.
7321 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7322 bld
.sopp(aco_opcode::s_barrier
);
7326 case nir_intrinsic_memory_barrier_tcs_patch
:
7327 case nir_intrinsic_group_memory_barrier
:
7328 case nir_intrinsic_memory_barrier
:
7329 case nir_intrinsic_memory_barrier_buffer
:
7330 case nir_intrinsic_memory_barrier_image
:
7331 case nir_intrinsic_memory_barrier_shared
:
7332 emit_memory_barrier(ctx
, instr
);
7334 case nir_intrinsic_load_num_work_groups
: {
7335 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7336 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7337 emit_split_vector(ctx
, dst
, 3);
7340 case nir_intrinsic_load_local_invocation_id
: {
7341 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7342 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7343 emit_split_vector(ctx
, dst
, 3);
7346 case nir_intrinsic_load_work_group_id
: {
7347 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7348 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7349 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7350 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7351 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7352 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7353 emit_split_vector(ctx
, dst
, 3);
7356 case nir_intrinsic_load_local_invocation_index
: {
7357 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7359 /* The tg_size bits [6:11] contain the subgroup id,
7360 * we need this multiplied by the wave size, and then OR the thread id to it.
7362 if (ctx
->program
->wave_size
== 64) {
7363 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7364 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7365 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7366 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7368 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7369 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7370 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7371 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7375 case nir_intrinsic_load_subgroup_id
: {
7376 if (ctx
->stage
== compute_cs
) {
7377 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7378 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7380 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7384 case nir_intrinsic_load_subgroup_invocation
: {
7385 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7388 case nir_intrinsic_load_num_subgroups
: {
7389 if (ctx
->stage
== compute_cs
)
7390 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7391 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7393 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7396 case nir_intrinsic_ballot
: {
7397 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7398 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7399 Definition tmp
= bld
.def(dst
.regClass());
7400 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7401 if (instr
->src
[0].ssa
->bit_size
== 1) {
7402 assert(src
.regClass() == bld
.lm
);
7403 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7404 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7405 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7406 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7407 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7409 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7410 nir_print_instr(&instr
->instr
, stderr
);
7411 fprintf(stderr
, "\n");
7413 if (dst
.size() != bld
.lm
.size()) {
7414 /* Wave32 with ballot size set to 64 */
7415 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7417 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7420 case nir_intrinsic_shuffle
:
7421 case nir_intrinsic_read_invocation
: {
7422 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7423 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7424 emit_uniform_subgroup(ctx
, instr
, src
);
7426 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7427 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7428 tid
= bld
.as_uniform(tid
);
7429 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7430 if (src
.regClass() == v1
) {
7431 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7432 } else if (src
.regClass() == v2
) {
7433 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7434 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7435 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7436 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7437 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7438 emit_split_vector(ctx
, dst
, 2);
7439 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7440 assert(src
.regClass() == bld
.lm
);
7441 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7442 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7443 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7444 assert(src
.regClass() == bld
.lm
);
7446 if (ctx
->program
->chip_class
<= GFX7
)
7447 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7448 else if (ctx
->program
->wave_size
== 64)
7449 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7451 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7452 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7453 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7454 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7456 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7457 nir_print_instr(&instr
->instr
, stderr
);
7458 fprintf(stderr
, "\n");
7463 case nir_intrinsic_load_sample_id
: {
7464 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7465 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7468 case nir_intrinsic_load_sample_mask_in
: {
7469 visit_load_sample_mask_in(ctx
, instr
);
7472 case nir_intrinsic_read_first_invocation
: {
7473 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7474 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7475 if (src
.regClass() == v1
) {
7477 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7479 } else if (src
.regClass() == v2
) {
7480 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7481 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7482 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7483 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7484 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7485 emit_split_vector(ctx
, dst
, 2);
7486 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7487 assert(src
.regClass() == bld
.lm
);
7488 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7489 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7490 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7491 } else if (src
.regClass() == s1
) {
7492 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7493 } else if (src
.regClass() == s2
) {
7494 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7496 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7497 nir_print_instr(&instr
->instr
, stderr
);
7498 fprintf(stderr
, "\n");
7502 case nir_intrinsic_vote_all
: {
7503 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7504 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7505 assert(src
.regClass() == bld
.lm
);
7506 assert(dst
.regClass() == bld
.lm
);
7508 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7509 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7510 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7513 case nir_intrinsic_vote_any
: {
7514 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7515 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7516 assert(src
.regClass() == bld
.lm
);
7517 assert(dst
.regClass() == bld
.lm
);
7519 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7520 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7523 case nir_intrinsic_reduce
:
7524 case nir_intrinsic_inclusive_scan
:
7525 case nir_intrinsic_exclusive_scan
: {
7526 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7527 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7528 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7529 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7530 nir_intrinsic_cluster_size(instr
) : 0;
7531 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7533 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7534 emit_uniform_subgroup(ctx
, instr
, src
);
7535 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7536 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7538 else if (op
== nir_op_iadd
)
7540 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7542 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7544 switch (instr
->intrinsic
) {
7545 case nir_intrinsic_reduce
:
7546 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7548 case nir_intrinsic_exclusive_scan
:
7549 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7551 case nir_intrinsic_inclusive_scan
:
7552 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7557 } else if (cluster_size
== 1) {
7558 bld
.copy(Definition(dst
), src
);
7560 src
= as_vgpr(ctx
, src
);
7564 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7579 unreachable("unknown reduction op");
7584 switch (instr
->intrinsic
) {
7585 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7586 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7587 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7589 unreachable("unknown reduce intrinsic");
7592 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7593 reduce
->operands
[0] = Operand(src
);
7594 // filled in by aco_reduce_assign.cpp, used internally as part of the
7596 assert(dst
.size() == 1 || dst
.size() == 2);
7597 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7598 reduce
->operands
[2] = Operand(v1
.as_linear());
7600 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7601 reduce
->definitions
[0] = Definition(tmp_dst
);
7602 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7603 reduce
->definitions
[2] = Definition();
7604 reduce
->definitions
[3] = Definition(scc
, s1
);
7605 reduce
->definitions
[4] = Definition();
7606 reduce
->reduce_op
= reduce_op
;
7607 reduce
->cluster_size
= cluster_size
;
7608 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7610 emit_wqm(ctx
, tmp_dst
, dst
);
7614 case nir_intrinsic_quad_broadcast
: {
7615 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7616 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7617 emit_uniform_subgroup(ctx
, instr
, src
);
7619 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7620 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7621 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7623 if (instr
->dest
.ssa
.bit_size
== 1) {
7624 assert(src
.regClass() == bld
.lm
);
7625 assert(dst
.regClass() == bld
.lm
);
7626 uint32_t half_mask
= 0x11111111u
<< lane
;
7627 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7628 Temp tmp
= bld
.tmp(bld
.lm
);
7629 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7630 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7631 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7632 emit_wqm(ctx
, tmp
, dst
);
7633 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7634 if (ctx
->program
->chip_class
>= GFX8
)
7635 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7637 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7638 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7639 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7640 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7641 if (ctx
->program
->chip_class
>= GFX8
) {
7642 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7643 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7645 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7646 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7648 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7649 emit_split_vector(ctx
, dst
, 2);
7651 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7652 nir_print_instr(&instr
->instr
, stderr
);
7653 fprintf(stderr
, "\n");
7658 case nir_intrinsic_quad_swap_horizontal
:
7659 case nir_intrinsic_quad_swap_vertical
:
7660 case nir_intrinsic_quad_swap_diagonal
:
7661 case nir_intrinsic_quad_swizzle_amd
: {
7662 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7663 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7664 emit_uniform_subgroup(ctx
, instr
, src
);
7667 uint16_t dpp_ctrl
= 0;
7668 switch (instr
->intrinsic
) {
7669 case nir_intrinsic_quad_swap_horizontal
:
7670 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7672 case nir_intrinsic_quad_swap_vertical
:
7673 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7675 case nir_intrinsic_quad_swap_diagonal
:
7676 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7678 case nir_intrinsic_quad_swizzle_amd
:
7679 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7684 if (ctx
->program
->chip_class
< GFX8
)
7685 dpp_ctrl
|= (1 << 15);
7687 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7688 if (instr
->dest
.ssa
.bit_size
== 1) {
7689 assert(src
.regClass() == bld
.lm
);
7690 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7691 if (ctx
->program
->chip_class
>= GFX8
)
7692 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7694 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7695 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7696 emit_wqm(ctx
, tmp
, dst
);
7697 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7699 if (ctx
->program
->chip_class
>= GFX8
)
7700 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7702 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7703 emit_wqm(ctx
, tmp
, dst
);
7704 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7705 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7706 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7707 if (ctx
->program
->chip_class
>= GFX8
) {
7708 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7709 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7711 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7712 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7714 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7715 emit_split_vector(ctx
, dst
, 2);
7717 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7718 nir_print_instr(&instr
->instr
, stderr
);
7719 fprintf(stderr
, "\n");
7723 case nir_intrinsic_masked_swizzle_amd
: {
7724 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7725 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7726 emit_uniform_subgroup(ctx
, instr
, src
);
7729 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7730 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7731 if (dst
.regClass() == v1
) {
7733 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7735 } else if (dst
.regClass() == v2
) {
7736 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7737 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7738 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7739 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7740 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7741 emit_split_vector(ctx
, dst
, 2);
7743 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7744 nir_print_instr(&instr
->instr
, stderr
);
7745 fprintf(stderr
, "\n");
7749 case nir_intrinsic_write_invocation_amd
: {
7750 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7751 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7752 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7753 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7754 if (dst
.regClass() == v1
) {
7755 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7756 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7757 } else if (dst
.regClass() == v2
) {
7758 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7759 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7760 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7761 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7762 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7763 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7764 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7765 emit_split_vector(ctx
, dst
, 2);
7767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7768 nir_print_instr(&instr
->instr
, stderr
);
7769 fprintf(stderr
, "\n");
7773 case nir_intrinsic_mbcnt_amd
: {
7774 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7775 RegClass rc
= RegClass(src
.type(), 1);
7776 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7777 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7778 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7779 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7780 emit_wqm(ctx
, wqm_tmp
, dst
);
7783 case nir_intrinsic_load_helper_invocation
: {
7784 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7785 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7786 ctx
->block
->kind
|= block_kind_needs_lowering
;
7787 ctx
->program
->needs_exact
= true;
7790 case nir_intrinsic_is_helper_invocation
: {
7791 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7792 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7793 ctx
->block
->kind
|= block_kind_needs_lowering
;
7794 ctx
->program
->needs_exact
= true;
7797 case nir_intrinsic_demote
:
7798 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7800 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7801 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7802 ctx
->block
->kind
|= block_kind_uses_demote
;
7803 ctx
->program
->needs_exact
= true;
7805 case nir_intrinsic_demote_if
: {
7806 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7807 assert(src
.regClass() == bld
.lm
);
7808 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7809 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7811 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7812 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7813 ctx
->block
->kind
|= block_kind_uses_demote
;
7814 ctx
->program
->needs_exact
= true;
7817 case nir_intrinsic_first_invocation
: {
7818 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7819 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7822 case nir_intrinsic_shader_clock
:
7823 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7824 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7826 case nir_intrinsic_load_vertex_id_zero_base
: {
7827 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7828 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7831 case nir_intrinsic_load_first_vertex
: {
7832 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7833 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7836 case nir_intrinsic_load_base_instance
: {
7837 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7838 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7841 case nir_intrinsic_load_instance_id
: {
7842 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7843 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7846 case nir_intrinsic_load_draw_id
: {
7847 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7848 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7851 case nir_intrinsic_load_invocation_id
: {
7852 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7854 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7855 if (ctx
->options
->chip_class
>= GFX10
)
7856 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7858 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7859 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7860 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7861 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7863 unreachable("Unsupported stage for load_invocation_id");
7868 case nir_intrinsic_load_primitive_id
: {
7869 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7871 switch (ctx
->shader
->info
.stage
) {
7872 case MESA_SHADER_GEOMETRY
:
7873 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7875 case MESA_SHADER_TESS_CTRL
:
7876 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7878 case MESA_SHADER_TESS_EVAL
:
7879 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7882 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7887 case nir_intrinsic_load_patch_vertices_in
: {
7888 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
7889 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
7891 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7892 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
7895 case nir_intrinsic_emit_vertex_with_counter
: {
7896 visit_emit_vertex_with_counter(ctx
, instr
);
7899 case nir_intrinsic_end_primitive_with_counter
: {
7900 unsigned stream
= nir_intrinsic_stream_id(instr
);
7901 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
7904 case nir_intrinsic_set_vertex_count
: {
7905 /* unused, the HW keeps track of this for us */
7909 fprintf(stderr
, "Unimplemented intrinsic instr: ");
7910 nir_print_instr(&instr
->instr
, stderr
);
7911 fprintf(stderr
, "\n");
7919 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
7920 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
7921 enum glsl_base_type
*stype
)
7923 nir_deref_instr
*texture_deref_instr
= NULL
;
7924 nir_deref_instr
*sampler_deref_instr
= NULL
;
7927 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
7928 switch (instr
->src
[i
].src_type
) {
7929 case nir_tex_src_texture_deref
:
7930 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7932 case nir_tex_src_sampler_deref
:
7933 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
7935 case nir_tex_src_plane
:
7936 plane
= nir_src_as_int(instr
->src
[i
].src
);
7943 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
7945 if (!sampler_deref_instr
)
7946 sampler_deref_instr
= texture_deref_instr
;
7949 assert(instr
->op
!= nir_texop_txf_ms
&&
7950 instr
->op
!= nir_texop_samples_identical
);
7951 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
7952 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
7953 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
7954 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
7955 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
7956 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7958 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
7961 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
7963 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
7964 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7965 Builder
bld(ctx
->program
, ctx
->block
);
7967 /* to avoid unnecessary moves, we split and recombine sampler and image */
7968 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
7969 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7970 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
7971 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
7972 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
7973 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
7974 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
7975 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
7977 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
7978 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
7979 img
[0], img
[1], img
[2], img
[3],
7980 img
[4], img
[5], img
[6], img
[7]);
7981 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
7982 samp
[0], samp
[1], samp
[2], samp
[3]);
7985 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
7986 instr
->op
== nir_texop_samples_identical
))
7987 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
7990 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
7991 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
7993 Builder
bld(ctx
->program
, ctx
->block
);
7995 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
7996 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
7997 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
7999 Operand
neg_one(0xbf800000u
);
8000 Operand
one(0x3f800000u
);
8001 Operand
two(0x40000000u
);
8002 Operand
four(0x40800000u
);
8004 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8005 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8006 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8008 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8009 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8010 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8011 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8014 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8015 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8016 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8018 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8021 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8022 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8023 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8026 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8027 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8029 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8030 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8033 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8035 Builder
bld(ctx
->program
, ctx
->block
);
8036 Temp ma
, tc
, sc
, id
;
8039 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8041 // see comment in ac_prepare_cube_coords()
8042 if (ctx
->options
->chip_class
<= GFX8
)
8043 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8046 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8048 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8049 vop3a
->operands
[0] = Operand(ma
);
8050 vop3a
->abs
[0] = true;
8051 Temp invma
= bld
.tmp(v1
);
8052 vop3a
->definitions
[0] = Definition(invma
);
8053 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8055 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8057 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8059 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8061 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8063 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8066 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8067 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8069 for (unsigned i
= 0; i
< 2; i
++) {
8070 // see comment in ac_prepare_cube_coords()
8072 Temp deriv_sc
, deriv_tc
;
8073 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8074 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8076 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8078 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8079 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8080 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8081 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8082 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8083 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8084 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8087 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8088 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8092 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8099 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8101 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8103 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8104 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8107 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8108 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8109 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8113 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8115 Builder
bld(ctx
->program
, ctx
->block
);
8116 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8117 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8118 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8119 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8120 std::vector
<Temp
> coords
;
8121 std::vector
<Temp
> derivs
;
8122 nir_const_value
*sample_index_cv
= NULL
;
8123 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8124 enum glsl_base_type stype
;
8125 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8127 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8128 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8129 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8130 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8132 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8133 switch (instr
->src
[i
].src_type
) {
8134 case nir_tex_src_coord
: {
8135 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8136 for (unsigned i
= 0; i
< coord
.size(); i
++)
8137 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8140 case nir_tex_src_bias
:
8141 if (instr
->op
== nir_texop_txb
) {
8142 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8146 case nir_tex_src_lod
: {
8147 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8149 if (val
&& val
->f32
<= 0.0) {
8152 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8157 case nir_tex_src_comparator
:
8158 if (instr
->is_shadow
) {
8159 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8163 case nir_tex_src_offset
:
8164 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8165 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8168 case nir_tex_src_ddx
:
8169 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8172 case nir_tex_src_ddy
:
8173 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8176 case nir_tex_src_ms_index
:
8177 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8178 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8179 has_sample_index
= true;
8181 case nir_tex_src_texture_offset
:
8182 case nir_tex_src_sampler_offset
:
8188 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8189 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8191 if (instr
->op
== nir_texop_texture_samples
) {
8192 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8194 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8195 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8196 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8197 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8199 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8200 samples
, Operand(1u), bld
.scc(is_msaa
));
8204 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8205 aco_ptr
<Instruction
> tmp_instr
;
8206 Temp acc
, pack
= Temp();
8208 uint32_t pack_const
= 0;
8209 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8210 if (!const_offset
[i
])
8212 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8215 if (offset
.type() == RegType::sgpr
) {
8216 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8217 if (const_offset
[i
])
8220 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8221 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8224 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8227 if (pack
== Temp()) {
8230 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8234 if (pack_const
&& pack
!= Temp())
8235 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8237 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8238 if (const_offset
[i
])
8241 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8242 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8245 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8248 if (pack
== Temp()) {
8251 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8255 if (pack_const
&& pack
!= Temp())
8256 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8258 if (pack_const
&& pack
== Temp())
8259 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8260 else if (pack
== Temp())
8266 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8267 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8269 /* pack derivatives */
8270 if (has_ddx
|| has_ddy
) {
8271 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8272 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8273 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8274 derivs
= {ddy
, zero
, ddy
, zero
};
8276 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8277 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8278 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8279 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8284 if (instr
->coord_components
> 1 &&
8285 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8287 instr
->op
!= nir_texop_txf
)
8288 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8290 if (instr
->coord_components
> 2 &&
8291 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8292 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8293 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8294 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8296 instr
->op
!= nir_texop_txf
&&
8297 instr
->op
!= nir_texop_txf_ms
&&
8298 instr
->op
!= nir_texop_fragment_fetch
&&
8299 instr
->op
!= nir_texop_fragment_mask_fetch
)
8300 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8302 if (ctx
->options
->chip_class
== GFX9
&&
8303 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8304 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8305 assert(coords
.size() > 0 && coords
.size() < 3);
8307 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8308 Operand((uint32_t) 0) :
8309 Operand((uint32_t) 0x3f000000)));
8312 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8314 if (instr
->op
== nir_texop_samples_identical
)
8315 resource
= fmask_ptr
;
8317 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8318 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8319 instr
->op
!= nir_texop_txs
&&
8320 instr
->op
!= nir_texop_fragment_fetch
&&
8321 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8322 assert(has_sample_index
);
8323 Operand
op(sample_index
);
8324 if (sample_index_cv
)
8325 op
= Operand(sample_index_cv
->u32
);
8326 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8329 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8330 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8331 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8332 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8337 /* Build tex instruction */
8338 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8339 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8340 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8342 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8345 /* gather4 selects the component by dmask and always returns vec4 */
8346 if (instr
->op
== nir_texop_tg4
) {
8347 assert(instr
->dest
.ssa
.num_components
== 4);
8348 if (instr
->is_shadow
)
8351 dmask
= 1 << instr
->component
;
8352 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8353 tmp_dst
= bld
.tmp(v4
);
8354 } else if (instr
->op
== nir_texop_samples_identical
) {
8355 tmp_dst
= bld
.tmp(v1
);
8356 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8357 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8360 aco_ptr
<MIMG_instruction
> tex
;
8361 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8363 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8365 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8366 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8369 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8370 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8372 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8373 tex
->operands
[0] = Operand(resource
);
8374 tex
->operands
[1] = Operand(s4
); /* no sampler */
8375 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8376 if (ctx
->options
->chip_class
== GFX9
&&
8377 instr
->op
== nir_texop_txs
&&
8378 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8380 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8381 } else if (instr
->op
== nir_texop_query_levels
) {
8382 tex
->dmask
= 1 << 3;
8387 tex
->definitions
[0] = Definition(tmp_dst
);
8389 tex
->can_reorder
= true;
8390 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8393 /* divide 3rd value by 6 by multiplying with magic number */
8394 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8395 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8396 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8397 assert(instr
->dest
.ssa
.num_components
== 3);
8398 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8399 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8400 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8401 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8406 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8410 Temp tg4_compare_cube_wa64
= Temp();
8412 if (tg4_integer_workarounds
) {
8413 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8414 tex
->operands
[0] = Operand(resource
);
8415 tex
->operands
[1] = Operand(s4
); /* no sampler */
8416 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8420 Temp size
= bld
.tmp(v2
);
8421 tex
->definitions
[0] = Definition(size
);
8422 tex
->can_reorder
= true;
8423 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8424 emit_split_vector(ctx
, size
, size
.size());
8427 for (unsigned i
= 0; i
< 2; i
++) {
8428 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8429 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8430 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8431 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8434 Temp new_coords
[2] = {
8435 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8436 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8439 if (tg4_integer_cube_workaround
) {
8440 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8441 Temp desc
[resource
.size()];
8442 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8443 Format::PSEUDO
, 1, resource
.size())};
8444 split
->operands
[0] = Operand(resource
);
8445 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8446 desc
[i
] = bld
.tmp(s1
);
8447 split
->definitions
[i
] = Definition(desc
[i
]);
8449 ctx
->block
->instructions
.emplace_back(std::move(split
));
8451 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8452 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8453 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8456 if (stype
== GLSL_TYPE_UINT
) {
8457 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8458 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8459 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8460 bld
.scc(compare_cube_wa
));
8462 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8463 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8464 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8465 bld
.scc(compare_cube_wa
));
8467 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8468 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8470 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8472 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8473 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8474 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8476 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8477 Format::PSEUDO
, resource
.size(), 1)};
8478 for (unsigned i
= 0; i
< resource
.size(); i
++)
8479 vec
->operands
[i
] = Operand(desc
[i
]);
8480 resource
= bld
.tmp(resource
.regClass());
8481 vec
->definitions
[0] = Definition(resource
);
8482 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8484 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8485 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8486 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8487 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8489 coords
[0] = new_coords
[0];
8490 coords
[1] = new_coords
[1];
8493 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8494 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8496 assert(coords
.size() == 1);
8497 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8501 op
= aco_opcode::buffer_load_format_x
; break;
8503 op
= aco_opcode::buffer_load_format_xy
; break;
8505 op
= aco_opcode::buffer_load_format_xyz
; break;
8507 op
= aco_opcode::buffer_load_format_xyzw
; break;
8509 unreachable("Tex instruction loads more than 4 components.");
8512 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8513 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8516 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8518 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8519 mubuf
->operands
[0] = Operand(resource
);
8520 mubuf
->operands
[1] = Operand(coords
[0]);
8521 mubuf
->operands
[2] = Operand((uint32_t) 0);
8522 mubuf
->definitions
[0] = Definition(tmp_dst
);
8523 mubuf
->idxen
= true;
8524 mubuf
->can_reorder
= true;
8525 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8527 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8531 /* gather MIMG address components */
8532 std::vector
<Temp
> args
;
8534 args
.emplace_back(offset
);
8536 args
.emplace_back(bias
);
8538 args
.emplace_back(compare
);
8540 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8542 args
.insert(args
.end(), coords
.begin(), coords
.end());
8543 if (has_sample_index
)
8544 args
.emplace_back(sample_index
);
8546 args
.emplace_back(lod
);
8548 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8549 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8550 vec
->definitions
[0] = Definition(arg
);
8551 for (unsigned i
= 0; i
< args
.size(); i
++)
8552 vec
->operands
[i
] = Operand(args
[i
]);
8553 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8556 if (instr
->op
== nir_texop_txf
||
8557 instr
->op
== nir_texop_txf_ms
||
8558 instr
->op
== nir_texop_samples_identical
||
8559 instr
->op
== nir_texop_fragment_fetch
||
8560 instr
->op
== nir_texop_fragment_mask_fetch
) {
8561 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8562 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8563 tex
->operands
[0] = Operand(resource
);
8564 tex
->operands
[1] = Operand(s4
); /* no sampler */
8565 tex
->operands
[2] = Operand(arg
);
8570 tex
->definitions
[0] = Definition(tmp_dst
);
8571 tex
->can_reorder
= true;
8572 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8574 if (instr
->op
== nir_texop_samples_identical
) {
8575 assert(dmask
== 1 && dst
.regClass() == v1
);
8576 assert(dst
.id() != tmp_dst
.id());
8578 Temp tmp
= bld
.tmp(bld
.lm
);
8579 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8580 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8583 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8588 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8589 aco_opcode opcode
= aco_opcode::image_sample
;
8590 if (has_offset
) { /* image_sample_*_o */
8592 opcode
= aco_opcode::image_sample_c_o
;
8594 opcode
= aco_opcode::image_sample_c_d_o
;
8596 opcode
= aco_opcode::image_sample_c_b_o
;
8598 opcode
= aco_opcode::image_sample_c_lz_o
;
8600 opcode
= aco_opcode::image_sample_c_l_o
;
8602 opcode
= aco_opcode::image_sample_o
;
8604 opcode
= aco_opcode::image_sample_d_o
;
8606 opcode
= aco_opcode::image_sample_b_o
;
8608 opcode
= aco_opcode::image_sample_lz_o
;
8610 opcode
= aco_opcode::image_sample_l_o
;
8612 } else { /* no offset */
8614 opcode
= aco_opcode::image_sample_c
;
8616 opcode
= aco_opcode::image_sample_c_d
;
8618 opcode
= aco_opcode::image_sample_c_b
;
8620 opcode
= aco_opcode::image_sample_c_lz
;
8622 opcode
= aco_opcode::image_sample_c_l
;
8624 opcode
= aco_opcode::image_sample
;
8626 opcode
= aco_opcode::image_sample_d
;
8628 opcode
= aco_opcode::image_sample_b
;
8630 opcode
= aco_opcode::image_sample_lz
;
8632 opcode
= aco_opcode::image_sample_l
;
8636 if (instr
->op
== nir_texop_tg4
) {
8638 opcode
= aco_opcode::image_gather4_lz_o
;
8640 opcode
= aco_opcode::image_gather4_c_lz_o
;
8642 opcode
= aco_opcode::image_gather4_lz
;
8644 opcode
= aco_opcode::image_gather4_c_lz
;
8646 } else if (instr
->op
== nir_texop_lod
) {
8647 opcode
= aco_opcode::image_get_lod
;
8650 /* we don't need the bias, sample index, compare value or offset to be
8651 * computed in WQM but if the p_create_vector copies the coordinates, then it
8652 * needs to be in WQM */
8653 if (ctx
->stage
== fragment_fs
&&
8654 !has_derivs
&& !has_lod
&& !level_zero
&&
8655 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8656 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8657 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8659 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8660 tex
->operands
[0] = Operand(resource
);
8661 tex
->operands
[1] = Operand(sampler
);
8662 tex
->operands
[2] = Operand(arg
);
8666 tex
->definitions
[0] = Definition(tmp_dst
);
8667 tex
->can_reorder
= true;
8668 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8670 if (tg4_integer_cube_workaround
) {
8671 assert(tmp_dst
.id() != dst
.id());
8672 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8674 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8676 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8677 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8679 if (stype
== GLSL_TYPE_UINT
)
8680 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8682 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8683 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8685 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8686 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8687 val
[0], val
[1], val
[2], val
[3]);
8689 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8690 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8695 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8697 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8698 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8699 return Operand(tmp
.regClass());
8701 return Operand(tmp
);
8704 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8706 aco_ptr
<Pseudo_instruction
> phi
;
8707 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8708 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8710 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8711 logical
|= ctx
->block
->kind
& block_kind_merge
;
8712 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8714 /* we want a sorted list of sources, since the predecessor list is also sorted */
8715 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8716 nir_foreach_phi_src(src
, instr
)
8717 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8719 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8720 unsigned num_operands
= 0;
8721 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8722 unsigned num_defined
= 0;
8723 unsigned cur_pred_idx
= 0;
8724 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8725 if (cur_pred_idx
< preds
.size()) {
8726 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8727 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8728 unsigned skipped
= 0;
8729 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8731 if (cur_pred_idx
+ skipped
< preds
.size()) {
8732 for (unsigned i
= 0; i
< skipped
; i
++)
8733 operands
[num_operands
++] = Operand(dst
.regClass());
8734 cur_pred_idx
+= skipped
;
8739 /* Handle missing predecessors at the end. This shouldn't happen with loop
8740 * headers and we can't ignore these sources for loop header phis. */
8741 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8744 Operand op
= get_phi_operand(ctx
, src
.second
);
8745 operands
[num_operands
++] = op
;
8746 num_defined
+= !op
.isUndefined();
8748 /* handle block_kind_continue_or_break at loop exit blocks */
8749 while (cur_pred_idx
++ < preds
.size())
8750 operands
[num_operands
++] = Operand(dst
.regClass());
8752 /* If the loop ends with a break, still add a linear continue edge in case
8753 * that break is divergent or continue_or_break is used. We'll either remove
8754 * this operand later in visit_loop() if it's not necessary or replace the
8755 * undef with something correct. */
8756 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8757 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8758 nir_block
*last
= nir_loop_last_block(loop
);
8759 if (last
->successors
[0] != instr
->instr
.block
)
8760 operands
[num_operands
++] = Operand(RegClass());
8763 if (num_defined
== 0) {
8764 Builder
bld(ctx
->program
, ctx
->block
);
8765 if (dst
.regClass() == s1
) {
8766 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8767 } else if (dst
.regClass() == v1
) {
8768 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8770 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8771 for (unsigned i
= 0; i
< dst
.size(); i
++)
8772 vec
->operands
[i
] = Operand(0u);
8773 vec
->definitions
[0] = Definition(dst
);
8774 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8779 /* we can use a linear phi in some cases if one src is undef */
8780 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8781 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8783 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8784 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8785 assert(invert
->kind
& block_kind_invert
);
8787 unsigned then_block
= invert
->linear_preds
[0];
8789 Block
* insert_block
= NULL
;
8790 for (unsigned i
= 0; i
< num_operands
; i
++) {
8791 Operand op
= operands
[i
];
8792 if (op
.isUndefined())
8794 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8795 phi
->operands
[0] = op
;
8798 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8799 phi
->operands
[1] = Operand(dst
.regClass());
8800 phi
->definitions
[0] = Definition(dst
);
8801 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8805 /* try to scalarize vector phis */
8806 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8807 // TODO: scalarize linear phis on divergent ifs
8808 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8809 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8810 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8811 Operand src
= operands
[i
];
8812 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8813 can_scalarize
= false;
8815 if (can_scalarize
) {
8816 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8817 assert(dst
.size() % num_components
== 0);
8818 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8820 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8821 for (unsigned k
= 0; k
< num_components
; k
++) {
8822 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8823 for (unsigned i
= 0; i
< num_operands
; i
++) {
8824 Operand src
= operands
[i
];
8825 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
8827 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
8828 phi
->definitions
[0] = Definition(phi_dst
);
8829 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8830 new_vec
[k
] = phi_dst
;
8831 vec
->operands
[k
] = Operand(phi_dst
);
8833 vec
->definitions
[0] = Definition(dst
);
8834 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8835 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
8840 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
8841 for (unsigned i
= 0; i
< num_operands
; i
++)
8842 phi
->operands
[i
] = operands
[i
];
8843 phi
->definitions
[0] = Definition(dst
);
8844 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
8848 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
8850 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
8852 assert(dst
.type() == RegType::sgpr
);
8854 if (dst
.size() == 1) {
8855 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
8857 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8858 for (unsigned i
= 0; i
< dst
.size(); i
++)
8859 vec
->operands
[i
] = Operand(0u);
8860 vec
->definitions
[0] = Definition(dst
);
8861 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8865 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
8867 Builder
bld(ctx
->program
, ctx
->block
);
8868 Block
*logical_target
;
8869 append_logical_end(ctx
->block
);
8870 unsigned idx
= ctx
->block
->index
;
8872 switch (instr
->type
) {
8873 case nir_jump_break
:
8874 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
8875 add_logical_edge(idx
, logical_target
);
8876 ctx
->block
->kind
|= block_kind_break
;
8878 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
8879 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
8880 /* uniform break - directly jump out of the loop */
8881 ctx
->block
->kind
|= block_kind_uniform
;
8882 ctx
->cf_info
.has_branch
= true;
8883 bld
.branch(aco_opcode::p_branch
);
8884 add_linear_edge(idx
, logical_target
);
8887 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8888 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8890 case nir_jump_continue
:
8891 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8892 add_logical_edge(idx
, logical_target
);
8893 ctx
->block
->kind
|= block_kind_continue
;
8895 if (ctx
->cf_info
.parent_if
.is_divergent
) {
8896 /* for potential uniform breaks after this continue,
8897 we must ensure that they are handled correctly */
8898 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
8899 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
8900 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
8902 /* uniform continue - directly jump to the loop header */
8903 ctx
->block
->kind
|= block_kind_uniform
;
8904 ctx
->cf_info
.has_branch
= true;
8905 bld
.branch(aco_opcode::p_branch
);
8906 add_linear_edge(idx
, logical_target
);
8911 fprintf(stderr
, "Unknown NIR jump instr: ");
8912 nir_print_instr(&instr
->instr
, stderr
);
8913 fprintf(stderr
, "\n");
8917 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
8918 ctx
->cf_info
.exec_potentially_empty_break
= true;
8919 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
8922 /* remove critical edges from linear CFG */
8923 bld
.branch(aco_opcode::p_branch
);
8924 Block
* break_block
= ctx
->program
->create_and_insert_block();
8925 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8926 break_block
->kind
|= block_kind_uniform
;
8927 add_linear_edge(idx
, break_block
);
8928 /* the loop_header pointer might be invalidated by this point */
8929 if (instr
->type
== nir_jump_continue
)
8930 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
8931 add_linear_edge(break_block
->index
, logical_target
);
8932 bld
.reset(break_block
);
8933 bld
.branch(aco_opcode::p_branch
);
8935 Block
* continue_block
= ctx
->program
->create_and_insert_block();
8936 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
8937 add_linear_edge(idx
, continue_block
);
8938 append_logical_start(continue_block
);
8939 ctx
->block
= continue_block
;
8943 void visit_block(isel_context
*ctx
, nir_block
*block
)
8945 nir_foreach_instr(instr
, block
) {
8946 switch (instr
->type
) {
8947 case nir_instr_type_alu
:
8948 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
8950 case nir_instr_type_load_const
:
8951 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
8953 case nir_instr_type_intrinsic
:
8954 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
8956 case nir_instr_type_tex
:
8957 visit_tex(ctx
, nir_instr_as_tex(instr
));
8959 case nir_instr_type_phi
:
8960 visit_phi(ctx
, nir_instr_as_phi(instr
));
8962 case nir_instr_type_ssa_undef
:
8963 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
8965 case nir_instr_type_deref
:
8967 case nir_instr_type_jump
:
8968 visit_jump(ctx
, nir_instr_as_jump(instr
));
8971 fprintf(stderr
, "Unknown NIR instr type: ");
8972 nir_print_instr(instr
, stderr
);
8973 fprintf(stderr
, "\n");
8978 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
8979 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
8984 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
8985 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
8987 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
8988 RegClass rc
= vals
[0].regClass();
8990 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
8992 unsigned next_pred
= 1;
8994 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
8995 Block
& block
= ctx
->program
->blocks
[idx
];
8996 if (block
.loop_nest_depth
!= loop_nest_depth
) {
8997 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9001 if (block
.kind
& block_kind_continue
) {
9002 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9007 bool all_same
= true;
9008 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9009 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9013 val
= vals
[block
.linear_preds
[0] - first
];
9015 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9016 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9017 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9018 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9019 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9020 phi
->definitions
[0] = Definition(val
.getTemp());
9021 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9023 vals
[idx
- first
] = val
;
9026 return vals
[last
- first
];
9029 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9031 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9032 append_logical_end(ctx
->block
);
9033 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9034 Builder
bld(ctx
->program
, ctx
->block
);
9035 bld
.branch(aco_opcode::p_branch
);
9036 unsigned loop_preheader_idx
= ctx
->block
->index
;
9038 Block loop_exit
= Block();
9039 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9040 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9042 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9043 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9044 loop_header
->kind
|= block_kind_loop_header
;
9045 add_edge(loop_preheader_idx
, loop_header
);
9046 ctx
->block
= loop_header
;
9048 /* emit loop body */
9049 unsigned loop_header_idx
= loop_header
->index
;
9050 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9051 append_logical_start(ctx
->block
);
9052 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9054 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9055 if (!ctx
->cf_info
.has_branch
) {
9056 append_logical_end(ctx
->block
);
9057 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9058 /* Discards can result in code running with an empty exec mask.
9059 * This would result in divergent breaks not ever being taken. As a
9060 * workaround, break the loop when the loop mask is empty instead of
9061 * always continuing. */
9062 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9063 unsigned block_idx
= ctx
->block
->index
;
9065 /* create helper blocks to avoid critical edges */
9066 Block
*break_block
= ctx
->program
->create_and_insert_block();
9067 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9068 break_block
->kind
= block_kind_uniform
;
9069 bld
.reset(break_block
);
9070 bld
.branch(aco_opcode::p_branch
);
9071 add_linear_edge(block_idx
, break_block
);
9072 add_linear_edge(break_block
->index
, &loop_exit
);
9074 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9075 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9076 continue_block
->kind
= block_kind_uniform
;
9077 bld
.reset(continue_block
);
9078 bld
.branch(aco_opcode::p_branch
);
9079 add_linear_edge(block_idx
, continue_block
);
9080 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9082 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9083 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9084 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9086 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9087 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9088 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9090 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9093 bld
.reset(ctx
->block
);
9094 bld
.branch(aco_opcode::p_branch
);
9097 /* Fixup phis in loop header from unreachable blocks.
9098 * has_branch/has_divergent_branch also indicates if the loop ends with a
9099 * break/continue instruction, but we don't emit those if unreachable=true */
9101 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9102 bool linear
= ctx
->cf_info
.has_branch
;
9103 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9104 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9105 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9106 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9107 /* the last operand should be the one that needs to be removed */
9108 instr
->operands
.pop_back();
9109 } else if (!is_phi(instr
)) {
9115 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9116 * and the previous one shouldn't both happen at once because a break in the
9117 * merge block would get CSE'd */
9118 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9119 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9120 Operand vals
[num_vals
];
9121 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9122 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9123 if (ctx
->cf_info
.has_branch
)
9124 instr
->operands
.pop_back();
9126 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9127 } else if (!is_phi(instr
)) {
9133 ctx
->cf_info
.has_branch
= false;
9135 // TODO: if the loop has not a single exit, we must add one °°
9136 /* emit loop successor block */
9137 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9138 append_logical_start(ctx
->block
);
9141 // TODO: check if it is beneficial to not branch on continues
9142 /* trim linear phis in loop header */
9143 for (auto&& instr
: loop_entry
->instructions
) {
9144 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9145 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9146 new_phi
->definitions
[0] = instr
->definitions
[0];
9147 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9148 new_phi
->operands
[i
] = instr
->operands
[i
];
9149 /* check that the remaining operands are all the same */
9150 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9151 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9152 instr
.swap(new_phi
);
9153 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9162 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9166 append_logical_end(ctx
->block
);
9167 ctx
->block
->kind
|= block_kind_branch
;
9169 /* branch to linear then block */
9170 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9171 aco_ptr
<Pseudo_branch_instruction
> branch
;
9172 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9173 branch
->operands
[0] = Operand(cond
);
9174 ctx
->block
->instructions
.push_back(std::move(branch
));
9176 ic
->BB_if_idx
= ctx
->block
->index
;
9177 ic
->BB_invert
= Block();
9178 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9179 /* Invert blocks are intentionally not marked as top level because they
9180 * are not part of the logical cfg. */
9181 ic
->BB_invert
.kind
|= block_kind_invert
;
9182 ic
->BB_endif
= Block();
9183 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9184 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9186 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9187 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9188 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9189 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9190 ctx
->cf_info
.parent_if
.is_divergent
= true;
9192 /* divergent branches use cbranch_execz */
9193 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9194 ctx
->cf_info
.exec_potentially_empty_break
= false;
9195 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9197 /** emit logical then block */
9198 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9199 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9200 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9201 ctx
->block
= BB_then_logical
;
9202 append_logical_start(BB_then_logical
);
9205 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9207 Block
*BB_then_logical
= ctx
->block
;
9208 append_logical_end(BB_then_logical
);
9209 /* branch from logical then block to invert block */
9210 aco_ptr
<Pseudo_branch_instruction
> branch
;
9211 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9212 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9213 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9214 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9215 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9216 BB_then_logical
->kind
|= block_kind_uniform
;
9217 assert(!ctx
->cf_info
.has_branch
);
9218 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9219 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9221 /** emit linear then block */
9222 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9223 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9224 BB_then_linear
->kind
|= block_kind_uniform
;
9225 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9226 /* branch from linear then block to invert block */
9227 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9228 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9229 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9231 /** emit invert merge block */
9232 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9233 ic
->invert_idx
= ctx
->block
->index
;
9235 /* branch to linear else block (skip else) */
9236 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9237 branch
->operands
[0] = Operand(ic
->cond
);
9238 ctx
->block
->instructions
.push_back(std::move(branch
));
9240 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9241 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9242 ic
->exec_potentially_empty_break_depth_old
=
9243 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9244 /* divergent branches use cbranch_execz */
9245 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9246 ctx
->cf_info
.exec_potentially_empty_break
= false;
9247 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9249 /** emit logical else block */
9250 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9251 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9252 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9253 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9254 ctx
->block
= BB_else_logical
;
9255 append_logical_start(BB_else_logical
);
9258 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9260 Block
*BB_else_logical
= ctx
->block
;
9261 append_logical_end(BB_else_logical
);
9263 /* branch from logical else block to endif block */
9264 aco_ptr
<Pseudo_branch_instruction
> branch
;
9265 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9266 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9267 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9268 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9269 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9270 BB_else_logical
->kind
|= block_kind_uniform
;
9272 assert(!ctx
->cf_info
.has_branch
);
9273 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9276 /** emit linear else block */
9277 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9278 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9279 BB_else_linear
->kind
|= block_kind_uniform
;
9280 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9282 /* branch from linear else block to endif block */
9283 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9284 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9285 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9288 /** emit endif merge block */
9289 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9290 append_logical_start(ctx
->block
);
9293 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9294 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9295 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9296 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9297 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9298 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9299 !ctx
->cf_info
.parent_if
.is_divergent
) {
9300 ctx
->cf_info
.exec_potentially_empty_break
= false;
9301 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9303 /* uniform control flow never has an empty exec-mask */
9304 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9305 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9306 ctx
->cf_info
.exec_potentially_empty_break
= false;
9307 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9311 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9313 assert(cond
.regClass() == s1
);
9315 append_logical_end(ctx
->block
);
9316 ctx
->block
->kind
|= block_kind_uniform
;
9318 aco_ptr
<Pseudo_branch_instruction
> branch
;
9319 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9320 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9321 branch
->operands
[0] = Operand(cond
);
9322 branch
->operands
[0].setFixed(scc
);
9323 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9325 ic
->BB_if_idx
= ctx
->block
->index
;
9326 ic
->BB_endif
= Block();
9327 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9328 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9330 ctx
->cf_info
.has_branch
= false;
9331 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9333 /** emit then block */
9334 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9335 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9336 add_edge(ic
->BB_if_idx
, BB_then
);
9337 append_logical_start(BB_then
);
9338 ctx
->block
= BB_then
;
9341 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9343 Block
*BB_then
= ctx
->block
;
9345 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9346 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9348 if (!ic
->uniform_has_then_branch
) {
9349 append_logical_end(BB_then
);
9350 /* branch from then block to endif block */
9351 aco_ptr
<Pseudo_branch_instruction
> branch
;
9352 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9353 BB_then
->instructions
.emplace_back(std::move(branch
));
9354 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9355 if (!ic
->then_branch_divergent
)
9356 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9357 BB_then
->kind
|= block_kind_uniform
;
9360 ctx
->cf_info
.has_branch
= false;
9361 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9363 /** emit else block */
9364 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9365 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9366 add_edge(ic
->BB_if_idx
, BB_else
);
9367 append_logical_start(BB_else
);
9368 ctx
->block
= BB_else
;
9371 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9373 Block
*BB_else
= ctx
->block
;
9375 if (!ctx
->cf_info
.has_branch
) {
9376 append_logical_end(BB_else
);
9377 /* branch from then block to endif block */
9378 aco_ptr
<Pseudo_branch_instruction
> branch
;
9379 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9380 BB_else
->instructions
.emplace_back(std::move(branch
));
9381 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9382 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9383 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9384 BB_else
->kind
|= block_kind_uniform
;
9387 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9388 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9390 /** emit endif merge block */
9391 if (!ctx
->cf_info
.has_branch
) {
9392 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9393 append_logical_start(ctx
->block
);
9397 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9399 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9400 Builder
bld(ctx
->program
, ctx
->block
);
9401 aco_ptr
<Pseudo_branch_instruction
> branch
;
9404 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9406 * Uniform conditionals are represented in the following way*) :
9408 * The linear and logical CFG:
9411 * BB_THEN (logical) BB_ELSE (logical)
9415 * *) Exceptions may be due to break and continue statements within loops
9416 * If a break/continue happens within uniform control flow, it branches
9417 * to the loop exit/entry block. Otherwise, it branches to the next
9421 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9422 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9423 cond
= bool_to_scalar_condition(ctx
, cond
);
9425 begin_uniform_if_then(ctx
, &ic
, cond
);
9426 visit_cf_list(ctx
, &if_stmt
->then_list
);
9428 begin_uniform_if_else(ctx
, &ic
);
9429 visit_cf_list(ctx
, &if_stmt
->else_list
);
9431 end_uniform_if(ctx
, &ic
);
9433 return !ctx
->cf_info
.has_branch
;
9434 } else { /* non-uniform condition */
9436 * To maintain a logical and linear CFG without critical edges,
9437 * non-uniform conditionals are represented in the following way*) :
9442 * BB_THEN (logical) BB_THEN (linear)
9444 * BB_INVERT (linear)
9446 * BB_ELSE (logical) BB_ELSE (linear)
9453 * BB_THEN (logical) BB_ELSE (logical)
9457 * *) Exceptions may be due to break and continue statements within loops
9460 begin_divergent_if_then(ctx
, &ic
, cond
);
9461 visit_cf_list(ctx
, &if_stmt
->then_list
);
9463 begin_divergent_if_else(ctx
, &ic
);
9464 visit_cf_list(ctx
, &if_stmt
->else_list
);
9466 end_divergent_if(ctx
, &ic
);
9472 static bool visit_cf_list(isel_context
*ctx
,
9473 struct exec_list
*list
)
9475 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9476 switch (node
->type
) {
9477 case nir_cf_node_block
:
9478 visit_block(ctx
, nir_cf_node_as_block(node
));
9480 case nir_cf_node_if
:
9481 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9484 case nir_cf_node_loop
:
9485 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9488 unreachable("unimplemented cf list type");
9494 static void create_null_export(isel_context
*ctx
)
9496 /* Some shader stages always need to have exports.
9497 * So when there is none, we need to add a null export.
9500 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9501 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9502 Builder
bld(ctx
->program
, ctx
->block
);
9503 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9504 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9507 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9509 assert(ctx
->stage
== vertex_vs
||
9510 ctx
->stage
== tess_eval_vs
||
9511 ctx
->stage
== gs_copy_vs
||
9512 ctx
->stage
== ngg_vertex_gs
||
9513 ctx
->stage
== ngg_tess_eval_gs
);
9515 int offset
= (ctx
->stage
& sw_tes
)
9516 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9517 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9518 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9519 if (!is_pos
&& !mask
)
9521 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9523 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9524 exp
->enabled_mask
= mask
;
9525 for (unsigned i
= 0; i
< 4; ++i
) {
9526 if (mask
& (1 << i
))
9527 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9529 exp
->operands
[i
] = Operand(v1
);
9531 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9532 * Setting valid_mask=1 prevents it and has no other effect.
9534 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9536 exp
->compressed
= false;
9538 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9540 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9541 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9546 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9548 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9549 exp
->enabled_mask
= 0;
9550 for (unsigned i
= 0; i
< 4; ++i
)
9551 exp
->operands
[i
] = Operand(v1
);
9552 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9553 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9554 exp
->enabled_mask
|= 0x1;
9556 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9557 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9558 exp
->enabled_mask
|= 0x4;
9560 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9561 if (ctx
->options
->chip_class
< GFX9
) {
9562 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9563 exp
->enabled_mask
|= 0x8;
9565 Builder
bld(ctx
->program
, ctx
->block
);
9567 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9568 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9569 if (exp
->operands
[2].isTemp())
9570 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9572 exp
->operands
[2] = Operand(out
);
9573 exp
->enabled_mask
|= 0x4;
9576 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9578 exp
->compressed
= false;
9579 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9580 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9583 static void create_export_phis(isel_context
*ctx
)
9585 /* Used when exports are needed, but the output temps are defined in a preceding block.
9586 * This function will set up phis in order to access the outputs in the next block.
9589 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9590 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9591 ctx
->block
->instructions
.pop_back();
9593 Builder
bld(ctx
->program
, ctx
->block
);
9595 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9596 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9597 for (unsigned i
= 0; i
< 4; ++i
) {
9598 if (!(mask
& (1 << i
)))
9601 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9602 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9603 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9607 bld
.insert(std::move(logical_start
));
9610 static void create_vs_exports(isel_context
*ctx
)
9612 assert(ctx
->stage
== vertex_vs
||
9613 ctx
->stage
== tess_eval_vs
||
9614 ctx
->stage
== gs_copy_vs
||
9615 ctx
->stage
== ngg_vertex_gs
||
9616 ctx
->stage
== ngg_tess_eval_gs
);
9618 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9619 ? &ctx
->program
->info
->tes
.outinfo
9620 : &ctx
->program
->info
->vs
.outinfo
;
9622 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9623 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9624 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9627 if (ctx
->options
->key
.has_multiview_view_index
) {
9628 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9629 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9632 /* the order these position exports are created is important */
9634 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9635 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9636 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9637 exported_pos
= true;
9639 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9640 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9641 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9642 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9644 if (ctx
->export_clip_dists
) {
9645 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9646 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9647 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9648 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9651 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9652 if (i
< VARYING_SLOT_VAR0
&&
9653 i
!= VARYING_SLOT_LAYER
&&
9654 i
!= VARYING_SLOT_PRIMITIVE_ID
)
9657 export_vs_varying(ctx
, i
, false, NULL
);
9661 create_null_export(ctx
);
9664 static bool export_fs_mrt_z(isel_context
*ctx
)
9666 Builder
bld(ctx
->program
, ctx
->block
);
9667 unsigned enabled_channels
= 0;
9671 for (unsigned i
= 0; i
< 4; ++i
) {
9672 values
[i
] = Operand(v1
);
9675 /* Both stencil and sample mask only need 16-bits. */
9676 if (!ctx
->program
->info
->ps
.writes_z
&&
9677 (ctx
->program
->info
->ps
.writes_stencil
||
9678 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9679 compr
= true; /* COMPR flag */
9681 if (ctx
->program
->info
->ps
.writes_stencil
) {
9682 /* Stencil should be in X[23:16]. */
9683 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9684 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9685 enabled_channels
|= 0x3;
9688 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9689 /* SampleMask should be in Y[15:0]. */
9690 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9691 enabled_channels
|= 0xc;
9694 if (ctx
->program
->info
->ps
.writes_z
) {
9695 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9696 enabled_channels
|= 0x1;
9699 if (ctx
->program
->info
->ps
.writes_stencil
) {
9700 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9701 enabled_channels
|= 0x2;
9704 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9705 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9706 enabled_channels
|= 0x4;
9710 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9711 * writemask component.
9713 if (ctx
->options
->chip_class
== GFX6
&&
9714 ctx
->options
->family
!= CHIP_OLAND
&&
9715 ctx
->options
->family
!= CHIP_HAINAN
) {
9716 enabled_channels
|= 0x1;
9719 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9720 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9725 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9727 Builder
bld(ctx
->program
, ctx
->block
);
9728 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9731 for (unsigned i
= 0; i
< 4; ++i
) {
9732 if (write_mask
& (1 << i
)) {
9733 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9735 values
[i
] = Operand(v1
);
9739 unsigned target
, col_format
;
9740 unsigned enabled_channels
= 0;
9741 aco_opcode compr_op
= (aco_opcode
)0;
9743 slot
-= FRAG_RESULT_DATA0
;
9744 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9745 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9747 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9748 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9752 case V_028714_SPI_SHADER_ZERO
:
9753 enabled_channels
= 0; /* writemask */
9754 target
= V_008DFC_SQ_EXP_NULL
;
9757 case V_028714_SPI_SHADER_32_R
:
9758 enabled_channels
= 1;
9761 case V_028714_SPI_SHADER_32_GR
:
9762 enabled_channels
= 0x3;
9765 case V_028714_SPI_SHADER_32_AR
:
9766 if (ctx
->options
->chip_class
>= GFX10
) {
9767 /* Special case: on GFX10, the outputs are different for 32_AR */
9768 enabled_channels
= 0x3;
9769 values
[1] = values
[3];
9770 values
[3] = Operand(v1
);
9772 enabled_channels
= 0x9;
9776 case V_028714_SPI_SHADER_FP16_ABGR
:
9777 enabled_channels
= 0x5;
9778 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9781 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9782 enabled_channels
= 0x5;
9783 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9786 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9787 enabled_channels
= 0x5;
9788 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
9791 case V_028714_SPI_SHADER_UINT16_ABGR
: {
9792 enabled_channels
= 0x5;
9793 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
9794 if (is_int8
|| is_int10
) {
9796 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
9797 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9799 for (unsigned i
= 0; i
< 4; i
++) {
9800 if ((write_mask
>> i
) & 1) {
9801 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
9802 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
9810 case V_028714_SPI_SHADER_SINT16_ABGR
:
9811 enabled_channels
= 0x5;
9812 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
9813 if (is_int8
|| is_int10
) {
9815 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
9816 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
9817 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
9818 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
9820 for (unsigned i
= 0; i
< 4; i
++) {
9821 if ((write_mask
>> i
) & 1) {
9822 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
9823 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
9825 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
9826 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
9833 case V_028714_SPI_SHADER_32_ABGR
:
9834 enabled_channels
= 0xF;
9841 if (target
== V_008DFC_SQ_EXP_NULL
)
9844 if ((bool) compr_op
) {
9845 for (int i
= 0; i
< 2; i
++) {
9846 /* check if at least one of the values to be compressed is enabled */
9847 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
9849 enabled_channels
|= enabled
<< (i
*2);
9850 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
9851 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
9852 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
9854 values
[i
] = Operand(v1
);
9857 values
[2] = Operand(v1
);
9858 values
[3] = Operand(v1
);
9860 for (int i
= 0; i
< 4; i
++)
9861 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
9864 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9865 enabled_channels
, target
, (bool) compr_op
);
9869 static void create_fs_exports(isel_context
*ctx
)
9871 bool exported
= false;
9873 /* Export depth, stencil and sample mask. */
9874 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
9875 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
9876 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
9877 exported
|= export_fs_mrt_z(ctx
);
9879 /* Export all color render targets. */
9880 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
9881 if (ctx
->outputs
.mask
[i
])
9882 exported
|= export_fs_mrt_color(ctx
, i
);
9885 create_null_export(ctx
);
9888 static void write_tcs_tess_factors(isel_context
*ctx
)
9890 unsigned outer_comps
;
9891 unsigned inner_comps
;
9893 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
9910 Builder
bld(ctx
->program
, ctx
->block
);
9912 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
9913 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
9914 bld
.sopp(aco_opcode::s_barrier
);
9916 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
9917 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
9919 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
9920 if_context ic_invocation_id_is_zero
;
9921 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
9922 bld
.reset(ctx
->block
);
9924 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
9926 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
9927 unsigned stride
= inner_comps
+ outer_comps
;
9928 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
9932 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
9934 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
9936 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9937 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
9938 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
9940 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
9941 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
9943 for (unsigned i
= 0; i
< outer_comps
; ++i
)
9944 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
9945 for (unsigned i
= 0; i
< inner_comps
; ++i
)
9946 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
9949 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
9950 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
9951 Temp byte_offset
= bld
.v_mul_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
9952 unsigned tf_const_offset
= 0;
9954 if (ctx
->program
->chip_class
<= GFX8
) {
9955 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
9956 if_context ic_rel_patch_id_is_zero
;
9957 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
9958 bld
.reset(ctx
->block
);
9960 /* Store the dynamic HS control word. */
9961 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
9962 bld
.mubuf(aco_opcode::buffer_store_dword
,
9963 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
9964 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9965 /* disable_wqm */ false, /* glc */ true);
9966 tf_const_offset
+= 4;
9968 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
9969 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
9970 bld
.reset(ctx
->block
);
9973 assert(stride
== 2 || stride
== 4 || stride
== 6);
9974 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
9975 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
9977 /* Store to offchip for TES to read - only if TES reads them */
9978 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
9979 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
9980 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
9982 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
9983 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
9985 if (likely(inner_comps
)) {
9986 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
9987 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
9991 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
9992 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
9995 static void emit_stream_output(isel_context
*ctx
,
9996 Temp
const *so_buffers
,
9997 Temp
const *so_write_offset
,
9998 const struct radv_stream_output
*output
)
10000 unsigned num_comps
= util_bitcount(output
->component_mask
);
10001 unsigned writemask
= (1 << num_comps
) - 1;
10002 unsigned loc
= output
->location
;
10003 unsigned buf
= output
->buffer
;
10005 assert(num_comps
&& num_comps
<= 4);
10006 if (!num_comps
|| num_comps
> 4)
10009 unsigned start
= ffs(output
->component_mask
) - 1;
10012 bool all_undef
= true;
10013 assert(ctx
->stage
== vertex_vs
|| ctx
->stage
== gs_copy_vs
);
10014 for (unsigned i
= 0; i
< num_comps
; i
++) {
10015 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10016 all_undef
= all_undef
&& !out
[i
].id();
10021 while (writemask
) {
10023 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10024 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10025 /* GFX6 doesn't support storing vec3, split it. */
10026 writemask
|= 1u << (start
+ 2);
10030 unsigned offset
= output
->offset
+ start
* 4;
10032 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10033 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10034 for (int i
= 0; i
< count
; ++i
)
10035 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10036 vec
->definitions
[0] = Definition(write_data
);
10037 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10042 opcode
= aco_opcode::buffer_store_dword
;
10045 opcode
= aco_opcode::buffer_store_dwordx2
;
10048 opcode
= aco_opcode::buffer_store_dwordx3
;
10051 opcode
= aco_opcode::buffer_store_dwordx4
;
10054 unreachable("Unsupported dword count.");
10057 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10058 store
->operands
[0] = Operand(so_buffers
[buf
]);
10059 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10060 store
->operands
[2] = Operand((uint32_t) 0);
10061 store
->operands
[3] = Operand(write_data
);
10062 if (offset
> 4095) {
10063 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10064 Builder
bld(ctx
->program
, ctx
->block
);
10065 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10067 store
->offset
= offset
;
10069 store
->offen
= true;
10071 store
->dlc
= false;
10073 store
->can_reorder
= true;
10074 ctx
->block
->instructions
.emplace_back(std::move(store
));
10078 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10080 Builder
bld(ctx
->program
, ctx
->block
);
10082 Temp so_buffers
[4];
10083 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10084 for (unsigned i
= 0; i
< 4; i
++) {
10085 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10089 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10090 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10093 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10094 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10096 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10098 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10101 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10103 bld
.reset(ctx
->block
);
10105 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10107 Temp so_write_offset
[4];
10109 for (unsigned i
= 0; i
< 4; i
++) {
10110 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10115 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10116 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10117 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10118 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10120 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10122 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10123 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10124 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10125 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10129 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10130 struct radv_stream_output
*output
=
10131 &ctx
->program
->info
->so
.outputs
[i
];
10132 if (stream
!= output
->stream
)
10135 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10138 begin_divergent_if_else(ctx
, &ic
);
10139 end_divergent_if(ctx
, &ic
);
10142 } /* end namespace */
10144 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10146 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10147 Builder
bld(ctx
->program
, ctx
->block
);
10148 constexpr unsigned hs_idx
= 1u;
10149 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10150 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10151 Operand((8u << 16) | (hs_idx
* 8u)));
10152 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10154 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10156 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10157 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10158 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10159 ls_has_nonzero_hs_threads
);
10160 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10161 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10162 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10163 ls_has_nonzero_hs_threads
);
10164 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10165 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10166 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10167 ls_has_nonzero_hs_threads
);
10169 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10170 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10171 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10174 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10176 /* Split all arguments except for the first (ring_offsets) and the last
10177 * (exec) so that the dead channels don't stay live throughout the program.
10179 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10180 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10181 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10182 startpgm
->definitions
[i
].regClass().size());
10187 void handle_bc_optimize(isel_context
*ctx
)
10189 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10190 Builder
bld(ctx
->program
, ctx
->block
);
10191 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10192 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10193 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10194 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10195 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10196 if (uses_center
&& uses_centroid
) {
10197 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10198 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10200 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10202 for (unsigned i
= 0; i
< 2; i
++) {
10203 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10204 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10205 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10206 persp_centroid
, persp_center
, sel
);
10208 ctx
->persp_centroid
= bld
.tmp(v2
);
10209 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10210 Operand(new_coord
[0]), Operand(new_coord
[1]));
10211 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10214 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10216 for (unsigned i
= 0; i
< 2; i
++) {
10217 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10218 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10219 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10220 linear_centroid
, linear_center
, sel
);
10222 ctx
->linear_centroid
= bld
.tmp(v2
);
10223 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10224 Operand(new_coord
[0]), Operand(new_coord
[1]));
10225 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10230 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10232 Program
*program
= ctx
->program
;
10234 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10236 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10237 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10238 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10239 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10240 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10242 program
->next_fp_mode
.must_flush_denorms32
=
10243 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10244 program
->next_fp_mode
.must_flush_denorms16_64
=
10245 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10246 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10248 program
->next_fp_mode
.care_about_round32
=
10249 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10251 program
->next_fp_mode
.care_about_round16_64
=
10252 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10253 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10255 /* default to preserving fp16 and fp64 denorms, since it's free */
10256 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10257 program
->next_fp_mode
.denorm16_64
= 0;
10259 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10261 /* preserving fp32 denorms is expensive, so only do it if asked */
10262 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10263 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10265 program
->next_fp_mode
.denorm32
= 0;
10267 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10268 program
->next_fp_mode
.round32
= fp_round_tz
;
10270 program
->next_fp_mode
.round32
= fp_round_ne
;
10272 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10273 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10275 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10277 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10280 void cleanup_cfg(Program
*program
)
10282 /* create linear_succs/logical_succs */
10283 for (Block
& BB
: program
->blocks
) {
10284 for (unsigned idx
: BB
.linear_preds
)
10285 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10286 for (unsigned idx
: BB
.logical_preds
)
10287 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10291 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10293 Builder
bld(ctx
->program
, ctx
->block
);
10295 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10296 Temp count
= i
== 0
10297 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10298 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10299 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10301 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10304 if (ctx
->program
->wave_size
== 64) {
10305 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10306 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10307 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10309 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10310 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10316 bool ngg_early_prim_export(isel_context
*ctx
)
10318 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10322 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10324 Builder
bld(ctx
->program
, ctx
->block
);
10326 /* Get the id of the current wave within the threadgroup (workgroup) */
10327 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10328 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10330 /* Execute the following code only on the first wave (wave id 0),
10331 * use the SCC def to tell if the wave id is zero or not.
10333 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10335 begin_uniform_if_then(ctx
, &ic
, cond
);
10336 begin_uniform_if_else(ctx
, &ic
);
10337 bld
.reset(ctx
->block
);
10339 /* Number of vertices output by VS/TES */
10340 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10341 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10342 /* Number of primitives output by VS/TES */
10343 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10344 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10346 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10347 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10348 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10350 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10351 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10353 end_uniform_if(ctx
, &ic
);
10356 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10358 Builder
bld(ctx
->program
, ctx
->block
);
10360 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10361 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10364 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10367 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10368 assert(vtxindex
[i
].id());
10371 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10375 /* The initial edge flag is always false in tess eval shaders. */
10376 if (ctx
->stage
== ngg_vertex_gs
) {
10377 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10378 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10382 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10387 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10389 Builder
bld(ctx
->program
, ctx
->block
);
10390 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10392 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10393 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10394 false /* compressed */, true/* done */, false /* valid mask */);
10397 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10399 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10400 * These must always come before VS exports.
10402 * It is recommended to do these as early as possible. They can be at the beginning when
10403 * there is no SW GS and the shader doesn't write edge flags.
10407 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10408 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10410 Builder
bld(ctx
->program
, ctx
->block
);
10411 constexpr unsigned max_vertices_per_primitive
= 3;
10412 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10414 if (ctx
->stage
== ngg_vertex_gs
) {
10415 /* TODO: optimize for points & lines */
10416 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10417 if (ctx
->shader
->info
.tess
.point_mode
)
10418 num_vertices_per_primitive
= 1;
10419 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10420 num_vertices_per_primitive
= 2;
10422 unreachable("Unsupported NGG shader stage");
10425 Temp vtxindex
[max_vertices_per_primitive
];
10426 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10427 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10428 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10429 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10430 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10431 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10432 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10433 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10435 /* Export primitive data to the index buffer. */
10436 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10438 /* Export primitive ID. */
10439 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10440 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10441 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10442 Temp provoking_vtx_index
= vtxindex
[0];
10443 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10445 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10448 begin_divergent_if_else(ctx
, &ic
);
10449 end_divergent_if(ctx
, &ic
);
10452 void ngg_emit_nogs_output(isel_context
*ctx
)
10454 /* Emits NGG GS output, for stages that don't have SW GS. */
10457 Builder
bld(ctx
->program
, ctx
->block
);
10458 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10460 /* NGG streamout is currently disabled by default. */
10461 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10463 if (late_prim_export
) {
10464 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10465 create_export_phis(ctx
);
10466 /* Do what we need to do in the GS threads. */
10467 ngg_emit_nogs_gsthreads(ctx
);
10469 /* What comes next should be executed on ES threads. */
10470 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10471 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10472 bld
.reset(ctx
->block
);
10475 /* Export VS outputs */
10476 ctx
->block
->kind
|= block_kind_export_end
;
10477 create_vs_exports(ctx
);
10479 /* Export primitive ID */
10480 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10483 if (ctx
->stage
== ngg_vertex_gs
) {
10484 /* Wait for GS threads to store primitive ID in LDS. */
10485 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10486 bld
.sopp(aco_opcode::s_barrier
);
10488 /* Calculate LDS address where the GS threads stored the primitive ID. */
10489 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10490 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10491 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10492 Temp wave_id_mul
= bld
.v_mul_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10493 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10494 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10496 /* Load primitive ID from LDS. */
10497 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10498 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10499 /* TES: Just use the patch ID as the primitive ID. */
10500 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10502 unreachable("unsupported NGG shader stage.");
10505 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10506 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10508 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10511 if (late_prim_export
) {
10512 begin_divergent_if_else(ctx
, &ic
);
10513 end_divergent_if(ctx
, &ic
);
10514 bld
.reset(ctx
->block
);
10518 void select_program(Program
*program
,
10519 unsigned shader_count
,
10520 struct nir_shader
*const *shaders
,
10521 ac_shader_config
* config
,
10522 struct radv_shader_args
*args
)
10524 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10525 if_context ic_merged_wave_info
;
10526 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10528 for (unsigned i
= 0; i
< shader_count
; i
++) {
10529 nir_shader
*nir
= shaders
[i
];
10530 init_context(&ctx
, nir
);
10532 setup_fp_mode(&ctx
, nir
);
10535 /* needs to be after init_context() for FS */
10536 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10537 append_logical_start(ctx
.block
);
10539 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10540 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10542 split_arguments(&ctx
, startpgm
);
10546 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10548 if (ngg_early_prim_export(&ctx
))
10549 ngg_emit_nogs_gsthreads(&ctx
);
10552 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10553 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10554 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10555 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10556 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10557 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10558 ctx
.stage
== tess_eval_geometry_gs
));
10560 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10561 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10562 if (check_merged_wave_info
) {
10563 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10564 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10568 Builder
bld(ctx
.program
, ctx
.block
);
10570 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10571 bld
.sopp(aco_opcode::s_barrier
);
10573 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10574 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10576 } else if (ctx
.stage
== geometry_gs
)
10577 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10579 if (ctx
.stage
== fragment_fs
)
10580 handle_bc_optimize(&ctx
);
10582 visit_cf_list(&ctx
, &func
->body
);
10584 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10585 emit_streamout(&ctx
, 0);
10587 if (ctx
.stage
& hw_vs
) {
10588 create_vs_exports(&ctx
);
10589 ctx
.block
->kind
|= block_kind_export_end
;
10590 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10591 ngg_emit_nogs_output(&ctx
);
10592 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10593 Builder
bld(ctx
.program
, ctx
.block
);
10594 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10595 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10596 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10597 write_tcs_tess_factors(&ctx
);
10600 if (ctx
.stage
== fragment_fs
) {
10601 create_fs_exports(&ctx
);
10602 ctx
.block
->kind
|= block_kind_export_end
;
10605 if (endif_merged_wave_info
) {
10606 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10607 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10610 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10611 ngg_emit_nogs_output(&ctx
);
10613 ralloc_free(ctx
.divergent_vals
);
10615 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10616 /* Outputs of the previous stage are inputs to the next stage */
10617 ctx
.inputs
= ctx
.outputs
;
10618 ctx
.outputs
= shader_io_state();
10622 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10624 append_logical_end(ctx
.block
);
10625 ctx
.block
->kind
|= block_kind_uniform
;
10626 Builder
bld(ctx
.program
, ctx
.block
);
10627 if (ctx
.program
->wb_smem_l1_on_end
)
10628 bld
.smem(aco_opcode::s_dcache_wb
, false);
10629 bld
.sopp(aco_opcode::s_endpgm
);
10631 cleanup_cfg(program
);
10634 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10635 ac_shader_config
* config
,
10636 struct radv_shader_args
*args
)
10638 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10640 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10641 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10642 program
->next_fp_mode
.must_flush_denorms32
= false;
10643 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10644 program
->next_fp_mode
.care_about_round32
= false;
10645 program
->next_fp_mode
.care_about_round16_64
= false;
10646 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10647 program
->next_fp_mode
.denorm32
= 0;
10648 program
->next_fp_mode
.round32
= fp_round_ne
;
10649 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10650 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10652 add_startpgm(&ctx
);
10653 append_logical_start(ctx
.block
);
10655 Builder
bld(ctx
.program
, ctx
.block
);
10657 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10659 Operand
stream_id(0u);
10660 if (args
->shader_info
->so
.num_outputs
)
10661 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10662 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10664 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10666 std::stack
<Block
> endif_blocks
;
10668 for (unsigned stream
= 0; stream
< 4; stream
++) {
10669 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10672 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10673 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10676 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10678 unsigned BB_if_idx
= ctx
.block
->index
;
10679 Block BB_endif
= Block();
10680 if (!stream_id
.isConstant()) {
10682 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10683 append_logical_end(ctx
.block
);
10684 ctx
.block
->kind
|= block_kind_uniform
;
10685 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10687 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10689 ctx
.block
= ctx
.program
->create_and_insert_block();
10690 add_edge(BB_if_idx
, ctx
.block
);
10691 bld
.reset(ctx
.block
);
10692 append_logical_start(ctx
.block
);
10695 unsigned offset
= 0;
10696 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10697 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10700 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10701 unsigned length
= util_last_bit(output_usage_mask
);
10702 for (unsigned j
= 0; j
< length
; ++j
) {
10703 if (!(output_usage_mask
& (1 << j
)))
10706 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10707 Temp voffset
= vtx_offset
;
10708 if (const_offset
>= 4096u) {
10709 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10710 const_offset
%= 4096u;
10713 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10714 mubuf
->definitions
[0] = bld
.def(v1
);
10715 mubuf
->operands
[0] = Operand(gsvs_ring
);
10716 mubuf
->operands
[1] = Operand(voffset
);
10717 mubuf
->operands
[2] = Operand(0u);
10718 mubuf
->offen
= true;
10719 mubuf
->offset
= const_offset
;
10722 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10723 mubuf
->barrier
= barrier_none
;
10724 mubuf
->can_reorder
= true;
10726 ctx
.outputs
.mask
[i
] |= 1 << j
;
10727 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10729 bld
.insert(std::move(mubuf
));
10735 if (args
->shader_info
->so
.num_outputs
) {
10736 emit_streamout(&ctx
, stream
);
10737 bld
.reset(ctx
.block
);
10741 create_vs_exports(&ctx
);
10742 ctx
.block
->kind
|= block_kind_export_end
;
10745 if (!stream_id
.isConstant()) {
10746 append_logical_end(ctx
.block
);
10748 /* branch from then block to endif block */
10749 bld
.branch(aco_opcode::p_branch
);
10750 add_edge(ctx
.block
->index
, &BB_endif
);
10751 ctx
.block
->kind
|= block_kind_uniform
;
10753 /* emit else block */
10754 ctx
.block
= ctx
.program
->create_and_insert_block();
10755 add_edge(BB_if_idx
, ctx
.block
);
10756 bld
.reset(ctx
.block
);
10757 append_logical_start(ctx
.block
);
10759 endif_blocks
.push(std::move(BB_endif
));
10763 while (!endif_blocks
.empty()) {
10764 Block BB_endif
= std::move(endif_blocks
.top());
10765 endif_blocks
.pop();
10767 Block
*BB_else
= ctx
.block
;
10769 append_logical_end(BB_else
);
10770 /* branch from else block to endif block */
10771 bld
.branch(aco_opcode::p_branch
);
10772 add_edge(BB_else
->index
, &BB_endif
);
10773 BB_else
->kind
|= block_kind_uniform
;
10775 /** emit endif merge block */
10776 ctx
.block
= program
->insert_block(std::move(BB_endif
));
10777 bld
.reset(ctx
.block
);
10778 append_logical_start(ctx
.block
);
10781 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10783 append_logical_end(ctx
.block
);
10784 ctx
.block
->kind
|= block_kind_uniform
;
10785 bld
.sopp(aco_opcode::s_endpgm
);
10787 cleanup_cfg(program
);