2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 if (ctx
->options
->chip_class
<= GFX7
) {
173 /* GFX6-7: there is no bpermute instruction */
174 Operand
index_op(index
);
175 Operand
input_data(data
);
176 index_op
.setLateKill(true);
177 input_data
.setLateKill(true);
179 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
180 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
181 /* GFX10 wave64 mode: emulate full-wave bpermute */
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
189 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
190 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
191 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
192 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
193 Operand
input_data(data
);
195 index_x4
.setLateKill(true);
196 input_data
.setLateKill(true);
197 same_half
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
201 /* GFX8-9 or GFX10 wave32: bpermute works normally */
202 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
203 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
207 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
209 if (val
.type() == RegType::sgpr
) {
210 Builder
bld(ctx
->program
, ctx
->block
);
211 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
213 assert(val
.type() == RegType::vgpr
);
217 //assumes a != 0xffffffff
218 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
221 Builder
bld(ctx
->program
, ctx
->block
);
223 if (util_is_power_of_two_or_zero(b
)) {
224 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
228 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
230 assert(info
.multiplier
<= 0xffffffff);
232 bool pre_shift
= info
.pre_shift
!= 0;
233 bool increment
= info
.increment
!= 0;
234 bool multiply
= true;
235 bool post_shift
= info
.post_shift
!= 0;
237 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
238 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
242 Temp pre_shift_dst
= a
;
244 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
245 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
248 Temp increment_dst
= pre_shift_dst
;
250 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
251 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
254 Temp multiply_dst
= increment_dst
;
256 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
257 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
258 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
262 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
266 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
268 Builder
bld(ctx
->program
, ctx
->block
);
269 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
273 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
275 /* no need to extract the whole vector */
276 if (src
.regClass() == dst_rc
) {
281 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
282 Builder
bld(ctx
->program
, ctx
->block
);
283 auto it
= ctx
->allocated_vec
.find(src
.id());
284 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
285 if (it
->second
[idx
].regClass() == dst_rc
) {
286 return it
->second
[idx
];
288 assert(!dst_rc
.is_subdword());
289 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
290 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
294 if (dst_rc
.is_subdword())
295 src
= as_vgpr(ctx
, src
);
297 if (src
.bytes() == dst_rc
.bytes()) {
299 return bld
.copy(bld
.def(dst_rc
), src
);
301 Temp dst
= bld
.tmp(dst_rc
);
302 emit_extract_vector(ctx
, src
, idx
, dst
);
307 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
309 if (num_components
== 1)
311 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
314 if (num_components
> vec_src
.size()) {
315 if (vec_src
.type() == RegType::sgpr
) {
316 /* should still help get_alu_src() */
317 emit_split_vector(ctx
, vec_src
, vec_src
.size());
320 /* sub-dword split */
321 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
323 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
325 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
326 split
->operands
[0] = Operand(vec_src
);
327 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
328 for (unsigned i
= 0; i
< num_components
; i
++) {
329 elems
[i
] = {ctx
->program
->allocateId(), rc
};
330 split
->definitions
[i
] = Definition(elems
[i
]);
332 ctx
->block
->instructions
.emplace_back(std::move(split
));
333 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
336 /* This vector expansion uses a mask to determine which elements in the new vector
337 * come from the original vector. The other elements are undefined. */
338 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
340 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
345 Builder
bld(ctx
->program
, ctx
->block
);
346 if (num_components
== 1) {
347 if (dst
.type() == RegType::sgpr
)
348 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
350 bld
.copy(Definition(dst
), vec_src
);
354 unsigned component_size
= dst
.size() / num_components
;
355 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
357 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
358 vec
->definitions
[0] = Definition(dst
);
360 for (unsigned i
= 0; i
< num_components
; i
++) {
361 if (mask
& (1 << i
)) {
362 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
363 if (dst
.type() == RegType::sgpr
)
364 src
= bld
.as_uniform(src
);
365 vec
->operands
[i
] = Operand(src
);
367 vec
->operands
[i
] = Operand(0u);
369 elems
[i
] = vec
->operands
[i
].getTemp();
371 ctx
->block
->instructions
.emplace_back(std::move(vec
));
372 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
375 /* adjust misaligned small bit size loads */
376 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
378 Builder
bld(ctx
->program
, ctx
->block
);
380 Temp select
= Temp();
381 if (offset
.isConstant()) {
382 assert(offset
.constantValue() && offset
.constantValue() < 4);
383 shift
= Operand(offset
.constantValue() * 8);
385 /* bit_offset = 8 * (offset & 0x3) */
386 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
387 select
= bld
.tmp(s1
);
388 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
391 if (vec
.size() == 1) {
392 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
393 } else if (vec
.size() == 2) {
394 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
395 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
397 emit_split_vector(ctx
, dst
, 2);
399 emit_extract_vector(ctx
, tmp
, 0, dst
);
400 } else if (vec
.size() == 4) {
401 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
402 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
403 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
404 if (select
!= Temp())
405 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
406 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
407 Temp mid
= bld
.tmp(s1
);
408 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
409 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
410 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
411 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
412 emit_split_vector(ctx
, dst
, 2);
416 /* this function trims subdword vectors:
417 * if dst is vgpr - split the src and create a shrunk version according to the mask.
418 * if dst is sgpr - split the src, but move the original to sgpr. */
419 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
421 assert(vec_src
.type() == RegType::vgpr
);
422 emit_split_vector(ctx
, vec_src
, num_components
);
424 Builder
bld(ctx
->program
, ctx
->block
);
425 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
426 unsigned component_size
= vec_src
.bytes() / num_components
;
427 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
430 for (unsigned i
= 0; i
< num_components
; i
++) {
432 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
435 if (dst
.type() == RegType::vgpr
) {
436 assert(dst
.bytes() == k
* component_size
);
437 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
438 for (unsigned i
= 0; i
< k
; i
++)
439 vec
->operands
[i
] = Operand(elems
[i
]);
440 vec
->definitions
[0] = Definition(dst
);
441 bld
.insert(std::move(vec
));
443 // TODO: alignbyte if mask doesn't start with 1?
445 assert(dst
.size() == vec_src
.size());
446 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
448 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
451 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
453 Builder
bld(ctx
->program
, ctx
->block
);
455 dst
= bld
.tmp(bld
.lm
);
457 assert(val
.regClass() == s1
);
458 assert(dst
.regClass() == bld
.lm
);
460 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
463 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
465 Builder
bld(ctx
->program
, ctx
->block
);
469 assert(val
.regClass() == bld
.lm
);
470 assert(dst
.regClass() == s1
);
472 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
473 Temp tmp
= bld
.tmp(s1
);
474 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
475 return emit_wqm(ctx
, tmp
, dst
);
478 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
480 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
481 return get_ssa_temp(ctx
, src
.src
.ssa
);
483 if (src
.src
.ssa
->num_components
== size
) {
484 bool identity_swizzle
= true;
485 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
486 if (src
.swizzle
[i
] != i
)
487 identity_swizzle
= false;
489 if (identity_swizzle
)
490 return get_ssa_temp(ctx
, src
.src
.ssa
);
493 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
494 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
495 assert(elem_size
> 0);
496 assert(vec
.bytes() % elem_size
== 0);
498 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
499 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
501 unsigned swizzle
= src
.swizzle
[0];
502 if (vec
.size() > 1) {
503 assert(src
.src
.ssa
->bit_size
== 16);
504 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
505 swizzle
= swizzle
& 1;
510 Temp dst
{ctx
->program
->allocateId(), s1
};
511 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 2)};
512 bfe
->operands
[0] = Operand(vec
);
513 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
514 bfe
->definitions
[0] = Definition(dst
);
515 bfe
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
516 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
520 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
522 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
525 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
526 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
527 for (unsigned i
= 0; i
< size
; ++i
) {
528 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
529 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
531 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
532 vec_instr
->definitions
[0] = Definition(dst
);
533 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
534 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
539 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
543 Builder
bld(ctx
->program
, ctx
->block
);
544 if (ptr
.type() == RegType::vgpr
)
545 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
546 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
547 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
550 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
552 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
553 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
554 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
555 sop2
->definitions
[0] = Definition(dst
);
557 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
558 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
561 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
562 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
564 Builder
bld(ctx
->program
, ctx
->block
);
565 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
566 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
567 if (src1
.type() == RegType::sgpr
) {
568 if (commutative
&& src0
.type() == RegType::vgpr
) {
573 src1
= as_vgpr(ctx
, src1
);
577 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
578 assert(dst
.size() == 1);
579 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
580 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
582 bld
.vop2(op
, Definition(dst
), src0
, src1
);
586 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
587 bool flush_denorms
= false)
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
591 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
593 /* ensure that the instruction has at most 1 sgpr operand
594 * The optimizer will inline constants for us */
595 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
596 src0
= as_vgpr(ctx
, src0
);
597 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
598 src1
= as_vgpr(ctx
, src1
);
599 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
600 src2
= as_vgpr(ctx
, src2
);
602 Builder
bld(ctx
->program
, ctx
->block
);
603 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
604 assert(dst
.size() == 1);
605 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
606 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
608 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
612 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
614 Builder
bld(ctx
->program
, ctx
->block
);
615 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
618 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
620 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
621 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
622 assert(src0
.size() == src1
.size());
624 aco_ptr
<Instruction
> vopc
;
625 if (src1
.type() == RegType::sgpr
) {
626 if (src0
.type() == RegType::vgpr
) {
627 /* to swap the operands, we might also have to change the opcode */
629 case aco_opcode::v_cmp_lt_f16
:
630 op
= aco_opcode::v_cmp_gt_f16
;
632 case aco_opcode::v_cmp_ge_f16
:
633 op
= aco_opcode::v_cmp_le_f16
;
635 case aco_opcode::v_cmp_lt_i16
:
636 op
= aco_opcode::v_cmp_gt_i16
;
638 case aco_opcode::v_cmp_ge_i16
:
639 op
= aco_opcode::v_cmp_le_i16
;
641 case aco_opcode::v_cmp_lt_u16
:
642 op
= aco_opcode::v_cmp_gt_u16
;
644 case aco_opcode::v_cmp_ge_u16
:
645 op
= aco_opcode::v_cmp_le_u16
;
647 case aco_opcode::v_cmp_lt_f32
:
648 op
= aco_opcode::v_cmp_gt_f32
;
650 case aco_opcode::v_cmp_ge_f32
:
651 op
= aco_opcode::v_cmp_le_f32
;
653 case aco_opcode::v_cmp_lt_i32
:
654 op
= aco_opcode::v_cmp_gt_i32
;
656 case aco_opcode::v_cmp_ge_i32
:
657 op
= aco_opcode::v_cmp_le_i32
;
659 case aco_opcode::v_cmp_lt_u32
:
660 op
= aco_opcode::v_cmp_gt_u32
;
662 case aco_opcode::v_cmp_ge_u32
:
663 op
= aco_opcode::v_cmp_le_u32
;
665 case aco_opcode::v_cmp_lt_f64
:
666 op
= aco_opcode::v_cmp_gt_f64
;
668 case aco_opcode::v_cmp_ge_f64
:
669 op
= aco_opcode::v_cmp_le_f64
;
671 case aco_opcode::v_cmp_lt_i64
:
672 op
= aco_opcode::v_cmp_gt_i64
;
674 case aco_opcode::v_cmp_ge_i64
:
675 op
= aco_opcode::v_cmp_le_i64
;
677 case aco_opcode::v_cmp_lt_u64
:
678 op
= aco_opcode::v_cmp_gt_u64
;
680 case aco_opcode::v_cmp_ge_u64
:
681 op
= aco_opcode::v_cmp_le_u64
;
683 default: /* eq and ne are commutative */
690 src1
= as_vgpr(ctx
, src1
);
694 Builder
bld(ctx
->program
, ctx
->block
);
695 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
698 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
700 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
701 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
702 Builder
bld(ctx
->program
, ctx
->block
);
704 assert(dst
.regClass() == bld
.lm
);
705 assert(src0
.type() == RegType::sgpr
);
706 assert(src1
.type() == RegType::sgpr
);
707 assert(src0
.regClass() == src1
.regClass());
709 /* Emit the SALU comparison instruction */
710 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
711 /* Turn the result into a per-lane bool */
712 bool_to_vector_condition(ctx
, cmp
, dst
);
715 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
716 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
718 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
719 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
720 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
721 nir_dest_is_divergent(instr
->dest
.dest
) ||
722 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
723 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
724 aco_opcode op
= use_valu
? v_op
: s_op
;
725 assert(op
!= aco_opcode::num_opcodes
);
726 assert(dst
.regClass() == ctx
->program
->lane_mask
);
729 emit_vopc_instruction(ctx
, instr
, op
, dst
);
731 emit_sopc_instruction(ctx
, instr
, op
, dst
);
734 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
736 Builder
bld(ctx
->program
, ctx
->block
);
737 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
738 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
740 assert(dst
.regClass() == bld
.lm
);
741 assert(src0
.regClass() == bld
.lm
);
742 assert(src1
.regClass() == bld
.lm
);
744 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
747 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
749 Builder
bld(ctx
->program
, ctx
->block
);
750 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
751 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
752 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
754 assert(cond
.regClass() == bld
.lm
);
756 if (dst
.type() == RegType::vgpr
) {
757 aco_ptr
<Instruction
> bcsel
;
758 if (dst
.size() == 1) {
759 then
= as_vgpr(ctx
, then
);
760 els
= as_vgpr(ctx
, els
);
762 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
763 } else if (dst
.size() == 2) {
764 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
765 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
766 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
767 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
769 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
770 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
772 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
774 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
775 nir_print_instr(&instr
->instr
, stderr
);
776 fprintf(stderr
, "\n");
781 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
782 assert(dst
.regClass() == bld
.lm
);
783 assert(then
.regClass() == bld
.lm
);
784 assert(els
.regClass() == bld
.lm
);
787 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
788 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
789 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
790 assert(dst
.size() == then
.size());
791 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
792 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
794 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
795 nir_print_instr(&instr
->instr
, stderr
);
796 fprintf(stderr
, "\n");
801 /* divergent boolean bcsel
802 * this implements bcsel on bools: dst = s0 ? s1 : s2
803 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
804 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
806 if (cond
.id() != then
.id())
807 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
809 if (cond
.id() == els
.id())
810 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
812 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
813 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
816 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
817 aco_opcode op
, uint32_t undo
)
819 /* multiply by 16777216 to handle denormals */
820 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
821 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
822 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
823 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
824 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
826 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
828 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
831 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
833 if (ctx
->block
->fp_mode
.denorm32
== 0) {
834 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
838 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
841 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
843 if (ctx
->block
->fp_mode
.denorm32
== 0) {
844 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
848 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
851 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
853 if (ctx
->block
->fp_mode
.denorm32
== 0) {
854 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
858 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
861 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
863 if (ctx
->block
->fp_mode
.denorm32
== 0) {
864 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
868 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
871 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
873 if (ctx
->options
->chip_class
>= GFX7
)
874 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
876 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
877 /* TODO: create more efficient code! */
878 if (val
.type() == RegType::sgpr
)
879 val
= as_vgpr(ctx
, val
);
881 /* Split the input value. */
882 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
883 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
885 /* Extract the exponent and compute the unbiased value. */
886 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
887 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
889 /* Extract the fractional part. */
890 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
891 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
893 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
894 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
896 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
897 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
898 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
899 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
900 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
902 /* Get the sign bit. */
903 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
905 /* Decide the operation to apply depending on the unbiased exponent. */
906 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
907 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
908 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
909 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
910 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
911 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
913 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
916 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
918 if (ctx
->options
->chip_class
>= GFX7
)
919 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
921 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
922 Temp src0
= as_vgpr(ctx
, val
);
924 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
925 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
927 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
928 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
929 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
931 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
933 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
934 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
936 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
937 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
939 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
941 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
942 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
944 return add
->definitions
[0].getTemp();
947 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
949 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
950 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
952 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
955 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
956 return bld
.copy(Definition(dst
), src
);
957 else if (dst
.bytes() < src
.bytes())
958 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
962 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
965 } else if (src
.regClass() == s1
) {
967 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
969 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
970 } else if (ctx
->options
->chip_class
>= GFX8
) {
971 assert(src_bits
!= 8 || src
.regClass() == v1b
);
972 assert(src_bits
!= 16 || src
.regClass() == v2b
);
973 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
974 sdwa
->operands
[0] = Operand(src
);
975 sdwa
->definitions
[0] = Definition(tmp
);
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
979 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
980 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
981 bld
.insert(std::move(sdwa
));
983 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
984 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
985 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
988 if (dst_bits
== 64) {
989 if (is_signed
&& dst
.regClass() == s2
) {
990 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
991 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
992 } else if (is_signed
&& dst
.regClass() == v2
) {
993 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
994 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
996 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
1003 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1005 if (!instr
->dest
.dest
.is_ssa
) {
1006 fprintf(stderr
, "nir alu dst not in ssa: ");
1007 nir_print_instr(&instr
->instr
, stderr
);
1008 fprintf(stderr
, "\n");
1011 Builder
bld(ctx
->program
, ctx
->block
);
1012 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1017 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1018 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1019 for (unsigned i
= 0; i
< num
; ++i
)
1020 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1022 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1023 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1024 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1025 for (unsigned i
= 0; i
< num
; ++i
) {
1026 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1027 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1029 vec
->operands
[i
] = Operand
{elems
[i
]};
1031 vec
->definitions
[0] = Definition(dst
);
1032 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1033 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1035 // TODO: that is a bit suboptimal..
1036 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1037 for (unsigned i
= 0; i
< num
- 1; ++i
)
1038 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1039 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1040 for (unsigned i
= 0; i
< num
; ++i
) {
1041 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1042 if (bit
% 32 == 0) {
1043 elems
[bit
/ 32] = elems
[i
];
1045 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1046 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1047 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1050 if (dst
.size() == 1)
1051 bld
.copy(Definition(dst
), elems
[0]);
1053 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1058 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1059 aco_ptr
<Instruction
> mov
;
1060 if (dst
.type() == RegType::sgpr
) {
1061 if (src
.type() == RegType::vgpr
)
1062 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1063 else if (src
.regClass() == s1
)
1064 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1065 else if (src
.regClass() == s2
)
1066 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1068 unreachable("wrong src register class for nir_op_imov");
1070 if (dst
.regClass() == v1
)
1071 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1072 else if (dst
.regClass() == v1b
||
1073 dst
.regClass() == v2b
||
1074 dst
.regClass() == v2
)
1075 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1077 unreachable("wrong src register class for nir_op_imov");
1082 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1083 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1084 assert(src
.regClass() == bld
.lm
);
1085 assert(dst
.regClass() == bld
.lm
);
1086 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1087 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1088 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1089 } else if (dst
.regClass() == v1
) {
1090 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1091 } else if (dst
.type() == RegType::sgpr
) {
1092 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1093 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1096 nir_print_instr(&instr
->instr
, stderr
);
1097 fprintf(stderr
, "\n");
1102 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1103 if (dst
.regClass() == v1
) {
1104 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1105 } else if (dst
.regClass() == s1
) {
1106 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1107 } else if (dst
.size() == 2) {
1108 Temp src0
= bld
.tmp(dst
.type(), 1);
1109 Temp src1
= bld
.tmp(dst
.type(), 1);
1110 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1112 if (dst
.regClass() == s2
) {
1113 Temp carry
= bld
.tmp(s1
);
1114 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1115 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1116 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1118 Temp lower
= bld
.tmp(v1
);
1119 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1120 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1121 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1131 if (dst
.regClass() == s1
) {
1132 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1133 } else if (dst
.regClass() == v1
) {
1134 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1135 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1137 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1138 nir_print_instr(&instr
->instr
, stderr
);
1139 fprintf(stderr
, "\n");
1143 case nir_op_isign
: {
1144 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1145 if (dst
.regClass() == s1
) {
1146 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1147 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1148 } else if (dst
.regClass() == s2
) {
1149 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1151 if (ctx
->program
->chip_class
>= GFX8
)
1152 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1154 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1155 /* SCC gets zero-extended to 64 bit */
1156 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1157 } else if (dst
.regClass() == v1
) {
1158 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1159 } else if (dst
.regClass() == v2
) {
1160 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1161 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1162 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1163 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1164 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1165 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1167 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1168 nir_print_instr(&instr
->instr
, stderr
);
1169 fprintf(stderr
, "\n");
1174 if (dst
.regClass() == v1
) {
1175 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1176 } else if (dst
.regClass() == s1
) {
1177 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1179 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1180 nir_print_instr(&instr
->instr
, stderr
);
1181 fprintf(stderr
, "\n");
1186 if (dst
.regClass() == v1
) {
1187 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1188 } else if (dst
.regClass() == s1
) {
1189 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1191 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1192 nir_print_instr(&instr
->instr
, stderr
);
1193 fprintf(stderr
, "\n");
1198 if (dst
.regClass() == v1
) {
1199 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1200 } else if (dst
.regClass() == s1
) {
1201 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1203 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1204 nir_print_instr(&instr
->instr
, stderr
);
1205 fprintf(stderr
, "\n");
1210 if (dst
.regClass() == v1
) {
1211 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1212 } else if (dst
.regClass() == s1
) {
1213 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1215 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1216 nir_print_instr(&instr
->instr
, stderr
);
1217 fprintf(stderr
, "\n");
1222 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1223 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1224 } else if (dst
.regClass() == v1
) {
1225 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1226 } else if (dst
.regClass() == s1
) {
1227 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1228 } else if (dst
.regClass() == s2
) {
1229 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1239 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1240 } else if (dst
.regClass() == v1
) {
1241 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1242 } else if (dst
.regClass() == s1
) {
1243 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1244 } else if (dst
.regClass() == s2
) {
1245 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1248 nir_print_instr(&instr
->instr
, stderr
);
1249 fprintf(stderr
, "\n");
1254 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1255 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1256 } else if (dst
.regClass() == v1
) {
1257 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1258 } else if (dst
.regClass() == s1
) {
1259 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1260 } else if (dst
.regClass() == s2
) {
1261 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1263 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1264 nir_print_instr(&instr
->instr
, stderr
);
1265 fprintf(stderr
, "\n");
1270 if (dst
.regClass() == v1
) {
1271 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1272 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1273 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1274 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1275 } else if (dst
.regClass() == v2
) {
1276 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1277 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1278 } else if (dst
.regClass() == s2
) {
1279 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1280 } else if (dst
.regClass() == s1
) {
1281 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1283 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1284 nir_print_instr(&instr
->instr
, stderr
);
1285 fprintf(stderr
, "\n");
1290 if (dst
.regClass() == v1
) {
1291 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1292 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1293 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1294 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1295 } else if (dst
.regClass() == v2
) {
1296 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1297 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1298 } else if (dst
.regClass() == s1
) {
1299 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1300 } else if (dst
.regClass() == s2
) {
1301 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1303 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1304 nir_print_instr(&instr
->instr
, stderr
);
1305 fprintf(stderr
, "\n");
1310 if (dst
.regClass() == v1
) {
1311 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1312 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1313 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1314 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1315 } else if (dst
.regClass() == v2
) {
1316 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1317 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1318 } else if (dst
.regClass() == s1
) {
1319 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1320 } else if (dst
.regClass() == s2
) {
1321 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1324 nir_print_instr(&instr
->instr
, stderr
);
1325 fprintf(stderr
, "\n");
1329 case nir_op_find_lsb
: {
1330 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1331 if (src
.regClass() == s1
) {
1332 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1333 } else if (src
.regClass() == v1
) {
1334 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1335 } else if (src
.regClass() == s2
) {
1336 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1338 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1339 nir_print_instr(&instr
->instr
, stderr
);
1340 fprintf(stderr
, "\n");
1344 case nir_op_ufind_msb
:
1345 case nir_op_ifind_msb
: {
1346 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1347 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1348 aco_opcode op
= src
.regClass() == s2
?
1349 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1350 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1351 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1353 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1354 Operand(src
.size() * 32u - 1u), msb_rev
);
1355 Temp msb
= sub
.def(0).getTemp();
1356 Temp carry
= sub
.def(1).getTemp();
1358 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1359 } else if (src
.regClass() == v1
) {
1360 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1361 Temp msb_rev
= bld
.tmp(v1
);
1362 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1363 Temp msb
= bld
.tmp(v1
);
1364 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1365 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1367 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1368 nir_print_instr(&instr
->instr
, stderr
);
1369 fprintf(stderr
, "\n");
1373 case nir_op_bitfield_reverse
: {
1374 if (dst
.regClass() == s1
) {
1375 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1376 } else if (dst
.regClass() == v1
) {
1377 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1379 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1380 nir_print_instr(&instr
->instr
, stderr
);
1381 fprintf(stderr
, "\n");
1386 if (dst
.regClass() == s1
) {
1387 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1391 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1392 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1393 if (dst
.regClass() == v1
) {
1394 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1398 assert(src0
.size() == 2 && src1
.size() == 2);
1399 Temp src00
= bld
.tmp(src0
.type(), 1);
1400 Temp src01
= bld
.tmp(dst
.type(), 1);
1401 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1402 Temp src10
= bld
.tmp(src1
.type(), 1);
1403 Temp src11
= bld
.tmp(dst
.type(), 1);
1404 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1406 if (dst
.regClass() == s2
) {
1407 Temp carry
= bld
.tmp(s1
);
1408 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1409 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1410 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1411 } else if (dst
.regClass() == v2
) {
1412 Temp dst0
= bld
.tmp(v1
);
1413 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1414 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1415 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1417 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1418 nir_print_instr(&instr
->instr
, stderr
);
1419 fprintf(stderr
, "\n");
1423 case nir_op_uadd_sat
: {
1424 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1425 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1426 if (dst
.regClass() == s1
) {
1427 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1428 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1430 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1431 } else if (dst
.regClass() == v1
) {
1432 if (ctx
->options
->chip_class
>= GFX9
) {
1433 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1434 add
->operands
[0] = Operand(src0
);
1435 add
->operands
[1] = Operand(src1
);
1436 add
->definitions
[0] = Definition(dst
);
1438 ctx
->block
->instructions
.emplace_back(std::move(add
));
1440 if (src1
.regClass() != v1
)
1441 std::swap(src0
, src1
);
1442 assert(src1
.regClass() == v1
);
1443 Temp tmp
= bld
.tmp(v1
);
1444 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1445 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1448 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1449 nir_print_instr(&instr
->instr
, stderr
);
1450 fprintf(stderr
, "\n");
1454 case nir_op_uadd_carry
: {
1455 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1456 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1457 if (dst
.regClass() == s1
) {
1458 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1461 if (dst
.regClass() == v1
) {
1462 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1463 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1467 Temp src00
= bld
.tmp(src0
.type(), 1);
1468 Temp src01
= bld
.tmp(dst
.type(), 1);
1469 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1470 Temp src10
= bld
.tmp(src1
.type(), 1);
1471 Temp src11
= bld
.tmp(dst
.type(), 1);
1472 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1473 if (dst
.regClass() == s2
) {
1474 Temp carry
= bld
.tmp(s1
);
1475 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1476 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1477 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1478 } else if (dst
.regClass() == v2
) {
1479 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1480 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1481 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1482 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1484 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1485 nir_print_instr(&instr
->instr
, stderr
);
1486 fprintf(stderr
, "\n");
1491 if (dst
.regClass() == s1
) {
1492 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1496 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1497 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1498 if (dst
.regClass() == v1
) {
1499 bld
.vsub32(Definition(dst
), src0
, src1
);
1503 Temp src00
= bld
.tmp(src0
.type(), 1);
1504 Temp src01
= bld
.tmp(dst
.type(), 1);
1505 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1506 Temp src10
= bld
.tmp(src1
.type(), 1);
1507 Temp src11
= bld
.tmp(dst
.type(), 1);
1508 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1509 if (dst
.regClass() == s2
) {
1510 Temp carry
= bld
.tmp(s1
);
1511 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1512 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1513 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1514 } else if (dst
.regClass() == v2
) {
1515 Temp lower
= bld
.tmp(v1
);
1516 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1517 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1518 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1520 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1521 nir_print_instr(&instr
->instr
, stderr
);
1522 fprintf(stderr
, "\n");
1526 case nir_op_usub_borrow
: {
1527 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1528 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1529 if (dst
.regClass() == s1
) {
1530 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1532 } else if (dst
.regClass() == v1
) {
1533 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1534 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1538 Temp src00
= bld
.tmp(src0
.type(), 1);
1539 Temp src01
= bld
.tmp(dst
.type(), 1);
1540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1541 Temp src10
= bld
.tmp(src1
.type(), 1);
1542 Temp src11
= bld
.tmp(dst
.type(), 1);
1543 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1544 if (dst
.regClass() == s2
) {
1545 Temp borrow
= bld
.tmp(s1
);
1546 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1547 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1548 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1549 } else if (dst
.regClass() == v2
) {
1550 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1551 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1552 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1564 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1565 } else if (dst
.regClass() == s1
) {
1566 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1568 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1569 nir_print_instr(&instr
->instr
, stderr
);
1570 fprintf(stderr
, "\n");
1574 case nir_op_umul_high
: {
1575 if (dst
.regClass() == v1
) {
1576 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1577 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1578 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1579 } else if (dst
.regClass() == s1
) {
1580 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1581 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1582 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1584 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1585 nir_print_instr(&instr
->instr
, stderr
);
1586 fprintf(stderr
, "\n");
1590 case nir_op_imul_high
: {
1591 if (dst
.regClass() == v1
) {
1592 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1593 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1594 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1595 } else if (dst
.regClass() == s1
) {
1596 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1597 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1598 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1600 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1601 nir_print_instr(&instr
->instr
, stderr
);
1602 fprintf(stderr
, "\n");
1607 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1608 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1609 if (dst
.regClass() == v2b
) {
1610 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1611 } else if (dst
.regClass() == v1
) {
1612 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1613 } else if (dst
.regClass() == v2
) {
1614 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1616 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1617 nir_print_instr(&instr
->instr
, stderr
);
1618 fprintf(stderr
, "\n");
1623 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1624 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1625 if (dst
.regClass() == v2b
) {
1626 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1627 } else if (dst
.regClass() == v1
) {
1628 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1629 } else if (dst
.regClass() == v2
) {
1630 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1632 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1633 nir_print_instr(&instr
->instr
, stderr
);
1634 fprintf(stderr
, "\n");
1639 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1640 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1641 if (dst
.regClass() == v2b
) {
1642 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1645 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1646 } else if (dst
.regClass() == v1
) {
1647 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1648 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1650 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1651 } else if (dst
.regClass() == v2
) {
1652 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1653 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1654 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1657 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1658 nir_print_instr(&instr
->instr
, stderr
);
1659 fprintf(stderr
, "\n");
1664 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1665 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1666 if (dst
.regClass() == v2b
) {
1667 // TODO: check fp_mode.must_flush_denorms16_64
1668 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1669 } else if (dst
.regClass() == v1
) {
1670 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1671 } else if (dst
.regClass() == v2
) {
1672 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1673 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1674 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1676 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1686 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1687 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1688 if (dst
.regClass() == v2b
) {
1689 // TODO: check fp_mode.must_flush_denorms16_64
1690 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1691 } else if (dst
.regClass() == v1
) {
1692 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1693 } else if (dst
.regClass() == v2
) {
1694 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1695 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1696 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1698 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1701 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1702 nir_print_instr(&instr
->instr
, stderr
);
1703 fprintf(stderr
, "\n");
1707 case nir_op_fmax3
: {
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, dst
, false);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1713 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1714 nir_print_instr(&instr
->instr
, stderr
);
1715 fprintf(stderr
, "\n");
1719 case nir_op_fmin3
: {
1720 if (dst
.regClass() == v2b
) {
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, dst
, false);
1722 } else if (dst
.regClass() == v1
) {
1723 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1725 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1726 nir_print_instr(&instr
->instr
, stderr
);
1727 fprintf(stderr
, "\n");
1731 case nir_op_fmed3
: {
1732 if (dst
.regClass() == v2b
) {
1733 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, dst
, false);
1734 } else if (dst
.regClass() == v1
) {
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1737 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1738 nir_print_instr(&instr
->instr
, stderr
);
1739 fprintf(stderr
, "\n");
1743 case nir_op_umax3
: {
1744 if (dst
.size() == 1) {
1745 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1748 nir_print_instr(&instr
->instr
, stderr
);
1749 fprintf(stderr
, "\n");
1753 case nir_op_umin3
: {
1754 if (dst
.size() == 1) {
1755 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1757 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1758 nir_print_instr(&instr
->instr
, stderr
);
1759 fprintf(stderr
, "\n");
1763 case nir_op_umed3
: {
1764 if (dst
.size() == 1) {
1765 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1767 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1768 nir_print_instr(&instr
->instr
, stderr
);
1769 fprintf(stderr
, "\n");
1773 case nir_op_imax3
: {
1774 if (dst
.size() == 1) {
1775 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1777 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1778 nir_print_instr(&instr
->instr
, stderr
);
1779 fprintf(stderr
, "\n");
1783 case nir_op_imin3
: {
1784 if (dst
.size() == 1) {
1785 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1787 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1788 nir_print_instr(&instr
->instr
, stderr
);
1789 fprintf(stderr
, "\n");
1793 case nir_op_imed3
: {
1794 if (dst
.size() == 1) {
1795 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1797 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1798 nir_print_instr(&instr
->instr
, stderr
);
1799 fprintf(stderr
, "\n");
1803 case nir_op_cube_face_coord
: {
1804 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1805 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1806 emit_extract_vector(ctx
, in
, 1, v1
),
1807 emit_extract_vector(ctx
, in
, 2, v1
) };
1808 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1809 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1810 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1811 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1813 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1814 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1817 case nir_op_cube_face_index
: {
1818 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1819 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1820 emit_extract_vector(ctx
, in
, 1, v1
),
1821 emit_extract_vector(ctx
, in
, 2, v1
) };
1822 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1825 case nir_op_bcsel
: {
1826 emit_bcsel(ctx
, instr
, dst
);
1830 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1831 if (dst
.regClass() == v2b
) {
1832 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1833 } else if (dst
.regClass() == v1
) {
1834 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1835 } else if (dst
.regClass() == v2
) {
1836 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1838 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1839 nir_print_instr(&instr
->instr
, stderr
);
1840 fprintf(stderr
, "\n");
1845 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1846 if (dst
.regClass() == v2b
) {
1847 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1848 } else if (dst
.regClass() == v1
) {
1849 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1850 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1851 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1852 } else if (dst
.regClass() == v2
) {
1853 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1854 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1855 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1856 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1857 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1858 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1860 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1861 nir_print_instr(&instr
->instr
, stderr
);
1862 fprintf(stderr
, "\n");
1867 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1868 if (dst
.regClass() == v2b
) {
1869 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1870 } else if (dst
.regClass() == v1
) {
1871 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1872 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1873 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1874 } else if (dst
.regClass() == v2
) {
1875 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1876 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1877 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1879 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1880 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1883 nir_print_instr(&instr
->instr
, stderr
);
1884 fprintf(stderr
, "\n");
1889 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1890 if (dst
.regClass() == v2b
) {
1891 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1892 } else if (dst
.regClass() == v1
) {
1893 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1894 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1895 // TODO: confirm that this holds under any circumstances
1896 } else if (dst
.regClass() == v2
) {
1897 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1898 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1901 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1902 nir_print_instr(&instr
->instr
, stderr
);
1903 fprintf(stderr
, "\n");
1907 case nir_op_flog2
: {
1908 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1909 if (dst
.regClass() == v2b
) {
1910 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1911 } else if (dst
.regClass() == v1
) {
1912 emit_log2(ctx
, bld
, Definition(dst
), src
);
1914 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1915 nir_print_instr(&instr
->instr
, stderr
);
1916 fprintf(stderr
, "\n");
1921 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1922 if (dst
.regClass() == v2b
) {
1923 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1924 } else if (dst
.regClass() == v1
) {
1925 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1926 } else if (dst
.regClass() == v2
) {
1927 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1929 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1930 nir_print_instr(&instr
->instr
, stderr
);
1931 fprintf(stderr
, "\n");
1935 case nir_op_fexp2
: {
1936 if (dst
.regClass() == v2b
) {
1937 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1938 } else if (dst
.regClass() == v1
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1941 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1942 nir_print_instr(&instr
->instr
, stderr
);
1943 fprintf(stderr
, "\n");
1947 case nir_op_fsqrt
: {
1948 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1949 if (dst
.regClass() == v2b
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1951 } else if (dst
.regClass() == v1
) {
1952 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1953 } else if (dst
.regClass() == v2
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1956 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1957 nir_print_instr(&instr
->instr
, stderr
);
1958 fprintf(stderr
, "\n");
1962 case nir_op_ffract
: {
1963 if (dst
.regClass() == v2b
) {
1964 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1965 } else if (dst
.regClass() == v1
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1967 } else if (dst
.regClass() == v2
) {
1968 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1970 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1971 nir_print_instr(&instr
->instr
, stderr
);
1972 fprintf(stderr
, "\n");
1976 case nir_op_ffloor
: {
1977 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1978 if (dst
.regClass() == v2b
) {
1979 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1980 } else if (dst
.regClass() == v1
) {
1981 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1982 } else if (dst
.regClass() == v2
) {
1983 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1986 nir_print_instr(&instr
->instr
, stderr
);
1987 fprintf(stderr
, "\n");
1991 case nir_op_fceil
: {
1992 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1993 if (dst
.regClass() == v2b
) {
1994 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 if (ctx
->options
->chip_class
>= GFX7
) {
1999 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2001 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2002 /* trunc = trunc(src0)
2003 * if (src0 > 0.0 && src0 != trunc)
2006 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2007 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2008 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2009 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2010 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2011 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2012 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2015 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2016 nir_print_instr(&instr
->instr
, stderr
);
2017 fprintf(stderr
, "\n");
2021 case nir_op_ftrunc
: {
2022 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2023 if (dst
.regClass() == v2b
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2025 } else if (dst
.regClass() == v1
) {
2026 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2027 } else if (dst
.regClass() == v2
) {
2028 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2030 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2031 nir_print_instr(&instr
->instr
, stderr
);
2032 fprintf(stderr
, "\n");
2036 case nir_op_fround_even
: {
2037 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2038 if (dst
.regClass() == v2b
) {
2039 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2040 } else if (dst
.regClass() == v1
) {
2041 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2042 } else if (dst
.regClass() == v2
) {
2043 if (ctx
->options
->chip_class
>= GFX7
) {
2044 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2046 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2047 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2048 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2050 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2051 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2052 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2053 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2054 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2055 tmp
= sub
->definitions
[0].getTemp();
2057 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2058 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2059 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2060 Temp cond
= vop3
->definitions
[0].getTemp();
2062 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2063 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2064 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2065 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2067 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2070 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2071 nir_print_instr(&instr
->instr
, stderr
);
2072 fprintf(stderr
, "\n");
2078 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2079 aco_ptr
<Instruction
> norm
;
2080 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2081 if (dst
.regClass() == v2b
) {
2082 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2083 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2084 bld
.vop1(opcode
, Definition(dst
), tmp
);
2085 } else if (dst
.regClass() == v1
) {
2086 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2088 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2089 if (ctx
->options
->chip_class
< GFX9
)
2090 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2092 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2093 bld
.vop1(opcode
, Definition(dst
), tmp
);
2095 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2096 nir_print_instr(&instr
->instr
, stderr
);
2097 fprintf(stderr
, "\n");
2101 case nir_op_ldexp
: {
2102 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2103 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2104 if (dst
.regClass() == v2b
) {
2105 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2106 } else if (dst
.regClass() == v1
) {
2107 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2108 } else if (dst
.regClass() == v2
) {
2109 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2112 nir_print_instr(&instr
->instr
, stderr
);
2113 fprintf(stderr
, "\n");
2117 case nir_op_frexp_sig
: {
2118 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2119 if (dst
.regClass() == v2b
) {
2120 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2121 } else if (dst
.regClass() == v1
) {
2122 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2123 } else if (dst
.regClass() == v2
) {
2124 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2126 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2127 nir_print_instr(&instr
->instr
, stderr
);
2128 fprintf(stderr
, "\n");
2132 case nir_op_frexp_exp
: {
2133 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2134 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2135 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2136 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2137 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2138 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2139 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2140 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2141 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2143 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2144 nir_print_instr(&instr
->instr
, stderr
);
2145 fprintf(stderr
, "\n");
2149 case nir_op_fsign
: {
2150 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2151 if (dst
.regClass() == v2b
) {
2152 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2153 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2154 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2155 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2156 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2157 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2158 } else if (dst
.regClass() == v1
) {
2159 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2160 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2161 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2162 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2163 } else if (dst
.regClass() == v2
) {
2164 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2165 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2166 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2168 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2169 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2170 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2172 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2174 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2175 nir_print_instr(&instr
->instr
, stderr
);
2176 fprintf(stderr
, "\n");
2181 case nir_op_f2f16_rtne
: {
2182 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2183 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2184 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2185 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2188 case nir_op_f2f16_rtz
: {
2189 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2190 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2191 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2192 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2195 case nir_op_f2f32
: {
2196 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2197 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2198 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2199 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2201 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2202 nir_print_instr(&instr
->instr
, stderr
);
2203 fprintf(stderr
, "\n");
2207 case nir_op_f2f64
: {
2208 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2209 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2210 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2211 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2214 case nir_op_i2f16
: {
2215 assert(dst
.regClass() == v2b
);
2216 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2217 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2218 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2219 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2222 case nir_op_i2f32
: {
2223 assert(dst
.size() == 1);
2224 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2225 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2226 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2227 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2230 case nir_op_i2f64
: {
2231 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2232 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2233 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2234 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2235 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2236 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2237 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2238 RegClass rc
= RegClass(src
.type(), 1);
2239 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2240 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2241 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2242 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2243 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2244 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2247 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2248 nir_print_instr(&instr
->instr
, stderr
);
2249 fprintf(stderr
, "\n");
2253 case nir_op_u2f16
: {
2254 assert(dst
.regClass() == v2b
);
2255 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2256 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2257 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2258 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2261 case nir_op_u2f32
: {
2262 assert(dst
.size() == 1);
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2265 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2266 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2268 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2269 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2270 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2274 case nir_op_u2f64
: {
2275 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2276 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2277 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2278 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2279 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2280 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 RegClass rc
= RegClass(src
.type(), 1);
2283 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2284 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2285 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2286 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2287 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2288 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2291 nir_print_instr(&instr
->instr
, stderr
);
2292 fprintf(stderr
, "\n");
2297 case nir_op_f2i16
: {
2298 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2299 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2300 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2301 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2302 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2304 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2306 if (dst
.type() == RegType::vgpr
)
2307 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2309 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2313 case nir_op_f2u16
: {
2314 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2315 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2316 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2317 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2318 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2320 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2322 if (dst
.type() == RegType::vgpr
)
2323 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2325 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2328 case nir_op_f2i32
: {
2329 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2330 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2331 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2332 if (dst
.type() == RegType::vgpr
) {
2333 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2335 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2336 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2338 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2339 if (dst
.type() == RegType::vgpr
)
2340 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2342 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2343 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2345 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2346 if (dst
.type() == RegType::vgpr
)
2347 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2349 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2350 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2354 nir_print_instr(&instr
->instr
, stderr
);
2355 fprintf(stderr
, "\n");
2359 case nir_op_f2u32
: {
2360 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2361 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2362 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2363 if (dst
.type() == RegType::vgpr
) {
2364 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2366 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2367 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2369 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2370 if (dst
.type() == RegType::vgpr
)
2371 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2373 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2374 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2376 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2377 if (dst
.type() == RegType::vgpr
)
2378 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2380 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2381 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2384 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2385 nir_print_instr(&instr
->instr
, stderr
);
2386 fprintf(stderr
, "\n");
2390 case nir_op_f2i64
: {
2391 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2392 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2393 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2395 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2396 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2397 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2398 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2399 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2400 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2401 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2402 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2403 Temp new_exponent
= bld
.tmp(v1
);
2404 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2405 if (ctx
->program
->chip_class
>= GFX8
)
2406 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2408 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2409 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2410 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2411 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2412 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2413 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2414 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2415 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2416 Temp new_lower
= bld
.tmp(v1
);
2417 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2418 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2419 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2421 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2422 if (src
.type() == RegType::vgpr
)
2423 src
= bld
.as_uniform(src
);
2424 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2425 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2426 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2427 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2428 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2429 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2430 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2431 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2432 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2433 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2434 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2435 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2436 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2437 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2438 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2439 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2440 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2441 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2442 Temp borrow
= bld
.tmp(s1
);
2443 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2444 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2445 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2447 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2448 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2449 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2450 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2451 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2452 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2453 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2454 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2455 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2456 if (dst
.type() == RegType::sgpr
) {
2457 lower
= bld
.as_uniform(lower
);
2458 upper
= bld
.as_uniform(upper
);
2460 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2463 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2464 nir_print_instr(&instr
->instr
, stderr
);
2465 fprintf(stderr
, "\n");
2469 case nir_op_f2u64
: {
2470 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2471 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2472 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2474 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2475 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2476 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2477 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2478 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2479 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2480 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2481 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2482 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2483 Temp new_exponent
= bld
.tmp(v1
);
2484 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2485 if (ctx
->program
->chip_class
>= GFX8
)
2486 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2488 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2489 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2490 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2491 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2492 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2493 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2494 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2495 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2497 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2498 if (src
.type() == RegType::vgpr
)
2499 src
= bld
.as_uniform(src
);
2500 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2501 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2502 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2503 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2504 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2505 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2506 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2507 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2508 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2509 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2510 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2511 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2512 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2513 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2514 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2515 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2516 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2519 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2520 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2521 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2522 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2523 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2524 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2525 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2526 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2527 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2528 if (dst
.type() == RegType::sgpr
) {
2529 lower
= bld
.as_uniform(lower
);
2530 upper
= bld
.as_uniform(upper
);
2532 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2535 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2536 nir_print_instr(&instr
->instr
, stderr
);
2537 fprintf(stderr
, "\n");
2541 case nir_op_b2f16
: {
2542 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2543 assert(src
.regClass() == bld
.lm
);
2545 if (dst
.regClass() == s1
) {
2546 src
= bool_to_scalar_condition(ctx
, src
);
2547 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2548 } else if (dst
.regClass() == v2b
) {
2549 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2550 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2552 unreachable("Wrong destination register class for nir_op_b2f16.");
2556 case nir_op_b2f32
: {
2557 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2558 assert(src
.regClass() == bld
.lm
);
2560 if (dst
.regClass() == s1
) {
2561 src
= bool_to_scalar_condition(ctx
, src
);
2562 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2563 } else if (dst
.regClass() == v1
) {
2564 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2566 unreachable("Wrong destination register class for nir_op_b2f32.");
2570 case nir_op_b2f64
: {
2571 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2572 assert(src
.regClass() == bld
.lm
);
2574 if (dst
.regClass() == s2
) {
2575 src
= bool_to_scalar_condition(ctx
, src
);
2576 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2577 } else if (dst
.regClass() == v2
) {
2578 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2579 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2580 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2582 unreachable("Wrong destination register class for nir_op_b2f64.");
2589 case nir_op_i2i64
: {
2590 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2591 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2597 case nir_op_u2u64
: {
2598 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2599 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2603 case nir_op_b2i32
: {
2604 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2605 assert(src
.regClass() == bld
.lm
);
2607 if (dst
.regClass() == s1
) {
2608 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2609 bool_to_scalar_condition(ctx
, src
, dst
);
2610 } else if (dst
.regClass() == v1
) {
2611 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2613 unreachable("Invalid register class for b2i32");
2619 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2620 assert(dst
.regClass() == bld
.lm
);
2622 if (src
.type() == RegType::vgpr
) {
2623 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2624 assert(dst
.regClass() == bld
.lm
);
2625 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2626 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2628 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2630 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2631 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2633 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2634 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2636 bool_to_vector_condition(ctx
, tmp
, dst
);
2640 case nir_op_pack_64_2x32_split
: {
2641 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2642 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2644 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2647 case nir_op_unpack_64_2x32_split_x
:
2648 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2650 case nir_op_unpack_64_2x32_split_y
:
2651 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2653 case nir_op_unpack_32_2x16_split_x
:
2654 if (dst
.type() == RegType::vgpr
) {
2655 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2657 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2660 case nir_op_unpack_32_2x16_split_y
:
2661 if (dst
.type() == RegType::vgpr
) {
2662 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2664 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2667 case nir_op_pack_32_2x16_split
: {
2668 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2669 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2670 if (dst
.regClass() == v1
) {
2671 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2672 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2673 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2676 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2677 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2681 case nir_op_pack_half_2x16
: {
2682 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2684 if (dst
.regClass() == v1
) {
2685 Temp src0
= bld
.tmp(v1
);
2686 Temp src1
= bld
.tmp(v1
);
2687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2688 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2689 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2691 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2692 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2693 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2695 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2696 nir_print_instr(&instr
->instr
, stderr
);
2697 fprintf(stderr
, "\n");
2701 case nir_op_unpack_half_2x16_split_x
: {
2702 if (dst
.regClass() == v1
) {
2703 Builder
bld(ctx
->program
, ctx
->block
);
2704 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2706 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2707 nir_print_instr(&instr
->instr
, stderr
);
2708 fprintf(stderr
, "\n");
2712 case nir_op_unpack_half_2x16_split_y
: {
2713 if (dst
.regClass() == v1
) {
2714 Builder
bld(ctx
->program
, ctx
->block
);
2715 /* TODO: use SDWA here */
2716 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2717 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2719 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2720 nir_print_instr(&instr
->instr
, stderr
);
2721 fprintf(stderr
, "\n");
2725 case nir_op_fquantize2f16
: {
2726 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2727 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2730 if (ctx
->program
->chip_class
>= GFX8
) {
2731 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2732 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2733 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2735 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2736 * so compare the result and flush to 0 if it's smaller.
2738 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2739 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2740 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2741 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2742 cmp_res
= vop3
->definitions
[0].getTemp();
2745 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2746 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2747 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2749 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2754 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2757 if (dst
.regClass() == s1
) {
2758 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2759 } else if (dst
.regClass() == v1
) {
2760 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2762 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2763 nir_print_instr(&instr
->instr
, stderr
);
2764 fprintf(stderr
, "\n");
2768 case nir_op_bitfield_select
: {
2769 /* (mask & insert) | (~mask & base) */
2770 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2771 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2772 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2774 /* dst = (insert & bitmask) | (base & ~bitmask) */
2775 if (dst
.regClass() == s1
) {
2776 aco_ptr
<Instruction
> sop2
;
2777 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2778 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2780 if (const_insert
&& const_bitmask
) {
2781 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2783 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2784 lhs
= Operand(insert
);
2788 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2789 if (const_base
&& const_bitmask
) {
2790 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2792 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2793 rhs
= Operand(base
);
2796 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2798 } else if (dst
.regClass() == v1
) {
2799 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2800 base
= as_vgpr(ctx
, base
);
2801 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2802 insert
= as_vgpr(ctx
, insert
);
2804 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2807 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2808 nir_print_instr(&instr
->instr
, stderr
);
2809 fprintf(stderr
, "\n");
2815 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2816 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2817 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2819 if (dst
.type() == RegType::sgpr
) {
2821 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2822 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2823 if (const_offset
&& const_bits
) {
2824 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2825 extract
= Operand(const_extract
);
2829 width
= Operand(const_bits
->u32
<< 16);
2831 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2833 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2837 if (dst
.regClass() == s1
) {
2838 if (instr
->op
== nir_op_ubfe
)
2839 opcode
= aco_opcode::s_bfe_u32
;
2841 opcode
= aco_opcode::s_bfe_i32
;
2842 } else if (dst
.regClass() == s2
) {
2843 if (instr
->op
== nir_op_ubfe
)
2844 opcode
= aco_opcode::s_bfe_u64
;
2846 opcode
= aco_opcode::s_bfe_i64
;
2848 unreachable("Unsupported BFE bit size");
2851 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2855 if (dst
.regClass() == v1
) {
2856 if (instr
->op
== nir_op_ubfe
)
2857 opcode
= aco_opcode::v_bfe_u32
;
2859 opcode
= aco_opcode::v_bfe_i32
;
2861 unreachable("Unsupported BFE bit size");
2864 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2868 case nir_op_bit_count
: {
2869 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2870 if (src
.regClass() == s1
) {
2871 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2872 } else if (src
.regClass() == v1
) {
2873 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2874 } else if (src
.regClass() == v2
) {
2875 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2876 emit_extract_vector(ctx
, src
, 1, v1
),
2877 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2878 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2879 } else if (src
.regClass() == s2
) {
2880 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2882 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2883 nir_print_instr(&instr
->instr
, stderr
);
2884 fprintf(stderr
, "\n");
2889 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2893 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2897 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2901 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2905 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2909 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2913 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2914 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2916 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2917 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2921 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2922 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2924 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2925 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2938 case nir_op_fddx_fine
:
2939 case nir_op_fddy_fine
:
2940 case nir_op_fddx_coarse
:
2941 case nir_op_fddy_coarse
: {
2942 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2943 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2944 if (instr
->op
== nir_op_fddx_fine
) {
2945 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2946 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2947 } else if (instr
->op
== nir_op_fddy_fine
) {
2948 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2949 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2951 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2952 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2953 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2955 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2959 if (ctx
->program
->chip_class
>= GFX8
) {
2960 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2961 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2963 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2964 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2965 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2967 emit_wqm(ctx
, tmp
, dst
, true);
2971 fprintf(stderr
, "Unknown NIR ALU instr: ");
2972 nir_print_instr(&instr
->instr
, stderr
);
2973 fprintf(stderr
, "\n");
2977 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2979 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2981 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2982 // which get truncated the lsb if double and msb if int
2983 // for now, we only use s_mov_b64 with 64bit inline constants
2984 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2985 assert(dst
.type() == RegType::sgpr
);
2987 Builder
bld(ctx
->program
, ctx
->block
);
2989 if (instr
->def
.bit_size
== 1) {
2990 assert(dst
.regClass() == bld
.lm
);
2991 int val
= instr
->value
[0].b
? -1 : 0;
2992 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2993 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2994 } else if (instr
->def
.bit_size
== 8) {
2995 /* ensure that the value is correctly represented in the low byte of the register */
2996 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2997 } else if (instr
->def
.bit_size
== 16) {
2998 /* ensure that the value is correctly represented in the low half of the register */
2999 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3000 } else if (dst
.size() == 1) {
3001 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3003 assert(dst
.size() != 1);
3004 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3005 if (instr
->def
.bit_size
== 64)
3006 for (unsigned i
= 0; i
< dst
.size(); i
++)
3007 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3009 for (unsigned i
= 0; i
< dst
.size(); i
++)
3010 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3012 vec
->definitions
[0] = Definition(dst
);
3013 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3017 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3019 uint32_t new_mask
= 0;
3020 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3021 if (mask
& (1u << i
))
3022 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3026 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3028 Builder
bld(ctx
->program
, ctx
->block
);
3029 if (offset
.isTemp()) {
3030 Temp tmp
[3] = {vec
, vec
, vec
};
3032 if (vec
.size() == 3) {
3033 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3034 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3035 } else if (vec
.size() == 2) {
3036 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3037 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3039 for (unsigned i
= 0; i
< dst
.size(); i
++)
3040 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3043 if (dst
.size() == 2)
3044 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3046 offset
= Operand(0u);
3049 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3050 bld
.copy(Definition(dst
), vec
);
3052 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3055 struct LoadEmitInfo
{
3058 unsigned num_components
;
3059 unsigned component_size
;
3060 Temp resource
= Temp(0, s1
);
3061 unsigned component_stride
= 0;
3062 unsigned const_offset
= 0;
3063 unsigned align_mul
= 0;
3064 unsigned align_offset
= 0;
3067 unsigned swizzle_component_size
= 0;
3068 barrier_interaction barrier
= barrier_none
;
3069 bool can_reorder
= true;
3070 Temp soffset
= Temp(0, s1
);
3073 using LoadCallback
= Temp(*)(
3074 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3075 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3077 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3078 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3080 unsigned load_size
= info
->num_components
* info
->component_size
;
3081 unsigned component_size
= info
->component_size
;
3083 unsigned num_vals
= 0;
3084 Temp vals
[info
->dst
.bytes()];
3086 unsigned const_offset
= info
->const_offset
;
3088 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3089 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3091 unsigned bytes_read
= 0;
3092 while (bytes_read
< load_size
) {
3093 unsigned bytes_needed
= load_size
- bytes_read
;
3095 /* add buffer for unaligned loads */
3096 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3099 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3100 if (info
->component_stride
) {
3101 assert(supports_8bit_16bit_loads
&& "unimplemented");
3105 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3106 bytes_needed
= align(bytes_needed
, 4);
3113 if (info
->swizzle_component_size
)
3114 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3115 if (info
->component_stride
)
3116 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3118 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3120 /* reduce constant offset */
3121 Operand offset
= info
->offset
;
3122 unsigned reduced_const_offset
= const_offset
;
3123 bool remove_const_offset_completely
= need_to_align_offset
;
3124 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3125 unsigned to_add
= const_offset
;
3126 if (remove_const_offset_completely
) {
3127 reduced_const_offset
= 0;
3129 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3130 reduced_const_offset
%= max_const_offset_plus_one
;
3132 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3133 if (offset
.isConstant()) {
3134 offset
= Operand(offset
.constantValue() + to_add
);
3135 } else if (offset_tmp
.regClass() == s1
) {
3136 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3137 offset_tmp
, Operand(to_add
));
3138 } else if (offset_tmp
.regClass() == v1
) {
3139 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3141 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3142 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3143 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3145 if (offset_tmp
.regClass() == s2
) {
3146 Temp carry
= bld
.tmp(s1
);
3147 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3148 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3149 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3151 Temp new_lo
= bld
.tmp(v1
);
3152 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3153 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3154 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3159 /* align offset down if needed */
3160 Operand aligned_offset
= offset
;
3161 if (need_to_align_offset
) {
3162 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3163 if (offset
.isConstant()) {
3164 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3165 } else if (offset_tmp
.regClass() == s1
) {
3166 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3167 } else if (offset_tmp
.regClass() == s2
) {
3168 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3169 } else if (offset_tmp
.regClass() == v1
) {
3170 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3171 } else if (offset_tmp
.regClass() == v2
) {
3172 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3173 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3174 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3175 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3178 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3179 bld
.copy(bld
.def(s1
), aligned_offset
);
3181 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3182 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3183 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3185 /* shift result right if needed */
3187 Operand
align((uint32_t)byte_align
);
3188 if (byte_align
== -1) {
3189 if (offset
.isConstant())
3190 align
= Operand(offset
.constantValue() % 4u);
3191 else if (offset
.size() == 2)
3192 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3197 if (align
.isTemp() || align
.constantValue()) {
3198 assert(val
.bytes() >= load_size
&& "unimplemented");
3199 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3200 if (val
.type() == RegType::sgpr
)
3201 byte_align_scalar(ctx
, val
, align
, new_val
);
3203 byte_align_vector(ctx
, val
, align
, new_val
);
3208 /* add result to list and advance */
3209 if (info
->component_stride
) {
3210 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3211 const_offset
+= info
->component_stride
;
3212 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3214 const_offset
+= val
.bytes();
3215 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3217 bytes_read
+= val
.bytes();
3218 vals
[num_vals
++] = val
;
3221 /* the callback wrote directly to dst */
3222 if (vals
[0] == info
->dst
) {
3223 assert(num_vals
== 1);
3224 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3228 /* create array of components */
3229 unsigned components_split
= 0;
3230 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3231 bool has_vgprs
= false;
3232 for (unsigned i
= 0; i
< num_vals
;) {
3234 unsigned num_tmps
= 0;
3235 unsigned tmp_size
= 0;
3236 RegType reg_type
= RegType::sgpr
;
3237 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3238 if (vals
[i
].type() == RegType::vgpr
)
3239 reg_type
= RegType::vgpr
;
3240 tmp_size
+= vals
[i
].bytes();
3241 tmp
[num_tmps
++] = vals
[i
++];
3244 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3245 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3246 for (unsigned i
= 0; i
< num_vals
; i
++)
3247 vec
->operands
[i
] = Operand(tmp
[i
]);
3248 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3249 vec
->definitions
[0] = Definition(tmp
[0]);
3250 bld
.insert(std::move(vec
));
3253 if (tmp
[0].bytes() % component_size
) {
3255 assert(i
== num_vals
);
3256 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3257 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3260 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3262 unsigned start
= components_split
;
3264 if (tmp_size
== elem_rc
.bytes()) {
3265 allocated_vec
[components_split
++] = tmp
[0];
3267 assert(tmp_size
% elem_rc
.bytes() == 0);
3268 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3269 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3270 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3271 Temp component
= bld
.tmp(elem_rc
);
3272 allocated_vec
[components_split
++] = component
;
3273 split
->definitions
[i
] = Definition(component
);
3275 split
->operands
[0] = Operand(tmp
[0]);
3276 bld
.insert(std::move(split
));
3279 /* try to p_as_uniform early so we can create more optimizable code and
3280 * also update allocated_vec */
3281 for (unsigned j
= start
; j
< components_split
; j
++) {
3282 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3283 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3284 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3288 /* concatenate components and p_as_uniform() result if needed */
3289 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3290 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3292 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3294 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3295 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3296 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3297 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3299 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3300 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3301 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3302 vec
->definitions
[0] = Definition(tmp
);
3303 bld
.insert(std::move(vec
));
3304 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3306 vec
->definitions
[0] = Definition(info
->dst
);
3307 bld
.insert(std::move(vec
));
3311 Operand
load_lds_size_m0(Builder
& bld
)
3313 /* TODO: m0 does not need to be initialized on GFX9+ */
3314 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3317 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3318 Temp offset
, unsigned bytes_needed
,
3319 unsigned align
, unsigned const_offset
,
3322 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3324 Operand m
= load_lds_size_m0(bld
);
3326 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3327 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3332 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3333 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3335 op
= aco_opcode::ds_read_b128
;
3336 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3339 op
= aco_opcode::ds_read2_b64
;
3340 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3342 op
= aco_opcode::ds_read_b96
;
3343 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3345 op
= aco_opcode::ds_read_b64
;
3346 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3349 op
= aco_opcode::ds_read2_b32
;
3350 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3352 op
= aco_opcode::ds_read_b32
;
3353 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3355 op
= aco_opcode::ds_read_u16
;
3358 op
= aco_opcode::ds_read_u8
;
3361 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3362 if (const_offset
>= max_offset_plus_one
) {
3363 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3364 const_offset
%= max_offset_plus_one
;
3368 const_offset
/= (size
/ 2u);
3370 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3371 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3373 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3375 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3378 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3383 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3385 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3386 Temp offset
, unsigned bytes_needed
,
3387 unsigned align
, unsigned const_offset
,
3392 if (bytes_needed
<= 4) {
3394 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3395 } else if (bytes_needed
<= 8) {
3397 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3398 } else if (bytes_needed
<= 16) {
3400 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3401 } else if (bytes_needed
<= 32) {
3403 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3406 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3408 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3409 if (info
->resource
.id()) {
3410 load
->operands
[0] = Operand(info
->resource
);
3411 load
->operands
[1] = Operand(offset
);
3413 load
->operands
[0] = Operand(offset
);
3414 load
->operands
[1] = Operand(0u);
3416 RegClass
rc(RegType::sgpr
, size
);
3417 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3418 load
->definitions
[0] = Definition(val
);
3419 load
->glc
= info
->glc
;
3420 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3421 load
->barrier
= info
->barrier
;
3422 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3423 bld
.insert(std::move(load
));
3427 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3429 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3430 Temp offset
, unsigned bytes_needed
,
3431 unsigned align_
, unsigned const_offset
,
3434 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3435 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3437 if (info
->soffset
.id()) {
3438 if (soffset
.isTemp())
3439 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3440 soffset
= Operand(info
->soffset
);
3443 unsigned bytes_size
= 0;
3445 if (bytes_needed
== 1) {
3447 op
= aco_opcode::buffer_load_ubyte
;
3448 } else if (bytes_needed
== 2) {
3450 op
= aco_opcode::buffer_load_ushort
;
3451 } else if (bytes_needed
<= 4) {
3453 op
= aco_opcode::buffer_load_dword
;
3454 } else if (bytes_needed
<= 8) {
3456 op
= aco_opcode::buffer_load_dwordx2
;
3457 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3459 op
= aco_opcode::buffer_load_dwordx3
;
3462 op
= aco_opcode::buffer_load_dwordx4
;
3464 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3465 mubuf
->operands
[0] = Operand(info
->resource
);
3466 mubuf
->operands
[1] = vaddr
;
3467 mubuf
->operands
[2] = soffset
;
3468 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3469 mubuf
->glc
= info
->glc
;
3470 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3471 mubuf
->barrier
= info
->barrier
;
3472 mubuf
->can_reorder
= info
->can_reorder
;
3473 mubuf
->offset
= const_offset
;
3474 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3475 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3476 mubuf
->definitions
[0] = Definition(val
);
3477 bld
.insert(std::move(mubuf
));
3480 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3485 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3487 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3489 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3490 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3492 if (addr
.type() == RegType::vgpr
)
3493 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3494 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3497 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3498 Temp offset
, unsigned bytes_needed
,
3499 unsigned align_
, unsigned const_offset
,
3502 unsigned bytes_size
= 0;
3503 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3504 bool global
= bld
.program
->chip_class
>= GFX9
;
3506 if (bytes_needed
== 1) {
3508 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3509 } else if (bytes_needed
== 2) {
3511 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3512 } else if (bytes_needed
<= 4) {
3514 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3515 } else if (bytes_needed
<= 8) {
3517 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3518 } else if (bytes_needed
<= 12 && !mubuf
) {
3520 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3523 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3525 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3526 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3528 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3529 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3530 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3531 mubuf
->operands
[2] = Operand(0u);
3532 mubuf
->glc
= info
->glc
;
3535 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3536 mubuf
->disable_wqm
= false;
3537 mubuf
->barrier
= info
->barrier
;
3538 mubuf
->definitions
[0] = Definition(val
);
3539 bld
.insert(std::move(mubuf
));
3541 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3543 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3544 flat
->operands
[0] = Operand(offset
);
3545 flat
->operands
[1] = Operand(s1
);
3546 flat
->glc
= info
->glc
;
3547 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3548 flat
->barrier
= info
->barrier
;
3550 flat
->definitions
[0] = Definition(val
);
3551 bld
.insert(std::move(flat
));
3555 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3560 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3562 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3563 Temp address
, unsigned base_offset
, unsigned align
)
3565 assert(util_is_power_of_two_nonzero(align
));
3567 Builder
bld(ctx
->program
, ctx
->block
);
3569 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3570 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3571 info
.align_mul
= align
;
3572 info
.align_offset
= 0;
3573 info
.barrier
= barrier_shared
;
3574 info
.can_reorder
= false;
3575 info
.const_offset
= base_offset
;
3576 emit_lds_load(ctx
, bld
, &info
);
3581 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3586 Builder
bld(ctx
->program
, ctx
->block
);
3588 ASSERTED
bool is_subdword
= false;
3589 for (unsigned i
= 0; i
< count
; i
++)
3590 is_subdword
|= offsets
[i
] % 4;
3591 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3592 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3594 /* count == 1 fast path */
3596 if (dst_type
== RegType::sgpr
)
3597 dst
[0] = bld
.as_uniform(src
);
3599 dst
[0] = as_vgpr(ctx
, src
);
3603 for (unsigned i
= 0; i
< count
- 1; i
++)
3604 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3605 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3607 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3608 src
= as_vgpr(ctx
, src
);
3610 /* use allocated_vec if possible */
3611 auto it
= ctx
->allocated_vec
.find(src
.id());
3612 if (it
!= ctx
->allocated_vec
.end()) {
3613 unsigned total_size
= 0;
3614 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3615 total_size
+= it
->second
[i
].bytes();
3616 if (total_size
!= src
.bytes())
3619 unsigned elem_size
= it
->second
[0].bytes();
3621 for (unsigned i
= 0; i
< count
; i
++) {
3622 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3626 for (unsigned i
= 0; i
< count
; i
++) {
3627 unsigned start_idx
= offsets
[i
] / elem_size
;
3628 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3629 if (op_count
== 1) {
3630 if (dst_type
== RegType::sgpr
)
3631 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3633 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3637 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3638 for (unsigned j
= 0; j
< op_count
; j
++) {
3639 Temp tmp
= it
->second
[start_idx
+ j
];
3640 if (dst_type
== RegType::sgpr
)
3641 tmp
= bld
.as_uniform(tmp
);
3642 vec
->operands
[j
] = Operand(tmp
);
3644 vec
->definitions
[0] = Definition(dst
[i
]);
3645 bld
.insert(std::move(vec
));
3651 if (dst_type
== RegType::sgpr
)
3652 src
= bld
.as_uniform(src
);
3656 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3657 split
->operands
[0] = Operand(src
);
3658 for (unsigned i
= 0; i
< count
; i
++)
3659 split
->definitions
[i
] = Definition(dst
[i
]);
3660 bld
.insert(std::move(split
));
3663 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3664 int *start
, int *count
)
3666 unsigned start_elem
= ffs(todo_mask
) - 1;
3667 bool skip
= !(mask
& (1 << start_elem
));
3669 mask
= ~mask
& todo_mask
;
3673 u_bit_scan_consecutive_range(&mask
, start
, count
);
3678 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3680 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3683 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3684 Temp address
, unsigned base_offset
, unsigned align
)
3686 assert(util_is_power_of_two_nonzero(align
));
3687 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3689 Builder
bld(ctx
->program
, ctx
->block
);
3690 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3691 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3693 unsigned write_count
= 0;
3694 Temp write_datas
[32];
3695 unsigned offsets
[32];
3696 aco_opcode opcodes
[32];
3698 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3700 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3703 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3704 offsets
[write_count
] = offset
;
3705 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3707 advance_write_mask(&todo
, offset
, bytes
);
3711 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3712 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3713 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3714 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3716 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3717 aco_opcode op
= aco_opcode::num_opcodes
;
3718 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3719 op
= aco_opcode::ds_write_b128
;
3721 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3722 op
= aco_opcode::ds_write_b96
;
3724 } else if (bytes
>= 8 && aligned8
) {
3725 op
= aco_opcode::ds_write_b64
;
3727 } else if (bytes
>= 4 && aligned4
) {
3728 op
= aco_opcode::ds_write_b32
;
3730 } else if (bytes
>= 2 && aligned2
) {
3731 op
= aco_opcode::ds_write_b16
;
3733 } else if (bytes
>= 1) {
3734 op
= aco_opcode::ds_write_b8
;
3740 offsets
[write_count
] = offset
;
3741 opcodes
[write_count
] = op
;
3743 advance_write_mask(&todo
, offset
, bytes
);
3746 Operand m
= load_lds_size_m0(bld
);
3748 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3750 for (unsigned i
= 0; i
< write_count
; i
++) {
3751 aco_opcode op
= opcodes
[i
];
3752 if (op
== aco_opcode::num_opcodes
)
3755 Temp data
= write_datas
[i
];
3757 unsigned second
= write_count
;
3758 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3759 for (second
= i
+ 1; second
< write_count
; second
++) {
3760 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3761 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3762 opcodes
[second
] = aco_opcode::num_opcodes
;
3768 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3769 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3771 unsigned inline_offset
= base_offset
+ offsets
[i
];
3772 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3773 Temp address_offset
= address
;
3774 if (inline_offset
> max_offset
) {
3775 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3776 inline_offset
= offsets
[i
];
3778 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3781 Temp second_data
= write_datas
[second
];
3782 inline_offset
/= data
.bytes();
3783 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3785 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3790 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3792 unsigned align
= 16;
3794 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3800 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3805 return aco_opcode::buffer_store_byte
;
3808 return aco_opcode::buffer_store_short
;
3810 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3812 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3815 return aco_opcode::buffer_store_dwordx3
;
3817 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3819 unreachable("Unexpected store size");
3820 return aco_opcode::num_opcodes
;
3823 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3824 Temp data
, unsigned writemask
, int swizzle_element_size
,
3825 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3827 unsigned write_count_with_skips
= 0;
3830 /* determine how to split the data */
3831 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3834 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3835 offsets
[write_count_with_skips
] = offset
;
3836 if (skips
[write_count_with_skips
]) {
3837 advance_write_mask(&todo
, offset
, bytes
);
3838 write_count_with_skips
++;
3842 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3843 * larger than swizzle_element_size */
3844 bytes
= MIN2(bytes
, swizzle_element_size
);
3846 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3848 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3849 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3852 /* dword or larger stores have to be dword-aligned */
3853 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3854 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3855 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3856 if (bytes
>= 4 && !dword_aligned
)
3857 bytes
= MIN2(bytes
, 2);
3859 advance_write_mask(&todo
, offset
, bytes
);
3860 write_count_with_skips
++;
3863 /* actually split data */
3864 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3867 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3870 write_datas
[*write_count
] = write_datas
[i
];
3871 offsets
[*write_count
] = offsets
[i
];
3876 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3877 unsigned split_cnt
= 0u, Temp dst
= Temp())
3879 Builder
bld(ctx
->program
, ctx
->block
);
3880 unsigned dword_size
= elem_size_bytes
/ 4;
3883 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3885 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3886 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3887 instr
->definitions
[0] = Definition(dst
);
3889 for (unsigned i
= 0; i
< cnt
; ++i
) {
3891 assert(arr
[i
].size() == dword_size
);
3892 allocated_vec
[i
] = arr
[i
];
3893 instr
->operands
[i
] = Operand(arr
[i
]);
3895 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3896 allocated_vec
[i
] = zero
;
3897 instr
->operands
[i
] = Operand(zero
);
3901 bld
.insert(std::move(instr
));
3904 emit_split_vector(ctx
, dst
, split_cnt
);
3906 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3911 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3913 if (const_offset
>= 4096) {
3914 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3915 const_offset
%= 4096u;
3918 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3919 else if (unlikely(voffset
.regClass() == s1
))
3920 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3921 else if (likely(voffset
.regClass() == v1
))
3922 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3924 unreachable("Unsupported register class of voffset");
3927 return const_offset
;
3930 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3931 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3934 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3935 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3937 Builder
bld(ctx
->program
, ctx
->block
);
3938 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3939 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3941 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3942 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3943 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3944 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3945 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3947 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3950 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3951 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3952 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3954 Builder
bld(ctx
->program
, ctx
->block
);
3955 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3957 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3959 unsigned write_count
= 0;
3960 Temp write_datas
[32];
3961 unsigned offsets
[32];
3962 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3963 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3965 for (unsigned i
= 0; i
< write_count
; i
++) {
3966 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3967 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3971 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3972 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3973 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3975 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3976 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3977 assert(!!stride
!= allow_combining
);
3979 Builder
bld(ctx
->program
, ctx
->block
);
3981 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3982 info
.component_stride
= allow_combining
? 0 : stride
;
3984 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3985 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3986 info
.align_offset
= 0;
3987 info
.soffset
= soffset
;
3988 info
.const_offset
= base_const_offset
;
3989 emit_mubuf_load(ctx
, bld
, &info
);
3992 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3994 Builder
bld(ctx
->program
, ctx
->block
);
3995 Temp offset
= base_offset
.first
;
3996 unsigned const_offset
= base_offset
.second
;
3998 if (!nir_src_is_const(*off_src
)) {
3999 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4002 /* Calculate indirect offset with stride */
4003 if (likely(indirect_offset_arg
.regClass() == v1
))
4004 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4005 else if (indirect_offset_arg
.regClass() == s1
)
4006 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4008 unreachable("Unsupported register class of indirect offset");
4010 /* Add to the supplied base offset */
4011 if (offset
.id() == 0)
4012 offset
= with_stride
;
4013 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4014 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4015 else if (offset
.size() == 1 && with_stride
.size() == 1)
4016 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4018 unreachable("Unsupported register class of indirect offset");
4020 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4021 const_offset
+= const_offset_arg
* stride
;
4024 return std::make_pair(offset
, const_offset
);
4027 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4029 Builder
bld(ctx
->program
, ctx
->block
);
4032 if (off1
.first
.id() && off2
.first
.id()) {
4033 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4034 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4035 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4036 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4038 unreachable("Unsupported register class of indirect offset");
4040 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4043 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4046 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4048 Builder
bld(ctx
->program
, ctx
->block
);
4049 unsigned const_offset
= offs
.second
* multiplier
;
4051 if (!offs
.first
.id())
4052 return std::make_pair(offs
.first
, const_offset
);
4054 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4055 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4056 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4058 return std::make_pair(offset
, const_offset
);
4061 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4063 Builder
bld(ctx
->program
, ctx
->block
);
4065 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4066 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4067 /* component is in bytes */
4068 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4070 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4071 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4072 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4075 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4077 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4080 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4082 Builder
bld(ctx
->program
, ctx
->block
);
4084 switch (ctx
->shader
->info
.stage
) {
4085 case MESA_SHADER_TESS_CTRL
:
4086 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4087 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4088 case MESA_SHADER_TESS_EVAL
:
4089 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4091 unreachable("Unsupported stage in get_tess_rel_patch_id");
4095 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4097 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4098 Builder
bld(ctx
->program
, ctx
->block
);
4100 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4101 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4103 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4105 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4106 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4108 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4109 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4110 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4112 return offset_mul(ctx
, offs
, 4u);
4115 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4117 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4118 Builder
bld(ctx
->program
, ctx
->block
);
4120 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4121 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4122 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4123 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4125 std::pair
<Temp
, unsigned> offs
= instr
4126 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4127 : std::make_pair(Temp(), 0u);
4129 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4130 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4135 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4136 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4138 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4139 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4141 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4142 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4148 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4150 Builder
bld(ctx
->program
, ctx
->block
);
4152 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4153 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4155 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4157 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4158 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4159 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4161 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4162 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4167 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4169 Builder
bld(ctx
->program
, ctx
->block
);
4171 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4172 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4173 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4174 unsigned attr_stride
= ctx
->tcs_num_patches
;
4176 std::pair
<Temp
, unsigned> offs
= instr
4177 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4178 : std::make_pair(Temp(), 0u);
4180 if (const_base_offset
)
4181 offs
.second
+= const_base_offset
* attr_stride
;
4183 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4184 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4185 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4190 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4192 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4197 unsigned drv_loc
= nir_intrinsic_base(instr
);
4198 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4200 if (!nir_src_is_const(*off_src
)) {
4206 uint64_t slot
= per_vertex
4207 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4208 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4209 return (((uint64_t) 1) << slot
) & mask
;
4212 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4214 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4215 unsigned component
= nir_intrinsic_component(instr
);
4216 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4218 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4219 if (off_instr
->type
!= nir_instr_type_load_const
)
4222 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4223 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4225 if (instr
->src
[0].ssa
->bit_size
== 64)
4226 write_mask
= widen_mask(write_mask
, 2);
4228 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4230 for (unsigned i
= 0; i
< 8; ++i
) {
4231 if (write_mask
& (1 << i
)) {
4232 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4233 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4241 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4243 /* Only TCS per-vertex inputs are supported by this function.
4244 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4246 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4249 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4250 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4251 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4252 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4253 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4254 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4259 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4260 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4261 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4266 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4268 Builder
bld(ctx
->program
, ctx
->block
);
4270 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4271 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4272 bool indirect_write
;
4273 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4274 if (temp_only_input
&& !indirect_write
)
4278 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4279 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4280 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4281 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4283 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4284 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4285 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4286 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4287 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4291 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4292 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4293 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4294 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4295 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4296 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4297 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4298 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4299 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4300 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4301 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4302 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4303 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4305 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4306 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4308 unreachable("Invalid LS or ES stage");
4311 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4312 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4313 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4317 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4322 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4323 return off
== ctx
->tcs_tess_lvl_out_loc
||
4324 off
== ctx
->tcs_tess_lvl_in_loc
;
4328 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4330 uint64_t mask
= per_vertex
4331 ? ctx
->program
->info
->tcs
.tes_inputs_read
4332 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4334 bool indirect_write
= false;
4335 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4336 return indirect_write
|| output_read_by_tes
;
4339 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4341 uint64_t mask
= per_vertex
4342 ? ctx
->shader
->info
.outputs_read
4343 : ctx
->shader
->info
.patch_outputs_read
;
4345 bool indirect_write
= false;
4346 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4347 return indirect_write
|| output_read
;
4350 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4352 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4353 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4355 Builder
bld(ctx
->program
, ctx
->block
);
4357 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4358 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4359 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4361 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4362 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4363 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4365 if (write_to_vmem
) {
4366 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4367 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4368 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4370 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4371 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4372 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4376 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4377 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4378 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4382 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4384 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4385 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4387 Builder
bld(ctx
->program
, ctx
->block
);
4389 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4390 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4391 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4392 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4394 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4397 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4399 if (ctx
->stage
== vertex_vs
||
4400 ctx
->stage
== tess_eval_vs
||
4401 ctx
->stage
== fragment_fs
||
4402 ctx
->stage
== ngg_vertex_gs
||
4403 ctx
->stage
== ngg_tess_eval_gs
||
4404 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4405 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4406 if (!stored_to_temps
) {
4407 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4408 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4409 fprintf(stderr
, "\n");
4412 } else if (ctx
->stage
== vertex_es
||
4413 ctx
->stage
== vertex_ls
||
4414 ctx
->stage
== tess_eval_es
||
4415 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4416 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4417 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4418 visit_store_ls_or_es_output(ctx
, instr
);
4419 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4420 visit_store_tcs_output(ctx
, instr
, false);
4422 unreachable("Shader stage not implemented");
4426 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4428 visit_load_tcs_output(ctx
, instr
, false);
4431 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4433 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4434 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4436 Builder
bld(ctx
->program
, ctx
->block
);
4438 if (dst
.regClass() == v2b
) {
4439 if (ctx
->program
->has_16bank_lds
) {
4440 assert(ctx
->options
->chip_class
<= GFX8
);
4441 Builder::Result interp_p1
=
4442 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4443 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4444 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4445 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4446 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4447 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4449 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4451 if (ctx
->options
->chip_class
== GFX8
)
4452 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4454 Builder::Result interp_p1
=
4455 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4456 coord1
, bld
.m0(prim_mask
), idx
, component
);
4457 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4458 interp_p1
, idx
, component
);
4461 Builder::Result interp_p1
=
4462 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4463 bld
.m0(prim_mask
), idx
, component
);
4465 if (ctx
->program
->has_16bank_lds
)
4466 interp_p1
.instr
->operands
[0].setLateKill(true);
4468 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4469 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4473 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4475 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4476 for (unsigned i
= 0; i
< num_components
; i
++)
4477 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4478 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4479 assert(num_components
== 4);
4480 Builder
bld(ctx
->program
, ctx
->block
);
4481 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4484 for (Operand
& op
: vec
->operands
)
4485 op
= op
.isUndefined() ? Operand(0u) : op
;
4487 vec
->definitions
[0] = Definition(dst
);
4488 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4489 emit_split_vector(ctx
, dst
, num_components
);
4493 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4495 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4496 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4497 unsigned idx
= nir_intrinsic_base(instr
);
4498 unsigned component
= nir_intrinsic_component(instr
);
4499 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4501 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4503 assert(offset
->u32
== 0);
4505 /* the lower 15bit of the prim_mask contain the offset into LDS
4506 * while the upper bits contain the number of prims */
4507 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4508 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4509 Builder
bld(ctx
->program
, ctx
->block
);
4510 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4511 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4512 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4513 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4514 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4517 if (instr
->dest
.ssa
.num_components
== 1) {
4518 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4520 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4521 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4523 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4524 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4525 vec
->operands
[i
] = Operand(tmp
);
4527 vec
->definitions
[0] = Definition(dst
);
4528 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4532 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4533 unsigned offset
, unsigned stride
, unsigned channels
)
4535 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4536 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4538 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4539 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4542 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4543 unsigned offset
, unsigned stride
, unsigned *channels
)
4545 if (!vtx_info
->chan_byte_size
) {
4546 *channels
= vtx_info
->num_channels
;
4547 return vtx_info
->chan_format
;
4550 unsigned num_channels
= *channels
;
4551 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4552 unsigned new_channels
= num_channels
+ 1;
4553 /* first, assume more loads is worse and try using a larger data format */
4554 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4556 /* don't make the attribute potentially out-of-bounds */
4557 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4561 if (new_channels
== 5) {
4562 /* then try decreasing load size (at the cost of more loads) */
4563 new_channels
= *channels
;
4564 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4568 if (new_channels
< *channels
)
4569 *channels
= new_channels
;
4570 num_channels
= new_channels
;
4573 switch (vtx_info
->chan_format
) {
4574 case V_008F0C_BUF_DATA_FORMAT_8
:
4575 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4576 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4577 case V_008F0C_BUF_DATA_FORMAT_16
:
4578 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4579 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4580 case V_008F0C_BUF_DATA_FORMAT_32
:
4581 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4582 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4584 unreachable("shouldn't reach here");
4585 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4588 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4589 * so we may need to fix it up. */
4590 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4592 Builder
bld(ctx
->program
, ctx
->block
);
4594 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4595 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4597 /* For the integer-like cases, do a natural sign extension.
4599 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4600 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4603 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4604 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4606 /* Convert back to the right type. */
4607 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4608 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4609 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4610 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4611 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4612 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4618 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4620 Builder
bld(ctx
->program
, ctx
->block
);
4621 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4622 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4624 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4625 if (off_instr
->type
!= nir_instr_type_load_const
) {
4626 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4627 nir_print_instr(off_instr
, stderr
);
4628 fprintf(stderr
, "\n");
4630 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4632 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4634 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4635 unsigned component
= nir_intrinsic_component(instr
);
4636 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4637 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4638 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4639 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4640 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4642 unsigned dfmt
= attrib_format
& 0xf;
4643 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4644 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4646 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4647 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4648 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4649 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4651 num_channels
= MAX2(num_channels
, 3);
4653 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4654 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4657 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4658 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4659 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4661 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4663 Temp divided
= bld
.tmp(v1
);
4664 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4665 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4667 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4670 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4673 index
= bld
.vadd32(bld
.def(v1
),
4674 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4675 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4678 Temp channels
[num_channels
];
4679 unsigned channel_start
= 0;
4680 bool direct_fetch
= false;
4682 /* skip unused channels at the start */
4683 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4684 channel_start
= ffs(mask
) - 1;
4685 for (unsigned i
= 0; i
< channel_start
; i
++)
4686 channels
[i
] = Temp(0, s1
);
4687 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4688 num_channels
= 3 - (ffs(mask
) - 1);
4692 while (channel_start
< num_channels
) {
4693 unsigned fetch_component
= num_channels
- channel_start
;
4694 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4695 bool expanded
= false;
4697 /* use MUBUF when possible to avoid possible alignment issues */
4698 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4699 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4700 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4701 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4702 vtx_info
->chan_byte_size
== 4;
4703 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4705 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4707 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4708 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4709 fetch_component
= 4;
4714 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4716 Temp fetch_index
= index
;
4717 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4718 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4719 fetch_offset
= fetch_offset
% attrib_stride
;
4722 Operand
soffset(0u);
4723 if (fetch_offset
>= 4096) {
4724 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4725 fetch_offset
%= 4096;
4729 switch (fetch_bytes
) {
4731 assert(!use_mubuf
&& bitsize
== 16);
4732 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4735 if (bitsize
== 16) {
4737 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4739 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4743 assert(!use_mubuf
&& bitsize
== 16);
4744 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4747 if (bitsize
== 16) {
4749 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4751 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4755 assert(ctx
->options
->chip_class
>= GFX7
||
4756 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4757 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4760 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4763 unreachable("Unimplemented load_input vector size");
4767 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4768 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4769 num_channels
<= 3)) {
4770 direct_fetch
= true;
4773 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4777 Instruction
*mubuf
= bld
.mubuf(opcode
,
4778 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4779 fetch_offset
, false, true).instr
;
4780 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4782 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4783 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4784 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4785 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4788 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4790 if (fetch_component
== 1) {
4791 channels
[channel_start
] = fetch_dst
;
4793 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4794 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4795 bitsize
== 16 ? v2b
: v1
);
4798 channel_start
+= fetch_component
;
4801 if (!direct_fetch
) {
4802 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4803 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4805 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4806 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4807 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4809 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4810 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4811 unsigned num_temp
= 0;
4812 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4813 unsigned idx
= i
+ component
;
4814 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4815 Temp channel
= channels
[swizzle
[idx
]];
4816 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4817 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4818 vec
->operands
[i
] = Operand(channel
);
4822 } else if (is_float
&& idx
== 3) {
4823 vec
->operands
[i
] = Operand(0x3f800000u
);
4824 } else if (!is_float
&& idx
== 3) {
4825 vec
->operands
[i
] = Operand(1u);
4827 vec
->operands
[i
] = Operand(0u);
4830 vec
->definitions
[0] = Definition(dst
);
4831 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4832 emit_split_vector(ctx
, dst
, dst
.size());
4834 if (num_temp
== dst
.size())
4835 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4837 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4838 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4839 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4840 if (off_instr
->type
!= nir_instr_type_load_const
||
4841 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4842 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4843 nir_print_instr(off_instr
, stderr
);
4844 fprintf(stderr
, "\n");
4847 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4848 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4850 assert(offset
->u32
== 0);
4852 /* the lower 15bit of the prim_mask contain the offset into LDS
4853 * while the upper bits contain the number of prims */
4854 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4855 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4856 Builder
bld(ctx
->program
, ctx
->block
);
4857 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4858 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4859 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4860 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4861 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4864 unsigned idx
= nir_intrinsic_base(instr
);
4865 unsigned component
= nir_intrinsic_component(instr
);
4866 unsigned vertex_id
= 2; /* P0 */
4868 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4869 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4870 switch (src0
->u32
) {
4872 vertex_id
= 2; /* P0 */
4875 vertex_id
= 0; /* P10 */
4878 vertex_id
= 1; /* P20 */
4881 unreachable("invalid vertex index");
4885 if (dst
.size() == 1) {
4886 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4888 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4889 for (unsigned i
= 0; i
< dst
.size(); i
++)
4890 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4891 vec
->definitions
[0] = Definition(dst
);
4892 bld
.insert(std::move(vec
));
4895 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4896 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4897 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4898 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4899 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4901 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4903 unreachable("Shader stage not implemented");
4907 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4909 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4911 Builder
bld(ctx
->program
, ctx
->block
);
4912 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4915 if (!nir_src_is_const(*vertex_src
)) {
4916 /* better code could be created, but this case probably doesn't happen
4917 * much in practice */
4918 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4919 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4922 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4923 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4925 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4927 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4930 if (vertex_offset
.id()) {
4931 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4932 Operand(i
), indirect_vertex
);
4933 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4935 vertex_offset
= elem
;
4939 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4940 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4942 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4943 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4944 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4945 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4946 Operand((vertex
% 2u) * 16u), Operand(16u));
4948 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4951 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4952 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4953 return offset_mul(ctx
, offs
, 4u);
4956 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4958 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4960 Builder
bld(ctx
->program
, ctx
->block
);
4961 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4962 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4964 if (ctx
->stage
== geometry_gs
) {
4965 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4966 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4967 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4968 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4969 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4970 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4971 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4973 unreachable("Unsupported GS stage.");
4977 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4979 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4981 Builder
bld(ctx
->program
, ctx
->block
);
4982 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4984 if (load_input_from_temps(ctx
, instr
, dst
))
4987 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4988 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4989 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4991 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4994 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4996 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4998 Builder
bld(ctx
->program
, ctx
->block
);
5000 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
5001 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
5002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5004 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
5005 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
5007 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
5010 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5012 switch (ctx
->shader
->info
.stage
) {
5013 case MESA_SHADER_GEOMETRY
:
5014 visit_load_gs_per_vertex_input(ctx
, instr
);
5016 case MESA_SHADER_TESS_CTRL
:
5017 visit_load_tcs_per_vertex_input(ctx
, instr
);
5019 case MESA_SHADER_TESS_EVAL
:
5020 visit_load_tes_per_vertex_input(ctx
, instr
);
5023 unreachable("Unimplemented shader stage");
5027 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5029 visit_load_tcs_output(ctx
, instr
, true);
5032 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5034 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
5035 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
5037 visit_store_tcs_output(ctx
, instr
, true);
5040 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5042 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5044 Builder
bld(ctx
->program
, ctx
->block
);
5045 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5047 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5048 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5051 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5052 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5053 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5054 tes_w
= Operand(tmp
);
5057 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5058 emit_split_vector(ctx
, tess_coord
, 3);
5061 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5063 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5064 Builder
bld(ctx
->program
, ctx
->block
);
5065 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5066 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5067 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5070 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5074 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5076 Builder
bld(ctx
->program
, ctx
->block
);
5077 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5078 if (!nir_dest_is_divergent(instr
->dest
))
5079 index
= bld
.as_uniform(index
);
5080 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5081 unsigned binding
= nir_intrinsic_binding(instr
);
5084 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5085 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5086 unsigned offset
= layout
->binding
[binding
].offset
;
5088 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5089 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5090 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5091 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5092 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5095 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5096 stride
= layout
->binding
[binding
].size
;
5099 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5100 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5102 if (nir_const_index
) {
5103 const_index
= const_index
* stride
;
5104 } else if (index
.type() == RegType::vgpr
) {
5105 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5106 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5108 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5112 if (nir_const_index
) {
5113 const_index
= const_index
+ offset
;
5114 } else if (index
.type() == RegType::vgpr
) {
5115 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5117 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5121 if (nir_const_index
&& const_index
== 0) {
5123 } else if (index
.type() == RegType::vgpr
) {
5124 index
= bld
.vadd32(bld
.def(v1
),
5125 nir_const_index
? Operand(const_index
) : Operand(index
),
5128 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5129 nir_const_index
? Operand(const_index
) : Operand(index
),
5133 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5136 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5137 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5138 bool glc
=false, bool readonly
=true)
5140 Builder
bld(ctx
->program
, ctx
->block
);
5142 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5144 offset
= bld
.as_uniform(offset
);
5146 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5148 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5149 info
.can_reorder
= readonly
;
5150 info
.align_mul
= align_mul
;
5151 info
.align_offset
= align_offset
;
5153 emit_smem_load(ctx
, bld
, &info
);
5155 emit_mubuf_load(ctx
, bld
, &info
);
5158 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5160 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5161 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5163 Builder
bld(ctx
->program
, ctx
->block
);
5165 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5166 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5167 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5168 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5170 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5171 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5172 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5173 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5174 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5175 if (ctx
->options
->chip_class
>= GFX10
) {
5176 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5177 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5178 S_008F0C_RESOURCE_LEVEL(1);
5180 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5181 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5183 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5184 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5185 Operand(0xFFFFFFFFu
),
5186 Operand(desc_type
));
5187 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5188 rsrc
, upper_dwords
);
5190 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5191 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5193 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5194 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5195 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5198 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5200 Builder
bld(ctx
->program
, ctx
->block
);
5201 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5202 unsigned offset
= nir_intrinsic_base(instr
);
5203 unsigned count
= instr
->dest
.ssa
.num_components
;
5204 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5206 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5207 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5208 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5209 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5210 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5211 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5212 for (unsigned i
= 0; i
< count
; ++i
) {
5213 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5214 vec
->operands
[i
] = Operand
{elems
[i
]};
5216 vec
->definitions
[0] = Definition(dst
);
5217 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5218 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5223 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5224 if (offset
!= 0) // TODO check if index != 0 as well
5225 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5226 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5229 bool aligned
= true;
5231 if (instr
->dest
.ssa
.bit_size
== 8) {
5232 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5233 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5235 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5236 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5237 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5239 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5244 switch (vec
.size()) {
5246 op
= aco_opcode::s_load_dword
;
5249 op
= aco_opcode::s_load_dwordx2
;
5255 op
= aco_opcode::s_load_dwordx4
;
5261 op
= aco_opcode::s_load_dwordx8
;
5264 unreachable("unimplemented or forbidden load_push_constant.");
5267 bld
.smem(op
, Definition(vec
), ptr
, index
);
5270 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5271 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5276 emit_split_vector(ctx
, vec
, 4);
5277 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5278 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5279 emit_extract_vector(ctx
, vec
, 0, rc
),
5280 emit_extract_vector(ctx
, vec
, 1, rc
),
5281 emit_extract_vector(ctx
, vec
, 2, rc
));
5284 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5287 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5289 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5291 Builder
bld(ctx
->program
, ctx
->block
);
5293 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5294 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5295 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5296 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5297 if (ctx
->options
->chip_class
>= GFX10
) {
5298 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5299 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5300 S_008F0C_RESOURCE_LEVEL(1);
5302 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5303 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5306 unsigned base
= nir_intrinsic_base(instr
);
5307 unsigned range
= nir_intrinsic_range(instr
);
5309 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5310 if (base
&& offset
.type() == RegType::sgpr
)
5311 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5312 else if (base
&& offset
.type() == RegType::vgpr
)
5313 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5315 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5316 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5317 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5318 Operand(desc_type
));
5319 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5320 // TODO: get alignment information for subdword constants
5321 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5324 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5326 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5327 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5329 ctx
->program
->needs_exact
= true;
5331 // TODO: optimize uniform conditions
5332 Builder
bld(ctx
->program
, ctx
->block
);
5333 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5334 assert(src
.regClass() == bld
.lm
);
5335 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5336 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5337 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5341 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5343 Builder
bld(ctx
->program
, ctx
->block
);
5345 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5346 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5348 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5349 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5351 if (ctx
->block
->loop_nest_depth
&&
5352 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5353 /* we handle discards the same way as jump instructions */
5354 append_logical_end(ctx
->block
);
5356 /* in loops, discard behaves like break */
5357 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5358 ctx
->block
->kind
|= block_kind_discard
;
5361 /* uniform discard - loop ends here */
5362 assert(nir_instr_is_last(&instr
->instr
));
5363 ctx
->block
->kind
|= block_kind_uniform
;
5364 ctx
->cf_info
.has_branch
= true;
5365 bld
.branch(aco_opcode::p_branch
);
5366 add_linear_edge(ctx
->block
->index
, linear_target
);
5370 /* we add a break right behind the discard() instructions */
5371 ctx
->block
->kind
|= block_kind_break
;
5372 unsigned idx
= ctx
->block
->index
;
5374 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5375 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5377 /* remove critical edges from linear CFG */
5378 bld
.branch(aco_opcode::p_branch
);
5379 Block
* break_block
= ctx
->program
->create_and_insert_block();
5380 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5381 break_block
->kind
|= block_kind_uniform
;
5382 add_linear_edge(idx
, break_block
);
5383 add_linear_edge(break_block
->index
, linear_target
);
5384 bld
.reset(break_block
);
5385 bld
.branch(aco_opcode::p_branch
);
5387 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5388 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5389 add_linear_edge(idx
, continue_block
);
5390 append_logical_start(continue_block
);
5391 ctx
->block
= continue_block
;
5396 /* it can currently happen that NIR doesn't remove the unreachable code */
5397 if (!nir_instr_is_last(&instr
->instr
)) {
5398 ctx
->program
->needs_exact
= true;
5399 /* save exec somewhere temporarily so that it doesn't get
5400 * overwritten before the discard from outer exec masks */
5401 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5402 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5403 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5407 /* This condition is incorrect for uniformly branched discards in a loop
5408 * predicated by a divergent condition, but the above code catches that case
5409 * and the discard would end up turning into a discard_if.
5419 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5420 /* program just ends here */
5421 ctx
->block
->kind
|= block_kind_uniform
;
5422 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5423 0 /* enabled mask */, 9 /* dest */,
5424 false /* compressed */, true/* done */, true /* valid mask */);
5425 bld
.sopp(aco_opcode::s_endpgm
);
5426 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5428 ctx
->block
->kind
|= block_kind_discard
;
5429 /* branch and linear edge is added by visit_if() */
5433 enum aco_descriptor_type
{
5444 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5445 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5447 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5448 return dim
== ac_image_cube
||
5449 dim
== ac_image_1darray
||
5450 dim
== ac_image_2darray
||
5451 dim
== ac_image_2darraymsaa
;
5454 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5455 enum aco_descriptor_type desc_type
,
5456 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5458 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5459 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5460 if (it != ctx->tex_desc.end())
5463 Temp index
= Temp();
5464 bool index_set
= false;
5465 unsigned constant_index
= 0;
5466 unsigned descriptor_set
;
5467 unsigned base_index
;
5468 Builder
bld(ctx
->program
, ctx
->block
);
5471 assert(tex_instr
&& !image
);
5473 base_index
= tex_instr
->sampler_index
;
5475 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5476 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5480 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5481 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5483 constant_index
+= array_size
* const_value
->u32
;
5485 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5486 if (indirect
.type() == RegType::vgpr
)
5487 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5489 if (array_size
!= 1)
5490 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5496 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5500 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5502 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5503 base_index
= deref_instr
->var
->data
.binding
;
5506 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5507 list
= convert_pointer_to_64_bit(ctx
, list
);
5509 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5510 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5511 unsigned offset
= binding
->offset
;
5512 unsigned stride
= binding
->size
;
5516 assert(base_index
< layout
->binding_count
);
5518 switch (desc_type
) {
5519 case ACO_DESC_IMAGE
:
5521 opcode
= aco_opcode::s_load_dwordx8
;
5523 case ACO_DESC_FMASK
:
5525 opcode
= aco_opcode::s_load_dwordx8
;
5528 case ACO_DESC_SAMPLER
:
5530 opcode
= aco_opcode::s_load_dwordx4
;
5531 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5532 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5534 case ACO_DESC_BUFFER
:
5536 opcode
= aco_opcode::s_load_dwordx4
;
5538 case ACO_DESC_PLANE_0
:
5539 case ACO_DESC_PLANE_1
:
5541 opcode
= aco_opcode::s_load_dwordx8
;
5542 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5544 case ACO_DESC_PLANE_2
:
5546 opcode
= aco_opcode::s_load_dwordx4
;
5550 unreachable("invalid desc_type\n");
5553 offset
+= constant_index
* stride
;
5555 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5556 (!index_set
|| binding
->immutable_samplers_equal
)) {
5557 if (binding
->immutable_samplers_equal
)
5560 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5561 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5562 Operand(samplers
[constant_index
* 4 + 0]),
5563 Operand(samplers
[constant_index
* 4 + 1]),
5564 Operand(samplers
[constant_index
* 4 + 2]),
5565 Operand(samplers
[constant_index
* 4 + 3]));
5570 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5572 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5573 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5576 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5578 if (desc_type
== ACO_DESC_PLANE_2
) {
5580 for (unsigned i
= 0; i
< 8; i
++)
5581 components
[i
] = bld
.tmp(s1
);
5582 bld
.pseudo(aco_opcode::p_split_vector
,
5583 Definition(components
[0]),
5584 Definition(components
[1]),
5585 Definition(components
[2]),
5586 Definition(components
[3]),
5589 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5590 bld
.pseudo(aco_opcode::p_split_vector
,
5591 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5592 Definition(components
[4]),
5593 Definition(components
[5]),
5594 Definition(components
[6]),
5595 Definition(components
[7]),
5598 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5599 components
[0], components
[1], components
[2], components
[3],
5600 components
[4], components
[5], components
[6], components
[7]);
5606 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5609 case GLSL_SAMPLER_DIM_BUF
:
5611 case GLSL_SAMPLER_DIM_1D
:
5612 return array
? 2 : 1;
5613 case GLSL_SAMPLER_DIM_2D
:
5614 return array
? 3 : 2;
5615 case GLSL_SAMPLER_DIM_MS
:
5616 return array
? 4 : 3;
5617 case GLSL_SAMPLER_DIM_3D
:
5618 case GLSL_SAMPLER_DIM_CUBE
:
5620 case GLSL_SAMPLER_DIM_RECT
:
5621 case GLSL_SAMPLER_DIM_SUBPASS
:
5623 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5632 /* Adjust the sample index according to FMASK.
5634 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5635 * which is the identity mapping. Each nibble says which physical sample
5636 * should be fetched to get that sample.
5638 * For example, 0x11111100 means there are only 2 samples stored and
5639 * the second sample covers 3/4 of the pixel. When reading samples 0
5640 * and 1, return physical sample 0 (determined by the first two 0s
5641 * in FMASK), otherwise return physical sample 1.
5643 * The sample index should be adjusted as follows:
5644 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5646 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5648 Builder
bld(ctx
->program
, ctx
->block
);
5649 Temp fmask
= bld
.tmp(v1
);
5650 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5651 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5654 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5655 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5656 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5657 load
->operands
[0] = Operand(fmask_desc_ptr
);
5658 load
->operands
[1] = Operand(s4
); /* no sampler */
5659 load
->operands
[2] = Operand(coord
);
5660 load
->definitions
[0] = Definition(fmask
);
5667 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5668 ctx
->block
->instructions
.emplace_back(std::move(load
));
5670 Operand sample_index4
;
5671 if (sample_index
.isConstant()) {
5672 if (sample_index
.constantValue() < 16) {
5673 sample_index4
= Operand(sample_index
.constantValue() << 2);
5675 sample_index4
= Operand(0u);
5677 } else if (sample_index
.regClass() == s1
) {
5678 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5680 assert(sample_index
.regClass() == v1
);
5681 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5685 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5686 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5687 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5688 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5690 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5692 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5693 * resource descriptor is 0 (invalid),
5695 Temp compare
= bld
.tmp(bld
.lm
);
5696 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5697 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5699 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5701 /* Replace the MSAA sample index. */
5702 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5705 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5708 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5709 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5710 bool is_array
= glsl_sampler_type_is_array(type
);
5711 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5712 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5713 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5714 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5715 int count
= image_type_to_components_count(dim
, is_array
);
5716 std::vector
<Temp
> coords(count
);
5717 Builder
bld(ctx
->program
, ctx
->block
);
5721 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5722 /* get sample index */
5723 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5724 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5725 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5726 std::vector
<Temp
> fmask_load_address
;
5727 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5728 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5730 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5731 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5733 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5738 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5739 coords
.resize(coords
.size() + 1);
5740 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5742 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5744 for (int i
= 0; i
< count
; i
++)
5745 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5748 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5749 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5750 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5751 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5754 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5757 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5758 for (unsigned i
= 0; i
< coords
.size(); i
++)
5759 vec
->operands
[i
] = Operand(coords
[i
]);
5760 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5761 vec
->definitions
[0] = Definition(res
);
5762 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5767 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5769 Builder
bld(ctx
->program
, ctx
->block
);
5770 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5771 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5772 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5773 bool is_array
= glsl_sampler_type_is_array(type
);
5774 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5776 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5777 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5778 unsigned num_channels
= util_last_bit(mask
);
5779 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5780 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5783 switch (num_channels
) {
5785 opcode
= aco_opcode::buffer_load_format_x
;
5788 opcode
= aco_opcode::buffer_load_format_xy
;
5791 opcode
= aco_opcode::buffer_load_format_xyz
;
5794 opcode
= aco_opcode::buffer_load_format_xyzw
;
5797 unreachable(">4 channel buffer image load");
5799 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5800 load
->operands
[0] = Operand(rsrc
);
5801 load
->operands
[1] = Operand(vindex
);
5802 load
->operands
[2] = Operand((uint32_t) 0);
5804 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5807 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5808 load
->definitions
[0] = Definition(tmp
);
5810 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5811 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5812 load
->barrier
= barrier_image
;
5813 ctx
->block
->instructions
.emplace_back(std::move(load
));
5815 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5819 Temp coords
= get_image_coords(ctx
, instr
, type
);
5820 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5822 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5823 unsigned num_components
= util_bitcount(dmask
);
5825 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5828 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5830 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5831 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5833 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5834 load
->operands
[0] = Operand(resource
);
5835 load
->operands
[1] = Operand(s4
); /* no sampler */
5836 load
->operands
[2] = Operand(coords
);
5837 load
->definitions
[0] = Definition(tmp
);
5838 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5839 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5840 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5841 load
->dmask
= dmask
;
5843 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5844 load
->barrier
= barrier_image
;
5845 ctx
->block
->instructions
.emplace_back(std::move(load
));
5847 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5851 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5853 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5854 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5855 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5856 bool is_array
= glsl_sampler_type_is_array(type
);
5857 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5859 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5861 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5862 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5863 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5865 switch (data
.size()) {
5867 opcode
= aco_opcode::buffer_store_format_x
;
5870 opcode
= aco_opcode::buffer_store_format_xy
;
5873 opcode
= aco_opcode::buffer_store_format_xyz
;
5876 opcode
= aco_opcode::buffer_store_format_xyzw
;
5879 unreachable(">4 channel buffer image store");
5881 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5882 store
->operands
[0] = Operand(rsrc
);
5883 store
->operands
[1] = Operand(vindex
);
5884 store
->operands
[2] = Operand((uint32_t) 0);
5885 store
->operands
[3] = Operand(data
);
5886 store
->idxen
= true;
5889 store
->disable_wqm
= true;
5890 store
->barrier
= barrier_image
;
5891 ctx
->program
->needs_exact
= true;
5892 ctx
->block
->instructions
.emplace_back(std::move(store
));
5896 assert(data
.type() == RegType::vgpr
);
5897 Temp coords
= get_image_coords(ctx
, instr
, type
);
5898 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5900 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5901 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5903 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5904 store
->operands
[0] = Operand(resource
);
5905 store
->operands
[1] = Operand(data
);
5906 store
->operands
[2] = Operand(coords
);
5909 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5910 store
->dmask
= (1 << data
.size()) - 1;
5912 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5913 store
->disable_wqm
= true;
5914 store
->barrier
= barrier_image
;
5915 ctx
->program
->needs_exact
= true;
5916 ctx
->block
->instructions
.emplace_back(std::move(store
));
5920 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5922 /* return the previous value if dest is ever used */
5923 bool return_previous
= false;
5924 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5925 return_previous
= true;
5928 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5929 return_previous
= true;
5933 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5934 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5935 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5936 bool is_array
= glsl_sampler_type_is_array(type
);
5937 Builder
bld(ctx
->program
, ctx
->block
);
5939 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5940 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5942 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5943 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5945 aco_opcode buf_op
, image_op
;
5946 switch (instr
->intrinsic
) {
5947 case nir_intrinsic_image_deref_atomic_add
:
5948 buf_op
= aco_opcode::buffer_atomic_add
;
5949 image_op
= aco_opcode::image_atomic_add
;
5951 case nir_intrinsic_image_deref_atomic_umin
:
5952 buf_op
= aco_opcode::buffer_atomic_umin
;
5953 image_op
= aco_opcode::image_atomic_umin
;
5955 case nir_intrinsic_image_deref_atomic_imin
:
5956 buf_op
= aco_opcode::buffer_atomic_smin
;
5957 image_op
= aco_opcode::image_atomic_smin
;
5959 case nir_intrinsic_image_deref_atomic_umax
:
5960 buf_op
= aco_opcode::buffer_atomic_umax
;
5961 image_op
= aco_opcode::image_atomic_umax
;
5963 case nir_intrinsic_image_deref_atomic_imax
:
5964 buf_op
= aco_opcode::buffer_atomic_smax
;
5965 image_op
= aco_opcode::image_atomic_smax
;
5967 case nir_intrinsic_image_deref_atomic_and
:
5968 buf_op
= aco_opcode::buffer_atomic_and
;
5969 image_op
= aco_opcode::image_atomic_and
;
5971 case nir_intrinsic_image_deref_atomic_or
:
5972 buf_op
= aco_opcode::buffer_atomic_or
;
5973 image_op
= aco_opcode::image_atomic_or
;
5975 case nir_intrinsic_image_deref_atomic_xor
:
5976 buf_op
= aco_opcode::buffer_atomic_xor
;
5977 image_op
= aco_opcode::image_atomic_xor
;
5979 case nir_intrinsic_image_deref_atomic_exchange
:
5980 buf_op
= aco_opcode::buffer_atomic_swap
;
5981 image_op
= aco_opcode::image_atomic_swap
;
5983 case nir_intrinsic_image_deref_atomic_comp_swap
:
5984 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5985 image_op
= aco_opcode::image_atomic_cmpswap
;
5988 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5991 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5993 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5994 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5995 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5996 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5997 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5998 mubuf
->operands
[0] = Operand(resource
);
5999 mubuf
->operands
[1] = Operand(vindex
);
6000 mubuf
->operands
[2] = Operand((uint32_t)0);
6001 mubuf
->operands
[3] = Operand(data
);
6002 if (return_previous
)
6003 mubuf
->definitions
[0] = Definition(dst
);
6005 mubuf
->idxen
= true;
6006 mubuf
->glc
= return_previous
;
6007 mubuf
->dlc
= false; /* Not needed for atomics */
6008 mubuf
->disable_wqm
= true;
6009 mubuf
->barrier
= barrier_image
;
6010 ctx
->program
->needs_exact
= true;
6011 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6015 Temp coords
= get_image_coords(ctx
, instr
, type
);
6016 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
6017 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
6018 mimg
->operands
[0] = Operand(resource
);
6019 mimg
->operands
[1] = Operand(data
);
6020 mimg
->operands
[2] = Operand(coords
);
6021 if (return_previous
)
6022 mimg
->definitions
[0] = Definition(dst
);
6023 mimg
->glc
= return_previous
;
6024 mimg
->dlc
= false; /* Not needed for atomics */
6025 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6026 mimg
->dmask
= (1 << data
.size()) - 1;
6028 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
6029 mimg
->disable_wqm
= true;
6030 mimg
->barrier
= barrier_image
;
6031 ctx
->program
->needs_exact
= true;
6032 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6036 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
6038 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
6039 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
6040 Builder
bld(ctx
->program
, ctx
->block
);
6042 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6044 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6045 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6047 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6048 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6050 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6051 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6053 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6054 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6055 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6056 if (dst
.type() == RegType::vgpr
)
6057 bld
.copy(Definition(dst
), shr_dst
);
6059 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6061 emit_extract_vector(ctx
, desc
, 2, dst
);
6065 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6067 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6068 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6069 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6070 bool is_array
= glsl_sampler_type_is_array(type
);
6071 Builder
bld(ctx
->program
, ctx
->block
);
6073 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6074 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6075 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6079 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6082 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6084 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6086 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6087 mimg
->operands
[0] = Operand(resource
);
6088 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6089 mimg
->operands
[2] = Operand(lod
);
6090 uint8_t& dmask
= mimg
->dmask
;
6091 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6092 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6093 mimg
->da
= glsl_sampler_type_is_array(type
);
6094 mimg
->can_reorder
= true;
6095 Definition
& def
= mimg
->definitions
[0];
6096 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6098 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6099 glsl_sampler_type_is_array(type
)) {
6101 assert(instr
->dest
.ssa
.num_components
== 3);
6102 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6103 def
= Definition(tmp
);
6104 emit_split_vector(ctx
, tmp
, 3);
6106 /* divide 3rd value by 6 by multiplying with magic number */
6107 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6108 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6110 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6111 emit_extract_vector(ctx
, tmp
, 0, v1
),
6112 emit_extract_vector(ctx
, tmp
, 1, v1
),
6115 } else if (ctx
->options
->chip_class
== GFX9
&&
6116 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6117 glsl_sampler_type_is_array(type
)) {
6118 assert(instr
->dest
.ssa
.num_components
== 2);
6119 def
= Definition(dst
);
6122 def
= Definition(dst
);
6125 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6128 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6130 Builder
bld(ctx
->program
, ctx
->block
);
6131 unsigned num_components
= instr
->num_components
;
6133 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6134 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6135 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6137 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6138 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6139 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6140 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6143 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6145 Builder
bld(ctx
->program
, ctx
->block
);
6146 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6147 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6148 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6149 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6151 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6152 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6154 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6155 ctx
->options
->chip_class
>= GFX8
&&
6156 elem_size_bytes
>= 4;
6158 offset
= bld
.as_uniform(offset
);
6159 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6161 unsigned write_count
= 0;
6162 Temp write_datas
[32];
6163 unsigned offsets
[32];
6164 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6165 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6167 for (unsigned i
= 0; i
< write_count
; i
++) {
6168 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6169 if (smem
&& ctx
->stage
== fragment_fs
)
6170 op
= aco_opcode::p_fs_buffer_store_smem
;
6173 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6174 store
->operands
[0] = Operand(rsrc
);
6176 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6177 offset
, Operand(offsets
[i
]));
6178 store
->operands
[1] = Operand(off
);
6180 store
->operands
[1] = Operand(offset
);
6182 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6183 store
->operands
[1].setFixed(m0
);
6184 store
->operands
[2] = Operand(write_datas
[i
]);
6185 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6187 store
->disable_wqm
= true;
6188 store
->barrier
= barrier_buffer
;
6189 ctx
->block
->instructions
.emplace_back(std::move(store
));
6190 ctx
->program
->wb_smem_l1_on_end
= true;
6191 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6192 ctx
->block
->kind
|= block_kind_needs_lowering
;
6193 ctx
->program
->needs_exact
= true;
6196 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6197 store
->operands
[0] = Operand(rsrc
);
6198 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6199 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6200 store
->operands
[3] = Operand(write_datas
[i
]);
6201 store
->offset
= offsets
[i
];
6202 store
->offen
= (offset
.type() == RegType::vgpr
);
6203 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6205 store
->disable_wqm
= true;
6206 store
->barrier
= barrier_buffer
;
6207 ctx
->program
->needs_exact
= true;
6208 ctx
->block
->instructions
.emplace_back(std::move(store
));
6213 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6215 /* return the previous value if dest is ever used */
6216 bool return_previous
= false;
6217 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6218 return_previous
= true;
6221 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6222 return_previous
= true;
6226 Builder
bld(ctx
->program
, ctx
->block
);
6227 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6229 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6230 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6231 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6233 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6234 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6235 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6237 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6239 aco_opcode op32
, op64
;
6240 switch (instr
->intrinsic
) {
6241 case nir_intrinsic_ssbo_atomic_add
:
6242 op32
= aco_opcode::buffer_atomic_add
;
6243 op64
= aco_opcode::buffer_atomic_add_x2
;
6245 case nir_intrinsic_ssbo_atomic_imin
:
6246 op32
= aco_opcode::buffer_atomic_smin
;
6247 op64
= aco_opcode::buffer_atomic_smin_x2
;
6249 case nir_intrinsic_ssbo_atomic_umin
:
6250 op32
= aco_opcode::buffer_atomic_umin
;
6251 op64
= aco_opcode::buffer_atomic_umin_x2
;
6253 case nir_intrinsic_ssbo_atomic_imax
:
6254 op32
= aco_opcode::buffer_atomic_smax
;
6255 op64
= aco_opcode::buffer_atomic_smax_x2
;
6257 case nir_intrinsic_ssbo_atomic_umax
:
6258 op32
= aco_opcode::buffer_atomic_umax
;
6259 op64
= aco_opcode::buffer_atomic_umax_x2
;
6261 case nir_intrinsic_ssbo_atomic_and
:
6262 op32
= aco_opcode::buffer_atomic_and
;
6263 op64
= aco_opcode::buffer_atomic_and_x2
;
6265 case nir_intrinsic_ssbo_atomic_or
:
6266 op32
= aco_opcode::buffer_atomic_or
;
6267 op64
= aco_opcode::buffer_atomic_or_x2
;
6269 case nir_intrinsic_ssbo_atomic_xor
:
6270 op32
= aco_opcode::buffer_atomic_xor
;
6271 op64
= aco_opcode::buffer_atomic_xor_x2
;
6273 case nir_intrinsic_ssbo_atomic_exchange
:
6274 op32
= aco_opcode::buffer_atomic_swap
;
6275 op64
= aco_opcode::buffer_atomic_swap_x2
;
6277 case nir_intrinsic_ssbo_atomic_comp_swap
:
6278 op32
= aco_opcode::buffer_atomic_cmpswap
;
6279 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6282 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6284 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6285 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6286 mubuf
->operands
[0] = Operand(rsrc
);
6287 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6288 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6289 mubuf
->operands
[3] = Operand(data
);
6290 if (return_previous
)
6291 mubuf
->definitions
[0] = Definition(dst
);
6293 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6294 mubuf
->glc
= return_previous
;
6295 mubuf
->dlc
= false; /* Not needed for atomics */
6296 mubuf
->disable_wqm
= true;
6297 mubuf
->barrier
= barrier_buffer
;
6298 ctx
->program
->needs_exact
= true;
6299 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6302 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6304 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6305 Builder
bld(ctx
->program
, ctx
->block
);
6306 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6307 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6310 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6312 Builder
bld(ctx
->program
, ctx
->block
);
6313 unsigned num_components
= instr
->num_components
;
6314 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6316 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6317 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6318 num_components
, component_size
};
6319 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6320 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6321 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6322 info
.barrier
= barrier_buffer
;
6323 info
.can_reorder
= false;
6324 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6325 * it's safe to use SMEM */
6326 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6327 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6328 emit_global_load(ctx
, bld
, &info
);
6330 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6331 emit_smem_load(ctx
, bld
, &info
);
6335 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6337 Builder
bld(ctx
->program
, ctx
->block
);
6338 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6339 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6341 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6342 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6343 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6345 if (ctx
->options
->chip_class
>= GFX7
)
6346 addr
= as_vgpr(ctx
, addr
);
6348 unsigned write_count
= 0;
6349 Temp write_datas
[32];
6350 unsigned offsets
[32];
6351 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6352 16, &write_count
, write_datas
, offsets
);
6354 for (unsigned i
= 0; i
< write_count
; i
++) {
6355 if (ctx
->options
->chip_class
>= GFX7
) {
6356 unsigned offset
= offsets
[i
];
6357 Temp store_addr
= addr
;
6358 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6359 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6360 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6361 Temp carry
= bld
.tmp(bld
.lm
);
6362 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6364 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6365 Operand(offset
), addr0
);
6366 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6368 carry
).def(1).setHint(vcc
);
6370 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6375 bool global
= ctx
->options
->chip_class
>= GFX9
;
6377 switch (write_datas
[i
].bytes()) {
6379 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6382 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6385 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6388 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6391 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6394 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6397 unreachable("store_global not implemented for this size.");
6400 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6401 flat
->operands
[0] = Operand(store_addr
);
6402 flat
->operands
[1] = Operand(s1
);
6403 flat
->operands
[2] = Operand(write_datas
[i
]);
6406 flat
->offset
= offset
;
6407 flat
->disable_wqm
= true;
6408 flat
->barrier
= barrier_buffer
;
6409 ctx
->program
->needs_exact
= true;
6410 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6412 assert(ctx
->options
->chip_class
== GFX6
);
6414 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6416 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6418 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6419 mubuf
->operands
[0] = Operand(rsrc
);
6420 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6421 mubuf
->operands
[2] = Operand(0u);
6422 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6425 mubuf
->offset
= offsets
[i
];
6426 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6427 mubuf
->disable_wqm
= true;
6428 mubuf
->barrier
= barrier_buffer
;
6429 ctx
->program
->needs_exact
= true;
6430 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6435 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6437 /* return the previous value if dest is ever used */
6438 bool return_previous
= false;
6439 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6440 return_previous
= true;
6443 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6444 return_previous
= true;
6448 Builder
bld(ctx
->program
, ctx
->block
);
6449 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6450 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6452 if (ctx
->options
->chip_class
>= GFX7
)
6453 addr
= as_vgpr(ctx
, addr
);
6455 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6456 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6457 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6459 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6461 aco_opcode op32
, op64
;
6463 if (ctx
->options
->chip_class
>= GFX7
) {
6464 bool global
= ctx
->options
->chip_class
>= GFX9
;
6465 switch (instr
->intrinsic
) {
6466 case nir_intrinsic_global_atomic_add
:
6467 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6468 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6470 case nir_intrinsic_global_atomic_imin
:
6471 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6472 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6474 case nir_intrinsic_global_atomic_umin
:
6475 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6476 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6478 case nir_intrinsic_global_atomic_imax
:
6479 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6480 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6482 case nir_intrinsic_global_atomic_umax
:
6483 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6484 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6486 case nir_intrinsic_global_atomic_and
:
6487 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6488 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6490 case nir_intrinsic_global_atomic_or
:
6491 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6492 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6494 case nir_intrinsic_global_atomic_xor
:
6495 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6496 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6498 case nir_intrinsic_global_atomic_exchange
:
6499 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6500 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6502 case nir_intrinsic_global_atomic_comp_swap
:
6503 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6504 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6507 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6510 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6511 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6512 flat
->operands
[0] = Operand(addr
);
6513 flat
->operands
[1] = Operand(s1
);
6514 flat
->operands
[2] = Operand(data
);
6515 if (return_previous
)
6516 flat
->definitions
[0] = Definition(dst
);
6517 flat
->glc
= return_previous
;
6518 flat
->dlc
= false; /* Not needed for atomics */
6520 flat
->disable_wqm
= true;
6521 flat
->barrier
= barrier_buffer
;
6522 ctx
->program
->needs_exact
= true;
6523 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6525 assert(ctx
->options
->chip_class
== GFX6
);
6527 switch (instr
->intrinsic
) {
6528 case nir_intrinsic_global_atomic_add
:
6529 op32
= aco_opcode::buffer_atomic_add
;
6530 op64
= aco_opcode::buffer_atomic_add_x2
;
6532 case nir_intrinsic_global_atomic_imin
:
6533 op32
= aco_opcode::buffer_atomic_smin
;
6534 op64
= aco_opcode::buffer_atomic_smin_x2
;
6536 case nir_intrinsic_global_atomic_umin
:
6537 op32
= aco_opcode::buffer_atomic_umin
;
6538 op64
= aco_opcode::buffer_atomic_umin_x2
;
6540 case nir_intrinsic_global_atomic_imax
:
6541 op32
= aco_opcode::buffer_atomic_smax
;
6542 op64
= aco_opcode::buffer_atomic_smax_x2
;
6544 case nir_intrinsic_global_atomic_umax
:
6545 op32
= aco_opcode::buffer_atomic_umax
;
6546 op64
= aco_opcode::buffer_atomic_umax_x2
;
6548 case nir_intrinsic_global_atomic_and
:
6549 op32
= aco_opcode::buffer_atomic_and
;
6550 op64
= aco_opcode::buffer_atomic_and_x2
;
6552 case nir_intrinsic_global_atomic_or
:
6553 op32
= aco_opcode::buffer_atomic_or
;
6554 op64
= aco_opcode::buffer_atomic_or_x2
;
6556 case nir_intrinsic_global_atomic_xor
:
6557 op32
= aco_opcode::buffer_atomic_xor
;
6558 op64
= aco_opcode::buffer_atomic_xor_x2
;
6560 case nir_intrinsic_global_atomic_exchange
:
6561 op32
= aco_opcode::buffer_atomic_swap
;
6562 op64
= aco_opcode::buffer_atomic_swap_x2
;
6564 case nir_intrinsic_global_atomic_comp_swap
:
6565 op32
= aco_opcode::buffer_atomic_cmpswap
;
6566 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6569 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6572 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6574 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6576 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6577 mubuf
->operands
[0] = Operand(rsrc
);
6578 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6579 mubuf
->operands
[2] = Operand(0u);
6580 mubuf
->operands
[3] = Operand(data
);
6581 if (return_previous
)
6582 mubuf
->definitions
[0] = Definition(dst
);
6583 mubuf
->glc
= return_previous
;
6586 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6587 mubuf
->disable_wqm
= true;
6588 mubuf
->barrier
= barrier_buffer
;
6589 ctx
->program
->needs_exact
= true;
6590 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6594 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6595 Builder
bld(ctx
->program
, ctx
->block
);
6596 switch(instr
->intrinsic
) {
6597 case nir_intrinsic_group_memory_barrier
:
6598 case nir_intrinsic_memory_barrier
:
6599 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6601 case nir_intrinsic_memory_barrier_buffer
:
6602 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6604 case nir_intrinsic_memory_barrier_image
:
6605 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6607 case nir_intrinsic_memory_barrier_tcs_patch
:
6608 case nir_intrinsic_memory_barrier_shared
:
6609 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6612 unreachable("Unimplemented memory barrier intrinsic");
6617 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6619 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6620 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6621 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6622 Builder
bld(ctx
->program
, ctx
->block
);
6624 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6625 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6626 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6629 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6631 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6632 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6633 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6634 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6636 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6637 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6640 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6642 unsigned offset
= nir_intrinsic_base(instr
);
6643 Builder
bld(ctx
->program
, ctx
->block
);
6644 Operand m
= load_lds_size_m0(bld
);
6645 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6646 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6648 unsigned num_operands
= 3;
6649 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6650 switch(instr
->intrinsic
) {
6651 case nir_intrinsic_shared_atomic_add
:
6652 op32
= aco_opcode::ds_add_u32
;
6653 op64
= aco_opcode::ds_add_u64
;
6654 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6655 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6657 case nir_intrinsic_shared_atomic_imin
:
6658 op32
= aco_opcode::ds_min_i32
;
6659 op64
= aco_opcode::ds_min_i64
;
6660 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6661 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6663 case nir_intrinsic_shared_atomic_umin
:
6664 op32
= aco_opcode::ds_min_u32
;
6665 op64
= aco_opcode::ds_min_u64
;
6666 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6667 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6669 case nir_intrinsic_shared_atomic_imax
:
6670 op32
= aco_opcode::ds_max_i32
;
6671 op64
= aco_opcode::ds_max_i64
;
6672 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6673 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6675 case nir_intrinsic_shared_atomic_umax
:
6676 op32
= aco_opcode::ds_max_u32
;
6677 op64
= aco_opcode::ds_max_u64
;
6678 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6679 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6681 case nir_intrinsic_shared_atomic_and
:
6682 op32
= aco_opcode::ds_and_b32
;
6683 op64
= aco_opcode::ds_and_b64
;
6684 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6685 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6687 case nir_intrinsic_shared_atomic_or
:
6688 op32
= aco_opcode::ds_or_b32
;
6689 op64
= aco_opcode::ds_or_b64
;
6690 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6691 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6693 case nir_intrinsic_shared_atomic_xor
:
6694 op32
= aco_opcode::ds_xor_b32
;
6695 op64
= aco_opcode::ds_xor_b64
;
6696 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6697 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6699 case nir_intrinsic_shared_atomic_exchange
:
6700 op32
= aco_opcode::ds_write_b32
;
6701 op64
= aco_opcode::ds_write_b64
;
6702 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6703 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6705 case nir_intrinsic_shared_atomic_comp_swap
:
6706 op32
= aco_opcode::ds_cmpst_b32
;
6707 op64
= aco_opcode::ds_cmpst_b64
;
6708 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6709 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6713 unreachable("Unhandled shared atomic intrinsic");
6716 /* return the previous value if dest is ever used */
6717 bool return_previous
= false;
6718 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6719 return_previous
= true;
6722 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6723 return_previous
= true;
6728 if (data
.size() == 1) {
6729 assert(instr
->dest
.ssa
.bit_size
== 32);
6730 op
= return_previous
? op32_rtn
: op32
;
6732 assert(instr
->dest
.ssa
.bit_size
== 64);
6733 op
= return_previous
? op64_rtn
: op64
;
6736 if (offset
> 65535) {
6737 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6741 aco_ptr
<DS_instruction
> ds
;
6742 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6743 ds
->operands
[0] = Operand(address
);
6744 ds
->operands
[1] = Operand(data
);
6745 if (num_operands
== 4)
6746 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6747 ds
->operands
[num_operands
- 1] = m
;
6748 ds
->offset0
= offset
;
6749 if (return_previous
)
6750 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6751 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6754 Temp
get_scratch_resource(isel_context
*ctx
)
6756 Builder
bld(ctx
->program
, ctx
->block
);
6757 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6758 if (ctx
->stage
!= compute_cs
)
6759 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6761 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6762 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6764 if (ctx
->program
->chip_class
>= GFX10
) {
6765 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6766 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6767 S_008F0C_RESOURCE_LEVEL(1);
6768 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6769 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6770 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6773 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6774 if (ctx
->program
->chip_class
<= GFX8
)
6775 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6777 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6780 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6781 Builder
bld(ctx
->program
, ctx
->block
);
6782 Temp rsrc
= get_scratch_resource(ctx
);
6783 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6784 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6786 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6787 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6788 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6789 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6790 info
.swizzle_component_size
= 16;
6791 info
.can_reorder
= false;
6792 info
.soffset
= ctx
->program
->scratch_offset
;
6793 emit_mubuf_load(ctx
, bld
, &info
);
6796 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6797 Builder
bld(ctx
->program
, ctx
->block
);
6798 Temp rsrc
= get_scratch_resource(ctx
);
6799 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6800 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6802 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6803 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6805 unsigned write_count
= 0;
6806 Temp write_datas
[32];
6807 unsigned offsets
[32];
6808 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6809 16, &write_count
, write_datas
, offsets
);
6811 for (unsigned i
= 0; i
< write_count
; i
++) {
6812 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6813 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true);
6817 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6818 uint8_t log2_ps_iter_samples
;
6819 if (ctx
->program
->info
->ps
.force_persample
) {
6820 log2_ps_iter_samples
=
6821 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6823 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6826 /* The bit pattern matches that used by fixed function fragment
6828 static const unsigned ps_iter_masks
[] = {
6829 0xffff, /* not used */
6835 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6837 Builder
bld(ctx
->program
, ctx
->block
);
6839 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6840 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6841 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6842 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6843 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6844 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6847 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6848 Builder
bld(ctx
->program
, ctx
->block
);
6850 unsigned stream
= nir_intrinsic_stream_id(instr
);
6851 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6852 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6853 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6856 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6858 unsigned num_components
=
6859 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6860 assert(num_components
);
6862 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6863 unsigned stream_offset
= 0;
6864 for (unsigned i
= 0; i
< stream
; i
++) {
6865 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6866 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6869 /* Limit on the stride field for <= GFX7. */
6870 assert(stride
< (1 << 14));
6872 Temp gsvs_dwords
[4];
6873 for (unsigned i
= 0; i
< 4; i
++)
6874 gsvs_dwords
[i
] = bld
.tmp(s1
);
6875 bld
.pseudo(aco_opcode::p_split_vector
,
6876 Definition(gsvs_dwords
[0]),
6877 Definition(gsvs_dwords
[1]),
6878 Definition(gsvs_dwords
[2]),
6879 Definition(gsvs_dwords
[3]),
6882 if (stream_offset
) {
6883 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6885 Temp carry
= bld
.tmp(s1
);
6886 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6887 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6890 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6891 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6893 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6894 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6896 unsigned offset
= 0;
6897 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6898 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6901 for (unsigned j
= 0; j
< 4; j
++) {
6902 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6905 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6906 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6907 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6908 if (const_offset
>= 4096u) {
6909 if (vaddr_offset
.isUndefined())
6910 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6912 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6913 const_offset
%= 4096u;
6916 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6917 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6918 mtbuf
->operands
[1] = vaddr_offset
;
6919 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6920 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6921 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6922 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6923 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6924 mtbuf
->offset
= const_offset
;
6927 mtbuf
->barrier
= barrier_gs_data
;
6928 mtbuf
->can_reorder
= true;
6929 bld
.insert(std::move(mtbuf
));
6932 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6935 /* outputs for the next vertex are undefined and keeping them around can
6936 * create invalid IR with control flow */
6937 ctx
->outputs
.mask
[i
] = 0;
6940 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6943 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6945 Builder
bld(ctx
->program
, ctx
->block
);
6947 if (cluster_size
== 1) {
6949 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6950 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6951 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6952 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6953 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6954 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6955 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6956 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6957 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6958 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6959 //subgroupAnd(val) -> (exec & ~val) == 0
6960 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6961 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6962 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6963 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6964 //subgroupOr(val) -> (val & exec) != 0
6965 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6966 return bool_to_vector_condition(ctx
, tmp
);
6967 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6968 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6969 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6970 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6971 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6972 return bool_to_vector_condition(ctx
, tmp
);
6974 //subgroupClustered{And,Or,Xor}(val, n) ->
6975 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6976 //cluster_offset = ~(n - 1) & lane_id
6977 //cluster_mask = ((1 << n) - 1)
6978 //subgroupClusteredAnd():
6979 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6980 //subgroupClusteredOr():
6981 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6982 //subgroupClusteredXor():
6983 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6984 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6985 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6988 if (op
== nir_op_iand
)
6989 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6991 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6993 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6995 if (ctx
->program
->chip_class
<= GFX7
)
6996 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6997 else if (ctx
->program
->wave_size
== 64)
6998 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7000 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7001 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7002 if (cluster_mask
!= 0xffffffff)
7003 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7005 Definition cmp_def
= Definition();
7006 if (op
== nir_op_iand
) {
7007 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7008 } else if (op
== nir_op_ior
) {
7009 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7010 } else if (op
== nir_op_ixor
) {
7011 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7012 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7013 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7015 cmp_def
.setHint(vcc
);
7016 return cmp_def
.getTemp();
7020 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7022 Builder
bld(ctx
->program
, ctx
->block
);
7024 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7025 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7026 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7028 if (op
== nir_op_iand
)
7029 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7031 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7033 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7034 Temp lo
= lohi
.def(0).getTemp();
7035 Temp hi
= lohi
.def(1).getTemp();
7036 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7038 Definition cmp_def
= Definition();
7039 if (op
== nir_op_iand
)
7040 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7041 else if (op
== nir_op_ior
)
7042 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7043 else if (op
== nir_op_ixor
)
7044 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7045 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7046 cmp_def
.setHint(vcc
);
7047 return cmp_def
.getTemp();
7050 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7052 Builder
bld(ctx
->program
, ctx
->block
);
7054 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7055 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7056 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7057 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7058 if (op
== nir_op_iand
)
7059 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7060 else if (op
== nir_op_ior
)
7061 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7062 else if (op
== nir_op_ixor
)
7063 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7069 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7071 Builder
bld(ctx
->program
, ctx
->block
);
7072 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7073 if (src
.regClass().type() == RegType::vgpr
) {
7074 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7075 } else if (src
.regClass() == s1
) {
7076 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7077 } else if (src
.regClass() == s2
) {
7078 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7080 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7081 nir_print_instr(&instr
->instr
, stderr
);
7082 fprintf(stderr
, "\n");
7086 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7088 Builder
bld(ctx
->program
, ctx
->block
);
7089 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7090 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7091 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7093 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7094 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7095 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7096 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7099 if (ctx
->program
->chip_class
>= GFX8
) {
7100 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7101 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7102 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7103 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7104 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7105 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7107 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7108 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7109 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7110 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7111 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7112 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7113 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7114 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7115 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7116 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7119 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7120 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7121 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7122 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7123 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7124 Temp wqm1
= bld
.tmp(v1
);
7125 emit_wqm(ctx
, tmp1
, wqm1
, true);
7126 Temp wqm2
= bld
.tmp(v1
);
7127 emit_wqm(ctx
, tmp2
, wqm2
, true);
7128 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7132 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7134 Builder
bld(ctx
->program
, ctx
->block
);
7135 switch(instr
->intrinsic
) {
7136 case nir_intrinsic_load_barycentric_sample
:
7137 case nir_intrinsic_load_barycentric_pixel
:
7138 case nir_intrinsic_load_barycentric_centroid
: {
7139 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7140 Temp bary
= Temp(0, s2
);
7142 case INTERP_MODE_SMOOTH
:
7143 case INTERP_MODE_NONE
:
7144 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7145 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7146 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7147 bary
= ctx
->persp_centroid
;
7148 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7149 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7151 case INTERP_MODE_NOPERSPECTIVE
:
7152 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7153 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7154 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7155 bary
= ctx
->linear_centroid
;
7156 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7157 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7162 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7163 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7164 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7165 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7166 Operand(p1
), Operand(p2
));
7167 emit_split_vector(ctx
, dst
, 2);
7170 case nir_intrinsic_load_barycentric_model
: {
7171 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7173 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7174 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7175 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7176 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7177 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7178 Operand(p1
), Operand(p2
), Operand(p3
));
7179 emit_split_vector(ctx
, dst
, 3);
7182 case nir_intrinsic_load_barycentric_at_sample
: {
7183 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7184 switch (ctx
->options
->key
.fs
.num_samples
) {
7185 case 2: sample_pos_offset
+= 1 << 3; break;
7186 case 4: sample_pos_offset
+= 3 << 3; break;
7187 case 8: sample_pos_offset
+= 7 << 3; break;
7191 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7192 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7193 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7194 if (addr
.type() == RegType::sgpr
) {
7197 sample_pos_offset
+= const_addr
->u32
<< 3;
7198 offset
= Operand(sample_pos_offset
);
7199 } else if (ctx
->options
->chip_class
>= GFX9
) {
7200 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7202 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7203 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7206 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7207 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7209 } else if (ctx
->options
->chip_class
>= GFX9
) {
7210 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7211 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7212 } else if (ctx
->options
->chip_class
>= GFX7
) {
7213 /* addr += private_segment_buffer + sample_pos_offset */
7214 Temp tmp0
= bld
.tmp(s1
);
7215 Temp tmp1
= bld
.tmp(s1
);
7216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7217 Definition scc_tmp
= bld
.def(s1
, scc
);
7218 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7219 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7220 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7221 Temp pck0
= bld
.tmp(v1
);
7222 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7223 tmp1
= as_vgpr(ctx
, tmp1
);
7224 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7225 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7227 /* sample_pos = flat_load_dwordx2 addr */
7228 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7230 assert(ctx
->options
->chip_class
== GFX6
);
7232 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7233 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7234 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7236 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7237 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7239 sample_pos
= bld
.tmp(v2
);
7241 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7242 load
->definitions
[0] = Definition(sample_pos
);
7243 load
->operands
[0] = Operand(rsrc
);
7244 load
->operands
[1] = Operand(addr
);
7245 load
->operands
[2] = Operand(0u);
7246 load
->offset
= sample_pos_offset
;
7248 load
->addr64
= true;
7251 load
->disable_wqm
= false;
7252 load
->barrier
= barrier_none
;
7253 load
->can_reorder
= true;
7254 ctx
->block
->instructions
.emplace_back(std::move(load
));
7257 /* sample_pos -= 0.5 */
7258 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7259 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7260 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7261 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7262 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7264 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7267 case nir_intrinsic_load_barycentric_at_offset
: {
7268 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7269 RegClass rc
= RegClass(offset
.type(), 1);
7270 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7271 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7272 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7275 case nir_intrinsic_load_front_face
: {
7276 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7277 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7280 case nir_intrinsic_load_view_index
: {
7281 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7282 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7283 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7289 case nir_intrinsic_load_layer_id
: {
7290 unsigned idx
= nir_intrinsic_base(instr
);
7291 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7292 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7295 case nir_intrinsic_load_frag_coord
: {
7296 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7299 case nir_intrinsic_load_sample_pos
: {
7300 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7301 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7303 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7304 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7307 case nir_intrinsic_load_tess_coord
:
7308 visit_load_tess_coord(ctx
, instr
);
7310 case nir_intrinsic_load_interpolated_input
:
7311 visit_load_interpolated_input(ctx
, instr
);
7313 case nir_intrinsic_store_output
:
7314 visit_store_output(ctx
, instr
);
7316 case nir_intrinsic_load_input
:
7317 case nir_intrinsic_load_input_vertex
:
7318 visit_load_input(ctx
, instr
);
7320 case nir_intrinsic_load_output
:
7321 visit_load_output(ctx
, instr
);
7323 case nir_intrinsic_load_per_vertex_input
:
7324 visit_load_per_vertex_input(ctx
, instr
);
7326 case nir_intrinsic_load_per_vertex_output
:
7327 visit_load_per_vertex_output(ctx
, instr
);
7329 case nir_intrinsic_store_per_vertex_output
:
7330 visit_store_per_vertex_output(ctx
, instr
);
7332 case nir_intrinsic_load_ubo
:
7333 visit_load_ubo(ctx
, instr
);
7335 case nir_intrinsic_load_push_constant
:
7336 visit_load_push_constant(ctx
, instr
);
7338 case nir_intrinsic_load_constant
:
7339 visit_load_constant(ctx
, instr
);
7341 case nir_intrinsic_vulkan_resource_index
:
7342 visit_load_resource(ctx
, instr
);
7344 case nir_intrinsic_discard
:
7345 visit_discard(ctx
, instr
);
7347 case nir_intrinsic_discard_if
:
7348 visit_discard_if(ctx
, instr
);
7350 case nir_intrinsic_load_shared
:
7351 visit_load_shared(ctx
, instr
);
7353 case nir_intrinsic_store_shared
:
7354 visit_store_shared(ctx
, instr
);
7356 case nir_intrinsic_shared_atomic_add
:
7357 case nir_intrinsic_shared_atomic_imin
:
7358 case nir_intrinsic_shared_atomic_umin
:
7359 case nir_intrinsic_shared_atomic_imax
:
7360 case nir_intrinsic_shared_atomic_umax
:
7361 case nir_intrinsic_shared_atomic_and
:
7362 case nir_intrinsic_shared_atomic_or
:
7363 case nir_intrinsic_shared_atomic_xor
:
7364 case nir_intrinsic_shared_atomic_exchange
:
7365 case nir_intrinsic_shared_atomic_comp_swap
:
7366 visit_shared_atomic(ctx
, instr
);
7368 case nir_intrinsic_image_deref_load
:
7369 visit_image_load(ctx
, instr
);
7371 case nir_intrinsic_image_deref_store
:
7372 visit_image_store(ctx
, instr
);
7374 case nir_intrinsic_image_deref_atomic_add
:
7375 case nir_intrinsic_image_deref_atomic_umin
:
7376 case nir_intrinsic_image_deref_atomic_imin
:
7377 case nir_intrinsic_image_deref_atomic_umax
:
7378 case nir_intrinsic_image_deref_atomic_imax
:
7379 case nir_intrinsic_image_deref_atomic_and
:
7380 case nir_intrinsic_image_deref_atomic_or
:
7381 case nir_intrinsic_image_deref_atomic_xor
:
7382 case nir_intrinsic_image_deref_atomic_exchange
:
7383 case nir_intrinsic_image_deref_atomic_comp_swap
:
7384 visit_image_atomic(ctx
, instr
);
7386 case nir_intrinsic_image_deref_size
:
7387 visit_image_size(ctx
, instr
);
7389 case nir_intrinsic_load_ssbo
:
7390 visit_load_ssbo(ctx
, instr
);
7392 case nir_intrinsic_store_ssbo
:
7393 visit_store_ssbo(ctx
, instr
);
7395 case nir_intrinsic_load_global
:
7396 visit_load_global(ctx
, instr
);
7398 case nir_intrinsic_store_global
:
7399 visit_store_global(ctx
, instr
);
7401 case nir_intrinsic_global_atomic_add
:
7402 case nir_intrinsic_global_atomic_imin
:
7403 case nir_intrinsic_global_atomic_umin
:
7404 case nir_intrinsic_global_atomic_imax
:
7405 case nir_intrinsic_global_atomic_umax
:
7406 case nir_intrinsic_global_atomic_and
:
7407 case nir_intrinsic_global_atomic_or
:
7408 case nir_intrinsic_global_atomic_xor
:
7409 case nir_intrinsic_global_atomic_exchange
:
7410 case nir_intrinsic_global_atomic_comp_swap
:
7411 visit_global_atomic(ctx
, instr
);
7413 case nir_intrinsic_ssbo_atomic_add
:
7414 case nir_intrinsic_ssbo_atomic_imin
:
7415 case nir_intrinsic_ssbo_atomic_umin
:
7416 case nir_intrinsic_ssbo_atomic_imax
:
7417 case nir_intrinsic_ssbo_atomic_umax
:
7418 case nir_intrinsic_ssbo_atomic_and
:
7419 case nir_intrinsic_ssbo_atomic_or
:
7420 case nir_intrinsic_ssbo_atomic_xor
:
7421 case nir_intrinsic_ssbo_atomic_exchange
:
7422 case nir_intrinsic_ssbo_atomic_comp_swap
:
7423 visit_atomic_ssbo(ctx
, instr
);
7425 case nir_intrinsic_load_scratch
:
7426 visit_load_scratch(ctx
, instr
);
7428 case nir_intrinsic_store_scratch
:
7429 visit_store_scratch(ctx
, instr
);
7431 case nir_intrinsic_get_buffer_size
:
7432 visit_get_buffer_size(ctx
, instr
);
7434 case nir_intrinsic_control_barrier
: {
7435 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7436 /* GFX6 only (thanks to a hw bug workaround):
7437 * The real barrier instruction isn’t needed, because an entire patch
7438 * always fits into a single wave.
7443 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7444 bld
.sopp(aco_opcode::s_barrier
);
7448 case nir_intrinsic_memory_barrier_tcs_patch
:
7449 case nir_intrinsic_group_memory_barrier
:
7450 case nir_intrinsic_memory_barrier
:
7451 case nir_intrinsic_memory_barrier_buffer
:
7452 case nir_intrinsic_memory_barrier_image
:
7453 case nir_intrinsic_memory_barrier_shared
:
7454 emit_memory_barrier(ctx
, instr
);
7456 case nir_intrinsic_load_num_work_groups
: {
7457 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7458 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7459 emit_split_vector(ctx
, dst
, 3);
7462 case nir_intrinsic_load_local_invocation_id
: {
7463 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7464 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7465 emit_split_vector(ctx
, dst
, 3);
7468 case nir_intrinsic_load_work_group_id
: {
7469 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7470 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7471 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7472 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7473 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7474 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7475 emit_split_vector(ctx
, dst
, 3);
7478 case nir_intrinsic_load_local_invocation_index
: {
7479 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7481 /* The tg_size bits [6:11] contain the subgroup id,
7482 * we need this multiplied by the wave size, and then OR the thread id to it.
7484 if (ctx
->program
->wave_size
== 64) {
7485 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7486 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7487 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7488 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7490 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7491 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7492 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7493 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7497 case nir_intrinsic_load_subgroup_id
: {
7498 if (ctx
->stage
== compute_cs
) {
7499 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7500 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7502 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7506 case nir_intrinsic_load_subgroup_invocation
: {
7507 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7510 case nir_intrinsic_load_num_subgroups
: {
7511 if (ctx
->stage
== compute_cs
)
7512 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7513 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7515 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7518 case nir_intrinsic_ballot
: {
7519 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7520 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7521 Definition tmp
= bld
.def(dst
.regClass());
7522 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7523 if (instr
->src
[0].ssa
->bit_size
== 1) {
7524 assert(src
.regClass() == bld
.lm
);
7525 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7526 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7527 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7528 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7529 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7531 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7532 nir_print_instr(&instr
->instr
, stderr
);
7533 fprintf(stderr
, "\n");
7535 if (dst
.size() != bld
.lm
.size()) {
7536 /* Wave32 with ballot size set to 64 */
7537 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7539 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7542 case nir_intrinsic_shuffle
:
7543 case nir_intrinsic_read_invocation
: {
7544 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7545 if (!nir_src_is_divergent(instr
->src
[0])) {
7546 emit_uniform_subgroup(ctx
, instr
, src
);
7548 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7549 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7550 tid
= bld
.as_uniform(tid
);
7551 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7552 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7553 Temp tmp
= bld
.tmp(v1
);
7554 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7555 if (dst
.type() == RegType::vgpr
)
7556 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7558 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7559 } else if (src
.regClass() == v1
) {
7560 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7561 } else if (src
.regClass() == v2
) {
7562 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7563 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7564 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7565 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7566 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7567 emit_split_vector(ctx
, dst
, 2);
7568 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7569 assert(src
.regClass() == bld
.lm
);
7570 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7571 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7572 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7573 assert(src
.regClass() == bld
.lm
);
7575 if (ctx
->program
->chip_class
<= GFX7
)
7576 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7577 else if (ctx
->program
->wave_size
== 64)
7578 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7580 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7581 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7582 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7583 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7585 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7586 nir_print_instr(&instr
->instr
, stderr
);
7587 fprintf(stderr
, "\n");
7592 case nir_intrinsic_load_sample_id
: {
7593 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7594 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7597 case nir_intrinsic_load_sample_mask_in
: {
7598 visit_load_sample_mask_in(ctx
, instr
);
7601 case nir_intrinsic_read_first_invocation
: {
7602 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7603 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7604 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7606 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7608 } else if (src
.regClass() == v2
) {
7609 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7610 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7611 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7612 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7613 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7614 emit_split_vector(ctx
, dst
, 2);
7615 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7616 assert(src
.regClass() == bld
.lm
);
7617 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7618 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7619 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7620 } else if (src
.regClass() == s1
) {
7621 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7622 } else if (src
.regClass() == s2
) {
7623 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7625 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7626 nir_print_instr(&instr
->instr
, stderr
);
7627 fprintf(stderr
, "\n");
7631 case nir_intrinsic_vote_all
: {
7632 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7633 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7634 assert(src
.regClass() == bld
.lm
);
7635 assert(dst
.regClass() == bld
.lm
);
7637 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7638 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7639 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7642 case nir_intrinsic_vote_any
: {
7643 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7644 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7645 assert(src
.regClass() == bld
.lm
);
7646 assert(dst
.regClass() == bld
.lm
);
7648 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7649 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7652 case nir_intrinsic_reduce
:
7653 case nir_intrinsic_inclusive_scan
:
7654 case nir_intrinsic_exclusive_scan
: {
7655 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7656 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7657 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7658 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7659 nir_intrinsic_cluster_size(instr
) : 0;
7660 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7662 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7663 emit_uniform_subgroup(ctx
, instr
, src
);
7664 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7665 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7667 else if (op
== nir_op_iadd
)
7669 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7671 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7673 switch (instr
->intrinsic
) {
7674 case nir_intrinsic_reduce
:
7675 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7677 case nir_intrinsic_exclusive_scan
:
7678 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7680 case nir_intrinsic_inclusive_scan
:
7681 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7686 } else if (cluster_size
== 1) {
7687 bld
.copy(Definition(dst
), src
);
7689 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7691 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7695 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7696 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7711 unreachable("unknown reduction op");
7717 switch (instr
->intrinsic
) {
7718 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7719 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7720 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7722 unreachable("unknown reduce intrinsic");
7725 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7726 reduce
->operands
[0] = Operand(src
);
7727 // filled in by aco_reduce_assign.cpp, used internally as part of the
7729 assert(dst
.size() == 1 || dst
.size() == 2);
7730 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7731 reduce
->operands
[2] = Operand(v1
.as_linear());
7733 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7734 reduce
->definitions
[0] = Definition(tmp_dst
);
7735 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7736 reduce
->definitions
[2] = Definition();
7737 reduce
->definitions
[3] = Definition(scc
, s1
);
7738 reduce
->definitions
[4] = Definition();
7739 reduce
->reduce_op
= reduce_op
;
7740 reduce
->cluster_size
= cluster_size
;
7741 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7743 emit_wqm(ctx
, tmp_dst
, dst
);
7747 case nir_intrinsic_quad_broadcast
: {
7748 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7749 if (!nir_dest_is_divergent(instr
->dest
)) {
7750 emit_uniform_subgroup(ctx
, instr
, src
);
7752 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7753 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7754 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7756 if (instr
->dest
.ssa
.bit_size
== 1) {
7757 assert(src
.regClass() == bld
.lm
);
7758 assert(dst
.regClass() == bld
.lm
);
7759 uint32_t half_mask
= 0x11111111u
<< lane
;
7760 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7761 Temp tmp
= bld
.tmp(bld
.lm
);
7762 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7763 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7764 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7765 emit_wqm(ctx
, tmp
, dst
);
7766 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7767 Temp tmp
= bld
.tmp(v1
);
7768 if (ctx
->program
->chip_class
>= GFX8
)
7769 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7771 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7772 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7773 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7774 Temp tmp
= bld
.tmp(v1
);
7775 if (ctx
->program
->chip_class
>= GFX8
)
7776 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7778 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7779 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7780 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7781 if (ctx
->program
->chip_class
>= GFX8
)
7782 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7784 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7785 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7786 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7787 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7788 if (ctx
->program
->chip_class
>= GFX8
) {
7789 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7790 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7792 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7793 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7795 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7796 emit_split_vector(ctx
, dst
, 2);
7798 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7799 nir_print_instr(&instr
->instr
, stderr
);
7800 fprintf(stderr
, "\n");
7805 case nir_intrinsic_quad_swap_horizontal
:
7806 case nir_intrinsic_quad_swap_vertical
:
7807 case nir_intrinsic_quad_swap_diagonal
:
7808 case nir_intrinsic_quad_swizzle_amd
: {
7809 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7810 if (!nir_dest_is_divergent(instr
->dest
)) {
7811 emit_uniform_subgroup(ctx
, instr
, src
);
7814 uint16_t dpp_ctrl
= 0;
7815 switch (instr
->intrinsic
) {
7816 case nir_intrinsic_quad_swap_horizontal
:
7817 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7819 case nir_intrinsic_quad_swap_vertical
:
7820 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7822 case nir_intrinsic_quad_swap_diagonal
:
7823 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7825 case nir_intrinsic_quad_swizzle_amd
:
7826 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7831 if (ctx
->program
->chip_class
< GFX8
)
7832 dpp_ctrl
|= (1 << 15);
7834 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7835 if (instr
->dest
.ssa
.bit_size
== 1) {
7836 assert(src
.regClass() == bld
.lm
);
7837 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7838 if (ctx
->program
->chip_class
>= GFX8
)
7839 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7841 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7842 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7843 emit_wqm(ctx
, tmp
, dst
);
7844 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7845 Temp tmp
= bld
.tmp(v1
);
7846 if (ctx
->program
->chip_class
>= GFX8
)
7847 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7849 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7850 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7851 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7852 Temp tmp
= bld
.tmp(v1
);
7853 if (ctx
->program
->chip_class
>= GFX8
)
7854 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7856 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7857 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7858 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7860 if (ctx
->program
->chip_class
>= GFX8
)
7861 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7863 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7864 emit_wqm(ctx
, tmp
, dst
);
7865 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7866 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7867 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7868 if (ctx
->program
->chip_class
>= GFX8
) {
7869 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7870 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7872 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7873 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7875 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7876 emit_split_vector(ctx
, dst
, 2);
7878 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7879 nir_print_instr(&instr
->instr
, stderr
);
7880 fprintf(stderr
, "\n");
7884 case nir_intrinsic_masked_swizzle_amd
: {
7885 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7886 if (!nir_dest_is_divergent(instr
->dest
)) {
7887 emit_uniform_subgroup(ctx
, instr
, src
);
7890 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7891 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7892 if (dst
.regClass() == v1
) {
7894 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7896 } else if (dst
.regClass() == v2
) {
7897 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7899 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7900 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7901 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7902 emit_split_vector(ctx
, dst
, 2);
7904 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7905 nir_print_instr(&instr
->instr
, stderr
);
7906 fprintf(stderr
, "\n");
7910 case nir_intrinsic_write_invocation_amd
: {
7911 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7912 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7913 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7914 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7915 if (dst
.regClass() == v1
) {
7916 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7917 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7918 } else if (dst
.regClass() == v2
) {
7919 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7920 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7921 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7922 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7923 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7924 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7925 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7926 emit_split_vector(ctx
, dst
, 2);
7928 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7929 nir_print_instr(&instr
->instr
, stderr
);
7930 fprintf(stderr
, "\n");
7934 case nir_intrinsic_mbcnt_amd
: {
7935 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7936 RegClass rc
= RegClass(src
.type(), 1);
7937 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7938 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7940 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7941 emit_wqm(ctx
, wqm_tmp
, dst
);
7944 case nir_intrinsic_load_helper_invocation
: {
7945 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7946 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7947 ctx
->block
->kind
|= block_kind_needs_lowering
;
7948 ctx
->program
->needs_exact
= true;
7951 case nir_intrinsic_is_helper_invocation
: {
7952 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7953 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7954 ctx
->block
->kind
|= block_kind_needs_lowering
;
7955 ctx
->program
->needs_exact
= true;
7958 case nir_intrinsic_demote
:
7959 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7961 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7962 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7963 ctx
->block
->kind
|= block_kind_uses_demote
;
7964 ctx
->program
->needs_exact
= true;
7966 case nir_intrinsic_demote_if
: {
7967 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7968 assert(src
.regClass() == bld
.lm
);
7969 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7970 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7972 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7973 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7974 ctx
->block
->kind
|= block_kind_uses_demote
;
7975 ctx
->program
->needs_exact
= true;
7978 case nir_intrinsic_first_invocation
: {
7979 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7980 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7983 case nir_intrinsic_shader_clock
: {
7985 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7986 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7987 bld
.smem(opcode
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
7988 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
7991 case nir_intrinsic_load_vertex_id_zero_base
: {
7992 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7993 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7996 case nir_intrinsic_load_first_vertex
: {
7997 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7998 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8001 case nir_intrinsic_load_base_instance
: {
8002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8003 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8006 case nir_intrinsic_load_instance_id
: {
8007 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8008 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8011 case nir_intrinsic_load_draw_id
: {
8012 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8013 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8016 case nir_intrinsic_load_invocation_id
: {
8017 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8019 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8020 if (ctx
->options
->chip_class
>= GFX10
)
8021 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8023 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8024 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8025 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8026 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8028 unreachable("Unsupported stage for load_invocation_id");
8033 case nir_intrinsic_load_primitive_id
: {
8034 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8036 switch (ctx
->shader
->info
.stage
) {
8037 case MESA_SHADER_GEOMETRY
:
8038 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8040 case MESA_SHADER_TESS_CTRL
:
8041 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8043 case MESA_SHADER_TESS_EVAL
:
8044 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8047 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8052 case nir_intrinsic_load_patch_vertices_in
: {
8053 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8054 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8056 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8057 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8060 case nir_intrinsic_emit_vertex_with_counter
: {
8061 visit_emit_vertex_with_counter(ctx
, instr
);
8064 case nir_intrinsic_end_primitive_with_counter
: {
8065 unsigned stream
= nir_intrinsic_stream_id(instr
);
8066 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8069 case nir_intrinsic_set_vertex_count
: {
8070 /* unused, the HW keeps track of this for us */
8074 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8075 nir_print_instr(&instr
->instr
, stderr
);
8076 fprintf(stderr
, "\n");
8084 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8085 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8086 enum glsl_base_type
*stype
)
8088 nir_deref_instr
*texture_deref_instr
= NULL
;
8089 nir_deref_instr
*sampler_deref_instr
= NULL
;
8092 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8093 switch (instr
->src
[i
].src_type
) {
8094 case nir_tex_src_texture_deref
:
8095 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8097 case nir_tex_src_sampler_deref
:
8098 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8100 case nir_tex_src_plane
:
8101 plane
= nir_src_as_int(instr
->src
[i
].src
);
8108 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8110 if (!sampler_deref_instr
)
8111 sampler_deref_instr
= texture_deref_instr
;
8114 assert(instr
->op
!= nir_texop_txf_ms
&&
8115 instr
->op
!= nir_texop_samples_identical
);
8116 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8117 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8118 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8119 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8120 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8121 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8123 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8126 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8128 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8129 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8130 Builder
bld(ctx
->program
, ctx
->block
);
8132 /* to avoid unnecessary moves, we split and recombine sampler and image */
8133 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8134 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8135 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8136 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8137 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8138 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8139 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8140 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8142 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8143 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8144 img
[0], img
[1], img
[2], img
[3],
8145 img
[4], img
[5], img
[6], img
[7]);
8146 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8147 samp
[0], samp
[1], samp
[2], samp
[3]);
8150 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8151 instr
->op
== nir_texop_samples_identical
))
8152 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8155 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8156 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8158 Builder
bld(ctx
->program
, ctx
->block
);
8160 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8161 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8162 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8164 Operand
neg_one(0xbf800000u
);
8165 Operand
one(0x3f800000u
);
8166 Operand
two(0x40000000u
);
8167 Operand
four(0x40800000u
);
8169 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8170 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8171 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8173 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8174 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8175 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8176 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8179 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8180 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8181 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8183 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8186 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8187 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8188 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8191 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8192 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8194 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8195 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8198 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8200 Builder
bld(ctx
->program
, ctx
->block
);
8201 Temp ma
, tc
, sc
, id
;
8204 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8206 // see comment in ac_prepare_cube_coords()
8207 if (ctx
->options
->chip_class
<= GFX8
)
8208 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8211 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8213 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8214 vop3a
->operands
[0] = Operand(ma
);
8215 vop3a
->abs
[0] = true;
8216 Temp invma
= bld
.tmp(v1
);
8217 vop3a
->definitions
[0] = Definition(invma
);
8218 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8220 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8222 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8224 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8226 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8228 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8231 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8232 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8234 for (unsigned i
= 0; i
< 2; i
++) {
8235 // see comment in ac_prepare_cube_coords()
8237 Temp deriv_sc
, deriv_tc
;
8238 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8239 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8241 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8243 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8244 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8245 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8246 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8247 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8248 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8249 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8252 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8253 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8257 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8264 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8266 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8268 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8269 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8272 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8273 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8274 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8278 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8280 Builder
bld(ctx
->program
, ctx
->block
);
8281 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8282 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8283 has_clamped_lod
= false;
8284 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8285 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8286 clamped_lod
= Temp();
8287 std::vector
<Temp
> coords
;
8288 std::vector
<Temp
> derivs
;
8289 nir_const_value
*sample_index_cv
= NULL
;
8290 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8291 enum glsl_base_type stype
;
8292 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8294 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8295 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8296 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8297 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8299 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8300 switch (instr
->src
[i
].src_type
) {
8301 case nir_tex_src_coord
: {
8302 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8303 for (unsigned i
= 0; i
< coord
.size(); i
++)
8304 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8307 case nir_tex_src_bias
:
8308 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8311 case nir_tex_src_lod
: {
8312 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8314 if (val
&& val
->f32
<= 0.0) {
8317 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8322 case nir_tex_src_min_lod
:
8323 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8324 has_clamped_lod
= true;
8326 case nir_tex_src_comparator
:
8327 if (instr
->is_shadow
) {
8328 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8332 case nir_tex_src_offset
:
8333 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8334 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8337 case nir_tex_src_ddx
:
8338 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8341 case nir_tex_src_ddy
:
8342 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8345 case nir_tex_src_ms_index
:
8346 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8347 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8348 has_sample_index
= true;
8350 case nir_tex_src_texture_offset
:
8351 case nir_tex_src_sampler_offset
:
8357 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8358 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8360 if (instr
->op
== nir_texop_texture_samples
) {
8361 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8363 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8364 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8365 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8367 Operand default_sample
= Operand(1u);
8368 if (ctx
->options
->robust_buffer_access
) {
8369 /* Extract the second dword of the descriptor, if it's
8370 * all zero, then it's a null descriptor.
8372 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8373 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8374 default_sample
= Operand(is_non_null_descriptor
);
8377 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8378 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8379 samples
, default_sample
, bld
.scc(is_msaa
));
8383 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8384 aco_ptr
<Instruction
> tmp_instr
;
8385 Temp acc
, pack
= Temp();
8387 uint32_t pack_const
= 0;
8388 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8389 if (!const_offset
[i
])
8391 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8394 if (offset
.type() == RegType::sgpr
) {
8395 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8396 if (const_offset
[i
])
8399 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8400 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8403 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8406 if (pack
== Temp()) {
8409 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8413 if (pack_const
&& pack
!= Temp())
8414 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8416 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8417 if (const_offset
[i
])
8420 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8421 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8424 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8427 if (pack
== Temp()) {
8430 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8434 if (pack_const
&& pack
!= Temp())
8435 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8437 if (pack_const
&& pack
== Temp())
8438 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8439 else if (pack
== Temp())
8445 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8446 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8448 /* pack derivatives */
8449 if (has_ddx
|| has_ddy
) {
8450 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8451 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8452 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8453 derivs
= {ddx
, zero
, ddy
, zero
};
8455 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8456 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8457 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8458 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8463 if (instr
->coord_components
> 1 &&
8464 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8466 instr
->op
!= nir_texop_txf
)
8467 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8469 if (instr
->coord_components
> 2 &&
8470 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8471 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8472 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8473 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8475 instr
->op
!= nir_texop_txf
&&
8476 instr
->op
!= nir_texop_txf_ms
&&
8477 instr
->op
!= nir_texop_fragment_fetch
&&
8478 instr
->op
!= nir_texop_fragment_mask_fetch
)
8479 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8481 if (ctx
->options
->chip_class
== GFX9
&&
8482 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8483 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8484 assert(coords
.size() > 0 && coords
.size() < 3);
8486 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8487 Operand((uint32_t) 0) :
8488 Operand((uint32_t) 0x3f000000)));
8491 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8493 if (instr
->op
== nir_texop_samples_identical
)
8494 resource
= fmask_ptr
;
8496 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8497 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8498 instr
->op
!= nir_texop_txs
&&
8499 instr
->op
!= nir_texop_fragment_fetch
&&
8500 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8501 assert(has_sample_index
);
8502 Operand
op(sample_index
);
8503 if (sample_index_cv
)
8504 op
= Operand(sample_index_cv
->u32
);
8505 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8508 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8509 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8510 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8511 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8516 /* Build tex instruction */
8517 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8518 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8519 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8521 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8524 /* gather4 selects the component by dmask and always returns vec4 */
8525 if (instr
->op
== nir_texop_tg4
) {
8526 assert(instr
->dest
.ssa
.num_components
== 4);
8527 if (instr
->is_shadow
)
8530 dmask
= 1 << instr
->component
;
8531 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8532 tmp_dst
= bld
.tmp(v4
);
8533 } else if (instr
->op
== nir_texop_samples_identical
) {
8534 tmp_dst
= bld
.tmp(v1
);
8535 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8536 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8539 aco_ptr
<MIMG_instruction
> tex
;
8540 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8542 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8544 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8545 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8548 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8549 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8551 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8552 tex
->operands
[0] = Operand(resource
);
8553 tex
->operands
[1] = Operand(s4
); /* no sampler */
8554 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8555 if (ctx
->options
->chip_class
== GFX9
&&
8556 instr
->op
== nir_texop_txs
&&
8557 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8559 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8560 } else if (instr
->op
== nir_texop_query_levels
) {
8561 tex
->dmask
= 1 << 3;
8566 tex
->definitions
[0] = Definition(tmp_dst
);
8568 tex
->can_reorder
= true;
8569 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8572 /* divide 3rd value by 6 by multiplying with magic number */
8573 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8574 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8575 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8576 assert(instr
->dest
.ssa
.num_components
== 3);
8577 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8578 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8579 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8580 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8585 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8589 Temp tg4_compare_cube_wa64
= Temp();
8591 if (tg4_integer_workarounds
) {
8592 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8593 tex
->operands
[0] = Operand(resource
);
8594 tex
->operands
[1] = Operand(s4
); /* no sampler */
8595 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8599 Temp size
= bld
.tmp(v2
);
8600 tex
->definitions
[0] = Definition(size
);
8601 tex
->can_reorder
= true;
8602 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8603 emit_split_vector(ctx
, size
, size
.size());
8606 for (unsigned i
= 0; i
< 2; i
++) {
8607 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8608 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8609 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8610 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8613 Temp new_coords
[2] = {
8614 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8615 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8618 if (tg4_integer_cube_workaround
) {
8619 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8620 Temp desc
[resource
.size()];
8621 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8622 Format::PSEUDO
, 1, resource
.size())};
8623 split
->operands
[0] = Operand(resource
);
8624 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8625 desc
[i
] = bld
.tmp(s1
);
8626 split
->definitions
[i
] = Definition(desc
[i
]);
8628 ctx
->block
->instructions
.emplace_back(std::move(split
));
8630 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8631 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8632 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8635 if (stype
== GLSL_TYPE_UINT
) {
8636 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8637 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8638 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8639 bld
.scc(compare_cube_wa
));
8641 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8642 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8643 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8644 bld
.scc(compare_cube_wa
));
8646 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8647 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8649 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8651 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8652 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8653 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8655 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8656 Format::PSEUDO
, resource
.size(), 1)};
8657 for (unsigned i
= 0; i
< resource
.size(); i
++)
8658 vec
->operands
[i
] = Operand(desc
[i
]);
8659 resource
= bld
.tmp(resource
.regClass());
8660 vec
->definitions
[0] = Definition(resource
);
8661 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8663 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8664 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8665 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8666 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8668 coords
[0] = new_coords
[0];
8669 coords
[1] = new_coords
[1];
8672 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8673 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8675 assert(coords
.size() == 1);
8676 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8680 op
= aco_opcode::buffer_load_format_x
; break;
8682 op
= aco_opcode::buffer_load_format_xy
; break;
8684 op
= aco_opcode::buffer_load_format_xyz
; break;
8686 op
= aco_opcode::buffer_load_format_xyzw
; break;
8688 unreachable("Tex instruction loads more than 4 components.");
8691 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8692 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8695 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8697 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8698 mubuf
->operands
[0] = Operand(resource
);
8699 mubuf
->operands
[1] = Operand(coords
[0]);
8700 mubuf
->operands
[2] = Operand((uint32_t) 0);
8701 mubuf
->definitions
[0] = Definition(tmp_dst
);
8702 mubuf
->idxen
= true;
8703 mubuf
->can_reorder
= true;
8704 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8706 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8710 /* gather MIMG address components */
8711 std::vector
<Temp
> args
;
8713 args
.emplace_back(offset
);
8715 args
.emplace_back(bias
);
8717 args
.emplace_back(compare
);
8719 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8721 args
.insert(args
.end(), coords
.begin(), coords
.end());
8722 if (has_sample_index
)
8723 args
.emplace_back(sample_index
);
8725 args
.emplace_back(lod
);
8726 if (has_clamped_lod
)
8727 args
.emplace_back(clamped_lod
);
8729 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8730 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8731 vec
->definitions
[0] = Definition(arg
);
8732 for (unsigned i
= 0; i
< args
.size(); i
++)
8733 vec
->operands
[i
] = Operand(args
[i
]);
8734 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8737 if (instr
->op
== nir_texop_txf
||
8738 instr
->op
== nir_texop_txf_ms
||
8739 instr
->op
== nir_texop_samples_identical
||
8740 instr
->op
== nir_texop_fragment_fetch
||
8741 instr
->op
== nir_texop_fragment_mask_fetch
) {
8742 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8743 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8744 tex
->operands
[0] = Operand(resource
);
8745 tex
->operands
[1] = Operand(s4
); /* no sampler */
8746 tex
->operands
[2] = Operand(arg
);
8751 tex
->definitions
[0] = Definition(tmp_dst
);
8752 tex
->can_reorder
= true;
8753 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8755 if (instr
->op
== nir_texop_samples_identical
) {
8756 assert(dmask
== 1 && dst
.regClass() == v1
);
8757 assert(dst
.id() != tmp_dst
.id());
8759 Temp tmp
= bld
.tmp(bld
.lm
);
8760 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8761 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8764 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8769 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8770 aco_opcode opcode
= aco_opcode::image_sample
;
8771 if (has_offset
) { /* image_sample_*_o */
8772 if (has_clamped_lod
) {
8774 opcode
= aco_opcode::image_sample_c_cl_o
;
8776 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8778 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8780 opcode
= aco_opcode::image_sample_cl_o
;
8782 opcode
= aco_opcode::image_sample_d_cl_o
;
8784 opcode
= aco_opcode::image_sample_b_cl_o
;
8786 } else if (has_compare
) {
8787 opcode
= aco_opcode::image_sample_c_o
;
8789 opcode
= aco_opcode::image_sample_c_d_o
;
8791 opcode
= aco_opcode::image_sample_c_b_o
;
8793 opcode
= aco_opcode::image_sample_c_lz_o
;
8795 opcode
= aco_opcode::image_sample_c_l_o
;
8797 opcode
= aco_opcode::image_sample_o
;
8799 opcode
= aco_opcode::image_sample_d_o
;
8801 opcode
= aco_opcode::image_sample_b_o
;
8803 opcode
= aco_opcode::image_sample_lz_o
;
8805 opcode
= aco_opcode::image_sample_l_o
;
8807 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8809 opcode
= aco_opcode::image_sample_c_cl
;
8811 opcode
= aco_opcode::image_sample_c_d_cl
;
8813 opcode
= aco_opcode::image_sample_c_b_cl
;
8815 opcode
= aco_opcode::image_sample_cl
;
8817 opcode
= aco_opcode::image_sample_d_cl
;
8819 opcode
= aco_opcode::image_sample_b_cl
;
8821 } else { /* no offset */
8823 opcode
= aco_opcode::image_sample_c
;
8825 opcode
= aco_opcode::image_sample_c_d
;
8827 opcode
= aco_opcode::image_sample_c_b
;
8829 opcode
= aco_opcode::image_sample_c_lz
;
8831 opcode
= aco_opcode::image_sample_c_l
;
8833 opcode
= aco_opcode::image_sample
;
8835 opcode
= aco_opcode::image_sample_d
;
8837 opcode
= aco_opcode::image_sample_b
;
8839 opcode
= aco_opcode::image_sample_lz
;
8841 opcode
= aco_opcode::image_sample_l
;
8845 if (instr
->op
== nir_texop_tg4
) {
8846 if (has_offset
) { /* image_gather4_*_o */
8848 opcode
= aco_opcode::image_gather4_c_lz_o
;
8850 opcode
= aco_opcode::image_gather4_c_l_o
;
8852 opcode
= aco_opcode::image_gather4_c_b_o
;
8854 opcode
= aco_opcode::image_gather4_lz_o
;
8856 opcode
= aco_opcode::image_gather4_l_o
;
8858 opcode
= aco_opcode::image_gather4_b_o
;
8862 opcode
= aco_opcode::image_gather4_c_lz
;
8864 opcode
= aco_opcode::image_gather4_c_l
;
8866 opcode
= aco_opcode::image_gather4_c_b
;
8868 opcode
= aco_opcode::image_gather4_lz
;
8870 opcode
= aco_opcode::image_gather4_l
;
8872 opcode
= aco_opcode::image_gather4_b
;
8875 } else if (instr
->op
== nir_texop_lod
) {
8876 opcode
= aco_opcode::image_get_lod
;
8879 /* we don't need the bias, sample index, compare value or offset to be
8880 * computed in WQM but if the p_create_vector copies the coordinates, then it
8881 * needs to be in WQM */
8882 if (ctx
->stage
== fragment_fs
&&
8883 !has_derivs
&& !has_lod
&& !level_zero
&&
8884 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8885 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8886 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8888 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8889 tex
->operands
[0] = Operand(resource
);
8890 tex
->operands
[1] = Operand(sampler
);
8891 tex
->operands
[2] = Operand(arg
);
8895 tex
->definitions
[0] = Definition(tmp_dst
);
8896 tex
->can_reorder
= true;
8897 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8899 if (tg4_integer_cube_workaround
) {
8900 assert(tmp_dst
.id() != dst
.id());
8901 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8903 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8905 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8906 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8908 if (stype
== GLSL_TYPE_UINT
)
8909 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8911 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8912 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8914 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8915 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8916 val
[0], val
[1], val
[2], val
[3]);
8918 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8919 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8924 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8926 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8927 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8928 return Operand(tmp
.regClass());
8930 return Operand(tmp
);
8933 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8935 aco_ptr
<Pseudo_instruction
> phi
;
8936 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8937 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8939 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8940 logical
|= ctx
->block
->kind
& block_kind_merge
;
8941 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8943 /* we want a sorted list of sources, since the predecessor list is also sorted */
8944 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8945 nir_foreach_phi_src(src
, instr
)
8946 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8948 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8949 unsigned num_operands
= 0;
8950 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8951 unsigned num_defined
= 0;
8952 unsigned cur_pred_idx
= 0;
8953 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8954 if (cur_pred_idx
< preds
.size()) {
8955 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8956 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8957 unsigned skipped
= 0;
8958 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8960 if (cur_pred_idx
+ skipped
< preds
.size()) {
8961 for (unsigned i
= 0; i
< skipped
; i
++)
8962 operands
[num_operands
++] = Operand(dst
.regClass());
8963 cur_pred_idx
+= skipped
;
8968 /* Handle missing predecessors at the end. This shouldn't happen with loop
8969 * headers and we can't ignore these sources for loop header phis. */
8970 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8973 Operand op
= get_phi_operand(ctx
, src
.second
);
8974 operands
[num_operands
++] = op
;
8975 num_defined
+= !op
.isUndefined();
8977 /* handle block_kind_continue_or_break at loop exit blocks */
8978 while (cur_pred_idx
++ < preds
.size())
8979 operands
[num_operands
++] = Operand(dst
.regClass());
8981 /* If the loop ends with a break, still add a linear continue edge in case
8982 * that break is divergent or continue_or_break is used. We'll either remove
8983 * this operand later in visit_loop() if it's not necessary or replace the
8984 * undef with something correct. */
8985 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8986 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8987 nir_block
*last
= nir_loop_last_block(loop
);
8988 if (last
->successors
[0] != instr
->instr
.block
)
8989 operands
[num_operands
++] = Operand(RegClass());
8992 if (num_defined
== 0) {
8993 Builder
bld(ctx
->program
, ctx
->block
);
8994 if (dst
.regClass() == s1
) {
8995 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8996 } else if (dst
.regClass() == v1
) {
8997 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8999 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9000 for (unsigned i
= 0; i
< dst
.size(); i
++)
9001 vec
->operands
[i
] = Operand(0u);
9002 vec
->definitions
[0] = Definition(dst
);
9003 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9008 /* we can use a linear phi in some cases if one src is undef */
9009 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
9010 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9012 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9013 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9014 assert(invert
->kind
& block_kind_invert
);
9016 unsigned then_block
= invert
->linear_preds
[0];
9018 Block
* insert_block
= NULL
;
9019 for (unsigned i
= 0; i
< num_operands
; i
++) {
9020 Operand op
= operands
[i
];
9021 if (op
.isUndefined())
9023 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9024 phi
->operands
[0] = op
;
9027 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9028 phi
->operands
[1] = Operand(dst
.regClass());
9029 phi
->definitions
[0] = Definition(dst
);
9030 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9034 /* try to scalarize vector phis */
9035 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9036 // TODO: scalarize linear phis on divergent ifs
9037 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9038 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9039 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9040 Operand src
= operands
[i
];
9041 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9042 can_scalarize
= false;
9044 if (can_scalarize
) {
9045 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9046 assert(dst
.size() % num_components
== 0);
9047 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9049 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9050 for (unsigned k
= 0; k
< num_components
; k
++) {
9051 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9052 for (unsigned i
= 0; i
< num_operands
; i
++) {
9053 Operand src
= operands
[i
];
9054 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9056 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9057 phi
->definitions
[0] = Definition(phi_dst
);
9058 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9059 new_vec
[k
] = phi_dst
;
9060 vec
->operands
[k
] = Operand(phi_dst
);
9062 vec
->definitions
[0] = Definition(dst
);
9063 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9064 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9069 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9070 for (unsigned i
= 0; i
< num_operands
; i
++)
9071 phi
->operands
[i
] = operands
[i
];
9072 phi
->definitions
[0] = Definition(dst
);
9073 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9077 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9079 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9081 assert(dst
.type() == RegType::sgpr
);
9083 if (dst
.size() == 1) {
9084 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9086 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9087 for (unsigned i
= 0; i
< dst
.size(); i
++)
9088 vec
->operands
[i
] = Operand(0u);
9089 vec
->definitions
[0] = Definition(dst
);
9090 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9094 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9096 Builder
bld(ctx
->program
, ctx
->block
);
9097 Block
*logical_target
;
9098 append_logical_end(ctx
->block
);
9099 unsigned idx
= ctx
->block
->index
;
9101 switch (instr
->type
) {
9102 case nir_jump_break
:
9103 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9104 add_logical_edge(idx
, logical_target
);
9105 ctx
->block
->kind
|= block_kind_break
;
9107 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9108 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9109 /* uniform break - directly jump out of the loop */
9110 ctx
->block
->kind
|= block_kind_uniform
;
9111 ctx
->cf_info
.has_branch
= true;
9112 bld
.branch(aco_opcode::p_branch
);
9113 add_linear_edge(idx
, logical_target
);
9116 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9117 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9119 case nir_jump_continue
:
9120 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9121 add_logical_edge(idx
, logical_target
);
9122 ctx
->block
->kind
|= block_kind_continue
;
9124 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9125 /* for potential uniform breaks after this continue,
9126 we must ensure that they are handled correctly */
9127 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9128 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9129 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9131 /* uniform continue - directly jump to the loop header */
9132 ctx
->block
->kind
|= block_kind_uniform
;
9133 ctx
->cf_info
.has_branch
= true;
9134 bld
.branch(aco_opcode::p_branch
);
9135 add_linear_edge(idx
, logical_target
);
9140 fprintf(stderr
, "Unknown NIR jump instr: ");
9141 nir_print_instr(&instr
->instr
, stderr
);
9142 fprintf(stderr
, "\n");
9146 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9147 ctx
->cf_info
.exec_potentially_empty_break
= true;
9148 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9151 /* remove critical edges from linear CFG */
9152 bld
.branch(aco_opcode::p_branch
);
9153 Block
* break_block
= ctx
->program
->create_and_insert_block();
9154 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9155 break_block
->kind
|= block_kind_uniform
;
9156 add_linear_edge(idx
, break_block
);
9157 /* the loop_header pointer might be invalidated by this point */
9158 if (instr
->type
== nir_jump_continue
)
9159 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9160 add_linear_edge(break_block
->index
, logical_target
);
9161 bld
.reset(break_block
);
9162 bld
.branch(aco_opcode::p_branch
);
9164 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9165 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9166 add_linear_edge(idx
, continue_block
);
9167 append_logical_start(continue_block
);
9168 ctx
->block
= continue_block
;
9172 void visit_block(isel_context
*ctx
, nir_block
*block
)
9174 nir_foreach_instr(instr
, block
) {
9175 switch (instr
->type
) {
9176 case nir_instr_type_alu
:
9177 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9179 case nir_instr_type_load_const
:
9180 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9182 case nir_instr_type_intrinsic
:
9183 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9185 case nir_instr_type_tex
:
9186 visit_tex(ctx
, nir_instr_as_tex(instr
));
9188 case nir_instr_type_phi
:
9189 visit_phi(ctx
, nir_instr_as_phi(instr
));
9191 case nir_instr_type_ssa_undef
:
9192 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9194 case nir_instr_type_deref
:
9196 case nir_instr_type_jump
:
9197 visit_jump(ctx
, nir_instr_as_jump(instr
));
9200 fprintf(stderr
, "Unknown NIR instr type: ");
9201 nir_print_instr(instr
, stderr
);
9202 fprintf(stderr
, "\n");
9207 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9208 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9213 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9214 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9216 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9217 RegClass rc
= vals
[0].regClass();
9219 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9221 unsigned next_pred
= 1;
9223 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9224 Block
& block
= ctx
->program
->blocks
[idx
];
9225 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9226 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9230 if (block
.kind
& block_kind_continue
) {
9231 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9236 bool all_same
= true;
9237 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9238 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9242 val
= vals
[block
.linear_preds
[0] - first
];
9244 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9245 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9246 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9247 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9248 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9249 phi
->definitions
[0] = Definition(val
.getTemp());
9250 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9252 vals
[idx
- first
] = val
;
9255 return vals
[last
- first
];
9258 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9260 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9261 append_logical_end(ctx
->block
);
9262 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9263 Builder
bld(ctx
->program
, ctx
->block
);
9264 bld
.branch(aco_opcode::p_branch
);
9265 unsigned loop_preheader_idx
= ctx
->block
->index
;
9267 Block loop_exit
= Block();
9268 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9269 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9271 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9272 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9273 loop_header
->kind
|= block_kind_loop_header
;
9274 add_edge(loop_preheader_idx
, loop_header
);
9275 ctx
->block
= loop_header
;
9277 /* emit loop body */
9278 unsigned loop_header_idx
= loop_header
->index
;
9279 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9280 append_logical_start(ctx
->block
);
9281 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9283 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9284 if (!ctx
->cf_info
.has_branch
) {
9285 append_logical_end(ctx
->block
);
9286 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9287 /* Discards can result in code running with an empty exec mask.
9288 * This would result in divergent breaks not ever being taken. As a
9289 * workaround, break the loop when the loop mask is empty instead of
9290 * always continuing. */
9291 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9292 unsigned block_idx
= ctx
->block
->index
;
9294 /* create helper blocks to avoid critical edges */
9295 Block
*break_block
= ctx
->program
->create_and_insert_block();
9296 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9297 break_block
->kind
= block_kind_uniform
;
9298 bld
.reset(break_block
);
9299 bld
.branch(aco_opcode::p_branch
);
9300 add_linear_edge(block_idx
, break_block
);
9301 add_linear_edge(break_block
->index
, &loop_exit
);
9303 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9304 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9305 continue_block
->kind
= block_kind_uniform
;
9306 bld
.reset(continue_block
);
9307 bld
.branch(aco_opcode::p_branch
);
9308 add_linear_edge(block_idx
, continue_block
);
9309 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9311 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9312 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9313 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9315 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9316 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9317 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9319 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9322 bld
.reset(ctx
->block
);
9323 bld
.branch(aco_opcode::p_branch
);
9326 /* Fixup phis in loop header from unreachable blocks.
9327 * has_branch/has_divergent_branch also indicates if the loop ends with a
9328 * break/continue instruction, but we don't emit those if unreachable=true */
9330 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9331 bool linear
= ctx
->cf_info
.has_branch
;
9332 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9333 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9334 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9335 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9336 /* the last operand should be the one that needs to be removed */
9337 instr
->operands
.pop_back();
9338 } else if (!is_phi(instr
)) {
9344 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9345 * and the previous one shouldn't both happen at once because a break in the
9346 * merge block would get CSE'd */
9347 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9348 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9349 Operand vals
[num_vals
];
9350 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9351 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9352 if (ctx
->cf_info
.has_branch
)
9353 instr
->operands
.pop_back();
9355 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9356 } else if (!is_phi(instr
)) {
9362 ctx
->cf_info
.has_branch
= false;
9364 // TODO: if the loop has not a single exit, we must add one °°
9365 /* emit loop successor block */
9366 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9367 append_logical_start(ctx
->block
);
9370 // TODO: check if it is beneficial to not branch on continues
9371 /* trim linear phis in loop header */
9372 for (auto&& instr
: loop_entry
->instructions
) {
9373 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9374 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9375 new_phi
->definitions
[0] = instr
->definitions
[0];
9376 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9377 new_phi
->operands
[i
] = instr
->operands
[i
];
9378 /* check that the remaining operands are all the same */
9379 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9380 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9381 instr
.swap(new_phi
);
9382 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9391 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9395 append_logical_end(ctx
->block
);
9396 ctx
->block
->kind
|= block_kind_branch
;
9398 /* branch to linear then block */
9399 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9400 aco_ptr
<Pseudo_branch_instruction
> branch
;
9401 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9402 branch
->operands
[0] = Operand(cond
);
9403 ctx
->block
->instructions
.push_back(std::move(branch
));
9405 ic
->BB_if_idx
= ctx
->block
->index
;
9406 ic
->BB_invert
= Block();
9407 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9408 /* Invert blocks are intentionally not marked as top level because they
9409 * are not part of the logical cfg. */
9410 ic
->BB_invert
.kind
|= block_kind_invert
;
9411 ic
->BB_endif
= Block();
9412 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9413 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9415 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9416 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9417 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9418 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9419 ctx
->cf_info
.parent_if
.is_divergent
= true;
9421 /* divergent branches use cbranch_execz */
9422 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9423 ctx
->cf_info
.exec_potentially_empty_break
= false;
9424 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9426 /** emit logical then block */
9427 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9428 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9429 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9430 ctx
->block
= BB_then_logical
;
9431 append_logical_start(BB_then_logical
);
9434 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9436 Block
*BB_then_logical
= ctx
->block
;
9437 append_logical_end(BB_then_logical
);
9438 /* branch from logical then block to invert block */
9439 aco_ptr
<Pseudo_branch_instruction
> branch
;
9440 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9441 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9442 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9443 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9444 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9445 BB_then_logical
->kind
|= block_kind_uniform
;
9446 assert(!ctx
->cf_info
.has_branch
);
9447 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9448 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9450 /** emit linear then block */
9451 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9452 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9453 BB_then_linear
->kind
|= block_kind_uniform
;
9454 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9455 /* branch from linear then block to invert block */
9456 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9457 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9458 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9460 /** emit invert merge block */
9461 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9462 ic
->invert_idx
= ctx
->block
->index
;
9464 /* branch to linear else block (skip else) */
9465 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9466 branch
->operands
[0] = Operand(ic
->cond
);
9467 ctx
->block
->instructions
.push_back(std::move(branch
));
9469 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9470 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9471 ic
->exec_potentially_empty_break_depth_old
=
9472 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9473 /* divergent branches use cbranch_execz */
9474 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9475 ctx
->cf_info
.exec_potentially_empty_break
= false;
9476 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9478 /** emit logical else block */
9479 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9480 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9481 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9482 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9483 ctx
->block
= BB_else_logical
;
9484 append_logical_start(BB_else_logical
);
9487 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9489 Block
*BB_else_logical
= ctx
->block
;
9490 append_logical_end(BB_else_logical
);
9492 /* branch from logical else block to endif block */
9493 aco_ptr
<Pseudo_branch_instruction
> branch
;
9494 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9495 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9496 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9497 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9498 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9499 BB_else_logical
->kind
|= block_kind_uniform
;
9501 assert(!ctx
->cf_info
.has_branch
);
9502 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9505 /** emit linear else block */
9506 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9507 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9508 BB_else_linear
->kind
|= block_kind_uniform
;
9509 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9511 /* branch from linear else block to endif block */
9512 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9513 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9514 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9517 /** emit endif merge block */
9518 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9519 append_logical_start(ctx
->block
);
9522 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9523 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9524 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9525 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9526 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9527 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9528 !ctx
->cf_info
.parent_if
.is_divergent
) {
9529 ctx
->cf_info
.exec_potentially_empty_break
= false;
9530 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9532 /* uniform control flow never has an empty exec-mask */
9533 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9534 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9535 ctx
->cf_info
.exec_potentially_empty_break
= false;
9536 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9540 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9542 assert(cond
.regClass() == s1
);
9544 append_logical_end(ctx
->block
);
9545 ctx
->block
->kind
|= block_kind_uniform
;
9547 aco_ptr
<Pseudo_branch_instruction
> branch
;
9548 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9549 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9550 branch
->operands
[0] = Operand(cond
);
9551 branch
->operands
[0].setFixed(scc
);
9552 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9554 ic
->BB_if_idx
= ctx
->block
->index
;
9555 ic
->BB_endif
= Block();
9556 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9557 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9559 ctx
->cf_info
.has_branch
= false;
9560 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9562 /** emit then block */
9563 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9564 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9565 add_edge(ic
->BB_if_idx
, BB_then
);
9566 append_logical_start(BB_then
);
9567 ctx
->block
= BB_then
;
9570 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9572 Block
*BB_then
= ctx
->block
;
9574 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9575 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9577 if (!ic
->uniform_has_then_branch
) {
9578 append_logical_end(BB_then
);
9579 /* branch from then block to endif block */
9580 aco_ptr
<Pseudo_branch_instruction
> branch
;
9581 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9582 BB_then
->instructions
.emplace_back(std::move(branch
));
9583 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9584 if (!ic
->then_branch_divergent
)
9585 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9586 BB_then
->kind
|= block_kind_uniform
;
9589 ctx
->cf_info
.has_branch
= false;
9590 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9592 /** emit else block */
9593 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9594 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9595 add_edge(ic
->BB_if_idx
, BB_else
);
9596 append_logical_start(BB_else
);
9597 ctx
->block
= BB_else
;
9600 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9602 Block
*BB_else
= ctx
->block
;
9604 if (!ctx
->cf_info
.has_branch
) {
9605 append_logical_end(BB_else
);
9606 /* branch from then block to endif block */
9607 aco_ptr
<Pseudo_branch_instruction
> branch
;
9608 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9609 BB_else
->instructions
.emplace_back(std::move(branch
));
9610 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9611 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9612 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9613 BB_else
->kind
|= block_kind_uniform
;
9616 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9617 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9619 /** emit endif merge block */
9620 if (!ctx
->cf_info
.has_branch
) {
9621 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9622 append_logical_start(ctx
->block
);
9626 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9628 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9629 Builder
bld(ctx
->program
, ctx
->block
);
9630 aco_ptr
<Pseudo_branch_instruction
> branch
;
9633 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9635 * Uniform conditionals are represented in the following way*) :
9637 * The linear and logical CFG:
9640 * BB_THEN (logical) BB_ELSE (logical)
9644 * *) Exceptions may be due to break and continue statements within loops
9645 * If a break/continue happens within uniform control flow, it branches
9646 * to the loop exit/entry block. Otherwise, it branches to the next
9650 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9651 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9652 cond
= bool_to_scalar_condition(ctx
, cond
);
9654 begin_uniform_if_then(ctx
, &ic
, cond
);
9655 visit_cf_list(ctx
, &if_stmt
->then_list
);
9657 begin_uniform_if_else(ctx
, &ic
);
9658 visit_cf_list(ctx
, &if_stmt
->else_list
);
9660 end_uniform_if(ctx
, &ic
);
9661 } else { /* non-uniform condition */
9663 * To maintain a logical and linear CFG without critical edges,
9664 * non-uniform conditionals are represented in the following way*) :
9669 * BB_THEN (logical) BB_THEN (linear)
9671 * BB_INVERT (linear)
9673 * BB_ELSE (logical) BB_ELSE (linear)
9680 * BB_THEN (logical) BB_ELSE (logical)
9684 * *) Exceptions may be due to break and continue statements within loops
9687 begin_divergent_if_then(ctx
, &ic
, cond
);
9688 visit_cf_list(ctx
, &if_stmt
->then_list
);
9690 begin_divergent_if_else(ctx
, &ic
);
9691 visit_cf_list(ctx
, &if_stmt
->else_list
);
9693 end_divergent_if(ctx
, &ic
);
9696 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9699 static bool visit_cf_list(isel_context
*ctx
,
9700 struct exec_list
*list
)
9702 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9703 switch (node
->type
) {
9704 case nir_cf_node_block
:
9705 visit_block(ctx
, nir_cf_node_as_block(node
));
9707 case nir_cf_node_if
:
9708 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9711 case nir_cf_node_loop
:
9712 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9715 unreachable("unimplemented cf list type");
9721 static void create_null_export(isel_context
*ctx
)
9723 /* Some shader stages always need to have exports.
9724 * So when there is none, we need to add a null export.
9727 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9728 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9729 Builder
bld(ctx
->program
, ctx
->block
);
9730 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9731 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9734 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9736 assert(ctx
->stage
== vertex_vs
||
9737 ctx
->stage
== tess_eval_vs
||
9738 ctx
->stage
== gs_copy_vs
||
9739 ctx
->stage
== ngg_vertex_gs
||
9740 ctx
->stage
== ngg_tess_eval_gs
);
9742 int offset
= (ctx
->stage
& sw_tes
)
9743 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9744 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9745 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9746 if (!is_pos
&& !mask
)
9748 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9750 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9751 exp
->enabled_mask
= mask
;
9752 for (unsigned i
= 0; i
< 4; ++i
) {
9753 if (mask
& (1 << i
))
9754 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9756 exp
->operands
[i
] = Operand(v1
);
9758 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9759 * Setting valid_mask=1 prevents it and has no other effect.
9761 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9763 exp
->compressed
= false;
9765 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9767 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9768 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9773 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9775 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9776 exp
->enabled_mask
= 0;
9777 for (unsigned i
= 0; i
< 4; ++i
)
9778 exp
->operands
[i
] = Operand(v1
);
9779 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9780 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9781 exp
->enabled_mask
|= 0x1;
9783 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9784 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9785 exp
->enabled_mask
|= 0x4;
9787 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9788 if (ctx
->options
->chip_class
< GFX9
) {
9789 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9790 exp
->enabled_mask
|= 0x8;
9792 Builder
bld(ctx
->program
, ctx
->block
);
9794 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9795 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9796 if (exp
->operands
[2].isTemp())
9797 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9799 exp
->operands
[2] = Operand(out
);
9800 exp
->enabled_mask
|= 0x4;
9803 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9805 exp
->compressed
= false;
9806 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9807 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9810 static void create_export_phis(isel_context
*ctx
)
9812 /* Used when exports are needed, but the output temps are defined in a preceding block.
9813 * This function will set up phis in order to access the outputs in the next block.
9816 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9817 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9818 ctx
->block
->instructions
.pop_back();
9820 Builder
bld(ctx
->program
, ctx
->block
);
9822 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9823 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9824 for (unsigned i
= 0; i
< 4; ++i
) {
9825 if (!(mask
& (1 << i
)))
9828 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9829 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9830 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9834 bld
.insert(std::move(logical_start
));
9837 static void create_vs_exports(isel_context
*ctx
)
9839 assert(ctx
->stage
== vertex_vs
||
9840 ctx
->stage
== tess_eval_vs
||
9841 ctx
->stage
== gs_copy_vs
||
9842 ctx
->stage
== ngg_vertex_gs
||
9843 ctx
->stage
== ngg_tess_eval_gs
);
9845 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9846 ? &ctx
->program
->info
->tes
.outinfo
9847 : &ctx
->program
->info
->vs
.outinfo
;
9849 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9850 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9851 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9854 if (ctx
->options
->key
.has_multiview_view_index
) {
9855 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9856 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9859 /* the order these position exports are created is important */
9861 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9862 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9863 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9864 exported_pos
= true;
9866 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9867 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9868 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9869 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9871 if (ctx
->export_clip_dists
) {
9872 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9873 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9874 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9875 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9878 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9879 if (i
< VARYING_SLOT_VAR0
&&
9880 i
!= VARYING_SLOT_LAYER
&&
9881 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9882 i
!= VARYING_SLOT_VIEWPORT
)
9885 export_vs_varying(ctx
, i
, false, NULL
);
9889 create_null_export(ctx
);
9892 static bool export_fs_mrt_z(isel_context
*ctx
)
9894 Builder
bld(ctx
->program
, ctx
->block
);
9895 unsigned enabled_channels
= 0;
9899 for (unsigned i
= 0; i
< 4; ++i
) {
9900 values
[i
] = Operand(v1
);
9903 /* Both stencil and sample mask only need 16-bits. */
9904 if (!ctx
->program
->info
->ps
.writes_z
&&
9905 (ctx
->program
->info
->ps
.writes_stencil
||
9906 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9907 compr
= true; /* COMPR flag */
9909 if (ctx
->program
->info
->ps
.writes_stencil
) {
9910 /* Stencil should be in X[23:16]. */
9911 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9912 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9913 enabled_channels
|= 0x3;
9916 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9917 /* SampleMask should be in Y[15:0]. */
9918 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9919 enabled_channels
|= 0xc;
9922 if (ctx
->program
->info
->ps
.writes_z
) {
9923 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9924 enabled_channels
|= 0x1;
9927 if (ctx
->program
->info
->ps
.writes_stencil
) {
9928 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9929 enabled_channels
|= 0x2;
9932 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9933 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9934 enabled_channels
|= 0x4;
9938 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9939 * writemask component.
9941 if (ctx
->options
->chip_class
== GFX6
&&
9942 ctx
->options
->family
!= CHIP_OLAND
&&
9943 ctx
->options
->family
!= CHIP_HAINAN
) {
9944 enabled_channels
|= 0x1;
9947 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9948 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9953 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9955 Builder
bld(ctx
->program
, ctx
->block
);
9956 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9959 for (unsigned i
= 0; i
< 4; ++i
) {
9960 if (write_mask
& (1 << i
)) {
9961 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9963 values
[i
] = Operand(v1
);
9967 unsigned target
, col_format
;
9968 unsigned enabled_channels
= 0;
9969 aco_opcode compr_op
= (aco_opcode
)0;
9971 slot
-= FRAG_RESULT_DATA0
;
9972 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9973 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9975 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9976 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9977 bool is_16bit
= values
[0].regClass() == v2b
;
9981 case V_028714_SPI_SHADER_ZERO
:
9982 enabled_channels
= 0; /* writemask */
9983 target
= V_008DFC_SQ_EXP_NULL
;
9986 case V_028714_SPI_SHADER_32_R
:
9987 enabled_channels
= 1;
9990 case V_028714_SPI_SHADER_32_GR
:
9991 enabled_channels
= 0x3;
9994 case V_028714_SPI_SHADER_32_AR
:
9995 if (ctx
->options
->chip_class
>= GFX10
) {
9996 /* Special case: on GFX10, the outputs are different for 32_AR */
9997 enabled_channels
= 0x3;
9998 values
[1] = values
[3];
9999 values
[3] = Operand(v1
);
10001 enabled_channels
= 0x9;
10005 case V_028714_SPI_SHADER_FP16_ABGR
:
10006 enabled_channels
= 0x5;
10007 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10009 if (ctx
->options
->chip_class
>= GFX9
) {
10010 /* Pack the FP16 values together instead of converting them to
10011 * FP32 and back to FP16.
10012 * TODO: use p_create_vector and let the compiler optimizes.
10014 compr_op
= aco_opcode::v_pack_b32_f16
;
10016 for (unsigned i
= 0; i
< 4; i
++) {
10017 if ((write_mask
>> i
) & 1)
10018 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
10024 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10025 enabled_channels
= 0x5;
10026 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10027 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
10029 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10033 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10034 enabled_channels
= 0x5;
10035 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
10036 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10038 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10042 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10043 enabled_channels
= 0x5;
10044 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10045 if (is_int8
|| is_int10
) {
10047 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10048 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10050 for (unsigned i
= 0; i
< 4; i
++) {
10051 if ((write_mask
>> i
) & 1) {
10052 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10053 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10057 } else if (is_16bit
) {
10058 for (unsigned i
= 0; i
< 4; i
++) {
10059 if ((write_mask
>> i
) & 1) {
10060 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10061 values
[i
] = Operand(tmp
);
10068 case V_028714_SPI_SHADER_SINT16_ABGR
:
10069 enabled_channels
= 0x5;
10070 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10071 if (is_int8
|| is_int10
) {
10073 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10074 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10075 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10076 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10078 for (unsigned i
= 0; i
< 4; i
++) {
10079 if ((write_mask
>> i
) & 1) {
10080 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10081 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10083 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10084 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10088 } else if (is_16bit
) {
10089 for (unsigned i
= 0; i
< 4; i
++) {
10090 if ((write_mask
>> i
) & 1) {
10091 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10092 values
[i
] = Operand(tmp
);
10098 case V_028714_SPI_SHADER_32_ABGR
:
10099 enabled_channels
= 0xF;
10106 if (target
== V_008DFC_SQ_EXP_NULL
)
10109 if ((bool) compr_op
) {
10110 for (int i
= 0; i
< 2; i
++) {
10111 /* check if at least one of the values to be compressed is enabled */
10112 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10114 enabled_channels
|= enabled
<< (i
*2);
10115 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10116 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10117 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10119 values
[i
] = Operand(v1
);
10122 values
[2] = Operand(v1
);
10123 values
[3] = Operand(v1
);
10125 for (int i
= 0; i
< 4; i
++)
10126 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10129 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10130 enabled_channels
, target
, (bool) compr_op
);
10134 static void create_fs_exports(isel_context
*ctx
)
10136 bool exported
= false;
10138 /* Export depth, stencil and sample mask. */
10139 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10140 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10141 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10142 exported
|= export_fs_mrt_z(ctx
);
10144 /* Export all color render targets. */
10145 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10146 if (ctx
->outputs
.mask
[i
])
10147 exported
|= export_fs_mrt_color(ctx
, i
);
10150 create_null_export(ctx
);
10153 static void write_tcs_tess_factors(isel_context
*ctx
)
10155 unsigned outer_comps
;
10156 unsigned inner_comps
;
10158 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10175 Builder
bld(ctx
->program
, ctx
->block
);
10177 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10178 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10179 bld
.sopp(aco_opcode::s_barrier
);
10181 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10182 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10184 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10185 if_context ic_invocation_id_is_zero
;
10186 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10187 bld
.reset(ctx
->block
);
10189 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10191 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10192 unsigned stride
= inner_comps
+ outer_comps
;
10193 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10197 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10199 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10201 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10202 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10203 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10205 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10206 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10208 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10209 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10210 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10211 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10214 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10215 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10216 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10217 unsigned tf_const_offset
= 0;
10219 if (ctx
->program
->chip_class
<= GFX8
) {
10220 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10221 if_context ic_rel_patch_id_is_zero
;
10222 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10223 bld
.reset(ctx
->block
);
10225 /* Store the dynamic HS control word. */
10226 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10227 bld
.mubuf(aco_opcode::buffer_store_dword
,
10228 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10229 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10230 /* disable_wqm */ false, /* glc */ true);
10231 tf_const_offset
+= 4;
10233 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10234 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10235 bld
.reset(ctx
->block
);
10238 assert(stride
== 2 || stride
== 4 || stride
== 6);
10239 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10240 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10242 /* Store to offchip for TES to read - only if TES reads them */
10243 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10244 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10245 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10247 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10248 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10250 if (likely(inner_comps
)) {
10251 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10252 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10256 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10257 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10260 static void emit_stream_output(isel_context
*ctx
,
10261 Temp
const *so_buffers
,
10262 Temp
const *so_write_offset
,
10263 const struct radv_stream_output
*output
)
10265 unsigned num_comps
= util_bitcount(output
->component_mask
);
10266 unsigned writemask
= (1 << num_comps
) - 1;
10267 unsigned loc
= output
->location
;
10268 unsigned buf
= output
->buffer
;
10270 assert(num_comps
&& num_comps
<= 4);
10271 if (!num_comps
|| num_comps
> 4)
10274 unsigned start
= ffs(output
->component_mask
) - 1;
10277 bool all_undef
= true;
10278 assert(ctx
->stage
& hw_vs
);
10279 for (unsigned i
= 0; i
< num_comps
; i
++) {
10280 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10281 all_undef
= all_undef
&& !out
[i
].id();
10286 while (writemask
) {
10288 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10289 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10290 /* GFX6 doesn't support storing vec3, split it. */
10291 writemask
|= 1u << (start
+ 2);
10295 unsigned offset
= output
->offset
+ start
* 4;
10297 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10298 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10299 for (int i
= 0; i
< count
; ++i
)
10300 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10301 vec
->definitions
[0] = Definition(write_data
);
10302 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10307 opcode
= aco_opcode::buffer_store_dword
;
10310 opcode
= aco_opcode::buffer_store_dwordx2
;
10313 opcode
= aco_opcode::buffer_store_dwordx3
;
10316 opcode
= aco_opcode::buffer_store_dwordx4
;
10319 unreachable("Unsupported dword count.");
10322 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10323 store
->operands
[0] = Operand(so_buffers
[buf
]);
10324 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10325 store
->operands
[2] = Operand((uint32_t) 0);
10326 store
->operands
[3] = Operand(write_data
);
10327 if (offset
> 4095) {
10328 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10329 Builder
bld(ctx
->program
, ctx
->block
);
10330 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10332 store
->offset
= offset
;
10334 store
->offen
= true;
10336 store
->dlc
= false;
10338 store
->can_reorder
= true;
10339 ctx
->block
->instructions
.emplace_back(std::move(store
));
10343 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10345 Builder
bld(ctx
->program
, ctx
->block
);
10347 Temp so_buffers
[4];
10348 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10349 for (unsigned i
= 0; i
< 4; i
++) {
10350 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10354 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10355 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10358 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10359 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10361 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10363 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10366 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10368 bld
.reset(ctx
->block
);
10370 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10372 Temp so_write_offset
[4];
10374 for (unsigned i
= 0; i
< 4; i
++) {
10375 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10380 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10381 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10382 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10383 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10385 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10387 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10388 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10389 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10390 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10394 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10395 struct radv_stream_output
*output
=
10396 &ctx
->program
->info
->so
.outputs
[i
];
10397 if (stream
!= output
->stream
)
10400 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10403 begin_divergent_if_else(ctx
, &ic
);
10404 end_divergent_if(ctx
, &ic
);
10407 } /* end namespace */
10409 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10411 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10412 Builder
bld(ctx
->program
, ctx
->block
);
10413 constexpr unsigned hs_idx
= 1u;
10414 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10415 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10416 Operand((8u << 16) | (hs_idx
* 8u)));
10417 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10419 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10421 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10422 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10423 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10424 ls_has_nonzero_hs_threads
);
10425 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10426 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10427 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10428 ls_has_nonzero_hs_threads
);
10429 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10430 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10431 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10432 ls_has_nonzero_hs_threads
);
10434 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10435 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10436 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10439 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10441 /* Split all arguments except for the first (ring_offsets) and the last
10442 * (exec) so that the dead channels don't stay live throughout the program.
10444 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10445 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10446 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10447 startpgm
->definitions
[i
].regClass().size());
10452 void handle_bc_optimize(isel_context
*ctx
)
10454 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10455 Builder
bld(ctx
->program
, ctx
->block
);
10456 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10457 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10458 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10459 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10460 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10461 if (uses_center
&& uses_centroid
) {
10462 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10463 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10465 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10467 for (unsigned i
= 0; i
< 2; i
++) {
10468 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10469 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10470 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10471 persp_centroid
, persp_center
, sel
);
10473 ctx
->persp_centroid
= bld
.tmp(v2
);
10474 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10475 Operand(new_coord
[0]), Operand(new_coord
[1]));
10476 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10479 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10481 for (unsigned i
= 0; i
< 2; i
++) {
10482 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10483 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10484 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10485 linear_centroid
, linear_center
, sel
);
10487 ctx
->linear_centroid
= bld
.tmp(v2
);
10488 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10489 Operand(new_coord
[0]), Operand(new_coord
[1]));
10490 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10495 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10497 Program
*program
= ctx
->program
;
10499 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10501 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10502 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10503 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10504 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10505 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10507 program
->next_fp_mode
.must_flush_denorms32
=
10508 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10509 program
->next_fp_mode
.must_flush_denorms16_64
=
10510 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10511 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10513 program
->next_fp_mode
.care_about_round32
=
10514 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10516 program
->next_fp_mode
.care_about_round16_64
=
10517 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10518 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10520 /* default to preserving fp16 and fp64 denorms, since it's free */
10521 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10522 program
->next_fp_mode
.denorm16_64
= 0;
10524 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10526 /* preserving fp32 denorms is expensive, so only do it if asked */
10527 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10528 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10530 program
->next_fp_mode
.denorm32
= 0;
10532 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10533 program
->next_fp_mode
.round32
= fp_round_tz
;
10535 program
->next_fp_mode
.round32
= fp_round_ne
;
10537 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10538 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10540 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10542 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10545 void cleanup_cfg(Program
*program
)
10547 /* create linear_succs/logical_succs */
10548 for (Block
& BB
: program
->blocks
) {
10549 for (unsigned idx
: BB
.linear_preds
)
10550 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10551 for (unsigned idx
: BB
.logical_preds
)
10552 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10556 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10558 Builder
bld(ctx
->program
, ctx
->block
);
10560 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10561 Temp count
= i
== 0
10562 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10563 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10564 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10566 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10569 if (ctx
->program
->wave_size
== 64) {
10570 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10571 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10572 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10574 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10575 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10581 bool ngg_early_prim_export(isel_context
*ctx
)
10583 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10587 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10589 Builder
bld(ctx
->program
, ctx
->block
);
10591 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10592 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10594 /* Get the id of the current wave within the threadgroup (workgroup) */
10595 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10596 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10598 /* Execute the following code only on the first wave (wave id 0),
10599 * use the SCC def to tell if the wave id is zero or not.
10601 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10603 begin_uniform_if_then(ctx
, &ic
, cond
);
10604 begin_uniform_if_else(ctx
, &ic
);
10605 bld
.reset(ctx
->block
);
10607 /* Number of vertices output by VS/TES */
10608 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10609 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10610 /* Number of primitives output by VS/TES */
10611 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10612 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10614 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10615 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10616 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10618 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10619 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10621 end_uniform_if(ctx
, &ic
);
10623 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10624 bld
.reset(ctx
->block
);
10625 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10628 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10630 Builder
bld(ctx
->program
, ctx
->block
);
10632 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10633 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10636 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10639 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10640 assert(vtxindex
[i
].id());
10643 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10647 /* The initial edge flag is always false in tess eval shaders. */
10648 if (ctx
->stage
== ngg_vertex_gs
) {
10649 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10650 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10654 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10659 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10661 Builder
bld(ctx
->program
, ctx
->block
);
10662 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10664 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10665 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10666 false /* compressed */, true/* done */, false /* valid mask */);
10669 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10671 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10672 * These must always come before VS exports.
10674 * It is recommended to do these as early as possible. They can be at the beginning when
10675 * there is no SW GS and the shader doesn't write edge flags.
10679 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10680 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10682 Builder
bld(ctx
->program
, ctx
->block
);
10683 constexpr unsigned max_vertices_per_primitive
= 3;
10684 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10686 if (ctx
->stage
== ngg_vertex_gs
) {
10687 /* TODO: optimize for points & lines */
10688 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10689 if (ctx
->shader
->info
.tess
.point_mode
)
10690 num_vertices_per_primitive
= 1;
10691 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10692 num_vertices_per_primitive
= 2;
10694 unreachable("Unsupported NGG shader stage");
10697 Temp vtxindex
[max_vertices_per_primitive
];
10698 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10699 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10700 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10701 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10702 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10703 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10704 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10705 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10707 /* Export primitive data to the index buffer. */
10708 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10710 /* Export primitive ID. */
10711 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10712 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10713 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10714 Temp provoking_vtx_index
= vtxindex
[0];
10715 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10717 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10720 begin_divergent_if_else(ctx
, &ic
);
10721 end_divergent_if(ctx
, &ic
);
10724 void ngg_emit_nogs_output(isel_context
*ctx
)
10726 /* Emits NGG GS output, for stages that don't have SW GS. */
10729 Builder
bld(ctx
->program
, ctx
->block
);
10730 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10732 /* NGG streamout is currently disabled by default. */
10733 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10735 if (late_prim_export
) {
10736 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10737 create_export_phis(ctx
);
10738 /* Do what we need to do in the GS threads. */
10739 ngg_emit_nogs_gsthreads(ctx
);
10741 /* What comes next should be executed on ES threads. */
10742 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10743 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10744 bld
.reset(ctx
->block
);
10747 /* Export VS outputs */
10748 ctx
->block
->kind
|= block_kind_export_end
;
10749 create_vs_exports(ctx
);
10751 /* Export primitive ID */
10752 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10755 if (ctx
->stage
== ngg_vertex_gs
) {
10756 /* Wait for GS threads to store primitive ID in LDS. */
10757 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10758 bld
.sopp(aco_opcode::s_barrier
);
10760 /* Calculate LDS address where the GS threads stored the primitive ID. */
10761 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10762 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10763 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10764 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10765 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10766 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10768 /* Load primitive ID from LDS. */
10769 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10770 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10771 /* TES: Just use the patch ID as the primitive ID. */
10772 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10774 unreachable("unsupported NGG shader stage.");
10777 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10778 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10780 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10783 if (late_prim_export
) {
10784 begin_divergent_if_else(ctx
, &ic
);
10785 end_divergent_if(ctx
, &ic
);
10786 bld
.reset(ctx
->block
);
10790 void select_program(Program
*program
,
10791 unsigned shader_count
,
10792 struct nir_shader
*const *shaders
,
10793 ac_shader_config
* config
,
10794 struct radv_shader_args
*args
)
10796 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10797 if_context ic_merged_wave_info
;
10798 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10800 for (unsigned i
= 0; i
< shader_count
; i
++) {
10801 nir_shader
*nir
= shaders
[i
];
10802 init_context(&ctx
, nir
);
10804 setup_fp_mode(&ctx
, nir
);
10807 /* needs to be after init_context() for FS */
10808 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10809 append_logical_start(ctx
.block
);
10811 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10812 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10814 split_arguments(&ctx
, startpgm
);
10818 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10820 if (ngg_early_prim_export(&ctx
))
10821 ngg_emit_nogs_gsthreads(&ctx
);
10824 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10825 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10826 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10827 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10828 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10829 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10830 ctx
.stage
== tess_eval_geometry_gs
));
10832 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10833 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10834 if (check_merged_wave_info
) {
10835 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10836 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10840 Builder
bld(ctx
.program
, ctx
.block
);
10842 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10843 bld
.sopp(aco_opcode::s_barrier
);
10845 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10846 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10848 } else if (ctx
.stage
== geometry_gs
)
10849 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10851 if (ctx
.stage
== fragment_fs
)
10852 handle_bc_optimize(&ctx
);
10854 visit_cf_list(&ctx
, &func
->body
);
10856 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10857 emit_streamout(&ctx
, 0);
10859 if (ctx
.stage
& hw_vs
) {
10860 create_vs_exports(&ctx
);
10861 ctx
.block
->kind
|= block_kind_export_end
;
10862 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10863 ngg_emit_nogs_output(&ctx
);
10864 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10865 Builder
bld(ctx
.program
, ctx
.block
);
10866 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10867 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10868 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10869 write_tcs_tess_factors(&ctx
);
10872 if (ctx
.stage
== fragment_fs
) {
10873 create_fs_exports(&ctx
);
10874 ctx
.block
->kind
|= block_kind_export_end
;
10877 if (endif_merged_wave_info
) {
10878 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10879 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10882 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10883 ngg_emit_nogs_output(&ctx
);
10885 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10886 /* Outputs of the previous stage are inputs to the next stage */
10887 ctx
.inputs
= ctx
.outputs
;
10888 ctx
.outputs
= shader_io_state();
10892 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10894 append_logical_end(ctx
.block
);
10895 ctx
.block
->kind
|= block_kind_uniform
;
10896 Builder
bld(ctx
.program
, ctx
.block
);
10897 if (ctx
.program
->wb_smem_l1_on_end
)
10898 bld
.smem(aco_opcode::s_dcache_wb
, false);
10899 bld
.sopp(aco_opcode::s_endpgm
);
10901 cleanup_cfg(program
);
10904 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10905 ac_shader_config
* config
,
10906 struct radv_shader_args
*args
)
10908 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10910 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10911 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10912 program
->next_fp_mode
.must_flush_denorms32
= false;
10913 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10914 program
->next_fp_mode
.care_about_round32
= false;
10915 program
->next_fp_mode
.care_about_round16_64
= false;
10916 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10917 program
->next_fp_mode
.denorm32
= 0;
10918 program
->next_fp_mode
.round32
= fp_round_ne
;
10919 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10920 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10922 add_startpgm(&ctx
);
10923 append_logical_start(ctx
.block
);
10925 Builder
bld(ctx
.program
, ctx
.block
);
10927 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10929 Operand
stream_id(0u);
10930 if (args
->shader_info
->so
.num_outputs
)
10931 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10932 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10934 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10936 std::stack
<Block
> endif_blocks
;
10938 for (unsigned stream
= 0; stream
< 4; stream
++) {
10939 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10942 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10943 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10946 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10948 unsigned BB_if_idx
= ctx
.block
->index
;
10949 Block BB_endif
= Block();
10950 if (!stream_id
.isConstant()) {
10952 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10953 append_logical_end(ctx
.block
);
10954 ctx
.block
->kind
|= block_kind_uniform
;
10955 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10957 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10959 ctx
.block
= ctx
.program
->create_and_insert_block();
10960 add_edge(BB_if_idx
, ctx
.block
);
10961 bld
.reset(ctx
.block
);
10962 append_logical_start(ctx
.block
);
10965 unsigned offset
= 0;
10966 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10967 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10970 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10971 unsigned length
= util_last_bit(output_usage_mask
);
10972 for (unsigned j
= 0; j
< length
; ++j
) {
10973 if (!(output_usage_mask
& (1 << j
)))
10976 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10977 Temp voffset
= vtx_offset
;
10978 if (const_offset
>= 4096u) {
10979 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10980 const_offset
%= 4096u;
10983 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10984 mubuf
->definitions
[0] = bld
.def(v1
);
10985 mubuf
->operands
[0] = Operand(gsvs_ring
);
10986 mubuf
->operands
[1] = Operand(voffset
);
10987 mubuf
->operands
[2] = Operand(0u);
10988 mubuf
->offen
= true;
10989 mubuf
->offset
= const_offset
;
10992 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10993 mubuf
->barrier
= barrier_none
;
10994 mubuf
->can_reorder
= true;
10996 ctx
.outputs
.mask
[i
] |= 1 << j
;
10997 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10999 bld
.insert(std::move(mubuf
));
11005 if (args
->shader_info
->so
.num_outputs
) {
11006 emit_streamout(&ctx
, stream
);
11007 bld
.reset(ctx
.block
);
11011 create_vs_exports(&ctx
);
11012 ctx
.block
->kind
|= block_kind_export_end
;
11015 if (!stream_id
.isConstant()) {
11016 append_logical_end(ctx
.block
);
11018 /* branch from then block to endif block */
11019 bld
.branch(aco_opcode::p_branch
);
11020 add_edge(ctx
.block
->index
, &BB_endif
);
11021 ctx
.block
->kind
|= block_kind_uniform
;
11023 /* emit else block */
11024 ctx
.block
= ctx
.program
->create_and_insert_block();
11025 add_edge(BB_if_idx
, ctx
.block
);
11026 bld
.reset(ctx
.block
);
11027 append_logical_start(ctx
.block
);
11029 endif_blocks
.push(std::move(BB_endif
));
11033 while (!endif_blocks
.empty()) {
11034 Block BB_endif
= std::move(endif_blocks
.top());
11035 endif_blocks
.pop();
11037 Block
*BB_else
= ctx
.block
;
11039 append_logical_end(BB_else
);
11040 /* branch from else block to endif block */
11041 bld
.branch(aco_opcode::p_branch
);
11042 add_edge(BB_else
->index
, &BB_endif
);
11043 BB_else
->kind
|= block_kind_uniform
;
11045 /** emit endif merge block */
11046 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11047 bld
.reset(ctx
.block
);
11048 append_logical_start(ctx
.block
);
11051 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11053 append_logical_end(ctx
.block
);
11054 ctx
.block
->kind
|= block_kind_uniform
;
11055 bld
.sopp(aco_opcode::s_endpgm
);
11057 cleanup_cfg(program
);