src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static void visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 void load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset >> 2, (offset >> 2) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749 }
2750
2751 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2752 {
2753    if (start == 0 && size == data.size())
2754       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2755
2756    unsigned size_hint = 1;
2757    auto it = ctx->allocated_vec.find(data.id());
2758    if (it != ctx->allocated_vec.end())
2759       size_hint = it->second[0].size();
2760    if (size % size_hint || start % size_hint)
2761       size_hint = 1;
2762
2763    start /= size_hint;
2764    size /= size_hint;
2765
2766    Temp elems[size];
2767    for (unsigned i = 0; i < size; i++)
2768       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2769
2770    if (size == 1)
2771       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2772
2773    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2774    for (unsigned i = 0; i < size; i++)
2775       vec->operands[i] = Operand(elems[i]);
2776    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2777    vec->definitions[0] = Definition(res);
2778    ctx->block->instructions.emplace_back(std::move(vec));
2779    return res;
2780 }
2781
2782 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2783 {
2784    Builder bld(ctx->program, ctx->block);
2785    unsigned bytes_written = 0;
2786    bool large_ds_write = ctx->options->chip_class >= GFX7;
2787    bool usable_write2 = ctx->options->chip_class >= GFX7;
2788
2789    while (bytes_written < total_size * 4) {
2790       unsigned todo = total_size * 4 - bytes_written;
2791       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2792       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2793
2794       aco_opcode op = aco_opcode::last_opcode;
2795       bool write2 = false;
2796       unsigned size = 0;
2797       if (todo >= 16 && aligned16 && large_ds_write) {
2798          op = aco_opcode::ds_write_b128;
2799          size = 4;
2800       } else if (todo >= 16 && aligned8 && usable_write2) {
2801          op = aco_opcode::ds_write2_b64;
2802          write2 = true;
2803          size = 4;
2804       } else if (todo >= 12 && aligned16 && large_ds_write) {
2805          op = aco_opcode::ds_write_b96;
2806          size = 3;
2807       } else if (todo >= 8 && aligned8) {
2808          op = aco_opcode::ds_write_b64;
2809          size = 2;
2810       } else if (todo >= 8 && usable_write2) {
2811          op = aco_opcode::ds_write2_b32;
2812          write2 = true;
2813          size = 2;
2814       } else if (todo >= 4) {
2815          op = aco_opcode::ds_write_b32;
2816          size = 1;
2817       } else {
2818          assert(false);
2819       }
2820
2821       unsigned offset = offset0 + offset1 + bytes_written;
2822       unsigned max_offset = write2 ? 1020 : 65535;
2823       Temp address_offset = address;
2824       if (offset > max_offset) {
2825          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2826          offset = offset1 + bytes_written;
2827       }
2828       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2829
2830       if (write2) {
2831          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2832          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2833          bld.ds(op, address_offset, val0, val1, m, offset >> 2, (offset >> 2) + 1);
2834       } else {
2835          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2836          bld.ds(op, address_offset, val, m, offset);
2837       }
2838
2839       bytes_written += size * 4;
2840    }
2841 }
2842
2843 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2844                Temp address, unsigned base_offset, unsigned align)
2845 {
2846    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2847
2848    Operand m = load_lds_size_m0(ctx);
2849
2850    /* we need at most two stores for 32bit variables */
2851    int start[2], count[2];
2852    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2853    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2854    assert(wrmask == 0);
2855
2856    /* one combined store is sufficient */
2857    if (count[0] == count[1]) {
2858       Builder bld(ctx->program, ctx->block);
2859
2860       Temp address_offset = address;
2861       if ((base_offset >> 2) + start[1] > 255) {
2862          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2863          base_offset = 0;
2864       }
2865
2866       assert(count[0] == 1);
2867       Temp val0 = emit_extract_vector(ctx, data, start[0], v1);
2868       Temp val1 = emit_extract_vector(ctx, data, start[1], v1);
2869       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2870       base_offset = base_offset / elem_size_bytes;
2871       bld.ds(op, address_offset, val0, val1, m,
2872              base_offset + start[0], base_offset + start[1]);
2873       return;
2874    }
2875
2876    for (unsigned i = 0; i < 2; i++) {
2877       if (count[i] == 0)
2878          continue;
2879
2880       unsigned elem_size_words = elem_size_bytes / 4;
2881       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2882                       base_offset, start[i] * elem_size_bytes, align);
2883    }
2884    return;
2885 }
2886
2887 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2888 {
2889    unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
2890    unsigned align = 16;
2891    align = std::min(align, 1u << (ffs(itemsize) - 1));
2892    if (const_offset)
2893       align = std::min(align, 1u << (ffs(const_offset) - 1));
2894
2895    return align;
2896 }
2897
2898 void visit_store_vsgs_output(isel_context *ctx, nir_intrinsic_instr *instr)
2899 {
2900    unsigned write_mask = nir_intrinsic_write_mask(instr);
2901    unsigned component = nir_intrinsic_component(instr);
2902    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2903    unsigned idx = (nir_intrinsic_base(instr) + component) * 4u;
2904    Operand offset(s1);
2905    Builder bld(ctx->program, ctx->block);
2906
2907    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2908    if (off_instr->type != nir_instr_type_load_const)
2909       offset = bld.v_mul24_imm(bld.def(v1), get_ssa_temp(ctx, instr->src[1].ssa), 16u);
2910    else
2911       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 16u;
2912
2913    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
2914    if (ctx->stage == vertex_es) {
2915       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
2916
2917       Temp elems[NIR_MAX_VEC_COMPONENTS * 2];
2918       if (elem_size_bytes == 8) {
2919          for (unsigned i = 0; i < src.size() / 2; i++) {
2920             Temp elem = emit_extract_vector(ctx, src, i, v2);
2921             elems[i*2] = bld.tmp(v1);
2922             elems[i*2+1] = bld.tmp(v1);
2923             bld.pseudo(aco_opcode::p_split_vector, Definition(elems[i*2]), Definition(elems[i*2+1]), elem);
2924          }
2925          write_mask = widen_mask(write_mask, 2);
2926          elem_size_bytes /= 2u;
2927       } else {
2928          for (unsigned i = 0; i < src.size(); i++)
2929             elems[i] = emit_extract_vector(ctx, src, i, v1);
2930       }
2931
2932       while (write_mask) {
2933          unsigned index = u_bit_scan(&write_mask);
2934          unsigned offset = index * elem_size_bytes;
2935          Temp elem = emit_extract_vector(ctx, src, index, RegClass(RegType::vgpr, elem_size_bytes / 4));
2936
2937          Operand vaddr_offset(v1);
2938          unsigned const_offset = idx + offset;
2939          if (const_offset >= 4096u) {
2940             vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
2941             const_offset %= 4096u;
2942          }
2943
2944          aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
2945          mtbuf->operands[0] = Operand(esgs_ring);
2946          mtbuf->operands[1] = vaddr_offset;
2947          mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->es2gs_offset));
2948          mtbuf->operands[3] = Operand(elem);
2949          mtbuf->offen = !vaddr_offset.isUndefined();
2950          mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
2951          mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
2952          mtbuf->offset = const_offset;
2953          mtbuf->glc = true;
2954          mtbuf->slc = true;
2955          mtbuf->barrier = barrier_none;
2956          mtbuf->can_reorder = true;
2957          bld.insert(std::move(mtbuf));
2958       }
2959    } else {
2960       unsigned itemsize = ctx->program->info->vs.es_info.esgs_itemsize;
2961
2962       Temp vertex_idx = emit_mbcnt(ctx, bld.def(v1));
2963       Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
2964       vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), vertex_idx,
2965                             bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
2966
2967       Temp lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
2968       if (!offset.isUndefined())
2969          lds_base = bld.vadd32(bld.def(v1), offset, lds_base);
2970
2971       unsigned align = calculate_lds_alignment(ctx, idx);
2972       store_lds(ctx, elem_size_bytes, src, write_mask, lds_base, idx, align);
2973    }
2974 }
2975
2976 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
2977 {
2978    if (ctx->stage == vertex_vs ||
2979        ctx->stage == fragment_fs ||
2980        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
2981       unsigned write_mask = nir_intrinsic_write_mask(instr);
2982       unsigned component = nir_intrinsic_component(instr);
2983       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
2984       unsigned idx = nir_intrinsic_base(instr) + component;
2985
2986       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
2987       if (off_instr->type != nir_instr_type_load_const) {
2988          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
2989          nir_print_instr(off_instr, stderr);
2990          fprintf(stderr, "\n");
2991       }
2992       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
2993
2994       if (instr->src[0].ssa->bit_size == 64)
2995          write_mask = widen_mask(write_mask, 2);
2996
2997       for (unsigned i = 0; i < 8; ++i) {
2998          if (write_mask & (1 << i)) {
2999             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3000             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3001          }
3002          idx++;
3003       }
3004    } else if (ctx->stage == vertex_es ||
3005               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX)) {
3006       visit_store_vsgs_output(ctx, instr);
3007    } else {
3008       unreachable("Shader stage not implemented");
3009    }
3010 }
3011
3012 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3013 {
3014    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3015    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3016
3017    Builder bld(ctx->program, ctx->block);
3018    Temp tmp = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3019    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), tmp, idx, component);
3020 }
3021
3022 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3023 {
3024    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3025    for (unsigned i = 0; i < num_components; i++)
3026       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3027    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3028       assert(num_components == 4);
3029       Builder bld(ctx->program, ctx->block);
3030       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3031    }
3032
3033    for (Operand& op : vec->operands)
3034       op = op.isUndefined() ? Operand(0u) : op;
3035
3036    vec->definitions[0] = Definition(dst);
3037    ctx->block->instructions.emplace_back(std::move(vec));
3038    emit_split_vector(ctx, dst, num_components);
3039    return;
3040 }
3041
3042 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3043 {
3044    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3045    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3046    unsigned idx = nir_intrinsic_base(instr);
3047    unsigned component = nir_intrinsic_component(instr);
3048    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3049
3050    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3051    if (offset) {
3052       assert(offset->u32 == 0);
3053    } else {
3054       /* the lower 15bit of the prim_mask contain the offset into LDS
3055        * while the upper bits contain the number of prims */
3056       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3057       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3058       Builder bld(ctx->program, ctx->block);
3059       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3060       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3061       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3062       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3063       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3064    }
3065
3066    if (instr->dest.ssa.num_components == 1) {
3067       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3068    } else {
3069       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3070       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3071       {
3072          Temp tmp = {ctx->program->allocateId(), v1};
3073          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3074          vec->operands[i] = Operand(tmp);
3075       }
3076       vec->definitions[0] = Definition(dst);
3077       ctx->block->instructions.emplace_back(std::move(vec));
3078    }
3079 }
3080
3081 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3082                              unsigned offset, unsigned stride, unsigned channels)
3083 {
3084    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3085    if (vtx_info->chan_byte_size != 4 && channels == 3)
3086       return false;
3087    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3088           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3089 }
3090
3091 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3092                               unsigned offset, unsigned stride, unsigned *channels)
3093 {
3094    if (!vtx_info->chan_byte_size) {
3095       *channels = vtx_info->num_channels;
3096       return vtx_info->chan_format;
3097    }
3098
3099    unsigned num_channels = *channels;
3100    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3101       unsigned new_channels = num_channels + 1;
3102       /* first, assume more loads is worse and try using a larger data format */
3103       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3104          new_channels++;
3105          /* don't make the attribute potentially out-of-bounds */
3106          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3107             new_channels = 5;
3108       }
3109
3110       if (new_channels == 5) {
3111          /* then try decreasing load size (at the cost of more loads) */
3112          new_channels = *channels;
3113          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3114             new_channels--;
3115       }
3116
3117       if (new_channels < *channels)
3118          *channels = new_channels;
3119       num_channels = new_channels;
3120    }
3121
3122    switch (vtx_info->chan_format) {
3123    case V_008F0C_BUF_DATA_FORMAT_8:
3124       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3125                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3126    case V_008F0C_BUF_DATA_FORMAT_16:
3127       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3128                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3129    case V_008F0C_BUF_DATA_FORMAT_32:
3130       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3131                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3132    }
3133    unreachable("shouldn't reach here");
3134    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3135 }
3136
3137 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3138  * so we may need to fix it up. */
3139 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3140 {
3141    Builder bld(ctx->program, ctx->block);
3142
3143    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3144       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3145
3146    /* For the integer-like cases, do a natural sign extension.
3147     *
3148     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3149     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3150     * exponent.
3151     */
3152    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3153    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3154
3155    /* Convert back to the right type. */
3156    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3157       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3158       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3159       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3160    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3161       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3162    }
3163
3164    return alpha;
3165 }
3166
3167 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3168 {
3169    Builder bld(ctx->program, ctx->block);
3170    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3171    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3172
3173       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3174       if (off_instr->type != nir_instr_type_load_const) {
3175          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3176          nir_print_instr(off_instr, stderr);
3177          fprintf(stderr, "\n");
3178       }
3179       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3180
3181       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3182
3183       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3184       unsigned component = nir_intrinsic_component(instr);
3185       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3186       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3187       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3188       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3189
3190       unsigned dfmt = attrib_format & 0xf;
3191       unsigned nfmt = (attrib_format >> 4) & 0x7;
3192       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3193
3194       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3195       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3196       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3197       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3198       if (post_shuffle)
3199          num_channels = MAX2(num_channels, 3);
3200
3201       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3202       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3203
3204       Temp index;
3205       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3206          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3207          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3208          if (divisor) {
3209             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3210             if (divisor != 1) {
3211                Temp divided = bld.tmp(v1);
3212                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3213                index = bld.vadd32(bld.def(v1), start_instance, divided);
3214             } else {
3215                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3216             }
3217          } else {
3218             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3219          }
3220       } else {
3221          index = bld.vadd32(bld.def(v1),
3222                             get_arg(ctx, ctx->args->ac.base_vertex),
3223                             get_arg(ctx, ctx->args->ac.vertex_id));
3224       }
3225
3226       Temp channels[num_channels];
3227       unsigned channel_start = 0;
3228       bool direct_fetch = false;
3229
3230       /* skip unused channels at the start */
3231       if (vtx_info->chan_byte_size && !post_shuffle) {
3232          channel_start = ffs(mask) - 1;
3233          for (unsigned i = 0; i < channel_start; i++)
3234             channels[i] = Temp(0, s1);
3235       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3236          num_channels = 3 - (ffs(mask) - 1);
3237       }
3238
3239       /* load channels */
3240       while (channel_start < num_channels) {
3241          unsigned fetch_size = num_channels - channel_start;
3242          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3243          bool expanded = false;
3244
3245          /* use MUBUF when possible to avoid possible alignment issues */
3246          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3247          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3248                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3249                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3250                           vtx_info->chan_byte_size == 4;
3251          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3252          if (!use_mubuf) {
3253             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3254          } else {
3255             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3256                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3257                fetch_size = 4;
3258                expanded = true;
3259             }
3260          }
3261
3262          Temp fetch_index = index;
3263          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3264             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3265             fetch_offset = fetch_offset % attrib_stride;
3266          }
3267
3268          Operand soffset(0u);
3269          if (fetch_offset >= 4096) {
3270             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3271             fetch_offset %= 4096;
3272          }
3273
3274          aco_opcode opcode;
3275          switch (fetch_size) {
3276          case 1:
3277             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3278             break;
3279          case 2:
3280             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3281             break;
3282          case 3:
3283             assert(ctx->options->chip_class >= GFX7 ||
3284                    (!use_mubuf && ctx->options->chip_class == GFX6));
3285             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3286             break;
3287          case 4:
3288             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3289             break;
3290          default:
3291             unreachable("Unimplemented load_input vector size");
3292          }
3293
3294          Temp fetch_dst;
3295          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3296              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3297                            num_channels <= 3)) {
3298             direct_fetch = true;
3299             fetch_dst = dst;
3300          } else {
3301             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3302          }
3303
3304          if (use_mubuf) {
3305             Instruction *mubuf = bld.mubuf(opcode,
3306                                            Definition(fetch_dst), list, fetch_index, soffset,
3307                                            fetch_offset, false, true).instr;
3308             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3309          } else {
3310             Instruction *mtbuf = bld.mtbuf(opcode,
3311                                            Definition(fetch_dst), list, fetch_index, soffset,
3312                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3313             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3314          }
3315
3316          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3317
3318          if (fetch_size == 1) {
3319             channels[channel_start] = fetch_dst;
3320          } else {
3321             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3322                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3323          }
3324
3325          channel_start += fetch_size;
3326       }
3327
3328       if (!direct_fetch) {
3329          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3330                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3331
3332          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3333          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3334          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3335
3336          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3337          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3338          unsigned num_temp = 0;
3339          for (unsigned i = 0; i < dst.size(); i++) {
3340             unsigned idx = i + component;
3341             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3342                Temp channel = channels[swizzle[idx]];
3343                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3344                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3345                vec->operands[i] = Operand(channel);
3346
3347                num_temp++;
3348                elems[i] = channel;
3349             } else if (is_float && idx == 3) {
3350                vec->operands[i] = Operand(0x3f800000u);
3351             } else if (!is_float && idx == 3) {
3352                vec->operands[i] = Operand(1u);
3353             } else {
3354                vec->operands[i] = Operand(0u);
3355             }
3356          }
3357          vec->definitions[0] = Definition(dst);
3358          ctx->block->instructions.emplace_back(std::move(vec));
3359          emit_split_vector(ctx, dst, dst.size());
3360
3361          if (num_temp == dst.size())
3362             ctx->allocated_vec.emplace(dst.id(), elems);
3363       }
3364    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3365       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3366       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3367       if (off_instr->type != nir_instr_type_load_const ||
3368           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3369          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3370          nir_print_instr(off_instr, stderr);
3371          fprintf(stderr, "\n");
3372       }
3373
3374       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3375       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3376       if (offset) {
3377          assert(offset->u32 == 0);
3378       } else {
3379          /* the lower 15bit of the prim_mask contain the offset into LDS
3380           * while the upper bits contain the number of prims */
3381          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3382          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3383          Builder bld(ctx->program, ctx->block);
3384          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3385          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3386          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3387          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3388          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3389       }
3390
3391       unsigned idx = nir_intrinsic_base(instr);
3392       unsigned component = nir_intrinsic_component(instr);
3393       unsigned vertex_id = 2; /* P0 */
3394
3395       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3396          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3397          switch (src0->u32) {
3398          case 0:
3399             vertex_id = 2; /* P0 */
3400             break;
3401          case 1:
3402             vertex_id = 0; /* P10 */
3403             break;
3404          case 2:
3405             vertex_id = 1; /* P20 */
3406             break;
3407          default:
3408             unreachable("invalid vertex index");
3409          }
3410       }
3411
3412       if (dst.size() == 1) {
3413          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3414       } else {
3415          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3416          for (unsigned i = 0; i < dst.size(); i++)
3417             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3418          vec->definitions[0] = Definition(dst);
3419          bld.insert(std::move(vec));
3420       }
3421
3422    } else {
3423       unreachable("Shader stage not implemented");
3424    }
3425 }
3426
3427 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3428 {
3429    assert(ctx->stage == vertex_geometry_gs || ctx->stage == geometry_gs);
3430    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3431
3432    Builder bld(ctx->program, ctx->block);
3433    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3434
3435    Temp offset = Temp();
3436    if (instr->src[0].ssa->parent_instr->type != nir_instr_type_load_const) {
3437       /* better code could be created, but this case probably doesn't happen
3438        * much in practice */
3439       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
3440       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3441          Temp elem;
3442          if (ctx->stage == vertex_geometry_gs) {
3443             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3444             if (i % 2u)
3445                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3446          } else {
3447             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3448          }
3449          if (offset.id()) {
3450             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(s2)),
3451                                  Operand(i), indirect_vertex);
3452             offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), offset, elem, cond);
3453          } else {
3454             offset = elem;
3455          }
3456       }
3457       if (ctx->stage == vertex_geometry_gs)
3458          offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), offset);
3459    } else {
3460       unsigned vertex = nir_src_as_uint(instr->src[0]);
3461       if (ctx->stage == vertex_geometry_gs)
3462          offset = bld.vop3(
3463          aco_opcode::v_bfe_u32, bld.def(v1), get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3464             Operand((vertex % 2u) * 16u), Operand(16u));
3465       else
3466          offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3467    }
3468
3469    unsigned const_offset = nir_intrinsic_base(instr);
3470    const_offset += nir_intrinsic_component(instr);
3471
3472    nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3473    if (off_instr->type != nir_instr_type_load_const) {
3474       Temp indirect_offset = get_ssa_temp(ctx, instr->src[1].ssa);
3475       offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u),
3476                         bld.vadd32(bld.def(v1), indirect_offset, offset));
3477    } else {
3478       const_offset += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3479    }
3480    const_offset *= 4u;
3481
3482    offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), offset);
3483
3484    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3485    if (ctx->stage == geometry_gs) {
3486       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3487
3488       const_offset *= ctx->program->wave_size;
3489
3490       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3491       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(
3492          aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1)};
3493       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++) {
3494          Temp subelems[2];
3495          for (unsigned j = 0; j < elem_size_bytes / 4; j++) {
3496             Operand soffset(0u);
3497             if (const_offset >= 4096u)
3498                soffset = bld.copy(bld.def(s1), Operand(const_offset / 4096u * 4096u));
3499
3500             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
3501             mubuf->definitions[0] = bld.def(v1);
3502             subelems[j] = mubuf->definitions[0].getTemp();
3503             mubuf->operands[0] = Operand(esgs_ring);
3504             mubuf->operands[1] = Operand(offset);
3505             mubuf->operands[2] = Operand(soffset);
3506             mubuf->offen = true;
3507             mubuf->offset = const_offset % 4096u;
3508             mubuf->glc = true;
3509             mubuf->dlc = ctx->options->chip_class >= GFX10;
3510             mubuf->barrier = barrier_none;
3511             mubuf->can_reorder = true;
3512             bld.insert(std::move(mubuf));
3513
3514             const_offset += ctx->program->wave_size * 4u;
3515          }
3516
3517          if (elem_size_bytes == 4)
3518             elems[i] = subelems[0];
3519          else
3520             elems[i] = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), subelems[0], subelems[1]);
3521          vec->operands[i] = Operand(elems[i]);
3522       }
3523       vec->definitions[0] = Definition(dst);
3524       ctx->block->instructions.emplace_back(std::move(vec));
3525       ctx->allocated_vec.emplace(dst.id(), elems);
3526    } else {
3527       unsigned align = calculate_lds_alignment(ctx, const_offset);
3528       load_lds(ctx, elem_size_bytes, dst, offset, const_offset, align);
3529    }
3530 }
3531
3532 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
3533 {
3534    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3535
3536    Builder bld(ctx->program, ctx->block);
3537    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3538
3539    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
3540    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
3541    Operand tes_w(0u);
3542
3543    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
3544       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
3545       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
3546       tes_w = Operand(tmp);
3547    }
3548
3549    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
3550    emit_split_vector(ctx, tess_coord, 3);
3551 }
3552
3553 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
3554 {
3555    if (ctx->program->info->need_indirect_descriptor_sets) {
3556       Builder bld(ctx->program, ctx->block);
3557       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
3558       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
3559       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
3560    }
3561
3562    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
3563 }
3564
3565
3566 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
3567 {
3568    Builder bld(ctx->program, ctx->block);
3569    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
3570    if (!ctx->divergent_vals[instr->dest.ssa.index])
3571       index = bld.as_uniform(index);
3572    unsigned desc_set = nir_intrinsic_desc_set(instr);
3573    unsigned binding = nir_intrinsic_binding(instr);
3574
3575    Temp desc_ptr;
3576    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
3577    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
3578    unsigned offset = layout->binding[binding].offset;
3579    unsigned stride;
3580    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
3581        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
3582       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
3583       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
3584       offset = pipeline_layout->push_constant_size + 16 * idx;
3585       stride = 16;
3586    } else {
3587       desc_ptr = load_desc_ptr(ctx, desc_set);
3588       stride = layout->binding[binding].size;
3589    }
3590
3591    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
3592    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
3593    if (stride != 1) {
3594       if (nir_const_index) {
3595          const_index = const_index * stride;
3596       } else if (index.type() == RegType::vgpr) {
3597          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
3598          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
3599       } else {
3600          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
3601       }
3602    }
3603    if (offset) {
3604       if (nir_const_index) {
3605          const_index = const_index + offset;
3606       } else if (index.type() == RegType::vgpr) {
3607          index = bld.vadd32(bld.def(v1), Operand(offset), index);
3608       } else {
3609          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
3610       }
3611    }
3612
3613    if (nir_const_index && const_index == 0) {
3614       index = desc_ptr;
3615    } else if (index.type() == RegType::vgpr) {
3616       index = bld.vadd32(bld.def(v1),
3617                          nir_const_index ? Operand(const_index) : Operand(index),
3618                          Operand(desc_ptr));
3619    } else {
3620       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
3621                        nir_const_index ? Operand(const_index) : Operand(index),
3622                        Operand(desc_ptr));
3623    }
3624
3625    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
3626 }
3627
3628 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
3629                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
3630 {
3631    Builder bld(ctx->program, ctx->block);
3632
3633    unsigned num_bytes = dst.size() * 4;
3634    bool dlc = glc && ctx->options->chip_class >= GFX10;
3635
3636    aco_opcode op;
3637    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
3638       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
3639       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
3640       unsigned const_offset = 0;
3641
3642       Temp lower = Temp();
3643       if (num_bytes > 16) {
3644          assert(num_components == 3 || num_components == 4);
3645          op = aco_opcode::buffer_load_dwordx4;
3646          lower = bld.tmp(v4);
3647          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3648          mubuf->definitions[0] = Definition(lower);
3649          mubuf->operands[0] = Operand(rsrc);
3650          mubuf->operands[1] = vaddr;
3651          mubuf->operands[2] = soffset;
3652          mubuf->offen = (offset.type() == RegType::vgpr);
3653          mubuf->glc = glc;
3654          mubuf->dlc = dlc;
3655          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3656          mubuf->can_reorder = readonly;
3657          bld.insert(std::move(mubuf));
3658          emit_split_vector(ctx, lower, 2);
3659          num_bytes -= 16;
3660          const_offset = 16;
3661       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
3662          /* GFX6 doesn't support loading vec3, expand to vec4. */
3663          num_bytes = 16;
3664       }
3665
3666       switch (num_bytes) {
3667          case 4:
3668             op = aco_opcode::buffer_load_dword;
3669             break;
3670          case 8:
3671             op = aco_opcode::buffer_load_dwordx2;
3672             break;
3673          case 12:
3674             assert(ctx->options->chip_class > GFX6);
3675             op = aco_opcode::buffer_load_dwordx3;
3676             break;
3677          case 16:
3678             op = aco_opcode::buffer_load_dwordx4;
3679             break;
3680          default:
3681             unreachable("Load SSBO not implemented for this size.");
3682       }
3683       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
3684       mubuf->operands[0] = Operand(rsrc);
3685       mubuf->operands[1] = vaddr;
3686       mubuf->operands[2] = soffset;
3687       mubuf->offen = (offset.type() == RegType::vgpr);
3688       mubuf->glc = glc;
3689       mubuf->dlc = dlc;
3690       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
3691       mubuf->can_reorder = readonly;
3692       mubuf->offset = const_offset;
3693       aco_ptr<Instruction> instr = std::move(mubuf);
3694
3695       if (dst.size() > 4) {
3696          assert(lower != Temp());
3697          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
3698          instr->definitions[0] = Definition(upper);
3699          bld.insert(std::move(instr));
3700          if (dst.size() == 8)
3701             emit_split_vector(ctx, upper, 2);
3702          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
3703          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
3704          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
3705          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
3706          if (dst.size() == 8)
3707             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
3708       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
3709          Temp vec = bld.tmp(v4);
3710          instr->definitions[0] = Definition(vec);
3711          bld.insert(std::move(instr));
3712          emit_split_vector(ctx, vec, 4);
3713
3714          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
3715          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
3716          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
3717          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
3718       }
3719
3720       if (dst.type() == RegType::sgpr) {
3721          Temp vec = bld.tmp(RegType::vgpr, dst.size());
3722          instr->definitions[0] = Definition(vec);
3723          bld.insert(std::move(instr));
3724          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
3725       } else {
3726          instr->definitions[0] = Definition(dst);
3727          bld.insert(std::move(instr));
3728          emit_split_vector(ctx, dst, num_components);
3729       }
3730    } else {
3731       switch (num_bytes) {
3732          case 4:
3733             op = aco_opcode::s_buffer_load_dword;
3734             break;
3735          case 8:
3736             op = aco_opcode::s_buffer_load_dwordx2;
3737             break;
3738          case 12:
3739          case 16:
3740             op = aco_opcode::s_buffer_load_dwordx4;
3741             break;
3742          case 24:
3743          case 32:
3744             op = aco_opcode::s_buffer_load_dwordx8;
3745             break;
3746          default:
3747             unreachable("Load SSBO not implemented for this size.");
3748       }
3749       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
3750       load->operands[0] = Operand(rsrc);
3751       load->operands[1] = Operand(bld.as_uniform(offset));
3752       assert(load->operands[1].getTemp().type() == RegType::sgpr);
3753       load->definitions[0] = Definition(dst);
3754       load->glc = glc;
3755       load->dlc = dlc;
3756       load->barrier = readonly ? barrier_none : barrier_buffer;
3757       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3758       assert(ctx->options->chip_class >= GFX8 || !glc);
3759
3760       /* trim vector */
3761       if (dst.size() == 3) {
3762          Temp vec = bld.tmp(s4);
3763          load->definitions[0] = Definition(vec);
3764          bld.insert(std::move(load));
3765          emit_split_vector(ctx, vec, 4);
3766
3767          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3768                     emit_extract_vector(ctx, vec, 0, s1),
3769                     emit_extract_vector(ctx, vec, 1, s1),
3770                     emit_extract_vector(ctx, vec, 2, s1));
3771       } else if (dst.size() == 6) {
3772          Temp vec = bld.tmp(s8);
3773          load->definitions[0] = Definition(vec);
3774          bld.insert(std::move(load));
3775          emit_split_vector(ctx, vec, 4);
3776
3777          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3778                     emit_extract_vector(ctx, vec, 0, s2),
3779                     emit_extract_vector(ctx, vec, 1, s2),
3780                     emit_extract_vector(ctx, vec, 2, s2));
3781       } else {
3782          bld.insert(std::move(load));
3783       }
3784       emit_split_vector(ctx, dst, num_components);
3785    }
3786 }
3787
3788 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
3789 {
3790    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3791    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
3792
3793    Builder bld(ctx->program, ctx->block);
3794
3795    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
3796    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
3797    unsigned binding = nir_intrinsic_binding(idx_instr);
3798    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3799
3800    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
3801       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3802                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3803                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3804                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3805       if (ctx->options->chip_class >= GFX10) {
3806          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3807                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3808                       S_008F0C_RESOURCE_LEVEL(1);
3809       } else {
3810          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3811                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3812       }
3813       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
3814                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
3815                                      Operand(0xFFFFFFFFu),
3816                                      Operand(desc_type));
3817       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3818                         rsrc, upper_dwords);
3819    } else {
3820       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
3821       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
3822    }
3823
3824    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
3825 }
3826
3827 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3828 {
3829    Builder bld(ctx->program, ctx->block);
3830    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3831
3832    unsigned offset = nir_intrinsic_base(instr);
3833    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
3834    if (index_cv && instr->dest.ssa.bit_size == 32) {
3835
3836       unsigned count = instr->dest.ssa.num_components;
3837       unsigned start = (offset + index_cv->u32) / 4u;
3838       start -= ctx->args->ac.base_inline_push_consts;
3839       if (start + count <= ctx->args->ac.num_inline_push_consts) {
3840          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3841          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
3842          for (unsigned i = 0; i < count; ++i) {
3843             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
3844             vec->operands[i] = Operand{elems[i]};
3845          }
3846          vec->definitions[0] = Definition(dst);
3847          ctx->block->instructions.emplace_back(std::move(vec));
3848          ctx->allocated_vec.emplace(dst.id(), elems);
3849          return;
3850       }
3851    }
3852
3853    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
3854    if (offset != 0) // TODO check if index != 0 as well
3855       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
3856    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
3857    Temp vec = dst;
3858    bool trim = false;
3859    aco_opcode op;
3860
3861    switch (dst.size()) {
3862    case 1:
3863       op = aco_opcode::s_load_dword;
3864       break;
3865    case 2:
3866       op = aco_opcode::s_load_dwordx2;
3867       break;
3868    case 3:
3869       vec = bld.tmp(s4);
3870       trim = true;
3871    case 4:
3872       op = aco_opcode::s_load_dwordx4;
3873       break;
3874    case 6:
3875       vec = bld.tmp(s8);
3876       trim = true;
3877    case 8:
3878       op = aco_opcode::s_load_dwordx8;
3879       break;
3880    default:
3881       unreachable("unimplemented or forbidden load_push_constant.");
3882    }
3883
3884    bld.smem(op, Definition(vec), ptr, index);
3885
3886    if (trim) {
3887       emit_split_vector(ctx, vec, 4);
3888       RegClass rc = dst.size() == 3 ? s1 : s2;
3889       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
3890                  emit_extract_vector(ctx, vec, 0, rc),
3891                  emit_extract_vector(ctx, vec, 1, rc),
3892                  emit_extract_vector(ctx, vec, 2, rc));
3893
3894    }
3895    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
3896 }
3897
3898 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
3899 {
3900    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3901
3902    Builder bld(ctx->program, ctx->block);
3903
3904    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3905                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3906                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3907                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3908    if (ctx->options->chip_class >= GFX10) {
3909       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3910                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3911                    S_008F0C_RESOURCE_LEVEL(1);
3912    } else {
3913       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3914                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3915    }
3916
3917    unsigned base = nir_intrinsic_base(instr);
3918    unsigned range = nir_intrinsic_range(instr);
3919
3920    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
3921    if (base && offset.type() == RegType::sgpr)
3922       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
3923    else if (base && offset.type() == RegType::vgpr)
3924       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
3925
3926    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
3927                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
3928                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
3929                           Operand(desc_type));
3930
3931    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
3932 }
3933
3934 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
3935 {
3936    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3937       ctx->cf_info.exec_potentially_empty_discard = true;
3938
3939    ctx->program->needs_exact = true;
3940
3941    // TODO: optimize uniform conditions
3942    Builder bld(ctx->program, ctx->block);
3943    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3944    assert(src.regClass() == bld.lm);
3945    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
3946    bld.pseudo(aco_opcode::p_discard_if, src);
3947    ctx->block->kind |= block_kind_uses_discard_if;
3948    return;
3949 }
3950
3951 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
3952 {
3953    Builder bld(ctx->program, ctx->block);
3954
3955    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
3956       ctx->cf_info.exec_potentially_empty_discard = true;
3957
3958    bool divergent = ctx->cf_info.parent_if.is_divergent ||
3959                     ctx->cf_info.parent_loop.has_divergent_continue;
3960
3961    if (ctx->block->loop_nest_depth &&
3962        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
3963       /* we handle discards the same way as jump instructions */
3964       append_logical_end(ctx->block);
3965
3966       /* in loops, discard behaves like break */
3967       Block *linear_target = ctx->cf_info.parent_loop.exit;
3968       ctx->block->kind |= block_kind_discard;
3969
3970       if (!divergent) {
3971          /* uniform discard - loop ends here */
3972          assert(nir_instr_is_last(&instr->instr));
3973          ctx->block->kind |= block_kind_uniform;
3974          ctx->cf_info.has_branch = true;
3975          bld.branch(aco_opcode::p_branch);
3976          add_linear_edge(ctx->block->index, linear_target);
3977          return;
3978       }
3979
3980       /* we add a break right behind the discard() instructions */
3981       ctx->block->kind |= block_kind_break;
3982       unsigned idx = ctx->block->index;
3983
3984       /* remove critical edges from linear CFG */
3985       bld.branch(aco_opcode::p_branch);
3986       Block* break_block = ctx->program->create_and_insert_block();
3987       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3988       break_block->kind |= block_kind_uniform;
3989       add_linear_edge(idx, break_block);
3990       add_linear_edge(break_block->index, linear_target);
3991       bld.reset(break_block);
3992       bld.branch(aco_opcode::p_branch);
3993
3994       Block* continue_block = ctx->program->create_and_insert_block();
3995       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
3996       add_linear_edge(idx, continue_block);
3997       append_logical_start(continue_block);
3998       ctx->block = continue_block;
3999
4000       return;
4001    }
4002
4003    /* it can currently happen that NIR doesn't remove the unreachable code */
4004    if (!nir_instr_is_last(&instr->instr)) {
4005       ctx->program->needs_exact = true;
4006       /* save exec somewhere temporarily so that it doesn't get
4007        * overwritten before the discard from outer exec masks */
4008       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4009       bld.pseudo(aco_opcode::p_discard_if, cond);
4010       ctx->block->kind |= block_kind_uses_discard_if;
4011       return;
4012    }
4013
4014    /* This condition is incorrect for uniformly branched discards in a loop
4015     * predicated by a divergent condition, but the above code catches that case
4016     * and the discard would end up turning into a discard_if.
4017     * For example:
4018     * if (divergent) {
4019     *    while (...) {
4020     *       if (uniform) {
4021     *          discard;
4022     *       }
4023     *    }
4024     * }
4025     */
4026    if (!ctx->cf_info.parent_if.is_divergent) {
4027       /* program just ends here */
4028       ctx->block->kind |= block_kind_uniform;
4029       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4030               0 /* enabled mask */, 9 /* dest */,
4031               false /* compressed */, true/* done */, true /* valid mask */);
4032       bld.sopp(aco_opcode::s_endpgm);
4033       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4034    } else {
4035       ctx->block->kind |= block_kind_discard;
4036       /* branch and linear edge is added by visit_if() */
4037    }
4038 }
4039
4040 enum aco_descriptor_type {
4041    ACO_DESC_IMAGE,
4042    ACO_DESC_FMASK,
4043    ACO_DESC_SAMPLER,
4044    ACO_DESC_BUFFER,
4045    ACO_DESC_PLANE_0,
4046    ACO_DESC_PLANE_1,
4047    ACO_DESC_PLANE_2,
4048 };
4049
4050 static bool
4051 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4052    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4053       return false;
4054    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4055    return dim == ac_image_cube ||
4056           dim == ac_image_1darray ||
4057           dim == ac_image_2darray ||
4058           dim == ac_image_2darraymsaa;
4059 }
4060
4061 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4062                       enum aco_descriptor_type desc_type,
4063                       const nir_tex_instr *tex_instr, bool image, bool write)
4064 {
4065 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4066    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4067    if (it != ctx->tex_desc.end())
4068       return it->second;
4069 */
4070    Temp index = Temp();
4071    bool index_set = false;
4072    unsigned constant_index = 0;
4073    unsigned descriptor_set;
4074    unsigned base_index;
4075    Builder bld(ctx->program, ctx->block);
4076
4077    if (!deref_instr) {
4078       assert(tex_instr && !image);
4079       descriptor_set = 0;
4080       base_index = tex_instr->sampler_index;
4081    } else {
4082       while(deref_instr->deref_type != nir_deref_type_var) {
4083          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4084          if (!array_size)
4085             array_size = 1;
4086
4087          assert(deref_instr->deref_type == nir_deref_type_array);
4088          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4089          if (const_value) {
4090             constant_index += array_size * const_value->u32;
4091          } else {
4092             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4093             if (indirect.type() == RegType::vgpr)
4094                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4095
4096             if (array_size != 1)
4097                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4098
4099             if (!index_set) {
4100                index = indirect;
4101                index_set = true;
4102             } else {
4103                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4104             }
4105          }
4106
4107          deref_instr = nir_src_as_deref(deref_instr->parent);
4108       }
4109       descriptor_set = deref_instr->var->data.descriptor_set;
4110       base_index = deref_instr->var->data.binding;
4111    }
4112
4113    Temp list = load_desc_ptr(ctx, descriptor_set);
4114    list = convert_pointer_to_64_bit(ctx, list);
4115
4116    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4117    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4118    unsigned offset = binding->offset;
4119    unsigned stride = binding->size;
4120    aco_opcode opcode;
4121    RegClass type;
4122
4123    assert(base_index < layout->binding_count);
4124
4125    switch (desc_type) {
4126    case ACO_DESC_IMAGE:
4127       type = s8;
4128       opcode = aco_opcode::s_load_dwordx8;
4129       break;
4130    case ACO_DESC_FMASK:
4131       type = s8;
4132       opcode = aco_opcode::s_load_dwordx8;
4133       offset += 32;
4134       break;
4135    case ACO_DESC_SAMPLER:
4136       type = s4;
4137       opcode = aco_opcode::s_load_dwordx4;
4138       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4139          offset += radv_combined_image_descriptor_sampler_offset(binding);
4140       break;
4141    case ACO_DESC_BUFFER:
4142       type = s4;
4143       opcode = aco_opcode::s_load_dwordx4;
4144       break;
4145    case ACO_DESC_PLANE_0:
4146    case ACO_DESC_PLANE_1:
4147       type = s8;
4148       opcode = aco_opcode::s_load_dwordx8;
4149       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4150       break;
4151    case ACO_DESC_PLANE_2:
4152       type = s4;
4153       opcode = aco_opcode::s_load_dwordx4;
4154       offset += 64;
4155       break;
4156    default:
4157       unreachable("invalid desc_type\n");
4158    }
4159
4160    offset += constant_index * stride;
4161
4162    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4163       (!index_set || binding->immutable_samplers_equal)) {
4164       if (binding->immutable_samplers_equal)
4165          constant_index = 0;
4166
4167       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4168       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4169                         Operand(samplers[constant_index * 4 + 0]),
4170                         Operand(samplers[constant_index * 4 + 1]),
4171                         Operand(samplers[constant_index * 4 + 2]),
4172                         Operand(samplers[constant_index * 4 + 3]));
4173    }
4174
4175    Operand off;
4176    if (!index_set) {
4177       off = bld.copy(bld.def(s1), Operand(offset));
4178    } else {
4179       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4180                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4181    }
4182
4183    Temp res = bld.smem(opcode, bld.def(type), list, off);
4184
4185    if (desc_type == ACO_DESC_PLANE_2) {
4186       Temp components[8];
4187       for (unsigned i = 0; i < 8; i++)
4188          components[i] = bld.tmp(s1);
4189       bld.pseudo(aco_opcode::p_split_vector,
4190                  Definition(components[0]),
4191                  Definition(components[1]),
4192                  Definition(components[2]),
4193                  Definition(components[3]),
4194                  res);
4195
4196       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4197       bld.pseudo(aco_opcode::p_split_vector,
4198                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4199                  Definition(components[4]),
4200                  Definition(components[5]),
4201                  Definition(components[6]),
4202                  Definition(components[7]),
4203                  desc2);
4204
4205       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4206                        components[0], components[1], components[2], components[3],
4207                        components[4], components[5], components[6], components[7]);
4208    }
4209
4210    return res;
4211 }
4212
4213 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4214 {
4215    switch (dim) {
4216    case GLSL_SAMPLER_DIM_BUF:
4217       return 1;
4218    case GLSL_SAMPLER_DIM_1D:
4219       return array ? 2 : 1;
4220    case GLSL_SAMPLER_DIM_2D:
4221       return array ? 3 : 2;
4222    case GLSL_SAMPLER_DIM_MS:
4223       return array ? 4 : 3;
4224    case GLSL_SAMPLER_DIM_3D:
4225    case GLSL_SAMPLER_DIM_CUBE:
4226       return 3;
4227    case GLSL_SAMPLER_DIM_RECT:
4228    case GLSL_SAMPLER_DIM_SUBPASS:
4229       return 2;
4230    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4231       return 3;
4232    default:
4233       break;
4234    }
4235    return 0;
4236 }
4237
4238
4239 /* Adjust the sample index according to FMASK.
4240  *
4241  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4242  * which is the identity mapping. Each nibble says which physical sample
4243  * should be fetched to get that sample.
4244  *
4245  * For example, 0x11111100 means there are only 2 samples stored and
4246  * the second sample covers 3/4 of the pixel. When reading samples 0
4247  * and 1, return physical sample 0 (determined by the first two 0s
4248  * in FMASK), otherwise return physical sample 1.
4249  *
4250  * The sample index should be adjusted as follows:
4251  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4252  */
4253 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4254 {
4255    Builder bld(ctx->program, ctx->block);
4256    Temp fmask = bld.tmp(v1);
4257    unsigned dim = ctx->options->chip_class >= GFX10
4258                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4259                   : 0;
4260
4261    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4262                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4263    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4264    load->operands[0] = Operand(fmask_desc_ptr);
4265    load->operands[1] = Operand(s4); /* no sampler */
4266    load->operands[2] = Operand(coord);
4267    load->definitions[0] = Definition(fmask);
4268    load->glc = false;
4269    load->dlc = false;
4270    load->dmask = 0x1;
4271    load->unrm = true;
4272    load->da = da;
4273    load->dim = dim;
4274    load->can_reorder = true; /* fmask images shouldn't be modified */
4275    ctx->block->instructions.emplace_back(std::move(load));
4276
4277    Operand sample_index4;
4278    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4279       sample_index4 = Operand(sample_index.constantValue() << 2);
4280    } else if (sample_index.regClass() == s1) {
4281       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4282    } else {
4283       assert(sample_index.regClass() == v1);
4284       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4285    }
4286
4287    Temp final_sample;
4288    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4289       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4290    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4291       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4292    else
4293       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4294
4295    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4296     * resource descriptor is 0 (invalid),
4297     */
4298    Temp compare = bld.tmp(bld.lm);
4299    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4300                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4301
4302    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4303
4304    /* Replace the MSAA sample index. */
4305    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4306 }
4307
4308 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4309 {
4310
4311    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4312    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4313    bool is_array = glsl_sampler_type_is_array(type);
4314    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4315    assert(!add_frag_pos && "Input attachments should be lowered.");
4316    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4317    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4318    int count = image_type_to_components_count(dim, is_array);
4319    std::vector<Temp> coords(count);
4320    Builder bld(ctx->program, ctx->block);
4321
4322    if (is_ms) {
4323       count--;
4324       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4325       /* get sample index */
4326       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4327          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4328          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4329          std::vector<Temp> fmask_load_address;
4330          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4331             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4332
4333          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4334          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4335       } else {
4336          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4337       }
4338    }
4339
4340    if (gfx9_1d) {
4341       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4342       coords.resize(coords.size() + 1);
4343       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4344       if (is_array)
4345          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4346    } else {
4347       for (int i = 0; i < count; i++)
4348          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4349    }
4350
4351    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4352        instr->intrinsic == nir_intrinsic_image_deref_store) {
4353       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4354       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4355
4356       if (!level_zero)
4357          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4358    }
4359
4360    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4361    for (unsigned i = 0; i < coords.size(); i++)
4362       vec->operands[i] = Operand(coords[i]);
4363    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4364    vec->definitions[0] = Definition(res);
4365    ctx->block->instructions.emplace_back(std::move(vec));
4366    return res;
4367 }
4368
4369
4370 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4371 {
4372    Builder bld(ctx->program, ctx->block);
4373    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4374    const struct glsl_type *type = glsl_without_array(var->type);
4375    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4376    bool is_array = glsl_sampler_type_is_array(type);
4377    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4378
4379    if (dim == GLSL_SAMPLER_DIM_BUF) {
4380       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4381       unsigned num_channels = util_last_bit(mask);
4382       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4383       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4384
4385       aco_opcode opcode;
4386       switch (num_channels) {
4387       case 1:
4388          opcode = aco_opcode::buffer_load_format_x;
4389          break;
4390       case 2:
4391          opcode = aco_opcode::buffer_load_format_xy;
4392          break;
4393       case 3:
4394          opcode = aco_opcode::buffer_load_format_xyz;
4395          break;
4396       case 4:
4397          opcode = aco_opcode::buffer_load_format_xyzw;
4398          break;
4399       default:
4400          unreachable(">4 channel buffer image load");
4401       }
4402       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4403       load->operands[0] = Operand(rsrc);
4404       load->operands[1] = Operand(vindex);
4405       load->operands[2] = Operand((uint32_t) 0);
4406       Temp tmp;
4407       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4408          tmp = dst;
4409       else
4410          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4411       load->definitions[0] = Definition(tmp);
4412       load->idxen = true;
4413       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4414       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4415       load->barrier = barrier_image;
4416       ctx->block->instructions.emplace_back(std::move(load));
4417
4418       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4419       return;
4420    }
4421
4422    Temp coords = get_image_coords(ctx, instr, type);
4423    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4424
4425    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4426    unsigned num_components = util_bitcount(dmask);
4427    Temp tmp;
4428    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4429       tmp = dst;
4430    else
4431       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4432
4433    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4434    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4435
4436    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4437    load->operands[0] = Operand(resource);
4438    load->operands[1] = Operand(s4); /* no sampler */
4439    load->operands[2] = Operand(coords);
4440    load->definitions[0] = Definition(tmp);
4441    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4442    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4443    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4444    load->dmask = dmask;
4445    load->unrm = true;
4446    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4447    load->barrier = barrier_image;
4448    ctx->block->instructions.emplace_back(std::move(load));
4449
4450    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4451    return;
4452 }
4453
4454 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4455 {
4456    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4457    const struct glsl_type *type = glsl_without_array(var->type);
4458    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4459    bool is_array = glsl_sampler_type_is_array(type);
4460    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4461
4462    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4463
4464    if (dim == GLSL_SAMPLER_DIM_BUF) {
4465       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4466       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4467       aco_opcode opcode;
4468       switch (data.size()) {
4469       case 1:
4470          opcode = aco_opcode::buffer_store_format_x;
4471          break;
4472       case 2:
4473          opcode = aco_opcode::buffer_store_format_xy;
4474          break;
4475       case 3:
4476          opcode = aco_opcode::buffer_store_format_xyz;
4477          break;
4478       case 4:
4479          opcode = aco_opcode::buffer_store_format_xyzw;
4480          break;
4481       default:
4482          unreachable(">4 channel buffer image store");
4483       }
4484       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4485       store->operands[0] = Operand(rsrc);
4486       store->operands[1] = Operand(vindex);
4487       store->operands[2] = Operand((uint32_t) 0);
4488       store->operands[3] = Operand(data);
4489       store->idxen = true;
4490       store->glc = glc;
4491       store->dlc = false;
4492       store->disable_wqm = true;
4493       store->barrier = barrier_image;
4494       ctx->program->needs_exact = true;
4495       ctx->block->instructions.emplace_back(std::move(store));
4496       return;
4497    }
4498
4499    assert(data.type() == RegType::vgpr);
4500    Temp coords = get_image_coords(ctx, instr, type);
4501    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4502
4503    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4504    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4505
4506    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
4507    store->operands[0] = Operand(resource);
4508    store->operands[1] = Operand(data);
4509    store->operands[2] = Operand(coords);
4510    store->glc = glc;
4511    store->dlc = false;
4512    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4513    store->dmask = (1 << data.size()) - 1;
4514    store->unrm = true;
4515    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4516    store->disable_wqm = true;
4517    store->barrier = barrier_image;
4518    ctx->program->needs_exact = true;
4519    ctx->block->instructions.emplace_back(std::move(store));
4520    return;
4521 }
4522
4523 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
4524 {
4525    /* return the previous value if dest is ever used */
4526    bool return_previous = false;
4527    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4528       return_previous = true;
4529       break;
4530    }
4531    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4532       return_previous = true;
4533       break;
4534    }
4535
4536    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4537    const struct glsl_type *type = glsl_without_array(var->type);
4538    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4539    bool is_array = glsl_sampler_type_is_array(type);
4540    Builder bld(ctx->program, ctx->block);
4541
4542    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4543    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
4544
4545    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
4546       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
4547
4548    aco_opcode buf_op, image_op;
4549    switch (instr->intrinsic) {
4550       case nir_intrinsic_image_deref_atomic_add:
4551          buf_op = aco_opcode::buffer_atomic_add;
4552          image_op = aco_opcode::image_atomic_add;
4553          break;
4554       case nir_intrinsic_image_deref_atomic_umin:
4555          buf_op = aco_opcode::buffer_atomic_umin;
4556          image_op = aco_opcode::image_atomic_umin;
4557          break;
4558       case nir_intrinsic_image_deref_atomic_imin:
4559          buf_op = aco_opcode::buffer_atomic_smin;
4560          image_op = aco_opcode::image_atomic_smin;
4561          break;
4562       case nir_intrinsic_image_deref_atomic_umax:
4563          buf_op = aco_opcode::buffer_atomic_umax;
4564          image_op = aco_opcode::image_atomic_umax;
4565          break;
4566       case nir_intrinsic_image_deref_atomic_imax:
4567          buf_op = aco_opcode::buffer_atomic_smax;
4568          image_op = aco_opcode::image_atomic_smax;
4569          break;
4570       case nir_intrinsic_image_deref_atomic_and:
4571          buf_op = aco_opcode::buffer_atomic_and;
4572          image_op = aco_opcode::image_atomic_and;
4573          break;
4574       case nir_intrinsic_image_deref_atomic_or:
4575          buf_op = aco_opcode::buffer_atomic_or;
4576          image_op = aco_opcode::image_atomic_or;
4577          break;
4578       case nir_intrinsic_image_deref_atomic_xor:
4579          buf_op = aco_opcode::buffer_atomic_xor;
4580          image_op = aco_opcode::image_atomic_xor;
4581          break;
4582       case nir_intrinsic_image_deref_atomic_exchange:
4583          buf_op = aco_opcode::buffer_atomic_swap;
4584          image_op = aco_opcode::image_atomic_swap;
4585          break;
4586       case nir_intrinsic_image_deref_atomic_comp_swap:
4587          buf_op = aco_opcode::buffer_atomic_cmpswap;
4588          image_op = aco_opcode::image_atomic_cmpswap;
4589          break;
4590       default:
4591          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4592    }
4593
4594    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4595
4596    if (dim == GLSL_SAMPLER_DIM_BUF) {
4597       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4598       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4599       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4600       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4601       mubuf->operands[0] = Operand(resource);
4602       mubuf->operands[1] = Operand(vindex);
4603       mubuf->operands[2] = Operand((uint32_t)0);
4604       mubuf->operands[3] = Operand(data);
4605       if (return_previous)
4606          mubuf->definitions[0] = Definition(dst);
4607       mubuf->offset = 0;
4608       mubuf->idxen = true;
4609       mubuf->glc = return_previous;
4610       mubuf->dlc = false; /* Not needed for atomics */
4611       mubuf->disable_wqm = true;
4612       mubuf->barrier = barrier_image;
4613       ctx->program->needs_exact = true;
4614       ctx->block->instructions.emplace_back(std::move(mubuf));
4615       return;
4616    }
4617
4618    Temp coords = get_image_coords(ctx, instr, type);
4619    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4620    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
4621    mimg->operands[0] = Operand(resource);
4622    mimg->operands[1] = Operand(data);
4623    mimg->operands[2] = Operand(coords);
4624    if (return_previous)
4625       mimg->definitions[0] = Definition(dst);
4626    mimg->glc = return_previous;
4627    mimg->dlc = false; /* Not needed for atomics */
4628    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4629    mimg->dmask = (1 << data.size()) - 1;
4630    mimg->unrm = true;
4631    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4632    mimg->disable_wqm = true;
4633    mimg->barrier = barrier_image;
4634    ctx->program->needs_exact = true;
4635    ctx->block->instructions.emplace_back(std::move(mimg));
4636    return;
4637 }
4638
4639 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
4640 {
4641    if (in_elements && ctx->options->chip_class == GFX8) {
4642       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
4643       Builder bld(ctx->program, ctx->block);
4644
4645       Temp size = emit_extract_vector(ctx, desc, 2, s1);
4646
4647       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
4648       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
4649
4650       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
4651       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
4652
4653       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
4654       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
4655
4656       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
4657       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
4658                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
4659       if (dst.type() == RegType::vgpr)
4660          bld.copy(Definition(dst), shr_dst);
4661
4662       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
4663    } else {
4664       emit_extract_vector(ctx, desc, 2, dst);
4665    }
4666 }
4667
4668 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
4669 {
4670    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4671    const struct glsl_type *type = glsl_without_array(var->type);
4672    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4673    bool is_array = glsl_sampler_type_is_array(type);
4674    Builder bld(ctx->program, ctx->block);
4675
4676    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
4677       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
4678       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
4679    }
4680
4681    /* LOD */
4682    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
4683
4684    /* Resource */
4685    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
4686
4687    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4688
4689    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
4690    mimg->operands[0] = Operand(resource);
4691    mimg->operands[1] = Operand(s4); /* no sampler */
4692    mimg->operands[2] = Operand(lod);
4693    uint8_t& dmask = mimg->dmask;
4694    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4695    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
4696    mimg->da = glsl_sampler_type_is_array(type);
4697    mimg->can_reorder = true;
4698    Definition& def = mimg->definitions[0];
4699    ctx->block->instructions.emplace_back(std::move(mimg));
4700
4701    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
4702        glsl_sampler_type_is_array(type)) {
4703
4704       assert(instr->dest.ssa.num_components == 3);
4705       Temp tmp = {ctx->program->allocateId(), v3};
4706       def = Definition(tmp);
4707       emit_split_vector(ctx, tmp, 3);
4708
4709       /* divide 3rd value by 6 by multiplying with magic number */
4710       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
4711       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
4712
4713       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4714                  emit_extract_vector(ctx, tmp, 0, v1),
4715                  emit_extract_vector(ctx, tmp, 1, v1),
4716                  by_6);
4717
4718    } else if (ctx->options->chip_class == GFX9 &&
4719               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
4720               glsl_sampler_type_is_array(type)) {
4721       assert(instr->dest.ssa.num_components == 2);
4722       def = Definition(dst);
4723       dmask = 0x5;
4724    } else {
4725       def = Definition(dst);
4726    }
4727
4728    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4729 }
4730
4731 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4732 {
4733    Builder bld(ctx->program, ctx->block);
4734    unsigned num_components = instr->num_components;
4735
4736    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4737    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4738    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4739
4740    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4741    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
4742 }
4743
4744 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4745 {
4746    Builder bld(ctx->program, ctx->block);
4747    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
4748    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
4749    unsigned writemask = nir_intrinsic_write_mask(instr);
4750    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
4751
4752    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
4753    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4754
4755    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
4756                ctx->options->chip_class >= GFX8;
4757    if (smem)
4758       offset = bld.as_uniform(offset);
4759    bool smem_nonfs = smem && ctx->stage != fragment_fs;
4760
4761    while (writemask) {
4762       int start, count;
4763       u_bit_scan_consecutive_range(&writemask, &start, &count);
4764       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
4765          /* GFX6 doesn't support storing vec3, split it. */
4766          writemask |= 1u << (start + 2);
4767          count = 2;
4768       }
4769       int num_bytes = count * elem_size_bytes;
4770
4771       if (num_bytes > 16) {
4772          assert(elem_size_bytes == 8);
4773          writemask |= (((count - 2) << 1) - 1) << (start + 2);
4774          count = 2;
4775          num_bytes = 16;
4776       }
4777
4778       // TODO: check alignment of sub-dword stores
4779       // TODO: split 3 bytes. there is no store instruction for that
4780
4781       Temp write_data;
4782       if (count != instr->num_components) {
4783          emit_split_vector(ctx, data, instr->num_components);
4784          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4785          for (int i = 0; i < count; i++) {
4786             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
4787             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
4788          }
4789          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
4790          vec->definitions[0] = Definition(write_data);
4791          ctx->block->instructions.emplace_back(std::move(vec));
4792       } else if (!smem && data.type() != RegType::vgpr) {
4793          assert(num_bytes % 4 == 0);
4794          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
4795       } else if (smem_nonfs && data.type() == RegType::vgpr) {
4796          assert(num_bytes % 4 == 0);
4797          write_data = bld.as_uniform(data);
4798       } else {
4799          write_data = data;
4800       }
4801
4802       aco_opcode vmem_op, smem_op;
4803       switch (num_bytes) {
4804          case 4:
4805             vmem_op = aco_opcode::buffer_store_dword;
4806             smem_op = aco_opcode::s_buffer_store_dword;
4807             break;
4808          case 8:
4809             vmem_op = aco_opcode::buffer_store_dwordx2;
4810             smem_op = aco_opcode::s_buffer_store_dwordx2;
4811             break;
4812          case 12:
4813             vmem_op = aco_opcode::buffer_store_dwordx3;
4814             smem_op = aco_opcode::last_opcode;
4815             assert(!smem && ctx->options->chip_class > GFX6);
4816             break;
4817          case 16:
4818             vmem_op = aco_opcode::buffer_store_dwordx4;
4819             smem_op = aco_opcode::s_buffer_store_dwordx4;
4820             break;
4821          default:
4822             unreachable("Store SSBO not implemented for this size.");
4823       }
4824       if (ctx->stage == fragment_fs)
4825          smem_op = aco_opcode::p_fs_buffer_store_smem;
4826
4827       if (smem) {
4828          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
4829          store->operands[0] = Operand(rsrc);
4830          if (start) {
4831             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4832                                 offset, Operand(start * elem_size_bytes));
4833             store->operands[1] = Operand(off);
4834          } else {
4835             store->operands[1] = Operand(offset);
4836          }
4837          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
4838             store->operands[1].setFixed(m0);
4839          store->operands[2] = Operand(write_data);
4840          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4841          store->dlc = false;
4842          store->disable_wqm = true;
4843          store->barrier = barrier_buffer;
4844          ctx->block->instructions.emplace_back(std::move(store));
4845          ctx->program->wb_smem_l1_on_end = true;
4846          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
4847             ctx->block->kind |= block_kind_needs_lowering;
4848             ctx->program->needs_exact = true;
4849          }
4850       } else {
4851          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
4852          store->operands[0] = Operand(rsrc);
4853          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4854          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4855          store->operands[3] = Operand(write_data);
4856          store->offset = start * elem_size_bytes;
4857          store->offen = (offset.type() == RegType::vgpr);
4858          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
4859          store->dlc = false;
4860          store->disable_wqm = true;
4861          store->barrier = barrier_buffer;
4862          ctx->program->needs_exact = true;
4863          ctx->block->instructions.emplace_back(std::move(store));
4864       }
4865    }
4866 }
4867
4868 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
4869 {
4870    /* return the previous value if dest is ever used */
4871    bool return_previous = false;
4872    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
4873       return_previous = true;
4874       break;
4875    }
4876    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
4877       return_previous = true;
4878       break;
4879    }
4880
4881    Builder bld(ctx->program, ctx->block);
4882    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
4883
4884    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
4885       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
4886                         get_ssa_temp(ctx, instr->src[3].ssa), data);
4887
4888    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
4889    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4890    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4891
4892    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4893
4894    aco_opcode op32, op64;
4895    switch (instr->intrinsic) {
4896       case nir_intrinsic_ssbo_atomic_add:
4897          op32 = aco_opcode::buffer_atomic_add;
4898          op64 = aco_opcode::buffer_atomic_add_x2;
4899          break;
4900       case nir_intrinsic_ssbo_atomic_imin:
4901          op32 = aco_opcode::buffer_atomic_smin;
4902          op64 = aco_opcode::buffer_atomic_smin_x2;
4903          break;
4904       case nir_intrinsic_ssbo_atomic_umin:
4905          op32 = aco_opcode::buffer_atomic_umin;
4906          op64 = aco_opcode::buffer_atomic_umin_x2;
4907          break;
4908       case nir_intrinsic_ssbo_atomic_imax:
4909          op32 = aco_opcode::buffer_atomic_smax;
4910          op64 = aco_opcode::buffer_atomic_smax_x2;
4911          break;
4912       case nir_intrinsic_ssbo_atomic_umax:
4913          op32 = aco_opcode::buffer_atomic_umax;
4914          op64 = aco_opcode::buffer_atomic_umax_x2;
4915          break;
4916       case nir_intrinsic_ssbo_atomic_and:
4917          op32 = aco_opcode::buffer_atomic_and;
4918          op64 = aco_opcode::buffer_atomic_and_x2;
4919          break;
4920       case nir_intrinsic_ssbo_atomic_or:
4921          op32 = aco_opcode::buffer_atomic_or;
4922          op64 = aco_opcode::buffer_atomic_or_x2;
4923          break;
4924       case nir_intrinsic_ssbo_atomic_xor:
4925          op32 = aco_opcode::buffer_atomic_xor;
4926          op64 = aco_opcode::buffer_atomic_xor_x2;
4927          break;
4928       case nir_intrinsic_ssbo_atomic_exchange:
4929          op32 = aco_opcode::buffer_atomic_swap;
4930          op64 = aco_opcode::buffer_atomic_swap_x2;
4931          break;
4932       case nir_intrinsic_ssbo_atomic_comp_swap:
4933          op32 = aco_opcode::buffer_atomic_cmpswap;
4934          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
4935          break;
4936       default:
4937          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4938    }
4939    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
4940    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
4941    mubuf->operands[0] = Operand(rsrc);
4942    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4943    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4944    mubuf->operands[3] = Operand(data);
4945    if (return_previous)
4946       mubuf->definitions[0] = Definition(dst);
4947    mubuf->offset = 0;
4948    mubuf->offen = (offset.type() == RegType::vgpr);
4949    mubuf->glc = return_previous;
4950    mubuf->dlc = false; /* Not needed for atomics */
4951    mubuf->disable_wqm = true;
4952    mubuf->barrier = barrier_buffer;
4953    ctx->program->needs_exact = true;
4954    ctx->block->instructions.emplace_back(std::move(mubuf));
4955 }
4956
4957 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
4958
4959    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
4960    Builder bld(ctx->program, ctx->block);
4961    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
4962    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
4963 }
4964
4965 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
4966 {
4967    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4968                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4969
4970    if (addr.type() == RegType::vgpr)
4971       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
4972    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
4973 }
4974
4975 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
4976 {
4977    Builder bld(ctx->program, ctx->block);
4978    unsigned num_components = instr->num_components;
4979    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
4980
4981    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4982    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
4983
4984    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
4985    bool dlc = glc && ctx->options->chip_class >= GFX10;
4986    aco_opcode op;
4987    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
4988       bool global = ctx->options->chip_class >= GFX9;
4989
4990       if (ctx->options->chip_class >= GFX7) {
4991          aco_opcode op;
4992          switch (num_bytes) {
4993          case 4:
4994             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
4995             break;
4996          case 8:
4997             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
4998             break;
4999          case 12:
5000             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5001             break;
5002          case 16:
5003             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5004             break;
5005          default:
5006             unreachable("load_global not implemented for this size.");
5007          }
5008
5009          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5010          flat->operands[0] = Operand(addr);
5011          flat->operands[1] = Operand(s1);
5012          flat->glc = glc;
5013          flat->dlc = dlc;
5014          flat->barrier = barrier_buffer;
5015
5016          if (dst.type() == RegType::sgpr) {
5017             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5018             flat->definitions[0] = Definition(vec);
5019             ctx->block->instructions.emplace_back(std::move(flat));
5020             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5021          } else {
5022             flat->definitions[0] = Definition(dst);
5023             ctx->block->instructions.emplace_back(std::move(flat));
5024          }
5025          emit_split_vector(ctx, dst, num_components);
5026       } else {
5027          assert(ctx->options->chip_class == GFX6);
5028
5029          /* GFX6 doesn't support loading vec3, expand to vec4. */
5030          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5031
5032          aco_opcode op;
5033          switch (num_bytes) {
5034          case 4:
5035             op = aco_opcode::buffer_load_dword;
5036             break;
5037          case 8:
5038             op = aco_opcode::buffer_load_dwordx2;
5039             break;
5040          case 16:
5041             op = aco_opcode::buffer_load_dwordx4;
5042             break;
5043          default:
5044             unreachable("load_global not implemented for this size.");
5045          }
5046
5047          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5048
5049          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5050          mubuf->operands[0] = Operand(rsrc);
5051          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5052          mubuf->operands[2] = Operand(0u);
5053          mubuf->glc = glc;
5054          mubuf->dlc = false;
5055          mubuf->offset = 0;
5056          mubuf->addr64 = addr.type() == RegType::vgpr;
5057          mubuf->disable_wqm = false;
5058          mubuf->barrier = barrier_buffer;
5059          aco_ptr<Instruction> instr = std::move(mubuf);
5060
5061          /* expand vector */
5062          if (dst.size() == 3) {
5063             Temp vec = bld.tmp(v4);
5064             instr->definitions[0] = Definition(vec);
5065             bld.insert(std::move(instr));
5066             emit_split_vector(ctx, vec, 4);
5067
5068             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5069             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5070             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5071             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5072          }
5073
5074          if (dst.type() == RegType::sgpr) {
5075             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5076             instr->definitions[0] = Definition(vec);
5077             bld.insert(std::move(instr));
5078             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5079             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5080          } else {
5081             instr->definitions[0] = Definition(dst);
5082             bld.insert(std::move(instr));
5083             emit_split_vector(ctx, dst, num_components);
5084          }
5085       }
5086    } else {
5087       switch (num_bytes) {
5088          case 4:
5089             op = aco_opcode::s_load_dword;
5090             break;
5091          case 8:
5092             op = aco_opcode::s_load_dwordx2;
5093             break;
5094          case 12:
5095          case 16:
5096             op = aco_opcode::s_load_dwordx4;
5097             break;
5098          default:
5099             unreachable("load_global not implemented for this size.");
5100       }
5101       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5102       load->operands[0] = Operand(addr);
5103       load->operands[1] = Operand(0u);
5104       load->definitions[0] = Definition(dst);
5105       load->glc = glc;
5106       load->dlc = dlc;
5107       load->barrier = barrier_buffer;
5108       assert(ctx->options->chip_class >= GFX8 || !glc);
5109
5110       if (dst.size() == 3) {
5111          /* trim vector */
5112          Temp vec = bld.tmp(s4);
5113          load->definitions[0] = Definition(vec);
5114          ctx->block->instructions.emplace_back(std::move(load));
5115          emit_split_vector(ctx, vec, 4);
5116
5117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5118                     emit_extract_vector(ctx, vec, 0, s1),
5119                     emit_extract_vector(ctx, vec, 1, s1),
5120                     emit_extract_vector(ctx, vec, 2, s1));
5121       } else {
5122          ctx->block->instructions.emplace_back(std::move(load));
5123       }
5124    }
5125 }
5126
5127 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5128 {
5129    Builder bld(ctx->program, ctx->block);
5130    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5131
5132    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5133    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5134
5135    if (ctx->options->chip_class >= GFX7)
5136       addr = as_vgpr(ctx, addr);
5137
5138    unsigned writemask = nir_intrinsic_write_mask(instr);
5139    while (writemask) {
5140       int start, count;
5141       u_bit_scan_consecutive_range(&writemask, &start, &count);
5142       if (count == 3 && ctx->options->chip_class == GFX6) {
5143          /* GFX6 doesn't support storing vec3, split it. */
5144          writemask |= 1u << (start + 2);
5145          count = 2;
5146       }
5147       unsigned num_bytes = count * elem_size_bytes;
5148
5149       Temp write_data = data;
5150       if (count != instr->num_components) {
5151          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5152          for (int i = 0; i < count; i++)
5153             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5154          write_data = bld.tmp(RegType::vgpr, count);
5155          vec->definitions[0] = Definition(write_data);
5156          ctx->block->instructions.emplace_back(std::move(vec));
5157       }
5158
5159       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5160       unsigned offset = start * elem_size_bytes;
5161
5162       if (ctx->options->chip_class >= GFX7) {
5163          if (offset > 0 && ctx->options->chip_class < GFX9) {
5164             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5165             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5166             Temp carry = bld.tmp(bld.lm);
5167             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5168
5169             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5170                      Operand(offset), addr0);
5171             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5172                      Operand(0u), addr1,
5173                      carry).def(1).setHint(vcc);
5174
5175             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5176
5177             offset = 0;
5178          }
5179
5180          bool global = ctx->options->chip_class >= GFX9;
5181          aco_opcode op;
5182          switch (num_bytes) {
5183          case 4:
5184             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5185             break;
5186          case 8:
5187             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5188             break;
5189          case 12:
5190             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5191             break;
5192          case 16:
5193             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5194             break;
5195          default:
5196             unreachable("store_global not implemented for this size.");
5197          }
5198
5199          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5200          flat->operands[0] = Operand(addr);
5201          flat->operands[1] = Operand(s1);
5202          flat->operands[2] = Operand(data);
5203          flat->glc = glc;
5204          flat->dlc = false;
5205          flat->offset = offset;
5206          flat->disable_wqm = true;
5207          flat->barrier = barrier_buffer;
5208          ctx->program->needs_exact = true;
5209          ctx->block->instructions.emplace_back(std::move(flat));
5210       } else {
5211          assert(ctx->options->chip_class == GFX6);
5212
5213          aco_opcode op;
5214          switch (num_bytes) {
5215          case 4:
5216             op = aco_opcode::buffer_store_dword;
5217             break;
5218          case 8:
5219             op = aco_opcode::buffer_store_dwordx2;
5220             break;
5221          case 16:
5222             op = aco_opcode::buffer_store_dwordx4;
5223             break;
5224          default:
5225             unreachable("store_global not implemented for this size.");
5226          }
5227
5228          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5229
5230          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5231          mubuf->operands[0] = Operand(rsrc);
5232          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5233          mubuf->operands[2] = Operand(0u);
5234          mubuf->operands[3] = Operand(write_data);
5235          mubuf->glc = glc;
5236          mubuf->dlc = false;
5237          mubuf->offset = offset;
5238          mubuf->addr64 = addr.type() == RegType::vgpr;
5239          mubuf->disable_wqm = true;
5240          mubuf->barrier = barrier_buffer;
5241          ctx->program->needs_exact = true;
5242          ctx->block->instructions.emplace_back(std::move(mubuf));
5243       }
5244    }
5245 }
5246
5247 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5248 {
5249    /* return the previous value if dest is ever used */
5250    bool return_previous = false;
5251    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5252       return_previous = true;
5253       break;
5254    }
5255    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5256       return_previous = true;
5257       break;
5258    }
5259
5260    Builder bld(ctx->program, ctx->block);
5261    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5262    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5263
5264    if (ctx->options->chip_class >= GFX7)
5265       addr = as_vgpr(ctx, addr);
5266
5267    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5268       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5269                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5270
5271    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5272
5273    aco_opcode op32, op64;
5274
5275    if (ctx->options->chip_class >= GFX7) {
5276       bool global = ctx->options->chip_class >= GFX9;
5277       switch (instr->intrinsic) {
5278          case nir_intrinsic_global_atomic_add:
5279             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5280             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5281             break;
5282          case nir_intrinsic_global_atomic_imin:
5283             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5284             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5285             break;
5286          case nir_intrinsic_global_atomic_umin:
5287             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5288             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5289             break;
5290          case nir_intrinsic_global_atomic_imax:
5291             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5292             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5293             break;
5294          case nir_intrinsic_global_atomic_umax:
5295             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5296             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5297             break;
5298          case nir_intrinsic_global_atomic_and:
5299             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5300             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5301             break;
5302          case nir_intrinsic_global_atomic_or:
5303             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5304             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5305             break;
5306          case nir_intrinsic_global_atomic_xor:
5307             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5308             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5309             break;
5310          case nir_intrinsic_global_atomic_exchange:
5311             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5312             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5313             break;
5314          case nir_intrinsic_global_atomic_comp_swap:
5315             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5316             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5317             break;
5318          default:
5319             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5320       }
5321
5322       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5323       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5324       flat->operands[0] = Operand(addr);
5325       flat->operands[1] = Operand(s1);
5326       flat->operands[2] = Operand(data);
5327       if (return_previous)
5328          flat->definitions[0] = Definition(dst);
5329       flat->glc = return_previous;
5330       flat->dlc = false; /* Not needed for atomics */
5331       flat->offset = 0;
5332       flat->disable_wqm = true;
5333       flat->barrier = barrier_buffer;
5334       ctx->program->needs_exact = true;
5335       ctx->block->instructions.emplace_back(std::move(flat));
5336    } else {
5337       assert(ctx->options->chip_class == GFX6);
5338
5339       switch (instr->intrinsic) {
5340          case nir_intrinsic_global_atomic_add:
5341             op32 = aco_opcode::buffer_atomic_add;
5342             op64 = aco_opcode::buffer_atomic_add_x2;
5343             break;
5344          case nir_intrinsic_global_atomic_imin:
5345             op32 = aco_opcode::buffer_atomic_smin;
5346             op64 = aco_opcode::buffer_atomic_smin_x2;
5347             break;
5348          case nir_intrinsic_global_atomic_umin:
5349             op32 = aco_opcode::buffer_atomic_umin;
5350             op64 = aco_opcode::buffer_atomic_umin_x2;
5351             break;
5352          case nir_intrinsic_global_atomic_imax:
5353             op32 = aco_opcode::buffer_atomic_smax;
5354             op64 = aco_opcode::buffer_atomic_smax_x2;
5355             break;
5356          case nir_intrinsic_global_atomic_umax:
5357             op32 = aco_opcode::buffer_atomic_umax;
5358             op64 = aco_opcode::buffer_atomic_umax_x2;
5359             break;
5360          case nir_intrinsic_global_atomic_and:
5361             op32 = aco_opcode::buffer_atomic_and;
5362             op64 = aco_opcode::buffer_atomic_and_x2;
5363             break;
5364          case nir_intrinsic_global_atomic_or:
5365             op32 = aco_opcode::buffer_atomic_or;
5366             op64 = aco_opcode::buffer_atomic_or_x2;
5367             break;
5368          case nir_intrinsic_global_atomic_xor:
5369             op32 = aco_opcode::buffer_atomic_xor;
5370             op64 = aco_opcode::buffer_atomic_xor_x2;
5371             break;
5372          case nir_intrinsic_global_atomic_exchange:
5373             op32 = aco_opcode::buffer_atomic_swap;
5374             op64 = aco_opcode::buffer_atomic_swap_x2;
5375             break;
5376          case nir_intrinsic_global_atomic_comp_swap:
5377             op32 = aco_opcode::buffer_atomic_cmpswap;
5378             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5379             break;
5380          default:
5381             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5382       }
5383
5384       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5385
5386       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5387
5388       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5389       mubuf->operands[0] = Operand(rsrc);
5390       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5391       mubuf->operands[2] = Operand(0u);
5392       mubuf->operands[3] = Operand(data);
5393       if (return_previous)
5394          mubuf->definitions[0] = Definition(dst);
5395       mubuf->glc = return_previous;
5396       mubuf->dlc = false;
5397       mubuf->offset = 0;
5398       mubuf->addr64 = addr.type() == RegType::vgpr;
5399       mubuf->disable_wqm = true;
5400       mubuf->barrier = barrier_buffer;
5401       ctx->program->needs_exact = true;
5402       ctx->block->instructions.emplace_back(std::move(mubuf));
5403    }
5404 }
5405
5406 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5407    Builder bld(ctx->program, ctx->block);
5408    switch(instr->intrinsic) {
5409       case nir_intrinsic_group_memory_barrier:
5410       case nir_intrinsic_memory_barrier:
5411          bld.barrier(aco_opcode::p_memory_barrier_common);
5412          break;
5413       case nir_intrinsic_memory_barrier_buffer:
5414          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5415          break;
5416       case nir_intrinsic_memory_barrier_image:
5417          bld.barrier(aco_opcode::p_memory_barrier_image);
5418          break;
5419       case nir_intrinsic_memory_barrier_tcs_patch:
5420       case nir_intrinsic_memory_barrier_shared:
5421          bld.barrier(aco_opcode::p_memory_barrier_shared);
5422          break;
5423       default:
5424          unreachable("Unimplemented memory barrier intrinsic");
5425          break;
5426    }
5427 }
5428
5429 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5430 {
5431    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5432    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5433    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5434    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5435    Builder bld(ctx->program, ctx->block);
5436
5437    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5438    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5439    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5440 }
5441
5442 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5443 {
5444    unsigned writemask = nir_intrinsic_write_mask(instr);
5445    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5446    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5447    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5448    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5449
5450    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5451    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5452 }
5453
5454 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5455 {
5456    unsigned offset = nir_intrinsic_base(instr);
5457    Operand m = load_lds_size_m0(ctx);
5458    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5459    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5460
5461    unsigned num_operands = 3;
5462    aco_opcode op32, op64, op32_rtn, op64_rtn;
5463    switch(instr->intrinsic) {
5464       case nir_intrinsic_shared_atomic_add:
5465          op32 = aco_opcode::ds_add_u32;
5466          op64 = aco_opcode::ds_add_u64;
5467          op32_rtn = aco_opcode::ds_add_rtn_u32;
5468          op64_rtn = aco_opcode::ds_add_rtn_u64;
5469          break;
5470       case nir_intrinsic_shared_atomic_imin:
5471          op32 = aco_opcode::ds_min_i32;
5472          op64 = aco_opcode::ds_min_i64;
5473          op32_rtn = aco_opcode::ds_min_rtn_i32;
5474          op64_rtn = aco_opcode::ds_min_rtn_i64;
5475          break;
5476       case nir_intrinsic_shared_atomic_umin:
5477          op32 = aco_opcode::ds_min_u32;
5478          op64 = aco_opcode::ds_min_u64;
5479          op32_rtn = aco_opcode::ds_min_rtn_u32;
5480          op64_rtn = aco_opcode::ds_min_rtn_u64;
5481          break;
5482       case nir_intrinsic_shared_atomic_imax:
5483          op32 = aco_opcode::ds_max_i32;
5484          op64 = aco_opcode::ds_max_i64;
5485          op32_rtn = aco_opcode::ds_max_rtn_i32;
5486          op64_rtn = aco_opcode::ds_max_rtn_i64;
5487          break;
5488       case nir_intrinsic_shared_atomic_umax:
5489          op32 = aco_opcode::ds_max_u32;
5490          op64 = aco_opcode::ds_max_u64;
5491          op32_rtn = aco_opcode::ds_max_rtn_u32;
5492          op64_rtn = aco_opcode::ds_max_rtn_u64;
5493          break;
5494       case nir_intrinsic_shared_atomic_and:
5495          op32 = aco_opcode::ds_and_b32;
5496          op64 = aco_opcode::ds_and_b64;
5497          op32_rtn = aco_opcode::ds_and_rtn_b32;
5498          op64_rtn = aco_opcode::ds_and_rtn_b64;
5499          break;
5500       case nir_intrinsic_shared_atomic_or:
5501          op32 = aco_opcode::ds_or_b32;
5502          op64 = aco_opcode::ds_or_b64;
5503          op32_rtn = aco_opcode::ds_or_rtn_b32;
5504          op64_rtn = aco_opcode::ds_or_rtn_b64;
5505          break;
5506       case nir_intrinsic_shared_atomic_xor:
5507          op32 = aco_opcode::ds_xor_b32;
5508          op64 = aco_opcode::ds_xor_b64;
5509          op32_rtn = aco_opcode::ds_xor_rtn_b32;
5510          op64_rtn = aco_opcode::ds_xor_rtn_b64;
5511          break;
5512       case nir_intrinsic_shared_atomic_exchange:
5513          op32 = aco_opcode::ds_write_b32;
5514          op64 = aco_opcode::ds_write_b64;
5515          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
5516          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
5517          break;
5518       case nir_intrinsic_shared_atomic_comp_swap:
5519          op32 = aco_opcode::ds_cmpst_b32;
5520          op64 = aco_opcode::ds_cmpst_b64;
5521          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
5522          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
5523          num_operands = 4;
5524          break;
5525       default:
5526          unreachable("Unhandled shared atomic intrinsic");
5527    }
5528
5529    /* return the previous value if dest is ever used */
5530    bool return_previous = false;
5531    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5532       return_previous = true;
5533       break;
5534    }
5535    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5536       return_previous = true;
5537       break;
5538    }
5539
5540    aco_opcode op;
5541    if (data.size() == 1) {
5542       assert(instr->dest.ssa.bit_size == 32);
5543       op = return_previous ? op32_rtn : op32;
5544    } else {
5545       assert(instr->dest.ssa.bit_size == 64);
5546       op = return_previous ? op64_rtn : op64;
5547    }
5548
5549    if (offset > 65535) {
5550       Builder bld(ctx->program, ctx->block);
5551       address = bld.vadd32(bld.def(v1), Operand(offset), address);
5552       offset = 0;
5553    }
5554
5555    aco_ptr<DS_instruction> ds;
5556    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
5557    ds->operands[0] = Operand(address);
5558    ds->operands[1] = Operand(data);
5559    if (num_operands == 4)
5560       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
5561    ds->operands[num_operands - 1] = m;
5562    ds->offset0 = offset;
5563    if (return_previous)
5564       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
5565    ctx->block->instructions.emplace_back(std::move(ds));
5566 }
5567
5568 Temp get_scratch_resource(isel_context *ctx)
5569 {
5570    Builder bld(ctx->program, ctx->block);
5571    Temp scratch_addr = ctx->program->private_segment_buffer;
5572    if (ctx->stage != compute_cs)
5573       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
5574
5575    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
5576                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
5577
5578    if (ctx->program->chip_class >= GFX10) {
5579       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5580                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
5581                    S_008F0C_RESOURCE_LEVEL(1);
5582    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5583       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5584                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5585    }
5586
5587    /* older generations need element size = 16 bytes. element size removed in GFX9 */
5588    if (ctx->program->chip_class <= GFX8)
5589       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
5590
5591    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
5592 }
5593
5594 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5595    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
5596    Builder bld(ctx->program, ctx->block);
5597    Temp rsrc = get_scratch_resource(ctx);
5598    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5599    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5600
5601    aco_opcode op;
5602    switch (dst.size()) {
5603       case 1:
5604          op = aco_opcode::buffer_load_dword;
5605          break;
5606       case 2:
5607          op = aco_opcode::buffer_load_dwordx2;
5608          break;
5609       case 3:
5610          op = aco_opcode::buffer_load_dwordx3;
5611          break;
5612       case 4:
5613          op = aco_opcode::buffer_load_dwordx4;
5614          break;
5615       case 6:
5616       case 8: {
5617          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
5618          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
5619                                 bld.def(v4), rsrc, offset,
5620                                 ctx->program->scratch_offset, 0, true);
5621          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
5622                                                   aco_opcode::buffer_load_dwordx4,
5623                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
5624                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
5625          emit_split_vector(ctx, lower, 2);
5626          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
5627          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
5628          if (dst.size() == 8) {
5629             emit_split_vector(ctx, upper, 2);
5630             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
5631             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
5632          } else {
5633             elems[2] = upper;
5634          }
5635
5636          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
5637                                                                          Format::PSEUDO, dst.size() / 2, 1)};
5638          for (unsigned i = 0; i < dst.size() / 2; i++)
5639             vec->operands[i] = Operand(elems[i]);
5640          vec->definitions[0] = Definition(dst);
5641          bld.insert(std::move(vec));
5642          ctx->allocated_vec.emplace(dst.id(), elems);
5643          return;
5644       }
5645       default:
5646          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5647    }
5648
5649    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
5650    emit_split_vector(ctx, dst, instr->num_components);
5651 }
5652
5653 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
5654    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
5655    Builder bld(ctx->program, ctx->block);
5656    Temp rsrc = get_scratch_resource(ctx);
5657    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5658    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5659
5660    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5661    unsigned writemask = nir_intrinsic_write_mask(instr);
5662
5663    while (writemask) {
5664       int start, count;
5665       u_bit_scan_consecutive_range(&writemask, &start, &count);
5666       int num_bytes = count * elem_size_bytes;
5667
5668       if (num_bytes > 16) {
5669          assert(elem_size_bytes == 8);
5670          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5671          count = 2;
5672          num_bytes = 16;
5673       }
5674
5675       // TODO: check alignment of sub-dword stores
5676       // TODO: split 3 bytes. there is no store instruction for that
5677
5678       Temp write_data;
5679       if (count != instr->num_components) {
5680          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5681          for (int i = 0; i < count; i++) {
5682             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
5683             vec->operands[i] = Operand(elem);
5684          }
5685          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
5686          vec->definitions[0] = Definition(write_data);
5687          ctx->block->instructions.emplace_back(std::move(vec));
5688       } else {
5689          write_data = data;
5690       }
5691
5692       aco_opcode op;
5693       switch (num_bytes) {
5694          case 4:
5695             op = aco_opcode::buffer_store_dword;
5696             break;
5697          case 8:
5698             op = aco_opcode::buffer_store_dwordx2;
5699             break;
5700          case 12:
5701             op = aco_opcode::buffer_store_dwordx3;
5702             break;
5703          case 16:
5704             op = aco_opcode::buffer_store_dwordx4;
5705             break;
5706          default:
5707             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5708       }
5709
5710       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
5711    }
5712 }
5713
5714 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
5715    uint8_t log2_ps_iter_samples;
5716    if (ctx->program->info->ps.force_persample) {
5717       log2_ps_iter_samples =
5718          util_logbase2(ctx->options->key.fs.num_samples);
5719    } else {
5720       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
5721    }
5722
5723    /* The bit pattern matches that used by fixed function fragment
5724     * processing. */
5725    static const unsigned ps_iter_masks[] = {
5726       0xffff, /* not used */
5727       0x5555,
5728       0x1111,
5729       0x0101,
5730       0x0001,
5731    };
5732    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
5733
5734    Builder bld(ctx->program, ctx->block);
5735
5736    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
5737                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
5738    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
5739    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
5740    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5741    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
5742 }
5743
5744 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
5745    Builder bld(ctx->program, ctx->block);
5746
5747    unsigned stream = nir_intrinsic_stream_id(instr);
5748    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5749    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
5750    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
5751
5752    /* get GSVS ring */
5753    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
5754
5755    unsigned num_components =
5756       ctx->program->info->gs.num_stream_output_components[stream];
5757    assert(num_components);
5758
5759    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
5760    unsigned stream_offset = 0;
5761    for (unsigned i = 0; i < stream; i++) {
5762       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
5763       stream_offset += prev_stride * ctx->program->wave_size;
5764    }
5765
5766    /* Limit on the stride field for <= GFX7. */
5767    assert(stride < (1 << 14));
5768
5769    Temp gsvs_dwords[4];
5770    for (unsigned i = 0; i < 4; i++)
5771       gsvs_dwords[i] = bld.tmp(s1);
5772    bld.pseudo(aco_opcode::p_split_vector,
5773               Definition(gsvs_dwords[0]),
5774               Definition(gsvs_dwords[1]),
5775               Definition(gsvs_dwords[2]),
5776               Definition(gsvs_dwords[3]),
5777               gsvs_ring);
5778
5779    if (stream_offset) {
5780       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
5781
5782       Temp carry = bld.tmp(s1);
5783       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
5784       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
5785    }
5786
5787    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
5788    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
5789
5790    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
5791                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
5792
5793    unsigned offset = 0;
5794    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
5795       if (ctx->program->info->gs.output_streams[i] != stream)
5796          continue;
5797
5798       for (unsigned j = 0; j < 4; j++) {
5799          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
5800             continue;
5801
5802          if (ctx->outputs.mask[i] & (1 << j)) {
5803             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
5804             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
5805             if (const_offset >= 4096u) {
5806                if (vaddr_offset.isUndefined())
5807                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
5808                else
5809                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
5810                const_offset %= 4096u;
5811             }
5812
5813             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
5814             mtbuf->operands[0] = Operand(gsvs_ring);
5815             mtbuf->operands[1] = vaddr_offset;
5816             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
5817             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
5818             mtbuf->offen = !vaddr_offset.isUndefined();
5819             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
5820             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
5821             mtbuf->offset = const_offset;
5822             mtbuf->glc = true;
5823             mtbuf->slc = true;
5824             mtbuf->barrier = barrier_gs_data;
5825             mtbuf->can_reorder = true;
5826             bld.insert(std::move(mtbuf));
5827          }
5828
5829          offset += ctx->shader->info.gs.vertices_out;
5830       }
5831
5832       /* outputs for the next vertex are undefined and keeping them around can
5833        * create invalid IR with control flow */
5834       ctx->outputs.mask[i] = 0;
5835    }
5836
5837    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
5838 }
5839
5840 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
5841 {
5842    Builder bld(ctx->program, ctx->block);
5843
5844    if (cluster_size == 1) {
5845       return src;
5846    } if (op == nir_op_iand && cluster_size == 4) {
5847       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5848       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5849       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
5850                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
5851    } else if (op == nir_op_ior && cluster_size == 4) {
5852       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5853       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
5854                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
5855    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
5856       //subgroupAnd(val) -> (exec & ~val) == 0
5857       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
5858       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
5859       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
5860    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
5861       //subgroupOr(val) -> (val & exec) != 0
5862       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
5863       return bool_to_vector_condition(ctx, tmp);
5864    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
5865       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5866       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5867       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
5868       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
5869       return bool_to_vector_condition(ctx, tmp);
5870    } else {
5871       //subgroupClustered{And,Or,Xor}(val, n) ->
5872       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
5873       //cluster_offset = ~(n - 1) & lane_id
5874       //cluster_mask = ((1 << n) - 1)
5875       //subgroupClusteredAnd():
5876       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5877       //subgroupClusteredOr():
5878       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
5879       //subgroupClusteredXor():
5880       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5881       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
5882       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
5883
5884       Temp tmp;
5885       if (op == nir_op_iand)
5886          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5887       else
5888          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
5889
5890       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
5891
5892       if (ctx->program->chip_class <= GFX7)
5893          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
5894       else if (ctx->program->wave_size == 64)
5895          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
5896       else
5897          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
5898       tmp = emit_extract_vector(ctx, tmp, 0, v1);
5899       if (cluster_mask != 0xffffffff)
5900          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
5901
5902       Definition cmp_def = Definition();
5903       if (op == nir_op_iand) {
5904          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
5905       } else if (op == nir_op_ior) {
5906          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5907       } else if (op == nir_op_ixor) {
5908          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
5909                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
5910          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
5911       }
5912       cmp_def.setHint(vcc);
5913       return cmp_def.getTemp();
5914    }
5915 }
5916
5917 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
5918 {
5919    Builder bld(ctx->program, ctx->block);
5920
5921    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5922    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5923    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5924    Temp tmp;
5925    if (op == nir_op_iand)
5926       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
5927    else
5928       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
5929
5930    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
5931    Temp lo = lohi.def(0).getTemp();
5932    Temp hi = lohi.def(1).getTemp();
5933    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
5934
5935    Definition cmp_def = Definition();
5936    if (op == nir_op_iand)
5937       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5938    else if (op == nir_op_ior)
5939       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
5940    else if (op == nir_op_ixor)
5941       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
5942                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
5943    cmp_def.setHint(vcc);
5944    return cmp_def.getTemp();
5945 }
5946
5947 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
5948 {
5949    Builder bld(ctx->program, ctx->block);
5950
5951    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5952    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5953    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5954    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
5955    if (op == nir_op_iand)
5956       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5957    else if (op == nir_op_ior)
5958       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5959    else if (op == nir_op_ixor)
5960       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
5961
5962    assert(false);
5963    return Temp();
5964 }
5965
5966 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
5967 {
5968    Builder bld(ctx->program, ctx->block);
5969    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
5970    if (src.regClass().type() == RegType::vgpr) {
5971       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
5972    } else if (src.regClass() == s1) {
5973       bld.sop1(aco_opcode::s_mov_b32, dst, src);
5974    } else if (src.regClass() == s2) {
5975       bld.sop1(aco_opcode::s_mov_b64, dst, src);
5976    } else {
5977       fprintf(stderr, "Unimplemented NIR instr bit size: ");
5978       nir_print_instr(&instr->instr, stderr);
5979       fprintf(stderr, "\n");
5980    }
5981 }
5982
5983 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
5984 {
5985    Builder bld(ctx->program, ctx->block);
5986    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
5987    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
5988    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
5989
5990    Temp ddx_1, ddx_2, ddy_1, ddy_2;
5991    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
5992    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
5993    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
5994
5995    /* Build DD X/Y */
5996    if (ctx->program->chip_class >= GFX8) {
5997       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
5998       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
5999       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6000       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6001       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6002       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6003    } else {
6004       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6005       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6006       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6007       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6008       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6009       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6010       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6011       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6012       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6013       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6014    }
6015
6016    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6017    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6018    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6019    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6020    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6021    Temp wqm1 = bld.tmp(v1);
6022    emit_wqm(ctx, tmp1, wqm1, true);
6023    Temp wqm2 = bld.tmp(v1);
6024    emit_wqm(ctx, tmp2, wqm2, true);
6025    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6026    return;
6027 }
6028
6029 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6030 {
6031    Builder bld(ctx->program, ctx->block);
6032    switch(instr->intrinsic) {
6033    case nir_intrinsic_load_barycentric_sample:
6034    case nir_intrinsic_load_barycentric_pixel:
6035    case nir_intrinsic_load_barycentric_centroid: {
6036       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6037       Temp bary = Temp(0, s2);
6038       switch (mode) {
6039       case INTERP_MODE_SMOOTH:
6040       case INTERP_MODE_NONE:
6041          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6042             bary = get_arg(ctx, ctx->args->ac.persp_center);
6043          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6044             bary = ctx->persp_centroid;
6045          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6046             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6047          break;
6048       case INTERP_MODE_NOPERSPECTIVE:
6049          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6050             bary = get_arg(ctx, ctx->args->ac.linear_center);
6051          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6052             bary = ctx->linear_centroid;
6053          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6054             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6055          break;
6056       default:
6057          break;
6058       }
6059       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6060       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6061       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6062       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6063                  Operand(p1), Operand(p2));
6064       emit_split_vector(ctx, dst, 2);
6065       break;
6066    }
6067    case nir_intrinsic_load_barycentric_model: {
6068       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6069
6070       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6071       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6072       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6073       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6074       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6075                  Operand(p1), Operand(p2), Operand(p3));
6076       emit_split_vector(ctx, dst, 3);
6077       break;
6078    }
6079    case nir_intrinsic_load_barycentric_at_sample: {
6080       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6081       switch (ctx->options->key.fs.num_samples) {
6082          case 2: sample_pos_offset += 1 << 3; break;
6083          case 4: sample_pos_offset += 3 << 3; break;
6084          case 8: sample_pos_offset += 7 << 3; break;
6085          default: break;
6086       }
6087       Temp sample_pos;
6088       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6089       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6090       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6091       if (addr.type() == RegType::sgpr) {
6092          Operand offset;
6093          if (const_addr) {
6094             sample_pos_offset += const_addr->u32 << 3;
6095             offset = Operand(sample_pos_offset);
6096          } else if (ctx->options->chip_class >= GFX9) {
6097             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6098          } else {
6099             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6100             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6101          }
6102
6103          Operand off = bld.copy(bld.def(s1), Operand(offset));
6104          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6105
6106       } else if (ctx->options->chip_class >= GFX9) {
6107          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6108          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6109       } else if (ctx->options->chip_class >= GFX7) {
6110          /* addr += private_segment_buffer + sample_pos_offset */
6111          Temp tmp0 = bld.tmp(s1);
6112          Temp tmp1 = bld.tmp(s1);
6113          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6114          Definition scc_tmp = bld.def(s1, scc);
6115          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6116          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6117          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6118          Temp pck0 = bld.tmp(v1);
6119          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6120          tmp1 = as_vgpr(ctx, tmp1);
6121          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6122          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6123
6124          /* sample_pos = flat_load_dwordx2 addr */
6125          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6126       } else {
6127          assert(ctx->options->chip_class == GFX6);
6128
6129          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6130                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6131          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6132
6133          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6134          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6135
6136          sample_pos = bld.tmp(v2);
6137
6138          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6139          load->definitions[0] = Definition(sample_pos);
6140          load->operands[0] = Operand(rsrc);
6141          load->operands[1] = Operand(addr);
6142          load->operands[2] = Operand(0u);
6143          load->offset = sample_pos_offset;
6144          load->offen = 0;
6145          load->addr64 = true;
6146          load->glc = false;
6147          load->dlc = false;
6148          load->disable_wqm = false;
6149          load->barrier = barrier_none;
6150          load->can_reorder = true;
6151          ctx->block->instructions.emplace_back(std::move(load));
6152       }
6153
6154       /* sample_pos -= 0.5 */
6155       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6156       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6157       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6158       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6159       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6160
6161       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6162       break;
6163    }
6164    case nir_intrinsic_load_barycentric_at_offset: {
6165       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6166       RegClass rc = RegClass(offset.type(), 1);
6167       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6168       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6169       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6170       break;
6171    }
6172    case nir_intrinsic_load_front_face: {
6173       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6174                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6175       break;
6176    }
6177    case nir_intrinsic_load_view_index: {
6178       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6179          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6180          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6181          break;
6182       }
6183
6184       /* fallthrough */
6185    }
6186    case nir_intrinsic_load_layer_id: {
6187       unsigned idx = nir_intrinsic_base(instr);
6188       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6189                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6190       break;
6191    }
6192    case nir_intrinsic_load_frag_coord: {
6193       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6194       break;
6195    }
6196    case nir_intrinsic_load_sample_pos: {
6197       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6198       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6199       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6200                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6201                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6202       break;
6203    }
6204    case nir_intrinsic_load_tess_coord:
6205       visit_load_tess_coord(ctx, instr);
6206       break;
6207    case nir_intrinsic_load_interpolated_input:
6208       visit_load_interpolated_input(ctx, instr);
6209       break;
6210    case nir_intrinsic_store_output:
6211       visit_store_output(ctx, instr);
6212       break;
6213    case nir_intrinsic_load_input:
6214    case nir_intrinsic_load_input_vertex:
6215       visit_load_input(ctx, instr);
6216       break;
6217    case nir_intrinsic_load_per_vertex_input:
6218       visit_load_per_vertex_input(ctx, instr);
6219       break;
6220    case nir_intrinsic_load_ubo:
6221       visit_load_ubo(ctx, instr);
6222       break;
6223    case nir_intrinsic_load_push_constant:
6224       visit_load_push_constant(ctx, instr);
6225       break;
6226    case nir_intrinsic_load_constant:
6227       visit_load_constant(ctx, instr);
6228       break;
6229    case nir_intrinsic_vulkan_resource_index:
6230       visit_load_resource(ctx, instr);
6231       break;
6232    case nir_intrinsic_discard:
6233       visit_discard(ctx, instr);
6234       break;
6235    case nir_intrinsic_discard_if:
6236       visit_discard_if(ctx, instr);
6237       break;
6238    case nir_intrinsic_load_shared:
6239       visit_load_shared(ctx, instr);
6240       break;
6241    case nir_intrinsic_store_shared:
6242       visit_store_shared(ctx, instr);
6243       break;
6244    case nir_intrinsic_shared_atomic_add:
6245    case nir_intrinsic_shared_atomic_imin:
6246    case nir_intrinsic_shared_atomic_umin:
6247    case nir_intrinsic_shared_atomic_imax:
6248    case nir_intrinsic_shared_atomic_umax:
6249    case nir_intrinsic_shared_atomic_and:
6250    case nir_intrinsic_shared_atomic_or:
6251    case nir_intrinsic_shared_atomic_xor:
6252    case nir_intrinsic_shared_atomic_exchange:
6253    case nir_intrinsic_shared_atomic_comp_swap:
6254       visit_shared_atomic(ctx, instr);
6255       break;
6256    case nir_intrinsic_image_deref_load:
6257       visit_image_load(ctx, instr);
6258       break;
6259    case nir_intrinsic_image_deref_store:
6260       visit_image_store(ctx, instr);
6261       break;
6262    case nir_intrinsic_image_deref_atomic_add:
6263    case nir_intrinsic_image_deref_atomic_umin:
6264    case nir_intrinsic_image_deref_atomic_imin:
6265    case nir_intrinsic_image_deref_atomic_umax:
6266    case nir_intrinsic_image_deref_atomic_imax:
6267    case nir_intrinsic_image_deref_atomic_and:
6268    case nir_intrinsic_image_deref_atomic_or:
6269    case nir_intrinsic_image_deref_atomic_xor:
6270    case nir_intrinsic_image_deref_atomic_exchange:
6271    case nir_intrinsic_image_deref_atomic_comp_swap:
6272       visit_image_atomic(ctx, instr);
6273       break;
6274    case nir_intrinsic_image_deref_size:
6275       visit_image_size(ctx, instr);
6276       break;
6277    case nir_intrinsic_load_ssbo:
6278       visit_load_ssbo(ctx, instr);
6279       break;
6280    case nir_intrinsic_store_ssbo:
6281       visit_store_ssbo(ctx, instr);
6282       break;
6283    case nir_intrinsic_load_global:
6284       visit_load_global(ctx, instr);
6285       break;
6286    case nir_intrinsic_store_global:
6287       visit_store_global(ctx, instr);
6288       break;
6289    case nir_intrinsic_global_atomic_add:
6290    case nir_intrinsic_global_atomic_imin:
6291    case nir_intrinsic_global_atomic_umin:
6292    case nir_intrinsic_global_atomic_imax:
6293    case nir_intrinsic_global_atomic_umax:
6294    case nir_intrinsic_global_atomic_and:
6295    case nir_intrinsic_global_atomic_or:
6296    case nir_intrinsic_global_atomic_xor:
6297    case nir_intrinsic_global_atomic_exchange:
6298    case nir_intrinsic_global_atomic_comp_swap:
6299       visit_global_atomic(ctx, instr);
6300       break;
6301    case nir_intrinsic_ssbo_atomic_add:
6302    case nir_intrinsic_ssbo_atomic_imin:
6303    case nir_intrinsic_ssbo_atomic_umin:
6304    case nir_intrinsic_ssbo_atomic_imax:
6305    case nir_intrinsic_ssbo_atomic_umax:
6306    case nir_intrinsic_ssbo_atomic_and:
6307    case nir_intrinsic_ssbo_atomic_or:
6308    case nir_intrinsic_ssbo_atomic_xor:
6309    case nir_intrinsic_ssbo_atomic_exchange:
6310    case nir_intrinsic_ssbo_atomic_comp_swap:
6311       visit_atomic_ssbo(ctx, instr);
6312       break;
6313    case nir_intrinsic_load_scratch:
6314       visit_load_scratch(ctx, instr);
6315       break;
6316    case nir_intrinsic_store_scratch:
6317       visit_store_scratch(ctx, instr);
6318       break;
6319    case nir_intrinsic_get_buffer_size:
6320       visit_get_buffer_size(ctx, instr);
6321       break;
6322    case nir_intrinsic_control_barrier: {
6323       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6324          /* GFX6 only (thanks to a hw bug workaround):
6325           * The real barrier instruction isn’t needed, because an entire patch
6326           * always fits into a single wave.
6327           */
6328          break;
6329       }
6330
6331       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6332          unsigned* bsize = ctx->program->info->cs.block_size;
6333          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6334          if (workgroup_size > ctx->program->wave_size)
6335             bld.sopp(aco_opcode::s_barrier);
6336       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6337          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6338           * where n is the number of vertices in the output patch.
6339           */
6340          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6341          if (workgroup_size > ctx->program->wave_size)
6342             bld.sopp(aco_opcode::s_barrier);
6343       } else {
6344          /* We don't know the workgroup size, so always emit the s_barrier. */
6345          bld.sopp(aco_opcode::s_barrier);
6346       }
6347
6348       break;
6349    }
6350    case nir_intrinsic_memory_barrier_tcs_patch:
6351    case nir_intrinsic_group_memory_barrier:
6352    case nir_intrinsic_memory_barrier:
6353    case nir_intrinsic_memory_barrier_buffer:
6354    case nir_intrinsic_memory_barrier_image:
6355    case nir_intrinsic_memory_barrier_shared:
6356       emit_memory_barrier(ctx, instr);
6357       break;
6358    case nir_intrinsic_load_num_work_groups: {
6359       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6360       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6361       emit_split_vector(ctx, dst, 3);
6362       break;
6363    }
6364    case nir_intrinsic_load_local_invocation_id: {
6365       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6366       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6367       emit_split_vector(ctx, dst, 3);
6368       break;
6369    }
6370    case nir_intrinsic_load_work_group_id: {
6371       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6372       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6373       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6374                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6375                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6376                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6377       emit_split_vector(ctx, dst, 3);
6378       break;
6379    }
6380    case nir_intrinsic_load_local_invocation_index: {
6381       Temp id = emit_mbcnt(ctx, bld.def(v1));
6382
6383       /* The tg_size bits [6:11] contain the subgroup id,
6384        * we need this multiplied by the wave size, and then OR the thread id to it.
6385        */
6386       if (ctx->program->wave_size == 64) {
6387          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6388          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6389                                 get_arg(ctx, ctx->args->ac.tg_size));
6390          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6391       } else {
6392          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6393          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6394                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6395          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6396       }
6397       break;
6398    }
6399    case nir_intrinsic_load_subgroup_id: {
6400       if (ctx->stage == compute_cs) {
6401          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6402                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6403       } else {
6404          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6405       }
6406       break;
6407    }
6408    case nir_intrinsic_load_subgroup_invocation: {
6409       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6410       break;
6411    }
6412    case nir_intrinsic_load_num_subgroups: {
6413       if (ctx->stage == compute_cs)
6414          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6415                   get_arg(ctx, ctx->args->ac.tg_size));
6416       else
6417          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6418       break;
6419    }
6420    case nir_intrinsic_ballot: {
6421       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6422       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6423       Definition tmp = bld.def(dst.regClass());
6424       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6425       if (instr->src[0].ssa->bit_size == 1) {
6426          assert(src.regClass() == bld.lm);
6427          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6428       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6429          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6430       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6431          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6432       } else {
6433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6434          nir_print_instr(&instr->instr, stderr);
6435          fprintf(stderr, "\n");
6436       }
6437       if (dst.size() != bld.lm.size()) {
6438          /* Wave32 with ballot size set to 64 */
6439          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6440       }
6441       emit_wqm(ctx, tmp.getTemp(), dst);
6442       break;
6443    }
6444    case nir_intrinsic_shuffle:
6445    case nir_intrinsic_read_invocation: {
6446       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6447       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6448          emit_uniform_subgroup(ctx, instr, src);
6449       } else {
6450          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6451          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6452             tid = bld.as_uniform(tid);
6453          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6454          if (src.regClass() == v1) {
6455             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6456          } else if (src.regClass() == v2) {
6457             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6458             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6459             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6460             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6461             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6462             emit_split_vector(ctx, dst, 2);
6463          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6464             assert(src.regClass() == bld.lm);
6465             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6466             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6467          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6468             assert(src.regClass() == bld.lm);
6469             Temp tmp;
6470             if (ctx->program->chip_class <= GFX7)
6471                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6472             else if (ctx->program->wave_size == 64)
6473                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6474             else
6475                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6476             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6477             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6478             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6479          } else {
6480             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6481             nir_print_instr(&instr->instr, stderr);
6482             fprintf(stderr, "\n");
6483          }
6484       }
6485       break;
6486    }
6487    case nir_intrinsic_load_sample_id: {
6488       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6489                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6490       break;
6491    }
6492    case nir_intrinsic_load_sample_mask_in: {
6493       visit_load_sample_mask_in(ctx, instr);
6494       break;
6495    }
6496    case nir_intrinsic_read_first_invocation: {
6497       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6498       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6499       if (src.regClass() == v1) {
6500          emit_wqm(ctx,
6501                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
6502                   dst);
6503       } else if (src.regClass() == v2) {
6504          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6505          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6506          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
6507          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
6508          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6509          emit_split_vector(ctx, dst, 2);
6510       } else if (instr->dest.ssa.bit_size == 1) {
6511          assert(src.regClass() == bld.lm);
6512          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
6513                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
6514          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6515       } else if (src.regClass() == s1) {
6516          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
6517       } else if (src.regClass() == s2) {
6518          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
6519       } else {
6520          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6521          nir_print_instr(&instr->instr, stderr);
6522          fprintf(stderr, "\n");
6523       }
6524       break;
6525    }
6526    case nir_intrinsic_vote_all: {
6527       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6528       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6529       assert(src.regClass() == bld.lm);
6530       assert(dst.regClass() == bld.lm);
6531
6532       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6533       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6534       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
6535       break;
6536    }
6537    case nir_intrinsic_vote_any: {
6538       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6539       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6540       assert(src.regClass() == bld.lm);
6541       assert(dst.regClass() == bld.lm);
6542
6543       Temp tmp = bool_to_scalar_condition(ctx, src);
6544       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6545       break;
6546    }
6547    case nir_intrinsic_reduce:
6548    case nir_intrinsic_inclusive_scan:
6549    case nir_intrinsic_exclusive_scan: {
6550       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6551       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6552       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
6553       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
6554          nir_intrinsic_cluster_size(instr) : 0;
6555       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
6556
6557       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
6558          emit_uniform_subgroup(ctx, instr, src);
6559       } else if (instr->dest.ssa.bit_size == 1) {
6560          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
6561             op = nir_op_iand;
6562          else if (op == nir_op_iadd)
6563             op = nir_op_ixor;
6564          else if (op == nir_op_umax || op == nir_op_imax)
6565             op = nir_op_ior;
6566          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
6567
6568          switch (instr->intrinsic) {
6569          case nir_intrinsic_reduce:
6570             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
6571             break;
6572          case nir_intrinsic_exclusive_scan:
6573             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
6574             break;
6575          case nir_intrinsic_inclusive_scan:
6576             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
6577             break;
6578          default:
6579             assert(false);
6580          }
6581       } else if (cluster_size == 1) {
6582          bld.copy(Definition(dst), src);
6583       } else {
6584          src = as_vgpr(ctx, src);
6585
6586          ReduceOp reduce_op;
6587          switch (op) {
6588          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
6589             CASE(iadd)
6590             CASE(imul)
6591             CASE(fadd)
6592             CASE(fmul)
6593             CASE(imin)
6594             CASE(umin)
6595             CASE(fmin)
6596             CASE(imax)
6597             CASE(umax)
6598             CASE(fmax)
6599             CASE(iand)
6600             CASE(ior)
6601             CASE(ixor)
6602             default:
6603                unreachable("unknown reduction op");
6604          #undef CASE
6605          }
6606
6607          aco_opcode aco_op;
6608          switch (instr->intrinsic) {
6609             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
6610             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
6611             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
6612             default:
6613                unreachable("unknown reduce intrinsic");
6614          }
6615
6616          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
6617          reduce->operands[0] = Operand(src);
6618          // filled in by aco_reduce_assign.cpp, used internally as part of the
6619          // reduce sequence
6620          assert(dst.size() == 1 || dst.size() == 2);
6621          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
6622          reduce->operands[2] = Operand(v1.as_linear());
6623
6624          Temp tmp_dst = bld.tmp(dst.regClass());
6625          reduce->definitions[0] = Definition(tmp_dst);
6626          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
6627          reduce->definitions[2] = Definition();
6628          reduce->definitions[3] = Definition(scc, s1);
6629          reduce->definitions[4] = Definition();
6630          reduce->reduce_op = reduce_op;
6631          reduce->cluster_size = cluster_size;
6632          ctx->block->instructions.emplace_back(std::move(reduce));
6633
6634          emit_wqm(ctx, tmp_dst, dst);
6635       }
6636       break;
6637    }
6638    case nir_intrinsic_quad_broadcast: {
6639       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6640       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6641          emit_uniform_subgroup(ctx, instr, src);
6642       } else {
6643          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6644          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
6645          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
6646
6647          if (instr->dest.ssa.bit_size == 1) {
6648             assert(src.regClass() == bld.lm);
6649             assert(dst.regClass() == bld.lm);
6650             uint32_t half_mask = 0x11111111u << lane;
6651             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
6652             Temp tmp = bld.tmp(bld.lm);
6653             bld.sop1(Builder::s_wqm, Definition(tmp),
6654                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
6655                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
6656             emit_wqm(ctx, tmp, dst);
6657          } else if (instr->dest.ssa.bit_size == 32) {
6658             if (ctx->program->chip_class >= GFX8)
6659                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
6660             else
6661                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
6662          } else if (instr->dest.ssa.bit_size == 64) {
6663             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6664             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6665             if (ctx->program->chip_class >= GFX8) {
6666                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6667                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6668             } else {
6669                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
6670                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
6671             }
6672             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6673             emit_split_vector(ctx, dst, 2);
6674          } else {
6675             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6676             nir_print_instr(&instr->instr, stderr);
6677             fprintf(stderr, "\n");
6678          }
6679       }
6680       break;
6681    }
6682    case nir_intrinsic_quad_swap_horizontal:
6683    case nir_intrinsic_quad_swap_vertical:
6684    case nir_intrinsic_quad_swap_diagonal:
6685    case nir_intrinsic_quad_swizzle_amd: {
6686       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6687       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6688          emit_uniform_subgroup(ctx, instr, src);
6689          break;
6690       }
6691       uint16_t dpp_ctrl = 0;
6692       switch (instr->intrinsic) {
6693       case nir_intrinsic_quad_swap_horizontal:
6694          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
6695          break;
6696       case nir_intrinsic_quad_swap_vertical:
6697          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
6698          break;
6699       case nir_intrinsic_quad_swap_diagonal:
6700          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
6701          break;
6702       case nir_intrinsic_quad_swizzle_amd:
6703          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
6704          break;
6705       default:
6706          break;
6707       }
6708       if (ctx->program->chip_class < GFX8)
6709          dpp_ctrl |= (1 << 15);
6710
6711       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6712       if (instr->dest.ssa.bit_size == 1) {
6713          assert(src.regClass() == bld.lm);
6714          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
6715          if (ctx->program->chip_class >= GFX8)
6716             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6717          else
6718             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6719          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
6720          emit_wqm(ctx, tmp, dst);
6721       } else if (instr->dest.ssa.bit_size == 32) {
6722          Temp tmp;
6723          if (ctx->program->chip_class >= GFX8)
6724             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
6725          else
6726             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
6727          emit_wqm(ctx, tmp, dst);
6728       } else if (instr->dest.ssa.bit_size == 64) {
6729          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6730          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6731          if (ctx->program->chip_class >= GFX8) {
6732             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
6733             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
6734          } else {
6735             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
6736             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
6737          }
6738          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6739          emit_split_vector(ctx, dst, 2);
6740       } else {
6741          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6742          nir_print_instr(&instr->instr, stderr);
6743          fprintf(stderr, "\n");
6744       }
6745       break;
6746    }
6747    case nir_intrinsic_masked_swizzle_amd: {
6748       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6749       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
6750          emit_uniform_subgroup(ctx, instr, src);
6751          break;
6752       }
6753       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6754       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
6755       if (dst.regClass() == v1) {
6756          emit_wqm(ctx,
6757                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
6758                   dst);
6759       } else if (dst.regClass() == v2) {
6760          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6761          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6762          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
6763          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
6764          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6765          emit_split_vector(ctx, dst, 2);
6766       } else {
6767          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6768          nir_print_instr(&instr->instr, stderr);
6769          fprintf(stderr, "\n");
6770       }
6771       break;
6772    }
6773    case nir_intrinsic_write_invocation_amd: {
6774       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6775       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
6776       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
6777       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6778       if (dst.regClass() == v1) {
6779          /* src2 is ignored for writelane. RA assigns the same reg for dst */
6780          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
6781       } else if (dst.regClass() == v2) {
6782          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
6783          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
6784          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
6785          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
6786          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
6787          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
6788          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6789          emit_split_vector(ctx, dst, 2);
6790       } else {
6791          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6792          nir_print_instr(&instr->instr, stderr);
6793          fprintf(stderr, "\n");
6794       }
6795       break;
6796    }
6797    case nir_intrinsic_mbcnt_amd: {
6798       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6799       RegClass rc = RegClass(src.type(), 1);
6800       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
6801       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
6802       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6803       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
6804       emit_wqm(ctx, wqm_tmp, dst);
6805       break;
6806    }
6807    case nir_intrinsic_load_helper_invocation: {
6808       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6809       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
6810       ctx->block->kind |= block_kind_needs_lowering;
6811       ctx->program->needs_exact = true;
6812       break;
6813    }
6814    case nir_intrinsic_is_helper_invocation: {
6815       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6816       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
6817       ctx->block->kind |= block_kind_needs_lowering;
6818       ctx->program->needs_exact = true;
6819       break;
6820    }
6821    case nir_intrinsic_demote:
6822       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
6823
6824       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6825          ctx->cf_info.exec_potentially_empty_discard = true;
6826       ctx->block->kind |= block_kind_uses_demote;
6827       ctx->program->needs_exact = true;
6828       break;
6829    case nir_intrinsic_demote_if: {
6830       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6831       assert(src.regClass() == bld.lm);
6832       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6833       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
6834
6835       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
6836          ctx->cf_info.exec_potentially_empty_discard = true;
6837       ctx->block->kind |= block_kind_uses_demote;
6838       ctx->program->needs_exact = true;
6839       break;
6840    }
6841    case nir_intrinsic_first_invocation: {
6842       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
6843                get_ssa_temp(ctx, &instr->dest.ssa));
6844       break;
6845    }
6846    case nir_intrinsic_shader_clock:
6847       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
6848       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
6849       break;
6850    case nir_intrinsic_load_vertex_id_zero_base: {
6851       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6852       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
6853       break;
6854    }
6855    case nir_intrinsic_load_first_vertex: {
6856       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6857       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
6858       break;
6859    }
6860    case nir_intrinsic_load_base_instance: {
6861       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6862       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
6863       break;
6864    }
6865    case nir_intrinsic_load_instance_id: {
6866       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6867       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
6868       break;
6869    }
6870    case nir_intrinsic_load_draw_id: {
6871       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6872       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
6873       break;
6874    }
6875    case nir_intrinsic_load_invocation_id: {
6876       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6877
6878       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
6879          if (ctx->options->chip_class >= GFX10)
6880             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
6881          else
6882             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
6883       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6884          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
6885                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
6886       } else {
6887          unreachable("Unsupported stage for load_invocation_id");
6888       }
6889
6890       break;
6891    }
6892    case nir_intrinsic_load_primitive_id: {
6893       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6894
6895       switch (ctx->shader->info.stage) {
6896       case MESA_SHADER_GEOMETRY:
6897          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
6898          break;
6899       case MESA_SHADER_TESS_CTRL:
6900          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
6901          break;
6902       case MESA_SHADER_TESS_EVAL:
6903          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
6904          break;
6905       default:
6906          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
6907       }
6908
6909       break;
6910    }
6911    case nir_intrinsic_load_patch_vertices_in: {
6912       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
6913              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
6914
6915       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6916       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
6917       break;
6918    }
6919    case nir_intrinsic_emit_vertex_with_counter: {
6920       visit_emit_vertex_with_counter(ctx, instr);
6921       break;
6922    }
6923    case nir_intrinsic_end_primitive_with_counter: {
6924       unsigned stream = nir_intrinsic_stream_id(instr);
6925       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
6926       break;
6927    }
6928    case nir_intrinsic_set_vertex_count: {
6929       /* unused, the HW keeps track of this for us */
6930       break;
6931    }
6932    default:
6933       fprintf(stderr, "Unimplemented intrinsic instr: ");
6934       nir_print_instr(&instr->instr, stderr);
6935       fprintf(stderr, "\n");
6936       abort();
6937
6938       break;
6939    }
6940 }
6941
6942
6943 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
6944                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
6945                     enum glsl_base_type *stype)
6946 {
6947    nir_deref_instr *texture_deref_instr = NULL;
6948    nir_deref_instr *sampler_deref_instr = NULL;
6949    int plane = -1;
6950
6951    for (unsigned i = 0; i < instr->num_srcs; i++) {
6952       switch (instr->src[i].src_type) {
6953       case nir_tex_src_texture_deref:
6954          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
6955          break;
6956       case nir_tex_src_sampler_deref:
6957          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
6958          break;
6959       case nir_tex_src_plane:
6960          plane = nir_src_as_int(instr->src[i].src);
6961          break;
6962       default:
6963          break;
6964       }
6965    }
6966
6967    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
6968
6969    if (!sampler_deref_instr)
6970       sampler_deref_instr = texture_deref_instr;
6971
6972    if (plane >= 0) {
6973       assert(instr->op != nir_texop_txf_ms &&
6974              instr->op != nir_texop_samples_identical);
6975       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
6976       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
6977    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
6978       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
6979    } else if (instr->op == nir_texop_fragment_mask_fetch) {
6980       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
6981    } else {
6982       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
6983    }
6984    if (samp_ptr) {
6985       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
6986
6987       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
6988          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
6989          Builder bld(ctx->program, ctx->block);
6990
6991          /* to avoid unnecessary moves, we split and recombine sampler and image */
6992          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
6993                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6994          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
6995          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
6996                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
6997                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
6998          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
6999                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7000
7001          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7002          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7003                                img[0], img[1], img[2], img[3],
7004                                img[4], img[5], img[6], img[7]);
7005          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7006                                 samp[0], samp[1], samp[2], samp[3]);
7007       }
7008    }
7009    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7010                      instr->op == nir_texop_samples_identical))
7011       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7012 }
7013
7014 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7015                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7016 {
7017    Builder bld(ctx->program, ctx->block);
7018
7019    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7020    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7021    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7022
7023    Operand neg_one(0xbf800000u);
7024    Operand one(0x3f800000u);
7025    Operand two(0x40000000u);
7026    Operand four(0x40800000u);
7027
7028    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7029    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7030    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7031
7032    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7033    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7034    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7035    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7036
7037    // select sc
7038    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7039    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7040                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7041                        one, is_ma_y);
7042    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7043
7044    // select tc
7045    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7046    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7047    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7048
7049    // select ma
7050    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7051                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7052                   deriv_z, is_ma_z);
7053    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7054    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7055 }
7056
7057 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7058 {
7059    Builder bld(ctx->program, ctx->block);
7060    Temp ma, tc, sc, id;
7061
7062    if (is_array) {
7063       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7064
7065       // see comment in ac_prepare_cube_coords()
7066       if (ctx->options->chip_class <= GFX8)
7067          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7068    }
7069
7070    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7071
7072    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7073    vop3a->operands[0] = Operand(ma);
7074    vop3a->abs[0] = true;
7075    Temp invma = bld.tmp(v1);
7076    vop3a->definitions[0] = Definition(invma);
7077    ctx->block->instructions.emplace_back(std::move(vop3a));
7078
7079    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7080    if (!is_deriv)
7081       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7082
7083    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7084    if (!is_deriv)
7085       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7086
7087    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7088
7089    if (is_deriv) {
7090       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7091       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7092
7093       for (unsigned i = 0; i < 2; i++) {
7094          // see comment in ac_prepare_cube_coords()
7095          Temp deriv_ma;
7096          Temp deriv_sc, deriv_tc;
7097          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7098                            &deriv_ma, &deriv_sc, &deriv_tc);
7099
7100          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7101
7102          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7103                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7104                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7105          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7106                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7107                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7108          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7109       }
7110
7111       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7112       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7113    }
7114
7115    if (is_array)
7116       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7117    coords.resize(3);
7118    coords[0] = sc;
7119    coords[1] = tc;
7120    coords[2] = id;
7121 }
7122
7123 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7124 {
7125    if (vec->parent_instr->type != nir_instr_type_alu)
7126       return;
7127    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7128    if (vec_instr->op != nir_op_vec(vec->num_components))
7129       return;
7130
7131    for (unsigned i = 0; i < vec->num_components; i++) {
7132       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7133               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7134    }
7135 }
7136
7137 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7138 {
7139    Builder bld(ctx->program, ctx->block);
7140    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7141         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7142    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7143         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7144    std::vector<Temp> coords;
7145    std::vector<Temp> derivs;
7146    nir_const_value *sample_index_cv = NULL;
7147    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7148    enum glsl_base_type stype;
7149    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7150
7151    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7152                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7153    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7154                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7155
7156    for (unsigned i = 0; i < instr->num_srcs; i++) {
7157       switch (instr->src[i].src_type) {
7158       case nir_tex_src_coord: {
7159          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7160          for (unsigned i = 0; i < coord.size(); i++)
7161             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7162          break;
7163       }
7164       case nir_tex_src_bias:
7165          if (instr->op == nir_texop_txb) {
7166             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7167             has_bias = true;
7168          }
7169          break;
7170       case nir_tex_src_lod: {
7171          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7172
7173          if (val && val->f32 <= 0.0) {
7174             level_zero = true;
7175          } else {
7176             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7177             has_lod = true;
7178          }
7179          break;
7180       }
7181       case nir_tex_src_comparator:
7182          if (instr->is_shadow) {
7183             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7184             has_compare = true;
7185          }
7186          break;
7187       case nir_tex_src_offset:
7188          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7189          get_const_vec(instr->src[i].src.ssa, const_offset);
7190          has_offset = true;
7191          break;
7192       case nir_tex_src_ddx:
7193          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7194          has_ddx = true;
7195          break;
7196       case nir_tex_src_ddy:
7197          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7198          has_ddy = true;
7199          break;
7200       case nir_tex_src_ms_index:
7201          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7202          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7203          has_sample_index = true;
7204          break;
7205       case nir_tex_src_texture_offset:
7206       case nir_tex_src_sampler_offset:
7207       default:
7208          break;
7209       }
7210    }
7211
7212    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7213       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7214
7215    if (instr->op == nir_texop_texture_samples) {
7216       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7217
7218       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7219       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7220       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7221       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7222
7223       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7224                samples, Operand(1u), bld.scc(is_msaa));
7225       return;
7226    }
7227
7228    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7229       aco_ptr<Instruction> tmp_instr;
7230       Temp acc, pack = Temp();
7231
7232       uint32_t pack_const = 0;
7233       for (unsigned i = 0; i < offset.size(); i++) {
7234          if (!const_offset[i])
7235             continue;
7236          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7237       }
7238
7239       if (offset.type() == RegType::sgpr) {
7240          for (unsigned i = 0; i < offset.size(); i++) {
7241             if (const_offset[i])
7242                continue;
7243
7244             acc = emit_extract_vector(ctx, offset, i, s1);
7245             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7246
7247             if (i) {
7248                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7249             }
7250
7251             if (pack == Temp()) {
7252                pack = acc;
7253             } else {
7254                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7255             }
7256          }
7257
7258          if (pack_const && pack != Temp())
7259             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7260       } else {
7261          for (unsigned i = 0; i < offset.size(); i++) {
7262             if (const_offset[i])
7263                continue;
7264
7265             acc = emit_extract_vector(ctx, offset, i, v1);
7266             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7267
7268             if (i) {
7269                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7270             }
7271
7272             if (pack == Temp()) {
7273                pack = acc;
7274             } else {
7275                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7276             }
7277          }
7278
7279          if (pack_const && pack != Temp())
7280             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7281       }
7282       if (pack_const && pack == Temp())
7283          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7284       else if (pack == Temp())
7285          has_offset = false;
7286       else
7287          offset = pack;
7288    }
7289
7290    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7291       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7292
7293    /* pack derivatives */
7294    if (has_ddx || has_ddy) {
7295       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7296          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7297          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7298          derivs = {ddy, zero, ddy, zero};
7299       } else {
7300          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7301             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7302          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7303             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7304       }
7305       has_derivs = true;
7306    }
7307
7308    if (instr->coord_components > 1 &&
7309        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7310        instr->is_array &&
7311        instr->op != nir_texop_txf)
7312       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7313
7314    if (instr->coord_components > 2 &&
7315       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7316        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7317        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7318        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7319        instr->is_array &&
7320        instr->op != nir_texop_txf &&
7321        instr->op != nir_texop_txf_ms &&
7322        instr->op != nir_texop_fragment_fetch &&
7323        instr->op != nir_texop_fragment_mask_fetch)
7324       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7325
7326    if (ctx->options->chip_class == GFX9 &&
7327        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7328        instr->op != nir_texop_lod && instr->coord_components) {
7329       assert(coords.size() > 0 && coords.size() < 3);
7330
7331       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7332                                                                      Operand((uint32_t) 0) :
7333                                                                      Operand((uint32_t) 0x3f000000)));
7334    }
7335
7336    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7337
7338    if (instr->op == nir_texop_samples_identical)
7339       resource = fmask_ptr;
7340
7341    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7342              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7343             instr->op != nir_texop_txs &&
7344             instr->op != nir_texop_fragment_fetch &&
7345             instr->op != nir_texop_fragment_mask_fetch) {
7346       assert(has_sample_index);
7347       Operand op(sample_index);
7348       if (sample_index_cv)
7349          op = Operand(sample_index_cv->u32);
7350       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7351    }
7352
7353    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7354       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7355          Temp off = emit_extract_vector(ctx, offset, i, v1);
7356          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7357       }
7358       has_offset = false;
7359    }
7360
7361    /* Build tex instruction */
7362    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7363    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7364                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7365                   : 0;
7366    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7367    Temp tmp_dst = dst;
7368
7369    /* gather4 selects the component by dmask and always returns vec4 */
7370    if (instr->op == nir_texop_tg4) {
7371       assert(instr->dest.ssa.num_components == 4);
7372       if (instr->is_shadow)
7373          dmask = 1;
7374       else
7375          dmask = 1 << instr->component;
7376       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7377          tmp_dst = bld.tmp(v4);
7378    } else if (instr->op == nir_texop_samples_identical) {
7379       tmp_dst = bld.tmp(v1);
7380    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7381       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7382    }
7383
7384    aco_ptr<MIMG_instruction> tex;
7385    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7386       if (!has_lod)
7387          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7388
7389       bool div_by_6 = instr->op == nir_texop_txs &&
7390                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7391                       instr->is_array &&
7392                       (dmask & (1 << 2));
7393       if (tmp_dst.id() == dst.id() && div_by_6)
7394          tmp_dst = bld.tmp(tmp_dst.regClass());
7395
7396       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7397       tex->operands[0] = Operand(resource);
7398       tex->operands[1] = Operand(s4); /* no sampler */
7399       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7400       if (ctx->options->chip_class == GFX9 &&
7401           instr->op == nir_texop_txs &&
7402           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7403           instr->is_array) {
7404          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7405       } else if (instr->op == nir_texop_query_levels) {
7406          tex->dmask = 1 << 3;
7407       } else {
7408          tex->dmask = dmask;
7409       }
7410       tex->da = da;
7411       tex->definitions[0] = Definition(tmp_dst);
7412       tex->dim = dim;
7413       tex->can_reorder = true;
7414       ctx->block->instructions.emplace_back(std::move(tex));
7415
7416       if (div_by_6) {
7417          /* divide 3rd value by 6 by multiplying with magic number */
7418          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7419          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7420          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7421          assert(instr->dest.ssa.num_components == 3);
7422          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7423          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7424                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7425                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7426                               by_6);
7427
7428       }
7429
7430       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7431       return;
7432    }
7433
7434    Temp tg4_compare_cube_wa64 = Temp();
7435
7436    if (tg4_integer_workarounds) {
7437       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7438       tex->operands[0] = Operand(resource);
7439       tex->operands[1] = Operand(s4); /* no sampler */
7440       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7441       tex->dim = dim;
7442       tex->dmask = 0x3;
7443       tex->da = da;
7444       Temp size = bld.tmp(v2);
7445       tex->definitions[0] = Definition(size);
7446       tex->can_reorder = true;
7447       ctx->block->instructions.emplace_back(std::move(tex));
7448       emit_split_vector(ctx, size, size.size());
7449
7450       Temp half_texel[2];
7451       for (unsigned i = 0; i < 2; i++) {
7452          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7453          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7454          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7455          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7456       }
7457
7458       Temp new_coords[2] = {
7459          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7460          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7461       };
7462
7463       if (tg4_integer_cube_workaround) {
7464          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7465          Temp desc[resource.size()];
7466          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7467                                                                            Format::PSEUDO, 1, resource.size())};
7468          split->operands[0] = Operand(resource);
7469          for (unsigned i = 0; i < resource.size(); i++) {
7470             desc[i] = bld.tmp(s1);
7471             split->definitions[i] = Definition(desc[i]);
7472          }
7473          ctx->block->instructions.emplace_back(std::move(split));
7474
7475          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7476          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7477                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7478
7479          Temp nfmt;
7480          if (stype == GLSL_TYPE_UINT) {
7481             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7482                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7483                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7484                             bld.scc(compare_cube_wa));
7485          } else {
7486             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7487                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7488                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7489                             bld.scc(compare_cube_wa));
7490          }
7491          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7492          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7493
7494          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7495
7496          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7497                             Operand((uint32_t)C_008F14_NUM_FORMAT));
7498          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
7499
7500          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
7501                                                                          Format::PSEUDO, resource.size(), 1)};
7502          for (unsigned i = 0; i < resource.size(); i++)
7503             vec->operands[i] = Operand(desc[i]);
7504          resource = bld.tmp(resource.regClass());
7505          vec->definitions[0] = Definition(resource);
7506          ctx->block->instructions.emplace_back(std::move(vec));
7507
7508          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7509                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
7510          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7511                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
7512       }
7513       coords[0] = new_coords[0];
7514       coords[1] = new_coords[1];
7515    }
7516
7517    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
7518       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
7519
7520       assert(coords.size() == 1);
7521       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
7522       aco_opcode op;
7523       switch (last_bit) {
7524       case 1:
7525          op = aco_opcode::buffer_load_format_x; break;
7526       case 2:
7527          op = aco_opcode::buffer_load_format_xy; break;
7528       case 3:
7529          op = aco_opcode::buffer_load_format_xyz; break;
7530       case 4:
7531          op = aco_opcode::buffer_load_format_xyzw; break;
7532       default:
7533          unreachable("Tex instruction loads more than 4 components.");
7534       }
7535
7536       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
7537       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
7538          tmp_dst = dst;
7539       else
7540          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
7541
7542       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
7543       mubuf->operands[0] = Operand(resource);
7544       mubuf->operands[1] = Operand(coords[0]);
7545       mubuf->operands[2] = Operand((uint32_t) 0);
7546       mubuf->definitions[0] = Definition(tmp_dst);
7547       mubuf->idxen = true;
7548       mubuf->can_reorder = true;
7549       ctx->block->instructions.emplace_back(std::move(mubuf));
7550
7551       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
7552       return;
7553    }
7554
7555    /* gather MIMG address components */
7556    std::vector<Temp> args;
7557    if (has_offset)
7558       args.emplace_back(offset);
7559    if (has_bias)
7560       args.emplace_back(bias);
7561    if (has_compare)
7562       args.emplace_back(compare);
7563    if (has_derivs)
7564       args.insert(args.end(), derivs.begin(), derivs.end());
7565
7566    args.insert(args.end(), coords.begin(), coords.end());
7567    if (has_sample_index)
7568       args.emplace_back(sample_index);
7569    if (has_lod)
7570       args.emplace_back(lod);
7571
7572    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
7573    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
7574    vec->definitions[0] = Definition(arg);
7575    for (unsigned i = 0; i < args.size(); i++)
7576       vec->operands[i] = Operand(args[i]);
7577    ctx->block->instructions.emplace_back(std::move(vec));
7578
7579
7580    if (instr->op == nir_texop_txf ||
7581        instr->op == nir_texop_txf_ms ||
7582        instr->op == nir_texop_samples_identical ||
7583        instr->op == nir_texop_fragment_fetch ||
7584        instr->op == nir_texop_fragment_mask_fetch) {
7585       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
7586       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
7587       tex->operands[0] = Operand(resource);
7588       tex->operands[1] = Operand(s4); /* no sampler */
7589       tex->operands[2] = Operand(arg);
7590       tex->dim = dim;
7591       tex->dmask = dmask;
7592       tex->unrm = true;
7593       tex->da = da;
7594       tex->definitions[0] = Definition(tmp_dst);
7595       tex->can_reorder = true;
7596       ctx->block->instructions.emplace_back(std::move(tex));
7597
7598       if (instr->op == nir_texop_samples_identical) {
7599          assert(dmask == 1 && dst.regClass() == v1);
7600          assert(dst.id() != tmp_dst.id());
7601
7602          Temp tmp = bld.tmp(bld.lm);
7603          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
7604          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
7605
7606       } else {
7607          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7608       }
7609       return;
7610    }
7611
7612    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
7613    aco_opcode opcode = aco_opcode::image_sample;
7614    if (has_offset) { /* image_sample_*_o */
7615       if (has_compare) {
7616          opcode = aco_opcode::image_sample_c_o;
7617          if (has_derivs)
7618             opcode = aco_opcode::image_sample_c_d_o;
7619          if (has_bias)
7620             opcode = aco_opcode::image_sample_c_b_o;
7621          if (level_zero)
7622             opcode = aco_opcode::image_sample_c_lz_o;
7623          if (has_lod)
7624             opcode = aco_opcode::image_sample_c_l_o;
7625       } else {
7626          opcode = aco_opcode::image_sample_o;
7627          if (has_derivs)
7628             opcode = aco_opcode::image_sample_d_o;
7629          if (has_bias)
7630             opcode = aco_opcode::image_sample_b_o;
7631          if (level_zero)
7632             opcode = aco_opcode::image_sample_lz_o;
7633          if (has_lod)
7634             opcode = aco_opcode::image_sample_l_o;
7635       }
7636    } else { /* no offset */
7637       if (has_compare) {
7638          opcode = aco_opcode::image_sample_c;
7639          if (has_derivs)
7640             opcode = aco_opcode::image_sample_c_d;
7641          if (has_bias)
7642             opcode = aco_opcode::image_sample_c_b;
7643          if (level_zero)
7644             opcode = aco_opcode::image_sample_c_lz;
7645          if (has_lod)
7646             opcode = aco_opcode::image_sample_c_l;
7647       } else {
7648          opcode = aco_opcode::image_sample;
7649          if (has_derivs)
7650             opcode = aco_opcode::image_sample_d;
7651          if (has_bias)
7652             opcode = aco_opcode::image_sample_b;
7653          if (level_zero)
7654             opcode = aco_opcode::image_sample_lz;
7655          if (has_lod)
7656             opcode = aco_opcode::image_sample_l;
7657       }
7658    }
7659
7660    if (instr->op == nir_texop_tg4) {
7661       if (has_offset) {
7662          opcode = aco_opcode::image_gather4_lz_o;
7663          if (has_compare)
7664             opcode = aco_opcode::image_gather4_c_lz_o;
7665       } else {
7666          opcode = aco_opcode::image_gather4_lz;
7667          if (has_compare)
7668             opcode = aco_opcode::image_gather4_c_lz;
7669       }
7670    } else if (instr->op == nir_texop_lod) {
7671       opcode = aco_opcode::image_get_lod;
7672    }
7673
7674    /* we don't need the bias, sample index, compare value or offset to be
7675     * computed in WQM but if the p_create_vector copies the coordinates, then it
7676     * needs to be in WQM */
7677    if (ctx->stage == fragment_fs &&
7678        !has_derivs && !has_lod && !level_zero &&
7679        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
7680        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
7681       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
7682
7683    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
7684    tex->operands[0] = Operand(resource);
7685    tex->operands[1] = Operand(sampler);
7686    tex->operands[2] = Operand(arg);
7687    tex->dim = dim;
7688    tex->dmask = dmask;
7689    tex->da = da;
7690    tex->definitions[0] = Definition(tmp_dst);
7691    tex->can_reorder = true;
7692    ctx->block->instructions.emplace_back(std::move(tex));
7693
7694    if (tg4_integer_cube_workaround) {
7695       assert(tmp_dst.id() != dst.id());
7696       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
7697
7698       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7699       Temp val[4];
7700       for (unsigned i = 0; i < dst.size(); i++) {
7701          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
7702          Temp cvt_val;
7703          if (stype == GLSL_TYPE_UINT)
7704             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
7705          else
7706             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
7707          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
7708       }
7709       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
7710       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7711                            val[0], val[1], val[2], val[3]);
7712    }
7713    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
7714    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
7715
7716 }
7717
7718
7719 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
7720 {
7721    Temp tmp = get_ssa_temp(ctx, ssa);
7722    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
7723       return Operand(tmp.regClass());
7724    else
7725       return Operand(tmp);
7726 }
7727
7728 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
7729 {
7730    aco_ptr<Pseudo_instruction> phi;
7731    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7732    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
7733
7734    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
7735    logical |= ctx->block->kind & block_kind_merge;
7736    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
7737
7738    /* we want a sorted list of sources, since the predecessor list is also sorted */
7739    std::map<unsigned, nir_ssa_def*> phi_src;
7740    nir_foreach_phi_src(src, instr)
7741       phi_src[src->pred->index] = src->src.ssa;
7742
7743    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
7744    unsigned num_operands = 0;
7745    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size())];
7746    unsigned num_defined = 0;
7747    unsigned cur_pred_idx = 0;
7748    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
7749       if (cur_pred_idx < preds.size()) {
7750          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
7751          unsigned block = ctx->cf_info.nir_to_aco[src.first];
7752          unsigned skipped = 0;
7753          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
7754             skipped++;
7755          if (cur_pred_idx + skipped < preds.size()) {
7756             for (unsigned i = 0; i < skipped; i++)
7757                operands[num_operands++] = Operand(dst.regClass());
7758             cur_pred_idx += skipped;
7759          } else {
7760             continue;
7761          }
7762       }
7763       cur_pred_idx++;
7764       Operand op = get_phi_operand(ctx, src.second);
7765       operands[num_operands++] = op;
7766       num_defined += !op.isUndefined();
7767    }
7768    /* handle block_kind_continue_or_break at loop exit blocks */
7769    while (cur_pred_idx++ < preds.size())
7770       operands[num_operands++] = Operand(dst.regClass());
7771
7772    if (num_defined == 0) {
7773       Builder bld(ctx->program, ctx->block);
7774       if (dst.regClass() == s1) {
7775          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
7776       } else if (dst.regClass() == v1) {
7777          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
7778       } else {
7779          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7780          for (unsigned i = 0; i < dst.size(); i++)
7781             vec->operands[i] = Operand(0u);
7782          vec->definitions[0] = Definition(dst);
7783          ctx->block->instructions.emplace_back(std::move(vec));
7784       }
7785       return;
7786    }
7787
7788    /* we can use a linear phi in some cases if one src is undef */
7789    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
7790       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
7791
7792       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
7793       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
7794       assert(invert->kind & block_kind_invert);
7795
7796       unsigned then_block = invert->linear_preds[0];
7797
7798       Block* insert_block = NULL;
7799       for (unsigned i = 0; i < num_operands; i++) {
7800          Operand op = operands[i];
7801          if (op.isUndefined())
7802             continue;
7803          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
7804          phi->operands[0] = op;
7805          break;
7806       }
7807       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
7808       phi->operands[1] = Operand(dst.regClass());
7809       phi->definitions[0] = Definition(dst);
7810       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
7811       return;
7812    }
7813
7814    /* try to scalarize vector phis */
7815    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
7816       // TODO: scalarize linear phis on divergent ifs
7817       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
7818       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
7819       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
7820          Operand src = operands[i];
7821          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
7822             can_scalarize = false;
7823       }
7824       if (can_scalarize) {
7825          unsigned num_components = instr->dest.ssa.num_components;
7826          assert(dst.size() % num_components == 0);
7827          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
7828
7829          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
7830          for (unsigned k = 0; k < num_components; k++) {
7831             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7832             for (unsigned i = 0; i < num_operands; i++) {
7833                Operand src = operands[i];
7834                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
7835             }
7836             Temp phi_dst = {ctx->program->allocateId(), rc};
7837             phi->definitions[0] = Definition(phi_dst);
7838             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7839             new_vec[k] = phi_dst;
7840             vec->operands[k] = Operand(phi_dst);
7841          }
7842          vec->definitions[0] = Definition(dst);
7843          ctx->block->instructions.emplace_back(std::move(vec));
7844          ctx->allocated_vec.emplace(dst.id(), new_vec);
7845          return;
7846       }
7847    }
7848
7849    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
7850    for (unsigned i = 0; i < num_operands; i++)
7851       phi->operands[i] = operands[i];
7852    phi->definitions[0] = Definition(dst);
7853    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
7854 }
7855
7856
7857 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
7858 {
7859    Temp dst = get_ssa_temp(ctx, &instr->def);
7860
7861    assert(dst.type() == RegType::sgpr);
7862
7863    if (dst.size() == 1) {
7864       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
7865    } else {
7866       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
7867       for (unsigned i = 0; i < dst.size(); i++)
7868          vec->operands[i] = Operand(0u);
7869       vec->definitions[0] = Definition(dst);
7870       ctx->block->instructions.emplace_back(std::move(vec));
7871    }
7872 }
7873
7874 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
7875 {
7876    Builder bld(ctx->program, ctx->block);
7877    Block *logical_target;
7878    append_logical_end(ctx->block);
7879    unsigned idx = ctx->block->index;
7880
7881    switch (instr->type) {
7882    case nir_jump_break:
7883       logical_target = ctx->cf_info.parent_loop.exit;
7884       add_logical_edge(idx, logical_target);
7885       ctx->block->kind |= block_kind_break;
7886
7887       if (!ctx->cf_info.parent_if.is_divergent &&
7888           !ctx->cf_info.parent_loop.has_divergent_continue) {
7889          /* uniform break - directly jump out of the loop */
7890          ctx->block->kind |= block_kind_uniform;
7891          ctx->cf_info.has_branch = true;
7892          bld.branch(aco_opcode::p_branch);
7893          add_linear_edge(idx, logical_target);
7894          return;
7895       }
7896       ctx->cf_info.parent_loop.has_divergent_branch = true;
7897       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7898       break;
7899    case nir_jump_continue:
7900       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7901       add_logical_edge(idx, logical_target);
7902       ctx->block->kind |= block_kind_continue;
7903
7904       if (ctx->cf_info.parent_if.is_divergent) {
7905          /* for potential uniform breaks after this continue,
7906             we must ensure that they are handled correctly */
7907          ctx->cf_info.parent_loop.has_divergent_continue = true;
7908          ctx->cf_info.parent_loop.has_divergent_branch = true;
7909          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
7910       } else {
7911          /* uniform continue - directly jump to the loop header */
7912          ctx->block->kind |= block_kind_uniform;
7913          ctx->cf_info.has_branch = true;
7914          bld.branch(aco_opcode::p_branch);
7915          add_linear_edge(idx, logical_target);
7916          return;
7917       }
7918       break;
7919    default:
7920       fprintf(stderr, "Unknown NIR jump instr: ");
7921       nir_print_instr(&instr->instr, stderr);
7922       fprintf(stderr, "\n");
7923       abort();
7924    }
7925
7926    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
7927       ctx->cf_info.exec_potentially_empty_break = true;
7928       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
7929    }
7930
7931    /* remove critical edges from linear CFG */
7932    bld.branch(aco_opcode::p_branch);
7933    Block* break_block = ctx->program->create_and_insert_block();
7934    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7935    break_block->kind |= block_kind_uniform;
7936    add_linear_edge(idx, break_block);
7937    /* the loop_header pointer might be invalidated by this point */
7938    if (instr->type == nir_jump_continue)
7939       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
7940    add_linear_edge(break_block->index, logical_target);
7941    bld.reset(break_block);
7942    bld.branch(aco_opcode::p_branch);
7943
7944    Block* continue_block = ctx->program->create_and_insert_block();
7945    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
7946    add_linear_edge(idx, continue_block);
7947    append_logical_start(continue_block);
7948    ctx->block = continue_block;
7949    return;
7950 }
7951
7952 void visit_block(isel_context *ctx, nir_block *block)
7953 {
7954    nir_foreach_instr(instr, block) {
7955       switch (instr->type) {
7956       case nir_instr_type_alu:
7957          visit_alu_instr(ctx, nir_instr_as_alu(instr));
7958          break;
7959       case nir_instr_type_load_const:
7960          visit_load_const(ctx, nir_instr_as_load_const(instr));
7961          break;
7962       case nir_instr_type_intrinsic:
7963          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
7964          break;
7965       case nir_instr_type_tex:
7966          visit_tex(ctx, nir_instr_as_tex(instr));
7967          break;
7968       case nir_instr_type_phi:
7969          visit_phi(ctx, nir_instr_as_phi(instr));
7970          break;
7971       case nir_instr_type_ssa_undef:
7972          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
7973          break;
7974       case nir_instr_type_deref:
7975          break;
7976       case nir_instr_type_jump:
7977          visit_jump(ctx, nir_instr_as_jump(instr));
7978          break;
7979       default:
7980          fprintf(stderr, "Unknown NIR instr type: ");
7981          nir_print_instr(instr, stderr);
7982          fprintf(stderr, "\n");
7983          //abort();
7984       }
7985    }
7986
7987    if (!ctx->cf_info.parent_loop.has_divergent_branch)
7988       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
7989 }
7990
7991
7992
7993 static void visit_loop(isel_context *ctx, nir_loop *loop)
7994 {
7995    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
7996    append_logical_end(ctx->block);
7997    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
7998    Builder bld(ctx->program, ctx->block);
7999    bld.branch(aco_opcode::p_branch);
8000    unsigned loop_preheader_idx = ctx->block->index;
8001
8002    Block loop_exit = Block();
8003    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8004    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8005
8006    Block* loop_header = ctx->program->create_and_insert_block();
8007    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8008    loop_header->kind |= block_kind_loop_header;
8009    add_edge(loop_preheader_idx, loop_header);
8010    ctx->block = loop_header;
8011
8012    /* emit loop body */
8013    unsigned loop_header_idx = loop_header->index;
8014    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8015    append_logical_start(ctx->block);
8016    visit_cf_list(ctx, &loop->body);
8017
8018    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8019    if (!ctx->cf_info.has_branch) {
8020       append_logical_end(ctx->block);
8021       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8022          /* Discards can result in code running with an empty exec mask.
8023           * This would result in divergent breaks not ever being taken. As a
8024           * workaround, break the loop when the loop mask is empty instead of
8025           * always continuing. */
8026          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8027          unsigned block_idx = ctx->block->index;
8028
8029          /* create helper blocks to avoid critical edges */
8030          Block *break_block = ctx->program->create_and_insert_block();
8031          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8032          break_block->kind = block_kind_uniform;
8033          bld.reset(break_block);
8034          bld.branch(aco_opcode::p_branch);
8035          add_linear_edge(block_idx, break_block);
8036          add_linear_edge(break_block->index, &loop_exit);
8037
8038          Block *continue_block = ctx->program->create_and_insert_block();
8039          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8040          continue_block->kind = block_kind_uniform;
8041          bld.reset(continue_block);
8042          bld.branch(aco_opcode::p_branch);
8043          add_linear_edge(block_idx, continue_block);
8044          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8045
8046          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8047             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8048          ctx->block = &ctx->program->blocks[block_idx];
8049       } else {
8050          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8051          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8052             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8053          else
8054             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8055       }
8056
8057       bld.reset(ctx->block);
8058       bld.branch(aco_opcode::p_branch);
8059    }
8060
8061    /* fixup phis in loop header from unreachable blocks */
8062    if (ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch) {
8063       bool linear = ctx->cf_info.has_branch;
8064       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8065       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8066          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8067              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8068             /* the last operand should be the one that needs to be removed */
8069             instr->operands.pop_back();
8070          } else if (!is_phi(instr)) {
8071             break;
8072          }
8073       }
8074    }
8075
8076    ctx->cf_info.has_branch = false;
8077
8078    // TODO: if the loop has not a single exit, we must add one °°
8079    /* emit loop successor block */
8080    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8081    append_logical_start(ctx->block);
8082
8083    #if 0
8084    // TODO: check if it is beneficial to not branch on continues
8085    /* trim linear phis in loop header */
8086    for (auto&& instr : loop_entry->instructions) {
8087       if (instr->opcode == aco_opcode::p_linear_phi) {
8088          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8089          new_phi->definitions[0] = instr->definitions[0];
8090          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8091             new_phi->operands[i] = instr->operands[i];
8092          /* check that the remaining operands are all the same */
8093          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8094             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8095          instr.swap(new_phi);
8096       } else if (instr->opcode == aco_opcode::p_phi) {
8097          continue;
8098       } else {
8099          break;
8100       }
8101    }
8102    #endif
8103 }
8104
8105 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8106 {
8107    ic->cond = cond;
8108
8109    append_logical_end(ctx->block);
8110    ctx->block->kind |= block_kind_branch;
8111
8112    /* branch to linear then block */
8113    assert(cond.regClass() == ctx->program->lane_mask);
8114    aco_ptr<Pseudo_branch_instruction> branch;
8115    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8116    branch->operands[0] = Operand(cond);
8117    ctx->block->instructions.push_back(std::move(branch));
8118
8119    ic->BB_if_idx = ctx->block->index;
8120    ic->BB_invert = Block();
8121    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8122    /* Invert blocks are intentionally not marked as top level because they
8123     * are not part of the logical cfg. */
8124    ic->BB_invert.kind |= block_kind_invert;
8125    ic->BB_endif = Block();
8126    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8127    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8128
8129    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8130    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8131    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8132    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8133    ctx->cf_info.parent_if.is_divergent = true;
8134
8135    /* divergent branches use cbranch_execz */
8136    ctx->cf_info.exec_potentially_empty_discard = false;
8137    ctx->cf_info.exec_potentially_empty_break = false;
8138    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8139
8140    /** emit logical then block */
8141    Block* BB_then_logical = ctx->program->create_and_insert_block();
8142    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8143    add_edge(ic->BB_if_idx, BB_then_logical);
8144    ctx->block = BB_then_logical;
8145    append_logical_start(BB_then_logical);
8146 }
8147
8148 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8149 {
8150    Block *BB_then_logical = ctx->block;
8151    append_logical_end(BB_then_logical);
8152     /* branch from logical then block to invert block */
8153    aco_ptr<Pseudo_branch_instruction> branch;
8154    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8155    BB_then_logical->instructions.emplace_back(std::move(branch));
8156    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8157    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8158       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8159    BB_then_logical->kind |= block_kind_uniform;
8160    assert(!ctx->cf_info.has_branch);
8161    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8162    ctx->cf_info.parent_loop.has_divergent_branch = false;
8163
8164    /** emit linear then block */
8165    Block* BB_then_linear = ctx->program->create_and_insert_block();
8166    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8167    BB_then_linear->kind |= block_kind_uniform;
8168    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8169    /* branch from linear then block to invert block */
8170    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8171    BB_then_linear->instructions.emplace_back(std::move(branch));
8172    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8173
8174    /** emit invert merge block */
8175    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8176    ic->invert_idx = ctx->block->index;
8177
8178    /* branch to linear else block (skip else) */
8179    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8180    branch->operands[0] = Operand(ic->cond);
8181    ctx->block->instructions.push_back(std::move(branch));
8182
8183    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8184    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8185    ic->exec_potentially_empty_break_depth_old =
8186       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8187    /* divergent branches use cbranch_execz */
8188    ctx->cf_info.exec_potentially_empty_discard = false;
8189    ctx->cf_info.exec_potentially_empty_break = false;
8190    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8191
8192    /** emit logical else block */
8193    Block* BB_else_logical = ctx->program->create_and_insert_block();
8194    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8195    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8196    add_linear_edge(ic->invert_idx, BB_else_logical);
8197    ctx->block = BB_else_logical;
8198    append_logical_start(BB_else_logical);
8199 }
8200
8201 static void end_divergent_if(isel_context *ctx, if_context *ic)
8202 {
8203    Block *BB_else_logical = ctx->block;
8204    append_logical_end(BB_else_logical);
8205
8206    /* branch from logical else block to endif block */
8207    aco_ptr<Pseudo_branch_instruction> branch;
8208    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8209    BB_else_logical->instructions.emplace_back(std::move(branch));
8210    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8211    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8212       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8213    BB_else_logical->kind |= block_kind_uniform;
8214
8215    assert(!ctx->cf_info.has_branch);
8216    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8217
8218
8219    /** emit linear else block */
8220    Block* BB_else_linear = ctx->program->create_and_insert_block();
8221    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8222    BB_else_linear->kind |= block_kind_uniform;
8223    add_linear_edge(ic->invert_idx, BB_else_linear);
8224
8225    /* branch from linear else block to endif block */
8226    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8227    BB_else_linear->instructions.emplace_back(std::move(branch));
8228    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8229
8230
8231    /** emit endif merge block */
8232    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8233    append_logical_start(ctx->block);
8234
8235
8236    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8237    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8238    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8239    ctx->cf_info.exec_potentially_empty_break_depth =
8240       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8241    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8242        !ctx->cf_info.parent_if.is_divergent) {
8243       ctx->cf_info.exec_potentially_empty_break = false;
8244       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8245    }
8246    /* uniform control flow never has an empty exec-mask */
8247    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8248       ctx->cf_info.exec_potentially_empty_discard = false;
8249       ctx->cf_info.exec_potentially_empty_break = false;
8250       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8251    }
8252 }
8253
8254 static void visit_if(isel_context *ctx, nir_if *if_stmt)
8255 {
8256    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8257    Builder bld(ctx->program, ctx->block);
8258    aco_ptr<Pseudo_branch_instruction> branch;
8259
8260    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8261       /**
8262        * Uniform conditionals are represented in the following way*) :
8263        *
8264        * The linear and logical CFG:
8265        *                        BB_IF
8266        *                        /    \
8267        *       BB_THEN (logical)      BB_ELSE (logical)
8268        *                        \    /
8269        *                        BB_ENDIF
8270        *
8271        * *) Exceptions may be due to break and continue statements within loops
8272        *    If a break/continue happens within uniform control flow, it branches
8273        *    to the loop exit/entry block. Otherwise, it branches to the next
8274        *    merge block.
8275        **/
8276       append_logical_end(ctx->block);
8277       ctx->block->kind |= block_kind_uniform;
8278
8279       /* emit branch */
8280       assert(cond.regClass() == bld.lm);
8281       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8282       cond = bool_to_scalar_condition(ctx, cond);
8283
8284       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8285       branch->operands[0] = Operand(cond);
8286       branch->operands[0].setFixed(scc);
8287       ctx->block->instructions.emplace_back(std::move(branch));
8288
8289       unsigned BB_if_idx = ctx->block->index;
8290       Block BB_endif = Block();
8291       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8292       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8293
8294       /** emit then block */
8295       Block* BB_then = ctx->program->create_and_insert_block();
8296       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8297       add_edge(BB_if_idx, BB_then);
8298       append_logical_start(BB_then);
8299       ctx->block = BB_then;
8300       visit_cf_list(ctx, &if_stmt->then_list);
8301       BB_then = ctx->block;
8302       bool then_branch = ctx->cf_info.has_branch;
8303       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8304
8305       if (!then_branch) {
8306          append_logical_end(BB_then);
8307          /* branch from then block to endif block */
8308          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8309          BB_then->instructions.emplace_back(std::move(branch));
8310          add_linear_edge(BB_then->index, &BB_endif);
8311          if (!then_branch_divergent)
8312             add_logical_edge(BB_then->index, &BB_endif);
8313          BB_then->kind |= block_kind_uniform;
8314       }
8315
8316       ctx->cf_info.has_branch = false;
8317       ctx->cf_info.parent_loop.has_divergent_branch = false;
8318
8319       /** emit else block */
8320       Block* BB_else = ctx->program->create_and_insert_block();
8321       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8322       add_edge(BB_if_idx, BB_else);
8323       append_logical_start(BB_else);
8324       ctx->block = BB_else;
8325       visit_cf_list(ctx, &if_stmt->else_list);
8326       BB_else = ctx->block;
8327
8328       if (!ctx->cf_info.has_branch) {
8329          append_logical_end(BB_else);
8330          /* branch from then block to endif block */
8331          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8332          BB_else->instructions.emplace_back(std::move(branch));
8333          add_linear_edge(BB_else->index, &BB_endif);
8334          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8335             add_logical_edge(BB_else->index, &BB_endif);
8336          BB_else->kind |= block_kind_uniform;
8337       }
8338
8339       ctx->cf_info.has_branch &= then_branch;
8340       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8341
8342       /** emit endif merge block */
8343       if (!ctx->cf_info.has_branch) {
8344          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8345          append_logical_start(ctx->block);
8346       }
8347    } else { /* non-uniform condition */
8348       /**
8349        * To maintain a logical and linear CFG without critical edges,
8350        * non-uniform conditionals are represented in the following way*) :
8351        *
8352        * The linear CFG:
8353        *                        BB_IF
8354        *                        /    \
8355        *       BB_THEN (logical)      BB_THEN (linear)
8356        *                        \    /
8357        *                        BB_INVERT (linear)
8358        *                        /    \
8359        *       BB_ELSE (logical)      BB_ELSE (linear)
8360        *                        \    /
8361        *                        BB_ENDIF
8362        *
8363        * The logical CFG:
8364        *                        BB_IF
8365        *                        /    \
8366        *       BB_THEN (logical)      BB_ELSE (logical)
8367        *                        \    /
8368        *                        BB_ENDIF
8369        *
8370        * *) Exceptions may be due to break and continue statements within loops
8371        **/
8372
8373       if_context ic;
8374
8375       begin_divergent_if_then(ctx, &ic, cond);
8376       visit_cf_list(ctx, &if_stmt->then_list);
8377
8378       begin_divergent_if_else(ctx, &ic);
8379       visit_cf_list(ctx, &if_stmt->else_list);
8380
8381       end_divergent_if(ctx, &ic);
8382    }
8383 }
8384
8385 static void visit_cf_list(isel_context *ctx,
8386                           struct exec_list *list)
8387 {
8388    foreach_list_typed(nir_cf_node, node, node, list) {
8389       switch (node->type) {
8390       case nir_cf_node_block:
8391          visit_block(ctx, nir_cf_node_as_block(node));
8392          break;
8393       case nir_cf_node_if:
8394          visit_if(ctx, nir_cf_node_as_if(node));
8395          break;
8396       case nir_cf_node_loop:
8397          visit_loop(ctx, nir_cf_node_as_loop(node));
8398          break;
8399       default:
8400          unreachable("unimplemented cf list type");
8401       }
8402    }
8403 }
8404
8405 static void export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
8406 {
8407    int offset = ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
8408    uint64_t mask = ctx->outputs.mask[slot];
8409    if (!is_pos && !mask)
8410       return;
8411    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
8412       return;
8413    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8414    exp->enabled_mask = mask;
8415    for (unsigned i = 0; i < 4; ++i) {
8416       if (mask & (1 << i))
8417          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
8418       else
8419          exp->operands[i] = Operand(v1);
8420    }
8421    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
8422     * Setting valid_mask=1 prevents it and has no other effect.
8423     */
8424    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
8425    exp->done = false;
8426    exp->compressed = false;
8427    if (is_pos)
8428       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8429    else
8430       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
8431    ctx->block->instructions.emplace_back(std::move(exp));
8432 }
8433
8434 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
8435 {
8436    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
8437    exp->enabled_mask = 0;
8438    for (unsigned i = 0; i < 4; ++i)
8439       exp->operands[i] = Operand(v1);
8440    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
8441       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
8442       exp->enabled_mask |= 0x1;
8443    }
8444    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
8445       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
8446       exp->enabled_mask |= 0x4;
8447    }
8448    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
8449       if (ctx->options->chip_class < GFX9) {
8450          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
8451          exp->enabled_mask |= 0x8;
8452       } else {
8453          Builder bld(ctx->program, ctx->block);
8454
8455          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
8456                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
8457          if (exp->operands[2].isTemp())
8458             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
8459
8460          exp->operands[2] = Operand(out);
8461          exp->enabled_mask |= 0x4;
8462       }
8463    }
8464    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
8465    exp->done = false;
8466    exp->compressed = false;
8467    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
8468    ctx->block->instructions.emplace_back(std::move(exp));
8469 }
8470
8471 static void create_vs_exports(isel_context *ctx)
8472 {
8473    radv_vs_output_info *outinfo = &ctx->program->info->vs.outinfo;
8474
8475    if (outinfo->export_prim_id) {
8476       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
8477       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
8478    }
8479
8480    if (ctx->options->key.has_multiview_view_index) {
8481       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
8482       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
8483    }
8484
8485    /* the order these position exports are created is important */
8486    int next_pos = 0;
8487    export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
8488    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
8489       export_vs_psiz_layer_viewport(ctx, &next_pos);
8490    }
8491    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8492       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
8493    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8494       export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
8495
8496    if (ctx->export_clip_dists) {
8497       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
8498          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
8499       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
8500          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
8501    }
8502
8503    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
8504       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
8505           i != VARYING_SLOT_PRIMITIVE_ID)
8506          continue;
8507
8508       export_vs_varying(ctx, i, false, NULL);
8509    }
8510 }
8511
8512 static void export_fs_mrt_z(isel_context *ctx)
8513 {
8514    Builder bld(ctx->program, ctx->block);
8515    unsigned enabled_channels = 0;
8516    bool compr = false;
8517    Operand values[4];
8518
8519    for (unsigned i = 0; i < 4; ++i) {
8520       values[i] = Operand(v1);
8521    }
8522
8523    /* Both stencil and sample mask only need 16-bits. */
8524    if (!ctx->program->info->ps.writes_z &&
8525        (ctx->program->info->ps.writes_stencil ||
8526         ctx->program->info->ps.writes_sample_mask)) {
8527       compr = true; /* COMPR flag */
8528
8529       if (ctx->program->info->ps.writes_stencil) {
8530          /* Stencil should be in X[23:16]. */
8531          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8532          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
8533          enabled_channels |= 0x3;
8534       }
8535
8536       if (ctx->program->info->ps.writes_sample_mask) {
8537          /* SampleMask should be in Y[15:0]. */
8538          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8539          enabled_channels |= 0xc;
8540      }
8541    } else {
8542       if (ctx->program->info->ps.writes_z) {
8543          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
8544          enabled_channels |= 0x1;
8545       }
8546
8547       if (ctx->program->info->ps.writes_stencil) {
8548          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
8549          enabled_channels |= 0x2;
8550       }
8551
8552       if (ctx->program->info->ps.writes_sample_mask) {
8553          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
8554          enabled_channels |= 0x4;
8555       }
8556    }
8557
8558    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
8559     * writemask component.
8560     */
8561    if (ctx->options->chip_class == GFX6 &&
8562        ctx->options->family != CHIP_OLAND &&
8563        ctx->options->family != CHIP_HAINAN) {
8564             enabled_channels |= 0x1;
8565    }
8566
8567    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8568            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
8569 }
8570
8571 static void export_fs_mrt_color(isel_context *ctx, int slot)
8572 {
8573    Builder bld(ctx->program, ctx->block);
8574    unsigned write_mask = ctx->outputs.mask[slot];
8575    Operand values[4];
8576
8577    for (unsigned i = 0; i < 4; ++i) {
8578       if (write_mask & (1 << i)) {
8579          values[i] = Operand(ctx->outputs.outputs[slot][i]);
8580       } else {
8581          values[i] = Operand(v1);
8582       }
8583    }
8584
8585    unsigned target, col_format;
8586    unsigned enabled_channels = 0;
8587    aco_opcode compr_op = (aco_opcode)0;
8588
8589    slot -= FRAG_RESULT_DATA0;
8590    target = V_008DFC_SQ_EXP_MRT + slot;
8591    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
8592
8593    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
8594    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
8595
8596    switch (col_format)
8597    {
8598    case V_028714_SPI_SHADER_ZERO:
8599       enabled_channels = 0; /* writemask */
8600       target = V_008DFC_SQ_EXP_NULL;
8601       break;
8602
8603    case V_028714_SPI_SHADER_32_R:
8604       enabled_channels = 1;
8605       break;
8606
8607    case V_028714_SPI_SHADER_32_GR:
8608       enabled_channels = 0x3;
8609       break;
8610
8611    case V_028714_SPI_SHADER_32_AR:
8612       if (ctx->options->chip_class >= GFX10) {
8613          /* Special case: on GFX10, the outputs are different for 32_AR */
8614          enabled_channels = 0x3;
8615          values[1] = values[3];
8616          values[3] = Operand(v1);
8617       } else {
8618          enabled_channels = 0x9;
8619       }
8620       break;
8621
8622    case V_028714_SPI_SHADER_FP16_ABGR:
8623       enabled_channels = 0x5;
8624       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
8625       break;
8626
8627    case V_028714_SPI_SHADER_UNORM16_ABGR:
8628       enabled_channels = 0x5;
8629       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
8630       break;
8631
8632    case V_028714_SPI_SHADER_SNORM16_ABGR:
8633       enabled_channels = 0x5;
8634       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
8635       break;
8636
8637    case V_028714_SPI_SHADER_UINT16_ABGR: {
8638       enabled_channels = 0x5;
8639       compr_op = aco_opcode::v_cvt_pk_u16_u32;
8640       if (is_int8 || is_int10) {
8641          /* clamp */
8642          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
8643          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8644
8645          for (unsigned i = 0; i < 4; i++) {
8646             if ((write_mask >> i) & 1) {
8647                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
8648                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
8649                                     values[i]);
8650             }
8651          }
8652       }
8653       break;
8654    }
8655
8656    case V_028714_SPI_SHADER_SINT16_ABGR:
8657       enabled_channels = 0x5;
8658       compr_op = aco_opcode::v_cvt_pk_i16_i32;
8659       if (is_int8 || is_int10) {
8660          /* clamp */
8661          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
8662          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
8663          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
8664          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
8665
8666          for (unsigned i = 0; i < 4; i++) {
8667             if ((write_mask >> i) & 1) {
8668                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
8669                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
8670                                     values[i]);
8671                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
8672                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
8673                                     values[i]);
8674             }
8675          }
8676       }
8677       break;
8678
8679    case V_028714_SPI_SHADER_32_ABGR:
8680       enabled_channels = 0xF;
8681       break;
8682
8683    default:
8684       break;
8685    }
8686
8687    if (target == V_008DFC_SQ_EXP_NULL)
8688       return;
8689
8690    if ((bool) compr_op) {
8691       for (int i = 0; i < 2; i++) {
8692          /* check if at least one of the values to be compressed is enabled */
8693          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
8694          if (enabled) {
8695             enabled_channels |= enabled << (i*2);
8696             values[i] = bld.vop3(compr_op, bld.def(v1),
8697                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
8698                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
8699          } else {
8700             values[i] = Operand(v1);
8701          }
8702       }
8703       values[2] = Operand(v1);
8704       values[3] = Operand(v1);
8705    } else {
8706       for (int i = 0; i < 4; i++)
8707          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
8708    }
8709
8710    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
8711            enabled_channels, target, (bool) compr_op);
8712 }
8713
8714 static void create_fs_exports(isel_context *ctx)
8715 {
8716    /* Export depth, stencil and sample mask. */
8717    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
8718        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
8719        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK]) {
8720       export_fs_mrt_z(ctx);
8721    }
8722
8723    /* Export all color render targets. */
8724    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i) {
8725       if (ctx->outputs.mask[i])
8726          export_fs_mrt_color(ctx, i);
8727    }
8728 }
8729
8730 static void emit_stream_output(isel_context *ctx,
8731                                Temp const *so_buffers,
8732                                Temp const *so_write_offset,
8733                                const struct radv_stream_output *output)
8734 {
8735    unsigned num_comps = util_bitcount(output->component_mask);
8736    unsigned writemask = (1 << num_comps) - 1;
8737    unsigned loc = output->location;
8738    unsigned buf = output->buffer;
8739
8740    assert(num_comps && num_comps <= 4);
8741    if (!num_comps || num_comps > 4)
8742       return;
8743
8744    unsigned start = ffs(output->component_mask) - 1;
8745
8746    Temp out[4];
8747    bool all_undef = true;
8748    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
8749    for (unsigned i = 0; i < num_comps; i++) {
8750       out[i] = ctx->outputs.outputs[loc][start + i];
8751       all_undef = all_undef && !out[i].id();
8752    }
8753    if (all_undef)
8754       return;
8755
8756    while (writemask) {
8757       int start, count;
8758       u_bit_scan_consecutive_range(&writemask, &start, &count);
8759       if (count == 3 && ctx->options->chip_class == GFX6) {
8760          /* GFX6 doesn't support storing vec3, split it. */
8761          writemask |= 1u << (start + 2);
8762          count = 2;
8763       }
8764
8765       unsigned offset = output->offset + start * 4;
8766
8767       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
8768       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
8769       for (int i = 0; i < count; ++i)
8770          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
8771       vec->definitions[0] = Definition(write_data);
8772       ctx->block->instructions.emplace_back(std::move(vec));
8773
8774       aco_opcode opcode;
8775       switch (count) {
8776       case 1:
8777          opcode = aco_opcode::buffer_store_dword;
8778          break;
8779       case 2:
8780          opcode = aco_opcode::buffer_store_dwordx2;
8781          break;
8782       case 3:
8783          opcode = aco_opcode::buffer_store_dwordx3;
8784          break;
8785       case 4:
8786          opcode = aco_opcode::buffer_store_dwordx4;
8787          break;
8788       default:
8789          unreachable("Unsupported dword count.");
8790       }
8791
8792       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
8793       store->operands[0] = Operand(so_buffers[buf]);
8794       store->operands[1] = Operand(so_write_offset[buf]);
8795       store->operands[2] = Operand((uint32_t) 0);
8796       store->operands[3] = Operand(write_data);
8797       if (offset > 4095) {
8798          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
8799          Builder bld(ctx->program, ctx->block);
8800          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
8801       } else {
8802          store->offset = offset;
8803       }
8804       store->offen = true;
8805       store->glc = true;
8806       store->dlc = false;
8807       store->slc = true;
8808       store->can_reorder = true;
8809       ctx->block->instructions.emplace_back(std::move(store));
8810    }
8811 }
8812
8813 static void emit_streamout(isel_context *ctx, unsigned stream)
8814 {
8815    Builder bld(ctx->program, ctx->block);
8816
8817    Temp so_buffers[4];
8818    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
8819    for (unsigned i = 0; i < 4; i++) {
8820       unsigned stride = ctx->program->info->so.strides[i];
8821       if (!stride)
8822          continue;
8823
8824       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
8825       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
8826    }
8827
8828    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
8829                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
8830
8831    Temp tid = emit_mbcnt(ctx, bld.def(v1));
8832
8833    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
8834
8835    if_context ic;
8836    begin_divergent_if_then(ctx, &ic, can_emit);
8837
8838    bld.reset(ctx->block);
8839
8840    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
8841
8842    Temp so_write_offset[4];
8843
8844    for (unsigned i = 0; i < 4; i++) {
8845       unsigned stride = ctx->program->info->so.strides[i];
8846       if (!stride)
8847          continue;
8848
8849       if (stride == 1) {
8850          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
8851                                 get_arg(ctx, ctx->args->streamout_write_idx),
8852                                 get_arg(ctx, ctx->args->streamout_offset[i]));
8853          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
8854
8855          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
8856       } else {
8857          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
8858          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
8859                                  get_arg(ctx, ctx->args->streamout_offset[i]));
8860          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
8861       }
8862    }
8863
8864    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
8865       struct radv_stream_output *output =
8866          &ctx->program->info->so.outputs[i];
8867       if (stream != output->stream)
8868          continue;
8869
8870       emit_stream_output(ctx, so_buffers, so_write_offset, output);
8871    }
8872
8873    begin_divergent_if_else(ctx, &ic);
8874    end_divergent_if(ctx, &ic);
8875 }
8876
8877 } /* end namespace */
8878
8879 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
8880 {
8881    /* Split all arguments except for the first (ring_offsets) and the last
8882     * (exec) so that the dead channels don't stay live throughout the program.
8883     */
8884    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
8885       if (startpgm->definitions[i].regClass().size() > 1) {
8886          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
8887                            startpgm->definitions[i].regClass().size());
8888       }
8889    }
8890 }
8891
8892 void handle_bc_optimize(isel_context *ctx)
8893 {
8894    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
8895    Builder bld(ctx->program, ctx->block);
8896    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
8897    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
8898    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
8899    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
8900    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
8901    if (uses_center && uses_centroid) {
8902       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
8903                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
8904
8905       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
8906          Temp new_coord[2];
8907          for (unsigned i = 0; i < 2; i++) {
8908             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
8909             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
8910             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8911                                     persp_centroid, persp_center, sel);
8912          }
8913          ctx->persp_centroid = bld.tmp(v2);
8914          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
8915                     Operand(new_coord[0]), Operand(new_coord[1]));
8916          emit_split_vector(ctx, ctx->persp_centroid, 2);
8917       }
8918
8919       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
8920          Temp new_coord[2];
8921          for (unsigned i = 0; i < 2; i++) {
8922             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
8923             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
8924             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8925                                     linear_centroid, linear_center, sel);
8926          }
8927          ctx->linear_centroid = bld.tmp(v2);
8928          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
8929                     Operand(new_coord[0]), Operand(new_coord[1]));
8930          emit_split_vector(ctx, ctx->linear_centroid, 2);
8931       }
8932    }
8933 }
8934
8935 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
8936 {
8937    Program *program = ctx->program;
8938
8939    unsigned float_controls = shader->info.float_controls_execution_mode;
8940
8941    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
8942       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
8943    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
8944       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
8945                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
8946
8947    program->next_fp_mode.must_flush_denorms32 =
8948       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
8949    program->next_fp_mode.must_flush_denorms16_64 =
8950       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
8951                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
8952
8953    program->next_fp_mode.care_about_round32 =
8954       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
8955
8956    program->next_fp_mode.care_about_round16_64 =
8957       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
8958                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
8959
8960    /* default to preserving fp16 and fp64 denorms, since it's free */
8961    if (program->next_fp_mode.must_flush_denorms16_64)
8962       program->next_fp_mode.denorm16_64 = 0;
8963    else
8964       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
8965
8966    /* preserving fp32 denorms is expensive, so only do it if asked */
8967    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
8968       program->next_fp_mode.denorm32 = fp_denorm_keep;
8969    else
8970       program->next_fp_mode.denorm32 = 0;
8971
8972    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
8973       program->next_fp_mode.round32 = fp_round_tz;
8974    else
8975       program->next_fp_mode.round32 = fp_round_ne;
8976
8977    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
8978       program->next_fp_mode.round16_64 = fp_round_tz;
8979    else
8980       program->next_fp_mode.round16_64 = fp_round_ne;
8981
8982    ctx->block->fp_mode = program->next_fp_mode;
8983 }
8984
8985 void cleanup_cfg(Program *program)
8986 {
8987    /* create linear_succs/logical_succs */
8988    for (Block& BB : program->blocks) {
8989       for (unsigned idx : BB.linear_preds)
8990          program->blocks[idx].linear_succs.emplace_back(BB.index);
8991       for (unsigned idx : BB.logical_preds)
8992          program->blocks[idx].logical_succs.emplace_back(BB.index);
8993    }
8994 }
8995
8996 void select_program(Program *program,
8997                     unsigned shader_count,
8998                     struct nir_shader *const *shaders,
8999                     ac_shader_config* config,
9000                     struct radv_shader_args *args)
9001 {
9002    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9003
9004    for (unsigned i = 0; i < shader_count; i++) {
9005       nir_shader *nir = shaders[i];
9006       init_context(&ctx, nir);
9007
9008       setup_fp_mode(&ctx, nir);
9009
9010       if (!i) {
9011          /* needs to be after init_context() for FS */
9012          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9013          append_logical_start(ctx.block);
9014          split_arguments(&ctx, startpgm);
9015       }
9016
9017       if_context ic;
9018       if (shader_count >= 2) {
9019          Builder bld(ctx.program, ctx.block);
9020          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9021          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9022          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9023
9024          begin_divergent_if_then(&ctx, &ic, cond);
9025       }
9026
9027       if (i) {
9028          Builder bld(ctx.program, ctx.block);
9029
9030          bld.barrier(aco_opcode::p_memory_barrier_shared);
9031          bld.sopp(aco_opcode::s_barrier);
9032
9033          if (ctx.stage == vertex_geometry_gs) {
9034             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9035          }
9036       } else if (ctx.stage == geometry_gs)
9037          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9038
9039       if (ctx.stage == fragment_fs)
9040          handle_bc_optimize(&ctx);
9041
9042       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9043       visit_cf_list(&ctx, &func->body);
9044
9045       if (ctx.program->info->so.num_outputs && ctx.stage == vertex_vs)
9046          emit_streamout(&ctx, 0);
9047
9048       if (ctx.stage == vertex_vs) {
9049          create_vs_exports(&ctx);
9050       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9051          Builder bld(ctx.program, ctx.block);
9052          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9053          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9054       }
9055
9056       if (ctx.stage == fragment_fs)
9057          create_fs_exports(&ctx);
9058
9059       if (shader_count >= 2) {
9060          begin_divergent_if_else(&ctx, &ic);
9061          end_divergent_if(&ctx, &ic);
9062       }
9063
9064       ralloc_free(ctx.divergent_vals);
9065    }
9066
9067    program->config->float_mode = program->blocks[0].fp_mode.val;
9068
9069    append_logical_end(ctx.block);
9070    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9071    Builder bld(ctx.program, ctx.block);
9072    if (ctx.program->wb_smem_l1_on_end)
9073       bld.smem(aco_opcode::s_dcache_wb, false);
9074    bld.sopp(aco_opcode::s_endpgm);
9075
9076    cleanup_cfg(program);
9077 }
9078
9079 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9080                            ac_shader_config* config,
9081                            struct radv_shader_args *args)
9082 {
9083    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9084
9085    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9086    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9087    program->next_fp_mode.must_flush_denorms32 = false;
9088    program->next_fp_mode.must_flush_denorms16_64 = false;
9089    program->next_fp_mode.care_about_round32 = false;
9090    program->next_fp_mode.care_about_round16_64 = false;
9091    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9092    program->next_fp_mode.denorm32 = 0;
9093    program->next_fp_mode.round32 = fp_round_ne;
9094    program->next_fp_mode.round16_64 = fp_round_ne;
9095    ctx.block->fp_mode = program->next_fp_mode;
9096
9097    add_startpgm(&ctx);
9098    append_logical_start(ctx.block);
9099
9100    Builder bld(ctx.program, ctx.block);
9101
9102    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9103
9104    Operand stream_id(0u);
9105    if (args->shader_info->so.num_outputs)
9106       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9107                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9108
9109    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9110
9111    std::stack<Block> endif_blocks;
9112
9113    for (unsigned stream = 0; stream < 4; stream++) {
9114       if (stream_id.isConstant() && stream != stream_id.constantValue())
9115          continue;
9116
9117       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9118       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9119          continue;
9120
9121       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9122
9123       unsigned BB_if_idx = ctx.block->index;
9124       Block BB_endif = Block();
9125       if (!stream_id.isConstant()) {
9126          /* begin IF */
9127          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9128          append_logical_end(ctx.block);
9129          ctx.block->kind |= block_kind_uniform;
9130          bld.branch(aco_opcode::p_cbranch_z, cond);
9131
9132          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9133
9134          ctx.block = ctx.program->create_and_insert_block();
9135          add_edge(BB_if_idx, ctx.block);
9136          bld.reset(ctx.block);
9137          append_logical_start(ctx.block);
9138       }
9139
9140       unsigned offset = 0;
9141       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9142          if (args->shader_info->gs.output_streams[i] != stream)
9143             continue;
9144
9145          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9146          unsigned length = util_last_bit(output_usage_mask);
9147          for (unsigned j = 0; j < length; ++j) {
9148             if (!(output_usage_mask & (1 << j)))
9149                continue;
9150
9151             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9152             Temp voffset = vtx_offset;
9153             if (const_offset >= 4096u) {
9154                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9155                const_offset %= 4096u;
9156             }
9157
9158             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9159             mubuf->definitions[0] = bld.def(v1);
9160             mubuf->operands[0] = Operand(gsvs_ring);
9161             mubuf->operands[1] = Operand(voffset);
9162             mubuf->operands[2] = Operand(0u);
9163             mubuf->offen = true;
9164             mubuf->offset = const_offset;
9165             mubuf->glc = true;
9166             mubuf->slc = true;
9167             mubuf->dlc = args->options->chip_class >= GFX10;
9168             mubuf->barrier = barrier_none;
9169             mubuf->can_reorder = true;
9170
9171             ctx.outputs.mask[i] |= 1 << j;
9172             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9173
9174             bld.insert(std::move(mubuf));
9175
9176             offset++;
9177          }
9178       }
9179
9180       if (args->shader_info->so.num_outputs) {
9181          emit_streamout(&ctx, stream);
9182          bld.reset(ctx.block);
9183       }
9184
9185       if (stream == 0) {
9186          create_vs_exports(&ctx);
9187          ctx.block->kind |= block_kind_export_end;
9188       }
9189
9190       if (!stream_id.isConstant()) {
9191          append_logical_end(ctx.block);
9192
9193          /* branch from then block to endif block */
9194          bld.branch(aco_opcode::p_branch);
9195          add_edge(ctx.block->index, &BB_endif);
9196          ctx.block->kind |= block_kind_uniform;
9197
9198          /* emit else block */
9199          ctx.block = ctx.program->create_and_insert_block();
9200          add_edge(BB_if_idx, ctx.block);
9201          bld.reset(ctx.block);
9202          append_logical_start(ctx.block);
9203
9204          endif_blocks.push(std::move(BB_endif));
9205       }
9206    }
9207
9208    while (!endif_blocks.empty()) {
9209       Block BB_endif = std::move(endif_blocks.top());
9210       endif_blocks.pop();
9211
9212       Block *BB_else = ctx.block;
9213
9214       append_logical_end(BB_else);
9215       /* branch from else block to endif block */
9216       bld.branch(aco_opcode::p_branch);
9217       add_edge(BB_else->index, &BB_endif);
9218       BB_else->kind |= block_kind_uniform;
9219
9220       /** emit endif merge block */
9221       ctx.block = program->insert_block(std::move(BB_endif));
9222       bld.reset(ctx.block);
9223       append_logical_start(ctx.block);
9224    }
9225
9226    program->config->float_mode = program->blocks[0].fp_mode.val;
9227
9228    append_logical_end(ctx.block);
9229    ctx.block->kind |= block_kind_uniform;
9230    bld.sopp(aco_opcode::s_endpgm);
9231
9232    cleanup_cfg(program);
9233 }
9234 }