src/amd/compiler/aco_instruction_selection.cpp

   1 /*
   2  * Copyright © 2018 Valve Corporation
   3  * Copyright © 2018 Google
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <algorithm>
  27 #include <array>
  28 #include <stack>
  29 #include <map>
  30
  31 #include "ac_shader_util.h"
  32 #include "aco_ir.h"
  33 #include "aco_builder.h"
  34 #include "aco_interface.h"
  35 #include "aco_instruction_selection_setup.cpp"
  36 #include "util/fast_idiv_by_const.h"
  37
  38 namespace aco {
  39 namespace {
  40
  41 class loop_info_RAII {
  42    isel_context* ctx;
  43    unsigned header_idx_old;
  44    Block* exit_old;
  45    bool divergent_cont_old;
  46    bool divergent_branch_old;
  47    bool divergent_if_old;
  48
  49 public:
  50    loop_info_RAII(isel_context* ctx, unsigned loop_header_idx, Block* loop_exit)
  51       : ctx(ctx),
  52         header_idx_old(ctx->cf_info.parent_loop.header_idx), exit_old(ctx->cf_info.parent_loop.exit),
  53         divergent_cont_old(ctx->cf_info.parent_loop.has_divergent_continue),
  54         divergent_branch_old(ctx->cf_info.parent_loop.has_divergent_branch),
  55         divergent_if_old(ctx->cf_info.parent_if.is_divergent)
  56    {
  57       ctx->cf_info.parent_loop.header_idx = loop_header_idx;
  58       ctx->cf_info.parent_loop.exit = loop_exit;
  59       ctx->cf_info.parent_loop.has_divergent_continue = false;
  60       ctx->cf_info.parent_loop.has_divergent_branch = false;
  61       ctx->cf_info.parent_if.is_divergent = false;
  62       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
  63    }
  64
  65    ~loop_info_RAII()
  66    {
  67       ctx->cf_info.parent_loop.header_idx = header_idx_old;
  68       ctx->cf_info.parent_loop.exit = exit_old;
  69       ctx->cf_info.parent_loop.has_divergent_continue = divergent_cont_old;
  70       ctx->cf_info.parent_loop.has_divergent_branch = divergent_branch_old;
  71       ctx->cf_info.parent_if.is_divergent = divergent_if_old;
  72       ctx->cf_info.loop_nest_depth = ctx->cf_info.loop_nest_depth - 1;
  73       if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent)
  74          ctx->cf_info.exec_potentially_empty_discard = false;
  75    }
  76 };
  77
  78 struct if_context {
  79    Temp cond;
  80
  81    bool divergent_old;
  82    bool exec_potentially_empty_discard_old;
  83    bool exec_potentially_empty_break_old;
  84    uint16_t exec_potentially_empty_break_depth_old;
  85
  86    unsigned BB_if_idx;
  87    unsigned invert_idx;
  88    bool then_branch_divergent;
  89    Block BB_invert;
  90    Block BB_endif;
  91 };
  92
  93 static bool visit_cf_list(struct isel_context *ctx,
  94                           struct exec_list *list);
  95
  96 static void add_logical_edge(unsigned pred_idx, Block *succ)
  97 {
  98    succ->logical_preds.emplace_back(pred_idx);
  99 }
 100
 101
 102 static void add_linear_edge(unsigned pred_idx, Block *succ)
 103 {
 104    succ->linear_preds.emplace_back(pred_idx);
 105 }
 106
 107 static void add_edge(unsigned pred_idx, Block *succ)
 108 {
 109    add_logical_edge(pred_idx, succ);
 110    add_linear_edge(pred_idx, succ);
 111 }
 112
 113 static void append_logical_start(Block *b)
 114 {
 115    Builder(NULL, b).pseudo(aco_opcode::p_logical_start);
 116 }
 117
 118 static void append_logical_end(Block *b)
 119 {
 120    Builder(NULL, b).pseudo(aco_opcode::p_logical_end);
 121 }
 122
 123 Temp get_ssa_temp(struct isel_context *ctx, nir_ssa_def *def)
 124 {
 125    assert(ctx->allocated[def->index].id());
 126    return ctx->allocated[def->index];
 127 }
 128
 129 Temp emit_mbcnt(isel_context *ctx, Definition dst,
 130                 Operand mask_lo = Operand((uint32_t) -1), Operand mask_hi = Operand((uint32_t) -1))
 131 {
 132    Builder bld(ctx->program, ctx->block);
 133    Definition lo_def = ctx->program->wave_size == 32 ? dst : bld.def(v1);
 134    Temp thread_id_lo = bld.vop3(aco_opcode::v_mbcnt_lo_u32_b32, lo_def, mask_lo, Operand(0u));
 135
 136    if (ctx->program->wave_size == 32) {
 137       return thread_id_lo;
 138    } else {
 139       Temp thread_id_hi = bld.vop3(aco_opcode::v_mbcnt_hi_u32_b32, dst, mask_hi, thread_id_lo);
 140       return thread_id_hi;
 141    }
 142 }
 143
 144 Temp emit_wqm(isel_context *ctx, Temp src, Temp dst=Temp(0, s1), bool program_needs_wqm = false)
 145 {
 146    Builder bld(ctx->program, ctx->block);
 147
 148    if (!dst.id())
 149       dst = bld.tmp(src.regClass());
 150
 151    assert(src.size() == dst.size());
 152
 153    if (ctx->stage != fragment_fs) {
 154       if (!dst.id())
 155          return src;
 156
 157       bld.copy(Definition(dst), src);
 158       return dst;
 159    }
 160
 161    bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
 162    ctx->program->needs_wqm |= program_needs_wqm;
 163    return dst;
 164 }
 165
 166 static Temp emit_bpermute(isel_context *ctx, Builder &bld, Temp index, Temp data)
 167 {
 168    if (index.regClass() == s1)
 169       return bld.readlane(bld.def(s1), data, index);
 170
 171    Temp index_x4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), index);
 172
 173    /* Currently not implemented on GFX6-7 */
 174    assert(ctx->options->chip_class >= GFX8);
 175
 176    if (ctx->options->chip_class <= GFX9 || ctx->program->wave_size == 32) {
 177       return bld.ds(aco_opcode::ds_bpermute_b32, bld.def(v1), index_x4, data);
 178    }
 179
 180    /* GFX10, wave64 mode:
 181     * The bpermute instruction is limited to half-wave operation, which means that it can't
 182     * properly support subgroup shuffle like older generations (or wave32 mode), so we
 183     * emulate it here.
 184     */
 185    if (!ctx->has_gfx10_wave64_bpermute) {
 186       ctx->has_gfx10_wave64_bpermute = true;
 187       ctx->program->config->num_shared_vgprs = 8; /* Shared VGPRs are allocated in groups of 8 */
 188       ctx->program->vgpr_limit -= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
 189    }
 190
 191    Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
 192    Temp lane_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), lane_id);
 193    Temp index_is_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x20u), index);
 194    Temp cmp = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm, vcc), lane_is_hi, index_is_hi);
 195
 196    return bld.reduction(aco_opcode::p_wave64_bpermute, bld.def(v1), bld.def(s2), bld.def(s1, scc),
 197                         bld.vcc(cmp), Operand(v2.as_linear()), index_x4, data, gfx10_wave64_bpermute);
 198 }
 199
 200 Temp as_vgpr(isel_context *ctx, Temp val)
 201 {
 202    if (val.type() == RegType::sgpr) {
 203       Builder bld(ctx->program, ctx->block);
 204       return bld.copy(bld.def(RegType::vgpr, val.size()), val);
 205    }
 206    assert(val.type() == RegType::vgpr);
 207    return val;
 208 }
 209
 210 //assumes a != 0xffffffff
 211 void emit_v_div_u32(isel_context *ctx, Temp dst, Temp a, uint32_t b)
 212 {
 213    assert(b != 0);
 214    Builder bld(ctx->program, ctx->block);
 215
 216    if (util_is_power_of_two_or_zero(b)) {
 217       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)util_logbase2(b)), a);
 218       return;
 219    }
 220
 221    util_fast_udiv_info info = util_compute_fast_udiv_info(b, 32, 32);
 222
 223    assert(info.multiplier <= 0xffffffff);
 224
 225    bool pre_shift = info.pre_shift != 0;
 226    bool increment = info.increment != 0;
 227    bool multiply = true;
 228    bool post_shift = info.post_shift != 0;
 229
 230    if (!pre_shift && !increment && !multiply && !post_shift) {
 231       bld.vop1(aco_opcode::v_mov_b32, Definition(dst), a);
 232       return;
 233    }
 234
 235    Temp pre_shift_dst = a;
 236    if (pre_shift) {
 237       pre_shift_dst = (increment || multiply || post_shift) ? bld.tmp(v1) : dst;
 238       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(pre_shift_dst), Operand((uint32_t)info.pre_shift), a);
 239    }
 240
 241    Temp increment_dst = pre_shift_dst;
 242    if (increment) {
 243       increment_dst = (post_shift || multiply) ? bld.tmp(v1) : dst;
 244       bld.vadd32(Definition(increment_dst), Operand((uint32_t) info.increment), pre_shift_dst);
 245    }
 246
 247    Temp multiply_dst = increment_dst;
 248    if (multiply) {
 249       multiply_dst = post_shift ? bld.tmp(v1) : dst;
 250       bld.vop3(aco_opcode::v_mul_hi_u32, Definition(multiply_dst), increment_dst,
 251                bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand((uint32_t)info.multiplier)));
 252    }
 253
 254    if (post_shift) {
 255       bld.vop2(aco_opcode::v_lshrrev_b32, Definition(dst), Operand((uint32_t)info.post_shift), multiply_dst);
 256    }
 257 }
 258
 259 void emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, Temp dst)
 260 {
 261    Builder bld(ctx->program, ctx->block);
 262    bld.pseudo(aco_opcode::p_extract_vector, Definition(dst), src, Operand(idx));
 263 }
 264
 265
 266 Temp emit_extract_vector(isel_context* ctx, Temp src, uint32_t idx, RegClass dst_rc)
 267 {
 268    /* no need to extract the whole vector */
 269    if (src.regClass() == dst_rc) {
 270       assert(idx == 0);
 271       return src;
 272    }
 273    assert(src.size() > idx);
 274    Builder bld(ctx->program, ctx->block);
 275    auto it = ctx->allocated_vec.find(src.id());
 276    /* the size check needs to be early because elements other than 0 may be garbage */
 277    if (it != ctx->allocated_vec.end() && it->second[0].size() == dst_rc.size()) {
 278       if (it->second[idx].regClass() == dst_rc) {
 279          return it->second[idx];
 280       } else {
 281          assert(dst_rc.size() == it->second[idx].regClass().size());
 282          assert(dst_rc.type() == RegType::vgpr && it->second[idx].type() == RegType::sgpr);
 283          return bld.copy(bld.def(dst_rc), it->second[idx]);
 284       }
 285    }
 286
 287    if (src.size() == dst_rc.size()) {
 288       assert(idx == 0);
 289       return bld.copy(bld.def(dst_rc), src);
 290    } else {
 291       Temp dst = bld.tmp(dst_rc);
 292       emit_extract_vector(ctx, src, idx, dst);
 293       return dst;
 294    }
 295 }
 296
 297 void emit_split_vector(isel_context* ctx, Temp vec_src, unsigned num_components)
 298 {
 299    if (num_components == 1)
 300       return;
 301    if (ctx->allocated_vec.find(vec_src.id()) != ctx->allocated_vec.end())
 302       return;
 303    aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_components)};
 304    split->operands[0] = Operand(vec_src);
 305    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 306    for (unsigned i = 0; i < num_components; i++) {
 307       elems[i] = {ctx->program->allocateId(), RegClass(vec_src.type(), vec_src.size() / num_components)};
 308       split->definitions[i] = Definition(elems[i]);
 309    }
 310    ctx->block->instructions.emplace_back(std::move(split));
 311    ctx->allocated_vec.emplace(vec_src.id(), elems);
 312 }
 313
 314 /* This vector expansion uses a mask to determine which elements in the new vector
 315  * come from the original vector. The other elements are undefined. */
 316 void expand_vector(isel_context* ctx, Temp vec_src, Temp dst, unsigned num_components, unsigned mask)
 317 {
 318    emit_split_vector(ctx, vec_src, util_bitcount(mask));
 319
 320    if (vec_src == dst)
 321       return;
 322
 323    Builder bld(ctx->program, ctx->block);
 324    if (num_components == 1) {
 325       if (dst.type() == RegType::sgpr)
 326          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec_src);
 327       else
 328          bld.copy(Definition(dst), vec_src);
 329       return;
 330    }
 331
 332    unsigned component_size = dst.size() / num_components;
 333    std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 334
 335    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
 336    vec->definitions[0] = Definition(dst);
 337    unsigned k = 0;
 338    for (unsigned i = 0; i < num_components; i++) {
 339       if (mask & (1 << i)) {
 340          Temp src = emit_extract_vector(ctx, vec_src, k++, RegClass(vec_src.type(), component_size));
 341          if (dst.type() == RegType::sgpr)
 342             src = bld.as_uniform(src);
 343          vec->operands[i] = Operand(src);
 344       } else {
 345          vec->operands[i] = Operand(0u);
 346       }
 347       elems[i] = vec->operands[i].getTemp();
 348    }
 349    ctx->block->instructions.emplace_back(std::move(vec));
 350    ctx->allocated_vec.emplace(dst.id(), elems);
 351 }
 352
 353 Temp bool_to_vector_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s2))
 354 {
 355    Builder bld(ctx->program, ctx->block);
 356    if (!dst.id())
 357       dst = bld.tmp(bld.lm);
 358
 359    assert(val.regClass() == s1);
 360    assert(dst.regClass() == bld.lm);
 361
 362    return bld.sop2(Builder::s_cselect, Definition(dst), Operand((uint32_t) -1), Operand(0u), bld.scc(val));
 363 }
 364
 365 Temp bool_to_scalar_condition(isel_context *ctx, Temp val, Temp dst = Temp(0, s1))
 366 {
 367    Builder bld(ctx->program, ctx->block);
 368    if (!dst.id())
 369       dst = bld.tmp(s1);
 370
 371    assert(val.regClass() == bld.lm);
 372    assert(dst.regClass() == s1);
 373
 374    /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
 375    Temp tmp = bld.tmp(s1);
 376    bld.sop2(Builder::s_and, bld.def(bld.lm), bld.scc(Definition(tmp)), val, Operand(exec, bld.lm));
 377    return emit_wqm(ctx, tmp, dst);
 378 }
 379
 380 Temp get_alu_src(struct isel_context *ctx, nir_alu_src src, unsigned size=1)
 381 {
 382    if (src.src.ssa->num_components == 1 && src.swizzle[0] == 0 && size == 1)
 383       return get_ssa_temp(ctx, src.src.ssa);
 384
 385    if (src.src.ssa->num_components == size) {
 386       bool identity_swizzle = true;
 387       for (unsigned i = 0; identity_swizzle && i < size; i++) {
 388          if (src.swizzle[i] != i)
 389             identity_swizzle = false;
 390       }
 391       if (identity_swizzle)
 392          return get_ssa_temp(ctx, src.src.ssa);
 393    }
 394
 395    Temp vec = get_ssa_temp(ctx, src.src.ssa);
 396    unsigned elem_size = vec.size() / src.src.ssa->num_components;
 397    assert(elem_size > 0); /* TODO: 8 and 16-bit vectors not supported */
 398    assert(vec.size() % elem_size == 0);
 399
 400    RegClass elem_rc = RegClass(vec.type(), elem_size);
 401    if (size == 1) {
 402       return emit_extract_vector(ctx, vec, src.swizzle[0], elem_rc);
 403    } else {
 404       assert(size <= 4);
 405       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 406       aco_ptr<Pseudo_instruction> vec_instr{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
 407       for (unsigned i = 0; i < size; ++i) {
 408          elems[i] = emit_extract_vector(ctx, vec, src.swizzle[i], elem_rc);
 409          vec_instr->operands[i] = Operand{elems[i]};
 410       }
 411       Temp dst{ctx->program->allocateId(), RegClass(vec.type(), elem_size * size)};
 412       vec_instr->definitions[0] = Definition(dst);
 413       ctx->block->instructions.emplace_back(std::move(vec_instr));
 414       ctx->allocated_vec.emplace(dst.id(), elems);
 415       return dst;
 416    }
 417 }
 418
 419 Temp convert_pointer_to_64_bit(isel_context *ctx, Temp ptr)
 420 {
 421    if (ptr.size() == 2)
 422       return ptr;
 423    Builder bld(ctx->program, ctx->block);
 424    if (ptr.type() == RegType::vgpr)
 425       ptr = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), ptr);
 426    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s2),
 427                      ptr, Operand((unsigned)ctx->options->address32_hi));
 428 }
 429
 430 void emit_sop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst, bool writes_scc)
 431 {
 432    aco_ptr<SOP2_instruction> sop2{create_instruction<SOP2_instruction>(op, Format::SOP2, 2, writes_scc ? 2 : 1)};
 433    sop2->operands[0] = Operand(get_alu_src(ctx, instr->src[0]));
 434    sop2->operands[1] = Operand(get_alu_src(ctx, instr->src[1]));
 435    sop2->definitions[0] = Definition(dst);
 436    if (writes_scc)
 437       sop2->definitions[1] = Definition(ctx->program->allocateId(), scc, s1);
 438    ctx->block->instructions.emplace_back(std::move(sop2));
 439 }
 440
 441 void emit_vop2_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 442                            bool commutative, bool swap_srcs=false, bool flush_denorms = false)
 443 {
 444    Builder bld(ctx->program, ctx->block);
 445    Temp src0 = get_alu_src(ctx, instr->src[swap_srcs ? 1 : 0]);
 446    Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
 447    if (src1.type() == RegType::sgpr) {
 448       if (commutative && src0.type() == RegType::vgpr) {
 449          Temp t = src0;
 450          src0 = src1;
 451          src1 = t;
 452       } else if (src0.type() == RegType::vgpr &&
 453                  op != aco_opcode::v_madmk_f32 &&
 454                  op != aco_opcode::v_madak_f32 &&
 455                  op != aco_opcode::v_madmk_f16 &&
 456                  op != aco_opcode::v_madak_f16) {
 457          /* If the instruction is not commutative, we emit a VOP3A instruction */
 458          bld.vop2_e64(op, Definition(dst), src0, src1);
 459          return;
 460       } else {
 461          src1 = bld.copy(bld.def(RegType::vgpr, src1.size()), src1); //TODO: as_vgpr
 462       }
 463    }
 464
 465    if (flush_denorms && ctx->program->chip_class < GFX9) {
 466       assert(dst.size() == 1);
 467       Temp tmp = bld.vop2(op, bld.def(v1), src0, src1);
 468       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 469    } else {
 470       bld.vop2(op, Definition(dst), src0, src1);
 471    }
 472 }
 473
 474 void emit_vop3a_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst,
 475                             bool flush_denorms = false)
 476 {
 477    Temp src0 = get_alu_src(ctx, instr->src[0]);
 478    Temp src1 = get_alu_src(ctx, instr->src[1]);
 479    Temp src2 = get_alu_src(ctx, instr->src[2]);
 480
 481    /* ensure that the instruction has at most 1 sgpr operand
 482     * The optimizer will inline constants for us */
 483    if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr)
 484       src0 = as_vgpr(ctx, src0);
 485    if (src1.type() == RegType::sgpr && src2.type() == RegType::sgpr)
 486       src1 = as_vgpr(ctx, src1);
 487    if (src2.type() == RegType::sgpr && src0.type() == RegType::sgpr)
 488       src2 = as_vgpr(ctx, src2);
 489
 490    Builder bld(ctx->program, ctx->block);
 491    if (flush_denorms && ctx->program->chip_class < GFX9) {
 492       assert(dst.size() == 1);
 493       Temp tmp = bld.vop3(op, Definition(dst), src0, src1, src2);
 494       bld.vop2(aco_opcode::v_mul_f32, Definition(dst), Operand(0x3f800000u), tmp);
 495    } else {
 496       bld.vop3(op, Definition(dst), src0, src1, src2);
 497    }
 498 }
 499
 500 void emit_vop1_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 501 {
 502    Builder bld(ctx->program, ctx->block);
 503    bld.vop1(op, Definition(dst), get_alu_src(ctx, instr->src[0]));
 504 }
 505
 506 void emit_vopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 507 {
 508    Temp src0 = get_alu_src(ctx, instr->src[0]);
 509    Temp src1 = get_alu_src(ctx, instr->src[1]);
 510    assert(src0.size() == src1.size());
 511
 512    aco_ptr<Instruction> vopc;
 513    if (src1.type() == RegType::sgpr) {
 514       if (src0.type() == RegType::vgpr) {
 515          /* to swap the operands, we might also have to change the opcode */
 516          switch (op) {
 517             case aco_opcode::v_cmp_lt_f32:
 518                op = aco_opcode::v_cmp_gt_f32;
 519                break;
 520             case aco_opcode::v_cmp_ge_f32:
 521                op = aco_opcode::v_cmp_le_f32;
 522                break;
 523             case aco_opcode::v_cmp_lt_i32:
 524                op = aco_opcode::v_cmp_gt_i32;
 525                break;
 526             case aco_opcode::v_cmp_ge_i32:
 527                op = aco_opcode::v_cmp_le_i32;
 528                break;
 529             case aco_opcode::v_cmp_lt_u32:
 530                op = aco_opcode::v_cmp_gt_u32;
 531                break;
 532             case aco_opcode::v_cmp_ge_u32:
 533                op = aco_opcode::v_cmp_le_u32;
 534                break;
 535             case aco_opcode::v_cmp_lt_f64:
 536                op = aco_opcode::v_cmp_gt_f64;
 537                break;
 538             case aco_opcode::v_cmp_ge_f64:
 539                op = aco_opcode::v_cmp_le_f64;
 540                break;
 541             case aco_opcode::v_cmp_lt_i64:
 542                op = aco_opcode::v_cmp_gt_i64;
 543                break;
 544             case aco_opcode::v_cmp_ge_i64:
 545                op = aco_opcode::v_cmp_le_i64;
 546                break;
 547             case aco_opcode::v_cmp_lt_u64:
 548                op = aco_opcode::v_cmp_gt_u64;
 549                break;
 550             case aco_opcode::v_cmp_ge_u64:
 551                op = aco_opcode::v_cmp_le_u64;
 552                break;
 553             default: /* eq and ne are commutative */
 554                break;
 555          }
 556          Temp t = src0;
 557          src0 = src1;
 558          src1 = t;
 559       } else {
 560          src1 = as_vgpr(ctx, src1);
 561       }
 562    }
 563
 564    Builder bld(ctx->program, ctx->block);
 565    bld.vopc(op, bld.hint_vcc(Definition(dst)), src0, src1);
 566 }
 567
 568 void emit_sopc_instruction(isel_context *ctx, nir_alu_instr *instr, aco_opcode op, Temp dst)
 569 {
 570    Temp src0 = get_alu_src(ctx, instr->src[0]);
 571    Temp src1 = get_alu_src(ctx, instr->src[1]);
 572    Builder bld(ctx->program, ctx->block);
 573
 574    assert(dst.regClass() == bld.lm);
 575    assert(src0.type() == RegType::sgpr);
 576    assert(src1.type() == RegType::sgpr);
 577    assert(src0.regClass() == src1.regClass());
 578
 579    /* Emit the SALU comparison instruction */
 580    Temp cmp = bld.sopc(op, bld.scc(bld.def(s1)), src0, src1);
 581    /* Turn the result into a per-lane bool */
 582    bool_to_vector_condition(ctx, cmp, dst);
 583 }
 584
 585 void emit_comparison(isel_context *ctx, nir_alu_instr *instr, Temp dst,
 586                      aco_opcode v32_op, aco_opcode v64_op, aco_opcode s32_op = aco_opcode::num_opcodes, aco_opcode s64_op = aco_opcode::num_opcodes)
 587 {
 588    aco_opcode s_op = instr->src[0].src.ssa->bit_size == 64 ? s64_op : s32_op;
 589    aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : v32_op;
 590    bool divergent_vals = ctx->divergent_vals[instr->dest.dest.ssa.index];
 591    bool use_valu = s_op == aco_opcode::num_opcodes ||
 592                    divergent_vals ||
 593                    ctx->allocated[instr->src[0].src.ssa->index].type() == RegType::vgpr ||
 594                    ctx->allocated[instr->src[1].src.ssa->index].type() == RegType::vgpr;
 595    aco_opcode op = use_valu ? v_op : s_op;
 596    assert(op != aco_opcode::num_opcodes);
 597    assert(dst.regClass() == ctx->program->lane_mask);
 598
 599    if (use_valu)
 600       emit_vopc_instruction(ctx, instr, op, dst);
 601    else
 602       emit_sopc_instruction(ctx, instr, op, dst);
 603 }
 604
 605 void emit_boolean_logic(isel_context *ctx, nir_alu_instr *instr, Builder::WaveSpecificOpcode op, Temp dst)
 606 {
 607    Builder bld(ctx->program, ctx->block);
 608    Temp src0 = get_alu_src(ctx, instr->src[0]);
 609    Temp src1 = get_alu_src(ctx, instr->src[1]);
 610
 611    assert(dst.regClass() == bld.lm);
 612    assert(src0.regClass() == bld.lm);
 613    assert(src1.regClass() == bld.lm);
 614
 615    bld.sop2(op, Definition(dst), bld.def(s1, scc), src0, src1);
 616 }
 617
 618 void emit_bcsel(isel_context *ctx, nir_alu_instr *instr, Temp dst)
 619 {
 620    Builder bld(ctx->program, ctx->block);
 621    Temp cond = get_alu_src(ctx, instr->src[0]);
 622    Temp then = get_alu_src(ctx, instr->src[1]);
 623    Temp els = get_alu_src(ctx, instr->src[2]);
 624
 625    assert(cond.regClass() == bld.lm);
 626
 627    if (dst.type() == RegType::vgpr) {
 628       aco_ptr<Instruction> bcsel;
 629       if (dst.size() == 1) {
 630          then = as_vgpr(ctx, then);
 631          els = as_vgpr(ctx, els);
 632
 633          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), els, then, cond);
 634       } else if (dst.size() == 2) {
 635          Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 636          bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), then);
 637          Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 638          bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), els);
 639
 640          Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, cond);
 641          Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, cond);
 642
 643          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 644       } else {
 645          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 646          nir_print_instr(&instr->instr, stderr);
 647          fprintf(stderr, "\n");
 648       }
 649       return;
 650    }
 651
 652    if (instr->dest.dest.ssa.bit_size == 1) {
 653       assert(dst.regClass() == bld.lm);
 654       assert(then.regClass() == bld.lm);
 655       assert(els.regClass() == bld.lm);
 656    }
 657
 658    if (!ctx->divergent_vals[instr->src[0].src.ssa->index]) { /* uniform condition and values in sgpr */
 659       if (dst.regClass() == s1 || dst.regClass() == s2) {
 660          assert((then.regClass() == s1 || then.regClass() == s2) && els.regClass() == then.regClass());
 661          assert(dst.size() == then.size());
 662          aco_opcode op = dst.regClass() == s1 ? aco_opcode::s_cselect_b32 : aco_opcode::s_cselect_b64;
 663          bld.sop2(op, Definition(dst), then, els, bld.scc(bool_to_scalar_condition(ctx, cond)));
 664       } else {
 665          fprintf(stderr, "Unimplemented uniform bcsel bit size: ");
 666          nir_print_instr(&instr->instr, stderr);
 667          fprintf(stderr, "\n");
 668       }
 669       return;
 670    }
 671
 672    /* divergent boolean bcsel
 673     * this implements bcsel on bools: dst = s0 ? s1 : s2
 674     * are going to be: dst = (s0 & s1) | (~s0 & s2) */
 675    assert(instr->dest.dest.ssa.bit_size == 1);
 676
 677    if (cond.id() != then.id())
 678       then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then);
 679
 680    if (cond.id() == els.id())
 681       bld.sop1(Builder::s_mov, Definition(dst), then);
 682    else
 683       bld.sop2(Builder::s_or, Definition(dst), bld.def(s1, scc), then,
 684                bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), els, cond));
 685 }
 686
 687 void emit_scaled_op(isel_context *ctx, Builder& bld, Definition dst, Temp val,
 688                     aco_opcode op, uint32_t undo)
 689 {
 690    /* multiply by 16777216 to handle denormals */
 691    Temp is_denormal = bld.vopc(aco_opcode::v_cmp_class_f32, bld.hint_vcc(bld.def(bld.lm)),
 692                                as_vgpr(ctx, val), bld.copy(bld.def(v1), Operand((1u << 7) | (1u << 4))));
 693    Temp scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x4b800000u), val);
 694    scaled = bld.vop1(op, bld.def(v1), scaled);
 695    scaled = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(undo), scaled);
 696
 697    Temp not_scaled = bld.vop1(op, bld.def(v1), val);
 698
 699    bld.vop2(aco_opcode::v_cndmask_b32, dst, not_scaled, scaled, is_denormal);
 700 }
 701
 702 void emit_rcp(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 703 {
 704    if (ctx->block->fp_mode.denorm32 == 0) {
 705       bld.vop1(aco_opcode::v_rcp_f32, dst, val);
 706       return;
 707    }
 708
 709    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rcp_f32, 0x4b800000u);
 710 }
 711
 712 void emit_rsq(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 713 {
 714    if (ctx->block->fp_mode.denorm32 == 0) {
 715       bld.vop1(aco_opcode::v_rsq_f32, dst, val);
 716       return;
 717    }
 718
 719    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_rsq_f32, 0x45800000u);
 720 }
 721
 722 void emit_sqrt(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 723 {
 724    if (ctx->block->fp_mode.denorm32 == 0) {
 725       bld.vop1(aco_opcode::v_sqrt_f32, dst, val);
 726       return;
 727    }
 728
 729    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_sqrt_f32, 0x39800000u);
 730 }
 731
 732 void emit_log2(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 733 {
 734    if (ctx->block->fp_mode.denorm32 == 0) {
 735       bld.vop1(aco_opcode::v_log_f32, dst, val);
 736       return;
 737    }
 738
 739    emit_scaled_op(ctx, bld, dst, val, aco_opcode::v_log_f32, 0xc1c00000u);
 740 }
 741
 742 Temp emit_trunc_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 743 {
 744    if (ctx->options->chip_class >= GFX7)
 745       return bld.vop1(aco_opcode::v_trunc_f64, Definition(dst), val);
 746
 747    /* GFX6 doesn't support V_TRUNC_F64, lower it. */
 748    /* TODO: create more efficient code! */
 749    if (val.type() == RegType::sgpr)
 750       val = as_vgpr(ctx, val);
 751
 752    /* Split the input value. */
 753    Temp val_lo = bld.tmp(v1), val_hi = bld.tmp(v1);
 754    bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
 755
 756    /* Extract the exponent and compute the unbiased value. */
 757    Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f64, bld.def(v1), val);
 758
 759    /* Extract the fractional part. */
 760    Temp fract_mask = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x000fffffu));
 761    fract_mask = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), fract_mask, exponent);
 762
 763    Temp fract_mask_lo = bld.tmp(v1), fract_mask_hi = bld.tmp(v1);
 764    bld.pseudo(aco_opcode::p_split_vector, Definition(fract_mask_lo), Definition(fract_mask_hi), fract_mask);
 765
 766    Temp fract_lo = bld.tmp(v1), fract_hi = bld.tmp(v1);
 767    Temp tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_lo);
 768    fract_lo = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_lo, tmp);
 769    tmp = bld.vop1(aco_opcode::v_not_b32, bld.def(v1), fract_mask_hi);
 770    fract_hi = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), val_hi, tmp);
 771
 772    /* Get the sign bit. */
 773    Temp sign = bld.vop2(aco_opcode::v_ashr_i32, bld.def(v1), Operand(31u), val_hi);
 774
 775    /* Decide the operation to apply depending on the unbiased exponent. */
 776    Temp exp_lt0 = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)), exponent, Operand(0u));
 777    Temp dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_lo, bld.copy(bld.def(v1), Operand(0u)), exp_lt0);
 778    Temp dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), fract_hi, sign, exp_lt0);
 779    Temp exp_gt51 = bld.vopc_e64(aco_opcode::v_cmp_gt_i32, bld.def(s2), exponent, Operand(51u));
 780    dst_lo = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_lo, val_lo, exp_gt51);
 781    dst_hi = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), dst_hi, val_hi, exp_gt51);
 782
 783    return bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst_lo, dst_hi);
 784 }
 785
 786 Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
 787 {
 788    if (ctx->options->chip_class >= GFX7)
 789       return bld.vop1(aco_opcode::v_floor_f64, Definition(dst), val);
 790
 791    /* GFX6 doesn't support V_FLOOR_F64, lower it. */
 792    Temp src0 = as_vgpr(ctx, val);
 793
 794    Temp mask = bld.copy(bld.def(s1), Operand(3u)); /* isnan */
 795    Temp min_val = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(-1u), Operand(0x3fefffffu));
 796
 797    Temp isnan = bld.vopc_e64(aco_opcode::v_cmp_class_f64, bld.hint_vcc(bld.def(bld.lm)), src0, mask);
 798    Temp fract = bld.vop1(aco_opcode::v_fract_f64, bld.def(v2), src0);
 799    Temp min = bld.vop3(aco_opcode::v_min_f64, bld.def(v2), fract, min_val);
 800
 801    Temp then_lo = bld.tmp(v1), then_hi = bld.tmp(v1);
 802    bld.pseudo(aco_opcode::p_split_vector, Definition(then_lo), Definition(then_hi), src0);
 803    Temp else_lo = bld.tmp(v1), else_hi = bld.tmp(v1);
 804    bld.pseudo(aco_opcode::p_split_vector, Definition(else_lo), Definition(else_hi), min);
 805
 806    Temp dst0 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_lo, then_lo, isnan);
 807    Temp dst1 = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), else_hi, then_hi, isnan);
 808
 809    Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
 810
 811    Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
 812    static_cast<VOP3A_instruction*>(add)->neg[1] = true;
 813
 814    return add->definitions[0].getTemp();
 815 }
 816
 817 void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
 818 {
 819    if (!instr->dest.dest.is_ssa) {
 820       fprintf(stderr, "nir alu dst not in ssa: ");
 821       nir_print_instr(&instr->instr, stderr);
 822       fprintf(stderr, "\n");
 823       abort();
 824    }
 825    Builder bld(ctx->program, ctx->block);
 826    Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa);
 827    switch(instr->op) {
 828    case nir_op_vec2:
 829    case nir_op_vec3:
 830    case nir_op_vec4: {
 831       std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
 832       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)};
 833       for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) {
 834          elems[i] = get_alu_src(ctx, instr->src[i]);
 835          vec->operands[i] = Operand{elems[i]};
 836       }
 837       vec->definitions[0] = Definition(dst);
 838       ctx->block->instructions.emplace_back(std::move(vec));
 839       ctx->allocated_vec.emplace(dst.id(), elems);
 840       break;
 841    }
 842    case nir_op_mov: {
 843       Temp src = get_alu_src(ctx, instr->src[0]);
 844       aco_ptr<Instruction> mov;
 845       if (dst.type() == RegType::sgpr) {
 846          if (src.type() == RegType::vgpr)
 847             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), src);
 848          else if (src.regClass() == s1)
 849             bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
 850          else if (src.regClass() == s2)
 851             bld.sop1(aco_opcode::s_mov_b64, Definition(dst), src);
 852          else
 853             unreachable("wrong src register class for nir_op_imov");
 854       } else if (dst.regClass() == v1) {
 855          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), src);
 856       } else if (dst.regClass() == v2) {
 857          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
 858       } else {
 859          nir_print_instr(&instr->instr, stderr);
 860          unreachable("Should have been lowered to scalar.");
 861       }
 862       break;
 863    }
 864    case nir_op_inot: {
 865       Temp src = get_alu_src(ctx, instr->src[0]);
 866       if (instr->dest.dest.ssa.bit_size == 1) {
 867          assert(src.regClass() == bld.lm);
 868          assert(dst.regClass() == bld.lm);
 869          /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
 870          Temp tmp = bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), src);
 871          bld.sop2(Builder::s_and, Definition(dst), bld.def(s1, scc), tmp, Operand(exec, bld.lm));
 872       } else if (dst.regClass() == v1) {
 873          emit_vop1_instruction(ctx, instr, aco_opcode::v_not_b32, dst);
 874       } else if (dst.type() == RegType::sgpr) {
 875          aco_opcode opcode = dst.size() == 1 ? aco_opcode::s_not_b32 : aco_opcode::s_not_b64;
 876          bld.sop1(opcode, Definition(dst), bld.def(s1, scc), src);
 877       } else {
 878          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 879          nir_print_instr(&instr->instr, stderr);
 880          fprintf(stderr, "\n");
 881       }
 882       break;
 883    }
 884    case nir_op_ineg: {
 885       Temp src = get_alu_src(ctx, instr->src[0]);
 886       if (dst.regClass() == v1) {
 887          bld.vsub32(Definition(dst), Operand(0u), Operand(src));
 888       } else if (dst.regClass() == s1) {
 889          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand((uint32_t) -1), src);
 890       } else if (dst.size() == 2) {
 891          Temp src0 = bld.tmp(dst.type(), 1);
 892          Temp src1 = bld.tmp(dst.type(), 1);
 893          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
 894
 895          if (dst.regClass() == s2) {
 896             Temp carry = bld.tmp(s1);
 897             Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), Operand(0u), src0);
 898             Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), src1, carry);
 899             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
 900          } else {
 901             Temp lower = bld.tmp(v1);
 902             Temp borrow = bld.vsub32(Definition(lower), Operand(0u), src0, true).def(1).getTemp();
 903             Temp upper = bld.vsub32(bld.def(v1), Operand(0u), src1, false, borrow);
 904             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 905          }
 906       } else {
 907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 908          nir_print_instr(&instr->instr, stderr);
 909          fprintf(stderr, "\n");
 910       }
 911       break;
 912    }
 913    case nir_op_iabs: {
 914       if (dst.regClass() == s1) {
 915          bld.sop1(aco_opcode::s_abs_i32, Definition(dst), bld.def(s1, scc), get_alu_src(ctx, instr->src[0]));
 916       } else if (dst.regClass() == v1) {
 917          Temp src = get_alu_src(ctx, instr->src[0]);
 918          bld.vop2(aco_opcode::v_max_i32, Definition(dst), src, bld.vsub32(bld.def(v1), Operand(0u), src));
 919       } else {
 920          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 921          nir_print_instr(&instr->instr, stderr);
 922          fprintf(stderr, "\n");
 923       }
 924       break;
 925    }
 926    case nir_op_isign: {
 927       Temp src = get_alu_src(ctx, instr->src[0]);
 928       if (dst.regClass() == s1) {
 929          Temp tmp = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
 930          Temp gtz = bld.sopc(aco_opcode::s_cmp_gt_i32, bld.def(s1, scc), src, Operand(0u));
 931          bld.sop2(aco_opcode::s_add_i32, Definition(dst), bld.def(s1, scc), gtz, tmp);
 932       } else if (dst.regClass() == s2) {
 933          Temp neg = bld.sop2(aco_opcode::s_ashr_i64, bld.def(s2), bld.def(s1, scc), src, Operand(63u));
 934          Temp neqz;
 935          if (ctx->program->chip_class >= GFX8)
 936             neqz = bld.sopc(aco_opcode::s_cmp_lg_u64, bld.def(s1, scc), src, Operand(0u));
 937          else
 938             neqz = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), src, Operand(0u)).def(1).getTemp();
 939          /* SCC gets zero-extended to 64 bit */
 940          bld.sop2(aco_opcode::s_or_b64, Definition(dst), bld.def(s1, scc), neg, bld.scc(neqz));
 941       } else if (dst.regClass() == v1) {
 942          Temp tmp = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
 943          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 944          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(1u), tmp, gtz);
 945       } else if (dst.regClass() == v2) {
 946          Temp upper = emit_extract_vector(ctx, src, 1, v1);
 947          Temp neg = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), upper);
 948          Temp gtz = bld.vopc(aco_opcode::v_cmp_ge_i64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
 949          Temp lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(1u), neg, gtz);
 950          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), neg, gtz);
 951          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
 952       } else {
 953          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 954          nir_print_instr(&instr->instr, stderr);
 955          fprintf(stderr, "\n");
 956       }
 957       break;
 958    }
 959    case nir_op_imax: {
 960       if (dst.regClass() == v1) {
 961          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true);
 962       } else if (dst.regClass() == s1) {
 963          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_i32, dst, true);
 964       } else {
 965          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 966          nir_print_instr(&instr->instr, stderr);
 967          fprintf(stderr, "\n");
 968       }
 969       break;
 970    }
 971    case nir_op_umax: {
 972       if (dst.regClass() == v1) {
 973          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true);
 974       } else if (dst.regClass() == s1) {
 975          emit_sop2_instruction(ctx, instr, aco_opcode::s_max_u32, dst, true);
 976       } else {
 977          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 978          nir_print_instr(&instr->instr, stderr);
 979          fprintf(stderr, "\n");
 980       }
 981       break;
 982    }
 983    case nir_op_imin: {
 984       if (dst.regClass() == v1) {
 985          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true);
 986       } else if (dst.regClass() == s1) {
 987          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_i32, dst, true);
 988       } else {
 989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
 990          nir_print_instr(&instr->instr, stderr);
 991          fprintf(stderr, "\n");
 992       }
 993       break;
 994    }
 995    case nir_op_umin: {
 996       if (dst.regClass() == v1) {
 997          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true);
 998       } else if (dst.regClass() == s1) {
 999          emit_sop2_instruction(ctx, instr, aco_opcode::s_min_u32, dst, true);
1000       } else {
1001          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1002          nir_print_instr(&instr->instr, stderr);
1003          fprintf(stderr, "\n");
1004       }
1005       break;
1006    }
1007    case nir_op_ior: {
1008       if (instr->dest.dest.ssa.bit_size == 1) {
1009          emit_boolean_logic(ctx, instr, Builder::s_or, dst);
1010       } else if (dst.regClass() == v1) {
1011          emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true);
1012       } else if (dst.regClass() == s1) {
1013          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b32, dst, true);
1014       } else if (dst.regClass() == s2) {
1015          emit_sop2_instruction(ctx, instr, aco_opcode::s_or_b64, dst, true);
1016       } else {
1017          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1018          nir_print_instr(&instr->instr, stderr);
1019          fprintf(stderr, "\n");
1020       }
1021       break;
1022    }
1023    case nir_op_iand: {
1024       if (instr->dest.dest.ssa.bit_size == 1) {
1025          emit_boolean_logic(ctx, instr, Builder::s_and, dst);
1026       } else if (dst.regClass() == v1) {
1027          emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true);
1028       } else if (dst.regClass() == s1) {
1029          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b32, dst, true);
1030       } else if (dst.regClass() == s2) {
1031          emit_sop2_instruction(ctx, instr, aco_opcode::s_and_b64, dst, true);
1032       } else {
1033          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1034          nir_print_instr(&instr->instr, stderr);
1035          fprintf(stderr, "\n");
1036       }
1037       break;
1038    }
1039    case nir_op_ixor: {
1040       if (instr->dest.dest.ssa.bit_size == 1) {
1041          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
1042       } else if (dst.regClass() == v1) {
1043          emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true);
1044       } else if (dst.regClass() == s1) {
1045          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b32, dst, true);
1046       } else if (dst.regClass() == s2) {
1047          emit_sop2_instruction(ctx, instr, aco_opcode::s_xor_b64, dst, true);
1048       } else {
1049          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1050          nir_print_instr(&instr->instr, stderr);
1051          fprintf(stderr, "\n");
1052       }
1053       break;
1054    }
1055    case nir_op_ushr: {
1056       if (dst.regClass() == v1) {
1057          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true);
1058       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1059          bld.vop3(aco_opcode::v_lshrrev_b64, Definition(dst),
1060                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1061       } else if (dst.regClass() == v2) {
1062          bld.vop3(aco_opcode::v_lshr_b64, Definition(dst),
1063                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1064       } else if (dst.regClass() == s2) {
1065          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b64, dst, true);
1066       } else if (dst.regClass() == s1) {
1067          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshr_b32, dst, true);
1068       } else {
1069          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1070          nir_print_instr(&instr->instr, stderr);
1071          fprintf(stderr, "\n");
1072       }
1073       break;
1074    }
1075    case nir_op_ishl: {
1076       if (dst.regClass() == v1) {
1077          emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true);
1078       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1079          bld.vop3(aco_opcode::v_lshlrev_b64, Definition(dst),
1080                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1081       } else if (dst.regClass() == v2) {
1082          bld.vop3(aco_opcode::v_lshl_b64, Definition(dst),
1083                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1084       } else if (dst.regClass() == s1) {
1085          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b32, dst, true);
1086       } else if (dst.regClass() == s2) {
1087          emit_sop2_instruction(ctx, instr, aco_opcode::s_lshl_b64, dst, true);
1088       } else {
1089          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1090          nir_print_instr(&instr->instr, stderr);
1091          fprintf(stderr, "\n");
1092       }
1093       break;
1094    }
1095    case nir_op_ishr: {
1096       if (dst.regClass() == v1) {
1097          emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true);
1098       } else if (dst.regClass() == v2 && ctx->program->chip_class >= GFX8) {
1099          bld.vop3(aco_opcode::v_ashrrev_i64, Definition(dst),
1100                   get_alu_src(ctx, instr->src[1]), get_alu_src(ctx, instr->src[0]));
1101       } else if (dst.regClass() == v2) {
1102          bld.vop3(aco_opcode::v_ashr_i64, Definition(dst),
1103                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1104       } else if (dst.regClass() == s1) {
1105          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i32, dst, true);
1106       } else if (dst.regClass() == s2) {
1107          emit_sop2_instruction(ctx, instr, aco_opcode::s_ashr_i64, dst, true);
1108       } else {
1109          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1110          nir_print_instr(&instr->instr, stderr);
1111          fprintf(stderr, "\n");
1112       }
1113       break;
1114    }
1115    case nir_op_find_lsb: {
1116       Temp src = get_alu_src(ctx, instr->src[0]);
1117       if (src.regClass() == s1) {
1118          bld.sop1(aco_opcode::s_ff1_i32_b32, Definition(dst), src);
1119       } else if (src.regClass() == v1) {
1120          emit_vop1_instruction(ctx, instr, aco_opcode::v_ffbl_b32, dst);
1121       } else if (src.regClass() == s2) {
1122          bld.sop1(aco_opcode::s_ff1_i32_b64, Definition(dst), src);
1123       } else {
1124          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1125          nir_print_instr(&instr->instr, stderr);
1126          fprintf(stderr, "\n");
1127       }
1128       break;
1129    }
1130    case nir_op_ufind_msb:
1131    case nir_op_ifind_msb: {
1132       Temp src = get_alu_src(ctx, instr->src[0]);
1133       if (src.regClass() == s1 || src.regClass() == s2) {
1134          aco_opcode op = src.regClass() == s2 ?
1135                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b64 : aco_opcode::s_flbit_i32_i64) :
1136                          (instr->op == nir_op_ufind_msb ? aco_opcode::s_flbit_i32_b32 : aco_opcode::s_flbit_i32);
1137          Temp msb_rev = bld.sop1(op, bld.def(s1), src);
1138
1139          Builder::Result sub = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc),
1140                                         Operand(src.size() * 32u - 1u), msb_rev);
1141          Temp msb = sub.def(0).getTemp();
1142          Temp carry = sub.def(1).getTemp();
1143
1144          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t)-1), msb, bld.scc(carry));
1145       } else if (src.regClass() == v1) {
1146          aco_opcode op = instr->op == nir_op_ufind_msb ? aco_opcode::v_ffbh_u32 : aco_opcode::v_ffbh_i32;
1147          Temp msb_rev = bld.tmp(v1);
1148          emit_vop1_instruction(ctx, instr, op, msb_rev);
1149          Temp msb = bld.tmp(v1);
1150          Temp carry = bld.vsub32(Definition(msb), Operand(31u), Operand(msb_rev), true).def(1).getTemp();
1151          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), msb, Operand((uint32_t)-1), carry);
1152       } else {
1153          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1154          nir_print_instr(&instr->instr, stderr);
1155          fprintf(stderr, "\n");
1156       }
1157       break;
1158    }
1159    case nir_op_bitfield_reverse: {
1160       if (dst.regClass() == s1) {
1161          bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1162       } else if (dst.regClass() == v1) {
1163          bld.vop1(aco_opcode::v_bfrev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));
1164       } else {
1165          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1166          nir_print_instr(&instr->instr, stderr);
1167          fprintf(stderr, "\n");
1168       }
1169       break;
1170    }
1171    case nir_op_iadd: {
1172       if (dst.regClass() == s1) {
1173          emit_sop2_instruction(ctx, instr, aco_opcode::s_add_u32, dst, true);
1174          break;
1175       }
1176
1177       Temp src0 = get_alu_src(ctx, instr->src[0]);
1178       Temp src1 = get_alu_src(ctx, instr->src[1]);
1179       if (dst.regClass() == v1) {
1180          bld.vadd32(Definition(dst), Operand(src0), Operand(src1));
1181          break;
1182       }
1183
1184       assert(src0.size() == 2 && src1.size() == 2);
1185       Temp src00 = bld.tmp(src0.type(), 1);
1186       Temp src01 = bld.tmp(dst.type(), 1);
1187       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1188       Temp src10 = bld.tmp(src1.type(), 1);
1189       Temp src11 = bld.tmp(dst.type(), 1);
1190       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1191
1192       if (dst.regClass() == s2) {
1193          Temp carry = bld.tmp(s1);
1194          Temp dst0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1195          Temp dst1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), src01, src11, bld.scc(carry));
1196          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1197       } else if (dst.regClass() == v2) {
1198          Temp dst0 = bld.tmp(v1);
1199          Temp carry = bld.vadd32(Definition(dst0), src00, src10, true).def(1).getTemp();
1200          Temp dst1 = bld.vadd32(bld.def(v1), src01, src11, false, carry);
1201          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1202       } else {
1203          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1204          nir_print_instr(&instr->instr, stderr);
1205          fprintf(stderr, "\n");
1206       }
1207       break;
1208    }
1209    case nir_op_uadd_sat: {
1210       Temp src0 = get_alu_src(ctx, instr->src[0]);
1211       Temp src1 = get_alu_src(ctx, instr->src[1]);
1212       if (dst.regClass() == s1) {
1213          Temp tmp = bld.tmp(s1), carry = bld.tmp(s1);
1214          bld.sop2(aco_opcode::s_add_u32, Definition(tmp), bld.scc(Definition(carry)),
1215                   src0, src1);
1216          bld.sop2(aco_opcode::s_cselect_b32, Definition(dst), Operand((uint32_t) -1), tmp, bld.scc(carry));
1217       } else if (dst.regClass() == v1) {
1218          if (ctx->options->chip_class >= GFX9) {
1219             aco_ptr<VOP3A_instruction> add{create_instruction<VOP3A_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
1220             add->operands[0] = Operand(src0);
1221             add->operands[1] = Operand(src1);
1222             add->definitions[0] = Definition(dst);
1223             add->clamp = 1;
1224             ctx->block->instructions.emplace_back(std::move(add));
1225          } else {
1226             if (src1.regClass() != v1)
1227                std::swap(src0, src1);
1228             assert(src1.regClass() == v1);
1229             Temp tmp = bld.tmp(v1);
1230             Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp();
1231             bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry);
1232          }
1233       } else {
1234          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1235          nir_print_instr(&instr->instr, stderr);
1236          fprintf(stderr, "\n");
1237       }
1238       break;
1239    }
1240    case nir_op_uadd_carry: {
1241       Temp src0 = get_alu_src(ctx, instr->src[0]);
1242       Temp src1 = get_alu_src(ctx, instr->src[1]);
1243       if (dst.regClass() == s1) {
1244          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1245          break;
1246       }
1247       if (dst.regClass() == v1) {
1248          Temp carry = bld.vadd32(bld.def(v1), src0, src1, true).def(1).getTemp();
1249          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), carry);
1250          break;
1251       }
1252
1253       Temp src00 = bld.tmp(src0.type(), 1);
1254       Temp src01 = bld.tmp(dst.type(), 1);
1255       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1256       Temp src10 = bld.tmp(src1.type(), 1);
1257       Temp src11 = bld.tmp(dst.type(), 1);
1258       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1259       if (dst.regClass() == s2) {
1260          Temp carry = bld.tmp(s1);
1261          bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1262          carry = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(carry)).def(1).getTemp();
1263          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1264       } else if (dst.regClass() == v2) {
1265          Temp carry = bld.vadd32(bld.def(v1), src00, src10, true).def(1).getTemp();
1266          carry = bld.vadd32(bld.def(v1), src01, src11, true, carry).def(1).getTemp();
1267          carry = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), carry);
1268          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), carry, Operand(0u));
1269       } else {
1270          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1271          nir_print_instr(&instr->instr, stderr);
1272          fprintf(stderr, "\n");
1273       }
1274       break;
1275    }
1276    case nir_op_isub: {
1277       if (dst.regClass() == s1) {
1278          emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true);
1279          break;
1280       }
1281
1282       Temp src0 = get_alu_src(ctx, instr->src[0]);
1283       Temp src1 = get_alu_src(ctx, instr->src[1]);
1284       if (dst.regClass() == v1) {
1285          bld.vsub32(Definition(dst), src0, src1);
1286          break;
1287       }
1288
1289       Temp src00 = bld.tmp(src0.type(), 1);
1290       Temp src01 = bld.tmp(dst.type(), 1);
1291       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1292       Temp src10 = bld.tmp(src1.type(), 1);
1293       Temp src11 = bld.tmp(dst.type(), 1);
1294       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1295       if (dst.regClass() == s2) {
1296          Temp carry = bld.tmp(s1);
1297          Temp dst0 = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(carry)), src00, src10);
1298          Temp dst1 = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), src01, src11, carry);
1299          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1300       } else if (dst.regClass() == v2) {
1301          Temp lower = bld.tmp(v1);
1302          Temp borrow = bld.vsub32(Definition(lower), src00, src10, true).def(1).getTemp();
1303          Temp upper = bld.vsub32(bld.def(v1), src01, src11, false, borrow);
1304          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1305       } else {
1306          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1307          nir_print_instr(&instr->instr, stderr);
1308          fprintf(stderr, "\n");
1309       }
1310       break;
1311    }
1312    case nir_op_usub_borrow: {
1313       Temp src0 = get_alu_src(ctx, instr->src[0]);
1314       Temp src1 = get_alu_src(ctx, instr->src[1]);
1315       if (dst.regClass() == s1) {
1316          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(dst)), src0, src1);
1317          break;
1318       } else if (dst.regClass() == v1) {
1319          Temp borrow = bld.vsub32(bld.def(v1), src0, src1, true).def(1).getTemp();
1320          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), borrow);
1321          break;
1322       }
1323
1324       Temp src00 = bld.tmp(src0.type(), 1);
1325       Temp src01 = bld.tmp(dst.type(), 1);
1326       bld.pseudo(aco_opcode::p_split_vector, Definition(src00), Definition(src01), src0);
1327       Temp src10 = bld.tmp(src1.type(), 1);
1328       Temp src11 = bld.tmp(dst.type(), 1);
1329       bld.pseudo(aco_opcode::p_split_vector, Definition(src10), Definition(src11), src1);
1330       if (dst.regClass() == s2) {
1331          Temp borrow = bld.tmp(s1);
1332          bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), src00, src10);
1333          borrow = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.scc(bld.def(s1)), src01, src11, bld.scc(borrow)).def(1).getTemp();
1334          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1335       } else if (dst.regClass() == v2) {
1336          Temp borrow = bld.vsub32(bld.def(v1), src00, src10, true).def(1).getTemp();
1337          borrow = bld.vsub32(bld.def(v1), src01, src11, true, Operand(borrow)).def(1).getTemp();
1338          borrow = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand(1u), borrow);
1339          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), borrow, Operand(0u));
1340       } else {
1341          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1342          nir_print_instr(&instr->instr, stderr);
1343          fprintf(stderr, "\n");
1344       }
1345       break;
1346    }
1347    case nir_op_imul: {
1348       if (dst.regClass() == v1) {
1349          bld.vop3(aco_opcode::v_mul_lo_u32, Definition(dst),
1350                   get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1351       } else if (dst.regClass() == s1) {
1352          emit_sop2_instruction(ctx, instr, aco_opcode::s_mul_i32, dst, false);
1353       } else {
1354          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1355          nir_print_instr(&instr->instr, stderr);
1356          fprintf(stderr, "\n");
1357       }
1358       break;
1359    }
1360    case nir_op_umul_high: {
1361       if (dst.regClass() == v1) {
1362          bld.vop3(aco_opcode::v_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1363       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1364          bld.sop2(aco_opcode::s_mul_hi_u32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1365       } else if (dst.regClass() == s1) {
1366          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1367                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1368          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1369       } else {
1370          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1371          nir_print_instr(&instr->instr, stderr);
1372          fprintf(stderr, "\n");
1373       }
1374       break;
1375    }
1376    case nir_op_imul_high: {
1377       if (dst.regClass() == v1) {
1378          bld.vop3(aco_opcode::v_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1379       } else if (dst.regClass() == s1 && ctx->options->chip_class >= GFX9) {
1380          bld.sop2(aco_opcode::s_mul_hi_i32, Definition(dst), get_alu_src(ctx, instr->src[0]), get_alu_src(ctx, instr->src[1]));
1381       } else if (dst.regClass() == s1) {
1382          Temp tmp = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), get_alu_src(ctx, instr->src[0]),
1383                              as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1384          bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp);
1385       } else {
1386          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1387          nir_print_instr(&instr->instr, stderr);
1388          fprintf(stderr, "\n");
1389       }
1390       break;
1391    }
1392    case nir_op_fmul: {
1393       if (dst.size() == 1) {
1394          emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true);
1395       } else if (dst.size() == 2) {
1396          bld.vop3(aco_opcode::v_mul_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1397                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1398       } else {
1399          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1400          nir_print_instr(&instr->instr, stderr);
1401          fprintf(stderr, "\n");
1402       }
1403       break;
1404    }
1405    case nir_op_fadd: {
1406       if (dst.size() == 1) {
1407          emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true);
1408       } else if (dst.size() == 2) {
1409          bld.vop3(aco_opcode::v_add_f64, Definition(dst), get_alu_src(ctx, instr->src[0]),
1410                   as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1411       } else {
1412          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1413          nir_print_instr(&instr->instr, stderr);
1414          fprintf(stderr, "\n");
1415       }
1416       break;
1417    }
1418    case nir_op_fsub: {
1419       Temp src0 = get_alu_src(ctx, instr->src[0]);
1420       Temp src1 = get_alu_src(ctx, instr->src[1]);
1421       if (dst.size() == 1) {
1422          if (src1.type() == RegType::vgpr || src0.type() != RegType::vgpr)
1423             emit_vop2_instruction(ctx, instr, aco_opcode::v_sub_f32, dst, false);
1424          else
1425             emit_vop2_instruction(ctx, instr, aco_opcode::v_subrev_f32, dst, true);
1426       } else if (dst.size() == 2) {
1427          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
1428                                      get_alu_src(ctx, instr->src[0]),
1429                                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1430          VOP3A_instruction* sub = static_cast<VOP3A_instruction*>(add);
1431          sub->neg[1] = true;
1432       } else {
1433          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1434          nir_print_instr(&instr->instr, stderr);
1435          fprintf(stderr, "\n");
1436       }
1437       break;
1438    }
1439    case nir_op_fmax: {
1440       if (dst.size() == 1) {
1441          emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1442       } else if (dst.size() == 2) {
1443          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1444             Temp tmp = bld.vop3(aco_opcode::v_max_f64, bld.def(v2),
1445                                 get_alu_src(ctx, instr->src[0]),
1446                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1447             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1448          } else {
1449             bld.vop3(aco_opcode::v_max_f64, Definition(dst),
1450                      get_alu_src(ctx, instr->src[0]),
1451                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1452          }
1453       } else {
1454          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1455          nir_print_instr(&instr->instr, stderr);
1456          fprintf(stderr, "\n");
1457       }
1458       break;
1459    }
1460    case nir_op_fmin: {
1461       if (dst.size() == 1) {
1462          emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, ctx->block->fp_mode.must_flush_denorms32);
1463       } else if (dst.size() == 2) {
1464          if (ctx->block->fp_mode.must_flush_denorms16_64 && ctx->program->chip_class < GFX9) {
1465             Temp tmp = bld.vop3(aco_opcode::v_min_f64, bld.def(v2),
1466                                 get_alu_src(ctx, instr->src[0]),
1467                                 as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1468             bld.vop3(aco_opcode::v_mul_f64, Definition(dst), Operand(0x3FF0000000000000lu), tmp);
1469          } else {
1470             bld.vop3(aco_opcode::v_min_f64, Definition(dst),
1471                      get_alu_src(ctx, instr->src[0]),
1472                      as_vgpr(ctx, get_alu_src(ctx, instr->src[1])));
1473          }
1474       } else {
1475          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1476          nir_print_instr(&instr->instr, stderr);
1477          fprintf(stderr, "\n");
1478       }
1479       break;
1480    }
1481    case nir_op_fmax3: {
1482       if (dst.size() == 1) {
1483          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1484       } else {
1485          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1486          nir_print_instr(&instr->instr, stderr);
1487          fprintf(stderr, "\n");
1488       }
1489       break;
1490    }
1491    case nir_op_fmin3: {
1492       if (dst.size() == 1) {
1493          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1494       } else {
1495          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1496          nir_print_instr(&instr->instr, stderr);
1497          fprintf(stderr, "\n");
1498       }
1499       break;
1500    }
1501    case nir_op_fmed3: {
1502       if (dst.size() == 1) {
1503          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_f32, dst, ctx->block->fp_mode.must_flush_denorms32);
1504       } else {
1505          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1506          nir_print_instr(&instr->instr, stderr);
1507          fprintf(stderr, "\n");
1508       }
1509       break;
1510    }
1511    case nir_op_umax3: {
1512       if (dst.size() == 1) {
1513          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_u32, dst);
1514       } else {
1515          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1516          nir_print_instr(&instr->instr, stderr);
1517          fprintf(stderr, "\n");
1518       }
1519       break;
1520    }
1521    case nir_op_umin3: {
1522       if (dst.size() == 1) {
1523          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_u32, dst);
1524       } else {
1525          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1526          nir_print_instr(&instr->instr, stderr);
1527          fprintf(stderr, "\n");
1528       }
1529       break;
1530    }
1531    case nir_op_umed3: {
1532       if (dst.size() == 1) {
1533          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_u32, dst);
1534       } else {
1535          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1536          nir_print_instr(&instr->instr, stderr);
1537          fprintf(stderr, "\n");
1538       }
1539       break;
1540    }
1541    case nir_op_imax3: {
1542       if (dst.size() == 1) {
1543          emit_vop3a_instruction(ctx, instr, aco_opcode::v_max3_i32, dst);
1544       } else {
1545          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1546          nir_print_instr(&instr->instr, stderr);
1547          fprintf(stderr, "\n");
1548       }
1549       break;
1550    }
1551    case nir_op_imin3: {
1552       if (dst.size() == 1) {
1553          emit_vop3a_instruction(ctx, instr, aco_opcode::v_min3_i32, dst);
1554       } else {
1555          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1556          nir_print_instr(&instr->instr, stderr);
1557          fprintf(stderr, "\n");
1558       }
1559       break;
1560    }
1561    case nir_op_imed3: {
1562       if (dst.size() == 1) {
1563          emit_vop3a_instruction(ctx, instr, aco_opcode::v_med3_i32, dst);
1564       } else {
1565          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1566          nir_print_instr(&instr->instr, stderr);
1567          fprintf(stderr, "\n");
1568       }
1569       break;
1570    }
1571    case nir_op_cube_face_coord: {
1572       Temp in = get_alu_src(ctx, instr->src[0], 3);
1573       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1574                       emit_extract_vector(ctx, in, 1, v1),
1575                       emit_extract_vector(ctx, in, 2, v1) };
1576       Temp ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), src[0], src[1], src[2]);
1577       ma = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), ma);
1578       Temp sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), src[0], src[1], src[2]);
1579       Temp tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), src[0], src[1], src[2]);
1580       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, ma, Operand(0x3f000000u/*0.5*/));
1581       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, ma, Operand(0x3f000000u/*0.5*/));
1582       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), sc, tc);
1583       break;
1584    }
1585    case nir_op_cube_face_index: {
1586       Temp in = get_alu_src(ctx, instr->src[0], 3);
1587       Temp src[3] = { emit_extract_vector(ctx, in, 0, v1),
1588                       emit_extract_vector(ctx, in, 1, v1),
1589                       emit_extract_vector(ctx, in, 2, v1) };
1590       bld.vop3(aco_opcode::v_cubeid_f32, Definition(dst), src[0], src[1], src[2]);
1591       break;
1592    }
1593    case nir_op_bcsel: {
1594       emit_bcsel(ctx, instr, dst);
1595       break;
1596    }
1597    case nir_op_frsq: {
1598       if (dst.size() == 1) {
1599          emit_rsq(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1600       } else if (dst.size() == 2) {
1601          emit_vop1_instruction(ctx, instr, aco_opcode::v_rsq_f64, dst);
1602       } else {
1603          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1604          nir_print_instr(&instr->instr, stderr);
1605          fprintf(stderr, "\n");
1606       }
1607       break;
1608    }
1609    case nir_op_fneg: {
1610       Temp src = get_alu_src(ctx, instr->src[0]);
1611       if (dst.size() == 1) {
1612          if (ctx->block->fp_mode.must_flush_denorms32)
1613             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1614          bld.vop2(aco_opcode::v_xor_b32, Definition(dst), Operand(0x80000000u), as_vgpr(ctx, src));
1615       } else if (dst.size() == 2) {
1616          if (ctx->block->fp_mode.must_flush_denorms16_64)
1617             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1618          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1619          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1620          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), Operand(0x80000000u), upper);
1621          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1622       } else {
1623          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1624          nir_print_instr(&instr->instr, stderr);
1625          fprintf(stderr, "\n");
1626       }
1627       break;
1628    }
1629    case nir_op_fabs: {
1630       Temp src = get_alu_src(ctx, instr->src[0]);
1631       if (dst.size() == 1) {
1632          if (ctx->block->fp_mode.must_flush_denorms32)
1633             src = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0x3f800000u), as_vgpr(ctx, src));
1634          bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0x7FFFFFFFu), as_vgpr(ctx, src));
1635       } else if (dst.size() == 2) {
1636          if (ctx->block->fp_mode.must_flush_denorms16_64)
1637             src = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), Operand(0x3FF0000000000000lu), as_vgpr(ctx, src));
1638          Temp upper = bld.tmp(v1), lower = bld.tmp(v1);
1639          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1640          upper = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7FFFFFFFu), upper);
1641          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
1642       } else {
1643          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1644          nir_print_instr(&instr->instr, stderr);
1645          fprintf(stderr, "\n");
1646       }
1647       break;
1648    }
1649    case nir_op_fsat: {
1650       Temp src = get_alu_src(ctx, instr->src[0]);
1651       if (dst.size() == 1) {
1652          bld.vop3(aco_opcode::v_med3_f32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
1653          /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1654          // TODO: confirm that this holds under any circumstances
1655       } else if (dst.size() == 2) {
1656          Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
1657          VOP3A_instruction* vop3 = static_cast<VOP3A_instruction*>(add);
1658          vop3->clamp = true;
1659       } else {
1660          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1661          nir_print_instr(&instr->instr, stderr);
1662          fprintf(stderr, "\n");
1663       }
1664       break;
1665    }
1666    case nir_op_flog2: {
1667       if (dst.size() == 1) {
1668          emit_log2(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1669       } else {
1670          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1671          nir_print_instr(&instr->instr, stderr);
1672          fprintf(stderr, "\n");
1673       }
1674       break;
1675    }
1676    case nir_op_frcp: {
1677       if (dst.size() == 1) {
1678          emit_rcp(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1679       } else if (dst.size() == 2) {
1680          emit_vop1_instruction(ctx, instr, aco_opcode::v_rcp_f64, dst);
1681       } else {
1682          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1683          nir_print_instr(&instr->instr, stderr);
1684          fprintf(stderr, "\n");
1685       }
1686       break;
1687    }
1688    case nir_op_fexp2: {
1689       if (dst.size() == 1) {
1690          emit_vop1_instruction(ctx, instr, aco_opcode::v_exp_f32, dst);
1691       } else {
1692          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1693          nir_print_instr(&instr->instr, stderr);
1694          fprintf(stderr, "\n");
1695       }
1696       break;
1697    }
1698    case nir_op_fsqrt: {
1699       if (dst.size() == 1) {
1700          emit_sqrt(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1701       } else if (dst.size() == 2) {
1702          emit_vop1_instruction(ctx, instr, aco_opcode::v_sqrt_f64, dst);
1703       } else {
1704          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1705          nir_print_instr(&instr->instr, stderr);
1706          fprintf(stderr, "\n");
1707       }
1708       break;
1709    }
1710    case nir_op_ffract: {
1711       if (dst.size() == 1) {
1712          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f32, dst);
1713       } else if (dst.size() == 2) {
1714          emit_vop1_instruction(ctx, instr, aco_opcode::v_fract_f64, dst);
1715       } else {
1716          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1717          nir_print_instr(&instr->instr, stderr);
1718          fprintf(stderr, "\n");
1719       }
1720       break;
1721    }
1722    case nir_op_ffloor: {
1723       if (dst.size() == 1) {
1724          emit_vop1_instruction(ctx, instr, aco_opcode::v_floor_f32, dst);
1725       } else if (dst.size() == 2) {
1726          emit_floor_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1727       } else {
1728          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1729          nir_print_instr(&instr->instr, stderr);
1730          fprintf(stderr, "\n");
1731       }
1732       break;
1733    }
1734    case nir_op_fceil: {
1735       if (dst.size() == 1) {
1736          emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f32, dst);
1737       } else if (dst.size() == 2) {
1738          if (ctx->options->chip_class >= GFX7) {
1739             emit_vop1_instruction(ctx, instr, aco_opcode::v_ceil_f64, dst);
1740          } else {
1741             /* GFX6 doesn't support V_CEIL_F64, lower it. */
1742             Temp src0 = get_alu_src(ctx, instr->src[0]);
1743
1744             /* trunc = trunc(src0)
1745              * if (src0 > 0.0 && src0 != trunc)
1746              *    trunc += 1.0
1747              */
1748             Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src0);
1749             Temp tmp0 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.def(bld.lm), src0, Operand(0u));
1750             Temp tmp1 = bld.vopc(aco_opcode::v_cmp_lg_f64, bld.hint_vcc(bld.def(bld.lm)), src0, trunc);
1751             Temp cond = bld.sop2(aco_opcode::s_and_b64, bld.hint_vcc(bld.def(s2)), bld.def(s1, scc), tmp0, tmp1);
1752             Temp add = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), bld.copy(bld.def(v1), Operand(0u)), bld.copy(bld.def(v1), Operand(0x3ff00000u)), cond);
1753             add = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), bld.copy(bld.def(v1), Operand(0u)), add);
1754             bld.vop3(aco_opcode::v_add_f64, Definition(dst), trunc, add);
1755          }
1756       } else {
1757          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1758          nir_print_instr(&instr->instr, stderr);
1759          fprintf(stderr, "\n");
1760       }
1761       break;
1762    }
1763    case nir_op_ftrunc: {
1764       if (dst.size() == 1) {
1765          emit_vop1_instruction(ctx, instr, aco_opcode::v_trunc_f32, dst);
1766       } else if (dst.size() == 2) {
1767          emit_trunc_f64(ctx, bld, Definition(dst), get_alu_src(ctx, instr->src[0]));
1768       } else {
1769          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1770          nir_print_instr(&instr->instr, stderr);
1771          fprintf(stderr, "\n");
1772       }
1773       break;
1774    }
1775    case nir_op_fround_even: {
1776       if (dst.size() == 1) {
1777          emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f32, dst);
1778       } else if (dst.size() == 2) {
1779          if (ctx->options->chip_class >= GFX7) {
1780             emit_vop1_instruction(ctx, instr, aco_opcode::v_rndne_f64, dst);
1781          } else {
1782             /* GFX6 doesn't support V_RNDNE_F64, lower it. */
1783             Temp src0 = get_alu_src(ctx, instr->src[0]);
1784
1785             Temp src0_lo = bld.tmp(v1), src0_hi = bld.tmp(v1);
1786             bld.pseudo(aco_opcode::p_split_vector, Definition(src0_lo), Definition(src0_hi), src0);
1787
1788             Temp bitmask = bld.sop1(aco_opcode::s_brev_b32, bld.def(s1), bld.copy(bld.def(s1), Operand(-2u)));
1789             Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
1790             Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1791             Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
1792             static_cast<VOP3A_instruction*>(sub)->neg[1] = true;
1793             tmp = sub->definitions[0].getTemp();
1794
1795             Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
1796             Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
1797             static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
1798             Temp cond = vop3->definitions[0].getTemp();
1799
1800             Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
1801             bld.pseudo(aco_opcode::p_split_vector, Definition(tmp_lo), Definition(tmp_hi), tmp);
1802             Temp dst0 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_lo, as_vgpr(ctx, src0_lo), cond);
1803             Temp dst1 = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp_hi, as_vgpr(ctx, src0_hi), cond);
1804
1805             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), dst0, dst1);
1806          }
1807       } else {
1808          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1809          nir_print_instr(&instr->instr, stderr);
1810          fprintf(stderr, "\n");
1811       }
1812       break;
1813    }
1814    case nir_op_fsin:
1815    case nir_op_fcos: {
1816       Temp src = get_alu_src(ctx, instr->src[0]);
1817       aco_ptr<Instruction> norm;
1818       if (dst.size() == 1) {
1819          Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u));
1820          Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, as_vgpr(ctx, src));
1821
1822          /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1823          if (ctx->options->chip_class < GFX9)
1824             tmp = bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), tmp);
1825
1826          aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f32 : aco_opcode::v_cos_f32;
1827          bld.vop1(opcode, Definition(dst), tmp);
1828       } else {
1829          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1830          nir_print_instr(&instr->instr, stderr);
1831          fprintf(stderr, "\n");
1832       }
1833       break;
1834    }
1835    case nir_op_ldexp: {
1836       if (dst.size() == 1) {
1837          bld.vop3(aco_opcode::v_ldexp_f32, Definition(dst),
1838                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1839                   get_alu_src(ctx, instr->src[1]));
1840       } else if (dst.size() == 2) {
1841          bld.vop3(aco_opcode::v_ldexp_f64, Definition(dst),
1842                   as_vgpr(ctx, get_alu_src(ctx, instr->src[0])),
1843                   get_alu_src(ctx, instr->src[1]));
1844       } else {
1845          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1846          nir_print_instr(&instr->instr, stderr);
1847          fprintf(stderr, "\n");
1848       }
1849       break;
1850    }
1851    case nir_op_frexp_sig: {
1852       if (dst.size() == 1) {
1853          bld.vop1(aco_opcode::v_frexp_mant_f32, Definition(dst),
1854                   get_alu_src(ctx, instr->src[0]));
1855       } else if (dst.size() == 2) {
1856          bld.vop1(aco_opcode::v_frexp_mant_f64, Definition(dst),
1857                   get_alu_src(ctx, instr->src[0]));
1858       } else {
1859          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1860          nir_print_instr(&instr->instr, stderr);
1861          fprintf(stderr, "\n");
1862       }
1863       break;
1864    }
1865    case nir_op_frexp_exp: {
1866       if (instr->src[0].src.ssa->bit_size == 32) {
1867          bld.vop1(aco_opcode::v_frexp_exp_i32_f32, Definition(dst),
1868                   get_alu_src(ctx, instr->src[0]));
1869       } else if (instr->src[0].src.ssa->bit_size == 64) {
1870          bld.vop1(aco_opcode::v_frexp_exp_i32_f64, Definition(dst),
1871                   get_alu_src(ctx, instr->src[0]));
1872       } else {
1873          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1874          nir_print_instr(&instr->instr, stderr);
1875          fprintf(stderr, "\n");
1876       }
1877       break;
1878    }
1879    case nir_op_fsign: {
1880       Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0]));
1881       if (dst.size() == 1) {
1882          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1883          src = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0x3f800000u), src, cond);
1884          cond = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1885          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0xbf800000u), src, cond);
1886       } else if (dst.size() == 2) {
1887          Temp cond = bld.vopc(aco_opcode::v_cmp_nlt_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1888          Temp tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0x3FF00000u));
1889          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, emit_extract_vector(ctx, src, 1, v1), cond);
1890
1891          cond = bld.vopc(aco_opcode::v_cmp_le_f64, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), src);
1892          tmp = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0xBFF00000u));
1893          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), tmp, upper, cond);
1894
1895          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
1896       } else {
1897          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1898          nir_print_instr(&instr->instr, stderr);
1899          fprintf(stderr, "\n");
1900       }
1901       break;
1902    }
1903    case nir_op_f2f32: {
1904       if (instr->src[0].src.ssa->bit_size == 64) {
1905          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f64, dst);
1906       } else {
1907          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1908          nir_print_instr(&instr->instr, stderr);
1909          fprintf(stderr, "\n");
1910       }
1911       break;
1912    }
1913    case nir_op_f2f64: {
1914       if (instr->src[0].src.ssa->bit_size == 32) {
1915          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_f32, dst);
1916       } else {
1917          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1918          nir_print_instr(&instr->instr, stderr);
1919          fprintf(stderr, "\n");
1920       }
1921       break;
1922    }
1923    case nir_op_i2f32: {
1924       assert(dst.size() == 1);
1925       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_i32, dst);
1926       break;
1927    }
1928    case nir_op_i2f64: {
1929       if (instr->src[0].src.ssa->bit_size == 32) {
1930          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_i32, dst);
1931       } else if (instr->src[0].src.ssa->bit_size == 64) {
1932          Temp src = get_alu_src(ctx, instr->src[0]);
1933          RegClass rc = RegClass(src.type(), 1);
1934          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1935          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1936          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1937          upper = bld.vop1(aco_opcode::v_cvt_f64_i32, bld.def(v2), upper);
1938          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1939          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1940
1941       } else {
1942          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1943          nir_print_instr(&instr->instr, stderr);
1944          fprintf(stderr, "\n");
1945       }
1946       break;
1947    }
1948    case nir_op_u2f32: {
1949       assert(dst.size() == 1);
1950       emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_u32, dst);
1951       break;
1952    }
1953    case nir_op_u2f64: {
1954       if (instr->src[0].src.ssa->bit_size == 32) {
1955          emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f64_u32, dst);
1956       } else if (instr->src[0].src.ssa->bit_size == 64) {
1957          Temp src = get_alu_src(ctx, instr->src[0]);
1958          RegClass rc = RegClass(src.type(), 1);
1959          Temp lower = bld.tmp(rc), upper = bld.tmp(rc);
1960          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), src);
1961          lower = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), lower);
1962          upper = bld.vop1(aco_opcode::v_cvt_f64_u32, bld.def(v2), upper);
1963          upper = bld.vop3(aco_opcode::v_ldexp_f64, bld.def(v2), upper, Operand(32u));
1964          bld.vop3(aco_opcode::v_add_f64, Definition(dst), lower, upper);
1965       } else {
1966          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1967          nir_print_instr(&instr->instr, stderr);
1968          fprintf(stderr, "\n");
1969       }
1970       break;
1971    }
1972    case nir_op_f2i32: {
1973       Temp src = get_alu_src(ctx, instr->src[0]);
1974       if (instr->src[0].src.ssa->bit_size == 32) {
1975          if (dst.type() == RegType::vgpr)
1976             bld.vop1(aco_opcode::v_cvt_i32_f32, Definition(dst), src);
1977          else
1978             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1979                        bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), src));
1980
1981       } else if (instr->src[0].src.ssa->bit_size == 64) {
1982          if (dst.type() == RegType::vgpr)
1983             bld.vop1(aco_opcode::v_cvt_i32_f64, Definition(dst), src);
1984          else
1985             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
1986                        bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), src));
1987
1988       } else {
1989          fprintf(stderr, "Unimplemented NIR instr bit size: ");
1990          nir_print_instr(&instr->instr, stderr);
1991          fprintf(stderr, "\n");
1992       }
1993       break;
1994    }
1995    case nir_op_f2u32: {
1996       Temp src = get_alu_src(ctx, instr->src[0]);
1997       if (instr->src[0].src.ssa->bit_size == 32) {
1998          if (dst.type() == RegType::vgpr)
1999             bld.vop1(aco_opcode::v_cvt_u32_f32, Definition(dst), src);
2000          else
2001             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2002                        bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), src));
2003
2004       } else if (instr->src[0].src.ssa->bit_size == 64) {
2005          if (dst.type() == RegType::vgpr)
2006             bld.vop1(aco_opcode::v_cvt_u32_f64, Definition(dst), src);
2007          else
2008             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst),
2009                        bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), src));
2010
2011       } else {
2012          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2013          nir_print_instr(&instr->instr, stderr);
2014          fprintf(stderr, "\n");
2015       }
2016       break;
2017    }
2018    case nir_op_f2i64: {
2019       Temp src = get_alu_src(ctx, instr->src[0]);
2020       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2021          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2022          exponent = bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand(0x0u), exponent, Operand(64u));
2023          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2024          Temp sign = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2025          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2026          mantissa = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(7u), mantissa);
2027          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2028          Temp new_exponent = bld.tmp(v1);
2029          Temp borrow = bld.vsub32(Definition(new_exponent), Operand(63u), exponent, true).def(1).getTemp();
2030          if (ctx->program->chip_class >= GFX8)
2031             mantissa = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), new_exponent, mantissa);
2032          else
2033             mantissa = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), mantissa, new_exponent);
2034          Temp saturate = bld.vop1(aco_opcode::v_bfrev_b32, bld.def(v1), Operand(0xfffffffeu));
2035          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2036          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2037          lower = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), lower, Operand(0xffffffffu), borrow);
2038          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), upper, saturate, borrow);
2039          lower = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, lower);
2040          upper = bld.vop2(aco_opcode::v_xor_b32, bld.def(v1), sign, upper);
2041          Temp new_lower = bld.tmp(v1);
2042          borrow = bld.vsub32(Definition(new_lower), lower, sign, true).def(1).getTemp();
2043          Temp new_upper = bld.vsub32(bld.def(v1), upper, sign, false, borrow);
2044          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), new_lower, new_upper);
2045
2046       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2047          if (src.type() == RegType::vgpr)
2048             src = bld.as_uniform(src);
2049          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2050          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2051          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2052          exponent = bld.sop2(aco_opcode::s_min_u32, bld.def(s1), bld.def(s1, scc), Operand(64u), exponent);
2053          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2054          Temp sign = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2055          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2056          mantissa = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), mantissa, Operand(7u));
2057          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2058          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(63u), exponent);
2059          mantissa = bld.sop2(aco_opcode::s_lshr_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent);
2060          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), exponent, Operand(0xffffffffu)); // exp >= 64
2061          Temp saturate = bld.sop1(aco_opcode::s_brev_b64, bld.def(s2), Operand(0xfffffffeu));
2062          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), saturate, mantissa, cond);
2063          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2064          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2065          lower = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, lower);
2066          upper = bld.sop2(aco_opcode::s_xor_b32, bld.def(s1), bld.def(s1, scc), sign, upper);
2067          Temp borrow = bld.tmp(s1);
2068          lower = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.scc(Definition(borrow)), lower, sign);
2069          upper = bld.sop2(aco_opcode::s_subb_u32, bld.def(s1), bld.def(s1, scc), upper, sign, borrow);
2070          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2071
2072       } else if (instr->src[0].src.ssa->bit_size == 64) {
2073          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2074          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2075          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2076          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2077          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2078          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2079          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2080          Temp upper = bld.vop1(aco_opcode::v_cvt_i32_f64, bld.def(v1), floor);
2081          if (dst.type() == RegType::sgpr) {
2082             lower = bld.as_uniform(lower);
2083             upper = bld.as_uniform(upper);
2084          }
2085          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2086
2087       } else {
2088          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2089          nir_print_instr(&instr->instr, stderr);
2090          fprintf(stderr, "\n");
2091       }
2092       break;
2093    }
2094    case nir_op_f2u64: {
2095       Temp src = get_alu_src(ctx, instr->src[0]);
2096       if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::vgpr) {
2097          Temp exponent = bld.vop1(aco_opcode::v_frexp_exp_i32_f32, bld.def(v1), src);
2098          Temp exponent_in_range = bld.vopc(aco_opcode::v_cmp_ge_i32, bld.hint_vcc(bld.def(bld.lm)), Operand(64u), exponent);
2099          exponent = bld.vop2(aco_opcode::v_max_i32, bld.def(v1), Operand(0x0u), exponent);
2100          Temp mantissa = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffu), src);
2101          mantissa = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(0x800000u), mantissa);
2102          Temp exponent_small = bld.vsub32(bld.def(v1), Operand(24u), exponent);
2103          Temp small = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), exponent_small, mantissa);
2104          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), mantissa);
2105          Temp new_exponent = bld.tmp(v1);
2106          Temp cond_small = bld.vsub32(Definition(new_exponent), exponent, Operand(24u), true).def(1).getTemp();
2107          if (ctx->program->chip_class >= GFX8)
2108             mantissa = bld.vop3(aco_opcode::v_lshlrev_b64, bld.def(v2), new_exponent, mantissa);
2109          else
2110             mantissa = bld.vop3(aco_opcode::v_lshl_b64, bld.def(v2), mantissa, new_exponent);
2111          Temp lower = bld.tmp(v1), upper = bld.tmp(v1);
2112          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2113          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), lower, small, cond_small);
2114          upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), upper, Operand(0u), cond_small);
2115          lower = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), lower, exponent_in_range);
2116          upper = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xffffffffu), upper, exponent_in_range);
2117          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2118
2119       } else if (instr->src[0].src.ssa->bit_size == 32 && dst.type() == RegType::sgpr) {
2120          if (src.type() == RegType::vgpr)
2121             src = bld.as_uniform(src);
2122          Temp exponent = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), src, Operand(0x80017u));
2123          exponent = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(126u));
2124          exponent = bld.sop2(aco_opcode::s_max_u32, bld.def(s1), bld.def(s1, scc), Operand(0u), exponent);
2125          Temp mantissa = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0x7fffffu), src);
2126          mantissa = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(0x800000u), mantissa);
2127          Temp exponent_small = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), Operand(24u), exponent);
2128          Temp small = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), mantissa, exponent_small);
2129          mantissa = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), mantissa);
2130          Temp exponent_large = bld.sop2(aco_opcode::s_sub_u32, bld.def(s1), bld.def(s1, scc), exponent, Operand(24u));
2131          mantissa = bld.sop2(aco_opcode::s_lshl_b64, bld.def(s2), bld.def(s1, scc), mantissa, exponent_large);
2132          Temp cond = bld.sopc(aco_opcode::s_cmp_ge_i32, bld.def(s1, scc), Operand(64u), exponent);
2133          mantissa = bld.sop2(aco_opcode::s_cselect_b64, bld.def(s2), mantissa, Operand(0xffffffffu), cond);
2134          Temp lower = bld.tmp(s1), upper = bld.tmp(s1);
2135          bld.pseudo(aco_opcode::p_split_vector, Definition(lower), Definition(upper), mantissa);
2136          Temp cond_small = bld.sopc(aco_opcode::s_cmp_le_i32, bld.def(s1, scc), exponent, Operand(24u));
2137          lower = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), small, lower, cond_small);
2138          upper = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), Operand(0u), upper, cond_small);
2139          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2140
2141       } else if (instr->src[0].src.ssa->bit_size == 64) {
2142          Temp vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0x3df00000u));
2143          Temp trunc = emit_trunc_f64(ctx, bld, bld.def(v2), src);
2144          Temp mul = bld.vop3(aco_opcode::v_mul_f64, bld.def(v2), trunc, vec);
2145          vec = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(0u), Operand(0xc1f00000u));
2146          Temp floor = emit_floor_f64(ctx, bld, bld.def(v2), mul);
2147          Temp fma = bld.vop3(aco_opcode::v_fma_f64, bld.def(v2), floor, vec, trunc);
2148          Temp lower = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), fma);
2149          Temp upper = bld.vop1(aco_opcode::v_cvt_u32_f64, bld.def(v1), floor);
2150          if (dst.type() == RegType::sgpr) {
2151             lower = bld.as_uniform(lower);
2152             upper = bld.as_uniform(upper);
2153          }
2154          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lower, upper);
2155
2156       } else {
2157          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2158          nir_print_instr(&instr->instr, stderr);
2159          fprintf(stderr, "\n");
2160       }
2161       break;
2162    }
2163    case nir_op_b2f32: {
2164       Temp src = get_alu_src(ctx, instr->src[0]);
2165       assert(src.regClass() == bld.lm);
2166
2167       if (dst.regClass() == s1) {
2168          src = bool_to_scalar_condition(ctx, src);
2169          bld.sop2(aco_opcode::s_mul_i32, Definition(dst), Operand(0x3f800000u), src);
2170       } else if (dst.regClass() == v1) {
2171          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(0x3f800000u), src);
2172       } else {
2173          unreachable("Wrong destination register class for nir_op_b2f32.");
2174       }
2175       break;
2176    }
2177    case nir_op_b2f64: {
2178       Temp src = get_alu_src(ctx, instr->src[0]);
2179       assert(src.regClass() == bld.lm);
2180
2181       if (dst.regClass() == s2) {
2182          src = bool_to_scalar_condition(ctx, src);
2183          bld.sop2(aco_opcode::s_cselect_b64, Definition(dst), Operand(0x3f800000u), Operand(0u), bld.scc(src));
2184       } else if (dst.regClass() == v2) {
2185          Temp one = bld.vop1(aco_opcode::v_mov_b32, bld.def(v2), Operand(0x3FF00000u));
2186          Temp upper = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), one, src);
2187          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), Operand(0u), upper);
2188       } else {
2189          unreachable("Wrong destination register class for nir_op_b2f64.");
2190       }
2191       break;
2192    }
2193    case nir_op_i2i32: {
2194       Temp src = get_alu_src(ctx, instr->src[0]);
2195       if (instr->src[0].src.ssa->bit_size == 64) {
2196          /* we can actually just say dst = src, as it would map the lower register */
2197          emit_extract_vector(ctx, src, 0, dst);
2198       } else {
2199          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2200          nir_print_instr(&instr->instr, stderr);
2201          fprintf(stderr, "\n");
2202       }
2203       break;
2204    }
2205    case nir_op_u2u32: {
2206       Temp src = get_alu_src(ctx, instr->src[0]);
2207       if (instr->src[0].src.ssa->bit_size == 16) {
2208          if (dst.regClass() == s1) {
2209             bld.sop2(aco_opcode::s_and_b32, Definition(dst), bld.def(s1, scc), Operand(0xFFFFu), src);
2210          } else {
2211             // TODO: do better with SDWA
2212             bld.vop2(aco_opcode::v_and_b32, Definition(dst), Operand(0xFFFFu), src);
2213          }
2214       } else if (instr->src[0].src.ssa->bit_size == 64) {
2215          /* we can actually just say dst = src, as it would map the lower register */
2216          emit_extract_vector(ctx, src, 0, dst);
2217       } else {
2218          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2219          nir_print_instr(&instr->instr, stderr);
2220          fprintf(stderr, "\n");
2221       }
2222       break;
2223    }
2224    case nir_op_i2i64: {
2225       Temp src = get_alu_src(ctx, instr->src[0]);
2226       if (src.regClass() == s1) {
2227          Temp high = bld.sop2(aco_opcode::s_ashr_i32, bld.def(s1), bld.def(s1, scc), src, Operand(31u));
2228          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2229       } else if (src.regClass() == v1) {
2230          Temp high = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(31u), src);
2231          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, high);
2232       } else {
2233          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2234          nir_print_instr(&instr->instr, stderr);
2235          fprintf(stderr, "\n");
2236       }
2237       break;
2238    }
2239    case nir_op_u2u64: {
2240       Temp src = get_alu_src(ctx, instr->src[0]);
2241       if (instr->src[0].src.ssa->bit_size == 32) {
2242          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src, Operand(0u));
2243       } else {
2244          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2245          nir_print_instr(&instr->instr, stderr);
2246          fprintf(stderr, "\n");
2247       }
2248       break;
2249    }
2250    case nir_op_b2i32: {
2251       Temp src = get_alu_src(ctx, instr->src[0]);
2252       assert(src.regClass() == bld.lm);
2253
2254       if (dst.regClass() == s1) {
2255          // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2256          bool_to_scalar_condition(ctx, src, dst);
2257       } else if (dst.regClass() == v1) {
2258          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand(1u), src);
2259       } else {
2260          unreachable("Invalid register class for b2i32");
2261       }
2262       break;
2263    }
2264    case nir_op_i2b1: {
2265       Temp src = get_alu_src(ctx, instr->src[0]);
2266       assert(dst.regClass() == bld.lm);
2267
2268       if (src.type() == RegType::vgpr) {
2269          assert(src.regClass() == v1 || src.regClass() == v2);
2270          assert(dst.regClass() == bld.lm);
2271          bld.vopc(src.size() == 2 ? aco_opcode::v_cmp_lg_u64 : aco_opcode::v_cmp_lg_u32,
2272                   Definition(dst), Operand(0u), src).def(0).setHint(vcc);
2273       } else {
2274          assert(src.regClass() == s1 || src.regClass() == s2);
2275          Temp tmp;
2276          if (src.regClass() == s2 && ctx->program->chip_class <= GFX7) {
2277             tmp = bld.sop2(aco_opcode::s_or_b64, bld.def(s2), bld.def(s1, scc), Operand(0u), src).def(1).getTemp();
2278          } else {
2279             tmp = bld.sopc(src.size() == 2 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::s_cmp_lg_u32,
2280                            bld.scc(bld.def(s1)), Operand(0u), src);
2281          }
2282          bool_to_vector_condition(ctx, tmp, dst);
2283       }
2284       break;
2285    }
2286    case nir_op_pack_64_2x32_split: {
2287       Temp src0 = get_alu_src(ctx, instr->src[0]);
2288       Temp src1 = get_alu_src(ctx, instr->src[1]);
2289
2290       bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src0, src1);
2291       break;
2292    }
2293    case nir_op_unpack_64_2x32_split_x:
2294       bld.pseudo(aco_opcode::p_split_vector, Definition(dst), bld.def(dst.regClass()), get_alu_src(ctx, instr->src[0]));
2295       break;
2296    case nir_op_unpack_64_2x32_split_y:
2297       bld.pseudo(aco_opcode::p_split_vector, bld.def(dst.regClass()), Definition(dst), get_alu_src(ctx, instr->src[0]));
2298       break;
2299    case nir_op_pack_half_2x16: {
2300       Temp src = get_alu_src(ctx, instr->src[0], 2);
2301
2302       if (dst.regClass() == v1) {
2303          Temp src0 = bld.tmp(v1);
2304          Temp src1 = bld.tmp(v1);
2305          bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
2306          if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
2307             bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
2308          else
2309             bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
2310                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
2311                      bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
2312       } else {
2313          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2314          nir_print_instr(&instr->instr, stderr);
2315          fprintf(stderr, "\n");
2316       }
2317       break;
2318    }
2319    case nir_op_unpack_half_2x16_split_x: {
2320       if (dst.regClass() == v1) {
2321          Builder bld(ctx->program, ctx->block);
2322          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0]));
2323       } else {
2324          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2325          nir_print_instr(&instr->instr, stderr);
2326          fprintf(stderr, "\n");
2327       }
2328       break;
2329    }
2330    case nir_op_unpack_half_2x16_split_y: {
2331       if (dst.regClass() == v1) {
2332          Builder bld(ctx->program, ctx->block);
2333          /* TODO: use SDWA here */
2334          bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst),
2335                   bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0]))));
2336       } else {
2337          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2338          nir_print_instr(&instr->instr, stderr);
2339          fprintf(stderr, "\n");
2340       }
2341       break;
2342    }
2343    case nir_op_fquantize2f16: {
2344       Temp src = get_alu_src(ctx, instr->src[0]);
2345       Temp f16 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src);
2346       Temp f32, cmp_res;
2347
2348       if (ctx->program->chip_class >= GFX8) {
2349          Temp mask = bld.copy(bld.def(s1), Operand(0x36Fu)); /* value is NOT negative/positive denormal value */
2350          cmp_res = bld.vopc_e64(aco_opcode::v_cmp_class_f16, bld.hint_vcc(bld.def(bld.lm)), f16, mask);
2351          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2352       } else {
2353          /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2354           * so compare the result and flush to 0 if it's smaller.
2355           */
2356          f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
2357          Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
2358          Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
2359          static_cast<VOP3A_instruction*>(vop3)->abs[0] = true;
2360          cmp_res = vop3->definitions[0].getTemp();
2361       }
2362
2363       if (ctx->block->fp_mode.preserve_signed_zero_inf_nan32 || ctx->program->chip_class < GFX8) {
2364          Temp copysign_0 = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0u), as_vgpr(ctx, src));
2365          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), copysign_0, f32, cmp_res);
2366       } else {
2367          bld.vop2(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), f32, cmp_res);
2368       }
2369       break;
2370    }
2371    case nir_op_bfm: {
2372       Temp bits = get_alu_src(ctx, instr->src[0]);
2373       Temp offset = get_alu_src(ctx, instr->src[1]);
2374
2375       if (dst.regClass() == s1) {
2376          bld.sop2(aco_opcode::s_bfm_b32, Definition(dst), bits, offset);
2377       } else if (dst.regClass() == v1) {
2378          bld.vop3(aco_opcode::v_bfm_b32, Definition(dst), bits, offset);
2379       } else {
2380          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2381          nir_print_instr(&instr->instr, stderr);
2382          fprintf(stderr, "\n");
2383       }
2384       break;
2385    }
2386    case nir_op_bitfield_select: {
2387       /* (mask & insert) | (~mask & base) */
2388       Temp bitmask = get_alu_src(ctx, instr->src[0]);
2389       Temp insert = get_alu_src(ctx, instr->src[1]);
2390       Temp base = get_alu_src(ctx, instr->src[2]);
2391
2392       /* dst = (insert & bitmask) | (base & ~bitmask) */
2393       if (dst.regClass() == s1) {
2394          aco_ptr<Instruction> sop2;
2395          nir_const_value* const_bitmask = nir_src_as_const_value(instr->src[0].src);
2396          nir_const_value* const_insert = nir_src_as_const_value(instr->src[1].src);
2397          Operand lhs;
2398          if (const_insert && const_bitmask) {
2399             lhs = Operand(const_insert->u32 & const_bitmask->u32);
2400          } else {
2401             insert = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), insert, bitmask);
2402             lhs = Operand(insert);
2403          }
2404
2405          Operand rhs;
2406          nir_const_value* const_base = nir_src_as_const_value(instr->src[2].src);
2407          if (const_base && const_bitmask) {
2408             rhs = Operand(const_base->u32 & ~const_bitmask->u32);
2409          } else {
2410             base = bld.sop2(aco_opcode::s_andn2_b32, bld.def(s1), bld.def(s1, scc), base, bitmask);
2411             rhs = Operand(base);
2412          }
2413
2414          bld.sop2(aco_opcode::s_or_b32, Definition(dst), bld.def(s1, scc), rhs, lhs);
2415
2416       } else if (dst.regClass() == v1) {
2417          if (base.type() == RegType::sgpr && (bitmask.type() == RegType::sgpr || (insert.type() == RegType::sgpr)))
2418             base = as_vgpr(ctx, base);
2419          if (insert.type() == RegType::sgpr && bitmask.type() == RegType::sgpr)
2420             insert = as_vgpr(ctx, insert);
2421
2422          bld.vop3(aco_opcode::v_bfi_b32, Definition(dst), bitmask, insert, base);
2423
2424       } else {
2425          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2426          nir_print_instr(&instr->instr, stderr);
2427          fprintf(stderr, "\n");
2428       }
2429       break;
2430    }
2431    case nir_op_ubfe:
2432    case nir_op_ibfe: {
2433       Temp base = get_alu_src(ctx, instr->src[0]);
2434       Temp offset = get_alu_src(ctx, instr->src[1]);
2435       Temp bits = get_alu_src(ctx, instr->src[2]);
2436
2437       if (dst.type() == RegType::sgpr) {
2438          Operand extract;
2439          nir_const_value* const_offset = nir_src_as_const_value(instr->src[1].src);
2440          nir_const_value* const_bits = nir_src_as_const_value(instr->src[2].src);
2441          if (const_offset && const_bits) {
2442             uint32_t const_extract = (const_bits->u32 << 16) | const_offset->u32;
2443             extract = Operand(const_extract);
2444          } else {
2445             Operand width;
2446             if (const_bits) {
2447                width = Operand(const_bits->u32 << 16);
2448             } else {
2449                width = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), bits, Operand(16u));
2450             }
2451             extract = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), offset, width);
2452          }
2453
2454          aco_opcode opcode;
2455          if (dst.regClass() == s1) {
2456             if (instr->op == nir_op_ubfe)
2457                opcode = aco_opcode::s_bfe_u32;
2458             else
2459                opcode = aco_opcode::s_bfe_i32;
2460          } else if (dst.regClass() == s2) {
2461             if (instr->op == nir_op_ubfe)
2462                opcode = aco_opcode::s_bfe_u64;
2463             else
2464                opcode = aco_opcode::s_bfe_i64;
2465          } else {
2466             unreachable("Unsupported BFE bit size");
2467          }
2468
2469          bld.sop2(opcode, Definition(dst), bld.def(s1, scc), base, extract);
2470
2471       } else {
2472          aco_opcode opcode;
2473          if (dst.regClass() == v1) {
2474             if (instr->op == nir_op_ubfe)
2475                opcode = aco_opcode::v_bfe_u32;
2476             else
2477                opcode = aco_opcode::v_bfe_i32;
2478          } else {
2479             unreachable("Unsupported BFE bit size");
2480          }
2481
2482          emit_vop3a_instruction(ctx, instr, opcode, dst);
2483       }
2484       break;
2485    }
2486    case nir_op_bit_count: {
2487       Temp src = get_alu_src(ctx, instr->src[0]);
2488       if (src.regClass() == s1) {
2489          bld.sop1(aco_opcode::s_bcnt1_i32_b32, Definition(dst), bld.def(s1, scc), src);
2490       } else if (src.regClass() == v1) {
2491          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst), src, Operand(0u));
2492       } else if (src.regClass() == v2) {
2493          bld.vop3(aco_opcode::v_bcnt_u32_b32, Definition(dst),
2494                   emit_extract_vector(ctx, src, 1, v1),
2495                   bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1),
2496                            emit_extract_vector(ctx, src, 0, v1), Operand(0u)));
2497       } else if (src.regClass() == s2) {
2498          bld.sop1(aco_opcode::s_bcnt1_i32_b64, Definition(dst), bld.def(s1, scc), src);
2499       } else {
2500          fprintf(stderr, "Unimplemented NIR instr bit size: ");
2501          nir_print_instr(&instr->instr, stderr);
2502          fprintf(stderr, "\n");
2503       }
2504       break;
2505    }
2506    case nir_op_flt: {
2507       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_f32, aco_opcode::v_cmp_lt_f64);
2508       break;
2509    }
2510    case nir_op_fge: {
2511       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_f32, aco_opcode::v_cmp_ge_f64);
2512       break;
2513    }
2514    case nir_op_feq: {
2515       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_f32, aco_opcode::v_cmp_eq_f64);
2516       break;
2517    }
2518    case nir_op_fne: {
2519       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_neq_f32, aco_opcode::v_cmp_neq_f64);
2520       break;
2521    }
2522    case nir_op_ilt: {
2523       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_i32, aco_opcode::v_cmp_lt_i64, aco_opcode::s_cmp_lt_i32);
2524       break;
2525    }
2526    case nir_op_ige: {
2527       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_i32, aco_opcode::v_cmp_ge_i64, aco_opcode::s_cmp_ge_i32);
2528       break;
2529    }
2530    case nir_op_ieq: {
2531       if (instr->src[0].src.ssa->bit_size == 1)
2532          emit_boolean_logic(ctx, instr, Builder::s_xnor, dst);
2533       else
2534          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_eq_i32, aco_opcode::v_cmp_eq_i64, aco_opcode::s_cmp_eq_i32,
2535                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_eq_u64 : aco_opcode::num_opcodes);
2536       break;
2537    }
2538    case nir_op_ine: {
2539       if (instr->src[0].src.ssa->bit_size == 1)
2540          emit_boolean_logic(ctx, instr, Builder::s_xor, dst);
2541       else
2542          emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lg_i32, aco_opcode::v_cmp_lg_i64, aco_opcode::s_cmp_lg_i32,
2543                          ctx->program->chip_class >= GFX8 ? aco_opcode::s_cmp_lg_u64 : aco_opcode::num_opcodes);
2544       break;
2545    }
2546    case nir_op_ult: {
2547       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_lt_u32, aco_opcode::v_cmp_lt_u64, aco_opcode::s_cmp_lt_u32);
2548       break;
2549    }
2550    case nir_op_uge: {
2551       emit_comparison(ctx, instr, dst, aco_opcode::v_cmp_ge_u32, aco_opcode::v_cmp_ge_u64, aco_opcode::s_cmp_ge_u32);
2552       break;
2553    }
2554    case nir_op_fddx:
2555    case nir_op_fddy:
2556    case nir_op_fddx_fine:
2557    case nir_op_fddy_fine:
2558    case nir_op_fddx_coarse:
2559    case nir_op_fddy_coarse: {
2560       Temp src = get_alu_src(ctx, instr->src[0]);
2561       uint16_t dpp_ctrl1, dpp_ctrl2;
2562       if (instr->op == nir_op_fddx_fine) {
2563          dpp_ctrl1 = dpp_quad_perm(0, 0, 2, 2);
2564          dpp_ctrl2 = dpp_quad_perm(1, 1, 3, 3);
2565       } else if (instr->op == nir_op_fddy_fine) {
2566          dpp_ctrl1 = dpp_quad_perm(0, 1, 0, 1);
2567          dpp_ctrl2 = dpp_quad_perm(2, 3, 2, 3);
2568       } else {
2569          dpp_ctrl1 = dpp_quad_perm(0, 0, 0, 0);
2570          if (instr->op == nir_op_fddx || instr->op == nir_op_fddx_coarse)
2571             dpp_ctrl2 = dpp_quad_perm(1, 1, 1, 1);
2572          else
2573             dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
2574       }
2575
2576       Temp tmp;
2577       if (ctx->program->chip_class >= GFX8) {
2578          Temp tl = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl1);
2579          tmp = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), src, tl, dpp_ctrl2);
2580       } else {
2581          Temp tl = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl1);
2582          Temp tr = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl2);
2583          tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), tr, tl);
2584       }
2585       emit_wqm(ctx, tmp, dst, true);
2586       break;
2587    }
2588    default:
2589       fprintf(stderr, "Unknown NIR ALU instr: ");
2590       nir_print_instr(&instr->instr, stderr);
2591       fprintf(stderr, "\n");
2592    }
2593 }
2594
2595 void visit_load_const(isel_context *ctx, nir_load_const_instr *instr)
2596 {
2597    Temp dst = get_ssa_temp(ctx, &instr->def);
2598
2599    // TODO: we really want to have the resulting type as this would allow for 64bit literals
2600    // which get truncated the lsb if double and msb if int
2601    // for now, we only use s_mov_b64 with 64bit inline constants
2602    assert(instr->def.num_components == 1 && "Vector load_const should be lowered to scalar.");
2603    assert(dst.type() == RegType::sgpr);
2604
2605    Builder bld(ctx->program, ctx->block);
2606
2607    if (instr->def.bit_size == 1) {
2608       assert(dst.regClass() == bld.lm);
2609       int val = instr->value[0].b ? -1 : 0;
2610       Operand op = bld.lm.size() == 1 ? Operand((uint32_t) val) : Operand((uint64_t) val);
2611       bld.sop1(Builder::s_mov, Definition(dst), op);
2612    } else if (dst.size() == 1) {
2613       bld.copy(Definition(dst), Operand(instr->value[0].u32));
2614    } else {
2615       assert(dst.size() != 1);
2616       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
2617       if (instr->def.bit_size == 64)
2618          for (unsigned i = 0; i < dst.size(); i++)
2619             vec->operands[i] = Operand{(uint32_t)(instr->value[0].u64 >> i * 32)};
2620       else {
2621          for (unsigned i = 0; i < dst.size(); i++)
2622             vec->operands[i] = Operand{instr->value[i].u32};
2623       }
2624       vec->definitions[0] = Definition(dst);
2625       ctx->block->instructions.emplace_back(std::move(vec));
2626    }
2627 }
2628
2629 uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2630 {
2631    uint32_t new_mask = 0;
2632    for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2633       if (mask & (1u << i))
2634          new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2635    return new_mask;
2636 }
2637
2638 Operand load_lds_size_m0(isel_context *ctx)
2639 {
2640    /* TODO: m0 does not need to be initialized on GFX9+ */
2641    Builder bld(ctx->program, ctx->block);
2642    return bld.m0((Temp)bld.sopk(aco_opcode::s_movk_i32, bld.def(s1, m0), 0xffff));
2643 }
2644
2645 Temp load_lds(isel_context *ctx, unsigned elem_size_bytes, Temp dst,
2646               Temp address, unsigned base_offset, unsigned align)
2647 {
2648    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2649
2650    Builder bld(ctx->program, ctx->block);
2651
2652    Operand m = load_lds_size_m0(ctx);
2653
2654    unsigned num_components = dst.size() * 4u / elem_size_bytes;
2655    unsigned bytes_read = 0;
2656    unsigned result_size = 0;
2657    unsigned total_bytes = num_components * elem_size_bytes;
2658    std::array<Temp, NIR_MAX_VEC_COMPONENTS> result;
2659    bool large_ds_read = ctx->options->chip_class >= GFX7;
2660    bool usable_read2 = ctx->options->chip_class >= GFX7;
2661
2662    while (bytes_read < total_bytes) {
2663       unsigned todo = total_bytes - bytes_read;
2664       bool aligned8 = bytes_read % 8 == 0 && align % 8 == 0;
2665       bool aligned16 = bytes_read % 16 == 0 && align % 16 == 0;
2666
2667       aco_opcode op = aco_opcode::last_opcode;
2668       bool read2 = false;
2669       if (todo >= 16 && aligned16 && large_ds_read) {
2670          op = aco_opcode::ds_read_b128;
2671          todo = 16;
2672       } else if (todo >= 16 && aligned8 && usable_read2) {
2673          op = aco_opcode::ds_read2_b64;
2674          read2 = true;
2675          todo = 16;
2676       } else if (todo >= 12 && aligned16 && large_ds_read) {
2677          op = aco_opcode::ds_read_b96;
2678          todo = 12;
2679       } else if (todo >= 8 && aligned8) {
2680          op = aco_opcode::ds_read_b64;
2681          todo = 8;
2682       } else if (todo >= 8 && usable_read2) {
2683          op = aco_opcode::ds_read2_b32;
2684          read2 = true;
2685          todo = 8;
2686       } else if (todo >= 4) {
2687          op = aco_opcode::ds_read_b32;
2688          todo = 4;
2689       } else {
2690          assert(false);
2691       }
2692       assert(todo % elem_size_bytes == 0);
2693       unsigned num_elements = todo / elem_size_bytes;
2694       unsigned offset = base_offset + bytes_read;
2695       unsigned max_offset = read2 ? 1019 : 65535;
2696
2697       Temp address_offset = address;
2698       if (offset > max_offset) {
2699          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2700          offset = bytes_read;
2701       }
2702       assert(offset <= max_offset); /* bytes_read shouldn't be large enough for this to happen */
2703
2704       Temp res;
2705       if (num_components == 1 && dst.type() == RegType::vgpr)
2706          res = dst;
2707       else
2708          res = bld.tmp(RegClass(RegType::vgpr, todo / 4));
2709
2710       if (read2)
2711          res = bld.ds(op, Definition(res), address_offset, m, offset / (todo / 2), (offset / (todo / 2)) + 1);
2712       else
2713          res = bld.ds(op, Definition(res), address_offset, m, offset);
2714
2715       if (num_components == 1) {
2716          assert(todo == total_bytes);
2717          if (dst.type() == RegType::sgpr)
2718             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), res);
2719          return dst;
2720       }
2721
2722       if (dst.type() == RegType::sgpr) {
2723          Temp new_res = bld.tmp(RegType::sgpr, res.size());
2724          expand_vector(ctx, res, new_res, res.size(), (1 << res.size()) - 1);
2725          res = new_res;
2726       }
2727
2728       if (num_elements == 1) {
2729          result[result_size++] = res;
2730       } else {
2731          assert(res != dst && res.size() % num_elements == 0);
2732          aco_ptr<Pseudo_instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector, Format::PSEUDO, 1, num_elements)};
2733          split->operands[0] = Operand(res);
2734          for (unsigned i = 0; i < num_elements; i++)
2735             split->definitions[i] = Definition(result[result_size++] = bld.tmp(res.type(), elem_size_bytes / 4));
2736          ctx->block->instructions.emplace_back(std::move(split));
2737       }
2738
2739       bytes_read += todo;
2740    }
2741
2742    assert(result_size == num_components && result_size > 1);
2743    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, result_size, 1)};
2744    for (unsigned i = 0; i < result_size; i++)
2745       vec->operands[i] = Operand(result[i]);
2746    vec->definitions[0] = Definition(dst);
2747    ctx->block->instructions.emplace_back(std::move(vec));
2748    ctx->allocated_vec.emplace(dst.id(), result);
2749
2750    return dst;
2751 }
2752
2753 Temp extract_subvector(isel_context *ctx, Temp data, unsigned start, unsigned size, RegType type)
2754 {
2755    if (start == 0 && size == data.size())
2756       return type == RegType::vgpr ? as_vgpr(ctx, data) : data;
2757
2758    unsigned size_hint = 1;
2759    auto it = ctx->allocated_vec.find(data.id());
2760    if (it != ctx->allocated_vec.end())
2761       size_hint = it->second[0].size();
2762    if (size % size_hint || start % size_hint)
2763       size_hint = 1;
2764
2765    start /= size_hint;
2766    size /= size_hint;
2767
2768    Temp elems[size];
2769    for (unsigned i = 0; i < size; i++)
2770       elems[i] = emit_extract_vector(ctx, data, start + i, RegClass(type, size_hint));
2771
2772    if (size == 1)
2773       return type == RegType::vgpr ? as_vgpr(ctx, elems[0]) : elems[0];
2774
2775    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, size, 1)};
2776    for (unsigned i = 0; i < size; i++)
2777       vec->operands[i] = Operand(elems[i]);
2778    Temp res = {ctx->program->allocateId(), RegClass(type, size * size_hint)};
2779    vec->definitions[0] = Definition(res);
2780    ctx->block->instructions.emplace_back(std::move(vec));
2781    return res;
2782 }
2783
2784 void ds_write_helper(isel_context *ctx, Operand m, Temp address, Temp data, unsigned data_start, unsigned total_size, unsigned offset0, unsigned offset1, unsigned align)
2785 {
2786    Builder bld(ctx->program, ctx->block);
2787    unsigned bytes_written = 0;
2788    bool large_ds_write = ctx->options->chip_class >= GFX7;
2789    bool usable_write2 = ctx->options->chip_class >= GFX7;
2790
2791    while (bytes_written < total_size * 4) {
2792       unsigned todo = total_size * 4 - bytes_written;
2793       bool aligned8 = bytes_written % 8 == 0 && align % 8 == 0;
2794       bool aligned16 = bytes_written % 16 == 0 && align % 16 == 0;
2795
2796       aco_opcode op = aco_opcode::last_opcode;
2797       bool write2 = false;
2798       unsigned size = 0;
2799       if (todo >= 16 && aligned16 && large_ds_write) {
2800          op = aco_opcode::ds_write_b128;
2801          size = 4;
2802       } else if (todo >= 16 && aligned8 && usable_write2) {
2803          op = aco_opcode::ds_write2_b64;
2804          write2 = true;
2805          size = 4;
2806       } else if (todo >= 12 && aligned16 && large_ds_write) {
2807          op = aco_opcode::ds_write_b96;
2808          size = 3;
2809       } else if (todo >= 8 && aligned8) {
2810          op = aco_opcode::ds_write_b64;
2811          size = 2;
2812       } else if (todo >= 8 && usable_write2) {
2813          op = aco_opcode::ds_write2_b32;
2814          write2 = true;
2815          size = 2;
2816       } else if (todo >= 4) {
2817          op = aco_opcode::ds_write_b32;
2818          size = 1;
2819       } else {
2820          assert(false);
2821       }
2822
2823       unsigned offset = offset0 + offset1 + bytes_written;
2824       unsigned max_offset = write2 ? 1020 : 65535;
2825       Temp address_offset = address;
2826       if (offset > max_offset) {
2827          address_offset = bld.vadd32(bld.def(v1), Operand(offset0), address_offset);
2828          offset = offset1 + bytes_written;
2829       }
2830       assert(offset <= max_offset); /* offset1 shouldn't be large enough for this to happen */
2831
2832       if (write2) {
2833          Temp val0 = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size / 2, RegType::vgpr);
2834          Temp val1 = extract_subvector(ctx, data, data_start + (bytes_written >> 2) + 1, size / 2, RegType::vgpr);
2835          bld.ds(op, address_offset, val0, val1, m, offset / size / 2, (offset / size / 2) + 1);
2836       } else {
2837          Temp val = extract_subvector(ctx, data, data_start + (bytes_written >> 2), size, RegType::vgpr);
2838          bld.ds(op, address_offset, val, m, offset);
2839       }
2840
2841       bytes_written += size * 4;
2842    }
2843 }
2844
2845 void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t wrmask,
2846                Temp address, unsigned base_offset, unsigned align)
2847 {
2848    assert(util_is_power_of_two_nonzero(align) && align >= 4);
2849    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2850
2851    Operand m = load_lds_size_m0(ctx);
2852
2853    /* we need at most two stores, assuming that the writemask is at most 4 bits wide */
2854    assert(wrmask <= 0x0f);
2855    int start[2], count[2];
2856    u_bit_scan_consecutive_range(&wrmask, &start[0], &count[0]);
2857    u_bit_scan_consecutive_range(&wrmask, &start[1], &count[1]);
2858    assert(wrmask == 0);
2859
2860    /* one combined store is sufficient */
2861    if (count[0] == count[1] && (align % elem_size_bytes) == 0 && (base_offset % elem_size_bytes) == 0) {
2862       Builder bld(ctx->program, ctx->block);
2863
2864       Temp address_offset = address;
2865       if ((base_offset / elem_size_bytes) + start[1] > 255) {
2866          address_offset = bld.vadd32(bld.def(v1), Operand(base_offset), address_offset);
2867          base_offset = 0;
2868       }
2869
2870       assert(count[0] == 1);
2871       RegClass xtract_rc(RegType::vgpr, elem_size_bytes / 4);
2872
2873       Temp val0 = emit_extract_vector(ctx, data, start[0], xtract_rc);
2874       Temp val1 = emit_extract_vector(ctx, data, start[1], xtract_rc);
2875       aco_opcode op = elem_size_bytes == 4 ? aco_opcode::ds_write2_b32 : aco_opcode::ds_write2_b64;
2876       base_offset = base_offset / elem_size_bytes;
2877       bld.ds(op, address_offset, val0, val1, m,
2878              base_offset + start[0], base_offset + start[1]);
2879       return;
2880    }
2881
2882    for (unsigned i = 0; i < 2; i++) {
2883       if (count[i] == 0)
2884          continue;
2885
2886       unsigned elem_size_words = elem_size_bytes / 4;
2887       ds_write_helper(ctx, m, address, data, start[i] * elem_size_words, count[i] * elem_size_words,
2888                       base_offset, start[i] * elem_size_bytes, align);
2889    }
2890    return;
2891 }
2892
2893 unsigned calculate_lds_alignment(isel_context *ctx, unsigned const_offset)
2894 {
2895    unsigned align = 16;
2896    if (const_offset)
2897       align = std::min(align, 1u << (ffs(const_offset) - 1));
2898
2899    return align;
2900 }
2901
2902
2903 Temp create_vec_from_array(isel_context *ctx, Temp arr[], unsigned cnt, RegType reg_type, unsigned split_cnt = 0u, Temp dst = Temp())
2904 {
2905    Builder bld(ctx->program, ctx->block);
2906
2907    if (!dst.id())
2908       dst = bld.tmp(RegClass(reg_type, cnt * arr[0].size()));
2909
2910    std::array<Temp, NIR_MAX_VEC_COMPONENTS> allocated_vec;
2911    aco_ptr<Pseudo_instruction> instr {create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, cnt, 1)};
2912    instr->definitions[0] = Definition(dst);
2913
2914    for (unsigned i = 0; i < cnt; ++i) {
2915       assert(arr[i].size() == arr[0].size());
2916       allocated_vec[i] = arr[i];
2917       instr->operands[i] = Operand(arr[i]);
2918    }
2919
2920    bld.insert(std::move(instr));
2921
2922    if (split_cnt)
2923       emit_split_vector(ctx, dst, split_cnt);
2924    else
2925       ctx->allocated_vec.emplace(dst.id(), allocated_vec); /* emit_split_vector already does this */
2926
2927    return dst;
2928 }
2929
2930 inline unsigned resolve_excess_vmem_const_offset(Builder &bld, Temp &voffset, unsigned const_offset)
2931 {
2932    if (const_offset >= 4096) {
2933       unsigned excess_const_offset = const_offset / 4096u * 4096u;
2934       const_offset %= 4096u;
2935
2936       if (!voffset.id())
2937          voffset = bld.copy(bld.def(v1), Operand(excess_const_offset));
2938       else if (unlikely(voffset.regClass() == s1))
2939          voffset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), Operand(excess_const_offset), Operand(voffset));
2940       else if (likely(voffset.regClass() == v1))
2941          voffset = bld.vadd32(bld.def(v1), Operand(voffset), Operand(excess_const_offset));
2942       else
2943          unreachable("Unsupported register class of voffset");
2944    }
2945
2946    return const_offset;
2947 }
2948
2949 void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset, Temp vdata,
2950                              unsigned const_offset = 0u, bool allow_reorder = true, bool slc = false)
2951 {
2952    assert(vdata.id());
2953    assert(vdata.size() != 3 || ctx->program->chip_class != GFX6);
2954    assert(vdata.size() >= 1 && vdata.size() <= 4);
2955
2956    Builder bld(ctx->program, ctx->block);
2957    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_store_dword + vdata.size() - 1);
2958    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
2959
2960    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
2961    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
2962    Builder::Result r = bld.mubuf(op, Operand(descriptor), voffset_op, soffset_op, Operand(vdata), const_offset,
2963                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
2964                                  /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc);
2965
2966    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
2967 }
2968
2969 void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
2970                                    unsigned base_const_offset, unsigned elem_size_bytes, unsigned write_mask,
2971                                    bool allow_combining = true, bool reorder = true, bool slc = false)
2972 {
2973    Builder bld(ctx->program, ctx->block);
2974    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
2975    assert(write_mask);
2976
2977    if (elem_size_bytes == 8) {
2978       elem_size_bytes = 4;
2979       write_mask = widen_mask(write_mask, 2);
2980    }
2981
2982    while (write_mask) {
2983       int start = 0;
2984       int count = 0;
2985       u_bit_scan_consecutive_range(&write_mask, &start, &count);
2986       assert(count > 0);
2987       assert(start >= 0);
2988
2989       while (count > 0) {
2990          unsigned sub_count = allow_combining ? MIN2(count, 4) : 1;
2991          unsigned const_offset = (unsigned) start * elem_size_bytes + base_const_offset;
2992
2993          /* GFX6 doesn't have buffer_store_dwordx3, so make sure not to emit that here either. */
2994          if (unlikely(ctx->program->chip_class == GFX6 && sub_count == 3))
2995             sub_count = 2;
2996
2997          Temp elem = extract_subvector(ctx, src, start, sub_count, RegType::vgpr);
2998          emit_single_mubuf_store(ctx, descriptor, voffset, soffset, elem, const_offset, reorder, slc);
2999
3000          count -= sub_count;
3001          start += sub_count;
3002       }
3003
3004       assert(count == 0);
3005    }
3006 }
3007
3008 Temp emit_single_mubuf_load(isel_context *ctx, Temp descriptor, Temp voffset, Temp soffset,
3009                             unsigned const_offset, unsigned size_dwords, bool allow_reorder = true)
3010 {
3011    assert(size_dwords != 3 || ctx->program->chip_class != GFX6);
3012    assert(size_dwords >= 1 && size_dwords <= 4);
3013
3014    Builder bld(ctx->program, ctx->block);
3015    Temp vdata = bld.tmp(RegClass(RegType::vgpr, size_dwords));
3016    aco_opcode op = (aco_opcode) ((unsigned) aco_opcode::buffer_load_dword + size_dwords - 1);
3017    const_offset = resolve_excess_vmem_const_offset(bld, voffset, const_offset);
3018
3019    Operand voffset_op = voffset.id() ? Operand(as_vgpr(ctx, voffset)) : Operand(v1);
3020    Operand soffset_op = soffset.id() ? Operand(soffset) : Operand(0u);
3021    Builder::Result r = bld.mubuf(op, Definition(vdata), Operand(descriptor), voffset_op, soffset_op, const_offset,
3022                                  /* offen */ !voffset_op.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3023                                  /* disable_wqm */ false, /* glc */ true,
3024                                  /* dlc*/ ctx->program->chip_class >= GFX10, /* slc */ false);
3025
3026    static_cast<MUBUF_instruction *>(r.instr)->can_reorder = allow_reorder;
3027
3028    return vdata;
3029 }
3030
3031 void load_vmem_mubuf(isel_context *ctx, Temp dst, Temp descriptor, Temp voffset, Temp soffset,
3032                      unsigned base_const_offset, unsigned elem_size_bytes, unsigned num_components,
3033                      unsigned stride = 0u, bool allow_combining = true, bool allow_reorder = true)
3034 {
3035    assert(elem_size_bytes == 4 || elem_size_bytes == 8);
3036    assert((num_components * elem_size_bytes / 4) == dst.size());
3037    assert(!!stride != allow_combining);
3038
3039    Builder bld(ctx->program, ctx->block);
3040    unsigned split_cnt = num_components;
3041
3042    if (elem_size_bytes == 8) {
3043       elem_size_bytes = 4;
3044       num_components *= 2;
3045    }
3046
3047    if (!stride)
3048       stride = elem_size_bytes;
3049
3050    unsigned load_size = 1;
3051    if (allow_combining) {
3052       if ((num_components % 4) == 0)
3053          load_size = 4;
3054       else if ((num_components % 3) == 0 && ctx->program->chip_class != GFX6)
3055          load_size = 3;
3056       else if ((num_components % 2) == 0)
3057          load_size = 2;
3058    }
3059
3060    unsigned num_loads = num_components / load_size;
3061    std::array<Temp, NIR_MAX_VEC_COMPONENTS> elems;
3062
3063    for (unsigned i = 0; i < num_loads; ++i) {
3064       unsigned const_offset = i * stride * load_size + base_const_offset;
3065       elems[i] = emit_single_mubuf_load(ctx, descriptor, voffset, soffset, const_offset, load_size, allow_reorder);
3066    }
3067
3068    create_vec_from_array(ctx, elems.data(), num_loads, RegType::vgpr, split_cnt, dst);
3069 }
3070
3071 std::pair<Temp, unsigned> offset_add_from_nir(isel_context *ctx, const std::pair<Temp, unsigned> &base_offset, nir_src *off_src, unsigned stride = 1u)
3072 {
3073    Builder bld(ctx->program, ctx->block);
3074    Temp offset = base_offset.first;
3075    unsigned const_offset = base_offset.second;
3076
3077    if (!nir_src_is_const(*off_src)) {
3078       Temp indirect_offset_arg = get_ssa_temp(ctx, off_src->ssa);
3079       Temp with_stride;
3080
3081       /* Calculate indirect offset with stride */
3082       if (likely(indirect_offset_arg.regClass() == v1))
3083          with_stride = bld.v_mul_imm(bld.def(v1), indirect_offset_arg, stride);
3084       else if (indirect_offset_arg.regClass() == s1)
3085          with_stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), indirect_offset_arg);
3086       else
3087          unreachable("Unsupported register class of indirect offset");
3088
3089       /* Add to the supplied base offset */
3090       if (offset.id() == 0)
3091          offset = with_stride;
3092       else if (unlikely(offset.regClass() == s1 && with_stride.regClass() == s1))
3093          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), with_stride, offset);
3094       else if (offset.size() == 1 && with_stride.size() == 1)
3095          offset = bld.vadd32(bld.def(v1), with_stride, offset);
3096       else
3097          unreachable("Unsupported register class of indirect offset");
3098    } else {
3099       unsigned const_offset_arg = nir_src_as_uint(*off_src);
3100       const_offset += const_offset_arg * stride;
3101    }
3102
3103    return std::make_pair(offset, const_offset);
3104 }
3105
3106 std::pair<Temp, unsigned> offset_add(isel_context *ctx, const std::pair<Temp, unsigned> &off1, const std::pair<Temp, unsigned> &off2)
3107 {
3108    Builder bld(ctx->program, ctx->block);
3109    Temp offset;
3110
3111    if (off1.first.id() && off2.first.id()) {
3112       if (unlikely(off1.first.regClass() == s1 && off2.first.regClass() == s1))
3113          offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), off1.first, off2.first);
3114       else if (off1.first.size() == 1 && off2.first.size() == 1)
3115          offset = bld.vadd32(bld.def(v1), off1.first, off2.first);
3116       else
3117          unreachable("Unsupported register class of indirect offset");
3118    } else {
3119       offset = off1.first.id() ? off1.first : off2.first;
3120    }
3121
3122    return std::make_pair(offset, off1.second + off2.second);
3123 }
3124
3125 std::pair<Temp, unsigned> offset_mul(isel_context *ctx, const std::pair<Temp, unsigned> &offs, unsigned multiplier)
3126 {
3127    Builder bld(ctx->program, ctx->block);
3128    unsigned const_offset = offs.second * multiplier;
3129
3130    if (!offs.first.id())
3131       return std::make_pair(offs.first, const_offset);
3132
3133    Temp offset = unlikely(offs.first.regClass() == s1)
3134                  ? bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(multiplier), offs.first)
3135                  : bld.v_mul_imm(bld.def(v1), offs.first, multiplier);
3136
3137    return std::make_pair(offset, const_offset);
3138 }
3139
3140 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride, unsigned component_stride)
3141 {
3142    Builder bld(ctx->program, ctx->block);
3143
3144    /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3145    unsigned const_offset = nir_intrinsic_base(instr) * base_stride;
3146    /* component is in bytes */
3147    const_offset += nir_intrinsic_component(instr) * component_stride;
3148
3149    /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3150    nir_src *off_src = nir_get_io_offset_src(instr);
3151    return offset_add_from_nir(ctx, std::make_pair(Temp(), const_offset), off_src, 4u * base_stride);
3152 }
3153
3154 std::pair<Temp, unsigned> get_intrinsic_io_basic_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned stride = 1u)
3155 {
3156    return get_intrinsic_io_basic_offset(ctx, instr, stride, stride);
3157 }
3158
3159 Temp get_tess_rel_patch_id(isel_context *ctx)
3160 {
3161    Builder bld(ctx->program, ctx->block);
3162
3163    switch (ctx->shader->info.stage) {
3164    case MESA_SHADER_TESS_CTRL:
3165       return bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffu),
3166                       get_arg(ctx, ctx->args->ac.tcs_rel_ids));
3167    case MESA_SHADER_TESS_EVAL:
3168       return get_arg(ctx, ctx->args->tes_rel_patch_id);
3169    default:
3170       unreachable("Unsupported stage in get_tess_rel_patch_id");
3171    }
3172 }
3173
3174 std::pair<Temp, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3175 {
3176    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3177    Builder bld(ctx->program, ctx->block);
3178
3179    uint32_t tcs_in_patch_stride = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 4;
3180    uint32_t tcs_in_vertex_stride = ctx->tcs_num_inputs * 4;
3181
3182    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr);
3183
3184    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3185    offs = offset_add_from_nir(ctx, offs, vertex_index_src, tcs_in_vertex_stride);
3186
3187    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3188    Temp tcs_in_current_patch_offset = bld.v_mul24_imm(bld.def(v1), rel_patch_id, tcs_in_patch_stride);
3189    offs = offset_add(ctx, offs, std::make_pair(tcs_in_current_patch_offset, 0));
3190
3191    return offset_mul(ctx, offs, 4u);
3192 }
3193
3194 std::pair<Temp, unsigned> get_tcs_output_lds_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, bool per_vertex = false)
3195 {
3196    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3197    Builder bld(ctx->program, ctx->block);
3198
3199    uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * ctx->tcs_num_inputs * 16;
3200    uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
3201    uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
3202    uint32_t output_vertex_size = num_tcs_outputs * 16;
3203    uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3204    uint32_t output_patch_stride = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
3205
3206    std::pair<Temp, unsigned> offs = instr
3207                                     ? get_intrinsic_io_basic_offset(ctx, instr, 4u)
3208                                     : std::make_pair(Temp(), 0u);
3209
3210    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3211    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, output_patch_stride);
3212
3213    if (per_vertex) {
3214       assert(instr);
3215
3216       nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3217       offs = offset_add_from_nir(ctx, offs, vertex_index_src, output_vertex_size);
3218
3219       uint32_t output_patch0_offset = (input_patch_size * ctx->tcs_num_patches);
3220       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_offset));
3221    } else {
3222       uint32_t output_patch0_patch_data_offset = (input_patch_size * ctx->tcs_num_patches + pervertex_output_patch_size);
3223       offs = offset_add(ctx, offs, std::make_pair(patch_off, output_patch0_patch_data_offset));
3224    }
3225
3226    return offs;
3227 }
3228
3229 std::pair<Temp, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr)
3230 {
3231    Builder bld(ctx->program, ctx->block);
3232
3233    unsigned vertices_per_patch = ctx->shader->info.tess.tcs_vertices_out;
3234    unsigned attr_stride = vertices_per_patch * ctx->tcs_num_patches;
3235
3236    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u);
3237
3238    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3239    Temp patch_off = bld.v_mul24_imm(bld.def(v1), rel_patch_id, vertices_per_patch * 16u);
3240    offs = offset_add(ctx, offs, std::make_pair(patch_off, 0u));
3241
3242    nir_src *vertex_index_src = nir_get_io_vertex_index_src(instr);
3243    offs = offset_add_from_nir(ctx, offs, vertex_index_src, 16u);
3244
3245    return offs;
3246 }
3247
3248 std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx, nir_intrinsic_instr *instr = nullptr, unsigned const_base_offset = 0u)
3249 {
3250    Builder bld(ctx->program, ctx->block);
3251
3252    unsigned num_tcs_outputs = ctx->shader->info.stage == MESA_SHADER_TESS_CTRL
3253                               ? util_last_bit64(ctx->args->shader_info->tcs.outputs_written)
3254                               : ctx->args->options->key.tes.tcs_num_outputs;
3255
3256    unsigned output_vertex_size = num_tcs_outputs * 16;
3257    unsigned per_vertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
3258    unsigned per_patch_data_offset = per_vertex_output_patch_size * ctx->tcs_num_patches;
3259    unsigned attr_stride = ctx->tcs_num_patches;
3260
3261    std::pair<Temp, unsigned> offs = instr
3262                                     ? get_intrinsic_io_basic_offset(ctx, instr, attr_stride * 4u, 4u)
3263                                     : std::make_pair(Temp(), 0u);
3264
3265    if (const_base_offset)
3266       offs.second += const_base_offset * attr_stride;
3267
3268    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
3269    Temp patch_off = bld.v_mul_imm(bld.def(v1), rel_patch_id, 16u);
3270    offs = offset_add(ctx, offs, std::make_pair(patch_off, per_patch_data_offset));
3271
3272    return offs;
3273 }
3274
3275 bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex, uint64_t mask, bool *indirect)
3276 {
3277    unsigned off = nir_intrinsic_base(instr) * 4u;
3278    nir_src *off_src = nir_get_io_offset_src(instr);
3279
3280    if (!nir_src_is_const(*off_src)) {
3281       *indirect = true;
3282       return false;
3283    }
3284
3285    *indirect = false;
3286    off += nir_src_as_uint(*off_src) * 16u;
3287
3288    while (mask) {
3289       unsigned slot = u_bit_scan64(&mask) + (per_vertex ? 0 : VARYING_SLOT_PATCH0);
3290       if (off == shader_io_get_unique_index((gl_varying_slot) slot) * 16u)
3291          return true;
3292    }
3293
3294    return false;
3295 }
3296
3297 void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
3298 {
3299    Builder bld(ctx->program, ctx->block);
3300
3301    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, 4u);
3302    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3303    unsigned write_mask = nir_intrinsic_write_mask(instr);
3304    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8u;
3305
3306    if (ctx->stage == vertex_es || ctx->stage == tess_eval_es) {
3307       /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
3308       Temp esgs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_VS * 16u));
3309       Temp es2gs_offset = get_arg(ctx, ctx->args->es2gs_offset);
3310       store_vmem_mubuf(ctx, src, esgs_ring, offs.first, es2gs_offset, offs.second, elem_size_bytes, write_mask, false, true, true);
3311    } else {
3312       Temp lds_base;
3313
3314       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3315          /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
3316          unsigned itemsize = ctx->stage == vertex_geometry_gs
3317                              ? ctx->program->info->vs.es_info.esgs_itemsize
3318                              : ctx->program->info->tes.es_info.esgs_itemsize;
3319          Temp thread_id = emit_mbcnt(ctx, bld.def(v1));
3320          Temp wave_idx = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(ctx, ctx->args->merged_wave_info), Operand(4u << 16 | 24));
3321          Temp vertex_idx = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), thread_id,
3322                                bld.v_mul24_imm(bld.def(v1), as_vgpr(ctx, wave_idx), ctx->program->wave_size));
3323          lds_base = bld.v_mul24_imm(bld.def(v1), vertex_idx, itemsize);
3324       } else if (ctx->stage == vertex_ls || ctx->stage == vertex_tess_control_hs) {
3325          /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
3326           * GFX9+: LS is merged into HS, but still uses the same LDS layout.
3327           */
3328          unsigned num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
3329          Temp vertex_idx = get_arg(ctx, ctx->args->rel_auto_id);
3330          lds_base = bld.v_mul_imm(bld.def(v1), vertex_idx, num_tcs_inputs * 16u);
3331       } else {
3332          unreachable("Invalid LS or ES stage");
3333       }
3334
3335       offs = offset_add(ctx, offs, std::make_pair(lds_base, 0u));
3336       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3337       store_lds(ctx, elem_size_bytes, src, write_mask, offs.first, offs.second, lds_align);
3338    }
3339 }
3340
3341 bool should_write_tcs_patch_output_to_vmem(isel_context *ctx, nir_intrinsic_instr *instr)
3342 {
3343    unsigned off = nir_intrinsic_base(instr) * 4u;
3344    nir_src *off_src = nir_get_io_offset_src(instr);
3345
3346    /* Indirect offset, we can't be sure if this is a tess factor, always write to VMEM */
3347    if (!nir_src_is_const(*off_src))
3348       return true;
3349
3350    off += nir_src_as_uint(*off_src) * 16u;
3351
3352    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3353    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3354
3355    return (off != (tess_index_inner * 16u)) &&
3356           (off != (tess_index_outer * 16u));
3357 }
3358
3359 bool should_write_tcs_output_to_lds(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3360 {
3361    /* When none of the appropriate outputs are read, we are OK to never write to LDS */
3362    if (per_vertex ? ctx->shader->info.outputs_read == 0U : ctx->shader->info.patch_outputs_read == 0u)
3363       return false;
3364
3365    uint64_t mask = per_vertex
3366                    ? ctx->shader->info.outputs_read
3367                    : ctx->shader->info.patch_outputs_read;
3368    bool indirect_write;
3369    bool output_read = tcs_driver_location_matches_api_mask(ctx, instr, per_vertex, mask, &indirect_write);
3370    return indirect_write || output_read;
3371 }
3372
3373 void visit_store_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3374 {
3375    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3376    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3377
3378    Builder bld(ctx->program, ctx->block);
3379
3380    Temp store_val = get_ssa_temp(ctx, instr->src[0].ssa);
3381    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3382    unsigned write_mask = nir_intrinsic_write_mask(instr);
3383
3384    /* Only write to VMEM if the output is per-vertex or it's per-patch non tess factor */
3385    bool write_to_vmem = per_vertex || should_write_tcs_patch_output_to_vmem(ctx, instr);
3386    /* Only write to LDS if the output is read by the shader, or it's per-patch tess factor */
3387    bool write_to_lds = !write_to_vmem || should_write_tcs_output_to_lds(ctx, instr, per_vertex);
3388
3389    if (write_to_vmem) {
3390       std::pair<Temp, unsigned> vmem_offs = per_vertex
3391                                             ? get_tcs_per_vertex_output_vmem_offset(ctx, instr)
3392                                             : get_tcs_per_patch_output_vmem_offset(ctx, instr);
3393
3394       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3395       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3396       store_vmem_mubuf(ctx, store_val, hs_ring_tess_offchip, vmem_offs.first, oc_lds, vmem_offs.second, elem_size_bytes, write_mask, false, false);
3397    }
3398
3399    if (write_to_lds) {
3400       std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3401       unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3402       store_lds(ctx, elem_size_bytes, store_val, write_mask, lds_offs.first, lds_offs.second, lds_align);
3403    }
3404 }
3405
3406 void visit_load_tcs_output(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex)
3407 {
3408    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
3409    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3410
3411    Builder bld(ctx->program, ctx->block);
3412
3413    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3414    std::pair<Temp, unsigned> lds_offs = get_tcs_output_lds_offset(ctx, instr, per_vertex);
3415    unsigned lds_align = calculate_lds_alignment(ctx, lds_offs.second);
3416    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
3417
3418    load_lds(ctx, elem_size_bytes, dst, lds_offs.first, lds_offs.second, lds_align);
3419 }
3420
3421 void visit_store_output(isel_context *ctx, nir_intrinsic_instr *instr)
3422 {
3423    if (ctx->stage == vertex_vs ||
3424        ctx->stage == tess_eval_vs ||
3425        ctx->stage == fragment_fs ||
3426        ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
3427       unsigned write_mask = nir_intrinsic_write_mask(instr);
3428       unsigned component = nir_intrinsic_component(instr);
3429       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
3430       unsigned idx = nir_intrinsic_base(instr) + component;
3431
3432       nir_instr *off_instr = instr->src[1].ssa->parent_instr;
3433       if (off_instr->type != nir_instr_type_load_const) {
3434          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3435          nir_print_instr(off_instr, stderr);
3436          fprintf(stderr, "\n");
3437       }
3438       idx += nir_instr_as_load_const(off_instr)->value[0].u32 * 4u;
3439
3440       if (instr->src[0].ssa->bit_size == 64)
3441          write_mask = widen_mask(write_mask, 2);
3442
3443       for (unsigned i = 0; i < 8; ++i) {
3444          if (write_mask & (1 << i)) {
3445             ctx->outputs.mask[idx / 4u] |= 1 << (idx % 4u);
3446             ctx->outputs.outputs[idx / 4u][idx % 4u] = emit_extract_vector(ctx, src, i, v1);
3447          }
3448          idx++;
3449       }
3450    } else if (ctx->stage == vertex_es ||
3451               ctx->stage == vertex_ls ||
3452               ctx->stage == tess_eval_es ||
3453               (ctx->stage == vertex_tess_control_hs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3454               (ctx->stage == vertex_geometry_gs && ctx->shader->info.stage == MESA_SHADER_VERTEX) ||
3455               (ctx->stage == tess_eval_geometry_gs && ctx->shader->info.stage == MESA_SHADER_TESS_EVAL)) {
3456       visit_store_ls_or_es_output(ctx, instr);
3457    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
3458       visit_store_tcs_output(ctx, instr, false);
3459    } else {
3460       unreachable("Shader stage not implemented");
3461    }
3462 }
3463
3464 void visit_load_output(isel_context *ctx, nir_intrinsic_instr *instr)
3465 {
3466    visit_load_tcs_output(ctx, instr, false);
3467 }
3468
3469 void emit_interp_instr(isel_context *ctx, unsigned idx, unsigned component, Temp src, Temp dst, Temp prim_mask)
3470 {
3471    Temp coord1 = emit_extract_vector(ctx, src, 0, v1);
3472    Temp coord2 = emit_extract_vector(ctx, src, 1, v1);
3473
3474    Builder bld(ctx->program, ctx->block);
3475    Builder::Result interp_p1 = bld.vintrp(aco_opcode::v_interp_p1_f32, bld.def(v1), coord1, bld.m0(prim_mask), idx, component);
3476    if (ctx->program->has_16bank_lds)
3477       interp_p1.instr->operands[0].setLateKill(true);
3478    bld.vintrp(aco_opcode::v_interp_p2_f32, Definition(dst), coord2, bld.m0(prim_mask), interp_p1, idx, component);
3479 }
3480
3481 void emit_load_frag_coord(isel_context *ctx, Temp dst, unsigned num_components)
3482 {
3483    aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1));
3484    for (unsigned i = 0; i < num_components; i++)
3485       vec->operands[i] = Operand(get_arg(ctx, ctx->args->ac.frag_pos[i]));
3486    if (G_0286CC_POS_W_FLOAT_ENA(ctx->program->config->spi_ps_input_ena)) {
3487       assert(num_components == 4);
3488       Builder bld(ctx->program, ctx->block);
3489       vec->operands[3] = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), get_arg(ctx, ctx->args->ac.frag_pos[3]));
3490    }
3491
3492    for (Operand& op : vec->operands)
3493       op = op.isUndefined() ? Operand(0u) : op;
3494
3495    vec->definitions[0] = Definition(dst);
3496    ctx->block->instructions.emplace_back(std::move(vec));
3497    emit_split_vector(ctx, dst, num_components);
3498    return;
3499 }
3500
3501 void visit_load_interpolated_input(isel_context *ctx, nir_intrinsic_instr *instr)
3502 {
3503    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3504    Temp coords = get_ssa_temp(ctx, instr->src[0].ssa);
3505    unsigned idx = nir_intrinsic_base(instr);
3506    unsigned component = nir_intrinsic_component(instr);
3507    Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3508
3509    nir_const_value* offset = nir_src_as_const_value(instr->src[1]);
3510    if (offset) {
3511       assert(offset->u32 == 0);
3512    } else {
3513       /* the lower 15bit of the prim_mask contain the offset into LDS
3514        * while the upper bits contain the number of prims */
3515       Temp offset_src = get_ssa_temp(ctx, instr->src[1].ssa);
3516       assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3517       Builder bld(ctx->program, ctx->block);
3518       Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3519       stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3520       stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3521       offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3522       prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3523    }
3524
3525    if (instr->dest.ssa.num_components == 1) {
3526       emit_interp_instr(ctx, idx, component, coords, dst, prim_mask);
3527    } else {
3528       aco_ptr<Pseudo_instruction> vec(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.ssa.num_components, 1));
3529       for (unsigned i = 0; i < instr->dest.ssa.num_components; i++)
3530       {
3531          Temp tmp = {ctx->program->allocateId(), v1};
3532          emit_interp_instr(ctx, idx, component+i, coords, tmp, prim_mask);
3533          vec->operands[i] = Operand(tmp);
3534       }
3535       vec->definitions[0] = Definition(dst);
3536       ctx->block->instructions.emplace_back(std::move(vec));
3537    }
3538 }
3539
3540 bool check_vertex_fetch_size(isel_context *ctx, const ac_data_format_info *vtx_info,
3541                              unsigned offset, unsigned stride, unsigned channels)
3542 {
3543    unsigned vertex_byte_size = vtx_info->chan_byte_size * channels;
3544    if (vtx_info->chan_byte_size != 4 && channels == 3)
3545       return false;
3546    return (ctx->options->chip_class != GFX6 && ctx->options->chip_class != GFX10) ||
3547           (offset % vertex_byte_size == 0 && stride % vertex_byte_size == 0);
3548 }
3549
3550 uint8_t get_fetch_data_format(isel_context *ctx, const ac_data_format_info *vtx_info,
3551                               unsigned offset, unsigned stride, unsigned *channels)
3552 {
3553    if (!vtx_info->chan_byte_size) {
3554       *channels = vtx_info->num_channels;
3555       return vtx_info->chan_format;
3556    }
3557
3558    unsigned num_channels = *channels;
3559    if (!check_vertex_fetch_size(ctx, vtx_info, offset, stride, *channels)) {
3560       unsigned new_channels = num_channels + 1;
3561       /* first, assume more loads is worse and try using a larger data format */
3562       while (new_channels <= 4 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels)) {
3563          new_channels++;
3564          /* don't make the attribute potentially out-of-bounds */
3565          if (offset + new_channels * vtx_info->chan_byte_size > stride)
3566             new_channels = 5;
3567       }
3568
3569       if (new_channels == 5) {
3570          /* then try decreasing load size (at the cost of more loads) */
3571          new_channels = *channels;
3572          while (new_channels > 1 && !check_vertex_fetch_size(ctx, vtx_info, offset, stride, new_channels))
3573             new_channels--;
3574       }
3575
3576       if (new_channels < *channels)
3577          *channels = new_channels;
3578       num_channels = new_channels;
3579    }
3580
3581    switch (vtx_info->chan_format) {
3582    case V_008F0C_BUF_DATA_FORMAT_8:
3583       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8, V_008F0C_BUF_DATA_FORMAT_8_8,
3584                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_8_8_8_8}[num_channels - 1];
3585    case V_008F0C_BUF_DATA_FORMAT_16:
3586       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16, V_008F0C_BUF_DATA_FORMAT_16_16,
3587                          V_008F0C_BUF_DATA_FORMAT_INVALID, V_008F0C_BUF_DATA_FORMAT_16_16_16_16}[num_channels - 1];
3588    case V_008F0C_BUF_DATA_FORMAT_32:
3589       return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_DATA_FORMAT_32_32,
3590                          V_008F0C_BUF_DATA_FORMAT_32_32_32, V_008F0C_BUF_DATA_FORMAT_32_32_32_32}[num_channels - 1];
3591    }
3592    unreachable("shouldn't reach here");
3593    return V_008F0C_BUF_DATA_FORMAT_INVALID;
3594 }
3595
3596 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3597  * so we may need to fix it up. */
3598 Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alpha)
3599 {
3600    Builder bld(ctx->program, ctx->block);
3601
3602    if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
3603       alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha);
3604
3605    /* For the integer-like cases, do a natural sign extension.
3606     *
3607     * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3608     * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3609     * exponent.
3610     */
3611    alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha);
3612    alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha);
3613
3614    /* Convert back to the right type. */
3615    if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
3616       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3617       Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha);
3618       alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp);
3619    } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
3620       alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha);
3621    }
3622
3623    return alpha;
3624 }
3625
3626 void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
3627 {
3628    Builder bld(ctx->program, ctx->block);
3629    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3630    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
3631
3632       nir_instr *off_instr = instr->src[0].ssa->parent_instr;
3633       if (off_instr->type != nir_instr_type_load_const) {
3634          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3635          nir_print_instr(off_instr, stderr);
3636          fprintf(stderr, "\n");
3637       }
3638       uint32_t offset = nir_instr_as_load_const(off_instr)->value[0].u32;
3639
3640       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
3641
3642       unsigned location = nir_intrinsic_base(instr) / 4 - VERT_ATTRIB_GENERIC0 + offset;
3643       unsigned component = nir_intrinsic_component(instr);
3644       unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[location];
3645       uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location];
3646       uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location];
3647       unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location];
3648
3649       unsigned dfmt = attrib_format & 0xf;
3650       unsigned nfmt = (attrib_format >> 4) & 0x7;
3651       const struct ac_data_format_info *vtx_info = ac_get_data_format_info(dfmt);
3652
3653       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
3654       unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
3655       unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3;
3656       bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location);
3657       if (post_shuffle)
3658          num_channels = MAX2(num_channels, 3);
3659
3660       Operand off = bld.copy(bld.def(s1), Operand(attrib_binding * 16u));
3661       Temp list = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), vertex_buffers, off);
3662
3663       Temp index;
3664       if (ctx->options->key.vs.instance_rate_inputs & (1u << location)) {
3665          uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[location];
3666          Temp start_instance = get_arg(ctx, ctx->args->ac.start_instance);
3667          if (divisor) {
3668             Temp instance_id = get_arg(ctx, ctx->args->ac.instance_id);
3669             if (divisor != 1) {
3670                Temp divided = bld.tmp(v1);
3671                emit_v_div_u32(ctx, divided, as_vgpr(ctx, instance_id), divisor);
3672                index = bld.vadd32(bld.def(v1), start_instance, divided);
3673             } else {
3674                index = bld.vadd32(bld.def(v1), start_instance, instance_id);
3675             }
3676          } else {
3677             index = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), start_instance);
3678          }
3679       } else {
3680          index = bld.vadd32(bld.def(v1),
3681                             get_arg(ctx, ctx->args->ac.base_vertex),
3682                             get_arg(ctx, ctx->args->ac.vertex_id));
3683       }
3684
3685       Temp channels[num_channels];
3686       unsigned channel_start = 0;
3687       bool direct_fetch = false;
3688
3689       /* skip unused channels at the start */
3690       if (vtx_info->chan_byte_size && !post_shuffle) {
3691          channel_start = ffs(mask) - 1;
3692          for (unsigned i = 0; i < channel_start; i++)
3693             channels[i] = Temp(0, s1);
3694       } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
3695          num_channels = 3 - (ffs(mask) - 1);
3696       }
3697
3698       /* load channels */
3699       while (channel_start < num_channels) {
3700          unsigned fetch_size = num_channels - channel_start;
3701          unsigned fetch_offset = attrib_offset + channel_start * vtx_info->chan_byte_size;
3702          bool expanded = false;
3703
3704          /* use MUBUF when possible to avoid possible alignment issues */
3705          /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
3706          bool use_mubuf = (nfmt == V_008F0C_BUF_NUM_FORMAT_FLOAT ||
3707                            nfmt == V_008F0C_BUF_NUM_FORMAT_UINT ||
3708                            nfmt == V_008F0C_BUF_NUM_FORMAT_SINT) &&
3709                           vtx_info->chan_byte_size == 4;
3710          unsigned fetch_dfmt = V_008F0C_BUF_DATA_FORMAT_INVALID;
3711          if (!use_mubuf) {
3712             fetch_dfmt = get_fetch_data_format(ctx, vtx_info, fetch_offset, attrib_stride, &fetch_size);
3713          } else {
3714             if (fetch_size == 3 && ctx->options->chip_class == GFX6) {
3715                /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
3716                fetch_size = 4;
3717                expanded = true;
3718             }
3719          }
3720
3721          Temp fetch_index = index;
3722          if (attrib_stride != 0 && fetch_offset > attrib_stride) {
3723             fetch_index = bld.vadd32(bld.def(v1), Operand(fetch_offset / attrib_stride), fetch_index);
3724             fetch_offset = fetch_offset % attrib_stride;
3725          }
3726
3727          Operand soffset(0u);
3728          if (fetch_offset >= 4096) {
3729             soffset = bld.copy(bld.def(s1), Operand(fetch_offset / 4096 * 4096));
3730             fetch_offset %= 4096;
3731          }
3732
3733          aco_opcode opcode;
3734          switch (fetch_size) {
3735          case 1:
3736             opcode = use_mubuf ? aco_opcode::buffer_load_dword : aco_opcode::tbuffer_load_format_x;
3737             break;
3738          case 2:
3739             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx2 : aco_opcode::tbuffer_load_format_xy;
3740             break;
3741          case 3:
3742             assert(ctx->options->chip_class >= GFX7 ||
3743                    (!use_mubuf && ctx->options->chip_class == GFX6));
3744             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx3 : aco_opcode::tbuffer_load_format_xyz;
3745             break;
3746          case 4:
3747             opcode = use_mubuf ? aco_opcode::buffer_load_dwordx4 : aco_opcode::tbuffer_load_format_xyzw;
3748             break;
3749          default:
3750             unreachable("Unimplemented load_input vector size");
3751          }
3752
3753          Temp fetch_dst;
3754          if (channel_start == 0 && fetch_size == dst.size() && !post_shuffle &&
3755              !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE ||
3756                            num_channels <= 3)) {
3757             direct_fetch = true;
3758             fetch_dst = dst;
3759          } else {
3760             fetch_dst = bld.tmp(RegType::vgpr, fetch_size);
3761          }
3762
3763          if (use_mubuf) {
3764             Instruction *mubuf = bld.mubuf(opcode,
3765                                            Definition(fetch_dst), list, fetch_index, soffset,
3766                                            fetch_offset, false, true).instr;
3767             static_cast<MUBUF_instruction*>(mubuf)->can_reorder = true;
3768          } else {
3769             Instruction *mtbuf = bld.mtbuf(opcode,
3770                                            Definition(fetch_dst), list, fetch_index, soffset,
3771                                            fetch_dfmt, nfmt, fetch_offset, false, true).instr;
3772             static_cast<MTBUF_instruction*>(mtbuf)->can_reorder = true;
3773          }
3774
3775          emit_split_vector(ctx, fetch_dst, fetch_dst.size());
3776
3777          if (fetch_size == 1) {
3778             channels[channel_start] = fetch_dst;
3779          } else {
3780             for (unsigned i = 0; i < MIN2(fetch_size, num_channels - channel_start); i++)
3781                channels[channel_start + i] = emit_extract_vector(ctx, fetch_dst, i, v1);
3782          }
3783
3784          channel_start += fetch_size;
3785       }
3786
3787       if (!direct_fetch) {
3788          bool is_float = nfmt != V_008F0C_BUF_NUM_FORMAT_UINT &&
3789                          nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
3790
3791          static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
3792          static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
3793          const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
3794
3795          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3796          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
3797          unsigned num_temp = 0;
3798          for (unsigned i = 0; i < dst.size(); i++) {
3799             unsigned idx = i + component;
3800             if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
3801                Temp channel = channels[swizzle[idx]];
3802                if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE)
3803                   channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel);
3804                vec->operands[i] = Operand(channel);
3805
3806                num_temp++;
3807                elems[i] = channel;
3808             } else if (is_float && idx == 3) {
3809                vec->operands[i] = Operand(0x3f800000u);
3810             } else if (!is_float && idx == 3) {
3811                vec->operands[i] = Operand(1u);
3812             } else {
3813                vec->operands[i] = Operand(0u);
3814             }
3815          }
3816          vec->definitions[0] = Definition(dst);
3817          ctx->block->instructions.emplace_back(std::move(vec));
3818          emit_split_vector(ctx, dst, dst.size());
3819
3820          if (num_temp == dst.size())
3821             ctx->allocated_vec.emplace(dst.id(), elems);
3822       }
3823    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
3824       unsigned offset_idx = instr->intrinsic == nir_intrinsic_load_input ? 0 : 1;
3825       nir_instr *off_instr = instr->src[offset_idx].ssa->parent_instr;
3826       if (off_instr->type != nir_instr_type_load_const ||
3827           nir_instr_as_load_const(off_instr)->value[0].u32 != 0) {
3828          fprintf(stderr, "Unimplemented nir_intrinsic_load_input offset\n");
3829          nir_print_instr(off_instr, stderr);
3830          fprintf(stderr, "\n");
3831       }
3832
3833       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);
3834       nir_const_value* offset = nir_src_as_const_value(instr->src[offset_idx]);
3835       if (offset) {
3836          assert(offset->u32 == 0);
3837       } else {
3838          /* the lower 15bit of the prim_mask contain the offset into LDS
3839           * while the upper bits contain the number of prims */
3840          Temp offset_src = get_ssa_temp(ctx, instr->src[offset_idx].ssa);
3841          assert(offset_src.regClass() == s1 && "TODO: divergent offsets...");
3842          Builder bld(ctx->program, ctx->block);
3843          Temp stride = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), prim_mask, Operand(16u));
3844          stride = bld.sop1(aco_opcode::s_bcnt1_i32_b32, bld.def(s1), bld.def(s1, scc), stride);
3845          stride = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, Operand(48u));
3846          offset_src = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), stride, offset_src);
3847          prim_mask = bld.sop2(aco_opcode::s_add_i32, bld.def(s1, m0), bld.def(s1, scc), offset_src, prim_mask);
3848       }
3849
3850       unsigned idx = nir_intrinsic_base(instr);
3851       unsigned component = nir_intrinsic_component(instr);
3852       unsigned vertex_id = 2; /* P0 */
3853
3854       if (instr->intrinsic == nir_intrinsic_load_input_vertex) {
3855          nir_const_value* src0 = nir_src_as_const_value(instr->src[0]);
3856          switch (src0->u32) {
3857          case 0:
3858             vertex_id = 2; /* P0 */
3859             break;
3860          case 1:
3861             vertex_id = 0; /* P10 */
3862             break;
3863          case 2:
3864             vertex_id = 1; /* P20 */
3865             break;
3866          default:
3867             unreachable("invalid vertex index");
3868          }
3869       }
3870
3871       if (dst.size() == 1) {
3872          bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(dst), Operand(vertex_id), bld.m0(prim_mask), idx, component);
3873       } else {
3874          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
3875          for (unsigned i = 0; i < dst.size(); i++)
3876             vec->operands[i] = bld.vintrp(aco_opcode::v_interp_mov_f32, bld.def(v1), Operand(vertex_id), bld.m0(prim_mask), idx, component + i);
3877          vec->definitions[0] = Definition(dst);
3878          bld.insert(std::move(vec));
3879       }
3880
3881    } else if (ctx->shader->info.stage == MESA_SHADER_TESS_EVAL) {
3882       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3883       Temp soffset = get_arg(ctx, ctx->args->oc_lds);
3884       std::pair<Temp, unsigned> offs = get_tcs_per_patch_output_vmem_offset(ctx, instr);
3885       unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8u;
3886
3887       load_vmem_mubuf(ctx, dst, ring, offs.first, soffset, offs.second, elem_size_bytes, instr->dest.ssa.num_components);
3888    } else {
3889       unreachable("Shader stage not implemented");
3890    }
3891 }
3892
3893 std::pair<Temp, unsigned> get_gs_per_vertex_input_offset(isel_context *ctx, nir_intrinsic_instr *instr, unsigned base_stride = 1u)
3894 {
3895    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3896
3897    Builder bld(ctx->program, ctx->block);
3898    nir_src *vertex_src = nir_get_io_vertex_index_src(instr);
3899    Temp vertex_offset;
3900
3901    if (!nir_src_is_const(*vertex_src)) {
3902       /* better code could be created, but this case probably doesn't happen
3903        * much in practice */
3904       Temp indirect_vertex = as_vgpr(ctx, get_ssa_temp(ctx, vertex_src->ssa));
3905       for (unsigned i = 0; i < ctx->shader->info.gs.vertices_in; i++) {
3906          Temp elem;
3907
3908          if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3909             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i / 2u * 2u]);
3910             if (i % 2u)
3911                elem = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), elem);
3912          } else {
3913             elem = get_arg(ctx, ctx->args->gs_vtx_offset[i]);
3914          }
3915
3916          if (vertex_offset.id()) {
3917             Temp cond = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)),
3918                                  Operand(i), indirect_vertex);
3919             vertex_offset = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), vertex_offset, elem, cond);
3920          } else {
3921             vertex_offset = elem;
3922          }
3923       }
3924
3925       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3926          vertex_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0xffffu), vertex_offset);
3927    } else {
3928       unsigned vertex = nir_src_as_uint(*vertex_src);
3929       if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs)
3930          vertex_offset = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
3931                                   get_arg(ctx, ctx->args->gs_vtx_offset[vertex / 2u * 2u]),
3932                                   Operand((vertex % 2u) * 16u), Operand(16u));
3933       else
3934          vertex_offset = get_arg(ctx, ctx->args->gs_vtx_offset[vertex]);
3935    }
3936
3937    std::pair<Temp, unsigned> offs = get_intrinsic_io_basic_offset(ctx, instr, base_stride);
3938    offs = offset_add(ctx, offs, std::make_pair(vertex_offset, 0u));
3939    return offset_mul(ctx, offs, 4u);
3940 }
3941
3942 void visit_load_gs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3943 {
3944    assert(ctx->shader->info.stage == MESA_SHADER_GEOMETRY);
3945
3946    Builder bld(ctx->program, ctx->block);
3947    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3948    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3949
3950    if (ctx->stage == geometry_gs) {
3951       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr, ctx->program->wave_size);
3952       Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_ESGS_GS * 16u));
3953       load_vmem_mubuf(ctx, dst, ring, offs.first, Temp(), offs.second, elem_size_bytes, instr->dest.ssa.num_components, 4u * ctx->program->wave_size, false, true);
3954    } else if (ctx->stage == vertex_geometry_gs || ctx->stage == tess_eval_geometry_gs) {
3955       std::pair<Temp, unsigned> offs = get_gs_per_vertex_input_offset(ctx, instr);
3956       unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3957       load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3958    } else {
3959       unreachable("Unsupported GS stage.");
3960    }
3961 }
3962
3963 void visit_load_tcs_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3964 {
3965    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
3966
3967    Builder bld(ctx->program, ctx->block);
3968    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3969    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_input_lds_offset(ctx, instr);
3970    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3971    unsigned lds_align = calculate_lds_alignment(ctx, offs.second);
3972
3973    load_lds(ctx, elem_size_bytes, dst, offs.first, offs.second, lds_align);
3974 }
3975
3976 void visit_load_tes_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3977 {
3978    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
3979
3980    Builder bld(ctx->program, ctx->block);
3981
3982    Temp ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
3983    Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
3984    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
3985
3986    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
3987    std::pair<Temp, unsigned> offs = get_tcs_per_vertex_output_vmem_offset(ctx, instr);
3988
3989    load_vmem_mubuf(ctx, dst, ring, offs.first, oc_lds, offs.second, elem_size_bytes, instr->dest.ssa.num_components, 0u, true, true);
3990 }
3991
3992 void visit_load_per_vertex_input(isel_context *ctx, nir_intrinsic_instr *instr)
3993 {
3994    switch (ctx->shader->info.stage) {
3995    case MESA_SHADER_GEOMETRY:
3996       visit_load_gs_per_vertex_input(ctx, instr);
3997       break;
3998    case MESA_SHADER_TESS_CTRL:
3999       visit_load_tcs_per_vertex_input(ctx, instr);
4000       break;
4001    case MESA_SHADER_TESS_EVAL:
4002       visit_load_tes_per_vertex_input(ctx, instr);
4003       break;
4004    default:
4005       unreachable("Unimplemented shader stage");
4006    }
4007 }
4008
4009 void visit_load_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4010 {
4011    visit_load_tcs_output(ctx, instr, true);
4012 }
4013
4014 void visit_store_per_vertex_output(isel_context *ctx, nir_intrinsic_instr *instr)
4015 {
4016    assert(ctx->stage == tess_control_hs || ctx->stage == vertex_tess_control_hs);
4017    assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
4018
4019    visit_store_tcs_output(ctx, instr, true);
4020 }
4021
4022 void visit_load_tess_coord(isel_context *ctx, nir_intrinsic_instr *instr)
4023 {
4024    assert(ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
4025
4026    Builder bld(ctx->program, ctx->block);
4027    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4028
4029    Operand tes_u(get_arg(ctx, ctx->args->tes_u));
4030    Operand tes_v(get_arg(ctx, ctx->args->tes_v));
4031    Operand tes_w(0u);
4032
4033    if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES) {
4034       Temp tmp = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), tes_u, tes_v);
4035       tmp = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0x3f800000u /* 1.0f */), tmp);
4036       tes_w = Operand(tmp);
4037    }
4038
4039    Temp tess_coord = bld.pseudo(aco_opcode::p_create_vector, Definition(dst), tes_u, tes_v, tes_w);
4040    emit_split_vector(ctx, tess_coord, 3);
4041 }
4042
4043 Temp load_desc_ptr(isel_context *ctx, unsigned desc_set)
4044 {
4045    if (ctx->program->info->need_indirect_descriptor_sets) {
4046       Builder bld(ctx->program, ctx->block);
4047       Temp ptr64 = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->descriptor_sets[0]));
4048       Operand off = bld.copy(bld.def(s1), Operand(desc_set << 2));
4049       return bld.smem(aco_opcode::s_load_dword, bld.def(s1), ptr64, off);//, false, false, false);
4050    }
4051
4052    return get_arg(ctx, ctx->args->descriptor_sets[desc_set]);
4053 }
4054
4055
4056 void visit_load_resource(isel_context *ctx, nir_intrinsic_instr *instr)
4057 {
4058    Builder bld(ctx->program, ctx->block);
4059    Temp index = get_ssa_temp(ctx, instr->src[0].ssa);
4060    if (!ctx->divergent_vals[instr->dest.ssa.index])
4061       index = bld.as_uniform(index);
4062    unsigned desc_set = nir_intrinsic_desc_set(instr);
4063    unsigned binding = nir_intrinsic_binding(instr);
4064
4065    Temp desc_ptr;
4066    radv_pipeline_layout *pipeline_layout = ctx->options->layout;
4067    radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
4068    unsigned offset = layout->binding[binding].offset;
4069    unsigned stride;
4070    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
4071        layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
4072       unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start + layout->binding[binding].dynamic_offset_offset;
4073       desc_ptr = get_arg(ctx, ctx->args->ac.push_constants);
4074       offset = pipeline_layout->push_constant_size + 16 * idx;
4075       stride = 16;
4076    } else {
4077       desc_ptr = load_desc_ptr(ctx, desc_set);
4078       stride = layout->binding[binding].size;
4079    }
4080
4081    nir_const_value* nir_const_index = nir_src_as_const_value(instr->src[0]);
4082    unsigned const_index = nir_const_index ? nir_const_index->u32 : 0;
4083    if (stride != 1) {
4084       if (nir_const_index) {
4085          const_index = const_index * stride;
4086       } else if (index.type() == RegType::vgpr) {
4087          bool index24bit = layout->binding[binding].array_size <= 0x1000000;
4088          index = bld.v_mul_imm(bld.def(v1), index, stride, index24bit);
4089       } else {
4090          index = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), Operand(index));
4091       }
4092    }
4093    if (offset) {
4094       if (nir_const_index) {
4095          const_index = const_index + offset;
4096       } else if (index.type() == RegType::vgpr) {
4097          index = bld.vadd32(bld.def(v1), Operand(offset), index);
4098       } else {
4099          index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), Operand(index));
4100       }
4101    }
4102
4103    if (nir_const_index && const_index == 0) {
4104       index = desc_ptr;
4105    } else if (index.type() == RegType::vgpr) {
4106       index = bld.vadd32(bld.def(v1),
4107                          nir_const_index ? Operand(const_index) : Operand(index),
4108                          Operand(desc_ptr));
4109    } else {
4110       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
4111                        nir_const_index ? Operand(const_index) : Operand(index),
4112                        Operand(desc_ptr));
4113    }
4114
4115    bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), index);
4116 }
4117
4118 void load_buffer(isel_context *ctx, unsigned num_components, Temp dst,
4119                  Temp rsrc, Temp offset, bool glc=false, bool readonly=true)
4120 {
4121    Builder bld(ctx->program, ctx->block);
4122
4123    unsigned num_bytes = dst.size() * 4;
4124    bool dlc = glc && ctx->options->chip_class >= GFX10;
4125
4126    aco_opcode op;
4127    if (dst.type() == RegType::vgpr || (ctx->options->chip_class < GFX8 && !readonly)) {
4128       Operand vaddr = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
4129       Operand soffset = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
4130       unsigned const_offset = 0;
4131
4132       Temp lower = Temp();
4133       if (num_bytes > 16) {
4134          assert(num_components == 3 || num_components == 4);
4135          op = aco_opcode::buffer_load_dwordx4;
4136          lower = bld.tmp(v4);
4137          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4138          mubuf->definitions[0] = Definition(lower);
4139          mubuf->operands[0] = Operand(rsrc);
4140          mubuf->operands[1] = vaddr;
4141          mubuf->operands[2] = soffset;
4142          mubuf->offen = (offset.type() == RegType::vgpr);
4143          mubuf->glc = glc;
4144          mubuf->dlc = dlc;
4145          mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4146          mubuf->can_reorder = readonly;
4147          bld.insert(std::move(mubuf));
4148          emit_split_vector(ctx, lower, 2);
4149          num_bytes -= 16;
4150          const_offset = 16;
4151       } else if (num_bytes == 12 && ctx->options->chip_class == GFX6) {
4152          /* GFX6 doesn't support loading vec3, expand to vec4. */
4153          num_bytes = 16;
4154       }
4155
4156       switch (num_bytes) {
4157          case 4:
4158             op = aco_opcode::buffer_load_dword;
4159             break;
4160          case 8:
4161             op = aco_opcode::buffer_load_dwordx2;
4162             break;
4163          case 12:
4164             assert(ctx->options->chip_class > GFX6);
4165             op = aco_opcode::buffer_load_dwordx3;
4166             break;
4167          case 16:
4168             op = aco_opcode::buffer_load_dwordx4;
4169             break;
4170          default:
4171             unreachable("Load SSBO not implemented for this size.");
4172       }
4173       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
4174       mubuf->operands[0] = Operand(rsrc);
4175       mubuf->operands[1] = vaddr;
4176       mubuf->operands[2] = soffset;
4177       mubuf->offen = (offset.type() == RegType::vgpr);
4178       mubuf->glc = glc;
4179       mubuf->dlc = dlc;
4180       mubuf->barrier = readonly ? barrier_none : barrier_buffer;
4181       mubuf->can_reorder = readonly;
4182       mubuf->offset = const_offset;
4183       aco_ptr<Instruction> instr = std::move(mubuf);
4184
4185       if (dst.size() > 4) {
4186          assert(lower != Temp());
4187          Temp upper = bld.tmp(RegType::vgpr, dst.size() - lower.size());
4188          instr->definitions[0] = Definition(upper);
4189          bld.insert(std::move(instr));
4190          if (dst.size() == 8)
4191             emit_split_vector(ctx, upper, 2);
4192          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size() / 2, 1));
4193          instr->operands[0] = Operand(emit_extract_vector(ctx, lower, 0, v2));
4194          instr->operands[1] = Operand(emit_extract_vector(ctx, lower, 1, v2));
4195          instr->operands[2] = Operand(emit_extract_vector(ctx, upper, 0, v2));
4196          if (dst.size() == 8)
4197             instr->operands[3] = Operand(emit_extract_vector(ctx, upper, 1, v2));
4198       } else if (dst.size() == 3 && ctx->options->chip_class == GFX6) {
4199          Temp vec = bld.tmp(v4);
4200          instr->definitions[0] = Definition(vec);
4201          bld.insert(std::move(instr));
4202          emit_split_vector(ctx, vec, 4);
4203
4204          instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
4205          instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
4206          instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
4207          instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
4208       }
4209
4210       if (dst.type() == RegType::sgpr) {
4211          Temp vec = bld.tmp(RegType::vgpr, dst.size());
4212          instr->definitions[0] = Definition(vec);
4213          bld.insert(std::move(instr));
4214          expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
4215       } else {
4216          instr->definitions[0] = Definition(dst);
4217          bld.insert(std::move(instr));
4218          emit_split_vector(ctx, dst, num_components);
4219       }
4220    } else {
4221       switch (num_bytes) {
4222          case 4:
4223             op = aco_opcode::s_buffer_load_dword;
4224             break;
4225          case 8:
4226             op = aco_opcode::s_buffer_load_dwordx2;
4227             break;
4228          case 12:
4229          case 16:
4230             op = aco_opcode::s_buffer_load_dwordx4;
4231             break;
4232          case 24:
4233          case 32:
4234             op = aco_opcode::s_buffer_load_dwordx8;
4235             break;
4236          default:
4237             unreachable("Load SSBO not implemented for this size.");
4238       }
4239       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
4240       load->operands[0] = Operand(rsrc);
4241       load->operands[1] = Operand(bld.as_uniform(offset));
4242       assert(load->operands[1].getTemp().type() == RegType::sgpr);
4243       load->definitions[0] = Definition(dst);
4244       load->glc = glc;
4245       load->dlc = dlc;
4246       load->barrier = readonly ? barrier_none : barrier_buffer;
4247       load->can_reorder = false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
4248       assert(ctx->options->chip_class >= GFX8 || !glc);
4249
4250       /* trim vector */
4251       if (dst.size() == 3) {
4252          Temp vec = bld.tmp(s4);
4253          load->definitions[0] = Definition(vec);
4254          bld.insert(std::move(load));
4255          emit_split_vector(ctx, vec, 4);
4256
4257          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4258                     emit_extract_vector(ctx, vec, 0, s1),
4259                     emit_extract_vector(ctx, vec, 1, s1),
4260                     emit_extract_vector(ctx, vec, 2, s1));
4261       } else if (dst.size() == 6) {
4262          Temp vec = bld.tmp(s8);
4263          load->definitions[0] = Definition(vec);
4264          bld.insert(std::move(load));
4265          emit_split_vector(ctx, vec, 4);
4266
4267          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4268                     emit_extract_vector(ctx, vec, 0, s2),
4269                     emit_extract_vector(ctx, vec, 1, s2),
4270                     emit_extract_vector(ctx, vec, 2, s2));
4271       } else {
4272          bld.insert(std::move(load));
4273       }
4274       emit_split_vector(ctx, dst, num_components);
4275    }
4276 }
4277
4278 void visit_load_ubo(isel_context *ctx, nir_intrinsic_instr *instr)
4279 {
4280    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4281    Temp rsrc = get_ssa_temp(ctx, instr->src[0].ssa);
4282
4283    Builder bld(ctx->program, ctx->block);
4284
4285    nir_intrinsic_instr* idx_instr = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);
4286    unsigned desc_set = nir_intrinsic_desc_set(idx_instr);
4287    unsigned binding = nir_intrinsic_binding(idx_instr);
4288    radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
4289
4290    if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
4291       uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4292                            S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4293                            S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4294                            S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4295       if (ctx->options->chip_class >= GFX10) {
4296          desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4297                       S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4298                       S_008F0C_RESOURCE_LEVEL(1);
4299       } else {
4300          desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4301                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4302       }
4303       Temp upper_dwords = bld.pseudo(aco_opcode::p_create_vector, bld.def(s3),
4304                                      Operand(S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi)),
4305                                      Operand(0xFFFFFFFFu),
4306                                      Operand(desc_type));
4307       rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4308                         rsrc, upper_dwords);
4309    } else {
4310       rsrc = convert_pointer_to_64_bit(ctx, rsrc);
4311       rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
4312    }
4313
4314    load_buffer(ctx, instr->num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa));
4315 }
4316
4317 void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4318 {
4319    Builder bld(ctx->program, ctx->block);
4320    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4321
4322    unsigned offset = nir_intrinsic_base(instr);
4323    nir_const_value *index_cv = nir_src_as_const_value(instr->src[0]);
4324    if (index_cv && instr->dest.ssa.bit_size == 32) {
4325
4326       unsigned count = instr->dest.ssa.num_components;
4327       unsigned start = (offset + index_cv->u32) / 4u;
4328       start -= ctx->args->ac.base_inline_push_consts;
4329       if (start + count <= ctx->args->ac.num_inline_push_consts) {
4330          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
4331          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
4332          for (unsigned i = 0; i < count; ++i) {
4333             elems[i] = get_arg(ctx, ctx->args->ac.inline_push_consts[start + i]);
4334             vec->operands[i] = Operand{elems[i]};
4335          }
4336          vec->definitions[0] = Definition(dst);
4337          ctx->block->instructions.emplace_back(std::move(vec));
4338          ctx->allocated_vec.emplace(dst.id(), elems);
4339          return;
4340       }
4341    }
4342
4343    Temp index = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa));
4344    if (offset != 0) // TODO check if index != 0 as well
4345       index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset), index);
4346    Temp ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->ac.push_constants));
4347    Temp vec = dst;
4348    bool trim = false;
4349    aco_opcode op;
4350
4351    switch (dst.size()) {
4352    case 1:
4353       op = aco_opcode::s_load_dword;
4354       break;
4355    case 2:
4356       op = aco_opcode::s_load_dwordx2;
4357       break;
4358    case 3:
4359       vec = bld.tmp(s4);
4360       trim = true;
4361    case 4:
4362       op = aco_opcode::s_load_dwordx4;
4363       break;
4364    case 6:
4365       vec = bld.tmp(s8);
4366       trim = true;
4367    case 8:
4368       op = aco_opcode::s_load_dwordx8;
4369       break;
4370    default:
4371       unreachable("unimplemented or forbidden load_push_constant.");
4372    }
4373
4374    bld.smem(op, Definition(vec), ptr, index);
4375
4376    if (trim) {
4377       emit_split_vector(ctx, vec, 4);
4378       RegClass rc = dst.size() == 3 ? s1 : s2;
4379       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
4380                  emit_extract_vector(ctx, vec, 0, rc),
4381                  emit_extract_vector(ctx, vec, 1, rc),
4382                  emit_extract_vector(ctx, vec, 2, rc));
4383
4384    }
4385    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
4386 }
4387
4388 void visit_load_constant(isel_context *ctx, nir_intrinsic_instr *instr)
4389 {
4390    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4391
4392    Builder bld(ctx->program, ctx->block);
4393
4394    uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
4395                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
4396                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
4397                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
4398    if (ctx->options->chip_class >= GFX10) {
4399       desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
4400                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
4401                    S_008F0C_RESOURCE_LEVEL(1);
4402    } else {
4403       desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
4404                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
4405    }
4406
4407    unsigned base = nir_intrinsic_base(instr);
4408    unsigned range = nir_intrinsic_range(instr);
4409
4410    Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
4411    if (base && offset.type() == RegType::sgpr)
4412       offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), offset, Operand(base));
4413    else if (base && offset.type() == RegType::vgpr)
4414       offset = bld.vadd32(bld.def(v1), Operand(base), offset);
4415
4416    Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4417                           bld.sop1(aco_opcode::p_constaddr, bld.def(s2), bld.def(s1, scc), Operand(ctx->constant_data_offset)),
4418                           Operand(MIN2(base + range, ctx->shader->constant_data_size)),
4419                           Operand(desc_type));
4420
4421    load_buffer(ctx, instr->num_components, dst, rsrc, offset);
4422 }
4423
4424 void visit_discard_if(isel_context *ctx, nir_intrinsic_instr *instr)
4425 {
4426    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4427       ctx->cf_info.exec_potentially_empty_discard = true;
4428
4429    ctx->program->needs_exact = true;
4430
4431    // TODO: optimize uniform conditions
4432    Builder bld(ctx->program, ctx->block);
4433    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
4434    assert(src.regClass() == bld.lm);
4435    src = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
4436    bld.pseudo(aco_opcode::p_discard_if, src);
4437    ctx->block->kind |= block_kind_uses_discard_if;
4438    return;
4439 }
4440
4441 void visit_discard(isel_context* ctx, nir_intrinsic_instr *instr)
4442 {
4443    Builder bld(ctx->program, ctx->block);
4444
4445    if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
4446       ctx->cf_info.exec_potentially_empty_discard = true;
4447
4448    bool divergent = ctx->cf_info.parent_if.is_divergent ||
4449                     ctx->cf_info.parent_loop.has_divergent_continue;
4450
4451    if (ctx->block->loop_nest_depth &&
4452        ((nir_instr_is_last(&instr->instr) && !divergent) || divergent)) {
4453       /* we handle discards the same way as jump instructions */
4454       append_logical_end(ctx->block);
4455
4456       /* in loops, discard behaves like break */
4457       Block *linear_target = ctx->cf_info.parent_loop.exit;
4458       ctx->block->kind |= block_kind_discard;
4459
4460       if (!divergent) {
4461          /* uniform discard - loop ends here */
4462          assert(nir_instr_is_last(&instr->instr));
4463          ctx->block->kind |= block_kind_uniform;
4464          ctx->cf_info.has_branch = true;
4465          bld.branch(aco_opcode::p_branch);
4466          add_linear_edge(ctx->block->index, linear_target);
4467          return;
4468       }
4469
4470       /* we add a break right behind the discard() instructions */
4471       ctx->block->kind |= block_kind_break;
4472       unsigned idx = ctx->block->index;
4473
4474       ctx->cf_info.parent_loop.has_divergent_branch = true;
4475       ctx->cf_info.nir_to_aco[instr->instr.block->index] = idx;
4476
4477       /* remove critical edges from linear CFG */
4478       bld.branch(aco_opcode::p_branch);
4479       Block* break_block = ctx->program->create_and_insert_block();
4480       break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4481       break_block->kind |= block_kind_uniform;
4482       add_linear_edge(idx, break_block);
4483       add_linear_edge(break_block->index, linear_target);
4484       bld.reset(break_block);
4485       bld.branch(aco_opcode::p_branch);
4486
4487       Block* continue_block = ctx->program->create_and_insert_block();
4488       continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
4489       add_linear_edge(idx, continue_block);
4490       append_logical_start(continue_block);
4491       ctx->block = continue_block;
4492
4493       return;
4494    }
4495
4496    /* it can currently happen that NIR doesn't remove the unreachable code */
4497    if (!nir_instr_is_last(&instr->instr)) {
4498       ctx->program->needs_exact = true;
4499       /* save exec somewhere temporarily so that it doesn't get
4500        * overwritten before the discard from outer exec masks */
4501       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), Operand(0xFFFFFFFF), Operand(exec, bld.lm));
4502       bld.pseudo(aco_opcode::p_discard_if, cond);
4503       ctx->block->kind |= block_kind_uses_discard_if;
4504       return;
4505    }
4506
4507    /* This condition is incorrect for uniformly branched discards in a loop
4508     * predicated by a divergent condition, but the above code catches that case
4509     * and the discard would end up turning into a discard_if.
4510     * For example:
4511     * if (divergent) {
4512     *    while (...) {
4513     *       if (uniform) {
4514     *          discard;
4515     *       }
4516     *    }
4517     * }
4518     */
4519    if (!ctx->cf_info.parent_if.is_divergent) {
4520       /* program just ends here */
4521       ctx->block->kind |= block_kind_uniform;
4522       bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
4523               0 /* enabled mask */, 9 /* dest */,
4524               false /* compressed */, true/* done */, true /* valid mask */);
4525       bld.sopp(aco_opcode::s_endpgm);
4526       // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
4527    } else {
4528       ctx->block->kind |= block_kind_discard;
4529       /* branch and linear edge is added by visit_if() */
4530    }
4531 }
4532
4533 enum aco_descriptor_type {
4534    ACO_DESC_IMAGE,
4535    ACO_DESC_FMASK,
4536    ACO_DESC_SAMPLER,
4537    ACO_DESC_BUFFER,
4538    ACO_DESC_PLANE_0,
4539    ACO_DESC_PLANE_1,
4540    ACO_DESC_PLANE_2,
4541 };
4542
4543 static bool
4544 should_declare_array(isel_context *ctx, enum glsl_sampler_dim sampler_dim, bool is_array) {
4545    if (sampler_dim == GLSL_SAMPLER_DIM_BUF)
4546       return false;
4547    ac_image_dim dim = ac_get_sampler_dim(ctx->options->chip_class, sampler_dim, is_array);
4548    return dim == ac_image_cube ||
4549           dim == ac_image_1darray ||
4550           dim == ac_image_2darray ||
4551           dim == ac_image_2darraymsaa;
4552 }
4553
4554 Temp get_sampler_desc(isel_context *ctx, nir_deref_instr *deref_instr,
4555                       enum aco_descriptor_type desc_type,
4556                       const nir_tex_instr *tex_instr, bool image, bool write)
4557 {
4558 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
4559    std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
4560    if (it != ctx->tex_desc.end())
4561       return it->second;
4562 */
4563    Temp index = Temp();
4564    bool index_set = false;
4565    unsigned constant_index = 0;
4566    unsigned descriptor_set;
4567    unsigned base_index;
4568    Builder bld(ctx->program, ctx->block);
4569
4570    if (!deref_instr) {
4571       assert(tex_instr && !image);
4572       descriptor_set = 0;
4573       base_index = tex_instr->sampler_index;
4574    } else {
4575       while(deref_instr->deref_type != nir_deref_type_var) {
4576          unsigned array_size = glsl_get_aoa_size(deref_instr->type);
4577          if (!array_size)
4578             array_size = 1;
4579
4580          assert(deref_instr->deref_type == nir_deref_type_array);
4581          nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
4582          if (const_value) {
4583             constant_index += array_size * const_value->u32;
4584          } else {
4585             Temp indirect = get_ssa_temp(ctx, deref_instr->arr.index.ssa);
4586             if (indirect.type() == RegType::vgpr)
4587                indirect = bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), indirect);
4588
4589             if (array_size != 1)
4590                indirect = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(array_size), indirect);
4591
4592             if (!index_set) {
4593                index = indirect;
4594                index_set = true;
4595             } else {
4596                index = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), index, indirect);
4597             }
4598          }
4599
4600          deref_instr = nir_src_as_deref(deref_instr->parent);
4601       }
4602       descriptor_set = deref_instr->var->data.descriptor_set;
4603       base_index = deref_instr->var->data.binding;
4604    }
4605
4606    Temp list = load_desc_ptr(ctx, descriptor_set);
4607    list = convert_pointer_to_64_bit(ctx, list);
4608
4609    struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4610    struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4611    unsigned offset = binding->offset;
4612    unsigned stride = binding->size;
4613    aco_opcode opcode;
4614    RegClass type;
4615
4616    assert(base_index < layout->binding_count);
4617
4618    switch (desc_type) {
4619    case ACO_DESC_IMAGE:
4620       type = s8;
4621       opcode = aco_opcode::s_load_dwordx8;
4622       break;
4623    case ACO_DESC_FMASK:
4624       type = s8;
4625       opcode = aco_opcode::s_load_dwordx8;
4626       offset += 32;
4627       break;
4628    case ACO_DESC_SAMPLER:
4629       type = s4;
4630       opcode = aco_opcode::s_load_dwordx4;
4631       if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4632          offset += radv_combined_image_descriptor_sampler_offset(binding);
4633       break;
4634    case ACO_DESC_BUFFER:
4635       type = s4;
4636       opcode = aco_opcode::s_load_dwordx4;
4637       break;
4638    case ACO_DESC_PLANE_0:
4639    case ACO_DESC_PLANE_1:
4640       type = s8;
4641       opcode = aco_opcode::s_load_dwordx8;
4642       offset += 32 * (desc_type - ACO_DESC_PLANE_0);
4643       break;
4644    case ACO_DESC_PLANE_2:
4645       type = s4;
4646       opcode = aco_opcode::s_load_dwordx4;
4647       offset += 64;
4648       break;
4649    default:
4650       unreachable("invalid desc_type\n");
4651    }
4652
4653    offset += constant_index * stride;
4654
4655    if (desc_type == ACO_DESC_SAMPLER && binding->immutable_samplers_offset &&
4656       (!index_set || binding->immutable_samplers_equal)) {
4657       if (binding->immutable_samplers_equal)
4658          constant_index = 0;
4659
4660       const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4661       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
4662                         Operand(samplers[constant_index * 4 + 0]),
4663                         Operand(samplers[constant_index * 4 + 1]),
4664                         Operand(samplers[constant_index * 4 + 2]),
4665                         Operand(samplers[constant_index * 4 + 3]));
4666    }
4667
4668    Operand off;
4669    if (!index_set) {
4670       off = bld.copy(bld.def(s1), Operand(offset));
4671    } else {
4672       off = Operand((Temp)bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc), Operand(offset),
4673                                    bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(stride), index)));
4674    }
4675
4676    Temp res = bld.smem(opcode, bld.def(type), list, off);
4677
4678    if (desc_type == ACO_DESC_PLANE_2) {
4679       Temp components[8];
4680       for (unsigned i = 0; i < 8; i++)
4681          components[i] = bld.tmp(s1);
4682       bld.pseudo(aco_opcode::p_split_vector,
4683                  Definition(components[0]),
4684                  Definition(components[1]),
4685                  Definition(components[2]),
4686                  Definition(components[3]),
4687                  res);
4688
4689       Temp desc2 = get_sampler_desc(ctx, deref_instr, ACO_DESC_PLANE_1, tex_instr, image, write);
4690       bld.pseudo(aco_opcode::p_split_vector,
4691                  bld.def(s1), bld.def(s1), bld.def(s1), bld.def(s1),
4692                  Definition(components[4]),
4693                  Definition(components[5]),
4694                  Definition(components[6]),
4695                  Definition(components[7]),
4696                  desc2);
4697
4698       res = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
4699                        components[0], components[1], components[2], components[3],
4700                        components[4], components[5], components[6], components[7]);
4701    }
4702
4703    return res;
4704 }
4705
4706 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
4707 {
4708    switch (dim) {
4709    case GLSL_SAMPLER_DIM_BUF:
4710       return 1;
4711    case GLSL_SAMPLER_DIM_1D:
4712       return array ? 2 : 1;
4713    case GLSL_SAMPLER_DIM_2D:
4714       return array ? 3 : 2;
4715    case GLSL_SAMPLER_DIM_MS:
4716       return array ? 4 : 3;
4717    case GLSL_SAMPLER_DIM_3D:
4718    case GLSL_SAMPLER_DIM_CUBE:
4719       return 3;
4720    case GLSL_SAMPLER_DIM_RECT:
4721    case GLSL_SAMPLER_DIM_SUBPASS:
4722       return 2;
4723    case GLSL_SAMPLER_DIM_SUBPASS_MS:
4724       return 3;
4725    default:
4726       break;
4727    }
4728    return 0;
4729 }
4730
4731
4732 /* Adjust the sample index according to FMASK.
4733  *
4734  * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4735  * which is the identity mapping. Each nibble says which physical sample
4736  * should be fetched to get that sample.
4737  *
4738  * For example, 0x11111100 means there are only 2 samples stored and
4739  * the second sample covers 3/4 of the pixel. When reading samples 0
4740  * and 1, return physical sample 0 (determined by the first two 0s
4741  * in FMASK), otherwise return physical sample 1.
4742  *
4743  * The sample index should be adjusted as follows:
4744  *   sample_index = (fmask >> (sample_index * 4)) & 0xF;
4745  */
4746 static Temp adjust_sample_index_using_fmask(isel_context *ctx, bool da, std::vector<Temp>& coords, Operand sample_index, Temp fmask_desc_ptr)
4747 {
4748    Builder bld(ctx->program, ctx->block);
4749    Temp fmask = bld.tmp(v1);
4750    unsigned dim = ctx->options->chip_class >= GFX10
4751                   ? ac_get_sampler_dim(ctx->options->chip_class, GLSL_SAMPLER_DIM_2D, da)
4752                   : 0;
4753
4754    Temp coord = da ? bld.pseudo(aco_opcode::p_create_vector, bld.def(v3), coords[0], coords[1], coords[2]) :
4755                      bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), coords[0], coords[1]);
4756    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(aco_opcode::image_load, Format::MIMG, 3, 1)};
4757    load->operands[0] = Operand(fmask_desc_ptr);
4758    load->operands[1] = Operand(s4); /* no sampler */
4759    load->operands[2] = Operand(coord);
4760    load->definitions[0] = Definition(fmask);
4761    load->glc = false;
4762    load->dlc = false;
4763    load->dmask = 0x1;
4764    load->unrm = true;
4765    load->da = da;
4766    load->dim = dim;
4767    load->can_reorder = true; /* fmask images shouldn't be modified */
4768    ctx->block->instructions.emplace_back(std::move(load));
4769
4770    Operand sample_index4;
4771    if (sample_index.isConstant() && sample_index.constantValue() < 16) {
4772       sample_index4 = Operand(sample_index.constantValue() << 2);
4773    } else if (sample_index.regClass() == s1) {
4774       sample_index4 = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), sample_index, Operand(2u));
4775    } else {
4776       assert(sample_index.regClass() == v1);
4777       sample_index4 = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), sample_index);
4778    }
4779
4780    Temp final_sample;
4781    if (sample_index4.isConstant() && sample_index4.constantValue() == 0)
4782       final_sample = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(15u), fmask);
4783    else if (sample_index4.isConstant() && sample_index4.constantValue() == 28)
4784       final_sample = bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(28u), fmask);
4785    else
4786       final_sample = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), fmask, sample_index4, Operand(4u));
4787
4788    /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4789     * resource descriptor is 0 (invalid),
4790     */
4791    Temp compare = bld.tmp(bld.lm);
4792    bld.vopc_e64(aco_opcode::v_cmp_lg_u32, Definition(compare),
4793                 Operand(0u), emit_extract_vector(ctx, fmask_desc_ptr, 1, s1)).def(0).setHint(vcc);
4794
4795    Temp sample_index_v = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), sample_index);
4796
4797    /* Replace the MSAA sample index. */
4798    return bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), sample_index_v, final_sample, compare);
4799 }
4800
4801 static Temp get_image_coords(isel_context *ctx, const nir_intrinsic_instr *instr, const struct glsl_type *type)
4802 {
4803
4804    Temp src0 = get_ssa_temp(ctx, instr->src[1].ssa);
4805    enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4806    bool is_array = glsl_sampler_type_is_array(type);
4807    ASSERTED bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4808    assert(!add_frag_pos && "Input attachments should be lowered.");
4809    bool is_ms = (dim == GLSL_SAMPLER_DIM_MS || dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
4810    bool gfx9_1d = ctx->options->chip_class == GFX9 && dim == GLSL_SAMPLER_DIM_1D;
4811    int count = image_type_to_components_count(dim, is_array);
4812    std::vector<Temp> coords(count);
4813    Builder bld(ctx->program, ctx->block);
4814
4815    if (is_ms) {
4816       count--;
4817       Temp src2 = get_ssa_temp(ctx, instr->src[2].ssa);
4818       /* get sample index */
4819       if (instr->intrinsic == nir_intrinsic_image_deref_load) {
4820          nir_const_value *sample_cv = nir_src_as_const_value(instr->src[2]);
4821          Operand sample_index = sample_cv ? Operand(sample_cv->u32) : Operand(emit_extract_vector(ctx, src2, 0, v1));
4822          std::vector<Temp> fmask_load_address;
4823          for (unsigned i = 0; i < (is_array ? 3 : 2); i++)
4824             fmask_load_address.emplace_back(emit_extract_vector(ctx, src0, i, v1));
4825
4826          Temp fmask_desc_ptr = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_FMASK, nullptr, false, false);
4827          coords[count] = adjust_sample_index_using_fmask(ctx, is_array, fmask_load_address, sample_index, fmask_desc_ptr);
4828       } else {
4829          coords[count] = emit_extract_vector(ctx, src2, 0, v1);
4830       }
4831    }
4832
4833    if (gfx9_1d) {
4834       coords[0] = emit_extract_vector(ctx, src0, 0, v1);
4835       coords.resize(coords.size() + 1);
4836       coords[1] = bld.copy(bld.def(v1), Operand(0u));
4837       if (is_array)
4838          coords[2] = emit_extract_vector(ctx, src0, 1, v1);
4839    } else {
4840       for (int i = 0; i < count; i++)
4841          coords[i] = emit_extract_vector(ctx, src0, i, v1);
4842    }
4843
4844    if (instr->intrinsic == nir_intrinsic_image_deref_load ||
4845        instr->intrinsic == nir_intrinsic_image_deref_store) {
4846       int lod_index = instr->intrinsic == nir_intrinsic_image_deref_load ? 3 : 4;
4847       bool level_zero = nir_src_is_const(instr->src[lod_index]) && nir_src_as_uint(instr->src[lod_index]) == 0;
4848
4849       if (!level_zero)
4850          coords.emplace_back(get_ssa_temp(ctx, instr->src[lod_index].ssa));
4851    }
4852
4853    aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, coords.size(), 1)};
4854    for (unsigned i = 0; i < coords.size(); i++)
4855       vec->operands[i] = Operand(coords[i]);
4856    Temp res = {ctx->program->allocateId(), RegClass(RegType::vgpr, coords.size())};
4857    vec->definitions[0] = Definition(res);
4858    ctx->block->instructions.emplace_back(std::move(vec));
4859    return res;
4860 }
4861
4862
4863 void visit_image_load(isel_context *ctx, nir_intrinsic_instr *instr)
4864 {
4865    Builder bld(ctx->program, ctx->block);
4866    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4867    const struct glsl_type *type = glsl_without_array(var->type);
4868    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4869    bool is_array = glsl_sampler_type_is_array(type);
4870    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
4871
4872    if (dim == GLSL_SAMPLER_DIM_BUF) {
4873       unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
4874       unsigned num_channels = util_last_bit(mask);
4875       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4876       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4877
4878       aco_opcode opcode;
4879       switch (num_channels) {
4880       case 1:
4881          opcode = aco_opcode::buffer_load_format_x;
4882          break;
4883       case 2:
4884          opcode = aco_opcode::buffer_load_format_xy;
4885          break;
4886       case 3:
4887          opcode = aco_opcode::buffer_load_format_xyz;
4888          break;
4889       case 4:
4890          opcode = aco_opcode::buffer_load_format_xyzw;
4891          break;
4892       default:
4893          unreachable(">4 channel buffer image load");
4894       }
4895       aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 3, 1)};
4896       load->operands[0] = Operand(rsrc);
4897       load->operands[1] = Operand(vindex);
4898       load->operands[2] = Operand((uint32_t) 0);
4899       Temp tmp;
4900       if (num_channels == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4901          tmp = dst;
4902       else
4903          tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_channels)};
4904       load->definitions[0] = Definition(tmp);
4905       load->idxen = true;
4906       load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT);
4907       load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4908       load->barrier = barrier_image;
4909       ctx->block->instructions.emplace_back(std::move(load));
4910
4911       expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, (1 << num_channels) - 1);
4912       return;
4913    }
4914
4915    Temp coords = get_image_coords(ctx, instr, type);
4916    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4917
4918    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
4919    unsigned num_components = util_bitcount(dmask);
4920    Temp tmp;
4921    if (num_components == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
4922       tmp = dst;
4923    else
4924       tmp = {ctx->program->allocateId(), RegClass(RegType::vgpr, num_components)};
4925
4926    bool level_zero = nir_src_is_const(instr->src[3]) && nir_src_as_uint(instr->src[3]) == 0;
4927    aco_opcode opcode = level_zero ? aco_opcode::image_load : aco_opcode::image_load_mip;
4928
4929    aco_ptr<MIMG_instruction> load{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1)};
4930    load->operands[0] = Operand(resource);
4931    load->operands[1] = Operand(s4); /* no sampler */
4932    load->operands[2] = Operand(coords);
4933    load->definitions[0] = Definition(tmp);
4934    load->glc = var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT) ? 1 : 0;
4935    load->dlc = load->glc && ctx->options->chip_class >= GFX10;
4936    load->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
4937    load->dmask = dmask;
4938    load->unrm = true;
4939    load->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
4940    load->barrier = barrier_image;
4941    ctx->block->instructions.emplace_back(std::move(load));
4942
4943    expand_vector(ctx, tmp, dst, instr->dest.ssa.num_components, dmask);
4944    return;
4945 }
4946
4947 void visit_image_store(isel_context *ctx, nir_intrinsic_instr *instr)
4948 {
4949    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
4950    const struct glsl_type *type = glsl_without_array(var->type);
4951    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
4952    bool is_array = glsl_sampler_type_is_array(type);
4953    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
4954
4955    bool glc = ctx->options->chip_class == GFX6 || var->data.access & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE) ? 1 : 0;
4956
4957    if (dim == GLSL_SAMPLER_DIM_BUF) {
4958       Temp rsrc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
4959       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
4960       aco_opcode opcode;
4961       switch (data.size()) {
4962       case 1:
4963          opcode = aco_opcode::buffer_store_format_x;
4964          break;
4965       case 2:
4966          opcode = aco_opcode::buffer_store_format_xy;
4967          break;
4968       case 3:
4969          opcode = aco_opcode::buffer_store_format_xyz;
4970          break;
4971       case 4:
4972          opcode = aco_opcode::buffer_store_format_xyzw;
4973          break;
4974       default:
4975          unreachable(">4 channel buffer image store");
4976       }
4977       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
4978       store->operands[0] = Operand(rsrc);
4979       store->operands[1] = Operand(vindex);
4980       store->operands[2] = Operand((uint32_t) 0);
4981       store->operands[3] = Operand(data);
4982       store->idxen = true;
4983       store->glc = glc;
4984       store->dlc = false;
4985       store->disable_wqm = true;
4986       store->barrier = barrier_image;
4987       ctx->program->needs_exact = true;
4988       ctx->block->instructions.emplace_back(std::move(store));
4989       return;
4990    }
4991
4992    assert(data.type() == RegType::vgpr);
4993    Temp coords = get_image_coords(ctx, instr, type);
4994    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
4995
4996    bool level_zero = nir_src_is_const(instr->src[4]) && nir_src_as_uint(instr->src[4]) == 0;
4997    aco_opcode opcode = level_zero ? aco_opcode::image_store : aco_opcode::image_store_mip;
4998
4999    aco_ptr<MIMG_instruction> store{create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 0)};
5000    store->operands[0] = Operand(resource);
5001    store->operands[1] = Operand(data);
5002    store->operands[2] = Operand(coords);
5003    store->glc = glc;
5004    store->dlc = false;
5005    store->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5006    store->dmask = (1 << data.size()) - 1;
5007    store->unrm = true;
5008    store->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5009    store->disable_wqm = true;
5010    store->barrier = barrier_image;
5011    ctx->program->needs_exact = true;
5012    ctx->block->instructions.emplace_back(std::move(store));
5013    return;
5014 }
5015
5016 void visit_image_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5017 {
5018    /* return the previous value if dest is ever used */
5019    bool return_previous = false;
5020    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5021       return_previous = true;
5022       break;
5023    }
5024    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5025       return_previous = true;
5026       break;
5027    }
5028
5029    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5030    const struct glsl_type *type = glsl_without_array(var->type);
5031    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5032    bool is_array = glsl_sampler_type_is_array(type);
5033    Builder bld(ctx->program, ctx->block);
5034
5035    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[3].ssa));
5036    assert(data.size() == 1 && "64bit ssbo atomics not yet implemented.");
5037
5038    if (instr->intrinsic == nir_intrinsic_image_deref_atomic_comp_swap)
5039       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), get_ssa_temp(ctx, instr->src[4].ssa), data);
5040
5041    aco_opcode buf_op, image_op;
5042    switch (instr->intrinsic) {
5043       case nir_intrinsic_image_deref_atomic_add:
5044          buf_op = aco_opcode::buffer_atomic_add;
5045          image_op = aco_opcode::image_atomic_add;
5046          break;
5047       case nir_intrinsic_image_deref_atomic_umin:
5048          buf_op = aco_opcode::buffer_atomic_umin;
5049          image_op = aco_opcode::image_atomic_umin;
5050          break;
5051       case nir_intrinsic_image_deref_atomic_imin:
5052          buf_op = aco_opcode::buffer_atomic_smin;
5053          image_op = aco_opcode::image_atomic_smin;
5054          break;
5055       case nir_intrinsic_image_deref_atomic_umax:
5056          buf_op = aco_opcode::buffer_atomic_umax;
5057          image_op = aco_opcode::image_atomic_umax;
5058          break;
5059       case nir_intrinsic_image_deref_atomic_imax:
5060          buf_op = aco_opcode::buffer_atomic_smax;
5061          image_op = aco_opcode::image_atomic_smax;
5062          break;
5063       case nir_intrinsic_image_deref_atomic_and:
5064          buf_op = aco_opcode::buffer_atomic_and;
5065          image_op = aco_opcode::image_atomic_and;
5066          break;
5067       case nir_intrinsic_image_deref_atomic_or:
5068          buf_op = aco_opcode::buffer_atomic_or;
5069          image_op = aco_opcode::image_atomic_or;
5070          break;
5071       case nir_intrinsic_image_deref_atomic_xor:
5072          buf_op = aco_opcode::buffer_atomic_xor;
5073          image_op = aco_opcode::image_atomic_xor;
5074          break;
5075       case nir_intrinsic_image_deref_atomic_exchange:
5076          buf_op = aco_opcode::buffer_atomic_swap;
5077          image_op = aco_opcode::image_atomic_swap;
5078          break;
5079       case nir_intrinsic_image_deref_atomic_comp_swap:
5080          buf_op = aco_opcode::buffer_atomic_cmpswap;
5081          image_op = aco_opcode::image_atomic_cmpswap;
5082          break;
5083       default:
5084          unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5085    }
5086
5087    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5088
5089    if (dim == GLSL_SAMPLER_DIM_BUF) {
5090       Temp vindex = emit_extract_vector(ctx, get_ssa_temp(ctx, instr->src[1].ssa), 0, v1);
5091       Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, nullptr, true, true);
5092       //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5093       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(buf_op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5094       mubuf->operands[0] = Operand(resource);
5095       mubuf->operands[1] = Operand(vindex);
5096       mubuf->operands[2] = Operand((uint32_t)0);
5097       mubuf->operands[3] = Operand(data);
5098       if (return_previous)
5099          mubuf->definitions[0] = Definition(dst);
5100       mubuf->offset = 0;
5101       mubuf->idxen = true;
5102       mubuf->glc = return_previous;
5103       mubuf->dlc = false; /* Not needed for atomics */
5104       mubuf->disable_wqm = true;
5105       mubuf->barrier = barrier_image;
5106       ctx->program->needs_exact = true;
5107       ctx->block->instructions.emplace_back(std::move(mubuf));
5108       return;
5109    }
5110
5111    Temp coords = get_image_coords(ctx, instr, type);
5112    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, nullptr, true, true);
5113    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(image_op, Format::MIMG, 3, return_previous ? 1 : 0)};
5114    mimg->operands[0] = Operand(resource);
5115    mimg->operands[1] = Operand(data);
5116    mimg->operands[2] = Operand(coords);
5117    if (return_previous)
5118       mimg->definitions[0] = Definition(dst);
5119    mimg->glc = return_previous;
5120    mimg->dlc = false; /* Not needed for atomics */
5121    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5122    mimg->dmask = (1 << data.size()) - 1;
5123    mimg->unrm = true;
5124    mimg->da = should_declare_array(ctx, dim, glsl_sampler_type_is_array(type));
5125    mimg->disable_wqm = true;
5126    mimg->barrier = barrier_image;
5127    ctx->program->needs_exact = true;
5128    ctx->block->instructions.emplace_back(std::move(mimg));
5129    return;
5130 }
5131
5132 void get_buffer_size(isel_context *ctx, Temp desc, Temp dst, bool in_elements)
5133 {
5134    if (in_elements && ctx->options->chip_class == GFX8) {
5135       /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5136       Builder bld(ctx->program, ctx->block);
5137
5138       Temp size = emit_extract_vector(ctx, desc, 2, s1);
5139
5140       Temp size_div3 = bld.vop3(aco_opcode::v_mul_hi_u32, bld.def(v1), bld.copy(bld.def(v1), Operand(0xaaaaaaabu)), size);
5141       size_div3 = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.as_uniform(size_div3), Operand(1u));
5142
5143       Temp stride = emit_extract_vector(ctx, desc, 1, s1);
5144       stride = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), stride, Operand((5u << 16) | 16u));
5145
5146       Temp is12 = bld.sopc(aco_opcode::s_cmp_eq_i32, bld.def(s1, scc), stride, Operand(12u));
5147       size = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1), size_div3, size, bld.scc(is12));
5148
5149       Temp shr_dst = dst.type() == RegType::vgpr ? bld.tmp(s1) : dst;
5150       bld.sop2(aco_opcode::s_lshr_b32, Definition(shr_dst), bld.def(s1, scc),
5151                size, bld.sop1(aco_opcode::s_ff1_i32_b32, bld.def(s1), stride));
5152       if (dst.type() == RegType::vgpr)
5153          bld.copy(Definition(dst), shr_dst);
5154
5155       /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5156    } else {
5157       emit_extract_vector(ctx, desc, 2, dst);
5158    }
5159 }
5160
5161 void visit_image_size(isel_context *ctx, nir_intrinsic_instr *instr)
5162 {
5163    const nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
5164    const struct glsl_type *type = glsl_without_array(var->type);
5165    const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
5166    bool is_array = glsl_sampler_type_is_array(type);
5167    Builder bld(ctx->program, ctx->block);
5168
5169    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
5170       Temp desc = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_BUFFER, NULL, true, false);
5171       return get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), true);
5172    }
5173
5174    /* LOD */
5175    Temp lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
5176
5177    /* Resource */
5178    Temp resource = get_sampler_desc(ctx, nir_instr_as_deref(instr->src[0].ssa->parent_instr), ACO_DESC_IMAGE, NULL, true, false);
5179
5180    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5181
5182    aco_ptr<MIMG_instruction> mimg{create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1)};
5183    mimg->operands[0] = Operand(resource);
5184    mimg->operands[1] = Operand(s4); /* no sampler */
5185    mimg->operands[2] = Operand(lod);
5186    uint8_t& dmask = mimg->dmask;
5187    mimg->dim = ac_get_image_dim(ctx->options->chip_class, dim, is_array);
5188    mimg->dmask = (1 << instr->dest.ssa.num_components) - 1;
5189    mimg->da = glsl_sampler_type_is_array(type);
5190    mimg->can_reorder = true;
5191    Definition& def = mimg->definitions[0];
5192    ctx->block->instructions.emplace_back(std::move(mimg));
5193
5194    if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
5195        glsl_sampler_type_is_array(type)) {
5196
5197       assert(instr->dest.ssa.num_components == 3);
5198       Temp tmp = {ctx->program->allocateId(), v3};
5199       def = Definition(tmp);
5200       emit_split_vector(ctx, tmp, 3);
5201
5202       /* divide 3rd value by 6 by multiplying with magic number */
5203       Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
5204       Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp, 2, v1), c);
5205
5206       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5207                  emit_extract_vector(ctx, tmp, 0, v1),
5208                  emit_extract_vector(ctx, tmp, 1, v1),
5209                  by_6);
5210
5211    } else if (ctx->options->chip_class == GFX9 &&
5212               glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
5213               glsl_sampler_type_is_array(type)) {
5214       assert(instr->dest.ssa.num_components == 2);
5215       def = Definition(dst);
5216       dmask = 0x5;
5217    } else {
5218       def = Definition(dst);
5219    }
5220
5221    emit_split_vector(ctx, dst, instr->dest.ssa.num_components);
5222 }
5223
5224 void visit_load_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5225 {
5226    Builder bld(ctx->program, ctx->block);
5227    unsigned num_components = instr->num_components;
5228
5229    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5230    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5231    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5232
5233    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5234    load_buffer(ctx, num_components, dst, rsrc, get_ssa_temp(ctx, instr->src[1].ssa), glc, false);
5235 }
5236
5237 void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5238 {
5239    Builder bld(ctx->program, ctx->block);
5240    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5241    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5242    unsigned writemask = nir_intrinsic_write_mask(instr);
5243    Temp offset = get_ssa_temp(ctx, instr->src[2].ssa);
5244
5245    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5246    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5247
5248    bool smem = !ctx->divergent_vals[instr->src[2].ssa->index] &&
5249                ctx->options->chip_class >= GFX8;
5250    if (smem)
5251       offset = bld.as_uniform(offset);
5252    bool smem_nonfs = smem && ctx->stage != fragment_fs;
5253
5254    while (writemask) {
5255       int start, count;
5256       u_bit_scan_consecutive_range(&writemask, &start, &count);
5257       if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
5258          /* GFX6 doesn't support storing vec3, split it. */
5259          writemask |= 1u << (start + 2);
5260          count = 2;
5261       }
5262       int num_bytes = count * elem_size_bytes;
5263
5264       if (num_bytes > 16) {
5265          assert(elem_size_bytes == 8);
5266          writemask |= (((count - 2) << 1) - 1) << (start + 2);
5267          count = 2;
5268          num_bytes = 16;
5269       }
5270
5271       // TODO: check alignment of sub-dword stores
5272       // TODO: split 3 bytes. there is no store instruction for that
5273
5274       Temp write_data;
5275       if (count != instr->num_components) {
5276          emit_split_vector(ctx, data, instr->num_components);
5277          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5278          for (int i = 0; i < count; i++) {
5279             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(data.type(), elem_size_bytes / 4));
5280             vec->operands[i] = Operand(smem_nonfs ? bld.as_uniform(elem) : elem);
5281          }
5282          write_data = bld.tmp(!smem ? RegType::vgpr : smem_nonfs ? RegType::sgpr : data.type(), count * elem_size_bytes / 4);
5283          vec->definitions[0] = Definition(write_data);
5284          ctx->block->instructions.emplace_back(std::move(vec));
5285       } else if (!smem && data.type() != RegType::vgpr) {
5286          assert(num_bytes % 4 == 0);
5287          write_data = bld.copy(bld.def(RegType::vgpr, num_bytes / 4), data);
5288       } else if (smem_nonfs && data.type() == RegType::vgpr) {
5289          assert(num_bytes % 4 == 0);
5290          write_data = bld.as_uniform(data);
5291       } else {
5292          write_data = data;
5293       }
5294
5295       aco_opcode vmem_op, smem_op;
5296       switch (num_bytes) {
5297          case 4:
5298             vmem_op = aco_opcode::buffer_store_dword;
5299             smem_op = aco_opcode::s_buffer_store_dword;
5300             break;
5301          case 8:
5302             vmem_op = aco_opcode::buffer_store_dwordx2;
5303             smem_op = aco_opcode::s_buffer_store_dwordx2;
5304             break;
5305          case 12:
5306             vmem_op = aco_opcode::buffer_store_dwordx3;
5307             smem_op = aco_opcode::last_opcode;
5308             assert(!smem && ctx->options->chip_class > GFX6);
5309             break;
5310          case 16:
5311             vmem_op = aco_opcode::buffer_store_dwordx4;
5312             smem_op = aco_opcode::s_buffer_store_dwordx4;
5313             break;
5314          default:
5315             unreachable("Store SSBO not implemented for this size.");
5316       }
5317       if (ctx->stage == fragment_fs)
5318          smem_op = aco_opcode::p_fs_buffer_store_smem;
5319
5320       if (smem) {
5321          aco_ptr<SMEM_instruction> store{create_instruction<SMEM_instruction>(smem_op, Format::SMEM, 3, 0)};
5322          store->operands[0] = Operand(rsrc);
5323          if (start) {
5324             Temp off = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
5325                                 offset, Operand(start * elem_size_bytes));
5326             store->operands[1] = Operand(off);
5327          } else {
5328             store->operands[1] = Operand(offset);
5329          }
5330          if (smem_op != aco_opcode::p_fs_buffer_store_smem)
5331             store->operands[1].setFixed(m0);
5332          store->operands[2] = Operand(write_data);
5333          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5334          store->dlc = false;
5335          store->disable_wqm = true;
5336          store->barrier = barrier_buffer;
5337          ctx->block->instructions.emplace_back(std::move(store));
5338          ctx->program->wb_smem_l1_on_end = true;
5339          if (smem_op == aco_opcode::p_fs_buffer_store_smem) {
5340             ctx->block->kind |= block_kind_needs_lowering;
5341             ctx->program->needs_exact = true;
5342          }
5343       } else {
5344          aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(vmem_op, Format::MUBUF, 4, 0)};
5345          store->operands[0] = Operand(rsrc);
5346          store->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5347          store->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5348          store->operands[3] = Operand(write_data);
5349          store->offset = start * elem_size_bytes;
5350          store->offen = (offset.type() == RegType::vgpr);
5351          store->glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5352          store->dlc = false;
5353          store->disable_wqm = true;
5354          store->barrier = barrier_buffer;
5355          ctx->program->needs_exact = true;
5356          ctx->block->instructions.emplace_back(std::move(store));
5357       }
5358    }
5359 }
5360
5361 void visit_atomic_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
5362 {
5363    /* return the previous value if dest is ever used */
5364    bool return_previous = false;
5365    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5366       return_previous = true;
5367       break;
5368    }
5369    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5370       return_previous = true;
5371       break;
5372    }
5373
5374    Builder bld(ctx->program, ctx->block);
5375    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[2].ssa));
5376
5377    if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap)
5378       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5379                         get_ssa_temp(ctx, instr->src[3].ssa), data);
5380
5381    Temp offset = get_ssa_temp(ctx, instr->src[1].ssa);
5382    Temp rsrc = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5383    rsrc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), rsrc, Operand(0u));
5384
5385    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5386
5387    aco_opcode op32, op64;
5388    switch (instr->intrinsic) {
5389       case nir_intrinsic_ssbo_atomic_add:
5390          op32 = aco_opcode::buffer_atomic_add;
5391          op64 = aco_opcode::buffer_atomic_add_x2;
5392          break;
5393       case nir_intrinsic_ssbo_atomic_imin:
5394          op32 = aco_opcode::buffer_atomic_smin;
5395          op64 = aco_opcode::buffer_atomic_smin_x2;
5396          break;
5397       case nir_intrinsic_ssbo_atomic_umin:
5398          op32 = aco_opcode::buffer_atomic_umin;
5399          op64 = aco_opcode::buffer_atomic_umin_x2;
5400          break;
5401       case nir_intrinsic_ssbo_atomic_imax:
5402          op32 = aco_opcode::buffer_atomic_smax;
5403          op64 = aco_opcode::buffer_atomic_smax_x2;
5404          break;
5405       case nir_intrinsic_ssbo_atomic_umax:
5406          op32 = aco_opcode::buffer_atomic_umax;
5407          op64 = aco_opcode::buffer_atomic_umax_x2;
5408          break;
5409       case nir_intrinsic_ssbo_atomic_and:
5410          op32 = aco_opcode::buffer_atomic_and;
5411          op64 = aco_opcode::buffer_atomic_and_x2;
5412          break;
5413       case nir_intrinsic_ssbo_atomic_or:
5414          op32 = aco_opcode::buffer_atomic_or;
5415          op64 = aco_opcode::buffer_atomic_or_x2;
5416          break;
5417       case nir_intrinsic_ssbo_atomic_xor:
5418          op32 = aco_opcode::buffer_atomic_xor;
5419          op64 = aco_opcode::buffer_atomic_xor_x2;
5420          break;
5421       case nir_intrinsic_ssbo_atomic_exchange:
5422          op32 = aco_opcode::buffer_atomic_swap;
5423          op64 = aco_opcode::buffer_atomic_swap_x2;
5424          break;
5425       case nir_intrinsic_ssbo_atomic_comp_swap:
5426          op32 = aco_opcode::buffer_atomic_cmpswap;
5427          op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5428          break;
5429       default:
5430          unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
5431    }
5432    aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5433    aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5434    mubuf->operands[0] = Operand(rsrc);
5435    mubuf->operands[1] = offset.type() == RegType::vgpr ? Operand(offset) : Operand(v1);
5436    mubuf->operands[2] = offset.type() == RegType::sgpr ? Operand(offset) : Operand((uint32_t) 0);
5437    mubuf->operands[3] = Operand(data);
5438    if (return_previous)
5439       mubuf->definitions[0] = Definition(dst);
5440    mubuf->offset = 0;
5441    mubuf->offen = (offset.type() == RegType::vgpr);
5442    mubuf->glc = return_previous;
5443    mubuf->dlc = false; /* Not needed for atomics */
5444    mubuf->disable_wqm = true;
5445    mubuf->barrier = barrier_buffer;
5446    ctx->program->needs_exact = true;
5447    ctx->block->instructions.emplace_back(std::move(mubuf));
5448 }
5449
5450 void visit_get_buffer_size(isel_context *ctx, nir_intrinsic_instr *instr) {
5451
5452    Temp index = convert_pointer_to_64_bit(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5453    Builder bld(ctx->program, ctx->block);
5454    Temp desc = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), index, Operand(0u));
5455    get_buffer_size(ctx, desc, get_ssa_temp(ctx, &instr->dest.ssa), false);
5456 }
5457
5458 Temp get_gfx6_global_rsrc(Builder& bld, Temp addr)
5459 {
5460    uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5461                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
5462
5463    if (addr.type() == RegType::vgpr)
5464       return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf));
5465    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), addr, Operand(-1u), Operand(rsrc_conf));
5466 }
5467
5468 void visit_load_global(isel_context *ctx, nir_intrinsic_instr *instr)
5469 {
5470    Builder bld(ctx->program, ctx->block);
5471    unsigned num_components = instr->num_components;
5472    unsigned num_bytes = num_components * instr->dest.ssa.bit_size / 8;
5473
5474    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5475    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5476
5477    bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT);
5478    bool dlc = glc && ctx->options->chip_class >= GFX10;
5479    aco_opcode op;
5480    if (dst.type() == RegType::vgpr || (glc && ctx->options->chip_class < GFX8)) {
5481       bool global = ctx->options->chip_class >= GFX9;
5482
5483       if (ctx->options->chip_class >= GFX7) {
5484          aco_opcode op;
5485          switch (num_bytes) {
5486          case 4:
5487             op = global ? aco_opcode::global_load_dword : aco_opcode::flat_load_dword;
5488             break;
5489          case 8:
5490             op = global ? aco_opcode::global_load_dwordx2 : aco_opcode::flat_load_dwordx2;
5491             break;
5492          case 12:
5493             op = global ? aco_opcode::global_load_dwordx3 : aco_opcode::flat_load_dwordx3;
5494             break;
5495          case 16:
5496             op = global ? aco_opcode::global_load_dwordx4 : aco_opcode::flat_load_dwordx4;
5497             break;
5498          default:
5499             unreachable("load_global not implemented for this size.");
5500          }
5501
5502          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 2, 1)};
5503          flat->operands[0] = Operand(addr);
5504          flat->operands[1] = Operand(s1);
5505          flat->glc = glc;
5506          flat->dlc = dlc;
5507          flat->barrier = barrier_buffer;
5508
5509          if (dst.type() == RegType::sgpr) {
5510             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5511             flat->definitions[0] = Definition(vec);
5512             ctx->block->instructions.emplace_back(std::move(flat));
5513             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5514          } else {
5515             flat->definitions[0] = Definition(dst);
5516             ctx->block->instructions.emplace_back(std::move(flat));
5517          }
5518          emit_split_vector(ctx, dst, num_components);
5519       } else {
5520          assert(ctx->options->chip_class == GFX6);
5521
5522          /* GFX6 doesn't support loading vec3, expand to vec4. */
5523          num_bytes = num_bytes == 12 ? 16 : num_bytes;
5524
5525          aco_opcode op;
5526          switch (num_bytes) {
5527          case 4:
5528             op = aco_opcode::buffer_load_dword;
5529             break;
5530          case 8:
5531             op = aco_opcode::buffer_load_dwordx2;
5532             break;
5533          case 16:
5534             op = aco_opcode::buffer_load_dwordx4;
5535             break;
5536          default:
5537             unreachable("load_global not implemented for this size.");
5538          }
5539
5540          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5541
5542          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
5543          mubuf->operands[0] = Operand(rsrc);
5544          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5545          mubuf->operands[2] = Operand(0u);
5546          mubuf->glc = glc;
5547          mubuf->dlc = false;
5548          mubuf->offset = 0;
5549          mubuf->addr64 = addr.type() == RegType::vgpr;
5550          mubuf->disable_wqm = false;
5551          mubuf->barrier = barrier_buffer;
5552          aco_ptr<Instruction> instr = std::move(mubuf);
5553
5554          /* expand vector */
5555          if (dst.size() == 3) {
5556             Temp vec = bld.tmp(v4);
5557             instr->definitions[0] = Definition(vec);
5558             bld.insert(std::move(instr));
5559             emit_split_vector(ctx, vec, 4);
5560
5561             instr.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, 3, 1));
5562             instr->operands[0] = Operand(emit_extract_vector(ctx, vec, 0, v1));
5563             instr->operands[1] = Operand(emit_extract_vector(ctx, vec, 1, v1));
5564             instr->operands[2] = Operand(emit_extract_vector(ctx, vec, 2, v1));
5565          }
5566
5567          if (dst.type() == RegType::sgpr) {
5568             Temp vec = bld.tmp(RegType::vgpr, dst.size());
5569             instr->definitions[0] = Definition(vec);
5570             bld.insert(std::move(instr));
5571             expand_vector(ctx, vec, dst, num_components, (1 << num_components) - 1);
5572             bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), vec);
5573          } else {
5574             instr->definitions[0] = Definition(dst);
5575             bld.insert(std::move(instr));
5576             emit_split_vector(ctx, dst, num_components);
5577          }
5578       }
5579    } else {
5580       switch (num_bytes) {
5581          case 4:
5582             op = aco_opcode::s_load_dword;
5583             break;
5584          case 8:
5585             op = aco_opcode::s_load_dwordx2;
5586             break;
5587          case 12:
5588          case 16:
5589             op = aco_opcode::s_load_dwordx4;
5590             break;
5591          default:
5592             unreachable("load_global not implemented for this size.");
5593       }
5594       aco_ptr<SMEM_instruction> load{create_instruction<SMEM_instruction>(op, Format::SMEM, 2, 1)};
5595       load->operands[0] = Operand(addr);
5596       load->operands[1] = Operand(0u);
5597       load->definitions[0] = Definition(dst);
5598       load->glc = glc;
5599       load->dlc = dlc;
5600       load->barrier = barrier_buffer;
5601       assert(ctx->options->chip_class >= GFX8 || !glc);
5602
5603       if (dst.size() == 3) {
5604          /* trim vector */
5605          Temp vec = bld.tmp(s4);
5606          load->definitions[0] = Definition(vec);
5607          ctx->block->instructions.emplace_back(std::move(load));
5608          emit_split_vector(ctx, vec, 4);
5609
5610          bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
5611                     emit_extract_vector(ctx, vec, 0, s1),
5612                     emit_extract_vector(ctx, vec, 1, s1),
5613                     emit_extract_vector(ctx, vec, 2, s1));
5614       } else {
5615          ctx->block->instructions.emplace_back(std::move(load));
5616       }
5617    }
5618 }
5619
5620 void visit_store_global(isel_context *ctx, nir_intrinsic_instr *instr)
5621 {
5622    Builder bld(ctx->program, ctx->block);
5623    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5624
5625    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5626    Temp addr = get_ssa_temp(ctx, instr->src[1].ssa);
5627
5628    if (ctx->options->chip_class >= GFX7)
5629       addr = as_vgpr(ctx, addr);
5630
5631    unsigned writemask = nir_intrinsic_write_mask(instr);
5632    while (writemask) {
5633       int start, count;
5634       u_bit_scan_consecutive_range(&writemask, &start, &count);
5635       if (count == 3 && ctx->options->chip_class == GFX6) {
5636          /* GFX6 doesn't support storing vec3, split it. */
5637          writemask |= 1u << (start + 2);
5638          count = 2;
5639       }
5640       unsigned num_bytes = count * elem_size_bytes;
5641
5642       Temp write_data = data;
5643       if (count != instr->num_components) {
5644          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
5645          for (int i = 0; i < count; i++)
5646             vec->operands[i] = Operand(emit_extract_vector(ctx, data, start + i, v1));
5647          write_data = bld.tmp(RegType::vgpr, count);
5648          vec->definitions[0] = Definition(write_data);
5649          ctx->block->instructions.emplace_back(std::move(vec));
5650       }
5651
5652       bool glc = nir_intrinsic_access(instr) & (ACCESS_VOLATILE | ACCESS_COHERENT | ACCESS_NON_READABLE);
5653       unsigned offset = start * elem_size_bytes;
5654
5655       if (ctx->options->chip_class >= GFX7) {
5656          if (offset > 0 && ctx->options->chip_class < GFX9) {
5657             Temp addr0 = bld.tmp(v1), addr1 = bld.tmp(v1);
5658             Temp new_addr0 = bld.tmp(v1), new_addr1 = bld.tmp(v1);
5659             Temp carry = bld.tmp(bld.lm);
5660             bld.pseudo(aco_opcode::p_split_vector, Definition(addr0), Definition(addr1), addr);
5661
5662             bld.vop2(aco_opcode::v_add_co_u32, Definition(new_addr0), bld.hint_vcc(Definition(carry)),
5663                      Operand(offset), addr0);
5664             bld.vop2(aco_opcode::v_addc_co_u32, Definition(new_addr1), bld.def(bld.lm),
5665                      Operand(0u), addr1,
5666                      carry).def(1).setHint(vcc);
5667
5668             addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), new_addr0, new_addr1);
5669
5670             offset = 0;
5671          }
5672
5673          bool global = ctx->options->chip_class >= GFX9;
5674          aco_opcode op;
5675          switch (num_bytes) {
5676          case 4:
5677             op = global ? aco_opcode::global_store_dword : aco_opcode::flat_store_dword;
5678             break;
5679          case 8:
5680             op = global ? aco_opcode::global_store_dwordx2 : aco_opcode::flat_store_dwordx2;
5681             break;
5682          case 12:
5683             op = global ? aco_opcode::global_store_dwordx3 : aco_opcode::flat_store_dwordx3;
5684             break;
5685          case 16:
5686             op = global ? aco_opcode::global_store_dwordx4 : aco_opcode::flat_store_dwordx4;
5687             break;
5688          default:
5689             unreachable("store_global not implemented for this size.");
5690          }
5691
5692          aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, 0)};
5693          flat->operands[0] = Operand(addr);
5694          flat->operands[1] = Operand(s1);
5695          flat->operands[2] = Operand(data);
5696          flat->glc = glc;
5697          flat->dlc = false;
5698          flat->offset = offset;
5699          flat->disable_wqm = true;
5700          flat->barrier = barrier_buffer;
5701          ctx->program->needs_exact = true;
5702          ctx->block->instructions.emplace_back(std::move(flat));
5703       } else {
5704          assert(ctx->options->chip_class == GFX6);
5705
5706          aco_opcode op;
5707          switch (num_bytes) {
5708          case 4:
5709             op = aco_opcode::buffer_store_dword;
5710             break;
5711          case 8:
5712             op = aco_opcode::buffer_store_dwordx2;
5713             break;
5714          case 16:
5715             op = aco_opcode::buffer_store_dwordx4;
5716             break;
5717          default:
5718             unreachable("store_global not implemented for this size.");
5719          }
5720
5721          Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5722
5723          aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, 0)};
5724          mubuf->operands[0] = Operand(rsrc);
5725          mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5726          mubuf->operands[2] = Operand(0u);
5727          mubuf->operands[3] = Operand(write_data);
5728          mubuf->glc = glc;
5729          mubuf->dlc = false;
5730          mubuf->offset = offset;
5731          mubuf->addr64 = addr.type() == RegType::vgpr;
5732          mubuf->disable_wqm = true;
5733          mubuf->barrier = barrier_buffer;
5734          ctx->program->needs_exact = true;
5735          ctx->block->instructions.emplace_back(std::move(mubuf));
5736       }
5737    }
5738 }
5739
5740 void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5741 {
5742    /* return the previous value if dest is ever used */
5743    bool return_previous = false;
5744    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
5745       return_previous = true;
5746       break;
5747    }
5748    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
5749       return_previous = true;
5750       break;
5751    }
5752
5753    Builder bld(ctx->program, ctx->block);
5754    Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
5755    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5756
5757    if (ctx->options->chip_class >= GFX7)
5758       addr = as_vgpr(ctx, addr);
5759
5760    if (instr->intrinsic == nir_intrinsic_global_atomic_comp_swap)
5761       data = bld.pseudo(aco_opcode::p_create_vector, bld.def(RegType::vgpr, data.size() * 2),
5762                         get_ssa_temp(ctx, instr->src[2].ssa), data);
5763
5764    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5765
5766    aco_opcode op32, op64;
5767
5768    if (ctx->options->chip_class >= GFX7) {
5769       bool global = ctx->options->chip_class >= GFX9;
5770       switch (instr->intrinsic) {
5771          case nir_intrinsic_global_atomic_add:
5772             op32 = global ? aco_opcode::global_atomic_add : aco_opcode::flat_atomic_add;
5773             op64 = global ? aco_opcode::global_atomic_add_x2 : aco_opcode::flat_atomic_add_x2;
5774             break;
5775          case nir_intrinsic_global_atomic_imin:
5776             op32 = global ? aco_opcode::global_atomic_smin : aco_opcode::flat_atomic_smin;
5777             op64 = global ? aco_opcode::global_atomic_smin_x2 : aco_opcode::flat_atomic_smin_x2;
5778             break;
5779          case nir_intrinsic_global_atomic_umin:
5780             op32 = global ? aco_opcode::global_atomic_umin : aco_opcode::flat_atomic_umin;
5781             op64 = global ? aco_opcode::global_atomic_umin_x2 : aco_opcode::flat_atomic_umin_x2;
5782             break;
5783          case nir_intrinsic_global_atomic_imax:
5784             op32 = global ? aco_opcode::global_atomic_smax : aco_opcode::flat_atomic_smax;
5785             op64 = global ? aco_opcode::global_atomic_smax_x2 : aco_opcode::flat_atomic_smax_x2;
5786             break;
5787          case nir_intrinsic_global_atomic_umax:
5788             op32 = global ? aco_opcode::global_atomic_umax : aco_opcode::flat_atomic_umax;
5789             op64 = global ? aco_opcode::global_atomic_umax_x2 : aco_opcode::flat_atomic_umax_x2;
5790             break;
5791          case nir_intrinsic_global_atomic_and:
5792             op32 = global ? aco_opcode::global_atomic_and : aco_opcode::flat_atomic_and;
5793             op64 = global ? aco_opcode::global_atomic_and_x2 : aco_opcode::flat_atomic_and_x2;
5794             break;
5795          case nir_intrinsic_global_atomic_or:
5796             op32 = global ? aco_opcode::global_atomic_or : aco_opcode::flat_atomic_or;
5797             op64 = global ? aco_opcode::global_atomic_or_x2 : aco_opcode::flat_atomic_or_x2;
5798             break;
5799          case nir_intrinsic_global_atomic_xor:
5800             op32 = global ? aco_opcode::global_atomic_xor : aco_opcode::flat_atomic_xor;
5801             op64 = global ? aco_opcode::global_atomic_xor_x2 : aco_opcode::flat_atomic_xor_x2;
5802             break;
5803          case nir_intrinsic_global_atomic_exchange:
5804             op32 = global ? aco_opcode::global_atomic_swap : aco_opcode::flat_atomic_swap;
5805             op64 = global ? aco_opcode::global_atomic_swap_x2 : aco_opcode::flat_atomic_swap_x2;
5806             break;
5807          case nir_intrinsic_global_atomic_comp_swap:
5808             op32 = global ? aco_opcode::global_atomic_cmpswap : aco_opcode::flat_atomic_cmpswap;
5809             op64 = global ? aco_opcode::global_atomic_cmpswap_x2 : aco_opcode::flat_atomic_cmpswap_x2;
5810             break;
5811          default:
5812             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5813       }
5814
5815       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5816       aco_ptr<FLAT_instruction> flat{create_instruction<FLAT_instruction>(op, global ? Format::GLOBAL : Format::FLAT, 3, return_previous ? 1 : 0)};
5817       flat->operands[0] = Operand(addr);
5818       flat->operands[1] = Operand(s1);
5819       flat->operands[2] = Operand(data);
5820       if (return_previous)
5821          flat->definitions[0] = Definition(dst);
5822       flat->glc = return_previous;
5823       flat->dlc = false; /* Not needed for atomics */
5824       flat->offset = 0;
5825       flat->disable_wqm = true;
5826       flat->barrier = barrier_buffer;
5827       ctx->program->needs_exact = true;
5828       ctx->block->instructions.emplace_back(std::move(flat));
5829    } else {
5830       assert(ctx->options->chip_class == GFX6);
5831
5832       switch (instr->intrinsic) {
5833          case nir_intrinsic_global_atomic_add:
5834             op32 = aco_opcode::buffer_atomic_add;
5835             op64 = aco_opcode::buffer_atomic_add_x2;
5836             break;
5837          case nir_intrinsic_global_atomic_imin:
5838             op32 = aco_opcode::buffer_atomic_smin;
5839             op64 = aco_opcode::buffer_atomic_smin_x2;
5840             break;
5841          case nir_intrinsic_global_atomic_umin:
5842             op32 = aco_opcode::buffer_atomic_umin;
5843             op64 = aco_opcode::buffer_atomic_umin_x2;
5844             break;
5845          case nir_intrinsic_global_atomic_imax:
5846             op32 = aco_opcode::buffer_atomic_smax;
5847             op64 = aco_opcode::buffer_atomic_smax_x2;
5848             break;
5849          case nir_intrinsic_global_atomic_umax:
5850             op32 = aco_opcode::buffer_atomic_umax;
5851             op64 = aco_opcode::buffer_atomic_umax_x2;
5852             break;
5853          case nir_intrinsic_global_atomic_and:
5854             op32 = aco_opcode::buffer_atomic_and;
5855             op64 = aco_opcode::buffer_atomic_and_x2;
5856             break;
5857          case nir_intrinsic_global_atomic_or:
5858             op32 = aco_opcode::buffer_atomic_or;
5859             op64 = aco_opcode::buffer_atomic_or_x2;
5860             break;
5861          case nir_intrinsic_global_atomic_xor:
5862             op32 = aco_opcode::buffer_atomic_xor;
5863             op64 = aco_opcode::buffer_atomic_xor_x2;
5864             break;
5865          case nir_intrinsic_global_atomic_exchange:
5866             op32 = aco_opcode::buffer_atomic_swap;
5867             op64 = aco_opcode::buffer_atomic_swap_x2;
5868             break;
5869          case nir_intrinsic_global_atomic_comp_swap:
5870             op32 = aco_opcode::buffer_atomic_cmpswap;
5871             op64 = aco_opcode::buffer_atomic_cmpswap_x2;
5872             break;
5873          default:
5874             unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
5875       }
5876
5877       Temp rsrc = get_gfx6_global_rsrc(bld, addr);
5878
5879       aco_opcode op = instr->dest.ssa.bit_size == 32 ? op32 : op64;
5880
5881       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 4, return_previous ? 1 : 0)};
5882       mubuf->operands[0] = Operand(rsrc);
5883       mubuf->operands[1] = addr.type() == RegType::vgpr ? Operand(addr) : Operand(v1);
5884       mubuf->operands[2] = Operand(0u);
5885       mubuf->operands[3] = Operand(data);
5886       if (return_previous)
5887          mubuf->definitions[0] = Definition(dst);
5888       mubuf->glc = return_previous;
5889       mubuf->dlc = false;
5890       mubuf->offset = 0;
5891       mubuf->addr64 = addr.type() == RegType::vgpr;
5892       mubuf->disable_wqm = true;
5893       mubuf->barrier = barrier_buffer;
5894       ctx->program->needs_exact = true;
5895       ctx->block->instructions.emplace_back(std::move(mubuf));
5896    }
5897 }
5898
5899 void emit_memory_barrier(isel_context *ctx, nir_intrinsic_instr *instr) {
5900    Builder bld(ctx->program, ctx->block);
5901    switch(instr->intrinsic) {
5902       case nir_intrinsic_group_memory_barrier:
5903       case nir_intrinsic_memory_barrier:
5904          bld.barrier(aco_opcode::p_memory_barrier_common);
5905          break;
5906       case nir_intrinsic_memory_barrier_buffer:
5907          bld.barrier(aco_opcode::p_memory_barrier_buffer);
5908          break;
5909       case nir_intrinsic_memory_barrier_image:
5910          bld.barrier(aco_opcode::p_memory_barrier_image);
5911          break;
5912       case nir_intrinsic_memory_barrier_tcs_patch:
5913       case nir_intrinsic_memory_barrier_shared:
5914          bld.barrier(aco_opcode::p_memory_barrier_shared);
5915          break;
5916       default:
5917          unreachable("Unimplemented memory barrier intrinsic");
5918          break;
5919    }
5920 }
5921
5922 void visit_load_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5923 {
5924    // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
5925    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
5926    assert(instr->dest.ssa.bit_size >= 32 && "Bitsize not supported in load_shared.");
5927    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5928    Builder bld(ctx->program, ctx->block);
5929
5930    unsigned elem_size_bytes = instr->dest.ssa.bit_size / 8;
5931    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5932    load_lds(ctx, elem_size_bytes, dst, address, nir_intrinsic_base(instr), align);
5933 }
5934
5935 void visit_store_shared(isel_context *ctx, nir_intrinsic_instr *instr)
5936 {
5937    unsigned writemask = nir_intrinsic_write_mask(instr);
5938    Temp data = get_ssa_temp(ctx, instr->src[0].ssa);
5939    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5940    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
5941    assert(elem_size_bytes >= 4 && "Only 32bit & 64bit store_shared currently supported.");
5942
5943    unsigned align = nir_intrinsic_align_mul(instr) ? nir_intrinsic_align(instr) : elem_size_bytes;
5944    store_lds(ctx, elem_size_bytes, data, writemask, address, nir_intrinsic_base(instr), align);
5945 }
5946
5947 void visit_shared_atomic(isel_context *ctx, nir_intrinsic_instr *instr)
5948 {
5949    unsigned offset = nir_intrinsic_base(instr);
5950    Operand m = load_lds_size_m0(ctx);
5951    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
5952    Temp address = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
5953
5954    unsigned num_operands = 3;
5955    aco_opcode op32, op64, op32_rtn, op64_rtn;
5956    switch(instr->intrinsic) {
5957       case nir_intrinsic_shared_atomic_add:
5958          op32 = aco_opcode::ds_add_u32;
5959          op64 = aco_opcode::ds_add_u64;
5960          op32_rtn = aco_opcode::ds_add_rtn_u32;
5961          op64_rtn = aco_opcode::ds_add_rtn_u64;
5962          break;
5963       case nir_intrinsic_shared_atomic_imin:
5964          op32 = aco_opcode::ds_min_i32;
5965          op64 = aco_opcode::ds_min_i64;
5966          op32_rtn = aco_opcode::ds_min_rtn_i32;
5967          op64_rtn = aco_opcode::ds_min_rtn_i64;
5968          break;
5969       case nir_intrinsic_shared_atomic_umin:
5970          op32 = aco_opcode::ds_min_u32;
5971          op64 = aco_opcode::ds_min_u64;
5972          op32_rtn = aco_opcode::ds_min_rtn_u32;
5973          op64_rtn = aco_opcode::ds_min_rtn_u64;
5974          break;
5975       case nir_intrinsic_shared_atomic_imax:
5976          op32 = aco_opcode::ds_max_i32;
5977          op64 = aco_opcode::ds_max_i64;
5978          op32_rtn = aco_opcode::ds_max_rtn_i32;
5979          op64_rtn = aco_opcode::ds_max_rtn_i64;
5980          break;
5981       case nir_intrinsic_shared_atomic_umax:
5982          op32 = aco_opcode::ds_max_u32;
5983          op64 = aco_opcode::ds_max_u64;
5984          op32_rtn = aco_opcode::ds_max_rtn_u32;
5985          op64_rtn = aco_opcode::ds_max_rtn_u64;
5986          break;
5987       case nir_intrinsic_shared_atomic_and:
5988          op32 = aco_opcode::ds_and_b32;
5989          op64 = aco_opcode::ds_and_b64;
5990          op32_rtn = aco_opcode::ds_and_rtn_b32;
5991          op64_rtn = aco_opcode::ds_and_rtn_b64;
5992          break;
5993       case nir_intrinsic_shared_atomic_or:
5994          op32 = aco_opcode::ds_or_b32;
5995          op64 = aco_opcode::ds_or_b64;
5996          op32_rtn = aco_opcode::ds_or_rtn_b32;
5997          op64_rtn = aco_opcode::ds_or_rtn_b64;
5998          break;
5999       case nir_intrinsic_shared_atomic_xor:
6000          op32 = aco_opcode::ds_xor_b32;
6001          op64 = aco_opcode::ds_xor_b64;
6002          op32_rtn = aco_opcode::ds_xor_rtn_b32;
6003          op64_rtn = aco_opcode::ds_xor_rtn_b64;
6004          break;
6005       case nir_intrinsic_shared_atomic_exchange:
6006          op32 = aco_opcode::ds_write_b32;
6007          op64 = aco_opcode::ds_write_b64;
6008          op32_rtn = aco_opcode::ds_wrxchg_rtn_b32;
6009          op64_rtn = aco_opcode::ds_wrxchg2_rtn_b64;
6010          break;
6011       case nir_intrinsic_shared_atomic_comp_swap:
6012          op32 = aco_opcode::ds_cmpst_b32;
6013          op64 = aco_opcode::ds_cmpst_b64;
6014          op32_rtn = aco_opcode::ds_cmpst_rtn_b32;
6015          op64_rtn = aco_opcode::ds_cmpst_rtn_b64;
6016          num_operands = 4;
6017          break;
6018       default:
6019          unreachable("Unhandled shared atomic intrinsic");
6020    }
6021
6022    /* return the previous value if dest is ever used */
6023    bool return_previous = false;
6024    nir_foreach_use_safe(use_src, &instr->dest.ssa) {
6025       return_previous = true;
6026       break;
6027    }
6028    nir_foreach_if_use_safe(use_src, &instr->dest.ssa) {
6029       return_previous = true;
6030       break;
6031    }
6032
6033    aco_opcode op;
6034    if (data.size() == 1) {
6035       assert(instr->dest.ssa.bit_size == 32);
6036       op = return_previous ? op32_rtn : op32;
6037    } else {
6038       assert(instr->dest.ssa.bit_size == 64);
6039       op = return_previous ? op64_rtn : op64;
6040    }
6041
6042    if (offset > 65535) {
6043       Builder bld(ctx->program, ctx->block);
6044       address = bld.vadd32(bld.def(v1), Operand(offset), address);
6045       offset = 0;
6046    }
6047
6048    aco_ptr<DS_instruction> ds;
6049    ds.reset(create_instruction<DS_instruction>(op, Format::DS, num_operands, return_previous ? 1 : 0));
6050    ds->operands[0] = Operand(address);
6051    ds->operands[1] = Operand(data);
6052    if (num_operands == 4)
6053       ds->operands[2] = Operand(get_ssa_temp(ctx, instr->src[2].ssa));
6054    ds->operands[num_operands - 1] = m;
6055    ds->offset0 = offset;
6056    if (return_previous)
6057       ds->definitions[0] = Definition(get_ssa_temp(ctx, &instr->dest.ssa));
6058    ctx->block->instructions.emplace_back(std::move(ds));
6059 }
6060
6061 Temp get_scratch_resource(isel_context *ctx)
6062 {
6063    Builder bld(ctx->program, ctx->block);
6064    Temp scratch_addr = ctx->program->private_segment_buffer;
6065    if (ctx->stage != compute_cs)
6066       scratch_addr = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), scratch_addr, Operand(0u));
6067
6068    uint32_t rsrc_conf = S_008F0C_ADD_TID_ENABLE(1) |
6069                         S_008F0C_INDEX_STRIDE(ctx->program->wave_size == 64 ? 3 : 2);;
6070
6071    if (ctx->program->chip_class >= GFX10) {
6072       rsrc_conf |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
6073                    S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
6074                    S_008F0C_RESOURCE_LEVEL(1);
6075    } else if (ctx->program->chip_class <= GFX7) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6076       rsrc_conf |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6077                    S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6078    }
6079
6080    /* older generations need element size = 16 bytes. element size removed in GFX9 */
6081    if (ctx->program->chip_class <= GFX8)
6082       rsrc_conf |= S_008F0C_ELEMENT_SIZE(3);
6083
6084    return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), scratch_addr, Operand(-1u), Operand(rsrc_conf));
6085 }
6086
6087 void visit_load_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6088    assert(instr->dest.ssa.bit_size == 32 || instr->dest.ssa.bit_size == 64);
6089    Builder bld(ctx->program, ctx->block);
6090    Temp rsrc = get_scratch_resource(ctx);
6091    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6092    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6093
6094    aco_opcode op;
6095    switch (dst.size()) {
6096       case 1:
6097          op = aco_opcode::buffer_load_dword;
6098          break;
6099       case 2:
6100          op = aco_opcode::buffer_load_dwordx2;
6101          break;
6102       case 3:
6103          op = aco_opcode::buffer_load_dwordx3;
6104          break;
6105       case 4:
6106          op = aco_opcode::buffer_load_dwordx4;
6107          break;
6108       case 6:
6109       case 8: {
6110          std::array<Temp,NIR_MAX_VEC_COMPONENTS> elems;
6111          Temp lower = bld.mubuf(aco_opcode::buffer_load_dwordx4,
6112                                 bld.def(v4), rsrc, offset,
6113                                 ctx->program->scratch_offset, 0, true);
6114          Temp upper = bld.mubuf(dst.size() == 6 ? aco_opcode::buffer_load_dwordx2 :
6115                                                   aco_opcode::buffer_load_dwordx4,
6116                                 dst.size() == 6 ? bld.def(v2) : bld.def(v4),
6117                                 rsrc, offset, ctx->program->scratch_offset, 16, true);
6118          emit_split_vector(ctx, lower, 2);
6119          elems[0] = emit_extract_vector(ctx, lower, 0, v2);
6120          elems[1] = emit_extract_vector(ctx, lower, 1, v2);
6121          if (dst.size() == 8) {
6122             emit_split_vector(ctx, upper, 2);
6123             elems[2] = emit_extract_vector(ctx, upper, 0, v2);
6124             elems[3] = emit_extract_vector(ctx, upper, 1, v2);
6125          } else {
6126             elems[2] = upper;
6127          }
6128
6129          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
6130                                                                          Format::PSEUDO, dst.size() / 2, 1)};
6131          for (unsigned i = 0; i < dst.size() / 2; i++)
6132             vec->operands[i] = Operand(elems[i]);
6133          vec->definitions[0] = Definition(dst);
6134          bld.insert(std::move(vec));
6135          ctx->allocated_vec.emplace(dst.id(), elems);
6136          return;
6137       }
6138       default:
6139          unreachable("Wrong dst size for nir_intrinsic_load_scratch");
6140    }
6141
6142    bld.mubuf(op, Definition(dst), rsrc, offset, ctx->program->scratch_offset, 0, true);
6143    emit_split_vector(ctx, dst, instr->num_components);
6144 }
6145
6146 void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
6147    assert(instr->src[0].ssa->bit_size == 32 || instr->src[0].ssa->bit_size == 64);
6148    Builder bld(ctx->program, ctx->block);
6149    Temp rsrc = get_scratch_resource(ctx);
6150    Temp data = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6151    Temp offset = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[1].ssa));
6152
6153    unsigned elem_size_bytes = instr->src[0].ssa->bit_size / 8;
6154    unsigned writemask = nir_intrinsic_write_mask(instr);
6155
6156    while (writemask) {
6157       int start, count;
6158       u_bit_scan_consecutive_range(&writemask, &start, &count);
6159       int num_bytes = count * elem_size_bytes;
6160
6161       if (num_bytes > 16) {
6162          assert(elem_size_bytes == 8);
6163          writemask |= (((count - 2) << 1) - 1) << (start + 2);
6164          count = 2;
6165          num_bytes = 16;
6166       }
6167
6168       // TODO: check alignment of sub-dword stores
6169       // TODO: split 3 bytes. there is no store instruction for that
6170
6171       Temp write_data;
6172       if (count != instr->num_components) {
6173          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
6174          for (int i = 0; i < count; i++) {
6175             Temp elem = emit_extract_vector(ctx, data, start + i, RegClass(RegType::vgpr, elem_size_bytes / 4));
6176             vec->operands[i] = Operand(elem);
6177          }
6178          write_data = bld.tmp(RegClass(RegType::vgpr, count * elem_size_bytes / 4));
6179          vec->definitions[0] = Definition(write_data);
6180          ctx->block->instructions.emplace_back(std::move(vec));
6181       } else {
6182          write_data = data;
6183       }
6184
6185       aco_opcode op;
6186       switch (num_bytes) {
6187          case 4:
6188             op = aco_opcode::buffer_store_dword;
6189             break;
6190          case 8:
6191             op = aco_opcode::buffer_store_dwordx2;
6192             break;
6193          case 12:
6194             op = aco_opcode::buffer_store_dwordx3;
6195             break;
6196          case 16:
6197             op = aco_opcode::buffer_store_dwordx4;
6198             break;
6199          default:
6200             unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6201       }
6202
6203       bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_data, start * elem_size_bytes, true);
6204    }
6205 }
6206
6207 void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
6208    uint8_t log2_ps_iter_samples;
6209    if (ctx->program->info->ps.force_persample) {
6210       log2_ps_iter_samples =
6211          util_logbase2(ctx->options->key.fs.num_samples);
6212    } else {
6213       log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
6214    }
6215
6216    /* The bit pattern matches that used by fixed function fragment
6217     * processing. */
6218    static const unsigned ps_iter_masks[] = {
6219       0xffff, /* not used */
6220       0x5555,
6221       0x1111,
6222       0x0101,
6223       0x0001,
6224    };
6225    assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
6226
6227    Builder bld(ctx->program, ctx->block);
6228
6229    Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
6230                              get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6231    Temp ps_iter_mask = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
6232    Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
6233    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6234    bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
6235 }
6236
6237 void visit_emit_vertex_with_counter(isel_context *ctx, nir_intrinsic_instr *instr) {
6238    Builder bld(ctx->program, ctx->block);
6239
6240    unsigned stream = nir_intrinsic_stream_id(instr);
6241    Temp next_vertex = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
6242    next_vertex = bld.v_mul_imm(bld.def(v1), next_vertex, 4u);
6243    nir_const_value *next_vertex_cv = nir_src_as_const_value(instr->src[0]);
6244
6245    /* get GSVS ring */
6246    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_GSVS_GS * 16u));
6247
6248    unsigned num_components =
6249       ctx->program->info->gs.num_stream_output_components[stream];
6250    assert(num_components);
6251
6252    unsigned stride = 4u * num_components * ctx->shader->info.gs.vertices_out;
6253    unsigned stream_offset = 0;
6254    for (unsigned i = 0; i < stream; i++) {
6255       unsigned prev_stride = 4u * ctx->program->info->gs.num_stream_output_components[i] * ctx->shader->info.gs.vertices_out;
6256       stream_offset += prev_stride * ctx->program->wave_size;
6257    }
6258
6259    /* Limit on the stride field for <= GFX7. */
6260    assert(stride < (1 << 14));
6261
6262    Temp gsvs_dwords[4];
6263    for (unsigned i = 0; i < 4; i++)
6264       gsvs_dwords[i] = bld.tmp(s1);
6265    bld.pseudo(aco_opcode::p_split_vector,
6266               Definition(gsvs_dwords[0]),
6267               Definition(gsvs_dwords[1]),
6268               Definition(gsvs_dwords[2]),
6269               Definition(gsvs_dwords[3]),
6270               gsvs_ring);
6271
6272    if (stream_offset) {
6273       Temp stream_offset_tmp = bld.copy(bld.def(s1), Operand(stream_offset));
6274
6275       Temp carry = bld.tmp(s1);
6276       gsvs_dwords[0] = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.scc(Definition(carry)), gsvs_dwords[0], stream_offset_tmp);
6277       gsvs_dwords[1] = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(0u), bld.scc(carry));
6278    }
6279
6280    gsvs_dwords[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), gsvs_dwords[1], Operand(S_008F04_STRIDE(stride)));
6281    gsvs_dwords[2] = bld.copy(bld.def(s1), Operand((uint32_t)ctx->program->wave_size));
6282
6283    gsvs_ring = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
6284                           gsvs_dwords[0], gsvs_dwords[1], gsvs_dwords[2], gsvs_dwords[3]);
6285
6286    unsigned offset = 0;
6287    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; i++) {
6288       if (ctx->program->info->gs.output_streams[i] != stream)
6289          continue;
6290
6291       for (unsigned j = 0; j < 4; j++) {
6292          if (!(ctx->program->info->gs.output_usage_mask[i] & (1 << j)))
6293             continue;
6294
6295          if (ctx->outputs.mask[i] & (1 << j)) {
6296             Operand vaddr_offset = next_vertex_cv ? Operand(v1) : Operand(next_vertex);
6297             unsigned const_offset = (offset + (next_vertex_cv ? next_vertex_cv->u32 : 0u)) * 4u;
6298             if (const_offset >= 4096u) {
6299                if (vaddr_offset.isUndefined())
6300                   vaddr_offset = bld.copy(bld.def(v1), Operand(const_offset / 4096u * 4096u));
6301                else
6302                   vaddr_offset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), vaddr_offset);
6303                const_offset %= 4096u;
6304             }
6305
6306             aco_ptr<MTBUF_instruction> mtbuf{create_instruction<MTBUF_instruction>(aco_opcode::tbuffer_store_format_x, Format::MTBUF, 4, 0)};
6307             mtbuf->operands[0] = Operand(gsvs_ring);
6308             mtbuf->operands[1] = vaddr_offset;
6309             mtbuf->operands[2] = Operand(get_arg(ctx, ctx->args->gs2vs_offset));
6310             mtbuf->operands[3] = Operand(ctx->outputs.outputs[i][j]);
6311             mtbuf->offen = !vaddr_offset.isUndefined();
6312             mtbuf->dfmt = V_008F0C_BUF_DATA_FORMAT_32;
6313             mtbuf->nfmt = V_008F0C_BUF_NUM_FORMAT_UINT;
6314             mtbuf->offset = const_offset;
6315             mtbuf->glc = true;
6316             mtbuf->slc = true;
6317             mtbuf->barrier = barrier_gs_data;
6318             mtbuf->can_reorder = true;
6319             bld.insert(std::move(mtbuf));
6320          }
6321
6322          offset += ctx->shader->info.gs.vertices_out;
6323       }
6324
6325       /* outputs for the next vertex are undefined and keeping them around can
6326        * create invalid IR with control flow */
6327       ctx->outputs.mask[i] = 0;
6328    }
6329
6330    bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(false, true, stream));
6331 }
6332
6333 Temp emit_boolean_reduce(isel_context *ctx, nir_op op, unsigned cluster_size, Temp src)
6334 {
6335    Builder bld(ctx->program, ctx->block);
6336
6337    if (cluster_size == 1) {
6338       return src;
6339    } if (op == nir_op_iand && cluster_size == 4) {
6340       //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6341       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6342       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc),
6343                       bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc), tmp));
6344    } else if (op == nir_op_ior && cluster_size == 4) {
6345       //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6346       return bld.sop1(Builder::s_wqm, bld.def(bld.lm), bld.def(s1, scc),
6347                       bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)));
6348    } else if (op == nir_op_iand && cluster_size == ctx->program->wave_size) {
6349       //subgroupAnd(val) -> (exec & ~val) == 0
6350       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
6351       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
6352       return bld.sop1(Builder::s_not, bld.def(bld.lm), bld.def(s1, scc), cond);
6353    } else if (op == nir_op_ior && cluster_size == ctx->program->wave_size) {
6354       //subgroupOr(val) -> (val & exec) != 0
6355       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm)).def(1).getTemp();
6356       return bool_to_vector_condition(ctx, tmp);
6357    } else if (op == nir_op_ixor && cluster_size == ctx->program->wave_size) {
6358       //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6359       Temp tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6360       tmp = bld.sop1(Builder::s_bcnt1_i32, bld.def(s1), bld.def(s1, scc), tmp);
6361       tmp = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), tmp, Operand(1u)).def(1).getTemp();
6362       return bool_to_vector_condition(ctx, tmp);
6363    } else {
6364       //subgroupClustered{And,Or,Xor}(val, n) ->
6365       //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ;  just v_mbcnt_lo_u32_b32 on wave32
6366       //cluster_offset = ~(n - 1) & lane_id
6367       //cluster_mask = ((1 << n) - 1)
6368       //subgroupClusteredAnd():
6369       //   return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6370       //subgroupClusteredOr():
6371       //   return ((val & exec) >> cluster_offset) & cluster_mask != 0
6372       //subgroupClusteredXor():
6373       //   return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6374       Temp lane_id = emit_mbcnt(ctx, bld.def(v1));
6375       Temp cluster_offset = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(~uint32_t(cluster_size - 1)), lane_id);
6376
6377       Temp tmp;
6378       if (op == nir_op_iand)
6379          tmp = bld.sop2(Builder::s_orn2, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6380       else
6381          tmp = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
6382
6383       uint32_t cluster_mask = cluster_size == 32 ? -1 : (1u << cluster_size) - 1u;
6384
6385       if (ctx->program->chip_class <= GFX7)
6386          tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), tmp, cluster_offset);
6387       else if (ctx->program->wave_size == 64)
6388          tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), cluster_offset, tmp);
6389       else
6390          tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), cluster_offset, tmp);
6391       tmp = emit_extract_vector(ctx, tmp, 0, v1);
6392       if (cluster_mask != 0xffffffff)
6393          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(cluster_mask), tmp);
6394
6395       Definition cmp_def = Definition();
6396       if (op == nir_op_iand) {
6397          cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(cluster_mask), tmp).def(0);
6398       } else if (op == nir_op_ior) {
6399          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6400       } else if (op == nir_op_ixor) {
6401          tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u),
6402                         bld.vop3(aco_opcode::v_bcnt_u32_b32, bld.def(v1), tmp, Operand(0u)));
6403          cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp).def(0);
6404       }
6405       cmp_def.setHint(vcc);
6406       return cmp_def.getTemp();
6407    }
6408 }
6409
6410 Temp emit_boolean_exclusive_scan(isel_context *ctx, nir_op op, Temp src)
6411 {
6412    Builder bld(ctx->program, ctx->block);
6413
6414    //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6415    //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6416    //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6417    Temp tmp;
6418    if (op == nir_op_iand)
6419       tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src);
6420    else
6421       tmp = bld.sop2(Builder::s_and, bld.def(s2), bld.def(s1, scc), src, Operand(exec, bld.lm));
6422
6423    Builder::Result lohi = bld.pseudo(aco_opcode::p_split_vector, bld.def(s1), bld.def(s1), tmp);
6424    Temp lo = lohi.def(0).getTemp();
6425    Temp hi = lohi.def(1).getTemp();
6426    Temp mbcnt = emit_mbcnt(ctx, bld.def(v1), Operand(lo), Operand(hi));
6427
6428    Definition cmp_def = Definition();
6429    if (op == nir_op_iand)
6430       cmp_def = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6431    else if (op == nir_op_ior)
6432       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), mbcnt).def(0);
6433    else if (op == nir_op_ixor)
6434       cmp_def = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u),
6435                          bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), mbcnt)).def(0);
6436    cmp_def.setHint(vcc);
6437    return cmp_def.getTemp();
6438 }
6439
6440 Temp emit_boolean_inclusive_scan(isel_context *ctx, nir_op op, Temp src)
6441 {
6442    Builder bld(ctx->program, ctx->block);
6443
6444    //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
6445    //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
6446    //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
6447    Temp tmp = emit_boolean_exclusive_scan(ctx, op, src);
6448    if (op == nir_op_iand)
6449       return bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6450    else if (op == nir_op_ior)
6451       return bld.sop2(Builder::s_or, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6452    else if (op == nir_op_ixor)
6453       return bld.sop2(Builder::s_xor, bld.def(bld.lm), bld.def(s1, scc), tmp, src);
6454
6455    assert(false);
6456    return Temp();
6457 }
6458
6459 void emit_uniform_subgroup(isel_context *ctx, nir_intrinsic_instr *instr, Temp src)
6460 {
6461    Builder bld(ctx->program, ctx->block);
6462    Definition dst(get_ssa_temp(ctx, &instr->dest.ssa));
6463    if (src.regClass().type() == RegType::vgpr) {
6464       bld.pseudo(aco_opcode::p_as_uniform, dst, src);
6465    } else if (src.regClass() == s1) {
6466       bld.sop1(aco_opcode::s_mov_b32, dst, src);
6467    } else if (src.regClass() == s2) {
6468       bld.sop1(aco_opcode::s_mov_b64, dst, src);
6469    } else {
6470       fprintf(stderr, "Unimplemented NIR instr bit size: ");
6471       nir_print_instr(&instr->instr, stderr);
6472       fprintf(stderr, "\n");
6473    }
6474 }
6475
6476 void emit_interp_center(isel_context *ctx, Temp dst, Temp pos1, Temp pos2)
6477 {
6478    Builder bld(ctx->program, ctx->block);
6479    Temp persp_center = get_arg(ctx, ctx->args->ac.persp_center);
6480    Temp p1 = emit_extract_vector(ctx, persp_center, 0, v1);
6481    Temp p2 = emit_extract_vector(ctx, persp_center, 1, v1);
6482
6483    Temp ddx_1, ddx_2, ddy_1, ddy_2;
6484    uint32_t dpp_ctrl0 = dpp_quad_perm(0, 0, 0, 0);
6485    uint32_t dpp_ctrl1 = dpp_quad_perm(1, 1, 1, 1);
6486    uint32_t dpp_ctrl2 = dpp_quad_perm(2, 2, 2, 2);
6487
6488    /* Build DD X/Y */
6489    if (ctx->program->chip_class >= GFX8) {
6490       Temp tl_1 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p1, dpp_ctrl0);
6491       ddx_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl1);
6492       ddy_1 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p1, tl_1, dpp_ctrl2);
6493       Temp tl_2 = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), p2, dpp_ctrl0);
6494       ddx_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl1);
6495       ddy_2 = bld.vop2_dpp(aco_opcode::v_sub_f32, bld.def(v1), p2, tl_2, dpp_ctrl2);
6496    } else {
6497       Temp tl_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl0);
6498       ddx_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl1);
6499       ddx_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_1, tl_1);
6500       ddx_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p1, (1 << 15) | dpp_ctrl2);
6501       ddx_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddx_2, tl_1);
6502       Temp tl_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl0);
6503       ddy_1 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl1);
6504       ddy_1 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_1, tl_2);
6505       ddy_2 = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), p2, (1 << 15) | dpp_ctrl2);
6506       ddy_2 = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), ddy_2, tl_2);
6507    }
6508
6509    /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
6510    Temp tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_1, pos1, p1);
6511    Temp tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddx_2, pos1, p2);
6512    tmp1 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_1, pos2, tmp1);
6513    tmp2 = bld.vop3(aco_opcode::v_mad_f32, bld.def(v1), ddy_2, pos2, tmp2);
6514    Temp wqm1 = bld.tmp(v1);
6515    emit_wqm(ctx, tmp1, wqm1, true);
6516    Temp wqm2 = bld.tmp(v1);
6517    emit_wqm(ctx, tmp2, wqm2, true);
6518    bld.pseudo(aco_opcode::p_create_vector, Definition(dst), wqm1, wqm2);
6519    return;
6520 }
6521
6522 void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr)
6523 {
6524    Builder bld(ctx->program, ctx->block);
6525    switch(instr->intrinsic) {
6526    case nir_intrinsic_load_barycentric_sample:
6527    case nir_intrinsic_load_barycentric_pixel:
6528    case nir_intrinsic_load_barycentric_centroid: {
6529       glsl_interp_mode mode = (glsl_interp_mode)nir_intrinsic_interp_mode(instr);
6530       Temp bary = Temp(0, s2);
6531       switch (mode) {
6532       case INTERP_MODE_SMOOTH:
6533       case INTERP_MODE_NONE:
6534          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6535             bary = get_arg(ctx, ctx->args->ac.persp_center);
6536          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6537             bary = ctx->persp_centroid;
6538          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6539             bary = get_arg(ctx, ctx->args->ac.persp_sample);
6540          break;
6541       case INTERP_MODE_NOPERSPECTIVE:
6542          if (instr->intrinsic == nir_intrinsic_load_barycentric_pixel)
6543             bary = get_arg(ctx, ctx->args->ac.linear_center);
6544          else if (instr->intrinsic == nir_intrinsic_load_barycentric_centroid)
6545             bary = ctx->linear_centroid;
6546          else if (instr->intrinsic == nir_intrinsic_load_barycentric_sample)
6547             bary = get_arg(ctx, ctx->args->ac.linear_sample);
6548          break;
6549       default:
6550          break;
6551       }
6552       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6553       Temp p1 = emit_extract_vector(ctx, bary, 0, v1);
6554       Temp p2 = emit_extract_vector(ctx, bary, 1, v1);
6555       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6556                  Operand(p1), Operand(p2));
6557       emit_split_vector(ctx, dst, 2);
6558       break;
6559    }
6560    case nir_intrinsic_load_barycentric_model: {
6561       Temp model = get_arg(ctx, ctx->args->ac.pull_model);
6562
6563       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6564       Temp p1 = emit_extract_vector(ctx, model, 0, v1);
6565       Temp p2 = emit_extract_vector(ctx, model, 1, v1);
6566       Temp p3 = emit_extract_vector(ctx, model, 2, v1);
6567       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6568                  Operand(p1), Operand(p2), Operand(p3));
6569       emit_split_vector(ctx, dst, 3);
6570       break;
6571    }
6572    case nir_intrinsic_load_barycentric_at_sample: {
6573       uint32_t sample_pos_offset = RING_PS_SAMPLE_POSITIONS * 16;
6574       switch (ctx->options->key.fs.num_samples) {
6575          case 2: sample_pos_offset += 1 << 3; break;
6576          case 4: sample_pos_offset += 3 << 3; break;
6577          case 8: sample_pos_offset += 7 << 3; break;
6578          default: break;
6579       }
6580       Temp sample_pos;
6581       Temp addr = get_ssa_temp(ctx, instr->src[0].ssa);
6582       nir_const_value* const_addr = nir_src_as_const_value(instr->src[0]);
6583       Temp private_segment_buffer = ctx->program->private_segment_buffer;
6584       if (addr.type() == RegType::sgpr) {
6585          Operand offset;
6586          if (const_addr) {
6587             sample_pos_offset += const_addr->u32 << 3;
6588             offset = Operand(sample_pos_offset);
6589          } else if (ctx->options->chip_class >= GFX9) {
6590             offset = bld.sop2(aco_opcode::s_lshl3_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6591          } else {
6592             offset = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), addr, Operand(3u));
6593             offset = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), bld.def(s1, scc), addr, Operand(sample_pos_offset));
6594          }
6595
6596          Operand off = bld.copy(bld.def(s1), Operand(offset));
6597          sample_pos = bld.smem(aco_opcode::s_load_dwordx2, bld.def(s2), private_segment_buffer, off);
6598
6599       } else if (ctx->options->chip_class >= GFX9) {
6600          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6601          sample_pos = bld.global(aco_opcode::global_load_dwordx2, bld.def(v2), addr, private_segment_buffer, sample_pos_offset);
6602       } else if (ctx->options->chip_class >= GFX7) {
6603          /* addr += private_segment_buffer + sample_pos_offset */
6604          Temp tmp0 = bld.tmp(s1);
6605          Temp tmp1 = bld.tmp(s1);
6606          bld.pseudo(aco_opcode::p_split_vector, Definition(tmp0), Definition(tmp1), private_segment_buffer);
6607          Definition scc_tmp = bld.def(s1, scc);
6608          tmp0 = bld.sop2(aco_opcode::s_add_u32, bld.def(s1), scc_tmp, tmp0, Operand(sample_pos_offset));
6609          tmp1 = bld.sop2(aco_opcode::s_addc_u32, bld.def(s1), bld.def(s1, scc), tmp1, Operand(0u), bld.scc(scc_tmp.getTemp()));
6610          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6611          Temp pck0 = bld.tmp(v1);
6612          Temp carry = bld.vadd32(Definition(pck0), tmp0, addr, true).def(1).getTemp();
6613          tmp1 = as_vgpr(ctx, tmp1);
6614          Temp pck1 = bld.vop2_e64(aco_opcode::v_addc_co_u32, bld.def(v1), bld.hint_vcc(bld.def(bld.lm)), tmp1, Operand(0u), carry);
6615          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), pck0, pck1);
6616
6617          /* sample_pos = flat_load_dwordx2 addr */
6618          sample_pos = bld.flat(aco_opcode::flat_load_dwordx2, bld.def(v2), addr, Operand(s1));
6619       } else {
6620          assert(ctx->options->chip_class == GFX6);
6621
6622          uint32_t rsrc_conf = S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
6623                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
6624          Temp rsrc = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), private_segment_buffer, Operand(0u), Operand(rsrc_conf));
6625
6626          addr = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(3u), addr);
6627          addr = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), addr, Operand(0u));
6628
6629          sample_pos = bld.tmp(v2);
6630
6631          aco_ptr<MUBUF_instruction> load{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dwordx2, Format::MUBUF, 3, 1)};
6632          load->definitions[0] = Definition(sample_pos);
6633          load->operands[0] = Operand(rsrc);
6634          load->operands[1] = Operand(addr);
6635          load->operands[2] = Operand(0u);
6636          load->offset = sample_pos_offset;
6637          load->offen = 0;
6638          load->addr64 = true;
6639          load->glc = false;
6640          load->dlc = false;
6641          load->disable_wqm = false;
6642          load->barrier = barrier_none;
6643          load->can_reorder = true;
6644          ctx->block->instructions.emplace_back(std::move(load));
6645       }
6646
6647       /* sample_pos -= 0.5 */
6648       Temp pos1 = bld.tmp(RegClass(sample_pos.type(), 1));
6649       Temp pos2 = bld.tmp(RegClass(sample_pos.type(), 1));
6650       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), sample_pos);
6651       pos1 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos1, Operand(0x3f000000u));
6652       pos2 = bld.vop2_e64(aco_opcode::v_sub_f32, bld.def(v1), pos2, Operand(0x3f000000u));
6653
6654       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6655       break;
6656    }
6657    case nir_intrinsic_load_barycentric_at_offset: {
6658       Temp offset = get_ssa_temp(ctx, instr->src[0].ssa);
6659       RegClass rc = RegClass(offset.type(), 1);
6660       Temp pos1 = bld.tmp(rc), pos2 = bld.tmp(rc);
6661       bld.pseudo(aco_opcode::p_split_vector, Definition(pos1), Definition(pos2), offset);
6662       emit_interp_center(ctx, get_ssa_temp(ctx, &instr->dest.ssa), pos1, pos2);
6663       break;
6664    }
6665    case nir_intrinsic_load_front_face: {
6666       bld.vopc(aco_opcode::v_cmp_lg_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6667                Operand(0u), get_arg(ctx, ctx->args->ac.front_face)).def(0).setHint(vcc);
6668       break;
6669    }
6670    case nir_intrinsic_load_view_index: {
6671       if (ctx->stage & (sw_vs | sw_gs | sw_tcs | sw_tes)) {
6672          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6673          bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
6674          break;
6675       }
6676
6677       /* fallthrough */
6678    }
6679    case nir_intrinsic_load_layer_id: {
6680       unsigned idx = nir_intrinsic_base(instr);
6681       bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6682                  Operand(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
6683       break;
6684    }
6685    case nir_intrinsic_load_frag_coord: {
6686       emit_load_frag_coord(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 4);
6687       break;
6688    }
6689    case nir_intrinsic_load_sample_pos: {
6690       Temp posx = get_arg(ctx, ctx->args->ac.frag_pos[0]);
6691       Temp posy = get_arg(ctx, ctx->args->ac.frag_pos[1]);
6692       bld.pseudo(aco_opcode::p_create_vector, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6693                  posx.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posx) : Operand(0u),
6694                  posy.id() ? bld.vop1(aco_opcode::v_fract_f32, bld.def(v1), posy) : Operand(0u));
6695       break;
6696    }
6697    case nir_intrinsic_load_tess_coord:
6698       visit_load_tess_coord(ctx, instr);
6699       break;
6700    case nir_intrinsic_load_interpolated_input:
6701       visit_load_interpolated_input(ctx, instr);
6702       break;
6703    case nir_intrinsic_store_output:
6704       visit_store_output(ctx, instr);
6705       break;
6706    case nir_intrinsic_load_input:
6707    case nir_intrinsic_load_input_vertex:
6708       visit_load_input(ctx, instr);
6709       break;
6710    case nir_intrinsic_load_output:
6711       visit_load_output(ctx, instr);
6712       break;
6713    case nir_intrinsic_load_per_vertex_input:
6714       visit_load_per_vertex_input(ctx, instr);
6715       break;
6716    case nir_intrinsic_load_per_vertex_output:
6717       visit_load_per_vertex_output(ctx, instr);
6718       break;
6719    case nir_intrinsic_store_per_vertex_output:
6720       visit_store_per_vertex_output(ctx, instr);
6721       break;
6722    case nir_intrinsic_load_ubo:
6723       visit_load_ubo(ctx, instr);
6724       break;
6725    case nir_intrinsic_load_push_constant:
6726       visit_load_push_constant(ctx, instr);
6727       break;
6728    case nir_intrinsic_load_constant:
6729       visit_load_constant(ctx, instr);
6730       break;
6731    case nir_intrinsic_vulkan_resource_index:
6732       visit_load_resource(ctx, instr);
6733       break;
6734    case nir_intrinsic_discard:
6735       visit_discard(ctx, instr);
6736       break;
6737    case nir_intrinsic_discard_if:
6738       visit_discard_if(ctx, instr);
6739       break;
6740    case nir_intrinsic_load_shared:
6741       visit_load_shared(ctx, instr);
6742       break;
6743    case nir_intrinsic_store_shared:
6744       visit_store_shared(ctx, instr);
6745       break;
6746    case nir_intrinsic_shared_atomic_add:
6747    case nir_intrinsic_shared_atomic_imin:
6748    case nir_intrinsic_shared_atomic_umin:
6749    case nir_intrinsic_shared_atomic_imax:
6750    case nir_intrinsic_shared_atomic_umax:
6751    case nir_intrinsic_shared_atomic_and:
6752    case nir_intrinsic_shared_atomic_or:
6753    case nir_intrinsic_shared_atomic_xor:
6754    case nir_intrinsic_shared_atomic_exchange:
6755    case nir_intrinsic_shared_atomic_comp_swap:
6756       visit_shared_atomic(ctx, instr);
6757       break;
6758    case nir_intrinsic_image_deref_load:
6759       visit_image_load(ctx, instr);
6760       break;
6761    case nir_intrinsic_image_deref_store:
6762       visit_image_store(ctx, instr);
6763       break;
6764    case nir_intrinsic_image_deref_atomic_add:
6765    case nir_intrinsic_image_deref_atomic_umin:
6766    case nir_intrinsic_image_deref_atomic_imin:
6767    case nir_intrinsic_image_deref_atomic_umax:
6768    case nir_intrinsic_image_deref_atomic_imax:
6769    case nir_intrinsic_image_deref_atomic_and:
6770    case nir_intrinsic_image_deref_atomic_or:
6771    case nir_intrinsic_image_deref_atomic_xor:
6772    case nir_intrinsic_image_deref_atomic_exchange:
6773    case nir_intrinsic_image_deref_atomic_comp_swap:
6774       visit_image_atomic(ctx, instr);
6775       break;
6776    case nir_intrinsic_image_deref_size:
6777       visit_image_size(ctx, instr);
6778       break;
6779    case nir_intrinsic_load_ssbo:
6780       visit_load_ssbo(ctx, instr);
6781       break;
6782    case nir_intrinsic_store_ssbo:
6783       visit_store_ssbo(ctx, instr);
6784       break;
6785    case nir_intrinsic_load_global:
6786       visit_load_global(ctx, instr);
6787       break;
6788    case nir_intrinsic_store_global:
6789       visit_store_global(ctx, instr);
6790       break;
6791    case nir_intrinsic_global_atomic_add:
6792    case nir_intrinsic_global_atomic_imin:
6793    case nir_intrinsic_global_atomic_umin:
6794    case nir_intrinsic_global_atomic_imax:
6795    case nir_intrinsic_global_atomic_umax:
6796    case nir_intrinsic_global_atomic_and:
6797    case nir_intrinsic_global_atomic_or:
6798    case nir_intrinsic_global_atomic_xor:
6799    case nir_intrinsic_global_atomic_exchange:
6800    case nir_intrinsic_global_atomic_comp_swap:
6801       visit_global_atomic(ctx, instr);
6802       break;
6803    case nir_intrinsic_ssbo_atomic_add:
6804    case nir_intrinsic_ssbo_atomic_imin:
6805    case nir_intrinsic_ssbo_atomic_umin:
6806    case nir_intrinsic_ssbo_atomic_imax:
6807    case nir_intrinsic_ssbo_atomic_umax:
6808    case nir_intrinsic_ssbo_atomic_and:
6809    case nir_intrinsic_ssbo_atomic_or:
6810    case nir_intrinsic_ssbo_atomic_xor:
6811    case nir_intrinsic_ssbo_atomic_exchange:
6812    case nir_intrinsic_ssbo_atomic_comp_swap:
6813       visit_atomic_ssbo(ctx, instr);
6814       break;
6815    case nir_intrinsic_load_scratch:
6816       visit_load_scratch(ctx, instr);
6817       break;
6818    case nir_intrinsic_store_scratch:
6819       visit_store_scratch(ctx, instr);
6820       break;
6821    case nir_intrinsic_get_buffer_size:
6822       visit_get_buffer_size(ctx, instr);
6823       break;
6824    case nir_intrinsic_control_barrier: {
6825       if (ctx->program->chip_class == GFX6 && ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6826          /* GFX6 only (thanks to a hw bug workaround):
6827           * The real barrier instruction isn’t needed, because an entire patch
6828           * always fits into a single wave.
6829           */
6830          break;
6831       }
6832
6833       if (ctx->shader->info.stage == MESA_SHADER_COMPUTE) {
6834          unsigned* bsize = ctx->program->info->cs.block_size;
6835          unsigned workgroup_size = bsize[0] * bsize[1] * bsize[2];
6836          if (workgroup_size > ctx->program->wave_size)
6837             bld.sopp(aco_opcode::s_barrier);
6838       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
6839          /* For each patch provided during rendering, n TCS shader invocations will be processed,
6840           * where n is the number of vertices in the output patch.
6841           */
6842          unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
6843          if (workgroup_size > ctx->program->wave_size)
6844             bld.sopp(aco_opcode::s_barrier);
6845       } else {
6846          /* We don't know the workgroup size, so always emit the s_barrier. */
6847          bld.sopp(aco_opcode::s_barrier);
6848       }
6849
6850       break;
6851    }
6852    case nir_intrinsic_memory_barrier_tcs_patch:
6853    case nir_intrinsic_group_memory_barrier:
6854    case nir_intrinsic_memory_barrier:
6855    case nir_intrinsic_memory_barrier_buffer:
6856    case nir_intrinsic_memory_barrier_image:
6857    case nir_intrinsic_memory_barrier_shared:
6858       emit_memory_barrier(ctx, instr);
6859       break;
6860    case nir_intrinsic_load_num_work_groups: {
6861       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6862       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.num_work_groups)));
6863       emit_split_vector(ctx, dst, 3);
6864       break;
6865    }
6866    case nir_intrinsic_load_local_invocation_id: {
6867       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6868       bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.local_invocation_ids)));
6869       emit_split_vector(ctx, dst, 3);
6870       break;
6871    }
6872    case nir_intrinsic_load_work_group_id: {
6873       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6874       struct ac_arg *args = ctx->args->ac.workgroup_ids;
6875       bld.pseudo(aco_opcode::p_create_vector, Definition(dst),
6876                  args[0].used ? Operand(get_arg(ctx, args[0])) : Operand(0u),
6877                  args[1].used ? Operand(get_arg(ctx, args[1])) : Operand(0u),
6878                  args[2].used ? Operand(get_arg(ctx, args[2])) : Operand(0u));
6879       emit_split_vector(ctx, dst, 3);
6880       break;
6881    }
6882    case nir_intrinsic_load_local_invocation_index: {
6883       Temp id = emit_mbcnt(ctx, bld.def(v1));
6884
6885       /* The tg_size bits [6:11] contain the subgroup id,
6886        * we need this multiplied by the wave size, and then OR the thread id to it.
6887        */
6888       if (ctx->program->wave_size == 64) {
6889          /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
6890          Temp tg_num = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), Operand(0xfc0u),
6891                                 get_arg(ctx, ctx->args->ac.tg_size));
6892          bld.vop2(aco_opcode::v_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, id);
6893       } else {
6894          /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR  */
6895          Temp tg_num = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
6896                                 get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6897          bld.vop3(aco_opcode::v_lshl_or_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), tg_num, Operand(0x5u), id);
6898       }
6899       break;
6900    }
6901    case nir_intrinsic_load_subgroup_id: {
6902       if (ctx->stage == compute_cs) {
6903          bld.sop2(aco_opcode::s_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc),
6904                   get_arg(ctx, ctx->args->ac.tg_size), Operand(0x6u | (0x6u << 16)));
6905       } else {
6906          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x0u));
6907       }
6908       break;
6909    }
6910    case nir_intrinsic_load_subgroup_invocation: {
6911       emit_mbcnt(ctx, Definition(get_ssa_temp(ctx, &instr->dest.ssa)));
6912       break;
6913    }
6914    case nir_intrinsic_load_num_subgroups: {
6915       if (ctx->stage == compute_cs)
6916          bld.sop2(aco_opcode::s_and_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), bld.def(s1, scc), Operand(0x3fu),
6917                   get_arg(ctx, ctx->args->ac.tg_size));
6918       else
6919          bld.sop1(aco_opcode::s_mov_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), Operand(0x1u));
6920       break;
6921    }
6922    case nir_intrinsic_ballot: {
6923       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6924       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6925       Definition tmp = bld.def(dst.regClass());
6926       Definition lanemask_tmp = dst.size() == bld.lm.size() ? tmp : bld.def(src.regClass());
6927       if (instr->src[0].ssa->bit_size == 1) {
6928          assert(src.regClass() == bld.lm);
6929          bld.sop2(Builder::s_and, lanemask_tmp, bld.def(s1, scc), Operand(exec, bld.lm), src);
6930       } else if (instr->src[0].ssa->bit_size == 32 && src.regClass() == v1) {
6931          bld.vopc(aco_opcode::v_cmp_lg_u32, lanemask_tmp, Operand(0u), src);
6932       } else if (instr->src[0].ssa->bit_size == 64 && src.regClass() == v2) {
6933          bld.vopc(aco_opcode::v_cmp_lg_u64, lanemask_tmp, Operand(0u), src);
6934       } else {
6935          fprintf(stderr, "Unimplemented NIR instr bit size: ");
6936          nir_print_instr(&instr->instr, stderr);
6937          fprintf(stderr, "\n");
6938       }
6939       if (dst.size() != bld.lm.size()) {
6940          /* Wave32 with ballot size set to 64 */
6941          bld.pseudo(aco_opcode::p_create_vector, Definition(tmp), lanemask_tmp.getTemp(), Operand(0u));
6942       }
6943       emit_wqm(ctx, tmp.getTemp(), dst);
6944       break;
6945    }
6946    case nir_intrinsic_shuffle:
6947    case nir_intrinsic_read_invocation: {
6948       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
6949       if (!ctx->divergent_vals[instr->src[0].ssa->index]) {
6950          emit_uniform_subgroup(ctx, instr, src);
6951       } else {
6952          Temp tid = get_ssa_temp(ctx, instr->src[1].ssa);
6953          if (instr->intrinsic == nir_intrinsic_read_invocation || !ctx->divergent_vals[instr->src[1].ssa->index])
6954             tid = bld.as_uniform(tid);
6955          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
6956          if (src.regClass() == v1) {
6957             emit_wqm(ctx, emit_bpermute(ctx, bld, tid, src), dst);
6958          } else if (src.regClass() == v2) {
6959             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
6960             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
6961             lo = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, lo));
6962             hi = emit_wqm(ctx, emit_bpermute(ctx, bld, tid, hi));
6963             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
6964             emit_split_vector(ctx, dst, 2);
6965          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == s1) {
6966             assert(src.regClass() == bld.lm);
6967             Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src, tid);
6968             bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
6969          } else if (instr->dest.ssa.bit_size == 1 && tid.regClass() == v1) {
6970             assert(src.regClass() == bld.lm);
6971             Temp tmp;
6972             if (ctx->program->chip_class <= GFX7)
6973                tmp = bld.vop3(aco_opcode::v_lshr_b64, bld.def(v2), src, tid);
6974             else if (ctx->program->wave_size == 64)
6975                tmp = bld.vop3(aco_opcode::v_lshrrev_b64, bld.def(v2), tid, src);
6976             else
6977                tmp = bld.vop2_e64(aco_opcode::v_lshrrev_b32, bld.def(v1), tid, src);
6978             tmp = emit_extract_vector(ctx, tmp, 0, v1);
6979             tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(1u), tmp);
6980             emit_wqm(ctx, bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), tmp), dst);
6981          } else {
6982             fprintf(stderr, "Unimplemented NIR instr bit size: ");
6983             nir_print_instr(&instr->instr, stderr);
6984             fprintf(stderr, "\n");
6985          }
6986       }
6987       break;
6988    }
6989    case nir_intrinsic_load_sample_id: {
6990       bld.vop3(aco_opcode::v_bfe_u32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
6991                get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
6992       break;
6993    }
6994    case nir_intrinsic_load_sample_mask_in: {
6995       visit_load_sample_mask_in(ctx, instr);
6996       break;
6997    }
6998    case nir_intrinsic_read_first_invocation: {
6999       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7000       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7001       if (src.regClass() == v1) {
7002          emit_wqm(ctx,
7003                   bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), src),
7004                   dst);
7005       } else if (src.regClass() == v2) {
7006          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7007          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7008          lo = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), lo));
7009          hi = emit_wqm(ctx, bld.vop1(aco_opcode::v_readfirstlane_b32, bld.def(s1), hi));
7010          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7011          emit_split_vector(ctx, dst, 2);
7012       } else if (instr->dest.ssa.bit_size == 1) {
7013          assert(src.regClass() == bld.lm);
7014          Temp tmp = bld.sopc(Builder::s_bitcmp1, bld.def(s1, scc), src,
7015                              bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)));
7016          bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7017       } else if (src.regClass() == s1) {
7018          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), src);
7019       } else if (src.regClass() == s2) {
7020          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), src);
7021       } else {
7022          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7023          nir_print_instr(&instr->instr, stderr);
7024          fprintf(stderr, "\n");
7025       }
7026       break;
7027    }
7028    case nir_intrinsic_vote_all: {
7029       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7030       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7031       assert(src.regClass() == bld.lm);
7032       assert(dst.regClass() == bld.lm);
7033
7034       Temp tmp = bld.sop2(Builder::s_andn2, bld.def(bld.lm), bld.def(s1, scc), Operand(exec, bld.lm), src).def(1).getTemp();
7035       Temp cond = bool_to_vector_condition(ctx, emit_wqm(ctx, tmp));
7036       bld.sop1(Builder::s_not, Definition(dst), bld.def(s1, scc), cond);
7037       break;
7038    }
7039    case nir_intrinsic_vote_any: {
7040       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7041       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7042       assert(src.regClass() == bld.lm);
7043       assert(dst.regClass() == bld.lm);
7044
7045       Temp tmp = bool_to_scalar_condition(ctx, src);
7046       bool_to_vector_condition(ctx, emit_wqm(ctx, tmp), dst);
7047       break;
7048    }
7049    case nir_intrinsic_reduce:
7050    case nir_intrinsic_inclusive_scan:
7051    case nir_intrinsic_exclusive_scan: {
7052       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7053       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7054       nir_op op = (nir_op) nir_intrinsic_reduction_op(instr);
7055       unsigned cluster_size = instr->intrinsic == nir_intrinsic_reduce ?
7056          nir_intrinsic_cluster_size(instr) : 0;
7057       cluster_size = util_next_power_of_two(MIN2(cluster_size ? cluster_size : ctx->program->wave_size, ctx->program->wave_size));
7058
7059       if (!ctx->divergent_vals[instr->src[0].ssa->index] && (op == nir_op_ior || op == nir_op_iand)) {
7060          emit_uniform_subgroup(ctx, instr, src);
7061       } else if (instr->dest.ssa.bit_size == 1) {
7062          if (op == nir_op_imul || op == nir_op_umin || op == nir_op_imin)
7063             op = nir_op_iand;
7064          else if (op == nir_op_iadd)
7065             op = nir_op_ixor;
7066          else if (op == nir_op_umax || op == nir_op_imax)
7067             op = nir_op_ior;
7068          assert(op == nir_op_iand || op == nir_op_ior || op == nir_op_ixor);
7069
7070          switch (instr->intrinsic) {
7071          case nir_intrinsic_reduce:
7072             emit_wqm(ctx, emit_boolean_reduce(ctx, op, cluster_size, src), dst);
7073             break;
7074          case nir_intrinsic_exclusive_scan:
7075             emit_wqm(ctx, emit_boolean_exclusive_scan(ctx, op, src), dst);
7076             break;
7077          case nir_intrinsic_inclusive_scan:
7078             emit_wqm(ctx, emit_boolean_inclusive_scan(ctx, op, src), dst);
7079             break;
7080          default:
7081             assert(false);
7082          }
7083       } else if (cluster_size == 1) {
7084          bld.copy(Definition(dst), src);
7085       } else {
7086          src = as_vgpr(ctx, src);
7087
7088          ReduceOp reduce_op;
7089          switch (op) {
7090          #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7091             CASE(iadd)
7092             CASE(imul)
7093             CASE(fadd)
7094             CASE(fmul)
7095             CASE(imin)
7096             CASE(umin)
7097             CASE(fmin)
7098             CASE(imax)
7099             CASE(umax)
7100             CASE(fmax)
7101             CASE(iand)
7102             CASE(ior)
7103             CASE(ixor)
7104             default:
7105                unreachable("unknown reduction op");
7106          #undef CASE
7107          }
7108
7109          aco_opcode aco_op;
7110          switch (instr->intrinsic) {
7111             case nir_intrinsic_reduce: aco_op = aco_opcode::p_reduce; break;
7112             case nir_intrinsic_inclusive_scan: aco_op = aco_opcode::p_inclusive_scan; break;
7113             case nir_intrinsic_exclusive_scan: aco_op = aco_opcode::p_exclusive_scan; break;
7114             default:
7115                unreachable("unknown reduce intrinsic");
7116          }
7117
7118          aco_ptr<Pseudo_reduction_instruction> reduce{create_instruction<Pseudo_reduction_instruction>(aco_op, Format::PSEUDO_REDUCTION, 3, 5)};
7119          reduce->operands[0] = Operand(src);
7120          // filled in by aco_reduce_assign.cpp, used internally as part of the
7121          // reduce sequence
7122          assert(dst.size() == 1 || dst.size() == 2);
7123          reduce->operands[1] = Operand(RegClass(RegType::vgpr, dst.size()).as_linear());
7124          reduce->operands[2] = Operand(v1.as_linear());
7125
7126          Temp tmp_dst = bld.tmp(dst.regClass());
7127          reduce->definitions[0] = Definition(tmp_dst);
7128          reduce->definitions[1] = bld.def(ctx->program->lane_mask); // used internally
7129          reduce->definitions[2] = Definition();
7130          reduce->definitions[3] = Definition(scc, s1);
7131          reduce->definitions[4] = Definition();
7132          reduce->reduce_op = reduce_op;
7133          reduce->cluster_size = cluster_size;
7134          ctx->block->instructions.emplace_back(std::move(reduce));
7135
7136          emit_wqm(ctx, tmp_dst, dst);
7137       }
7138       break;
7139    }
7140    case nir_intrinsic_quad_broadcast: {
7141       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7142       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7143          emit_uniform_subgroup(ctx, instr, src);
7144       } else {
7145          Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7146          unsigned lane = nir_src_as_const_value(instr->src[1])->u32;
7147          uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane);
7148
7149          if (instr->dest.ssa.bit_size == 1) {
7150             assert(src.regClass() == bld.lm);
7151             assert(dst.regClass() == bld.lm);
7152             uint32_t half_mask = 0x11111111u << lane;
7153             Temp mask_tmp = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), Operand(half_mask), Operand(half_mask));
7154             Temp tmp = bld.tmp(bld.lm);
7155             bld.sop1(Builder::s_wqm, Definition(tmp),
7156                      bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), mask_tmp,
7157                               bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm))));
7158             emit_wqm(ctx, tmp, dst);
7159          } else if (instr->dest.ssa.bit_size == 32) {
7160             if (ctx->program->chip_class >= GFX8)
7161                emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), dst);
7162             else
7163                emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), dst);
7164          } else if (instr->dest.ssa.bit_size == 64) {
7165             Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7166             bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7167             if (ctx->program->chip_class >= GFX8) {
7168                lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7169                hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7170             } else {
7171                lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, (1 << 15) | dpp_ctrl));
7172                hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, (1 << 15) | dpp_ctrl));
7173             }
7174             bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7175             emit_split_vector(ctx, dst, 2);
7176          } else {
7177             fprintf(stderr, "Unimplemented NIR instr bit size: ");
7178             nir_print_instr(&instr->instr, stderr);
7179             fprintf(stderr, "\n");
7180          }
7181       }
7182       break;
7183    }
7184    case nir_intrinsic_quad_swap_horizontal:
7185    case nir_intrinsic_quad_swap_vertical:
7186    case nir_intrinsic_quad_swap_diagonal:
7187    case nir_intrinsic_quad_swizzle_amd: {
7188       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7189       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7190          emit_uniform_subgroup(ctx, instr, src);
7191          break;
7192       }
7193       uint16_t dpp_ctrl = 0;
7194       switch (instr->intrinsic) {
7195       case nir_intrinsic_quad_swap_horizontal:
7196          dpp_ctrl = dpp_quad_perm(1, 0, 3, 2);
7197          break;
7198       case nir_intrinsic_quad_swap_vertical:
7199          dpp_ctrl = dpp_quad_perm(2, 3, 0, 1);
7200          break;
7201       case nir_intrinsic_quad_swap_diagonal:
7202          dpp_ctrl = dpp_quad_perm(3, 2, 1, 0);
7203          break;
7204       case nir_intrinsic_quad_swizzle_amd:
7205          dpp_ctrl = nir_intrinsic_swizzle_mask(instr);
7206          break;
7207       default:
7208          break;
7209       }
7210       if (ctx->program->chip_class < GFX8)
7211          dpp_ctrl |= (1 << 15);
7212
7213       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7214       if (instr->dest.ssa.bit_size == 1) {
7215          assert(src.regClass() == bld.lm);
7216          src = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0u), Operand((uint32_t)-1), src);
7217          if (ctx->program->chip_class >= GFX8)
7218             src = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7219          else
7220             src = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7221          Temp tmp = bld.vopc(aco_opcode::v_cmp_lg_u32, bld.def(bld.lm), Operand(0u), src);
7222          emit_wqm(ctx, tmp, dst);
7223       } else if (instr->dest.ssa.bit_size == 32) {
7224          Temp tmp;
7225          if (ctx->program->chip_class >= GFX8)
7226             tmp = bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl);
7227          else
7228             tmp = bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, dpp_ctrl);
7229          emit_wqm(ctx, tmp, dst);
7230       } else if (instr->dest.ssa.bit_size == 64) {
7231          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7232          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7233          if (ctx->program->chip_class >= GFX8) {
7234             lo = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), lo, dpp_ctrl));
7235             hi = emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), hi, dpp_ctrl));
7236          } else {
7237             lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, dpp_ctrl));
7238             hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, dpp_ctrl));
7239          }
7240          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7241          emit_split_vector(ctx, dst, 2);
7242       } else {
7243          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7244          nir_print_instr(&instr->instr, stderr);
7245          fprintf(stderr, "\n");
7246       }
7247       break;
7248    }
7249    case nir_intrinsic_masked_swizzle_amd: {
7250       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7251       if (!ctx->divergent_vals[instr->dest.ssa.index]) {
7252          emit_uniform_subgroup(ctx, instr, src);
7253          break;
7254       }
7255       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7256       uint32_t mask = nir_intrinsic_swizzle_mask(instr);
7257       if (dst.regClass() == v1) {
7258          emit_wqm(ctx,
7259                   bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, mask, 0, false),
7260                   dst);
7261       } else if (dst.regClass() == v2) {
7262          Temp lo = bld.tmp(v1), hi = bld.tmp(v1);
7263          bld.pseudo(aco_opcode::p_split_vector, Definition(lo), Definition(hi), src);
7264          lo = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), lo, mask, 0, false));
7265          hi = emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), hi, mask, 0, false));
7266          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7267          emit_split_vector(ctx, dst, 2);
7268       } else {
7269          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7270          nir_print_instr(&instr->instr, stderr);
7271          fprintf(stderr, "\n");
7272       }
7273       break;
7274    }
7275    case nir_intrinsic_write_invocation_amd: {
7276       Temp src = as_vgpr(ctx, get_ssa_temp(ctx, instr->src[0].ssa));
7277       Temp val = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa));
7278       Temp lane = bld.as_uniform(get_ssa_temp(ctx, instr->src[2].ssa));
7279       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7280       if (dst.regClass() == v1) {
7281          /* src2 is ignored for writelane. RA assigns the same reg for dst */
7282          emit_wqm(ctx, bld.writelane(bld.def(v1), val, lane, src), dst);
7283       } else if (dst.regClass() == v2) {
7284          Temp src_lo = bld.tmp(v1), src_hi = bld.tmp(v1);
7285          Temp val_lo = bld.tmp(s1), val_hi = bld.tmp(s1);
7286          bld.pseudo(aco_opcode::p_split_vector, Definition(src_lo), Definition(src_hi), src);
7287          bld.pseudo(aco_opcode::p_split_vector, Definition(val_lo), Definition(val_hi), val);
7288          Temp lo = emit_wqm(ctx, bld.writelane(bld.def(v1), val_lo, lane, src_hi));
7289          Temp hi = emit_wqm(ctx, bld.writelane(bld.def(v1), val_hi, lane, src_hi));
7290          bld.pseudo(aco_opcode::p_create_vector, Definition(dst), lo, hi);
7291          emit_split_vector(ctx, dst, 2);
7292       } else {
7293          fprintf(stderr, "Unimplemented NIR instr bit size: ");
7294          nir_print_instr(&instr->instr, stderr);
7295          fprintf(stderr, "\n");
7296       }
7297       break;
7298    }
7299    case nir_intrinsic_mbcnt_amd: {
7300       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7301       RegClass rc = RegClass(src.type(), 1);
7302       Temp mask_lo = bld.tmp(rc), mask_hi = bld.tmp(rc);
7303       bld.pseudo(aco_opcode::p_split_vector, Definition(mask_lo), Definition(mask_hi), src);
7304       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7305       Temp wqm_tmp = emit_mbcnt(ctx, bld.def(v1), Operand(mask_lo), Operand(mask_hi));
7306       emit_wqm(ctx, wqm_tmp, dst);
7307       break;
7308    }
7309    case nir_intrinsic_load_helper_invocation: {
7310       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7311       bld.pseudo(aco_opcode::p_load_helper, Definition(dst));
7312       ctx->block->kind |= block_kind_needs_lowering;
7313       ctx->program->needs_exact = true;
7314       break;
7315    }
7316    case nir_intrinsic_is_helper_invocation: {
7317       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7318       bld.pseudo(aco_opcode::p_is_helper, Definition(dst));
7319       ctx->block->kind |= block_kind_needs_lowering;
7320       ctx->program->needs_exact = true;
7321       break;
7322    }
7323    case nir_intrinsic_demote:
7324       bld.pseudo(aco_opcode::p_demote_to_helper, Operand(-1u));
7325
7326       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7327          ctx->cf_info.exec_potentially_empty_discard = true;
7328       ctx->block->kind |= block_kind_uses_demote;
7329       ctx->program->needs_exact = true;
7330       break;
7331    case nir_intrinsic_demote_if: {
7332       Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
7333       assert(src.regClass() == bld.lm);
7334       Temp cond = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), src, Operand(exec, bld.lm));
7335       bld.pseudo(aco_opcode::p_demote_to_helper, cond);
7336
7337       if (ctx->cf_info.loop_nest_depth || ctx->cf_info.parent_if.is_divergent)
7338          ctx->cf_info.exec_potentially_empty_discard = true;
7339       ctx->block->kind |= block_kind_uses_demote;
7340       ctx->program->needs_exact = true;
7341       break;
7342    }
7343    case nir_intrinsic_first_invocation: {
7344       emit_wqm(ctx, bld.sop1(Builder::s_ff1_i32, bld.def(s1), Operand(exec, bld.lm)),
7345                get_ssa_temp(ctx, &instr->dest.ssa));
7346       break;
7347    }
7348    case nir_intrinsic_shader_clock:
7349       bld.smem(aco_opcode::s_memtime, Definition(get_ssa_temp(ctx, &instr->dest.ssa)), false);
7350       emit_split_vector(ctx, get_ssa_temp(ctx, &instr->dest.ssa), 2);
7351       break;
7352    case nir_intrinsic_load_vertex_id_zero_base: {
7353       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7354       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.vertex_id));
7355       break;
7356    }
7357    case nir_intrinsic_load_first_vertex: {
7358       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7359       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.base_vertex));
7360       break;
7361    }
7362    case nir_intrinsic_load_base_instance: {
7363       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7364       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.start_instance));
7365       break;
7366    }
7367    case nir_intrinsic_load_instance_id: {
7368       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7369       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.instance_id));
7370       break;
7371    }
7372    case nir_intrinsic_load_draw_id: {
7373       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7374       bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.draw_id));
7375       break;
7376    }
7377    case nir_intrinsic_load_invocation_id: {
7378       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7379
7380       if (ctx->shader->info.stage == MESA_SHADER_GEOMETRY) {
7381          if (ctx->options->chip_class >= GFX10)
7382             bld.vop2_e64(aco_opcode::v_and_b32, Definition(dst), Operand(127u), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7383          else
7384             bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_invocation_id));
7385       } else if (ctx->shader->info.stage == MESA_SHADER_TESS_CTRL) {
7386          bld.vop3(aco_opcode::v_bfe_u32, Definition(dst),
7387                   get_arg(ctx, ctx->args->ac.tcs_rel_ids), Operand(8u), Operand(5u));
7388       } else {
7389          unreachable("Unsupported stage for load_invocation_id");
7390       }
7391
7392       break;
7393    }
7394    case nir_intrinsic_load_primitive_id: {
7395       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7396
7397       switch (ctx->shader->info.stage) {
7398       case MESA_SHADER_GEOMETRY:
7399          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.gs_prim_id));
7400          break;
7401       case MESA_SHADER_TESS_CTRL:
7402          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tcs_patch_id));
7403          break;
7404       case MESA_SHADER_TESS_EVAL:
7405          bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.tes_patch_id));
7406          break;
7407       default:
7408          unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7409       }
7410
7411       break;
7412    }
7413    case nir_intrinsic_load_patch_vertices_in: {
7414       assert(ctx->shader->info.stage == MESA_SHADER_TESS_CTRL ||
7415              ctx->shader->info.stage == MESA_SHADER_TESS_EVAL);
7416
7417       Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7418       bld.copy(Definition(dst), Operand(ctx->args->options->key.tcs.input_vertices));
7419       break;
7420    }
7421    case nir_intrinsic_emit_vertex_with_counter: {
7422       visit_emit_vertex_with_counter(ctx, instr);
7423       break;
7424    }
7425    case nir_intrinsic_end_primitive_with_counter: {
7426       unsigned stream = nir_intrinsic_stream_id(instr);
7427       bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx->gs_wave_id), -1, sendmsg_gs(true, false, stream));
7428       break;
7429    }
7430    case nir_intrinsic_set_vertex_count: {
7431       /* unused, the HW keeps track of this for us */
7432       break;
7433    }
7434    default:
7435       fprintf(stderr, "Unimplemented intrinsic instr: ");
7436       nir_print_instr(&instr->instr, stderr);
7437       fprintf(stderr, "\n");
7438       abort();
7439
7440       break;
7441    }
7442 }
7443
7444
7445 void tex_fetch_ptrs(isel_context *ctx, nir_tex_instr *instr,
7446                     Temp *res_ptr, Temp *samp_ptr, Temp *fmask_ptr,
7447                     enum glsl_base_type *stype)
7448 {
7449    nir_deref_instr *texture_deref_instr = NULL;
7450    nir_deref_instr *sampler_deref_instr = NULL;
7451    int plane = -1;
7452
7453    for (unsigned i = 0; i < instr->num_srcs; i++) {
7454       switch (instr->src[i].src_type) {
7455       case nir_tex_src_texture_deref:
7456          texture_deref_instr = nir_src_as_deref(instr->src[i].src);
7457          break;
7458       case nir_tex_src_sampler_deref:
7459          sampler_deref_instr = nir_src_as_deref(instr->src[i].src);
7460          break;
7461       case nir_tex_src_plane:
7462          plane = nir_src_as_int(instr->src[i].src);
7463          break;
7464       default:
7465          break;
7466       }
7467    }
7468
7469    *stype = glsl_get_sampler_result_type(texture_deref_instr->type);
7470
7471    if (!sampler_deref_instr)
7472       sampler_deref_instr = texture_deref_instr;
7473
7474    if (plane >= 0) {
7475       assert(instr->op != nir_texop_txf_ms &&
7476              instr->op != nir_texop_samples_identical);
7477       assert(instr->sampler_dim  != GLSL_SAMPLER_DIM_BUF);
7478       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, (aco_descriptor_type)(ACO_DESC_PLANE_0 + plane), instr, false, false);
7479    } else if (instr->sampler_dim  == GLSL_SAMPLER_DIM_BUF) {
7480       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_BUFFER, instr, false, false);
7481    } else if (instr->op == nir_texop_fragment_mask_fetch) {
7482       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7483    } else {
7484       *res_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_IMAGE, instr, false, false);
7485    }
7486    if (samp_ptr) {
7487       *samp_ptr = get_sampler_desc(ctx, sampler_deref_instr, ACO_DESC_SAMPLER, instr, false, false);
7488
7489       if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT && ctx->options->chip_class < GFX8) {
7490          /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
7491          Builder bld(ctx->program, ctx->block);
7492
7493          /* to avoid unnecessary moves, we split and recombine sampler and image */
7494          Temp img[8] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1),
7495                         bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7496          Temp samp[4] = {bld.tmp(s1), bld.tmp(s1), bld.tmp(s1), bld.tmp(s1)};
7497          bld.pseudo(aco_opcode::p_split_vector, Definition(img[0]), Definition(img[1]),
7498                     Definition(img[2]), Definition(img[3]), Definition(img[4]),
7499                     Definition(img[5]), Definition(img[6]), Definition(img[7]), *res_ptr);
7500          bld.pseudo(aco_opcode::p_split_vector, Definition(samp[0]), Definition(samp[1]),
7501                     Definition(samp[2]), Definition(samp[3]), *samp_ptr);
7502
7503          samp[0] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), samp[0], img[7]);
7504          *res_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s8),
7505                                img[0], img[1], img[2], img[3],
7506                                img[4], img[5], img[6], img[7]);
7507          *samp_ptr = bld.pseudo(aco_opcode::p_create_vector, bld.def(s4),
7508                                 samp[0], samp[1], samp[2], samp[3]);
7509       }
7510    }
7511    if (fmask_ptr && (instr->op == nir_texop_txf_ms ||
7512                      instr->op == nir_texop_samples_identical))
7513       *fmask_ptr = get_sampler_desc(ctx, texture_deref_instr, ACO_DESC_FMASK, instr, false, false);
7514 }
7515
7516 void build_cube_select(isel_context *ctx, Temp ma, Temp id, Temp deriv,
7517                        Temp *out_ma, Temp *out_sc, Temp *out_tc)
7518 {
7519    Builder bld(ctx->program, ctx->block);
7520
7521    Temp deriv_x = emit_extract_vector(ctx, deriv, 0, v1);
7522    Temp deriv_y = emit_extract_vector(ctx, deriv, 1, v1);
7523    Temp deriv_z = emit_extract_vector(ctx, deriv, 2, v1);
7524
7525    Operand neg_one(0xbf800000u);
7526    Operand one(0x3f800000u);
7527    Operand two(0x40000000u);
7528    Operand four(0x40800000u);
7529
7530    Temp is_ma_positive = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), ma);
7531    Temp sgn_ma = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, one, is_ma_positive);
7532    Temp neg_sgn_ma = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1), Operand(0u), sgn_ma);
7533
7534    Temp is_ma_z = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), four, id);
7535    Temp is_ma_y = bld.vopc(aco_opcode::v_cmp_le_f32, bld.def(bld.lm), two, id);
7536    is_ma_y = bld.sop2(Builder::s_andn2, bld.hint_vcc(bld.def(bld.lm)), is_ma_y, is_ma_z);
7537    Temp is_not_ma_x = bld.sop2(aco_opcode::s_or_b64, bld.hint_vcc(bld.def(bld.lm)), bld.def(s1, scc), is_ma_z, is_ma_y);
7538
7539    // select sc
7540    Temp tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_z, deriv_x, is_not_ma_x);
7541    Temp sgn = bld.vop2_e64(aco_opcode::v_cndmask_b32, bld.def(v1),
7542                        bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_sgn_ma, sgn_ma, is_ma_z),
7543                        one, is_ma_y);
7544    *out_sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7545
7546    // select tc
7547    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_y, deriv_z, is_ma_y);
7548    sgn = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), neg_one, sgn_ma, is_ma_y);
7549    *out_tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tmp, sgn);
7550
7551    // select ma
7552    tmp = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
7553                   bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), deriv_x, deriv_y, is_ma_y),
7554                   deriv_z, is_ma_z);
7555    tmp = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x7fffffffu), tmp);
7556    *out_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), two, tmp);
7557 }
7558
7559 void prepare_cube_coords(isel_context *ctx, std::vector<Temp>& coords, Temp* ddx, Temp* ddy, bool is_deriv, bool is_array)
7560 {
7561    Builder bld(ctx->program, ctx->block);
7562    Temp ma, tc, sc, id;
7563
7564    if (is_array) {
7565       coords[3] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[3]);
7566
7567       // see comment in ac_prepare_cube_coords()
7568       if (ctx->options->chip_class <= GFX8)
7569          coords[3] = bld.vop2(aco_opcode::v_max_f32, bld.def(v1), Operand(0u), coords[3]);
7570    }
7571
7572    ma = bld.vop3(aco_opcode::v_cubema_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7573
7574    aco_ptr<VOP3A_instruction> vop3a{create_instruction<VOP3A_instruction>(aco_opcode::v_rcp_f32, asVOP3(Format::VOP1), 1, 1)};
7575    vop3a->operands[0] = Operand(ma);
7576    vop3a->abs[0] = true;
7577    Temp invma = bld.tmp(v1);
7578    vop3a->definitions[0] = Definition(invma);
7579    ctx->block->instructions.emplace_back(std::move(vop3a));
7580
7581    sc = bld.vop3(aco_opcode::v_cubesc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7582    if (!is_deriv)
7583       sc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), sc, invma, Operand(0x3fc00000u/*1.5*/));
7584
7585    tc = bld.vop3(aco_opcode::v_cubetc_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7586    if (!is_deriv)
7587       tc = bld.vop2(aco_opcode::v_madak_f32, bld.def(v1), tc, invma, Operand(0x3fc00000u/*1.5*/));
7588
7589    id = bld.vop3(aco_opcode::v_cubeid_f32, bld.def(v1), coords[0], coords[1], coords[2]);
7590
7591    if (is_deriv) {
7592       sc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), sc, invma);
7593       tc = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), tc, invma);
7594
7595       for (unsigned i = 0; i < 2; i++) {
7596          // see comment in ac_prepare_cube_coords()
7597          Temp deriv_ma;
7598          Temp deriv_sc, deriv_tc;
7599          build_cube_select(ctx, ma, id, i ? *ddy : *ddx,
7600                            &deriv_ma, &deriv_sc, &deriv_tc);
7601
7602          deriv_ma = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, invma);
7603
7604          Temp x = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7605                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_sc, invma),
7606                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, sc));
7607          Temp y = bld.vop2(aco_opcode::v_sub_f32, bld.def(v1),
7608                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_tc, invma),
7609                                bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), deriv_ma, tc));
7610          *(i ? ddy : ddx) = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), x, y);
7611       }
7612
7613       sc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), sc);
7614       tc = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand(0x3fc00000u/*1.5*/), tc);
7615    }
7616
7617    if (is_array)
7618       id = bld.vop2(aco_opcode::v_madmk_f32, bld.def(v1), coords[3], id, Operand(0x41000000u/*8.0*/));
7619    coords.resize(3);
7620    coords[0] = sc;
7621    coords[1] = tc;
7622    coords[2] = id;
7623 }
7624
7625 void get_const_vec(nir_ssa_def *vec, nir_const_value *cv[4])
7626 {
7627    if (vec->parent_instr->type != nir_instr_type_alu)
7628       return;
7629    nir_alu_instr *vec_instr = nir_instr_as_alu(vec->parent_instr);
7630    if (vec_instr->op != nir_op_vec(vec->num_components))
7631       return;
7632
7633    for (unsigned i = 0; i < vec->num_components; i++) {
7634       cv[i] = vec_instr->src[i].swizzle[0] == 0 ?
7635               nir_src_as_const_value(vec_instr->src[i].src) : NULL;
7636    }
7637 }
7638
7639 void visit_tex(isel_context *ctx, nir_tex_instr *instr)
7640 {
7641    Builder bld(ctx->program, ctx->block);
7642    bool has_bias = false, has_lod = false, level_zero = false, has_compare = false,
7643         has_offset = false, has_ddx = false, has_ddy = false, has_derivs = false, has_sample_index = false;
7644    Temp resource, sampler, fmask_ptr, bias = Temp(), compare = Temp(), sample_index = Temp(),
7645         lod = Temp(), offset = Temp(), ddx = Temp(), ddy = Temp();
7646    std::vector<Temp> coords;
7647    std::vector<Temp> derivs;
7648    nir_const_value *sample_index_cv = NULL;
7649    nir_const_value *const_offset[4] = {NULL, NULL, NULL, NULL};
7650    enum glsl_base_type stype;
7651    tex_fetch_ptrs(ctx, instr, &resource, &sampler, &fmask_ptr, &stype);
7652
7653    bool tg4_integer_workarounds = ctx->options->chip_class <= GFX8 && instr->op == nir_texop_tg4 &&
7654                                   (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT);
7655    bool tg4_integer_cube_workaround = tg4_integer_workarounds &&
7656                                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
7657
7658    for (unsigned i = 0; i < instr->num_srcs; i++) {
7659       switch (instr->src[i].src_type) {
7660       case nir_tex_src_coord: {
7661          Temp coord = get_ssa_temp(ctx, instr->src[i].src.ssa);
7662          for (unsigned i = 0; i < coord.size(); i++)
7663             coords.emplace_back(emit_extract_vector(ctx, coord, i, v1));
7664          break;
7665       }
7666       case nir_tex_src_bias:
7667          if (instr->op == nir_texop_txb) {
7668             bias = get_ssa_temp(ctx, instr->src[i].src.ssa);
7669             has_bias = true;
7670          }
7671          break;
7672       case nir_tex_src_lod: {
7673          nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
7674
7675          if (val && val->f32 <= 0.0) {
7676             level_zero = true;
7677          } else {
7678             lod = get_ssa_temp(ctx, instr->src[i].src.ssa);
7679             has_lod = true;
7680          }
7681          break;
7682       }
7683       case nir_tex_src_comparator:
7684          if (instr->is_shadow) {
7685             compare = get_ssa_temp(ctx, instr->src[i].src.ssa);
7686             has_compare = true;
7687          }
7688          break;
7689       case nir_tex_src_offset:
7690          offset = get_ssa_temp(ctx, instr->src[i].src.ssa);
7691          get_const_vec(instr->src[i].src.ssa, const_offset);
7692          has_offset = true;
7693          break;
7694       case nir_tex_src_ddx:
7695          ddx = get_ssa_temp(ctx, instr->src[i].src.ssa);
7696          has_ddx = true;
7697          break;
7698       case nir_tex_src_ddy:
7699          ddy = get_ssa_temp(ctx, instr->src[i].src.ssa);
7700          has_ddy = true;
7701          break;
7702       case nir_tex_src_ms_index:
7703          sample_index = get_ssa_temp(ctx, instr->src[i].src.ssa);
7704          sample_index_cv = nir_src_as_const_value(instr->src[i].src);
7705          has_sample_index = true;
7706          break;
7707       case nir_tex_src_texture_offset:
7708       case nir_tex_src_sampler_offset:
7709       default:
7710          break;
7711       }
7712    }
7713
7714    if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
7715       return get_buffer_size(ctx, resource, get_ssa_temp(ctx, &instr->dest.ssa), true);
7716
7717    if (instr->op == nir_texop_texture_samples) {
7718       Temp dword3 = emit_extract_vector(ctx, resource, 3, s1);
7719
7720       Temp samples_log2 = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(16u | 4u<<16));
7721       Temp samples = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), Operand(1u), samples_log2);
7722       Temp type = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), dword3, Operand(28u | 4u<<16 /* offset=28, width=4 */));
7723       Temp is_msaa = bld.sopc(aco_opcode::s_cmp_ge_u32, bld.def(s1, scc), type, Operand(14u));
7724
7725       bld.sop2(aco_opcode::s_cselect_b32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
7726                samples, Operand(1u), bld.scc(is_msaa));
7727       return;
7728    }
7729
7730    if (has_offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
7731       aco_ptr<Instruction> tmp_instr;
7732       Temp acc, pack = Temp();
7733
7734       uint32_t pack_const = 0;
7735       for (unsigned i = 0; i < offset.size(); i++) {
7736          if (!const_offset[i])
7737             continue;
7738          pack_const |= (const_offset[i]->u32 & 0x3Fu) << (8u * i);
7739       }
7740
7741       if (offset.type() == RegType::sgpr) {
7742          for (unsigned i = 0; i < offset.size(); i++) {
7743             if (const_offset[i])
7744                continue;
7745
7746             acc = emit_extract_vector(ctx, offset, i, s1);
7747             acc = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(0x3Fu));
7748
7749             if (i) {
7750                acc = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), acc, Operand(8u * i));
7751             }
7752
7753             if (pack == Temp()) {
7754                pack = acc;
7755             } else {
7756                pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), pack, acc);
7757             }
7758          }
7759
7760          if (pack_const && pack != Temp())
7761             pack = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), Operand(pack_const), pack);
7762       } else {
7763          for (unsigned i = 0; i < offset.size(); i++) {
7764             if (const_offset[i])
7765                continue;
7766
7767             acc = emit_extract_vector(ctx, offset, i, v1);
7768             acc = bld.vop2(aco_opcode::v_and_b32, bld.def(v1), Operand(0x3Fu), acc);
7769
7770             if (i) {
7771                acc = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(8u * i), acc);
7772             }
7773
7774             if (pack == Temp()) {
7775                pack = acc;
7776             } else {
7777                pack = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), pack, acc);
7778             }
7779          }
7780
7781          if (pack_const && pack != Temp())
7782             pack = bld.sop2(aco_opcode::v_or_b32, bld.def(v1), Operand(pack_const), pack);
7783       }
7784       if (pack_const && pack == Temp())
7785          offset = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(pack_const));
7786       else if (pack == Temp())
7787          has_offset = false;
7788       else
7789          offset = pack;
7790    }
7791
7792    if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && instr->coord_components)
7793       prepare_cube_coords(ctx, coords, &ddx, &ddy, instr->op == nir_texop_txd, instr->is_array && instr->op != nir_texop_lod);
7794
7795    /* pack derivatives */
7796    if (has_ddx || has_ddy) {
7797       if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && ctx->options->chip_class == GFX9) {
7798          assert(has_ddx && has_ddy && ddx.size() == 1 && ddy.size() == 1);
7799          Temp zero = bld.copy(bld.def(v1), Operand(0u));
7800          derivs = {ddy, zero, ddy, zero};
7801       } else {
7802          for (unsigned i = 0; has_ddx && i < ddx.size(); i++)
7803             derivs.emplace_back(emit_extract_vector(ctx, ddx, i, v1));
7804          for (unsigned i = 0; has_ddy && i < ddy.size(); i++)
7805             derivs.emplace_back(emit_extract_vector(ctx, ddy, i, v1));
7806       }
7807       has_derivs = true;
7808    }
7809
7810    if (instr->coord_components > 1 &&
7811        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7812        instr->is_array &&
7813        instr->op != nir_texop_txf)
7814       coords[1] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[1]);
7815
7816    if (instr->coord_components > 2 &&
7817       (instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
7818        instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7819        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
7820        instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7821        instr->is_array &&
7822        instr->op != nir_texop_txf &&
7823        instr->op != nir_texop_txf_ms &&
7824        instr->op != nir_texop_fragment_fetch &&
7825        instr->op != nir_texop_fragment_mask_fetch)
7826       coords[2] = bld.vop1(aco_opcode::v_rndne_f32, bld.def(v1), coords[2]);
7827
7828    if (ctx->options->chip_class == GFX9 &&
7829        instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7830        instr->op != nir_texop_lod && instr->coord_components) {
7831       assert(coords.size() > 0 && coords.size() < 3);
7832
7833       coords.insert(std::next(coords.begin()), bld.copy(bld.def(v1), instr->op == nir_texop_txf ?
7834                                                                      Operand((uint32_t) 0) :
7835                                                                      Operand((uint32_t) 0x3f000000)));
7836    }
7837
7838    bool da = should_declare_array(ctx, instr->sampler_dim, instr->is_array);
7839
7840    if (instr->op == nir_texop_samples_identical)
7841       resource = fmask_ptr;
7842
7843    else if ((instr->sampler_dim == GLSL_SAMPLER_DIM_MS ||
7844              instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) &&
7845             instr->op != nir_texop_txs &&
7846             instr->op != nir_texop_fragment_fetch &&
7847             instr->op != nir_texop_fragment_mask_fetch) {
7848       assert(has_sample_index);
7849       Operand op(sample_index);
7850       if (sample_index_cv)
7851          op = Operand(sample_index_cv->u32);
7852       sample_index = adjust_sample_index_using_fmask(ctx, da, coords, op, fmask_ptr);
7853    }
7854
7855    if (has_offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
7856       for (unsigned i = 0; i < std::min(offset.size(), instr->coord_components); i++) {
7857          Temp off = emit_extract_vector(ctx, offset, i, v1);
7858          coords[i] = bld.vadd32(bld.def(v1), coords[i], off);
7859       }
7860       has_offset = false;
7861    }
7862
7863    /* Build tex instruction */
7864    unsigned dmask = nir_ssa_def_components_read(&instr->dest.ssa);
7865    unsigned dim = ctx->options->chip_class >= GFX10 && instr->sampler_dim != GLSL_SAMPLER_DIM_BUF
7866                   ? ac_get_sampler_dim(ctx->options->chip_class, instr->sampler_dim, instr->is_array)
7867                   : 0;
7868    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
7869    Temp tmp_dst = dst;
7870
7871    /* gather4 selects the component by dmask and always returns vec4 */
7872    if (instr->op == nir_texop_tg4) {
7873       assert(instr->dest.ssa.num_components == 4);
7874       if (instr->is_shadow)
7875          dmask = 1;
7876       else
7877          dmask = 1 << instr->component;
7878       if (tg4_integer_cube_workaround || dst.type() == RegType::sgpr)
7879          tmp_dst = bld.tmp(v4);
7880    } else if (instr->op == nir_texop_samples_identical) {
7881       tmp_dst = bld.tmp(v1);
7882    } else if (util_bitcount(dmask) != instr->dest.ssa.num_components || dst.type() == RegType::sgpr) {
7883       tmp_dst = bld.tmp(RegClass(RegType::vgpr, util_bitcount(dmask)));
7884    }
7885
7886    aco_ptr<MIMG_instruction> tex;
7887    if (instr->op == nir_texop_txs || instr->op == nir_texop_query_levels) {
7888       if (!has_lod)
7889          lod = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7890
7891       bool div_by_6 = instr->op == nir_texop_txs &&
7892                       instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
7893                       instr->is_array &&
7894                       (dmask & (1 << 2));
7895       if (tmp_dst.id() == dst.id() && div_by_6)
7896          tmp_dst = bld.tmp(tmp_dst.regClass());
7897
7898       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7899       tex->operands[0] = Operand(resource);
7900       tex->operands[1] = Operand(s4); /* no sampler */
7901       tex->operands[2] = Operand(as_vgpr(ctx,lod));
7902       if (ctx->options->chip_class == GFX9 &&
7903           instr->op == nir_texop_txs &&
7904           instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
7905           instr->is_array) {
7906          tex->dmask = (dmask & 0x1) | ((dmask & 0x2) << 1);
7907       } else if (instr->op == nir_texop_query_levels) {
7908          tex->dmask = 1 << 3;
7909       } else {
7910          tex->dmask = dmask;
7911       }
7912       tex->da = da;
7913       tex->definitions[0] = Definition(tmp_dst);
7914       tex->dim = dim;
7915       tex->can_reorder = true;
7916       ctx->block->instructions.emplace_back(std::move(tex));
7917
7918       if (div_by_6) {
7919          /* divide 3rd value by 6 by multiplying with magic number */
7920          emit_split_vector(ctx, tmp_dst, tmp_dst.size());
7921          Temp c = bld.copy(bld.def(s1), Operand((uint32_t) 0x2AAAAAAB));
7922          Temp by_6 = bld.vop3(aco_opcode::v_mul_hi_i32, bld.def(v1), emit_extract_vector(ctx, tmp_dst, 2, v1), c);
7923          assert(instr->dest.ssa.num_components == 3);
7924          Temp tmp = dst.type() == RegType::vgpr ? dst : bld.tmp(v3);
7925          tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
7926                               emit_extract_vector(ctx, tmp_dst, 0, v1),
7927                               emit_extract_vector(ctx, tmp_dst, 1, v1),
7928                               by_6);
7929
7930       }
7931
7932       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
7933       return;
7934    }
7935
7936    Temp tg4_compare_cube_wa64 = Temp();
7937
7938    if (tg4_integer_workarounds) {
7939       tex.reset(create_instruction<MIMG_instruction>(aco_opcode::image_get_resinfo, Format::MIMG, 3, 1));
7940       tex->operands[0] = Operand(resource);
7941       tex->operands[1] = Operand(s4); /* no sampler */
7942       tex->operands[2] = bld.vop1(aco_opcode::v_mov_b32, bld.def(v1), Operand(0u));
7943       tex->dim = dim;
7944       tex->dmask = 0x3;
7945       tex->da = da;
7946       Temp size = bld.tmp(v2);
7947       tex->definitions[0] = Definition(size);
7948       tex->can_reorder = true;
7949       ctx->block->instructions.emplace_back(std::move(tex));
7950       emit_split_vector(ctx, size, size.size());
7951
7952       Temp half_texel[2];
7953       for (unsigned i = 0; i < 2; i++) {
7954          half_texel[i] = emit_extract_vector(ctx, size, i, v1);
7955          half_texel[i] = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), half_texel[i]);
7956          half_texel[i] = bld.vop1(aco_opcode::v_rcp_iflag_f32, bld.def(v1), half_texel[i]);
7957          half_texel[i] = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), Operand(0xbf000000/*-0.5*/), half_texel[i]);
7958       }
7959
7960       Temp new_coords[2] = {
7961          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[0], half_texel[0]),
7962          bld.vop2(aco_opcode::v_add_f32, bld.def(v1), coords[1], half_texel[1])
7963       };
7964
7965       if (tg4_integer_cube_workaround) {
7966          // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
7967          Temp desc[resource.size()];
7968          aco_ptr<Instruction> split{create_instruction<Pseudo_instruction>(aco_opcode::p_split_vector,
7969                                                                            Format::PSEUDO, 1, resource.size())};
7970          split->operands[0] = Operand(resource);
7971          for (unsigned i = 0; i < resource.size(); i++) {
7972             desc[i] = bld.tmp(s1);
7973             split->definitions[i] = Definition(desc[i]);
7974          }
7975          ctx->block->instructions.emplace_back(std::move(split));
7976
7977          Temp dfmt = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), desc[1], Operand(20u | (6u << 16)));
7978          Temp compare_cube_wa = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), dfmt,
7979                                          Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8));
7980
7981          Temp nfmt;
7982          if (stype == GLSL_TYPE_UINT) {
7983             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7984                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED),
7985                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT),
7986                             bld.scc(compare_cube_wa));
7987          } else {
7988             nfmt = bld.sop2(aco_opcode::s_cselect_b32, bld.def(s1),
7989                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED),
7990                             Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT),
7991                             bld.scc(compare_cube_wa));
7992          }
7993          tg4_compare_cube_wa64 = bld.tmp(bld.lm);
7994          bool_to_vector_condition(ctx, compare_cube_wa, tg4_compare_cube_wa64);
7995
7996          nfmt = bld.sop2(aco_opcode::s_lshl_b32, bld.def(s1), bld.def(s1, scc), nfmt, Operand(26u));
7997
7998          desc[1] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), desc[1],
7999                             Operand((uint32_t)C_008F14_NUM_FORMAT));
8000          desc[1] = bld.sop2(aco_opcode::s_or_b32, bld.def(s1), bld.def(s1, scc), desc[1], nfmt);
8001
8002          aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector,
8003                                                                          Format::PSEUDO, resource.size(), 1)};
8004          for (unsigned i = 0; i < resource.size(); i++)
8005             vec->operands[i] = Operand(desc[i]);
8006          resource = bld.tmp(resource.regClass());
8007          vec->definitions[0] = Definition(resource);
8008          ctx->block->instructions.emplace_back(std::move(vec));
8009
8010          new_coords[0] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8011                                   new_coords[0], coords[0], tg4_compare_cube_wa64);
8012          new_coords[1] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
8013                                   new_coords[1], coords[1], tg4_compare_cube_wa64);
8014       }
8015       coords[0] = new_coords[0];
8016       coords[1] = new_coords[1];
8017    }
8018
8019    if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
8020       //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8021
8022       assert(coords.size() == 1);
8023       unsigned last_bit = util_last_bit(nir_ssa_def_components_read(&instr->dest.ssa));
8024       aco_opcode op;
8025       switch (last_bit) {
8026       case 1:
8027          op = aco_opcode::buffer_load_format_x; break;
8028       case 2:
8029          op = aco_opcode::buffer_load_format_xy; break;
8030       case 3:
8031          op = aco_opcode::buffer_load_format_xyz; break;
8032       case 4:
8033          op = aco_opcode::buffer_load_format_xyzw; break;
8034       default:
8035          unreachable("Tex instruction loads more than 4 components.");
8036       }
8037
8038       /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8039       if (last_bit == instr->dest.ssa.num_components && dst.type() == RegType::vgpr)
8040          tmp_dst = dst;
8041       else
8042          tmp_dst = bld.tmp(RegType::vgpr, last_bit);
8043
8044       aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(op, Format::MUBUF, 3, 1)};
8045       mubuf->operands[0] = Operand(resource);
8046       mubuf->operands[1] = Operand(coords[0]);
8047       mubuf->operands[2] = Operand((uint32_t) 0);
8048       mubuf->definitions[0] = Definition(tmp_dst);
8049       mubuf->idxen = true;
8050       mubuf->can_reorder = true;
8051       ctx->block->instructions.emplace_back(std::move(mubuf));
8052
8053       expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, (1 << last_bit) - 1);
8054       return;
8055    }
8056
8057    /* gather MIMG address components */
8058    std::vector<Temp> args;
8059    if (has_offset)
8060       args.emplace_back(offset);
8061    if (has_bias)
8062       args.emplace_back(bias);
8063    if (has_compare)
8064       args.emplace_back(compare);
8065    if (has_derivs)
8066       args.insert(args.end(), derivs.begin(), derivs.end());
8067
8068    args.insert(args.end(), coords.begin(), coords.end());
8069    if (has_sample_index)
8070       args.emplace_back(sample_index);
8071    if (has_lod)
8072       args.emplace_back(lod);
8073
8074    Temp arg = bld.tmp(RegClass(RegType::vgpr, args.size()));
8075    aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, args.size(), 1)};
8076    vec->definitions[0] = Definition(arg);
8077    for (unsigned i = 0; i < args.size(); i++)
8078       vec->operands[i] = Operand(args[i]);
8079    ctx->block->instructions.emplace_back(std::move(vec));
8080
8081
8082    if (instr->op == nir_texop_txf ||
8083        instr->op == nir_texop_txf_ms ||
8084        instr->op == nir_texop_samples_identical ||
8085        instr->op == nir_texop_fragment_fetch ||
8086        instr->op == nir_texop_fragment_mask_fetch) {
8087       aco_opcode op = level_zero || instr->sampler_dim == GLSL_SAMPLER_DIM_MS || instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS ? aco_opcode::image_load : aco_opcode::image_load_mip;
8088       tex.reset(create_instruction<MIMG_instruction>(op, Format::MIMG, 3, 1));
8089       tex->operands[0] = Operand(resource);
8090       tex->operands[1] = Operand(s4); /* no sampler */
8091       tex->operands[2] = Operand(arg);
8092       tex->dim = dim;
8093       tex->dmask = dmask;
8094       tex->unrm = true;
8095       tex->da = da;
8096       tex->definitions[0] = Definition(tmp_dst);
8097       tex->can_reorder = true;
8098       ctx->block->instructions.emplace_back(std::move(tex));
8099
8100       if (instr->op == nir_texop_samples_identical) {
8101          assert(dmask == 1 && dst.regClass() == v1);
8102          assert(dst.id() != tmp_dst.id());
8103
8104          Temp tmp = bld.tmp(bld.lm);
8105          bld.vopc(aco_opcode::v_cmp_eq_u32, Definition(tmp), Operand(0u), tmp_dst).def(0).setHint(vcc);
8106          bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), Operand(0u), Operand((uint32_t)-1), tmp);
8107
8108       } else {
8109          expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, dmask);
8110       }
8111       return;
8112    }
8113
8114    // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8115    aco_opcode opcode = aco_opcode::image_sample;
8116    if (has_offset) { /* image_sample_*_o */
8117       if (has_compare) {
8118          opcode = aco_opcode::image_sample_c_o;
8119          if (has_derivs)
8120             opcode = aco_opcode::image_sample_c_d_o;
8121          if (has_bias)
8122             opcode = aco_opcode::image_sample_c_b_o;
8123          if (level_zero)
8124             opcode = aco_opcode::image_sample_c_lz_o;
8125          if (has_lod)
8126             opcode = aco_opcode::image_sample_c_l_o;
8127       } else {
8128          opcode = aco_opcode::image_sample_o;
8129          if (has_derivs)
8130             opcode = aco_opcode::image_sample_d_o;
8131          if (has_bias)
8132             opcode = aco_opcode::image_sample_b_o;
8133          if (level_zero)
8134             opcode = aco_opcode::image_sample_lz_o;
8135          if (has_lod)
8136             opcode = aco_opcode::image_sample_l_o;
8137       }
8138    } else { /* no offset */
8139       if (has_compare) {
8140          opcode = aco_opcode::image_sample_c;
8141          if (has_derivs)
8142             opcode = aco_opcode::image_sample_c_d;
8143          if (has_bias)
8144             opcode = aco_opcode::image_sample_c_b;
8145          if (level_zero)
8146             opcode = aco_opcode::image_sample_c_lz;
8147          if (has_lod)
8148             opcode = aco_opcode::image_sample_c_l;
8149       } else {
8150          opcode = aco_opcode::image_sample;
8151          if (has_derivs)
8152             opcode = aco_opcode::image_sample_d;
8153          if (has_bias)
8154             opcode = aco_opcode::image_sample_b;
8155          if (level_zero)
8156             opcode = aco_opcode::image_sample_lz;
8157          if (has_lod)
8158             opcode = aco_opcode::image_sample_l;
8159       }
8160    }
8161
8162    if (instr->op == nir_texop_tg4) {
8163       if (has_offset) {
8164          opcode = aco_opcode::image_gather4_lz_o;
8165          if (has_compare)
8166             opcode = aco_opcode::image_gather4_c_lz_o;
8167       } else {
8168          opcode = aco_opcode::image_gather4_lz;
8169          if (has_compare)
8170             opcode = aco_opcode::image_gather4_c_lz;
8171       }
8172    } else if (instr->op == nir_texop_lod) {
8173       opcode = aco_opcode::image_get_lod;
8174    }
8175
8176    /* we don't need the bias, sample index, compare value or offset to be
8177     * computed in WQM but if the p_create_vector copies the coordinates, then it
8178     * needs to be in WQM */
8179    if (ctx->stage == fragment_fs &&
8180        !has_derivs && !has_lod && !level_zero &&
8181        instr->sampler_dim != GLSL_SAMPLER_DIM_MS &&
8182        instr->sampler_dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
8183       arg = emit_wqm(ctx, arg, bld.tmp(arg.regClass()), true);
8184
8185    tex.reset(create_instruction<MIMG_instruction>(opcode, Format::MIMG, 3, 1));
8186    tex->operands[0] = Operand(resource);
8187    tex->operands[1] = Operand(sampler);
8188    tex->operands[2] = Operand(arg);
8189    tex->dim = dim;
8190    tex->dmask = dmask;
8191    tex->da = da;
8192    tex->definitions[0] = Definition(tmp_dst);
8193    tex->can_reorder = true;
8194    ctx->block->instructions.emplace_back(std::move(tex));
8195
8196    if (tg4_integer_cube_workaround) {
8197       assert(tmp_dst.id() != dst.id());
8198       assert(tmp_dst.size() == dst.size() && dst.size() == 4);
8199
8200       emit_split_vector(ctx, tmp_dst, tmp_dst.size());
8201       Temp val[4];
8202       for (unsigned i = 0; i < dst.size(); i++) {
8203          val[i] = emit_extract_vector(ctx, tmp_dst, i, v1);
8204          Temp cvt_val;
8205          if (stype == GLSL_TYPE_UINT)
8206             cvt_val = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), val[i]);
8207          else
8208             cvt_val = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), val[i]);
8209          val[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), val[i], cvt_val, tg4_compare_cube_wa64);
8210       }
8211       Temp tmp = dst.regClass() == v4 ? dst : bld.tmp(v4);
8212       tmp_dst = bld.pseudo(aco_opcode::p_create_vector, Definition(tmp),
8213                            val[0], val[1], val[2], val[3]);
8214    }
8215    unsigned mask = instr->op == nir_texop_tg4 ? 0xF : dmask;
8216    expand_vector(ctx, tmp_dst, dst, instr->dest.ssa.num_components, mask);
8217
8218 }
8219
8220
8221 Operand get_phi_operand(isel_context *ctx, nir_ssa_def *ssa)
8222 {
8223    Temp tmp = get_ssa_temp(ctx, ssa);
8224    if (ssa->parent_instr->type == nir_instr_type_ssa_undef)
8225       return Operand(tmp.regClass());
8226    else
8227       return Operand(tmp);
8228 }
8229
8230 void visit_phi(isel_context *ctx, nir_phi_instr *instr)
8231 {
8232    aco_ptr<Pseudo_instruction> phi;
8233    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
8234    assert(instr->dest.ssa.bit_size != 1 || dst.regClass() == ctx->program->lane_mask);
8235
8236    bool logical = !dst.is_linear() || ctx->divergent_vals[instr->dest.ssa.index];
8237    logical |= ctx->block->kind & block_kind_merge;
8238    aco_opcode opcode = logical ? aco_opcode::p_phi : aco_opcode::p_linear_phi;
8239
8240    /* we want a sorted list of sources, since the predecessor list is also sorted */
8241    std::map<unsigned, nir_ssa_def*> phi_src;
8242    nir_foreach_phi_src(src, instr)
8243       phi_src[src->pred->index] = src->src.ssa;
8244
8245    std::vector<unsigned>& preds = logical ? ctx->block->logical_preds : ctx->block->linear_preds;
8246    unsigned num_operands = 0;
8247    Operand operands[std::max(exec_list_length(&instr->srcs), (unsigned)preds.size()) + 1];
8248    unsigned num_defined = 0;
8249    unsigned cur_pred_idx = 0;
8250    for (std::pair<unsigned, nir_ssa_def *> src : phi_src) {
8251       if (cur_pred_idx < preds.size()) {
8252          /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8253          unsigned block = ctx->cf_info.nir_to_aco[src.first];
8254          unsigned skipped = 0;
8255          while (cur_pred_idx + skipped < preds.size() && preds[cur_pred_idx + skipped] != block)
8256             skipped++;
8257          if (cur_pred_idx + skipped < preds.size()) {
8258             for (unsigned i = 0; i < skipped; i++)
8259                operands[num_operands++] = Operand(dst.regClass());
8260             cur_pred_idx += skipped;
8261          } else {
8262             continue;
8263          }
8264       }
8265       /* Handle missing predecessors at the end. This shouldn't happen with loop
8266        * headers and we can't ignore these sources for loop header phis. */
8267       if (!(ctx->block->kind & block_kind_loop_header) && cur_pred_idx >= preds.size())
8268          continue;
8269       cur_pred_idx++;
8270       Operand op = get_phi_operand(ctx, src.second);
8271       operands[num_operands++] = op;
8272       num_defined += !op.isUndefined();
8273    }
8274    /* handle block_kind_continue_or_break at loop exit blocks */
8275    while (cur_pred_idx++ < preds.size())
8276       operands[num_operands++] = Operand(dst.regClass());
8277
8278    /* If the loop ends with a break, still add a linear continue edge in case
8279     * that break is divergent or continue_or_break is used. We'll either remove
8280     * this operand later in visit_loop() if it's not necessary or replace the
8281     * undef with something correct. */
8282    if (!logical && ctx->block->kind & block_kind_loop_header) {
8283       nir_loop *loop = nir_cf_node_as_loop(instr->instr.block->cf_node.parent);
8284       nir_block *last = nir_loop_last_block(loop);
8285       if (last->successors[0] != instr->instr.block)
8286          operands[num_operands++] = Operand(RegClass());
8287    }
8288
8289    if (num_defined == 0) {
8290       Builder bld(ctx->program, ctx->block);
8291       if (dst.regClass() == s1) {
8292          bld.sop1(aco_opcode::s_mov_b32, Definition(dst), Operand(0u));
8293       } else if (dst.regClass() == v1) {
8294          bld.vop1(aco_opcode::v_mov_b32, Definition(dst), Operand(0u));
8295       } else {
8296          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8297          for (unsigned i = 0; i < dst.size(); i++)
8298             vec->operands[i] = Operand(0u);
8299          vec->definitions[0] = Definition(dst);
8300          ctx->block->instructions.emplace_back(std::move(vec));
8301       }
8302       return;
8303    }
8304
8305    /* we can use a linear phi in some cases if one src is undef */
8306    if (dst.is_linear() && ctx->block->kind & block_kind_merge && num_defined == 1) {
8307       phi.reset(create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, num_operands, 1));
8308
8309       Block *linear_else = &ctx->program->blocks[ctx->block->linear_preds[1]];
8310       Block *invert = &ctx->program->blocks[linear_else->linear_preds[0]];
8311       assert(invert->kind & block_kind_invert);
8312
8313       unsigned then_block = invert->linear_preds[0];
8314
8315       Block* insert_block = NULL;
8316       for (unsigned i = 0; i < num_operands; i++) {
8317          Operand op = operands[i];
8318          if (op.isUndefined())
8319             continue;
8320          insert_block = ctx->block->logical_preds[i] == then_block ? invert : ctx->block;
8321          phi->operands[0] = op;
8322          break;
8323       }
8324       assert(insert_block); /* should be handled by the "num_defined == 0" case above */
8325       phi->operands[1] = Operand(dst.regClass());
8326       phi->definitions[0] = Definition(dst);
8327       insert_block->instructions.emplace(insert_block->instructions.begin(), std::move(phi));
8328       return;
8329    }
8330
8331    /* try to scalarize vector phis */
8332    if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
8333       // TODO: scalarize linear phis on divergent ifs
8334       bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
8335       std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
8336       for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
8337          Operand src = operands[i];
8338          if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
8339             can_scalarize = false;
8340       }
8341       if (can_scalarize) {
8342          unsigned num_components = instr->dest.ssa.num_components;
8343          assert(dst.size() % num_components == 0);
8344          RegClass rc = RegClass(dst.type(), dst.size() / num_components);
8345
8346          aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
8347          for (unsigned k = 0; k < num_components; k++) {
8348             phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8349             for (unsigned i = 0; i < num_operands; i++) {
8350                Operand src = operands[i];
8351                phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
8352             }
8353             Temp phi_dst = {ctx->program->allocateId(), rc};
8354             phi->definitions[0] = Definition(phi_dst);
8355             ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8356             new_vec[k] = phi_dst;
8357             vec->operands[k] = Operand(phi_dst);
8358          }
8359          vec->definitions[0] = Definition(dst);
8360          ctx->block->instructions.emplace_back(std::move(vec));
8361          ctx->allocated_vec.emplace(dst.id(), new_vec);
8362          return;
8363       }
8364    }
8365
8366    phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
8367    for (unsigned i = 0; i < num_operands; i++)
8368       phi->operands[i] = operands[i];
8369    phi->definitions[0] = Definition(dst);
8370    ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
8371 }
8372
8373
8374 void visit_undef(isel_context *ctx, nir_ssa_undef_instr *instr)
8375 {
8376    Temp dst = get_ssa_temp(ctx, &instr->def);
8377
8378    assert(dst.type() == RegType::sgpr);
8379
8380    if (dst.size() == 1) {
8381       Builder(ctx->program, ctx->block).copy(Definition(dst), Operand(0u));
8382    } else {
8383       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, dst.size(), 1)};
8384       for (unsigned i = 0; i < dst.size(); i++)
8385          vec->operands[i] = Operand(0u);
8386       vec->definitions[0] = Definition(dst);
8387       ctx->block->instructions.emplace_back(std::move(vec));
8388    }
8389 }
8390
8391 void visit_jump(isel_context *ctx, nir_jump_instr *instr)
8392 {
8393    Builder bld(ctx->program, ctx->block);
8394    Block *logical_target;
8395    append_logical_end(ctx->block);
8396    unsigned idx = ctx->block->index;
8397
8398    switch (instr->type) {
8399    case nir_jump_break:
8400       logical_target = ctx->cf_info.parent_loop.exit;
8401       add_logical_edge(idx, logical_target);
8402       ctx->block->kind |= block_kind_break;
8403
8404       if (!ctx->cf_info.parent_if.is_divergent &&
8405           !ctx->cf_info.parent_loop.has_divergent_continue) {
8406          /* uniform break - directly jump out of the loop */
8407          ctx->block->kind |= block_kind_uniform;
8408          ctx->cf_info.has_branch = true;
8409          bld.branch(aco_opcode::p_branch);
8410          add_linear_edge(idx, logical_target);
8411          return;
8412       }
8413       ctx->cf_info.parent_loop.has_divergent_branch = true;
8414       ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8415       break;
8416    case nir_jump_continue:
8417       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8418       add_logical_edge(idx, logical_target);
8419       ctx->block->kind |= block_kind_continue;
8420
8421       if (ctx->cf_info.parent_if.is_divergent) {
8422          /* for potential uniform breaks after this continue,
8423             we must ensure that they are handled correctly */
8424          ctx->cf_info.parent_loop.has_divergent_continue = true;
8425          ctx->cf_info.parent_loop.has_divergent_branch = true;
8426          ctx->cf_info.nir_to_aco[instr->instr.block->index] = ctx->block->index;
8427       } else {
8428          /* uniform continue - directly jump to the loop header */
8429          ctx->block->kind |= block_kind_uniform;
8430          ctx->cf_info.has_branch = true;
8431          bld.branch(aco_opcode::p_branch);
8432          add_linear_edge(idx, logical_target);
8433          return;
8434       }
8435       break;
8436    default:
8437       fprintf(stderr, "Unknown NIR jump instr: ");
8438       nir_print_instr(&instr->instr, stderr);
8439       fprintf(stderr, "\n");
8440       abort();
8441    }
8442
8443    if (ctx->cf_info.parent_if.is_divergent && !ctx->cf_info.exec_potentially_empty_break) {
8444       ctx->cf_info.exec_potentially_empty_break = true;
8445       ctx->cf_info.exec_potentially_empty_break_depth = ctx->cf_info.loop_nest_depth;
8446    }
8447
8448    /* remove critical edges from linear CFG */
8449    bld.branch(aco_opcode::p_branch);
8450    Block* break_block = ctx->program->create_and_insert_block();
8451    break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8452    break_block->kind |= block_kind_uniform;
8453    add_linear_edge(idx, break_block);
8454    /* the loop_header pointer might be invalidated by this point */
8455    if (instr->type == nir_jump_continue)
8456       logical_target = &ctx->program->blocks[ctx->cf_info.parent_loop.header_idx];
8457    add_linear_edge(break_block->index, logical_target);
8458    bld.reset(break_block);
8459    bld.branch(aco_opcode::p_branch);
8460
8461    Block* continue_block = ctx->program->create_and_insert_block();
8462    continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8463    add_linear_edge(idx, continue_block);
8464    append_logical_start(continue_block);
8465    ctx->block = continue_block;
8466    return;
8467 }
8468
8469 void visit_block(isel_context *ctx, nir_block *block)
8470 {
8471    nir_foreach_instr(instr, block) {
8472       switch (instr->type) {
8473       case nir_instr_type_alu:
8474          visit_alu_instr(ctx, nir_instr_as_alu(instr));
8475          break;
8476       case nir_instr_type_load_const:
8477          visit_load_const(ctx, nir_instr_as_load_const(instr));
8478          break;
8479       case nir_instr_type_intrinsic:
8480          visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
8481          break;
8482       case nir_instr_type_tex:
8483          visit_tex(ctx, nir_instr_as_tex(instr));
8484          break;
8485       case nir_instr_type_phi:
8486          visit_phi(ctx, nir_instr_as_phi(instr));
8487          break;
8488       case nir_instr_type_ssa_undef:
8489          visit_undef(ctx, nir_instr_as_ssa_undef(instr));
8490          break;
8491       case nir_instr_type_deref:
8492          break;
8493       case nir_instr_type_jump:
8494          visit_jump(ctx, nir_instr_as_jump(instr));
8495          break;
8496       default:
8497          fprintf(stderr, "Unknown NIR instr type: ");
8498          nir_print_instr(instr, stderr);
8499          fprintf(stderr, "\n");
8500          //abort();
8501       }
8502    }
8503
8504    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8505       ctx->cf_info.nir_to_aco[block->index] = ctx->block->index;
8506 }
8507
8508
8509
8510 static Operand create_continue_phis(isel_context *ctx, unsigned first, unsigned last,
8511                                     aco_ptr<Instruction>& header_phi, Operand *vals)
8512 {
8513    vals[0] = Operand(header_phi->definitions[0].getTemp());
8514    RegClass rc = vals[0].regClass();
8515
8516    unsigned loop_nest_depth = ctx->program->blocks[first].loop_nest_depth;
8517
8518    unsigned next_pred = 1;
8519
8520    for (unsigned idx = first + 1; idx <= last; idx++) {
8521       Block& block = ctx->program->blocks[idx];
8522       if (block.loop_nest_depth != loop_nest_depth) {
8523          vals[idx - first] = vals[idx - 1 - first];
8524          continue;
8525       }
8526
8527       if (block.kind & block_kind_continue) {
8528          vals[idx - first] = header_phi->operands[next_pred];
8529          next_pred++;
8530          continue;
8531       }
8532
8533       bool all_same = true;
8534       for (unsigned i = 1; all_same && (i < block.linear_preds.size()); i++)
8535          all_same = vals[block.linear_preds[i] - first] == vals[block.linear_preds[0] - first];
8536
8537       Operand val;
8538       if (all_same) {
8539          val = vals[block.linear_preds[0] - first];
8540       } else {
8541          aco_ptr<Instruction> phi(create_instruction<Pseudo_instruction>(
8542             aco_opcode::p_linear_phi, Format::PSEUDO, block.linear_preds.size(), 1));
8543          for (unsigned i = 0; i < block.linear_preds.size(); i++)
8544             phi->operands[i] = vals[block.linear_preds[i] - first];
8545          val = Operand(Temp(ctx->program->allocateId(), rc));
8546          phi->definitions[0] = Definition(val.getTemp());
8547          block.instructions.emplace(block.instructions.begin(), std::move(phi));
8548       }
8549       vals[idx - first] = val;
8550    }
8551
8552    return vals[last - first];
8553 }
8554
8555 static void visit_loop(isel_context *ctx, nir_loop *loop)
8556 {
8557    //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
8558    append_logical_end(ctx->block);
8559    ctx->block->kind |= block_kind_loop_preheader | block_kind_uniform;
8560    Builder bld(ctx->program, ctx->block);
8561    bld.branch(aco_opcode::p_branch);
8562    unsigned loop_preheader_idx = ctx->block->index;
8563
8564    Block loop_exit = Block();
8565    loop_exit.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8566    loop_exit.kind |= (block_kind_loop_exit | (ctx->block->kind & block_kind_top_level));
8567
8568    Block* loop_header = ctx->program->create_and_insert_block();
8569    loop_header->loop_nest_depth = ctx->cf_info.loop_nest_depth + 1;
8570    loop_header->kind |= block_kind_loop_header;
8571    add_edge(loop_preheader_idx, loop_header);
8572    ctx->block = loop_header;
8573
8574    /* emit loop body */
8575    unsigned loop_header_idx = loop_header->index;
8576    loop_info_RAII loop_raii(ctx, loop_header_idx, &loop_exit);
8577    append_logical_start(ctx->block);
8578    bool unreachable = visit_cf_list(ctx, &loop->body);
8579
8580    //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
8581    if (!ctx->cf_info.has_branch) {
8582       append_logical_end(ctx->block);
8583       if (ctx->cf_info.exec_potentially_empty_discard || ctx->cf_info.exec_potentially_empty_break) {
8584          /* Discards can result in code running with an empty exec mask.
8585           * This would result in divergent breaks not ever being taken. As a
8586           * workaround, break the loop when the loop mask is empty instead of
8587           * always continuing. */
8588          ctx->block->kind |= (block_kind_continue_or_break | block_kind_uniform);
8589          unsigned block_idx = ctx->block->index;
8590
8591          /* create helper blocks to avoid critical edges */
8592          Block *break_block = ctx->program->create_and_insert_block();
8593          break_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8594          break_block->kind = block_kind_uniform;
8595          bld.reset(break_block);
8596          bld.branch(aco_opcode::p_branch);
8597          add_linear_edge(block_idx, break_block);
8598          add_linear_edge(break_block->index, &loop_exit);
8599
8600          Block *continue_block = ctx->program->create_and_insert_block();
8601          continue_block->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8602          continue_block->kind = block_kind_uniform;
8603          bld.reset(continue_block);
8604          bld.branch(aco_opcode::p_branch);
8605          add_linear_edge(block_idx, continue_block);
8606          add_linear_edge(continue_block->index, &ctx->program->blocks[loop_header_idx]);
8607
8608          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8609             add_logical_edge(block_idx, &ctx->program->blocks[loop_header_idx]);
8610          ctx->block = &ctx->program->blocks[block_idx];
8611       } else {
8612          ctx->block->kind |= (block_kind_continue | block_kind_uniform);
8613          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8614             add_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8615          else
8616             add_linear_edge(ctx->block->index, &ctx->program->blocks[loop_header_idx]);
8617       }
8618
8619       bld.reset(ctx->block);
8620       bld.branch(aco_opcode::p_branch);
8621    }
8622
8623    /* Fixup phis in loop header from unreachable blocks.
8624     * has_branch/has_divergent_branch also indicates if the loop ends with a
8625     * break/continue instruction, but we don't emit those if unreachable=true */
8626    if (unreachable) {
8627       assert(ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch);
8628       bool linear = ctx->cf_info.has_branch;
8629       bool logical = ctx->cf_info.has_branch || ctx->cf_info.parent_loop.has_divergent_branch;
8630       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8631          if ((logical && instr->opcode == aco_opcode::p_phi) ||
8632              (linear && instr->opcode == aco_opcode::p_linear_phi)) {
8633             /* the last operand should be the one that needs to be removed */
8634             instr->operands.pop_back();
8635          } else if (!is_phi(instr)) {
8636             break;
8637          }
8638       }
8639    }
8640
8641    /* Fixup linear phis in loop header from expecting a continue. Both this fixup
8642     * and the previous one shouldn't both happen at once because a break in the
8643     * merge block would get CSE'd */
8644    if (nir_loop_last_block(loop)->successors[0] != nir_loop_first_block(loop)) {
8645       unsigned num_vals = ctx->cf_info.has_branch ? 1 : (ctx->block->index - loop_header_idx + 1);
8646       Operand vals[num_vals];
8647       for (aco_ptr<Instruction>& instr : ctx->program->blocks[loop_header_idx].instructions) {
8648          if (instr->opcode == aco_opcode::p_linear_phi) {
8649             if (ctx->cf_info.has_branch)
8650                instr->operands.pop_back();
8651             else
8652                instr->operands.back() = create_continue_phis(ctx, loop_header_idx, ctx->block->index, instr, vals);
8653          } else if (!is_phi(instr)) {
8654             break;
8655          }
8656       }
8657    }
8658
8659    ctx->cf_info.has_branch = false;
8660
8661    // TODO: if the loop has not a single exit, we must add one °°
8662    /* emit loop successor block */
8663    ctx->block = ctx->program->insert_block(std::move(loop_exit));
8664    append_logical_start(ctx->block);
8665
8666    #if 0
8667    // TODO: check if it is beneficial to not branch on continues
8668    /* trim linear phis in loop header */
8669    for (auto&& instr : loop_entry->instructions) {
8670       if (instr->opcode == aco_opcode::p_linear_phi) {
8671          aco_ptr<Pseudo_instruction> new_phi{create_instruction<Pseudo_instruction>(aco_opcode::p_linear_phi, Format::PSEUDO, loop_entry->linear_predecessors.size(), 1)};
8672          new_phi->definitions[0] = instr->definitions[0];
8673          for (unsigned i = 0; i < new_phi->operands.size(); i++)
8674             new_phi->operands[i] = instr->operands[i];
8675          /* check that the remaining operands are all the same */
8676          for (unsigned i = new_phi->operands.size(); i < instr->operands.size(); i++)
8677             assert(instr->operands[i].tempId() == instr->operands.back().tempId());
8678          instr.swap(new_phi);
8679       } else if (instr->opcode == aco_opcode::p_phi) {
8680          continue;
8681       } else {
8682          break;
8683       }
8684    }
8685    #endif
8686 }
8687
8688 static void begin_divergent_if_then(isel_context *ctx, if_context *ic, Temp cond)
8689 {
8690    ic->cond = cond;
8691
8692    append_logical_end(ctx->block);
8693    ctx->block->kind |= block_kind_branch;
8694
8695    /* branch to linear then block */
8696    assert(cond.regClass() == ctx->program->lane_mask);
8697    aco_ptr<Pseudo_branch_instruction> branch;
8698    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8699    branch->operands[0] = Operand(cond);
8700    ctx->block->instructions.push_back(std::move(branch));
8701
8702    ic->BB_if_idx = ctx->block->index;
8703    ic->BB_invert = Block();
8704    ic->BB_invert.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8705    /* Invert blocks are intentionally not marked as top level because they
8706     * are not part of the logical cfg. */
8707    ic->BB_invert.kind |= block_kind_invert;
8708    ic->BB_endif = Block();
8709    ic->BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8710    ic->BB_endif.kind |= (block_kind_merge | (ctx->block->kind & block_kind_top_level));
8711
8712    ic->exec_potentially_empty_discard_old = ctx->cf_info.exec_potentially_empty_discard;
8713    ic->exec_potentially_empty_break_old = ctx->cf_info.exec_potentially_empty_break;
8714    ic->exec_potentially_empty_break_depth_old = ctx->cf_info.exec_potentially_empty_break_depth;
8715    ic->divergent_old = ctx->cf_info.parent_if.is_divergent;
8716    ctx->cf_info.parent_if.is_divergent = true;
8717
8718    /* divergent branches use cbranch_execz */
8719    ctx->cf_info.exec_potentially_empty_discard = false;
8720    ctx->cf_info.exec_potentially_empty_break = false;
8721    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8722
8723    /** emit logical then block */
8724    Block* BB_then_logical = ctx->program->create_and_insert_block();
8725    BB_then_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8726    add_edge(ic->BB_if_idx, BB_then_logical);
8727    ctx->block = BB_then_logical;
8728    append_logical_start(BB_then_logical);
8729 }
8730
8731 static void begin_divergent_if_else(isel_context *ctx, if_context *ic)
8732 {
8733    Block *BB_then_logical = ctx->block;
8734    append_logical_end(BB_then_logical);
8735     /* branch from logical then block to invert block */
8736    aco_ptr<Pseudo_branch_instruction> branch;
8737    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8738    BB_then_logical->instructions.emplace_back(std::move(branch));
8739    add_linear_edge(BB_then_logical->index, &ic->BB_invert);
8740    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8741       add_logical_edge(BB_then_logical->index, &ic->BB_endif);
8742    BB_then_logical->kind |= block_kind_uniform;
8743    assert(!ctx->cf_info.has_branch);
8744    ic->then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8745    ctx->cf_info.parent_loop.has_divergent_branch = false;
8746
8747    /** emit linear then block */
8748    Block* BB_then_linear = ctx->program->create_and_insert_block();
8749    BB_then_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8750    BB_then_linear->kind |= block_kind_uniform;
8751    add_linear_edge(ic->BB_if_idx, BB_then_linear);
8752    /* branch from linear then block to invert block */
8753    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8754    BB_then_linear->instructions.emplace_back(std::move(branch));
8755    add_linear_edge(BB_then_linear->index, &ic->BB_invert);
8756
8757    /** emit invert merge block */
8758    ctx->block = ctx->program->insert_block(std::move(ic->BB_invert));
8759    ic->invert_idx = ctx->block->index;
8760
8761    /* branch to linear else block (skip else) */
8762    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_nz, Format::PSEUDO_BRANCH, 1, 0));
8763    branch->operands[0] = Operand(ic->cond);
8764    ctx->block->instructions.push_back(std::move(branch));
8765
8766    ic->exec_potentially_empty_discard_old |= ctx->cf_info.exec_potentially_empty_discard;
8767    ic->exec_potentially_empty_break_old |= ctx->cf_info.exec_potentially_empty_break;
8768    ic->exec_potentially_empty_break_depth_old =
8769       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8770    /* divergent branches use cbranch_execz */
8771    ctx->cf_info.exec_potentially_empty_discard = false;
8772    ctx->cf_info.exec_potentially_empty_break = false;
8773    ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8774
8775    /** emit logical else block */
8776    Block* BB_else_logical = ctx->program->create_and_insert_block();
8777    BB_else_logical->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8778    add_logical_edge(ic->BB_if_idx, BB_else_logical);
8779    add_linear_edge(ic->invert_idx, BB_else_logical);
8780    ctx->block = BB_else_logical;
8781    append_logical_start(BB_else_logical);
8782 }
8783
8784 static void end_divergent_if(isel_context *ctx, if_context *ic)
8785 {
8786    Block *BB_else_logical = ctx->block;
8787    append_logical_end(BB_else_logical);
8788
8789    /* branch from logical else block to endif block */
8790    aco_ptr<Pseudo_branch_instruction> branch;
8791    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8792    BB_else_logical->instructions.emplace_back(std::move(branch));
8793    add_linear_edge(BB_else_logical->index, &ic->BB_endif);
8794    if (!ctx->cf_info.parent_loop.has_divergent_branch)
8795       add_logical_edge(BB_else_logical->index, &ic->BB_endif);
8796    BB_else_logical->kind |= block_kind_uniform;
8797
8798    assert(!ctx->cf_info.has_branch);
8799    ctx->cf_info.parent_loop.has_divergent_branch &= ic->then_branch_divergent;
8800
8801
8802    /** emit linear else block */
8803    Block* BB_else_linear = ctx->program->create_and_insert_block();
8804    BB_else_linear->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8805    BB_else_linear->kind |= block_kind_uniform;
8806    add_linear_edge(ic->invert_idx, BB_else_linear);
8807
8808    /* branch from linear else block to endif block */
8809    branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8810    BB_else_linear->instructions.emplace_back(std::move(branch));
8811    add_linear_edge(BB_else_linear->index, &ic->BB_endif);
8812
8813
8814    /** emit endif merge block */
8815    ctx->block = ctx->program->insert_block(std::move(ic->BB_endif));
8816    append_logical_start(ctx->block);
8817
8818
8819    ctx->cf_info.parent_if.is_divergent = ic->divergent_old;
8820    ctx->cf_info.exec_potentially_empty_discard |= ic->exec_potentially_empty_discard_old;
8821    ctx->cf_info.exec_potentially_empty_break |= ic->exec_potentially_empty_break_old;
8822    ctx->cf_info.exec_potentially_empty_break_depth =
8823       std::min(ic->exec_potentially_empty_break_depth_old, ctx->cf_info.exec_potentially_empty_break_depth);
8824    if (ctx->cf_info.loop_nest_depth == ctx->cf_info.exec_potentially_empty_break_depth &&
8825        !ctx->cf_info.parent_if.is_divergent) {
8826       ctx->cf_info.exec_potentially_empty_break = false;
8827       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8828    }
8829    /* uniform control flow never has an empty exec-mask */
8830    if (!ctx->cf_info.loop_nest_depth && !ctx->cf_info.parent_if.is_divergent) {
8831       ctx->cf_info.exec_potentially_empty_discard = false;
8832       ctx->cf_info.exec_potentially_empty_break = false;
8833       ctx->cf_info.exec_potentially_empty_break_depth = UINT16_MAX;
8834    }
8835 }
8836
8837 static bool visit_if(isel_context *ctx, nir_if *if_stmt)
8838 {
8839    Temp cond = get_ssa_temp(ctx, if_stmt->condition.ssa);
8840    Builder bld(ctx->program, ctx->block);
8841    aco_ptr<Pseudo_branch_instruction> branch;
8842
8843    if (!ctx->divergent_vals[if_stmt->condition.ssa->index]) { /* uniform condition */
8844       /**
8845        * Uniform conditionals are represented in the following way*) :
8846        *
8847        * The linear and logical CFG:
8848        *                        BB_IF
8849        *                        /    \
8850        *       BB_THEN (logical)      BB_ELSE (logical)
8851        *                        \    /
8852        *                        BB_ENDIF
8853        *
8854        * *) Exceptions may be due to break and continue statements within loops
8855        *    If a break/continue happens within uniform control flow, it branches
8856        *    to the loop exit/entry block. Otherwise, it branches to the next
8857        *    merge block.
8858        **/
8859       append_logical_end(ctx->block);
8860       ctx->block->kind |= block_kind_uniform;
8861
8862       /* emit branch */
8863       assert(cond.regClass() == bld.lm);
8864       // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
8865       cond = bool_to_scalar_condition(ctx, cond);
8866
8867       branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_cbranch_z, Format::PSEUDO_BRANCH, 1, 0));
8868       branch->operands[0] = Operand(cond);
8869       branch->operands[0].setFixed(scc);
8870       ctx->block->instructions.emplace_back(std::move(branch));
8871
8872       unsigned BB_if_idx = ctx->block->index;
8873       Block BB_endif = Block();
8874       BB_endif.loop_nest_depth = ctx->cf_info.loop_nest_depth;
8875       BB_endif.kind |= ctx->block->kind & block_kind_top_level;
8876
8877       /** emit then block */
8878       Block* BB_then = ctx->program->create_and_insert_block();
8879       BB_then->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8880       add_edge(BB_if_idx, BB_then);
8881       append_logical_start(BB_then);
8882       ctx->block = BB_then;
8883       visit_cf_list(ctx, &if_stmt->then_list);
8884       BB_then = ctx->block;
8885       bool then_branch = ctx->cf_info.has_branch;
8886       bool then_branch_divergent = ctx->cf_info.parent_loop.has_divergent_branch;
8887
8888       if (!then_branch) {
8889          append_logical_end(BB_then);
8890          /* branch from then block to endif block */
8891          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8892          BB_then->instructions.emplace_back(std::move(branch));
8893          add_linear_edge(BB_then->index, &BB_endif);
8894          if (!then_branch_divergent)
8895             add_logical_edge(BB_then->index, &BB_endif);
8896          BB_then->kind |= block_kind_uniform;
8897       }
8898
8899       ctx->cf_info.has_branch = false;
8900       ctx->cf_info.parent_loop.has_divergent_branch = false;
8901
8902       /** emit else block */
8903       Block* BB_else = ctx->program->create_and_insert_block();
8904       BB_else->loop_nest_depth = ctx->cf_info.loop_nest_depth;
8905       add_edge(BB_if_idx, BB_else);
8906       append_logical_start(BB_else);
8907       ctx->block = BB_else;
8908       visit_cf_list(ctx, &if_stmt->else_list);
8909       BB_else = ctx->block;
8910
8911       if (!ctx->cf_info.has_branch) {
8912          append_logical_end(BB_else);
8913          /* branch from then block to endif block */
8914          branch.reset(create_instruction<Pseudo_branch_instruction>(aco_opcode::p_branch, Format::PSEUDO_BRANCH, 0, 0));
8915          BB_else->instructions.emplace_back(std::move(branch));
8916          add_linear_edge(BB_else->index, &BB_endif);
8917          if (!ctx->cf_info.parent_loop.has_divergent_branch)
8918             add_logical_edge(BB_else->index, &BB_endif);
8919          BB_else->kind |= block_kind_uniform;
8920       }
8921
8922       ctx->cf_info.has_branch &= then_branch;
8923       ctx->cf_info.parent_loop.has_divergent_branch &= then_branch_divergent;
8924
8925       /** emit endif merge block */
8926       if (!ctx->cf_info.has_branch) {
8927          ctx->block = ctx->program->insert_block(std::move(BB_endif));
8928          append_logical_start(ctx->block);
8929       }
8930       return !ctx->cf_info.has_branch;
8931    } else { /* non-uniform condition */
8932       /**
8933        * To maintain a logical and linear CFG without critical edges,
8934        * non-uniform conditionals are represented in the following way*) :
8935        *
8936        * The linear CFG:
8937        *                        BB_IF
8938        *                        /    \
8939        *       BB_THEN (logical)      BB_THEN (linear)
8940        *                        \    /
8941        *                        BB_INVERT (linear)
8942        *                        /    \
8943        *       BB_ELSE (logical)      BB_ELSE (linear)
8944        *                        \    /
8945        *                        BB_ENDIF
8946        *
8947        * The logical CFG:
8948        *                        BB_IF
8949        *                        /    \
8950        *       BB_THEN (logical)      BB_ELSE (logical)
8951        *                        \    /
8952        *                        BB_ENDIF
8953        *
8954        * *) Exceptions may be due to break and continue statements within loops
8955        **/
8956
8957       if_context ic;
8958
8959       begin_divergent_if_then(ctx, &ic, cond);
8960       visit_cf_list(ctx, &if_stmt->then_list);
8961
8962       begin_divergent_if_else(ctx, &ic);
8963       visit_cf_list(ctx, &if_stmt->else_list);
8964
8965       end_divergent_if(ctx, &ic);
8966
8967       return true;
8968    }
8969 }
8970
8971 static bool visit_cf_list(isel_context *ctx,
8972                           struct exec_list *list)
8973 {
8974    foreach_list_typed(nir_cf_node, node, node, list) {
8975       switch (node->type) {
8976       case nir_cf_node_block:
8977          visit_block(ctx, nir_cf_node_as_block(node));
8978          break;
8979       case nir_cf_node_if:
8980          if (!visit_if(ctx, nir_cf_node_as_if(node)))
8981             return true;
8982          break;
8983       case nir_cf_node_loop:
8984          visit_loop(ctx, nir_cf_node_as_loop(node));
8985          break;
8986       default:
8987          unreachable("unimplemented cf list type");
8988       }
8989    }
8990    return false;
8991 }
8992
8993 static void create_null_export(isel_context *ctx)
8994 {
8995    /* Some shader stages always need to have exports.
8996     * So when there is none, we need to add a null export.
8997     */
8998
8999    unsigned dest = (ctx->program->stage & hw_fs) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS;
9000    bool vm = (ctx->program->stage & hw_fs) || ctx->program->chip_class >= GFX10;
9001    Builder bld(ctx->program, ctx->block);
9002    bld.exp(aco_opcode::exp, Operand(v1), Operand(v1), Operand(v1), Operand(v1),
9003            /* enabled_mask */ 0, dest, /* compr */ false, /* done */ true, vm);
9004 }
9005
9006 static bool export_vs_varying(isel_context *ctx, int slot, bool is_pos, int *next_pos)
9007 {
9008    assert(ctx->stage == vertex_vs ||
9009           ctx->stage == tess_eval_vs ||
9010           ctx->stage == gs_copy_vs);
9011
9012    int offset = ctx->stage == tess_eval_vs
9013                 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
9014                 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
9015    uint64_t mask = ctx->outputs.mask[slot];
9016    if (!is_pos && !mask)
9017       return false;
9018    if (!is_pos && offset == AC_EXP_PARAM_UNDEFINED)
9019       return false;
9020    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9021    exp->enabled_mask = mask;
9022    for (unsigned i = 0; i < 4; ++i) {
9023       if (mask & (1 << i))
9024          exp->operands[i] = Operand(ctx->outputs.outputs[slot][i]);
9025       else
9026          exp->operands[i] = Operand(v1);
9027    }
9028    /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9029     * Setting valid_mask=1 prevents it and has no other effect.
9030     */
9031    exp->valid_mask = ctx->options->chip_class >= GFX10 && is_pos && *next_pos == 0;
9032    exp->done = false;
9033    exp->compressed = false;
9034    if (is_pos)
9035       exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9036    else
9037       exp->dest = V_008DFC_SQ_EXP_PARAM + offset;
9038    ctx->block->instructions.emplace_back(std::move(exp));
9039
9040    return true;
9041 }
9042
9043 static void export_vs_psiz_layer_viewport(isel_context *ctx, int *next_pos)
9044 {
9045    aco_ptr<Export_instruction> exp{create_instruction<Export_instruction>(aco_opcode::exp, Format::EXP, 4, 0)};
9046    exp->enabled_mask = 0;
9047    for (unsigned i = 0; i < 4; ++i)
9048       exp->operands[i] = Operand(v1);
9049    if (ctx->outputs.mask[VARYING_SLOT_PSIZ]) {
9050       exp->operands[0] = Operand(ctx->outputs.outputs[VARYING_SLOT_PSIZ][0]);
9051       exp->enabled_mask |= 0x1;
9052    }
9053    if (ctx->outputs.mask[VARYING_SLOT_LAYER]) {
9054       exp->operands[2] = Operand(ctx->outputs.outputs[VARYING_SLOT_LAYER][0]);
9055       exp->enabled_mask |= 0x4;
9056    }
9057    if (ctx->outputs.mask[VARYING_SLOT_VIEWPORT]) {
9058       if (ctx->options->chip_class < GFX9) {
9059          exp->operands[3] = Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]);
9060          exp->enabled_mask |= 0x8;
9061       } else {
9062          Builder bld(ctx->program, ctx->block);
9063
9064          Temp out = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u),
9065                              Operand(ctx->outputs.outputs[VARYING_SLOT_VIEWPORT][0]));
9066          if (exp->operands[2].isTemp())
9067             out = bld.vop2(aco_opcode::v_or_b32, bld.def(v1), Operand(out), exp->operands[2]);
9068
9069          exp->operands[2] = Operand(out);
9070          exp->enabled_mask |= 0x4;
9071       }
9072    }
9073    exp->valid_mask = ctx->options->chip_class >= GFX10 && *next_pos == 0;
9074    exp->done = false;
9075    exp->compressed = false;
9076    exp->dest = V_008DFC_SQ_EXP_POS + (*next_pos)++;
9077    ctx->block->instructions.emplace_back(std::move(exp));
9078 }
9079
9080 static void create_vs_exports(isel_context *ctx)
9081 {
9082    assert(ctx->stage == vertex_vs ||
9083           ctx->stage == tess_eval_vs ||
9084           ctx->stage == gs_copy_vs);
9085
9086    radv_vs_output_info *outinfo = ctx->stage == tess_eval_vs
9087                                   ? &ctx->program->info->tes.outinfo
9088                                   : &ctx->program->info->vs.outinfo;
9089
9090    if (outinfo->export_prim_id) {
9091       ctx->outputs.mask[VARYING_SLOT_PRIMITIVE_ID] |= 0x1;
9092       ctx->outputs.outputs[VARYING_SLOT_PRIMITIVE_ID][0] = get_arg(ctx, ctx->args->vs_prim_id);
9093    }
9094
9095    if (ctx->options->key.has_multiview_view_index) {
9096       ctx->outputs.mask[VARYING_SLOT_LAYER] |= 0x1;
9097       ctx->outputs.outputs[VARYING_SLOT_LAYER][0] = as_vgpr(ctx, get_arg(ctx, ctx->args->ac.view_index));
9098    }
9099
9100    /* the order these position exports are created is important */
9101    int next_pos = 0;
9102    bool exported_pos = export_vs_varying(ctx, VARYING_SLOT_POS, true, &next_pos);
9103    if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) {
9104       export_vs_psiz_layer_viewport(ctx, &next_pos);
9105       exported_pos = true;
9106    }
9107    if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9108       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, true, &next_pos);
9109    if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9110       exported_pos |= export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, true, &next_pos);
9111
9112    if (ctx->export_clip_dists) {
9113       if (ctx->num_clip_distances + ctx->num_cull_distances > 0)
9114          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST0, false, &next_pos);
9115       if (ctx->num_clip_distances + ctx->num_cull_distances > 4)
9116          export_vs_varying(ctx, VARYING_SLOT_CLIP_DIST1, false, &next_pos);
9117    }
9118
9119    for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9120       if (i < VARYING_SLOT_VAR0 && i != VARYING_SLOT_LAYER &&
9121           i != VARYING_SLOT_PRIMITIVE_ID)
9122          continue;
9123
9124       export_vs_varying(ctx, i, false, NULL);
9125    }
9126
9127    if (!exported_pos)
9128       create_null_export(ctx);
9129 }
9130
9131 static bool export_fs_mrt_z(isel_context *ctx)
9132 {
9133    Builder bld(ctx->program, ctx->block);
9134    unsigned enabled_channels = 0;
9135    bool compr = false;
9136    Operand values[4];
9137
9138    for (unsigned i = 0; i < 4; ++i) {
9139       values[i] = Operand(v1);
9140    }
9141
9142    /* Both stencil and sample mask only need 16-bits. */
9143    if (!ctx->program->info->ps.writes_z &&
9144        (ctx->program->info->ps.writes_stencil ||
9145         ctx->program->info->ps.writes_sample_mask)) {
9146       compr = true; /* COMPR flag */
9147
9148       if (ctx->program->info->ps.writes_stencil) {
9149          /* Stencil should be in X[23:16]. */
9150          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9151          values[0] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(16u), values[0]);
9152          enabled_channels |= 0x3;
9153       }
9154
9155       if (ctx->program->info->ps.writes_sample_mask) {
9156          /* SampleMask should be in Y[15:0]. */
9157          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9158          enabled_channels |= 0xc;
9159      }
9160    } else {
9161       if (ctx->program->info->ps.writes_z) {
9162          values[0] = Operand(ctx->outputs.outputs[FRAG_RESULT_DEPTH][0]);
9163          enabled_channels |= 0x1;
9164       }
9165
9166       if (ctx->program->info->ps.writes_stencil) {
9167          values[1] = Operand(ctx->outputs.outputs[FRAG_RESULT_STENCIL][0]);
9168          enabled_channels |= 0x2;
9169       }
9170
9171       if (ctx->program->info->ps.writes_sample_mask) {
9172          values[2] = Operand(ctx->outputs.outputs[FRAG_RESULT_SAMPLE_MASK][0]);
9173          enabled_channels |= 0x4;
9174       }
9175    }
9176
9177    /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9178     * writemask component.
9179     */
9180    if (ctx->options->chip_class == GFX6 &&
9181        ctx->options->family != CHIP_OLAND &&
9182        ctx->options->family != CHIP_HAINAN) {
9183             enabled_channels |= 0x1;
9184    }
9185
9186    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9187            enabled_channels, V_008DFC_SQ_EXP_MRTZ, compr);
9188
9189    return true;
9190 }
9191
9192 static bool export_fs_mrt_color(isel_context *ctx, int slot)
9193 {
9194    Builder bld(ctx->program, ctx->block);
9195    unsigned write_mask = ctx->outputs.mask[slot];
9196    Operand values[4];
9197
9198    for (unsigned i = 0; i < 4; ++i) {
9199       if (write_mask & (1 << i)) {
9200          values[i] = Operand(ctx->outputs.outputs[slot][i]);
9201       } else {
9202          values[i] = Operand(v1);
9203       }
9204    }
9205
9206    unsigned target, col_format;
9207    unsigned enabled_channels = 0;
9208    aco_opcode compr_op = (aco_opcode)0;
9209
9210    slot -= FRAG_RESULT_DATA0;
9211    target = V_008DFC_SQ_EXP_MRT + slot;
9212    col_format = (ctx->options->key.fs.col_format >> (4 * slot)) & 0xf;
9213
9214    bool is_int8 = (ctx->options->key.fs.is_int8 >> slot) & 1;
9215    bool is_int10 = (ctx->options->key.fs.is_int10 >> slot) & 1;
9216
9217    switch (col_format)
9218    {
9219    case V_028714_SPI_SHADER_ZERO:
9220       enabled_channels = 0; /* writemask */
9221       target = V_008DFC_SQ_EXP_NULL;
9222       break;
9223
9224    case V_028714_SPI_SHADER_32_R:
9225       enabled_channels = 1;
9226       break;
9227
9228    case V_028714_SPI_SHADER_32_GR:
9229       enabled_channels = 0x3;
9230       break;
9231
9232    case V_028714_SPI_SHADER_32_AR:
9233       if (ctx->options->chip_class >= GFX10) {
9234          /* Special case: on GFX10, the outputs are different for 32_AR */
9235          enabled_channels = 0x3;
9236          values[1] = values[3];
9237          values[3] = Operand(v1);
9238       } else {
9239          enabled_channels = 0x9;
9240       }
9241       break;
9242
9243    case V_028714_SPI_SHADER_FP16_ABGR:
9244       enabled_channels = 0x5;
9245       compr_op = aco_opcode::v_cvt_pkrtz_f16_f32;
9246       break;
9247
9248    case V_028714_SPI_SHADER_UNORM16_ABGR:
9249       enabled_channels = 0x5;
9250       compr_op = aco_opcode::v_cvt_pknorm_u16_f32;
9251       break;
9252
9253    case V_028714_SPI_SHADER_SNORM16_ABGR:
9254       enabled_channels = 0x5;
9255       compr_op = aco_opcode::v_cvt_pknorm_i16_f32;
9256       break;
9257
9258    case V_028714_SPI_SHADER_UINT16_ABGR: {
9259       enabled_channels = 0x5;
9260       compr_op = aco_opcode::v_cvt_pk_u16_u32;
9261       if (is_int8 || is_int10) {
9262          /* clamp */
9263          uint32_t max_rgb = is_int8 ? 255 : is_int10 ? 1023 : 0;
9264          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9265
9266          for (unsigned i = 0; i < 4; i++) {
9267             if ((write_mask >> i) & 1) {
9268                values[i] = bld.vop2(aco_opcode::v_min_u32, bld.def(v1),
9269                                     i == 3 && is_int10 ? Operand(3u) : Operand(max_rgb_val),
9270                                     values[i]);
9271             }
9272          }
9273       }
9274       break;
9275    }
9276
9277    case V_028714_SPI_SHADER_SINT16_ABGR:
9278       enabled_channels = 0x5;
9279       compr_op = aco_opcode::v_cvt_pk_i16_i32;
9280       if (is_int8 || is_int10) {
9281          /* clamp */
9282          uint32_t max_rgb = is_int8 ? 127 : is_int10 ? 511 : 0;
9283          uint32_t min_rgb = is_int8 ? -128 :is_int10 ? -512 : 0;
9284          Temp max_rgb_val = bld.copy(bld.def(s1), Operand(max_rgb));
9285          Temp min_rgb_val = bld.copy(bld.def(s1), Operand(min_rgb));
9286
9287          for (unsigned i = 0; i < 4; i++) {
9288             if ((write_mask >> i) & 1) {
9289                values[i] = bld.vop2(aco_opcode::v_min_i32, bld.def(v1),
9290                                     i == 3 && is_int10 ? Operand(1u) : Operand(max_rgb_val),
9291                                     values[i]);
9292                values[i] = bld.vop2(aco_opcode::v_max_i32, bld.def(v1),
9293                                     i == 3 && is_int10 ? Operand(-2u) : Operand(min_rgb_val),
9294                                     values[i]);
9295             }
9296          }
9297       }
9298       break;
9299
9300    case V_028714_SPI_SHADER_32_ABGR:
9301       enabled_channels = 0xF;
9302       break;
9303
9304    default:
9305       break;
9306    }
9307
9308    if (target == V_008DFC_SQ_EXP_NULL)
9309       return false;
9310
9311    if ((bool) compr_op) {
9312       for (int i = 0; i < 2; i++) {
9313          /* check if at least one of the values to be compressed is enabled */
9314          unsigned enabled = (write_mask >> (i*2) | write_mask >> (i*2+1)) & 0x1;
9315          if (enabled) {
9316             enabled_channels |= enabled << (i*2);
9317             values[i] = bld.vop3(compr_op, bld.def(v1),
9318                                  values[i*2].isUndefined() ? Operand(0u) : values[i*2],
9319                                  values[i*2+1].isUndefined() ? Operand(0u): values[i*2+1]);
9320          } else {
9321             values[i] = Operand(v1);
9322          }
9323       }
9324       values[2] = Operand(v1);
9325       values[3] = Operand(v1);
9326    } else {
9327       for (int i = 0; i < 4; i++)
9328          values[i] = enabled_channels & (1 << i) ? values[i] : Operand(v1);
9329    }
9330
9331    bld.exp(aco_opcode::exp, values[0], values[1], values[2], values[3],
9332            enabled_channels, target, (bool) compr_op);
9333    return true;
9334 }
9335
9336 static void create_fs_exports(isel_context *ctx)
9337 {
9338    bool exported = false;
9339
9340    /* Export depth, stencil and sample mask. */
9341    if (ctx->outputs.mask[FRAG_RESULT_DEPTH] ||
9342        ctx->outputs.mask[FRAG_RESULT_STENCIL] ||
9343        ctx->outputs.mask[FRAG_RESULT_SAMPLE_MASK])
9344       exported |= export_fs_mrt_z(ctx);
9345
9346    /* Export all color render targets. */
9347    for (unsigned i = FRAG_RESULT_DATA0; i < FRAG_RESULT_DATA7 + 1; ++i)
9348       if (ctx->outputs.mask[i])
9349          exported |= export_fs_mrt_color(ctx, i);
9350
9351    if (!exported)
9352       create_null_export(ctx);
9353 }
9354
9355 static void write_tcs_tess_factors(isel_context *ctx)
9356 {
9357    unsigned outer_comps;
9358    unsigned inner_comps;
9359
9360    switch (ctx->args->options->key.tcs.primitive_mode) {
9361    case GL_ISOLINES:
9362       outer_comps = 2;
9363       inner_comps = 0;
9364       break;
9365    case GL_TRIANGLES:
9366       outer_comps = 3;
9367       inner_comps = 1;
9368       break;
9369    case GL_QUADS:
9370       outer_comps = 4;
9371       inner_comps = 2;
9372       break;
9373    default:
9374       return;
9375    }
9376
9377    const unsigned tess_index_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
9378    const unsigned tess_index_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
9379
9380    Builder bld(ctx->program, ctx->block);
9381
9382    bld.barrier(aco_opcode::p_memory_barrier_shared);
9383    unsigned workgroup_size = ctx->tcs_num_patches * ctx->shader->info.tess.tcs_vertices_out;
9384    if (unlikely(ctx->program->chip_class != GFX6 && workgroup_size > ctx->program->wave_size))
9385       bld.sopp(aco_opcode::s_barrier);
9386
9387    Temp tcs_rel_ids = get_arg(ctx, ctx->args->ac.tcs_rel_ids);
9388    Temp invocation_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1), tcs_rel_ids, Operand(8u), Operand(5u));
9389
9390    Temp invocation_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), invocation_id);
9391    if_context ic_invocation_id_is_zero;
9392    begin_divergent_if_then(ctx, &ic_invocation_id_is_zero, invocation_id_is_zero);
9393    bld.reset(ctx->block);
9394
9395    Temp hs_ring_tess_factor = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_FACTOR * 16u));
9396
9397    std::pair<Temp, unsigned> lds_base = get_tcs_output_lds_offset(ctx);
9398    unsigned stride = inner_comps + outer_comps;
9399    Temp inner[4];
9400    Temp outer[4];
9401    Temp out[6];
9402    assert(inner_comps <= (sizeof(inner) / sizeof(Temp)));
9403    assert(outer_comps <= (sizeof(outer) / sizeof(Temp)));
9404    assert(stride <= (sizeof(out) / sizeof(Temp)));
9405
9406    if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
9407       // LINES reversal
9408       outer[0] = out[1] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 0 * 4, 4);
9409       outer[1] = out[0] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + 1 * 4, 4);
9410    } else {
9411       for (unsigned i = 0; i < outer_comps; ++i)
9412          outer[i] = out[i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_outer * 16 + i * 4, 4);
9413
9414       for (unsigned i = 0; i < inner_comps; ++i)
9415          inner[i] = out[outer_comps + i] = load_lds(ctx, 4, bld.tmp(v1), lds_base.first, lds_base.second + tess_index_inner * 16 + i * 4, 4);
9416    }
9417
9418    Temp rel_patch_id = get_tess_rel_patch_id(ctx);
9419    Temp tf_base = get_arg(ctx, ctx->args->tess_factor_offset);
9420    Temp byte_offset = bld.v_mul_imm(bld.def(v1), rel_patch_id, stride * 4u);
9421    unsigned tf_const_offset = 0;
9422
9423    if (ctx->program->chip_class <= GFX8) {
9424       Temp rel_patch_id_is_zero = bld.vopc(aco_opcode::v_cmp_eq_u32, bld.hint_vcc(bld.def(bld.lm)), Operand(0u), rel_patch_id);
9425       if_context ic_rel_patch_id_is_zero;
9426       begin_divergent_if_then(ctx, &ic_rel_patch_id_is_zero, rel_patch_id_is_zero);
9427       bld.reset(ctx->block);
9428
9429       /* Store the dynamic HS control word. */
9430       Temp control_word = bld.copy(bld.def(v1), Operand(0x80000000u));
9431       bld.mubuf(aco_opcode::buffer_store_dword,
9432                 /* SRSRC */ hs_ring_tess_factor, /* VADDR */ Operand(v1), /* SOFFSET */ tf_base, /* VDATA */ control_word,
9433                 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
9434                 /* disable_wqm */ false, /* glc */ true);
9435       tf_const_offset += 4;
9436
9437       begin_divergent_if_else(ctx, &ic_rel_patch_id_is_zero);
9438       end_divergent_if(ctx, &ic_rel_patch_id_is_zero);
9439       bld.reset(ctx->block);
9440    }
9441
9442    assert(stride == 2 || stride == 4 || stride == 6);
9443    Temp tf_vec = create_vec_from_array(ctx, out, stride, RegType::vgpr);
9444    store_vmem_mubuf(ctx, tf_vec, hs_ring_tess_factor, byte_offset, tf_base, tf_const_offset, 4, (1 << stride) - 1, true, false);
9445
9446    /* Store to offchip for TES to read - only if TES reads them */
9447    if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
9448       Temp hs_ring_tess_offchip = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), ctx->program->private_segment_buffer, Operand(RING_HS_TESS_OFFCHIP * 16u));
9449       Temp oc_lds = get_arg(ctx, ctx->args->oc_lds);
9450
9451       std::pair<Temp, unsigned> vmem_offs_outer = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_outer * 16);
9452       Temp outer_vec = create_vec_from_array(ctx, outer, outer_comps, RegType::vgpr);
9453       store_vmem_mubuf(ctx, outer_vec, hs_ring_tess_offchip, vmem_offs_outer.first, oc_lds, vmem_offs_outer.second, 4, (1 << outer_comps) - 1, true, false);
9454
9455       if (likely(inner_comps)) {
9456          std::pair<Temp, unsigned> vmem_offs_inner = get_tcs_per_patch_output_vmem_offset(ctx, nullptr, tess_index_inner * 16);
9457          Temp inner_vec = create_vec_from_array(ctx, inner, inner_comps, RegType::vgpr);
9458          store_vmem_mubuf(ctx, inner_vec, hs_ring_tess_offchip, vmem_offs_inner.first, oc_lds, vmem_offs_inner.second, 4, (1 << inner_comps) - 1, true, false);
9459       }
9460    }
9461
9462    begin_divergent_if_else(ctx, &ic_invocation_id_is_zero);
9463    end_divergent_if(ctx, &ic_invocation_id_is_zero);
9464 }
9465
9466 static void emit_stream_output(isel_context *ctx,
9467                                Temp const *so_buffers,
9468                                Temp const *so_write_offset,
9469                                const struct radv_stream_output *output)
9470 {
9471    unsigned num_comps = util_bitcount(output->component_mask);
9472    unsigned writemask = (1 << num_comps) - 1;
9473    unsigned loc = output->location;
9474    unsigned buf = output->buffer;
9475
9476    assert(num_comps && num_comps <= 4);
9477    if (!num_comps || num_comps > 4)
9478       return;
9479
9480    unsigned start = ffs(output->component_mask) - 1;
9481
9482    Temp out[4];
9483    bool all_undef = true;
9484    assert(ctx->stage == vertex_vs || ctx->stage == gs_copy_vs);
9485    for (unsigned i = 0; i < num_comps; i++) {
9486       out[i] = ctx->outputs.outputs[loc][start + i];
9487       all_undef = all_undef && !out[i].id();
9488    }
9489    if (all_undef)
9490       return;
9491
9492    while (writemask) {
9493       int start, count;
9494       u_bit_scan_consecutive_range(&writemask, &start, &count);
9495       if (count == 3 && ctx->options->chip_class == GFX6) {
9496          /* GFX6 doesn't support storing vec3, split it. */
9497          writemask |= 1u << (start + 2);
9498          count = 2;
9499       }
9500
9501       unsigned offset = output->offset + start * 4;
9502
9503       Temp write_data = {ctx->program->allocateId(), RegClass(RegType::vgpr, count)};
9504       aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, count, 1)};
9505       for (int i = 0; i < count; ++i)
9506          vec->operands[i] = (ctx->outputs.mask[loc] & 1 << (start + i)) ? Operand(out[start + i]) : Operand(0u);
9507       vec->definitions[0] = Definition(write_data);
9508       ctx->block->instructions.emplace_back(std::move(vec));
9509
9510       aco_opcode opcode;
9511       switch (count) {
9512       case 1:
9513          opcode = aco_opcode::buffer_store_dword;
9514          break;
9515       case 2:
9516          opcode = aco_opcode::buffer_store_dwordx2;
9517          break;
9518       case 3:
9519          opcode = aco_opcode::buffer_store_dwordx3;
9520          break;
9521       case 4:
9522          opcode = aco_opcode::buffer_store_dwordx4;
9523          break;
9524       default:
9525          unreachable("Unsupported dword count.");
9526       }
9527
9528       aco_ptr<MUBUF_instruction> store{create_instruction<MUBUF_instruction>(opcode, Format::MUBUF, 4, 0)};
9529       store->operands[0] = Operand(so_buffers[buf]);
9530       store->operands[1] = Operand(so_write_offset[buf]);
9531       store->operands[2] = Operand((uint32_t) 0);
9532       store->operands[3] = Operand(write_data);
9533       if (offset > 4095) {
9534          /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
9535          Builder bld(ctx->program, ctx->block);
9536          store->operands[0] = bld.vadd32(bld.def(v1), Operand(offset), Operand(so_write_offset[buf]));
9537       } else {
9538          store->offset = offset;
9539       }
9540       store->offen = true;
9541       store->glc = true;
9542       store->dlc = false;
9543       store->slc = true;
9544       store->can_reorder = true;
9545       ctx->block->instructions.emplace_back(std::move(store));
9546    }
9547 }
9548
9549 static void emit_streamout(isel_context *ctx, unsigned stream)
9550 {
9551    Builder bld(ctx->program, ctx->block);
9552
9553    Temp so_buffers[4];
9554    Temp buf_ptr = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->streamout_buffers));
9555    for (unsigned i = 0; i < 4; i++) {
9556       unsigned stride = ctx->program->info->so.strides[i];
9557       if (!stride)
9558          continue;
9559
9560       Operand off = bld.copy(bld.def(s1), Operand(i * 16u));
9561       so_buffers[i] = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), buf_ptr, off);
9562    }
9563
9564    Temp so_vtx_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9565                                 get_arg(ctx, ctx->args->streamout_config), Operand(0x70010u));
9566
9567    Temp tid = emit_mbcnt(ctx, bld.def(v1));
9568
9569    Temp can_emit = bld.vopc(aco_opcode::v_cmp_gt_i32, bld.def(bld.lm), so_vtx_count, tid);
9570
9571    if_context ic;
9572    begin_divergent_if_then(ctx, &ic, can_emit);
9573
9574    bld.reset(ctx->block);
9575
9576    Temp so_write_index = bld.vadd32(bld.def(v1), get_arg(ctx, ctx->args->streamout_write_idx), tid);
9577
9578    Temp so_write_offset[4];
9579
9580    for (unsigned i = 0; i < 4; i++) {
9581       unsigned stride = ctx->program->info->so.strides[i];
9582       if (!stride)
9583          continue;
9584
9585       if (stride == 1) {
9586          Temp offset = bld.sop2(aco_opcode::s_add_i32, bld.def(s1), bld.def(s1, scc),
9587                                 get_arg(ctx, ctx->args->streamout_write_idx),
9588                                 get_arg(ctx, ctx->args->streamout_offset[i]));
9589          Temp new_offset = bld.vadd32(bld.def(v1), offset, tid);
9590
9591          so_write_offset[i] = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), new_offset);
9592       } else {
9593          Temp offset = bld.v_mul_imm(bld.def(v1), so_write_index, stride * 4u);
9594          Temp offset2 = bld.sop2(aco_opcode::s_mul_i32, bld.def(s1), Operand(4u),
9595                                  get_arg(ctx, ctx->args->streamout_offset[i]));
9596          so_write_offset[i] = bld.vadd32(bld.def(v1), offset, offset2);
9597       }
9598    }
9599
9600    for (unsigned i = 0; i < ctx->program->info->so.num_outputs; i++) {
9601       struct radv_stream_output *output =
9602          &ctx->program->info->so.outputs[i];
9603       if (stream != output->stream)
9604          continue;
9605
9606       emit_stream_output(ctx, so_buffers, so_write_offset, output);
9607    }
9608
9609    begin_divergent_if_else(ctx, &ic);
9610    end_divergent_if(ctx, &ic);
9611 }
9612
9613 } /* end namespace */
9614
9615 void fix_ls_vgpr_init_bug(isel_context *ctx, Pseudo_instruction *startpgm)
9616 {
9617    assert(ctx->shader->info.stage == MESA_SHADER_VERTEX);
9618    Builder bld(ctx->program, ctx->block);
9619    constexpr unsigned hs_idx = 1u;
9620    Builder::Result hs_thread_count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9621                                               get_arg(ctx, ctx->args->merged_wave_info),
9622                                               Operand((8u << 16) | (hs_idx * 8u)));
9623    Temp ls_has_nonzero_hs_threads = bool_to_vector_condition(ctx, hs_thread_count.def(1).getTemp());
9624
9625    /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
9626
9627    Temp instance_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9628                                get_arg(ctx, ctx->args->rel_auto_id),
9629                                get_arg(ctx, ctx->args->ac.instance_id),
9630                                ls_has_nonzero_hs_threads);
9631    Temp rel_auto_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9632                                get_arg(ctx, ctx->args->ac.tcs_rel_ids),
9633                                get_arg(ctx, ctx->args->rel_auto_id),
9634                                ls_has_nonzero_hs_threads);
9635    Temp vertex_id = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9636                              get_arg(ctx, ctx->args->ac.tcs_patch_id),
9637                              get_arg(ctx, ctx->args->ac.vertex_id),
9638                              ls_has_nonzero_hs_threads);
9639
9640    ctx->arg_temps[ctx->args->ac.instance_id.arg_index] = instance_id;
9641    ctx->arg_temps[ctx->args->rel_auto_id.arg_index] = rel_auto_id;
9642    ctx->arg_temps[ctx->args->ac.vertex_id.arg_index] = vertex_id;
9643 }
9644
9645 void split_arguments(isel_context *ctx, Pseudo_instruction *startpgm)
9646 {
9647    /* Split all arguments except for the first (ring_offsets) and the last
9648     * (exec) so that the dead channels don't stay live throughout the program.
9649     */
9650    for (int i = 1; i < startpgm->definitions.size() - 1; i++) {
9651       if (startpgm->definitions[i].regClass().size() > 1) {
9652          emit_split_vector(ctx, startpgm->definitions[i].getTemp(),
9653                            startpgm->definitions[i].regClass().size());
9654       }
9655    }
9656 }
9657
9658 void handle_bc_optimize(isel_context *ctx)
9659 {
9660    /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
9661    Builder bld(ctx->program, ctx->block);
9662    uint32_t spi_ps_input_ena = ctx->program->config->spi_ps_input_ena;
9663    bool uses_center = G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena);
9664    bool uses_centroid = G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena);
9665    ctx->persp_centroid = get_arg(ctx, ctx->args->ac.persp_centroid);
9666    ctx->linear_centroid = get_arg(ctx, ctx->args->ac.linear_centroid);
9667    if (uses_center && uses_centroid) {
9668       Temp sel = bld.vopc_e64(aco_opcode::v_cmp_lt_i32, bld.hint_vcc(bld.def(bld.lm)),
9669                               get_arg(ctx, ctx->args->ac.prim_mask), Operand(0u));
9670
9671       if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena)) {
9672          Temp new_coord[2];
9673          for (unsigned i = 0; i < 2; i++) {
9674             Temp persp_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_centroid), i, v1);
9675             Temp persp_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.persp_center), i, v1);
9676             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9677                                     persp_centroid, persp_center, sel);
9678          }
9679          ctx->persp_centroid = bld.tmp(v2);
9680          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->persp_centroid),
9681                     Operand(new_coord[0]), Operand(new_coord[1]));
9682          emit_split_vector(ctx, ctx->persp_centroid, 2);
9683       }
9684
9685       if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena)) {
9686          Temp new_coord[2];
9687          for (unsigned i = 0; i < 2; i++) {
9688             Temp linear_centroid = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_centroid), i, v1);
9689             Temp linear_center = emit_extract_vector(ctx, get_arg(ctx, ctx->args->ac.linear_center), i, v1);
9690             new_coord[i] = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1),
9691                                     linear_centroid, linear_center, sel);
9692          }
9693          ctx->linear_centroid = bld.tmp(v2);
9694          bld.pseudo(aco_opcode::p_create_vector, Definition(ctx->linear_centroid),
9695                     Operand(new_coord[0]), Operand(new_coord[1]));
9696          emit_split_vector(ctx, ctx->linear_centroid, 2);
9697       }
9698    }
9699 }
9700
9701 void setup_fp_mode(isel_context *ctx, nir_shader *shader)
9702 {
9703    Program *program = ctx->program;
9704
9705    unsigned float_controls = shader->info.float_controls_execution_mode;
9706
9707    program->next_fp_mode.preserve_signed_zero_inf_nan32 =
9708       float_controls & FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32;
9709    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 =
9710       float_controls & (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16 |
9711                         FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64);
9712
9713    program->next_fp_mode.must_flush_denorms32 =
9714       float_controls & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32;
9715    program->next_fp_mode.must_flush_denorms16_64 =
9716       float_controls & (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 |
9717                         FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64);
9718
9719    program->next_fp_mode.care_about_round32 =
9720       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32);
9721
9722    program->next_fp_mode.care_about_round16_64 =
9723       float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64 |
9724                         FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64);
9725
9726    /* default to preserving fp16 and fp64 denorms, since it's free */
9727    if (program->next_fp_mode.must_flush_denorms16_64)
9728       program->next_fp_mode.denorm16_64 = 0;
9729    else
9730       program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9731
9732    /* preserving fp32 denorms is expensive, so only do it if asked */
9733    if (float_controls & FLOAT_CONTROLS_DENORM_PRESERVE_FP32)
9734       program->next_fp_mode.denorm32 = fp_denorm_keep;
9735    else
9736       program->next_fp_mode.denorm32 = 0;
9737
9738    if (float_controls & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32)
9739       program->next_fp_mode.round32 = fp_round_tz;
9740    else
9741       program->next_fp_mode.round32 = fp_round_ne;
9742
9743    if (float_controls & (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16 | FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64))
9744       program->next_fp_mode.round16_64 = fp_round_tz;
9745    else
9746       program->next_fp_mode.round16_64 = fp_round_ne;
9747
9748    ctx->block->fp_mode = program->next_fp_mode;
9749 }
9750
9751 void cleanup_cfg(Program *program)
9752 {
9753    /* create linear_succs/logical_succs */
9754    for (Block& BB : program->blocks) {
9755       for (unsigned idx : BB.linear_preds)
9756          program->blocks[idx].linear_succs.emplace_back(BB.index);
9757       for (unsigned idx : BB.logical_preds)
9758          program->blocks[idx].logical_succs.emplace_back(BB.index);
9759    }
9760 }
9761
9762 void select_program(Program *program,
9763                     unsigned shader_count,
9764                     struct nir_shader *const *shaders,
9765                     ac_shader_config* config,
9766                     struct radv_shader_args *args)
9767 {
9768    isel_context ctx = setup_isel_context(program, shader_count, shaders, config, args, false);
9769
9770    for (unsigned i = 0; i < shader_count; i++) {
9771       nir_shader *nir = shaders[i];
9772       init_context(&ctx, nir);
9773
9774       setup_fp_mode(&ctx, nir);
9775
9776       if (!i) {
9777          /* needs to be after init_context() for FS */
9778          Pseudo_instruction *startpgm = add_startpgm(&ctx);
9779          append_logical_start(ctx.block);
9780
9781          if (unlikely(args->options->has_ls_vgpr_init_bug && ctx.stage == vertex_tess_control_hs))
9782             fix_ls_vgpr_init_bug(&ctx, startpgm);
9783
9784          split_arguments(&ctx, startpgm);
9785       }
9786
9787       /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
9788       nir_function_impl *func = nir_shader_get_entrypoint(nir);
9789       bool empty_shader = nir_cf_list_is_empty_block(&func->body) &&
9790                           ((nir->info.stage == MESA_SHADER_VERTEX &&
9791                             (ctx.stage == vertex_tess_control_hs || ctx.stage == vertex_geometry_gs)) ||
9792                            (nir->info.stage == MESA_SHADER_TESS_EVAL &&
9793                             ctx.stage == tess_eval_geometry_gs));
9794
9795       if_context ic;
9796       if (shader_count >= 2 && !empty_shader) {
9797          Builder bld(ctx.program, ctx.block);
9798          Temp count = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | (i * 8u)));
9799          Temp thread_id = emit_mbcnt(&ctx, bld.def(v1));
9800          Temp cond = bld.vopc(aco_opcode::v_cmp_gt_u32, bld.hint_vcc(bld.def(bld.lm)), count, thread_id);
9801
9802          begin_divergent_if_then(&ctx, &ic, cond);
9803       }
9804
9805       if (i) {
9806          Builder bld(ctx.program, ctx.block);
9807
9808          bld.barrier(aco_opcode::p_memory_barrier_shared);
9809          bld.sopp(aco_opcode::s_barrier);
9810
9811          if (ctx.stage == vertex_geometry_gs || ctx.stage == tess_eval_geometry_gs) {
9812             ctx.gs_wave_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1, m0), bld.def(s1, scc), get_arg(&ctx, args->merged_wave_info), Operand((8u << 16) | 16u));
9813          }
9814       } else if (ctx.stage == geometry_gs)
9815          ctx.gs_wave_id = get_arg(&ctx, args->gs_wave_id);
9816
9817       if (ctx.stage == fragment_fs)
9818          handle_bc_optimize(&ctx);
9819
9820       visit_cf_list(&ctx, &func->body);
9821
9822       if (ctx.program->info->so.num_outputs && (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs))
9823          emit_streamout(&ctx, 0);
9824
9825       if (ctx.stage == vertex_vs || ctx.stage == tess_eval_vs) {
9826          create_vs_exports(&ctx);
9827       } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
9828          Builder bld(ctx.program, ctx.block);
9829          bld.barrier(aco_opcode::p_memory_barrier_gs_data);
9830          bld.sopp(aco_opcode::s_sendmsg, bld.m0(ctx.gs_wave_id), -1, sendmsg_gs_done(false, false, 0));
9831       } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
9832          write_tcs_tess_factors(&ctx);
9833       }
9834
9835       if (ctx.stage == fragment_fs)
9836          create_fs_exports(&ctx);
9837
9838       if (shader_count >= 2 && !empty_shader) {
9839          begin_divergent_if_else(&ctx, &ic);
9840          end_divergent_if(&ctx, &ic);
9841       }
9842
9843       ralloc_free(ctx.divergent_vals);
9844    }
9845
9846    program->config->float_mode = program->blocks[0].fp_mode.val;
9847
9848    append_logical_end(ctx.block);
9849    ctx.block->kind |= block_kind_uniform | block_kind_export_end;
9850    Builder bld(ctx.program, ctx.block);
9851    if (ctx.program->wb_smem_l1_on_end)
9852       bld.smem(aco_opcode::s_dcache_wb, false);
9853    bld.sopp(aco_opcode::s_endpgm);
9854
9855    cleanup_cfg(program);
9856 }
9857
9858 void select_gs_copy_shader(Program *program, struct nir_shader *gs_shader,
9859                            ac_shader_config* config,
9860                            struct radv_shader_args *args)
9861 {
9862    isel_context ctx = setup_isel_context(program, 1, &gs_shader, config, args, true);
9863
9864    program->next_fp_mode.preserve_signed_zero_inf_nan32 = false;
9865    program->next_fp_mode.preserve_signed_zero_inf_nan16_64 = false;
9866    program->next_fp_mode.must_flush_denorms32 = false;
9867    program->next_fp_mode.must_flush_denorms16_64 = false;
9868    program->next_fp_mode.care_about_round32 = false;
9869    program->next_fp_mode.care_about_round16_64 = false;
9870    program->next_fp_mode.denorm16_64 = fp_denorm_keep;
9871    program->next_fp_mode.denorm32 = 0;
9872    program->next_fp_mode.round32 = fp_round_ne;
9873    program->next_fp_mode.round16_64 = fp_round_ne;
9874    ctx.block->fp_mode = program->next_fp_mode;
9875
9876    add_startpgm(&ctx);
9877    append_logical_start(ctx.block);
9878
9879    Builder bld(ctx.program, ctx.block);
9880
9881    Temp gsvs_ring = bld.smem(aco_opcode::s_load_dwordx4, bld.def(s4), program->private_segment_buffer, Operand(RING_GSVS_VS * 16u));
9882
9883    Operand stream_id(0u);
9884    if (args->shader_info->so.num_outputs)
9885       stream_id = bld.sop2(aco_opcode::s_bfe_u32, bld.def(s1), bld.def(s1, scc),
9886                            get_arg(&ctx, ctx.args->streamout_config), Operand(0x20018u));
9887
9888    Temp vtx_offset = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(2u), get_arg(&ctx, ctx.args->ac.vertex_id));
9889
9890    std::stack<Block> endif_blocks;
9891
9892    for (unsigned stream = 0; stream < 4; stream++) {
9893       if (stream_id.isConstant() && stream != stream_id.constantValue())
9894          continue;
9895
9896       unsigned num_components = args->shader_info->gs.num_stream_output_components[stream];
9897       if (stream > 0 && (!num_components || !args->shader_info->so.num_outputs))
9898          continue;
9899
9900       memset(ctx.outputs.mask, 0, sizeof(ctx.outputs.mask));
9901
9902       unsigned BB_if_idx = ctx.block->index;
9903       Block BB_endif = Block();
9904       if (!stream_id.isConstant()) {
9905          /* begin IF */
9906          Temp cond = bld.sopc(aco_opcode::s_cmp_eq_u32, bld.def(s1, scc), stream_id, Operand(stream));
9907          append_logical_end(ctx.block);
9908          ctx.block->kind |= block_kind_uniform;
9909          bld.branch(aco_opcode::p_cbranch_z, cond);
9910
9911          BB_endif.kind |= ctx.block->kind & block_kind_top_level;
9912
9913          ctx.block = ctx.program->create_and_insert_block();
9914          add_edge(BB_if_idx, ctx.block);
9915          bld.reset(ctx.block);
9916          append_logical_start(ctx.block);
9917       }
9918
9919       unsigned offset = 0;
9920       for (unsigned i = 0; i <= VARYING_SLOT_VAR31; ++i) {
9921          if (args->shader_info->gs.output_streams[i] != stream)
9922             continue;
9923
9924          unsigned output_usage_mask = args->shader_info->gs.output_usage_mask[i];
9925          unsigned length = util_last_bit(output_usage_mask);
9926          for (unsigned j = 0; j < length; ++j) {
9927             if (!(output_usage_mask & (1 << j)))
9928                continue;
9929
9930             unsigned const_offset = offset * args->shader_info->gs.vertices_out * 16 * 4;
9931             Temp voffset = vtx_offset;
9932             if (const_offset >= 4096u) {
9933                voffset = bld.vadd32(bld.def(v1), Operand(const_offset / 4096u * 4096u), voffset);
9934                const_offset %= 4096u;
9935             }
9936
9937             aco_ptr<MUBUF_instruction> mubuf{create_instruction<MUBUF_instruction>(aco_opcode::buffer_load_dword, Format::MUBUF, 3, 1)};
9938             mubuf->definitions[0] = bld.def(v1);
9939             mubuf->operands[0] = Operand(gsvs_ring);
9940             mubuf->operands[1] = Operand(voffset);
9941             mubuf->operands[2] = Operand(0u);
9942             mubuf->offen = true;
9943             mubuf->offset = const_offset;
9944             mubuf->glc = true;
9945             mubuf->slc = true;
9946             mubuf->dlc = args->options->chip_class >= GFX10;
9947             mubuf->barrier = barrier_none;
9948             mubuf->can_reorder = true;
9949
9950             ctx.outputs.mask[i] |= 1 << j;
9951             ctx.outputs.outputs[i][j] = mubuf->definitions[0].getTemp();
9952
9953             bld.insert(std::move(mubuf));
9954
9955             offset++;
9956          }
9957       }
9958
9959       if (args->shader_info->so.num_outputs) {
9960          emit_streamout(&ctx, stream);
9961          bld.reset(ctx.block);
9962       }
9963
9964       if (stream == 0) {
9965          create_vs_exports(&ctx);
9966          ctx.block->kind |= block_kind_export_end;
9967       }
9968
9969       if (!stream_id.isConstant()) {
9970          append_logical_end(ctx.block);
9971
9972          /* branch from then block to endif block */
9973          bld.branch(aco_opcode::p_branch);
9974          add_edge(ctx.block->index, &BB_endif);
9975          ctx.block->kind |= block_kind_uniform;
9976
9977          /* emit else block */
9978          ctx.block = ctx.program->create_and_insert_block();
9979          add_edge(BB_if_idx, ctx.block);
9980          bld.reset(ctx.block);
9981          append_logical_start(ctx.block);
9982
9983          endif_blocks.push(std::move(BB_endif));
9984       }
9985    }
9986
9987    while (!endif_blocks.empty()) {
9988       Block BB_endif = std::move(endif_blocks.top());
9989       endif_blocks.pop();
9990
9991       Block *BB_else = ctx.block;
9992
9993       append_logical_end(BB_else);
9994       /* branch from else block to endif block */
9995       bld.branch(aco_opcode::p_branch);
9996       add_edge(BB_else->index, &BB_endif);
9997       BB_else->kind |= block_kind_uniform;
9998
9999       /** emit endif merge block */
10000       ctx.block = program->insert_block(std::move(BB_endif));
10001       bld.reset(ctx.block);
10002       append_logical_start(ctx.block);
10003    }
10004
10005    program->config->float_mode = program->blocks[0].fp_mode.val;
10006
10007    append_logical_end(ctx.block);
10008    ctx.block->kind |= block_kind_uniform;
10009    bld.sopp(aco_opcode::s_endpgm);
10010
10011    cleanup_cfg(program);
10012 }
10013 }