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3 * Copyright © 2018 Google
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7 * to deal in the Software without restriction, including without limitation
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "ac_shader_util.h"
32 #include "aco_builder.h"
33 #include "aco_interface.h"
34 #include "aco_instruction_selection_setup.cpp"
35 #include "util/fast_idiv_by_const.h"
40 class loop_info_RAII
{
42 unsigned header_idx_old
;
44 bool divergent_cont_old
;
45 bool divergent_branch_old
;
46 bool divergent_if_old
;
49 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
51 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
52 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
53 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
54 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
56 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
57 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
58 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
59 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
60 ctx
->cf_info
.parent_if
.is_divergent
= false;
61 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
66 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
67 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
68 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
70 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
71 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
72 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
73 ctx
->cf_info
.exec_potentially_empty
= false;
81 bool exec_potentially_empty_old
;
85 bool then_branch_divergent
;
90 static void visit_cf_list(struct isel_context
*ctx
,
91 struct exec_list
*list
);
93 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
95 succ
->logical_preds
.emplace_back(pred_idx
);
99 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
101 succ
->linear_preds
.emplace_back(pred_idx
);
104 static void add_edge(unsigned pred_idx
, Block
*succ
)
106 add_logical_edge(pred_idx
, succ
);
107 add_linear_edge(pred_idx
, succ
);
110 static void append_logical_start(Block
*b
)
112 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
115 static void append_logical_end(Block
*b
)
117 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
120 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
122 assert(ctx
->allocated
[def
->index
].id());
123 return ctx
->allocated
[def
->index
];
126 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
127 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
129 Builder
bld(ctx
->program
, ctx
->block
);
130 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
131 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
133 if (ctx
->program
->wave_size
== 32) {
136 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
141 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
143 Builder
bld(ctx
->program
, ctx
->block
);
146 dst
= bld
.tmp(src
.regClass());
148 assert(src
.size() == dst
.size());
150 if (ctx
->stage
!= fragment_fs
) {
154 bld
.copy(Definition(dst
), src
);
158 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
159 ctx
->program
->needs_wqm
|= program_needs_wqm
;
163 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
165 if (index
.regClass() == s1
)
166 return bld
.vop3(aco_opcode::v_readlane_b32
, bld
.def(s1
), data
, index
);
168 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
170 /* Currently not implemented on GFX6-7 */
171 assert(ctx
->options
->chip_class
>= GFX8
);
173 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
174 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
177 /* GFX10, wave64 mode:
178 * The bpermute instruction is limited to half-wave operation, which means that it can't
179 * properly support subgroup shuffle like older generations (or wave32 mode), so we
182 if (!ctx
->has_gfx10_wave64_bpermute
) {
183 ctx
->has_gfx10_wave64_bpermute
= true;
184 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
185 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
188 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
189 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
190 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
191 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(s2
, vcc
), lane_is_hi
, index_is_hi
);
193 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
194 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
197 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
199 if (val
.type() == RegType::sgpr
) {
200 Builder
bld(ctx
->program
, ctx
->block
);
201 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
203 assert(val
.type() == RegType::vgpr
);
207 //assumes a != 0xffffffff
208 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
211 Builder
bld(ctx
->program
, ctx
->block
);
213 if (util_is_power_of_two_or_zero(b
)) {
214 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
218 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
220 assert(info
.multiplier
<= 0xffffffff);
222 bool pre_shift
= info
.pre_shift
!= 0;
223 bool increment
= info
.increment
!= 0;
224 bool multiply
= true;
225 bool post_shift
= info
.post_shift
!= 0;
227 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
228 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
232 Temp pre_shift_dst
= a
;
234 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
235 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
238 Temp increment_dst
= pre_shift_dst
;
240 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
241 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
244 Temp multiply_dst
= increment_dst
;
246 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
247 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
248 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
252 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
256 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
258 Builder
bld(ctx
->program
, ctx
->block
);
259 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
263 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
265 /* no need to extract the whole vector */
266 if (src
.regClass() == dst_rc
) {
270 assert(src
.size() > idx
);
271 Builder
bld(ctx
->program
, ctx
->block
);
272 auto it
= ctx
->allocated_vec
.find(src
.id());
273 /* the size check needs to be early because elements other than 0 may be garbage */
274 if (it
!= ctx
->allocated_vec
.end() && it
->second
[0].size() == dst_rc
.size()) {
275 if (it
->second
[idx
].regClass() == dst_rc
) {
276 return it
->second
[idx
];
278 assert(dst_rc
.size() == it
->second
[idx
].regClass().size());
279 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
280 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
284 if (src
.size() == dst_rc
.size()) {
286 return bld
.copy(bld
.def(dst_rc
), src
);
288 Temp dst
= bld
.tmp(dst_rc
);
289 emit_extract_vector(ctx
, src
, idx
, dst
);
294 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
296 if (num_components
== 1)
298 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
300 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
301 split
->operands
[0] = Operand(vec_src
);
302 std::array
<Temp
,4> elems
;
303 for (unsigned i
= 0; i
< num_components
; i
++) {
304 elems
[i
] = {ctx
->program
->allocateId(), RegClass(vec_src
.type(), vec_src
.size() / num_components
)};
305 split
->definitions
[i
] = Definition(elems
[i
]);
307 ctx
->block
->instructions
.emplace_back(std::move(split
));
308 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
311 /* This vector expansion uses a mask to determine which elements in the new vector
312 * come from the original vector. The other elements are undefined. */
313 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
315 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
320 Builder
bld(ctx
->program
, ctx
->block
);
321 if (num_components
== 1) {
322 if (dst
.type() == RegType::sgpr
)
323 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
325 bld
.copy(Definition(dst
), vec_src
);
329 unsigned component_size
= dst
.size() / num_components
;
330 std::array
<Temp
,4> elems
;
332 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
333 vec
->definitions
[0] = Definition(dst
);
335 for (unsigned i
= 0; i
< num_components
; i
++) {
336 if (mask
& (1 << i
)) {
337 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
338 if (dst
.type() == RegType::sgpr
)
339 src
= bld
.as_uniform(src
);
340 vec
->operands
[i
] = Operand(src
);
342 vec
->operands
[i
] = Operand(0u);
344 elems
[i
] = vec
->operands
[i
].getTemp();
346 ctx
->block
->instructions
.emplace_back(std::move(vec
));
347 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
350 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
352 Builder
bld(ctx
->program
, ctx
->block
);
354 dst
= bld
.tmp(bld
.lm
);
356 assert(val
.regClass() == s1
);
357 assert(dst
.regClass() == bld
.lm
);
359 return bld
.sop2(Builder::s_cselect
, bld
.hint_vcc(Definition(dst
)), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
362 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
364 Builder
bld(ctx
->program
, ctx
->block
);
368 assert(val
.regClass() == bld
.lm
);
369 assert(dst
.regClass() == s1
);
371 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
372 Temp tmp
= bld
.tmp(s1
);
373 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
374 return emit_wqm(ctx
, tmp
, dst
);
377 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
379 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
380 return get_ssa_temp(ctx
, src
.src
.ssa
);
382 if (src
.src
.ssa
->num_components
== size
) {
383 bool identity_swizzle
= true;
384 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
385 if (src
.swizzle
[i
] != i
)
386 identity_swizzle
= false;
388 if (identity_swizzle
)
389 return get_ssa_temp(ctx
, src
.src
.ssa
);
392 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
393 unsigned elem_size
= vec
.size() / src
.src
.ssa
->num_components
;
394 assert(elem_size
> 0); /* TODO: 8 and 16-bit vectors not supported */
395 assert(vec
.size() % elem_size
== 0);
397 RegClass elem_rc
= RegClass(vec
.type(), elem_size
);
399 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
402 std::array
<Temp
,4> elems
;
403 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
404 for (unsigned i
= 0; i
< size
; ++i
) {
405 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
406 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
408 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
)};
409 vec_instr
->definitions
[0] = Definition(dst
);
410 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
411 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
416 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
420 Builder
bld(ctx
->program
, ctx
->block
);
421 if (ptr
.type() == RegType::vgpr
)
422 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
423 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
424 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
427 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
429 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
430 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
431 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
432 sop2
->definitions
[0] = Definition(dst
);
434 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
435 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
438 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool commutative
, bool swap_srcs
=false)
440 Builder
bld(ctx
->program
, ctx
->block
);
441 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
442 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
443 if (src1
.type() == RegType::sgpr
) {
444 if (commutative
&& src0
.type() == RegType::vgpr
) {
448 } else if (src0
.type() == RegType::vgpr
&&
449 op
!= aco_opcode::v_madmk_f32
&&
450 op
!= aco_opcode::v_madak_f32
&&
451 op
!= aco_opcode::v_madmk_f16
&&
452 op
!= aco_opcode::v_madak_f16
) {
453 /* If the instruction is not commutative, we emit a VOP3A instruction */
454 bld
.vop2_e64(op
, Definition(dst
), src0
, src1
);
457 src1
= bld
.copy(bld
.def(RegType::vgpr
, src1
.size()), src1
); //TODO: as_vgpr
460 bld
.vop2(op
, Definition(dst
), src0
, src1
);
463 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
465 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
466 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
467 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
469 /* ensure that the instruction has at most 1 sgpr operand
470 * The optimizer will inline constants for us */
471 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
472 src0
= as_vgpr(ctx
, src0
);
473 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
474 src1
= as_vgpr(ctx
, src1
);
475 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
476 src2
= as_vgpr(ctx
, src2
);
478 Builder
bld(ctx
->program
, ctx
->block
);
479 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
482 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
484 Builder
bld(ctx
->program
, ctx
->block
);
485 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
488 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
490 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
491 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
492 assert(src0
.size() == src1
.size());
494 aco_ptr
<Instruction
> vopc
;
495 if (src1
.type() == RegType::sgpr
) {
496 if (src0
.type() == RegType::vgpr
) {
497 /* to swap the operands, we might also have to change the opcode */
499 case aco_opcode::v_cmp_lt_f32
:
500 op
= aco_opcode::v_cmp_gt_f32
;
502 case aco_opcode::v_cmp_ge_f32
:
503 op
= aco_opcode::v_cmp_le_f32
;
505 case aco_opcode::v_cmp_lt_i32
:
506 op
= aco_opcode::v_cmp_gt_i32
;
508 case aco_opcode::v_cmp_ge_i32
:
509 op
= aco_opcode::v_cmp_le_i32
;
511 case aco_opcode::v_cmp_lt_u32
:
512 op
= aco_opcode::v_cmp_gt_u32
;
514 case aco_opcode::v_cmp_ge_u32
:
515 op
= aco_opcode::v_cmp_le_u32
;
517 case aco_opcode::v_cmp_lt_f64
:
518 op
= aco_opcode::v_cmp_gt_f64
;
520 case aco_opcode::v_cmp_ge_f64
:
521 op
= aco_opcode::v_cmp_le_f64
;
523 case aco_opcode::v_cmp_lt_i64
:
524 op
= aco_opcode::v_cmp_gt_i64
;
526 case aco_opcode::v_cmp_ge_i64
:
527 op
= aco_opcode::v_cmp_le_i64
;
529 case aco_opcode::v_cmp_lt_u64
:
530 op
= aco_opcode::v_cmp_gt_u64
;
532 case aco_opcode::v_cmp_ge_u64
:
533 op
= aco_opcode::v_cmp_le_u64
;
535 default: /* eq and ne are commutative */
542 src1
= as_vgpr(ctx
, src1
);
546 Builder
bld(ctx
->program
, ctx
->block
);
547 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
550 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
552 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
553 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
554 Builder
bld(ctx
->program
, ctx
->block
);
556 assert(dst
.regClass() == bld
.lm
);
557 assert(src0
.type() == RegType::sgpr
);
558 assert(src1
.type() == RegType::sgpr
);
559 assert(src0
.regClass() == src1
.regClass());
561 /* Emit the SALU comparison instruction */
562 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
563 /* Turn the result into a per-lane bool */
564 bool_to_vector_condition(ctx
, cmp
, dst
);
567 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
568 aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::last_opcode
, aco_opcode s64_op
= aco_opcode::last_opcode
)
570 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: s32_op
;
571 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: v32_op
;
572 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
573 bool use_valu
= s_op
== aco_opcode::last_opcode
||
575 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
576 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
577 aco_opcode op
= use_valu
? v_op
: s_op
;
578 assert(op
!= aco_opcode::last_opcode
);
581 emit_vopc_instruction(ctx
, instr
, op
, dst
);
583 emit_sopc_instruction(ctx
, instr
, op
, dst
);
586 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
588 Builder
bld(ctx
->program
, ctx
->block
);
589 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
590 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
592 assert(dst
.regClass() == bld
.lm
);
593 assert(src0
.regClass() == bld
.lm
);
594 assert(src1
.regClass() == bld
.lm
);
596 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
599 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
601 Builder
bld(ctx
->program
, ctx
->block
);
602 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
603 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
604 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
606 assert(cond
.regClass() == bld
.lm
);
608 if (dst
.type() == RegType::vgpr
) {
609 aco_ptr
<Instruction
> bcsel
;
610 if (dst
.size() == 1) {
611 then
= as_vgpr(ctx
, then
);
612 els
= as_vgpr(ctx
, els
);
614 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
615 } else if (dst
.size() == 2) {
616 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
618 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
619 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
621 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
622 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
624 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
626 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
627 nir_print_instr(&instr
->instr
, stderr
);
628 fprintf(stderr
, "\n");
633 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
634 assert(dst
.regClass() == bld
.lm
);
635 assert(then
.regClass() == bld
.lm
);
636 assert(els
.regClass() == bld
.lm
);
639 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
640 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
641 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
642 assert(dst
.size() == then
.size());
643 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
644 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
646 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
647 nir_print_instr(&instr
->instr
, stderr
);
648 fprintf(stderr
, "\n");
653 /* divergent boolean bcsel
654 * this implements bcsel on bools: dst = s0 ? s1 : s2
655 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
656 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
658 if (cond
.id() != then
.id())
659 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
661 if (cond
.id() == els
.id())
662 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
664 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
665 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
668 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
669 aco_opcode op
, uint32_t undo
)
671 /* multiply by 16777216 to handle denormals */
672 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
673 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
674 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
675 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
676 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
678 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
680 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
683 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
685 if (ctx
->block
->fp_mode
.denorm32
== 0) {
686 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
690 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
693 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
695 if (ctx
->block
->fp_mode
.denorm32
== 0) {
696 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
700 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
703 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
705 if (ctx
->block
->fp_mode
.denorm32
== 0) {
706 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
710 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
713 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
715 if (ctx
->block
->fp_mode
.denorm32
== 0) {
716 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
720 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
723 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
725 if (!instr
->dest
.dest
.is_ssa
) {
726 fprintf(stderr
, "nir alu dst not in ssa: ");
727 nir_print_instr(&instr
->instr
, stderr
);
728 fprintf(stderr
, "\n");
731 Builder
bld(ctx
->program
, ctx
->block
);
732 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
737 std::array
<Temp
,4> elems
;
738 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
739 for (unsigned i
= 0; i
< instr
->dest
.dest
.ssa
.num_components
; ++i
) {
740 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
741 vec
->operands
[i
] = Operand
{elems
[i
]};
743 vec
->definitions
[0] = Definition(dst
);
744 ctx
->block
->instructions
.emplace_back(std::move(vec
));
745 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
749 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
750 aco_ptr
<Instruction
> mov
;
751 if (dst
.type() == RegType::sgpr
) {
752 if (src
.type() == RegType::vgpr
)
753 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
754 else if (src
.regClass() == s1
)
755 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
756 else if (src
.regClass() == s2
)
757 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
759 unreachable("wrong src register class for nir_op_imov");
760 } else if (dst
.regClass() == v1
) {
761 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
762 } else if (dst
.regClass() == v2
) {
763 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
765 nir_print_instr(&instr
->instr
, stderr
);
766 unreachable("Should have been lowered to scalar.");
771 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
772 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
773 assert(src
.regClass() == bld
.lm
);
774 assert(dst
.regClass() == bld
.lm
);
775 bld
.sop2(Builder::s_andn2
, Definition(dst
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
776 } else if (dst
.regClass() == v1
) {
777 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
778 } else if (dst
.type() == RegType::sgpr
) {
779 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
780 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
782 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
783 nir_print_instr(&instr
->instr
, stderr
);
784 fprintf(stderr
, "\n");
789 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
790 if (dst
.regClass() == v1
) {
791 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
792 } else if (dst
.regClass() == s1
) {
793 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
794 } else if (dst
.size() == 2) {
795 Temp src0
= bld
.tmp(dst
.type(), 1);
796 Temp src1
= bld
.tmp(dst
.type(), 1);
797 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
799 if (dst
.regClass() == s2
) {
800 Temp carry
= bld
.tmp(s1
);
801 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
802 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
803 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
805 Temp lower
= bld
.tmp(v1
);
806 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
807 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
808 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
811 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
812 nir_print_instr(&instr
->instr
, stderr
);
813 fprintf(stderr
, "\n");
818 if (dst
.regClass() == s1
) {
819 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
820 } else if (dst
.regClass() == v1
) {
821 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
822 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
824 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
825 nir_print_instr(&instr
->instr
, stderr
);
826 fprintf(stderr
, "\n");
831 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
832 if (dst
.regClass() == s1
) {
833 Temp tmp
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
834 Temp gtz
= bld
.sopc(aco_opcode::s_cmp_gt_i32
, bld
.def(s1
, scc
), src
, Operand(0u));
835 bld
.sop2(aco_opcode::s_add_i32
, Definition(dst
), bld
.def(s1
, scc
), gtz
, tmp
);
836 } else if (dst
.regClass() == s2
) {
837 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
838 Temp neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
839 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, neqz
);
840 } else if (dst
.regClass() == v1
) {
841 Temp tmp
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
842 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
843 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(1u), tmp
, gtz
);
844 } else if (dst
.regClass() == v2
) {
845 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
846 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
847 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
848 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
849 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
850 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
852 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
853 nir_print_instr(&instr
->instr
, stderr
);
854 fprintf(stderr
, "\n");
859 if (dst
.regClass() == v1
) {
860 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
861 } else if (dst
.regClass() == s1
) {
862 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
864 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
865 nir_print_instr(&instr
->instr
, stderr
);
866 fprintf(stderr
, "\n");
871 if (dst
.regClass() == v1
) {
872 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
873 } else if (dst
.regClass() == s1
) {
874 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
876 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
877 nir_print_instr(&instr
->instr
, stderr
);
878 fprintf(stderr
, "\n");
883 if (dst
.regClass() == v1
) {
884 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
885 } else if (dst
.regClass() == s1
) {
886 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
889 nir_print_instr(&instr
->instr
, stderr
);
890 fprintf(stderr
, "\n");
895 if (dst
.regClass() == v1
) {
896 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
897 } else if (dst
.regClass() == s1
) {
898 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
900 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
901 nir_print_instr(&instr
->instr
, stderr
);
902 fprintf(stderr
, "\n");
907 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
908 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
909 } else if (dst
.regClass() == v1
) {
910 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
911 } else if (dst
.regClass() == s1
) {
912 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
913 } else if (dst
.regClass() == s2
) {
914 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
916 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
917 nir_print_instr(&instr
->instr
, stderr
);
918 fprintf(stderr
, "\n");
923 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
924 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
925 } else if (dst
.regClass() == v1
) {
926 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
927 } else if (dst
.regClass() == s1
) {
928 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
929 } else if (dst
.regClass() == s2
) {
930 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
932 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
933 nir_print_instr(&instr
->instr
, stderr
);
934 fprintf(stderr
, "\n");
939 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
940 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
941 } else if (dst
.regClass() == v1
) {
942 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
943 } else if (dst
.regClass() == s1
) {
944 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
945 } else if (dst
.regClass() == s2
) {
946 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
948 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
949 nir_print_instr(&instr
->instr
, stderr
);
950 fprintf(stderr
, "\n");
955 if (dst
.regClass() == v1
) {
956 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
957 } else if (dst
.regClass() == v2
) {
958 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
959 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
960 } else if (dst
.regClass() == s2
) {
961 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
962 } else if (dst
.regClass() == s1
) {
963 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
965 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
966 nir_print_instr(&instr
->instr
, stderr
);
967 fprintf(stderr
, "\n");
972 if (dst
.regClass() == v1
) {
973 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
974 } else if (dst
.regClass() == v2
) {
975 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
976 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
977 } else if (dst
.regClass() == s1
) {
978 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
979 } else if (dst
.regClass() == s2
) {
980 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
982 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
983 nir_print_instr(&instr
->instr
, stderr
);
984 fprintf(stderr
, "\n");
989 if (dst
.regClass() == v1
) {
990 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
991 } else if (dst
.regClass() == v2
) {
992 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
993 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
994 } else if (dst
.regClass() == s1
) {
995 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
996 } else if (dst
.regClass() == s2
) {
997 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
999 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1000 nir_print_instr(&instr
->instr
, stderr
);
1001 fprintf(stderr
, "\n");
1005 case nir_op_find_lsb
: {
1006 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1007 if (src
.regClass() == s1
) {
1008 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1009 } else if (src
.regClass() == v1
) {
1010 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1011 } else if (src
.regClass() == s2
) {
1012 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1014 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1015 nir_print_instr(&instr
->instr
, stderr
);
1016 fprintf(stderr
, "\n");
1020 case nir_op_ufind_msb
:
1021 case nir_op_ifind_msb
: {
1022 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1023 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1024 aco_opcode op
= src
.regClass() == s2
?
1025 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1026 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1027 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1029 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1030 Operand(src
.size() * 32u - 1u), msb_rev
);
1031 Temp msb
= sub
.def(0).getTemp();
1032 Temp carry
= sub
.def(1).getTemp();
1034 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, carry
);
1035 } else if (src
.regClass() == v1
) {
1036 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1037 Temp msb_rev
= bld
.tmp(v1
);
1038 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1039 Temp msb
= bld
.tmp(v1
);
1040 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1041 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1043 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1044 nir_print_instr(&instr
->instr
, stderr
);
1045 fprintf(stderr
, "\n");
1049 case nir_op_bitfield_reverse
: {
1050 if (dst
.regClass() == s1
) {
1051 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1052 } else if (dst
.regClass() == v1
) {
1053 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1055 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1056 nir_print_instr(&instr
->instr
, stderr
);
1057 fprintf(stderr
, "\n");
1062 if (dst
.regClass() == s1
) {
1063 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1067 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1068 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1069 if (dst
.regClass() == v1
) {
1070 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1074 assert(src0
.size() == 2 && src1
.size() == 2);
1075 Temp src00
= bld
.tmp(src0
.type(), 1);
1076 Temp src01
= bld
.tmp(dst
.type(), 1);
1077 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1078 Temp src10
= bld
.tmp(src1
.type(), 1);
1079 Temp src11
= bld
.tmp(dst
.type(), 1);
1080 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1082 if (dst
.regClass() == s2
) {
1083 Temp carry
= bld
.tmp(s1
);
1084 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1085 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1086 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1087 } else if (dst
.regClass() == v2
) {
1088 Temp dst0
= bld
.tmp(v1
);
1089 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1090 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1093 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1094 nir_print_instr(&instr
->instr
, stderr
);
1095 fprintf(stderr
, "\n");
1099 case nir_op_uadd_sat
: {
1100 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1101 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1102 if (dst
.regClass() == s1
) {
1103 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1104 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1106 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1107 } else if (dst
.regClass() == v1
) {
1108 if (ctx
->options
->chip_class
>= GFX9
) {
1109 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1110 add
->operands
[0] = Operand(src0
);
1111 add
->operands
[1] = Operand(src1
);
1112 add
->definitions
[0] = Definition(dst
);
1114 ctx
->block
->instructions
.emplace_back(std::move(add
));
1116 if (src1
.regClass() != v1
)
1117 std::swap(src0
, src1
);
1118 assert(src1
.regClass() == v1
);
1119 Temp tmp
= bld
.tmp(v1
);
1120 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1121 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1130 case nir_op_uadd_carry
: {
1131 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1132 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1133 if (dst
.regClass() == s1
) {
1134 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1137 if (dst
.regClass() == v1
) {
1138 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1139 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1143 Temp src00
= bld
.tmp(src0
.type(), 1);
1144 Temp src01
= bld
.tmp(dst
.type(), 1);
1145 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1146 Temp src10
= bld
.tmp(src1
.type(), 1);
1147 Temp src11
= bld
.tmp(dst
.type(), 1);
1148 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1149 if (dst
.regClass() == s2
) {
1150 Temp carry
= bld
.tmp(s1
);
1151 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1152 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1153 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1154 } else if (dst
.regClass() == v2
) {
1155 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1156 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1157 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1158 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1160 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1161 nir_print_instr(&instr
->instr
, stderr
);
1162 fprintf(stderr
, "\n");
1167 if (dst
.regClass() == s1
) {
1168 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1172 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1173 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1174 if (dst
.regClass() == v1
) {
1175 bld
.vsub32(Definition(dst
), src0
, src1
);
1179 Temp src00
= bld
.tmp(src0
.type(), 1);
1180 Temp src01
= bld
.tmp(dst
.type(), 1);
1181 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1182 Temp src10
= bld
.tmp(src1
.type(), 1);
1183 Temp src11
= bld
.tmp(dst
.type(), 1);
1184 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1185 if (dst
.regClass() == s2
) {
1186 Temp carry
= bld
.tmp(s1
);
1187 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1188 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1189 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1190 } else if (dst
.regClass() == v2
) {
1191 Temp lower
= bld
.tmp(v1
);
1192 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1193 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1194 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1196 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1197 nir_print_instr(&instr
->instr
, stderr
);
1198 fprintf(stderr
, "\n");
1202 case nir_op_usub_borrow
: {
1203 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1204 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1205 if (dst
.regClass() == s1
) {
1206 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1208 } else if (dst
.regClass() == v1
) {
1209 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1210 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1214 Temp src00
= bld
.tmp(src0
.type(), 1);
1215 Temp src01
= bld
.tmp(dst
.type(), 1);
1216 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1217 Temp src10
= bld
.tmp(src1
.type(), 1);
1218 Temp src11
= bld
.tmp(dst
.type(), 1);
1219 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1220 if (dst
.regClass() == s2
) {
1221 Temp borrow
= bld
.tmp(s1
);
1222 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1223 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1224 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1225 } else if (dst
.regClass() == v2
) {
1226 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1227 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1228 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1229 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1231 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1232 nir_print_instr(&instr
->instr
, stderr
);
1233 fprintf(stderr
, "\n");
1238 if (dst
.regClass() == v1
) {
1239 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1240 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1241 } else if (dst
.regClass() == s1
) {
1242 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1244 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1245 nir_print_instr(&instr
->instr
, stderr
);
1246 fprintf(stderr
, "\n");
1250 case nir_op_umul_high
: {
1251 if (dst
.regClass() == v1
) {
1252 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1253 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1254 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1255 } else if (dst
.regClass() == s1
) {
1256 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1257 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1258 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1260 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1261 nir_print_instr(&instr
->instr
, stderr
);
1262 fprintf(stderr
, "\n");
1266 case nir_op_imul_high
: {
1267 if (dst
.regClass() == v1
) {
1268 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1269 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1270 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1271 } else if (dst
.regClass() == s1
) {
1272 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1273 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1274 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1276 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1277 nir_print_instr(&instr
->instr
, stderr
);
1278 fprintf(stderr
, "\n");
1283 if (dst
.size() == 1) {
1284 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1285 } else if (dst
.size() == 2) {
1286 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1287 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1289 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1290 nir_print_instr(&instr
->instr
, stderr
);
1291 fprintf(stderr
, "\n");
1296 if (dst
.size() == 1) {
1297 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1298 } else if (dst
.size() == 2) {
1299 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]),
1300 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1302 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1303 nir_print_instr(&instr
->instr
, stderr
);
1304 fprintf(stderr
, "\n");
1309 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1310 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1311 if (dst
.size() == 1) {
1312 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1313 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1315 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1316 } else if (dst
.size() == 2) {
1317 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1318 get_alu_src(ctx
, instr
->src
[0]),
1319 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1320 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1323 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1324 nir_print_instr(&instr
->instr
, stderr
);
1325 fprintf(stderr
, "\n");
1330 if (dst
.size() == 1) {
1331 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true);
1332 } else if (dst
.size() == 2) {
1333 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
),
1334 get_alu_src(ctx
, instr
->src
[0]),
1335 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1337 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1338 nir_print_instr(&instr
->instr
, stderr
);
1339 fprintf(stderr
, "\n");
1344 if (dst
.size() == 1) {
1345 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true);
1346 } else if (dst
.size() == 2) {
1347 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
),
1348 get_alu_src(ctx
, instr
->src
[0]),
1349 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1351 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1352 nir_print_instr(&instr
->instr
, stderr
);
1353 fprintf(stderr
, "\n");
1357 case nir_op_fmax3
: {
1358 if (dst
.size() == 1) {
1359 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
);
1361 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1362 nir_print_instr(&instr
->instr
, stderr
);
1363 fprintf(stderr
, "\n");
1367 case nir_op_fmin3
: {
1368 if (dst
.size() == 1) {
1369 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
);
1371 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1372 nir_print_instr(&instr
->instr
, stderr
);
1373 fprintf(stderr
, "\n");
1377 case nir_op_fmed3
: {
1378 if (dst
.size() == 1) {
1379 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
);
1381 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1382 nir_print_instr(&instr
->instr
, stderr
);
1383 fprintf(stderr
, "\n");
1387 case nir_op_umax3
: {
1388 if (dst
.size() == 1) {
1389 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1391 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1392 nir_print_instr(&instr
->instr
, stderr
);
1393 fprintf(stderr
, "\n");
1397 case nir_op_umin3
: {
1398 if (dst
.size() == 1) {
1399 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1401 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1402 nir_print_instr(&instr
->instr
, stderr
);
1403 fprintf(stderr
, "\n");
1407 case nir_op_umed3
: {
1408 if (dst
.size() == 1) {
1409 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1412 nir_print_instr(&instr
->instr
, stderr
);
1413 fprintf(stderr
, "\n");
1417 case nir_op_imax3
: {
1418 if (dst
.size() == 1) {
1419 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1421 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1422 nir_print_instr(&instr
->instr
, stderr
);
1423 fprintf(stderr
, "\n");
1427 case nir_op_imin3
: {
1428 if (dst
.size() == 1) {
1429 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1431 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1432 nir_print_instr(&instr
->instr
, stderr
);
1433 fprintf(stderr
, "\n");
1437 case nir_op_imed3
: {
1438 if (dst
.size() == 1) {
1439 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1441 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1442 nir_print_instr(&instr
->instr
, stderr
);
1443 fprintf(stderr
, "\n");
1447 case nir_op_cube_face_coord
: {
1448 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1449 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1450 emit_extract_vector(ctx
, in
, 1, v1
),
1451 emit_extract_vector(ctx
, in
, 2, v1
) };
1452 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1453 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1454 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1455 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1456 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1457 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1458 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1461 case nir_op_cube_face_index
: {
1462 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1463 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1464 emit_extract_vector(ctx
, in
, 1, v1
),
1465 emit_extract_vector(ctx
, in
, 2, v1
) };
1466 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1469 case nir_op_bcsel
: {
1470 emit_bcsel(ctx
, instr
, dst
);
1474 if (dst
.size() == 1) {
1475 emit_rsq(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1476 } else if (dst
.size() == 2) {
1477 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1479 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1480 nir_print_instr(&instr
->instr
, stderr
);
1481 fprintf(stderr
, "\n");
1486 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1487 if (dst
.size() == 1) {
1488 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1489 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1490 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1491 } else if (dst
.size() == 2) {
1492 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1493 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1494 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1496 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1497 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1499 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1500 nir_print_instr(&instr
->instr
, stderr
);
1501 fprintf(stderr
, "\n");
1506 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1507 if (dst
.size() == 1) {
1508 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1509 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1510 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1511 } else if (dst
.size() == 2) {
1512 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1513 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1514 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1515 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1516 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1517 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1519 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1520 nir_print_instr(&instr
->instr
, stderr
);
1521 fprintf(stderr
, "\n");
1526 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1527 if (dst
.size() == 1) {
1528 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1529 } else if (dst
.size() == 2) {
1530 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1531 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1534 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1535 nir_print_instr(&instr
->instr
, stderr
);
1536 fprintf(stderr
, "\n");
1540 case nir_op_flog2
: {
1541 if (dst
.size() == 1) {
1542 emit_log2(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1544 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1545 nir_print_instr(&instr
->instr
, stderr
);
1546 fprintf(stderr
, "\n");
1551 if (dst
.size() == 1) {
1552 emit_rcp(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1553 } else if (dst
.size() == 2) {
1554 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1556 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1557 nir_print_instr(&instr
->instr
, stderr
);
1558 fprintf(stderr
, "\n");
1562 case nir_op_fexp2
: {
1563 if (dst
.size() == 1) {
1564 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1566 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1567 nir_print_instr(&instr
->instr
, stderr
);
1568 fprintf(stderr
, "\n");
1572 case nir_op_fsqrt
: {
1573 if (dst
.size() == 1) {
1574 emit_sqrt(ctx
, bld
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1575 } else if (dst
.size() == 2) {
1576 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1578 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1579 nir_print_instr(&instr
->instr
, stderr
);
1580 fprintf(stderr
, "\n");
1584 case nir_op_ffract
: {
1585 if (dst
.size() == 1) {
1586 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1587 } else if (dst
.size() == 2) {
1588 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1590 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1591 nir_print_instr(&instr
->instr
, stderr
);
1592 fprintf(stderr
, "\n");
1596 case nir_op_ffloor
: {
1597 if (dst
.size() == 1) {
1598 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1599 } else if (dst
.size() == 2) {
1600 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f64
, dst
);
1602 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1603 nir_print_instr(&instr
->instr
, stderr
);
1604 fprintf(stderr
, "\n");
1608 case nir_op_fceil
: {
1609 if (dst
.size() == 1) {
1610 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1611 } else if (dst
.size() == 2) {
1612 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1614 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1615 nir_print_instr(&instr
->instr
, stderr
);
1616 fprintf(stderr
, "\n");
1620 case nir_op_ftrunc
: {
1621 if (dst
.size() == 1) {
1622 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
1623 } else if (dst
.size() == 2) {
1624 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f64
, dst
);
1626 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1627 nir_print_instr(&instr
->instr
, stderr
);
1628 fprintf(stderr
, "\n");
1632 case nir_op_fround_even
: {
1633 if (dst
.size() == 1) {
1634 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
1635 } else if (dst
.size() == 2) {
1636 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
1638 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1639 nir_print_instr(&instr
->instr
, stderr
);
1640 fprintf(stderr
, "\n");
1646 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1647 aco_ptr
<Instruction
> norm
;
1648 if (dst
.size() == 1) {
1650 Operand
half_pi(0x3e22f983u
);
1651 if (src
.type() == RegType::sgpr
)
1652 tmp
= bld
.vop2_e64(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
1654 tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
1656 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
1657 if (ctx
->options
->chip_class
< GFX9
)
1658 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
1660 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
1661 bld
.vop1(opcode
, Definition(dst
), tmp
);
1663 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1664 nir_print_instr(&instr
->instr
, stderr
);
1665 fprintf(stderr
, "\n");
1669 case nir_op_ldexp
: {
1670 if (dst
.size() == 1) {
1671 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
),
1672 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1673 get_alu_src(ctx
, instr
->src
[1]));
1674 } else if (dst
.size() == 2) {
1675 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
),
1676 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0])),
1677 get_alu_src(ctx
, instr
->src
[1]));
1679 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1680 nir_print_instr(&instr
->instr
, stderr
);
1681 fprintf(stderr
, "\n");
1685 case nir_op_frexp_sig
: {
1686 if (dst
.size() == 1) {
1687 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
),
1688 get_alu_src(ctx
, instr
->src
[0]));
1689 } else if (dst
.size() == 2) {
1690 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
),
1691 get_alu_src(ctx
, instr
->src
[0]));
1693 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1694 nir_print_instr(&instr
->instr
, stderr
);
1695 fprintf(stderr
, "\n");
1699 case nir_op_frexp_exp
: {
1700 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1701 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
),
1702 get_alu_src(ctx
, instr
->src
[0]));
1703 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1704 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
),
1705 get_alu_src(ctx
, instr
->src
[0]));
1707 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1708 nir_print_instr(&instr
->instr
, stderr
);
1709 fprintf(stderr
, "\n");
1713 case nir_op_fsign
: {
1714 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
1715 if (dst
.size() == 1) {
1716 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1717 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
1718 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1719 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
1720 } else if (dst
.size() == 2) {
1721 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1722 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
1723 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
1725 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1726 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
1727 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
1729 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
1731 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1732 nir_print_instr(&instr
->instr
, stderr
);
1733 fprintf(stderr
, "\n");
1737 case nir_op_f2f32
: {
1738 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1739 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
1741 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1742 nir_print_instr(&instr
->instr
, stderr
);
1743 fprintf(stderr
, "\n");
1747 case nir_op_f2f64
: {
1748 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1749 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_f32
, dst
);
1751 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1752 nir_print_instr(&instr
->instr
, stderr
);
1753 fprintf(stderr
, "\n");
1757 case nir_op_i2f32
: {
1758 assert(dst
.size() == 1);
1759 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_i32
, dst
);
1762 case nir_op_i2f64
: {
1763 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1764 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_i32
, dst
);
1765 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1766 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1767 RegClass rc
= RegClass(src
.type(), 1);
1768 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1769 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1770 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1771 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
1772 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1773 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1776 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1777 nir_print_instr(&instr
->instr
, stderr
);
1778 fprintf(stderr
, "\n");
1782 case nir_op_u2f32
: {
1783 assert(dst
.size() == 1);
1784 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_u32
, dst
);
1787 case nir_op_u2f64
: {
1788 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1789 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f64_u32
, dst
);
1790 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1791 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1792 RegClass rc
= RegClass(src
.type(), 1);
1793 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
1794 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1795 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
1796 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
1797 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
1798 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_f2i32
: {
1807 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1808 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1809 if (dst
.type() == RegType::vgpr
)
1810 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
1812 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1813 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
1815 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1816 if (dst
.type() == RegType::vgpr
)
1817 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
1819 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1820 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
1823 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1824 nir_print_instr(&instr
->instr
, stderr
);
1825 fprintf(stderr
, "\n");
1829 case nir_op_f2u32
: {
1830 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1831 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
1832 if (dst
.type() == RegType::vgpr
)
1833 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
1835 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1836 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
1838 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1839 if (dst
.type() == RegType::vgpr
)
1840 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
1842 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
1843 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
1846 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1847 nir_print_instr(&instr
->instr
, stderr
);
1848 fprintf(stderr
, "\n");
1852 case nir_op_f2i64
: {
1853 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1854 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
1855 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
1856 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
1857 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
1858 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
1859 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
1860 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
1861 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
1862 Temp new_exponent
= bld
.tmp(v1
);
1863 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
1864 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
1865 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
1866 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
1867 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1868 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
1869 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
1870 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
1871 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
1872 Temp new_lower
= bld
.tmp(v1
);
1873 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
1874 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
1875 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
1877 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
1878 if (src
.type() == RegType::vgpr
)
1879 src
= bld
.as_uniform(src
);
1880 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
1881 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
1882 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
1883 exponent
= bld
.sop2(aco_opcode::s_min_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
1884 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
1885 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
1886 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
1887 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
1888 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
1889 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
1890 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
1891 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
1892 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
1893 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
1894 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
1895 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1896 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
1897 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
1898 Temp borrow
= bld
.tmp(s1
);
1899 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
1900 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
1901 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1903 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1904 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
1905 Temp trunc
= bld
.vop1(aco_opcode::v_trunc_f64
, bld
.def(v2
), src
);
1906 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
1907 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
1908 Temp floor
= bld
.vop1(aco_opcode::v_floor_f64
, bld
.def(v2
), mul
);
1909 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
1910 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
1911 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
1912 if (dst
.type() == RegType::sgpr
) {
1913 lower
= bld
.as_uniform(lower
);
1914 upper
= bld
.as_uniform(upper
);
1916 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1919 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1920 nir_print_instr(&instr
->instr
, stderr
);
1921 fprintf(stderr
, "\n");
1925 case nir_op_f2u64
: {
1926 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1927 if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::vgpr
) {
1928 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
1929 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
1930 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
1931 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
1932 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
1933 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
1934 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
1935 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
1936 Temp new_exponent
= bld
.tmp(v1
);
1937 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
1938 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
1939 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
1940 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1941 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
1942 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
1943 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
1944 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
1945 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1947 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32 && dst
.type() == RegType::sgpr
) {
1948 if (src
.type() == RegType::vgpr
)
1949 src
= bld
.as_uniform(src
);
1950 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
1951 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
1952 exponent
= bld
.sop2(aco_opcode::s_max_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
1953 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
1954 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
1955 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
1956 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
1957 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
1958 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
1959 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
1960 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
1961 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
1962 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
1963 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
1964 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
1965 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
1966 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
1967 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1969 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
1970 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
1971 Temp trunc
= bld
.vop1(aco_opcode::v_trunc_f64
, bld
.def(v2
), src
);
1972 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
1973 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
1974 Temp floor
= bld
.vop1(aco_opcode::v_floor_f64
, bld
.def(v2
), mul
);
1975 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
1976 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
1977 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
1978 if (dst
.type() == RegType::sgpr
) {
1979 lower
= bld
.as_uniform(lower
);
1980 upper
= bld
.as_uniform(upper
);
1982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1986 nir_print_instr(&instr
->instr
, stderr
);
1987 fprintf(stderr
, "\n");
1991 case nir_op_b2f32
: {
1992 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1993 assert(src
.regClass() == bld
.lm
);
1995 if (dst
.regClass() == s1
) {
1996 src
= bool_to_scalar_condition(ctx
, src
);
1997 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
1998 } else if (dst
.regClass() == v1
) {
1999 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2001 unreachable("Wrong destination register class for nir_op_b2f32.");
2005 case nir_op_b2f64
: {
2006 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2007 assert(src
.regClass() == bld
.lm
);
2009 if (dst
.regClass() == s2
) {
2010 src
= bool_to_scalar_condition(ctx
, src
);
2011 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2012 } else if (dst
.regClass() == v2
) {
2013 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2014 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2015 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2017 unreachable("Wrong destination register class for nir_op_b2f64.");
2021 case nir_op_i2i32
: {
2022 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2023 if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2024 /* we can actually just say dst = src, as it would map the lower register */
2025 emit_extract_vector(ctx
, src
, 0, dst
);
2027 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2028 nir_print_instr(&instr
->instr
, stderr
);
2029 fprintf(stderr
, "\n");
2033 case nir_op_u2u32
: {
2034 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2035 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2036 if (dst
.regClass() == s1
) {
2037 bld
.sop2(aco_opcode::s_and_b32
, Definition(dst
), bld
.def(s1
, scc
), Operand(0xFFFFu
), src
);
2039 // TODO: do better with SDWA
2040 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0xFFFFu
), src
);
2042 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2043 /* we can actually just say dst = src, as it would map the lower register */
2044 emit_extract_vector(ctx
, src
, 0, dst
);
2046 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2047 nir_print_instr(&instr
->instr
, stderr
);
2048 fprintf(stderr
, "\n");
2052 case nir_op_i2i64
: {
2053 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2054 if (src
.regClass() == s1
) {
2055 Temp high
= bld
.sopc(aco_opcode::s_ashr_i32
, bld
.def(s1
, scc
), src
, Operand(31u));
2056 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2057 } else if (src
.regClass() == v1
) {
2058 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2059 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, high
);
2061 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2062 nir_print_instr(&instr
->instr
, stderr
);
2063 fprintf(stderr
, "\n");
2067 case nir_op_u2u64
: {
2068 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2069 if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2070 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
, Operand(0u));
2072 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2073 nir_print_instr(&instr
->instr
, stderr
);
2074 fprintf(stderr
, "\n");
2078 case nir_op_b2i32
: {
2079 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2080 assert(src
.regClass() == bld
.lm
);
2082 if (dst
.regClass() == s1
) {
2083 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2084 bool_to_scalar_condition(ctx
, src
, dst
);
2085 } else if (dst
.regClass() == v1
) {
2086 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2088 unreachable("Invalid register class for b2i32");
2093 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2094 assert(dst
.regClass() == bld
.lm
);
2096 if (src
.type() == RegType::vgpr
) {
2097 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2098 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2099 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2101 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2102 Temp tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2103 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2104 bool_to_vector_condition(ctx
, tmp
, dst
);
2108 case nir_op_pack_64_2x32_split
: {
2109 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2110 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2112 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2115 case nir_op_unpack_64_2x32_split_x
:
2116 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2118 case nir_op_unpack_64_2x32_split_y
:
2119 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2121 case nir_op_pack_half_2x16
: {
2122 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2124 if (dst
.regClass() == v1
) {
2125 Temp src0
= bld
.tmp(v1
);
2126 Temp src1
= bld
.tmp(v1
);
2127 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2128 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2129 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2131 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2132 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2133 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2135 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2136 nir_print_instr(&instr
->instr
, stderr
);
2137 fprintf(stderr
, "\n");
2141 case nir_op_unpack_half_2x16_split_x
: {
2142 if (dst
.regClass() == v1
) {
2143 Builder
bld(ctx
->program
, ctx
->block
);
2144 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2146 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2147 nir_print_instr(&instr
->instr
, stderr
);
2148 fprintf(stderr
, "\n");
2152 case nir_op_unpack_half_2x16_split_y
: {
2153 if (dst
.regClass() == v1
) {
2154 Builder
bld(ctx
->program
, ctx
->block
);
2155 /* TODO: use SDWA here */
2156 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2157 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2159 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2160 nir_print_instr(&instr
->instr
, stderr
);
2161 fprintf(stderr
, "\n");
2165 case nir_op_fquantize2f16
: {
2166 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2167 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2169 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2171 Temp cmp_res
= bld
.tmp(bld
.lm
);
2172 bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, Definition(cmp_res
), f16
, mask
).def(0).setHint(vcc
);
2174 Temp f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2176 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
) {
2177 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2178 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2180 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2185 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2186 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2188 if (dst
.regClass() == s1
) {
2189 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2190 } else if (dst
.regClass() == v1
) {
2191 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2193 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2194 nir_print_instr(&instr
->instr
, stderr
);
2195 fprintf(stderr
, "\n");
2199 case nir_op_bitfield_select
: {
2200 /* (mask & insert) | (~mask & base) */
2201 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2202 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2203 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2205 /* dst = (insert & bitmask) | (base & ~bitmask) */
2206 if (dst
.regClass() == s1
) {
2207 aco_ptr
<Instruction
> sop2
;
2208 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2209 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2211 if (const_insert
&& const_bitmask
) {
2212 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2214 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2215 lhs
= Operand(insert
);
2219 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2220 if (const_base
&& const_bitmask
) {
2221 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2223 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2224 rhs
= Operand(base
);
2227 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2229 } else if (dst
.regClass() == v1
) {
2230 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2231 base
= as_vgpr(ctx
, base
);
2232 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2233 insert
= as_vgpr(ctx
, insert
);
2235 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2238 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2239 nir_print_instr(&instr
->instr
, stderr
);
2240 fprintf(stderr
, "\n");
2246 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2247 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2248 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2250 if (dst
.type() == RegType::sgpr
) {
2252 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2253 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2254 if (const_offset
&& const_bits
) {
2255 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2256 extract
= Operand(const_extract
);
2260 width
= Operand(const_bits
->u32
<< 16);
2262 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2264 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2268 if (dst
.regClass() == s1
) {
2269 if (instr
->op
== nir_op_ubfe
)
2270 opcode
= aco_opcode::s_bfe_u32
;
2272 opcode
= aco_opcode::s_bfe_i32
;
2273 } else if (dst
.regClass() == s2
) {
2274 if (instr
->op
== nir_op_ubfe
)
2275 opcode
= aco_opcode::s_bfe_u64
;
2277 opcode
= aco_opcode::s_bfe_i64
;
2279 unreachable("Unsupported BFE bit size");
2282 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2286 if (dst
.regClass() == v1
) {
2287 if (instr
->op
== nir_op_ubfe
)
2288 opcode
= aco_opcode::v_bfe_u32
;
2290 opcode
= aco_opcode::v_bfe_i32
;
2292 unreachable("Unsupported BFE bit size");
2295 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2299 case nir_op_bit_count
: {
2300 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2301 if (src
.regClass() == s1
) {
2302 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2303 } else if (src
.regClass() == v1
) {
2304 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2305 } else if (src
.regClass() == v2
) {
2306 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2307 emit_extract_vector(ctx
, src
, 1, v1
),
2308 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2309 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2310 } else if (src
.regClass() == s2
) {
2311 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2313 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2314 nir_print_instr(&instr
->instr
, stderr
);
2315 fprintf(stderr
, "\n");
2320 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2324 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2328 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2332 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2336 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2340 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2344 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2345 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2347 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
, aco_opcode::s_cmp_eq_u64
);
2351 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2352 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2354 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
, aco_opcode::s_cmp_lg_u64
);
2358 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2362 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2367 case nir_op_fddx_fine
:
2368 case nir_op_fddy_fine
:
2369 case nir_op_fddx_coarse
:
2370 case nir_op_fddy_coarse
: {
2371 Definition tl
= bld
.def(v1
);
2373 if (instr
->op
== nir_op_fddx_fine
) {
2374 bld
.vop1_dpp(aco_opcode::v_mov_b32
, tl
, get_alu_src(ctx
, instr
->src
[0]), dpp_quad_perm(0, 0, 2, 2));
2375 dpp_ctrl
= dpp_quad_perm(1, 1, 3, 3);
2376 } else if (instr
->op
== nir_op_fddy_fine
) {
2377 bld
.vop1_dpp(aco_opcode::v_mov_b32
, tl
, get_alu_src(ctx
, instr
->src
[0]), dpp_quad_perm(0, 1, 0, 1));
2378 dpp_ctrl
= dpp_quad_perm(2, 3, 2, 3);
2380 bld
.vop1_dpp(aco_opcode::v_mov_b32
, tl
, get_alu_src(ctx
, instr
->src
[0]), dpp_quad_perm(0, 0, 0, 0));
2381 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2382 dpp_ctrl
= dpp_quad_perm(1, 1, 1, 1);
2384 dpp_ctrl
= dpp_quad_perm(2, 2, 2, 2);
2387 Definition tmp
= bld
.def(v1
);
2388 bld
.vop2_dpp(aco_opcode::v_sub_f32
, tmp
, get_alu_src(ctx
, instr
->src
[0]), tl
.getTemp(), dpp_ctrl
);
2389 emit_wqm(ctx
, tmp
.getTemp(), dst
, true);
2393 fprintf(stderr
, "Unknown NIR ALU instr: ");
2394 nir_print_instr(&instr
->instr
, stderr
);
2395 fprintf(stderr
, "\n");
2399 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2401 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2403 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2404 // which get truncated the lsb if double and msb if int
2405 // for now, we only use s_mov_b64 with 64bit inline constants
2406 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2407 assert(dst
.type() == RegType::sgpr
);
2409 Builder
bld(ctx
->program
, ctx
->block
);
2411 if (instr
->def
.bit_size
== 1) {
2412 assert(dst
.regClass() == bld
.lm
);
2413 int val
= instr
->value
[0].b
? -1 : 0;
2414 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2415 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2416 } else if (dst
.size() == 1) {
2417 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2419 assert(dst
.size() != 1);
2420 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2421 if (instr
->def
.bit_size
== 64)
2422 for (unsigned i
= 0; i
< dst
.size(); i
++)
2423 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2425 for (unsigned i
= 0; i
< dst
.size(); i
++)
2426 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2428 vec
->definitions
[0] = Definition(dst
);
2429 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2433 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2435 uint32_t new_mask
= 0;
2436 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2437 if (mask
& (1u << i
))
2438 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2442 void visit_store_vs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2444 /* This wouldn't work inside control flow or with indirect offsets but
2445 * that doesn't happen because of nir_lower_io_to_temporaries(). */
2447 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2448 unsigned component
= nir_intrinsic_component(instr
);
2449 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2450 unsigned idx
= nir_intrinsic_base(instr
) + component
;
2452 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
2453 if (off_instr
->type
!= nir_instr_type_load_const
) {
2454 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
2455 nir_print_instr(off_instr
, stderr
);
2456 fprintf(stderr
, "\n");
2458 idx
+= nir_instr_as_load_const(off_instr
)->value
[0].u32
* 4u;
2460 if (instr
->src
[0].ssa
->bit_size
== 64)
2461 write_mask
= widen_mask(write_mask
, 2);
2463 for (unsigned i
= 0; i
< 8; ++i
) {
2464 if (write_mask
& (1 << i
)) {
2465 ctx
->vs_output
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
2466 ctx
->vs_output
.outputs
[idx
/ 4u][idx
% 4u] = emit_extract_vector(ctx
, src
, i
, v1
);
2472 void visit_store_fs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2474 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
2476 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2477 for (unsigned i
= 0; i
< 4; ++i
) {
2478 if (write_mask
& (1 << i
)) {
2479 Temp tmp
= emit_extract_vector(ctx
, src
, i
, v1
);
2480 values
[i
] = Operand(tmp
);
2482 values
[i
] = Operand(v1
);
2486 unsigned index
= nir_intrinsic_base(instr
) / 4;
2487 unsigned target
, col_format
;
2488 unsigned enabled_channels
= 0xF;
2489 aco_opcode compr_op
= (aco_opcode
)0;
2491 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
2492 assert(offset
&& "Non-const offsets on exports not yet supported");
2493 index
+= offset
->u32
;
2495 assert(index
!= FRAG_RESULT_COLOR
);
2497 /* Unlike vertex shader exports, it's fine to use multiple exports to
2498 * export separate channels of one target. So shaders which export both
2499 * FRAG_RESULT_SAMPLE_MASK and FRAG_RESULT_DEPTH should work fine.
2500 * TODO: combine the exports in those cases and create better code
2503 if (index
== FRAG_RESULT_SAMPLE_MASK
) {
2505 if (ctx
->program
->info
->ps
.writes_z
) {
2506 target
= V_008DFC_SQ_EXP_MRTZ
;
2507 enabled_channels
= 0x4;
2508 col_format
= (unsigned) -1;
2510 values
[2] = values
[0];
2511 values
[0] = Operand(v1
);
2513 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
2514 exp
->valid_mask
= false;
2516 exp
->compressed
= true;
2517 exp
->dest
= V_008DFC_SQ_EXP_MRTZ
;
2518 exp
->enabled_mask
= 0xc;
2519 for (int i
= 0; i
< 4; i
++)
2520 exp
->operands
[i
] = Operand(v1
);
2521 exp
->operands
[1] = Operand(values
[0]);
2522 ctx
->block
->instructions
.emplace_back(std::move(exp
));
2526 } else if (index
== FRAG_RESULT_DEPTH
) {
2528 target
= V_008DFC_SQ_EXP_MRTZ
;
2529 enabled_channels
= 0x1;
2530 col_format
= (unsigned) -1;
2532 } else if (index
== FRAG_RESULT_STENCIL
) {
2534 if (ctx
->program
->info
->ps
.writes_z
) {
2535 target
= V_008DFC_SQ_EXP_MRTZ
;
2536 enabled_channels
= 0x2;
2537 col_format
= (unsigned) -1;
2539 values
[1] = values
[0];
2540 values
[0] = Operand(v1
);
2542 aco_ptr
<Instruction
> shift
{create_instruction
<VOP2_instruction
>(aco_opcode::v_lshlrev_b32
, Format::VOP2
, 2, 1)};
2543 shift
->operands
[0] = Operand((uint32_t) 16);
2544 shift
->operands
[1] = values
[0];
2545 Temp tmp
= {ctx
->program
->allocateId(), v1
};
2546 shift
->definitions
[0] = Definition(tmp
);
2547 ctx
->block
->instructions
.emplace_back(std::move(shift
));
2549 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
2550 exp
->valid_mask
= false;
2552 exp
->compressed
= true;
2553 exp
->dest
= V_008DFC_SQ_EXP_MRTZ
;
2554 exp
->enabled_mask
= 0x3;
2555 exp
->operands
[0] = Operand(tmp
);
2556 for (int i
= 1; i
< 4; i
++)
2557 exp
->operands
[i
] = Operand(v1
);
2558 ctx
->block
->instructions
.emplace_back(std::move(exp
));
2563 index
-= FRAG_RESULT_DATA0
;
2564 target
= V_008DFC_SQ_EXP_MRT
+ index
;
2565 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2567 ASSERTED
bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2568 ASSERTED
bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2569 assert(!is_int8
&& !is_int10
);
2573 case V_028714_SPI_SHADER_ZERO
:
2574 enabled_channels
= 0; /* writemask */
2575 target
= V_008DFC_SQ_EXP_NULL
;
2578 case V_028714_SPI_SHADER_32_R
:
2579 enabled_channels
= 1;
2582 case V_028714_SPI_SHADER_32_GR
:
2583 enabled_channels
= 0x3;
2586 case V_028714_SPI_SHADER_32_AR
:
2587 if (ctx
->options
->chip_class
>= GFX10
) {
2588 /* Special case: on GFX10, the outputs are different for 32_AR */
2589 enabled_channels
= 0x3;
2590 values
[1] = values
[3];
2592 enabled_channels
= 0x9;
2596 case V_028714_SPI_SHADER_FP16_ABGR
:
2597 enabled_channels
= 0x5;
2598 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
2601 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2602 enabled_channels
= 0x5;
2603 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
2606 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2607 enabled_channels
= 0x5;
2608 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
2611 case V_028714_SPI_SHADER_UINT16_ABGR
:
2612 enabled_channels
= 0x5;
2613 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
2616 case V_028714_SPI_SHADER_SINT16_ABGR
:
2617 enabled_channels
= 0x5;
2618 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
2621 case V_028714_SPI_SHADER_32_ABGR
:
2622 enabled_channels
= 0xF;
2629 if (target
== V_008DFC_SQ_EXP_NULL
)
2634 for (int i
= 0; i
< 2; i
++)
2636 /* check if at least one of the values to be compressed is enabled */
2637 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
2639 enabled_channels
|= enabled
<< (i
*2);
2640 aco_ptr
<VOP3A_instruction
> compr
{create_instruction
<VOP3A_instruction
>(compr_op
, Format::VOP3A
, 2, 1)};
2641 Temp tmp
{ctx
->program
->allocateId(), v1
};
2642 compr
->operands
[0] = values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2];
2643 compr
->operands
[1] = values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1];
2644 compr
->definitions
[0] = Definition(tmp
);
2645 values
[i
] = Operand(tmp
);
2646 ctx
->block
->instructions
.emplace_back(std::move(compr
));
2648 values
[i
] = Operand(v1
);
2653 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
2654 exp
->valid_mask
= false;
2656 exp
->compressed
= (bool) compr_op
;
2658 exp
->enabled_mask
= enabled_channels
;
2659 if ((bool) compr_op
) {
2660 for (int i
= 0; i
< 2; i
++)
2661 exp
->operands
[i
] = enabled_channels
& (3 << (i
* 2)) ? values
[i
] : Operand(v1
);
2662 exp
->operands
[2] = Operand(v1
);
2663 exp
->operands
[3] = Operand(v1
);
2665 for (int i
= 0; i
< 4; i
++)
2666 exp
->operands
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
2669 ctx
->block
->instructions
.emplace_back(std::move(exp
));
2672 Operand
load_lds_size_m0(isel_context
*ctx
)
2674 /* TODO: m0 does not need to be initialized on GFX9+ */
2675 Builder
bld(ctx
->program
, ctx
->block
);
2676 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
2679 void load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
2680 Temp address
, unsigned base_offset
, unsigned align
)
2682 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2684 Builder
bld(ctx
->program
, ctx
->block
);
2686 Operand m
= load_lds_size_m0(ctx
);
2688 unsigned num_components
= dst
.size() * 4u / elem_size_bytes
;
2689 unsigned bytes_read
= 0;
2690 unsigned result_size
= 0;
2691 unsigned total_bytes
= num_components
* elem_size_bytes
;
2692 std::array
<Temp
, 4> result
;
2694 while (bytes_read
< total_bytes
) {
2695 unsigned todo
= total_bytes
- bytes_read
;
2696 bool aligned8
= bytes_read
% 8 == 0 && align
% 8 == 0;
2697 bool aligned16
= bytes_read
% 16 == 0 && align
% 16 == 0;
2699 aco_opcode op
= aco_opcode::last_opcode
;
2701 if (todo
>= 16 && aligned16
) {
2702 op
= aco_opcode::ds_read_b128
;
2704 } else if (todo
>= 16 && aligned8
) {
2705 op
= aco_opcode::ds_read2_b64
;
2708 } else if (todo
>= 12 && aligned16
) {
2709 op
= aco_opcode::ds_read_b96
;
2711 } else if (todo
>= 8 && aligned8
) {
2712 op
= aco_opcode::ds_read_b64
;
2714 } else if (todo
>= 8) {
2715 op
= aco_opcode::ds_read2_b32
;
2718 } else if (todo
>= 4) {
2719 op
= aco_opcode::ds_read_b32
;
2724 assert(todo
% elem_size_bytes
== 0);
2725 unsigned num_elements
= todo
/ elem_size_bytes
;
2726 unsigned offset
= base_offset
+ bytes_read
;
2727 unsigned max_offset
= read2
? 1019 : 65535;
2729 Temp address_offset
= address
;
2730 if (offset
> max_offset
) {
2731 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2732 offset
= bytes_read
;
2734 assert(offset
<= max_offset
); /* bytes_read shouldn't be large enough for this to happen */
2737 if (num_components
== 1 && dst
.type() == RegType::vgpr
)
2740 res
= bld
.tmp(RegClass(RegType::vgpr
, todo
/ 4));
2743 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
>> 2, (offset
>> 2) + 1);
2745 res
= bld
.ds(op
, Definition(res
), address_offset
, m
, offset
);
2747 if (num_components
== 1) {
2748 assert(todo
== total_bytes
);
2749 if (dst
.type() == RegType::sgpr
)
2750 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
2754 if (dst
.type() == RegType::sgpr
)
2755 res
= bld
.as_uniform(res
);
2757 if (num_elements
== 1) {
2758 result
[result_size
++] = res
;
2760 assert(res
!= dst
&& res
.size() % num_elements
== 0);
2761 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_elements
)};
2762 split
->operands
[0] = Operand(res
);
2763 for (unsigned i
= 0; i
< num_elements
; i
++)
2764 split
->definitions
[i
] = Definition(result
[result_size
++] = bld
.tmp(res
.type(), elem_size_bytes
/ 4));
2765 ctx
->block
->instructions
.emplace_back(std::move(split
));
2771 assert(result_size
== num_components
&& result_size
> 1);
2772 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, result_size
, 1)};
2773 for (unsigned i
= 0; i
< result_size
; i
++)
2774 vec
->operands
[i
] = Operand(result
[i
]);
2775 vec
->definitions
[0] = Definition(dst
);
2776 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2777 ctx
->allocated_vec
.emplace(dst
.id(), result
);
2780 Temp
extract_subvector(isel_context
*ctx
, Temp data
, unsigned start
, unsigned size
, RegType type
)
2782 if (start
== 0 && size
== data
.size())
2783 return type
== RegType::vgpr
? as_vgpr(ctx
, data
) : data
;
2785 unsigned size_hint
= 1;
2786 auto it
= ctx
->allocated_vec
.find(data
.id());
2787 if (it
!= ctx
->allocated_vec
.end())
2788 size_hint
= it
->second
[0].size();
2789 if (size
% size_hint
|| start
% size_hint
)
2796 for (unsigned i
= 0; i
< size
; i
++)
2797 elems
[i
] = emit_extract_vector(ctx
, data
, start
+ i
, RegClass(type
, size_hint
));
2800 return type
== RegType::vgpr
? as_vgpr(ctx
, elems
[0]) : elems
[0];
2802 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
2803 for (unsigned i
= 0; i
< size
; i
++)
2804 vec
->operands
[i
] = Operand(elems
[i
]);
2805 Temp res
= {ctx
->program
->allocateId(), RegClass(type
, size
* size_hint
)};
2806 vec
->definitions
[0] = Definition(res
);
2807 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2811 void ds_write_helper(isel_context
*ctx
, Operand m
, Temp address
, Temp data
, unsigned data_start
, unsigned total_size
, unsigned offset0
, unsigned offset1
, unsigned align
)
2813 Builder
bld(ctx
->program
, ctx
->block
);
2814 unsigned bytes_written
= 0;
2815 while (bytes_written
< total_size
* 4) {
2816 unsigned todo
= total_size
* 4 - bytes_written
;
2817 bool aligned8
= bytes_written
% 8 == 0 && align
% 8 == 0;
2818 bool aligned16
= bytes_written
% 16 == 0 && align
% 16 == 0;
2820 aco_opcode op
= aco_opcode::last_opcode
;
2821 bool write2
= false;
2823 if (todo
>= 16 && aligned16
) {
2824 op
= aco_opcode::ds_write_b128
;
2826 } else if (todo
>= 16 && aligned8
) {
2827 op
= aco_opcode::ds_write2_b64
;
2830 } else if (todo
>= 12 && aligned16
) {
2831 op
= aco_opcode::ds_write_b96
;
2833 } else if (todo
>= 8 && aligned8
) {
2834 op
= aco_opcode::ds_write_b64
;
2836 } else if (todo
>= 8) {
2837 op
= aco_opcode::ds_write2_b32
;
2840 } else if (todo
>= 4) {
2841 op
= aco_opcode::ds_write_b32
;
2847 unsigned offset
= offset0
+ offset1
+ bytes_written
;
2848 unsigned max_offset
= write2
? 1020 : 65535;
2849 Temp address_offset
= address
;
2850 if (offset
> max_offset
) {
2851 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(offset0
), address_offset
);
2852 offset
= offset1
+ bytes_written
;
2854 assert(offset
<= max_offset
); /* offset1 shouldn't be large enough for this to happen */
2857 Temp val0
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
/ 2, RegType::vgpr
);
2858 Temp val1
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2) + 1, size
/ 2, RegType::vgpr
);
2859 bld
.ds(op
, address_offset
, val0
, val1
, m
, offset
>> 2, (offset
>> 2) + 1);
2861 Temp val
= extract_subvector(ctx
, data
, data_start
+ (bytes_written
>> 2), size
, RegType::vgpr
);
2862 bld
.ds(op
, address_offset
, val
, m
, offset
);
2865 bytes_written
+= size
* 4;
2869 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
2870 Temp address
, unsigned base_offset
, unsigned align
)
2872 assert(util_is_power_of_two_nonzero(align
) && align
>= 4);
2874 Operand m
= load_lds_size_m0(ctx
);
2876 /* we need at most two stores for 32bit variables */
2877 int start
[2], count
[2];
2878 u_bit_scan_consecutive_range(&wrmask
, &start
[0], &count
[0]);
2879 u_bit_scan_consecutive_range(&wrmask
, &start
[1], &count
[1]);
2880 assert(wrmask
== 0);
2882 /* one combined store is sufficient */
2883 if (count
[0] == count
[1]) {
2884 Builder
bld(ctx
->program
, ctx
->block
);
2886 Temp address_offset
= address
;
2887 if ((base_offset
>> 2) + start
[1] > 255) {
2888 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
2892 assert(count
[0] == 1);
2893 Temp val0
= emit_extract_vector(ctx
, data
, start
[0], v1
);
2894 Temp val1
= emit_extract_vector(ctx
, data
, start
[1], v1
);
2895 aco_opcode op
= elem_size_bytes
== 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
2896 base_offset
= base_offset
/ elem_size_bytes
;
2897 bld
.ds(op
, address_offset
, val0
, val1
, m
,
2898 base_offset
+ start
[0], base_offset
+ start
[1]);
2902 for (unsigned i
= 0; i
< 2; i
++) {
2906 unsigned elem_size_words
= elem_size_bytes
/ 4;
2907 ds_write_helper(ctx
, m
, address
, data
, start
[i
] * elem_size_words
, count
[i
] * elem_size_words
,
2908 base_offset
, start
[i
] * elem_size_bytes
, align
);
2913 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2915 if (ctx
->stage
== vertex_vs
) {
2916 visit_store_vs_output(ctx
, instr
);
2917 } else if (ctx
->stage
== fragment_fs
) {
2918 visit_store_fs_output(ctx
, instr
);
2920 unreachable("Shader stage not implemented");
2924 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
2926 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
2927 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
2929 Builder
bld(ctx
->program
, ctx
->block
);
2930 Temp tmp
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
2931 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), tmp
, idx
, component
);
2934 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
2936 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
2937 for (unsigned i
= 0; i
< num_components
; i
++)
2938 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
2939 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
2940 assert(num_components
== 4);
2941 Builder
bld(ctx
->program
, ctx
->block
);
2942 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
2945 for (Operand
& op
: vec
->operands
)
2946 op
= op
.isUndefined() ? Operand(0u) : op
;
2948 vec
->definitions
[0] = Definition(dst
);
2949 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2950 emit_split_vector(ctx
, dst
, num_components
);
2954 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
2956 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
2957 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
2958 unsigned idx
= nir_intrinsic_base(instr
);
2959 unsigned component
= nir_intrinsic_component(instr
);
2960 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
2962 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
2964 assert(offset
->u32
== 0);
2966 /* the lower 15bit of the prim_mask contain the offset into LDS
2967 * while the upper bits contain the number of prims */
2968 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
2969 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
2970 Builder
bld(ctx
->program
, ctx
->block
);
2971 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
2972 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
2973 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
2974 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
2975 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
2978 if (instr
->dest
.ssa
.num_components
== 1) {
2979 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
2981 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
2982 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
2984 Temp tmp
= {ctx
->program
->allocateId(), v1
};
2985 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
2986 vec
->operands
[i
] = Operand(tmp
);
2988 vec
->definitions
[0] = Definition(dst
);
2989 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2993 unsigned get_num_channels_from_data_format(unsigned data_format
)
2995 switch (data_format
) {
2996 case V_008F0C_BUF_DATA_FORMAT_8
:
2997 case V_008F0C_BUF_DATA_FORMAT_16
:
2998 case V_008F0C_BUF_DATA_FORMAT_32
:
3000 case V_008F0C_BUF_DATA_FORMAT_8_8
:
3001 case V_008F0C_BUF_DATA_FORMAT_16_16
:
3002 case V_008F0C_BUF_DATA_FORMAT_32_32
:
3004 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
3005 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
3006 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
3008 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
3009 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
3010 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
3011 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
3012 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
3021 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
3022 * so we may need to fix it up. */
3023 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
3025 Builder
bld(ctx
->program
, ctx
->block
);
3027 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
3028 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
3030 /* For the integer-like cases, do a natural sign extension.
3032 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
3033 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
3036 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
3037 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
3039 /* Convert back to the right type. */
3040 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
3041 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3042 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
3043 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
3044 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
3045 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
3051 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3053 Builder
bld(ctx
->program
, ctx
->block
);
3054 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3055 if (ctx
->stage
& sw_vs
) {
3057 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3058 if (off_instr
->type
!= nir_instr_type_load_const
) {
3059 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3060 nir_print_instr(off_instr
, stderr
);
3061 fprintf(stderr
, "\n");
3063 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
3065 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
3067 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
3068 unsigned component
= nir_intrinsic_component(instr
);
3069 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
3070 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
3071 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
3072 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
3074 unsigned dfmt
= attrib_format
& 0xf;
3076 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
3077 unsigned num_dfmt_channels
= get_num_channels_from_data_format(dfmt
);
3078 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
3079 unsigned num_channels
= MIN2(util_last_bit(mask
), num_dfmt_channels
);
3080 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
3081 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
3083 num_channels
= MAX2(num_channels
, 3);
3085 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, Operand(attrib_binding
* 16u));
3088 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
3089 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
3090 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
3092 ctx
->needs_instance_id
= true;
3093 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
3095 Temp divided
= bld
.tmp(v1
);
3096 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
3097 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
3099 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
3102 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
3105 index
= bld
.vadd32(bld
.def(v1
),
3106 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
3107 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
3110 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
3111 index
= bld
.vadd32(bld
.def(v1
), Operand(attrib_offset
/ attrib_stride
), index
);
3112 attrib_offset
= attrib_offset
% attrib_stride
;
3115 Operand
soffset(0u);
3116 if (attrib_offset
>= 4096) {
3117 soffset
= bld
.copy(bld
.def(s1
), Operand(attrib_offset
));
3122 switch (num_channels
) {
3124 opcode
= aco_opcode::tbuffer_load_format_x
;
3127 opcode
= aco_opcode::tbuffer_load_format_xy
;
3130 opcode
= aco_opcode::tbuffer_load_format_xyz
;
3133 opcode
= aco_opcode::tbuffer_load_format_xyzw
;
3136 unreachable("Unimplemented load_input vector size");
3139 Temp tmp
= post_shuffle
|| num_channels
!= dst
.size() || alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
|| component
? bld
.tmp(RegType::vgpr
, num_channels
) : dst
;
3141 aco_ptr
<MTBUF_instruction
> mubuf
{create_instruction
<MTBUF_instruction
>(opcode
, Format::MTBUF
, 3, 1)};
3142 mubuf
->operands
[0] = Operand(index
);
3143 mubuf
->operands
[1] = Operand(list
);
3144 mubuf
->operands
[2] = soffset
;
3145 mubuf
->definitions
[0] = Definition(tmp
);
3146 mubuf
->idxen
= true;
3147 mubuf
->can_reorder
= true;
3150 assert(attrib_offset
< 4096);
3151 mubuf
->offset
= attrib_offset
;
3152 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
3154 emit_split_vector(ctx
, tmp
, tmp
.size());
3156 if (tmp
.id() != dst
.id()) {
3157 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
3158 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
3160 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
3161 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
3162 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
3164 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3165 for (unsigned i
= 0; i
< dst
.size(); i
++) {
3166 unsigned idx
= i
+ component
;
3167 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
&& num_channels
>= 4) {
3168 Temp alpha
= emit_extract_vector(ctx
, tmp
, swizzle
[3], v1
);
3169 vec
->operands
[3] = Operand(adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, alpha
));
3170 } else if (idx
< num_channels
) {
3171 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, tmp
, swizzle
[idx
], v1
));
3172 } else if (is_float
&& idx
== 3) {
3173 vec
->operands
[i
] = Operand(0x3f800000u
);
3174 } else if (!is_float
&& idx
== 3) {
3175 vec
->operands
[i
] = Operand(1u);
3177 vec
->operands
[i
] = Operand(0u);
3180 vec
->definitions
[0] = Definition(dst
);
3181 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3182 emit_split_vector(ctx
, dst
, dst
.size());
3185 } else if (ctx
->stage
== fragment_fs
) {
3186 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
3187 if (off_instr
->type
!= nir_instr_type_load_const
||
3188 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
3189 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
3190 nir_print_instr(off_instr
, stderr
);
3191 fprintf(stderr
, "\n");
3194 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
3195 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[0]);
3197 assert(offset
->u32
== 0);
3199 /* the lower 15bit of the prim_mask contain the offset into LDS
3200 * while the upper bits contain the number of prims */
3201 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3202 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
3203 Builder
bld(ctx
->program
, ctx
->block
);
3204 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
3205 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
3206 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
3207 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
3208 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
3211 unsigned idx
= nir_intrinsic_base(instr
);
3212 unsigned component
= nir_intrinsic_component(instr
);
3214 if (dst
.size() == 1) {
3215 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(2u), bld
.m0(prim_mask
), idx
, component
);
3217 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3218 for (unsigned i
= 0; i
< dst
.size(); i
++)
3219 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(2u), bld
.m0(prim_mask
), idx
, component
+ i
);
3220 vec
->definitions
[0] = Definition(dst
);
3221 bld
.insert(std::move(vec
));
3225 unreachable("Shader stage not implemented");
3229 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
3231 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
3232 Builder
bld(ctx
->program
, ctx
->block
);
3233 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
3234 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, Operand(desc_set
<< 2));//, false, false, false);
3237 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
3241 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3243 Builder
bld(ctx
->program
, ctx
->block
);
3244 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3245 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
3246 index
= bld
.as_uniform(index
);
3247 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
3248 unsigned binding
= nir_intrinsic_binding(instr
);
3251 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
3252 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
3253 unsigned offset
= layout
->binding
[binding
].offset
;
3255 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
3256 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
3257 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
3258 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
3259 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
3262 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
3263 stride
= layout
->binding
[binding
].size
;
3266 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
3267 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
3269 if (nir_const_index
) {
3270 const_index
= const_index
* stride
;
3271 } else if (index
.type() == RegType::vgpr
) {
3272 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
3273 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
3275 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
3279 if (nir_const_index
) {
3280 const_index
= const_index
+ offset
;
3281 } else if (index
.type() == RegType::vgpr
) {
3282 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
3284 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
3288 if (nir_const_index
&& const_index
== 0) {
3290 } else if (index
.type() == RegType::vgpr
) {
3291 index
= bld
.vadd32(bld
.def(v1
),
3292 nir_const_index
? Operand(const_index
) : Operand(index
),
3295 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3296 nir_const_index
? Operand(const_index
) : Operand(index
),
3300 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
3303 void load_buffer(isel_context
*ctx
, unsigned num_components
, Temp dst
,
3304 Temp rsrc
, Temp offset
, bool glc
=false, bool readonly
=true)
3306 Builder
bld(ctx
->program
, ctx
->block
);
3308 unsigned num_bytes
= dst
.size() * 4;
3309 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
3312 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
3313 if (ctx
->options
->chip_class
< GFX8
)
3314 offset
= as_vgpr(ctx
, offset
);
3316 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3317 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3318 unsigned const_offset
= 0;
3320 Temp lower
= Temp();
3321 if (num_bytes
> 16) {
3322 assert(num_components
== 3 || num_components
== 4);
3323 op
= aco_opcode::buffer_load_dwordx4
;
3324 lower
= bld
.tmp(v4
);
3325 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3326 mubuf
->definitions
[0] = Definition(lower
);
3327 mubuf
->operands
[0] = vaddr
;
3328 mubuf
->operands
[1] = Operand(rsrc
);
3329 mubuf
->operands
[2] = soffset
;
3330 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3333 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3334 mubuf
->can_reorder
= readonly
;
3335 bld
.insert(std::move(mubuf
));
3336 emit_split_vector(ctx
, lower
, 2);
3341 switch (num_bytes
) {
3343 op
= aco_opcode::buffer_load_dword
;
3346 op
= aco_opcode::buffer_load_dwordx2
;
3349 op
= aco_opcode::buffer_load_dwordx3
;
3352 op
= aco_opcode::buffer_load_dwordx4
;
3355 unreachable("Load SSBO not implemented for this size.");
3357 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3358 mubuf
->operands
[0] = vaddr
;
3359 mubuf
->operands
[1] = Operand(rsrc
);
3360 mubuf
->operands
[2] = soffset
;
3361 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3364 mubuf
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3365 mubuf
->can_reorder
= readonly
;
3366 mubuf
->offset
= const_offset
;
3367 aco_ptr
<Instruction
> instr
= std::move(mubuf
);
3369 if (dst
.size() > 4) {
3370 assert(lower
!= Temp());
3371 Temp upper
= bld
.tmp(RegType::vgpr
, dst
.size() - lower
.size());
3372 instr
->definitions
[0] = Definition(upper
);
3373 bld
.insert(std::move(instr
));
3374 if (dst
.size() == 8)
3375 emit_split_vector(ctx
, upper
, 2);
3376 instr
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size() / 2, 1));
3377 instr
->operands
[0] = Operand(emit_extract_vector(ctx
, lower
, 0, v2
));
3378 instr
->operands
[1] = Operand(emit_extract_vector(ctx
, lower
, 1, v2
));
3379 instr
->operands
[2] = Operand(emit_extract_vector(ctx
, upper
, 0, v2
));
3380 if (dst
.size() == 8)
3381 instr
->operands
[3] = Operand(emit_extract_vector(ctx
, upper
, 1, v2
));
3384 if (dst
.type() == RegType::sgpr
) {
3385 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
3386 instr
->definitions
[0] = Definition(vec
);
3387 bld
.insert(std::move(instr
));
3388 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
3390 instr
->definitions
[0] = Definition(dst
);
3391 bld
.insert(std::move(instr
));
3394 switch (num_bytes
) {
3396 op
= aco_opcode::s_buffer_load_dword
;
3399 op
= aco_opcode::s_buffer_load_dwordx2
;
3403 op
= aco_opcode::s_buffer_load_dwordx4
;
3407 op
= aco_opcode::s_buffer_load_dwordx8
;
3410 unreachable("Load SSBO not implemented for this size.");
3412 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3413 load
->operands
[0] = Operand(rsrc
);
3414 load
->operands
[1] = Operand(bld
.as_uniform(offset
));
3415 assert(load
->operands
[1].getTemp().type() == RegType::sgpr
);
3416 load
->definitions
[0] = Definition(dst
);
3419 load
->barrier
= readonly
? barrier_none
: barrier_buffer
;
3420 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3421 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
3424 if (dst
.size() == 3) {
3425 Temp vec
= bld
.tmp(s4
);
3426 load
->definitions
[0] = Definition(vec
);
3427 bld
.insert(std::move(load
));
3428 emit_split_vector(ctx
, vec
, 4);
3430 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3431 emit_extract_vector(ctx
, vec
, 0, s1
),
3432 emit_extract_vector(ctx
, vec
, 1, s1
),
3433 emit_extract_vector(ctx
, vec
, 2, s1
));
3434 } else if (dst
.size() == 6) {
3435 Temp vec
= bld
.tmp(s8
);
3436 load
->definitions
[0] = Definition(vec
);
3437 bld
.insert(std::move(load
));
3438 emit_split_vector(ctx
, vec
, 4);
3440 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3441 emit_extract_vector(ctx
, vec
, 0, s2
),
3442 emit_extract_vector(ctx
, vec
, 1, s2
),
3443 emit_extract_vector(ctx
, vec
, 2, s2
));
3445 bld
.insert(std::move(load
));
3449 emit_split_vector(ctx
, dst
, num_components
);
3452 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3454 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3455 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3457 Builder
bld(ctx
->program
, ctx
->block
);
3459 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3460 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
3461 unsigned binding
= nir_intrinsic_binding(idx_instr
);
3462 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
3464 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
3465 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3466 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3467 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3468 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3469 if (ctx
->options
->chip_class
>= GFX10
) {
3470 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3471 S_008F0C_OOB_SELECT(3) |
3472 S_008F0C_RESOURCE_LEVEL(1);
3474 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3477 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
3478 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
3479 Operand(0xFFFFFFFFu
),
3480 Operand(desc_type
));
3481 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3482 rsrc
, upper_dwords
);
3484 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
3485 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
3488 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
3491 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3493 Builder
bld(ctx
->program
, ctx
->block
);
3494 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3496 unsigned offset
= nir_intrinsic_base(instr
);
3497 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
3498 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
3500 unsigned count
= instr
->dest
.ssa
.num_components
;
3501 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
3502 start
-= ctx
->args
->ac
.base_inline_push_consts
;
3503 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
3504 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
3505 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
3506 for (unsigned i
= 0; i
< count
; ++i
) {
3507 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
3508 vec
->operands
[i
] = Operand
{elems
[i
]};
3510 vec
->definitions
[0] = Definition(dst
);
3511 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3512 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
3517 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
3518 if (offset
!= 0) // TODO check if index != 0 as well
3519 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
3520 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
3525 switch (dst
.size()) {
3527 op
= aco_opcode::s_load_dword
;
3530 op
= aco_opcode::s_load_dwordx2
;
3536 op
= aco_opcode::s_load_dwordx4
;
3542 op
= aco_opcode::s_load_dwordx8
;
3545 unreachable("unimplemented or forbidden load_push_constant.");
3548 bld
.smem(op
, Definition(vec
), ptr
, index
);
3551 emit_split_vector(ctx
, vec
, 4);
3552 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
3553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
3554 emit_extract_vector(ctx
, vec
, 0, rc
),
3555 emit_extract_vector(ctx
, vec
, 1, rc
),
3556 emit_extract_vector(ctx
, vec
, 2, rc
));
3559 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
3562 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3564 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
3566 Builder
bld(ctx
->program
, ctx
->block
);
3568 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3569 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3570 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3571 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3572 if (ctx
->options
->chip_class
>= GFX10
) {
3573 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3574 S_008F0C_OOB_SELECT(3) |
3575 S_008F0C_RESOURCE_LEVEL(1);
3577 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3578 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3581 unsigned base
= nir_intrinsic_base(instr
);
3582 unsigned range
= nir_intrinsic_range(instr
);
3584 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3585 if (base
&& offset
.type() == RegType::sgpr
)
3586 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
3587 else if (base
&& offset
.type() == RegType::vgpr
)
3588 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
3590 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3591 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
3592 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
3593 Operand(desc_type
));
3595 load_buffer(ctx
, instr
->num_components
, dst
, rsrc
, offset
);
3598 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3600 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3601 ctx
->cf_info
.exec_potentially_empty
= true;
3603 ctx
->program
->needs_exact
= true;
3605 // TODO: optimize uniform conditions
3606 Builder
bld(ctx
->program
, ctx
->block
);
3607 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
3608 assert(src
.regClass() == bld
.lm
);
3609 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
3610 bld
.pseudo(aco_opcode::p_discard_if
, src
);
3611 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3615 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
3617 Builder
bld(ctx
->program
, ctx
->block
);
3619 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
3620 ctx
->cf_info
.exec_potentially_empty
= true;
3622 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
3623 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
3625 if (ctx
->block
->loop_nest_depth
&&
3626 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
3627 /* we handle discards the same way as jump instructions */
3628 append_logical_end(ctx
->block
);
3630 /* in loops, discard behaves like break */
3631 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
3632 ctx
->block
->kind
|= block_kind_discard
;
3635 /* uniform discard - loop ends here */
3636 assert(nir_instr_is_last(&instr
->instr
));
3637 ctx
->block
->kind
|= block_kind_uniform
;
3638 ctx
->cf_info
.has_branch
= true;
3639 bld
.branch(aco_opcode::p_branch
);
3640 add_linear_edge(ctx
->block
->index
, linear_target
);
3644 /* we add a break right behind the discard() instructions */
3645 ctx
->block
->kind
|= block_kind_break
;
3646 unsigned idx
= ctx
->block
->index
;
3648 /* remove critical edges from linear CFG */
3649 bld
.branch(aco_opcode::p_branch
);
3650 Block
* break_block
= ctx
->program
->create_and_insert_block();
3651 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3652 break_block
->kind
|= block_kind_uniform
;
3653 add_linear_edge(idx
, break_block
);
3654 add_linear_edge(break_block
->index
, linear_target
);
3655 bld
.reset(break_block
);
3656 bld
.branch(aco_opcode::p_branch
);
3658 Block
* continue_block
= ctx
->program
->create_and_insert_block();
3659 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
3660 add_linear_edge(idx
, continue_block
);
3661 append_logical_start(continue_block
);
3662 ctx
->block
= continue_block
;
3667 /* it can currently happen that NIR doesn't remove the unreachable code */
3668 if (!nir_instr_is_last(&instr
->instr
)) {
3669 ctx
->program
->needs_exact
= true;
3670 /* save exec somewhere temporarily so that it doesn't get
3671 * overwritten before the discard from outer exec masks */
3672 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
3673 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
3674 ctx
->block
->kind
|= block_kind_uses_discard_if
;
3678 /* This condition is incorrect for uniformly branched discards in a loop
3679 * predicated by a divergent condition, but the above code catches that case
3680 * and the discard would end up turning into a discard_if.
3690 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
3691 /* program just ends here */
3692 ctx
->block
->kind
|= block_kind_uniform
;
3693 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
3694 0 /* enabled mask */, 9 /* dest */,
3695 false /* compressed */, true/* done */, true /* valid mask */);
3696 bld
.sopp(aco_opcode::s_endpgm
);
3697 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
3699 ctx
->block
->kind
|= block_kind_discard
;
3700 /* branch and linear edge is added by visit_if() */
3704 enum aco_descriptor_type
{
3715 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
3716 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3718 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
3719 return dim
== ac_image_cube
||
3720 dim
== ac_image_1darray
||
3721 dim
== ac_image_2darray
||
3722 dim
== ac_image_2darraymsaa
;
3725 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
3726 enum aco_descriptor_type desc_type
,
3727 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
3729 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
3730 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
3731 if (it != ctx->tex_desc.end())
3734 Temp index
= Temp();
3735 bool index_set
= false;
3736 unsigned constant_index
= 0;
3737 unsigned descriptor_set
;
3738 unsigned base_index
;
3739 Builder
bld(ctx
->program
, ctx
->block
);
3742 assert(tex_instr
&& !image
);
3744 base_index
= tex_instr
->sampler_index
;
3746 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
3747 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
3751 assert(deref_instr
->deref_type
== nir_deref_type_array
);
3752 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
3754 constant_index
+= array_size
* const_value
->u32
;
3756 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
3757 if (indirect
.type() == RegType::vgpr
)
3758 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
3760 if (array_size
!= 1)
3761 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
3767 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
3771 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
3773 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
3774 base_index
= deref_instr
->var
->data
.binding
;
3777 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
3778 list
= convert_pointer_to_64_bit(ctx
, list
);
3780 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
3781 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
3782 unsigned offset
= binding
->offset
;
3783 unsigned stride
= binding
->size
;
3787 assert(base_index
< layout
->binding_count
);
3789 switch (desc_type
) {
3790 case ACO_DESC_IMAGE
:
3792 opcode
= aco_opcode::s_load_dwordx8
;
3794 case ACO_DESC_FMASK
:
3796 opcode
= aco_opcode::s_load_dwordx8
;
3799 case ACO_DESC_SAMPLER
:
3801 opcode
= aco_opcode::s_load_dwordx4
;
3802 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
3803 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
3805 case ACO_DESC_BUFFER
:
3807 opcode
= aco_opcode::s_load_dwordx4
;
3809 case ACO_DESC_PLANE_0
:
3810 case ACO_DESC_PLANE_1
:
3812 opcode
= aco_opcode::s_load_dwordx8
;
3813 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
3815 case ACO_DESC_PLANE_2
:
3817 opcode
= aco_opcode::s_load_dwordx4
;
3821 unreachable("invalid desc_type\n");
3824 offset
+= constant_index
* stride
;
3826 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
3827 (!index_set
|| binding
->immutable_samplers_equal
)) {
3828 if (binding
->immutable_samplers_equal
)
3831 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
3832 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
3833 Operand(samplers
[constant_index
* 4 + 0]),
3834 Operand(samplers
[constant_index
* 4 + 1]),
3835 Operand(samplers
[constant_index
* 4 + 2]),
3836 Operand(samplers
[constant_index
* 4 + 3]));
3841 off
= Operand(offset
);
3843 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
3844 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
3847 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
3849 if (desc_type
== ACO_DESC_PLANE_2
) {
3851 for (unsigned i
= 0; i
< 8; i
++)
3852 components
[i
] = bld
.tmp(s1
);
3853 bld
.pseudo(aco_opcode::p_split_vector
,
3854 Definition(components
[0]),
3855 Definition(components
[1]),
3856 Definition(components
[2]),
3857 Definition(components
[3]),
3860 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
3861 bld
.pseudo(aco_opcode::p_split_vector
,
3862 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
3863 Definition(components
[4]),
3864 Definition(components
[5]),
3865 Definition(components
[6]),
3866 Definition(components
[7]),
3869 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
3870 components
[0], components
[1], components
[2], components
[3],
3871 components
[4], components
[5], components
[6], components
[7]);
3877 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
3880 case GLSL_SAMPLER_DIM_BUF
:
3882 case GLSL_SAMPLER_DIM_1D
:
3883 return array
? 2 : 1;
3884 case GLSL_SAMPLER_DIM_2D
:
3885 return array
? 3 : 2;
3886 case GLSL_SAMPLER_DIM_MS
:
3887 return array
? 4 : 3;
3888 case GLSL_SAMPLER_DIM_3D
:
3889 case GLSL_SAMPLER_DIM_CUBE
:
3891 case GLSL_SAMPLER_DIM_RECT
:
3892 case GLSL_SAMPLER_DIM_SUBPASS
:
3894 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
3903 /* Adjust the sample index according to FMASK.
3905 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3906 * which is the identity mapping. Each nibble says which physical sample
3907 * should be fetched to get that sample.
3909 * For example, 0x11111100 means there are only 2 samples stored and
3910 * the second sample covers 3/4 of the pixel. When reading samples 0
3911 * and 1, return physical sample 0 (determined by the first two 0s
3912 * in FMASK), otherwise return physical sample 1.
3914 * The sample index should be adjusted as follows:
3915 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3917 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, Temp coords
, Operand sample_index
, Temp fmask_desc_ptr
)
3919 Builder
bld(ctx
->program
, ctx
->block
);
3920 Temp fmask
= bld
.tmp(v1
);
3921 unsigned dim
= ctx
->options
->chip_class
>= GFX10
3922 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
3925 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 2, 1)};
3926 load
->operands
[0] = Operand(coords
);
3927 load
->operands
[1] = Operand(fmask_desc_ptr
);
3928 load
->definitions
[0] = Definition(fmask
);
3935 load
->can_reorder
= true; /* fmask images shouldn't be modified */
3936 ctx
->block
->instructions
.emplace_back(std::move(load
));
3938 Operand sample_index4
;
3939 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
3940 sample_index4
= Operand(sample_index
.constantValue() << 2);
3941 } else if (sample_index
.regClass() == s1
) {
3942 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
3944 assert(sample_index
.regClass() == v1
);
3945 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
3949 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
3950 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
3951 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
3952 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
3954 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
3956 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3957 * resource descriptor is 0 (invalid),
3959 Temp compare
= bld
.tmp(bld
.lm
);
3960 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
3961 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
3963 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
3965 /* Replace the MSAA sample index. */
3966 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
3969 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
3972 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
3973 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
3974 bool is_array
= glsl_sampler_type_is_array(type
);
3975 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3976 assert(!add_frag_pos
&& "Input attachments should be lowered.");
3977 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
3978 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
3979 int count
= image_type_to_components_count(dim
, is_array
);
3980 std::vector
<Operand
> coords(count
);
3983 Operand sample_index
;
3984 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
3986 sample_index
= Operand(sample_cv
->u32
);
3988 sample_index
= Operand(emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
), 0, v1
));
3990 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
3991 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, is_array
? 3 : 2, 1)};
3992 for (unsigned i
= 0; i
< vec
->operands
.size(); i
++)
3993 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
3994 Temp fmask_load_address
= {ctx
->program
->allocateId(), is_array
? v3
: v2
};
3995 vec
->definitions
[0] = Definition(fmask_load_address
);
3996 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3998 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
3999 sample_index
= Operand(adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
));
4002 coords
[count
] = sample_index
;
4005 if (count
== 1 && !gfx9_1d
)
4006 return emit_extract_vector(ctx
, src0
, 0, v1
);
4009 coords
[0] = Operand(emit_extract_vector(ctx
, src0
, 0, v1
));
4010 coords
.resize(coords
.size() + 1);
4011 coords
[1] = Operand((uint32_t) 0);
4013 coords
[2] = Operand(emit_extract_vector(ctx
, src0
, 1, v1
));
4015 for (int i
= 0; i
< count
; i
++)
4016 coords
[i
] = Operand(emit_extract_vector(ctx
, src0
, i
, v1
));
4019 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
4020 for (unsigned i
= 0; i
< coords
.size(); i
++)
4021 vec
->operands
[i
] = coords
[i
];
4022 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
4023 vec
->definitions
[0] = Definition(res
);
4024 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4029 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4031 Builder
bld(ctx
->program
, ctx
->block
);
4032 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4033 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4034 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4035 bool is_array
= glsl_sampler_type_is_array(type
);
4036 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4038 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4039 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4040 unsigned num_channels
= util_last_bit(mask
);
4041 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4042 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4045 switch (num_channels
) {
4047 opcode
= aco_opcode::buffer_load_format_x
;
4050 opcode
= aco_opcode::buffer_load_format_xy
;
4053 opcode
= aco_opcode::buffer_load_format_xyz
;
4056 opcode
= aco_opcode::buffer_load_format_xyzw
;
4059 unreachable(">4 channel buffer image load");
4061 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
4062 load
->operands
[0] = Operand(vindex
);
4063 load
->operands
[1] = Operand(rsrc
);
4064 load
->operands
[2] = Operand((uint32_t) 0);
4066 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4069 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
4070 load
->definitions
[0] = Definition(tmp
);
4072 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4073 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4074 load
->barrier
= barrier_image
;
4075 ctx
->block
->instructions
.emplace_back(std::move(load
));
4077 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
4081 Temp coords
= get_image_coords(ctx
, instr
, type
);
4082 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4084 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
4085 unsigned num_components
= util_bitcount(dmask
);
4087 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
4090 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
4092 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 2, 1)};
4093 load
->operands
[0] = Operand(coords
);
4094 load
->operands
[1] = Operand(resource
);
4095 load
->definitions
[0] = Definition(tmp
);
4096 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
4097 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
4098 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4099 load
->dmask
= dmask
;
4101 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4102 load
->barrier
= barrier_image
;
4103 ctx
->block
->instructions
.emplace_back(std::move(load
));
4105 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
4109 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4111 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4112 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4113 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4114 bool is_array
= glsl_sampler_type_is_array(type
);
4115 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4117 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
4119 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4120 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4121 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4123 switch (data
.size()) {
4125 opcode
= aco_opcode::buffer_store_format_x
;
4128 opcode
= aco_opcode::buffer_store_format_xy
;
4131 opcode
= aco_opcode::buffer_store_format_xyz
;
4134 opcode
= aco_opcode::buffer_store_format_xyzw
;
4137 unreachable(">4 channel buffer image store");
4139 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
4140 store
->operands
[0] = Operand(vindex
);
4141 store
->operands
[1] = Operand(rsrc
);
4142 store
->operands
[2] = Operand((uint32_t) 0);
4143 store
->operands
[3] = Operand(data
);
4144 store
->idxen
= true;
4147 store
->disable_wqm
= true;
4148 store
->barrier
= barrier_image
;
4149 ctx
->program
->needs_exact
= true;
4150 ctx
->block
->instructions
.emplace_back(std::move(store
));
4154 assert(data
.type() == RegType::vgpr
);
4155 Temp coords
= get_image_coords(ctx
, instr
, type
);
4156 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4158 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(aco_opcode::image_store
, Format::MIMG
, 4, 0)};
4159 store
->operands
[0] = Operand(coords
);
4160 store
->operands
[1] = Operand(resource
);
4161 store
->operands
[2] = Operand(s4
);
4162 store
->operands
[3] = Operand(data
);
4165 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4166 store
->dmask
= (1 << data
.size()) - 1;
4168 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4169 store
->disable_wqm
= true;
4170 store
->barrier
= barrier_image
;
4171 ctx
->program
->needs_exact
= true;
4172 ctx
->block
->instructions
.emplace_back(std::move(store
));
4176 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4178 /* return the previous value if dest is ever used */
4179 bool return_previous
= false;
4180 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4181 return_previous
= true;
4184 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4185 return_previous
= true;
4189 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4190 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4191 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4192 bool is_array
= glsl_sampler_type_is_array(type
);
4193 Builder
bld(ctx
->program
, ctx
->block
);
4195 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
4196 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
4198 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
4199 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
4201 aco_opcode buf_op
, image_op
;
4202 switch (instr
->intrinsic
) {
4203 case nir_intrinsic_image_deref_atomic_add
:
4204 buf_op
= aco_opcode::buffer_atomic_add
;
4205 image_op
= aco_opcode::image_atomic_add
;
4207 case nir_intrinsic_image_deref_atomic_umin
:
4208 buf_op
= aco_opcode::buffer_atomic_umin
;
4209 image_op
= aco_opcode::image_atomic_umin
;
4211 case nir_intrinsic_image_deref_atomic_imin
:
4212 buf_op
= aco_opcode::buffer_atomic_smin
;
4213 image_op
= aco_opcode::image_atomic_smin
;
4215 case nir_intrinsic_image_deref_atomic_umax
:
4216 buf_op
= aco_opcode::buffer_atomic_umax
;
4217 image_op
= aco_opcode::image_atomic_umax
;
4219 case nir_intrinsic_image_deref_atomic_imax
:
4220 buf_op
= aco_opcode::buffer_atomic_smax
;
4221 image_op
= aco_opcode::image_atomic_smax
;
4223 case nir_intrinsic_image_deref_atomic_and
:
4224 buf_op
= aco_opcode::buffer_atomic_and
;
4225 image_op
= aco_opcode::image_atomic_and
;
4227 case nir_intrinsic_image_deref_atomic_or
:
4228 buf_op
= aco_opcode::buffer_atomic_or
;
4229 image_op
= aco_opcode::image_atomic_or
;
4231 case nir_intrinsic_image_deref_atomic_xor
:
4232 buf_op
= aco_opcode::buffer_atomic_xor
;
4233 image_op
= aco_opcode::image_atomic_xor
;
4235 case nir_intrinsic_image_deref_atomic_exchange
:
4236 buf_op
= aco_opcode::buffer_atomic_swap
;
4237 image_op
= aco_opcode::image_atomic_swap
;
4239 case nir_intrinsic_image_deref_atomic_comp_swap
:
4240 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
4241 image_op
= aco_opcode::image_atomic_cmpswap
;
4244 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
4247 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4249 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
4250 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
4251 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
4252 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
4253 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4254 mubuf
->operands
[0] = Operand(vindex
);
4255 mubuf
->operands
[1] = Operand(resource
);
4256 mubuf
->operands
[2] = Operand((uint32_t)0);
4257 mubuf
->operands
[3] = Operand(data
);
4258 if (return_previous
)
4259 mubuf
->definitions
[0] = Definition(dst
);
4261 mubuf
->idxen
= true;
4262 mubuf
->glc
= return_previous
;
4263 mubuf
->dlc
= false; /* Not needed for atomics */
4264 mubuf
->disable_wqm
= true;
4265 mubuf
->barrier
= barrier_image
;
4266 ctx
->program
->needs_exact
= true;
4267 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4271 Temp coords
= get_image_coords(ctx
, instr
, type
);
4272 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
4273 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 4, return_previous
? 1 : 0)};
4274 mimg
->operands
[0] = Operand(coords
);
4275 mimg
->operands
[1] = Operand(resource
);
4276 mimg
->operands
[2] = Operand(s4
); /* no sampler */
4277 mimg
->operands
[3] = Operand(data
);
4278 if (return_previous
)
4279 mimg
->definitions
[0] = Definition(dst
);
4280 mimg
->glc
= return_previous
;
4281 mimg
->dlc
= false; /* Not needed for atomics */
4282 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4283 mimg
->dmask
= (1 << data
.size()) - 1;
4285 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
4286 mimg
->disable_wqm
= true;
4287 mimg
->barrier
= barrier_image
;
4288 ctx
->program
->needs_exact
= true;
4289 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4293 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
4295 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
4296 Builder
bld(ctx
->program
, ctx
->block
);
4298 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
4299 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
4300 stride
= bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, bld
.def(v1
), stride
);
4301 stride
= bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), stride
);
4303 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
4304 size
= bld
.vop1(aco_opcode::v_cvt_f32_u32
, bld
.def(v1
), size
);
4306 Temp res
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), size
, stride
);
4307 res
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), res
);
4308 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), res
);
4310 // TODO: we can probably calculate this faster on the scalar unit to do: size / stride{1,2,4,8,12,16}
4312 * for 1,2,4,8,16, the result is just (stride >> S_FF1_I32_B32)
4313 * in case 12 (or 3?), we have to divide by 3:
4314 * set v_skip in case it's 12 (if we also have to take care of 3, shift first)
4315 * use v_mul_hi_u32 with magic number to divide
4316 * we need some pseudo merge opcode to overwrite the original SALU result with readfirstlane
4318 * total: 6 SALU + 2 VALU instructions vs 1 SALU + 6 VALU instructions
4322 emit_extract_vector(ctx
, desc
, 2, dst
);
4326 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4328 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
4329 const struct glsl_type
*type
= glsl_without_array(var
->type
);
4330 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
4331 bool is_array
= glsl_sampler_type_is_array(type
);
4332 Builder
bld(ctx
->program
, ctx
->block
);
4334 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
4335 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
4336 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
4340 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
4343 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
4345 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4347 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1)};
4348 mimg
->operands
[0] = Operand(lod
);
4349 mimg
->operands
[1] = Operand(resource
);
4350 unsigned& dmask
= mimg
->dmask
;
4351 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
4352 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
4353 mimg
->da
= glsl_sampler_type_is_array(type
);
4354 mimg
->can_reorder
= true;
4355 Definition
& def
= mimg
->definitions
[0];
4356 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
4358 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
4359 glsl_sampler_type_is_array(type
)) {
4361 assert(instr
->dest
.ssa
.num_components
== 3);
4362 Temp tmp
= {ctx
->program
->allocateId(), v3
};
4363 def
= Definition(tmp
);
4364 emit_split_vector(ctx
, tmp
, 3);
4366 /* divide 3rd value by 6 by multiplying with magic number */
4367 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
4368 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
4370 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4371 emit_extract_vector(ctx
, tmp
, 0, v1
),
4372 emit_extract_vector(ctx
, tmp
, 1, v1
),
4375 } else if (ctx
->options
->chip_class
== GFX9
&&
4376 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
4377 glsl_sampler_type_is_array(type
)) {
4378 assert(instr
->dest
.ssa
.num_components
== 2);
4379 def
= Definition(dst
);
4382 def
= Definition(dst
);
4385 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
4388 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4390 Builder
bld(ctx
->program
, ctx
->block
);
4391 unsigned num_components
= instr
->num_components
;
4393 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4394 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4395 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4397 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4398 load_buffer(ctx
, num_components
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), glc
, false);
4401 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4403 Builder
bld(ctx
->program
, ctx
->block
);
4404 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4405 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4406 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4409 if (ctx
->options
->chip_class
< GFX8
)
4410 offset
= as_vgpr(ctx
,get_ssa_temp(ctx
, instr
->src
[2].ssa
));
4412 offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
4414 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4415 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4417 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
4418 ctx
->options
->chip_class
>= GFX8
;
4420 offset
= bld
.as_uniform(offset
);
4421 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
4425 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
4426 if (count
== 3 && smem
) {
4427 writemask
|= 1u << (start
+ 2);
4430 int num_bytes
= count
* elem_size_bytes
;
4432 if (num_bytes
> 16) {
4433 assert(elem_size_bytes
== 8);
4434 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
4439 // TODO: check alignment of sub-dword stores
4440 // TODO: split 3 bytes. there is no store instruction for that
4443 if (count
!= instr
->num_components
) {
4444 emit_split_vector(ctx
, data
, instr
->num_components
);
4445 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4446 for (int i
= 0; i
< count
; i
++) {
4447 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
4448 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
4450 write_data
= bld
.tmp(smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
4451 vec
->definitions
[0] = Definition(write_data
);
4452 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4453 } else if (!smem
&& data
.type() != RegType::vgpr
) {
4454 assert(num_bytes
% 4 == 0);
4455 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
4456 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
4457 assert(num_bytes
% 4 == 0);
4458 write_data
= bld
.as_uniform(data
);
4463 aco_opcode vmem_op
, smem_op
;
4464 switch (num_bytes
) {
4466 vmem_op
= aco_opcode::buffer_store_dword
;
4467 smem_op
= aco_opcode::s_buffer_store_dword
;
4470 vmem_op
= aco_opcode::buffer_store_dwordx2
;
4471 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
4474 vmem_op
= aco_opcode::buffer_store_dwordx3
;
4475 smem_op
= aco_opcode::last_opcode
;
4479 vmem_op
= aco_opcode::buffer_store_dwordx4
;
4480 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
4483 unreachable("Store SSBO not implemented for this size.");
4485 if (ctx
->stage
== fragment_fs
)
4486 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
4489 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
4490 store
->operands
[0] = Operand(rsrc
);
4492 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
4493 offset
, Operand(start
* elem_size_bytes
));
4494 store
->operands
[1] = Operand(off
);
4496 store
->operands
[1] = Operand(offset
);
4498 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
4499 store
->operands
[1].setFixed(m0
);
4500 store
->operands
[2] = Operand(write_data
);
4501 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4503 store
->disable_wqm
= true;
4504 store
->barrier
= barrier_buffer
;
4505 ctx
->block
->instructions
.emplace_back(std::move(store
));
4506 ctx
->program
->wb_smem_l1_on_end
= true;
4507 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
4508 ctx
->block
->kind
|= block_kind_needs_lowering
;
4509 ctx
->program
->needs_exact
= true;
4512 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
4513 store
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4514 store
->operands
[1] = Operand(rsrc
);
4515 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4516 store
->operands
[3] = Operand(write_data
);
4517 store
->offset
= start
* elem_size_bytes
;
4518 store
->offen
= (offset
.type() == RegType::vgpr
);
4519 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4521 store
->disable_wqm
= true;
4522 store
->barrier
= barrier_buffer
;
4523 ctx
->program
->needs_exact
= true;
4524 ctx
->block
->instructions
.emplace_back(std::move(store
));
4529 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4531 /* return the previous value if dest is ever used */
4532 bool return_previous
= false;
4533 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4534 return_previous
= true;
4537 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4538 return_previous
= true;
4542 Builder
bld(ctx
->program
, ctx
->block
);
4543 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
4545 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
4546 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
4547 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
4550 if (ctx
->options
->chip_class
< GFX8
)
4551 offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4553 offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4555 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4556 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
4558 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4560 aco_opcode op32
, op64
;
4561 switch (instr
->intrinsic
) {
4562 case nir_intrinsic_ssbo_atomic_add
:
4563 op32
= aco_opcode::buffer_atomic_add
;
4564 op64
= aco_opcode::buffer_atomic_add_x2
;
4566 case nir_intrinsic_ssbo_atomic_imin
:
4567 op32
= aco_opcode::buffer_atomic_smin
;
4568 op64
= aco_opcode::buffer_atomic_smin_x2
;
4570 case nir_intrinsic_ssbo_atomic_umin
:
4571 op32
= aco_opcode::buffer_atomic_umin
;
4572 op64
= aco_opcode::buffer_atomic_umin_x2
;
4574 case nir_intrinsic_ssbo_atomic_imax
:
4575 op32
= aco_opcode::buffer_atomic_smax
;
4576 op64
= aco_opcode::buffer_atomic_smax_x2
;
4578 case nir_intrinsic_ssbo_atomic_umax
:
4579 op32
= aco_opcode::buffer_atomic_umax
;
4580 op64
= aco_opcode::buffer_atomic_umax_x2
;
4582 case nir_intrinsic_ssbo_atomic_and
:
4583 op32
= aco_opcode::buffer_atomic_and
;
4584 op64
= aco_opcode::buffer_atomic_and_x2
;
4586 case nir_intrinsic_ssbo_atomic_or
:
4587 op32
= aco_opcode::buffer_atomic_or
;
4588 op64
= aco_opcode::buffer_atomic_or_x2
;
4590 case nir_intrinsic_ssbo_atomic_xor
:
4591 op32
= aco_opcode::buffer_atomic_xor
;
4592 op64
= aco_opcode::buffer_atomic_xor_x2
;
4594 case nir_intrinsic_ssbo_atomic_exchange
:
4595 op32
= aco_opcode::buffer_atomic_swap
;
4596 op64
= aco_opcode::buffer_atomic_swap_x2
;
4598 case nir_intrinsic_ssbo_atomic_comp_swap
:
4599 op32
= aco_opcode::buffer_atomic_cmpswap
;
4600 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
4603 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
4605 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
4606 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
4607 mubuf
->operands
[0] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
4608 mubuf
->operands
[1] = Operand(rsrc
);
4609 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
4610 mubuf
->operands
[3] = Operand(data
);
4611 if (return_previous
)
4612 mubuf
->definitions
[0] = Definition(dst
);
4614 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
4615 mubuf
->glc
= return_previous
;
4616 mubuf
->dlc
= false; /* Not needed for atomics */
4617 mubuf
->disable_wqm
= true;
4618 mubuf
->barrier
= barrier_buffer
;
4619 ctx
->program
->needs_exact
= true;
4620 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
4623 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
4625 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4626 Builder
bld(ctx
->program
, ctx
->block
);
4627 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
4628 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
4631 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4633 Builder
bld(ctx
->program
, ctx
->block
);
4634 unsigned num_components
= instr
->num_components
;
4635 unsigned num_bytes
= num_components
* instr
->dest
.ssa
.bit_size
/ 8;
4637 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4638 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4640 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
4641 bool dlc
= glc
&& ctx
->options
->chip_class
>= GFX10
;
4643 if (dst
.type() == RegType::vgpr
|| (glc
&& ctx
->options
->chip_class
< GFX8
)) {
4644 bool global
= ctx
->options
->chip_class
>= GFX9
;
4646 switch (num_bytes
) {
4648 op
= global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
4651 op
= global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
4654 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
4657 op
= global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
4660 unreachable("load_global not implemented for this size.");
4662 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
4663 flat
->operands
[0] = Operand(addr
);
4664 flat
->operands
[1] = Operand(s1
);
4667 flat
->barrier
= barrier_buffer
;
4669 if (dst
.type() == RegType::sgpr
) {
4670 Temp vec
= bld
.tmp(RegType::vgpr
, dst
.size());
4671 flat
->definitions
[0] = Definition(vec
);
4672 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4673 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
4675 flat
->definitions
[0] = Definition(dst
);
4676 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4678 emit_split_vector(ctx
, dst
, num_components
);
4680 switch (num_bytes
) {
4682 op
= aco_opcode::s_load_dword
;
4685 op
= aco_opcode::s_load_dwordx2
;
4689 op
= aco_opcode::s_load_dwordx4
;
4692 unreachable("load_global not implemented for this size.");
4694 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
4695 load
->operands
[0] = Operand(addr
);
4696 load
->operands
[1] = Operand(0u);
4697 load
->definitions
[0] = Definition(dst
);
4700 load
->barrier
= barrier_buffer
;
4701 assert(ctx
->options
->chip_class
>= GFX8
|| !glc
);
4703 if (dst
.size() == 3) {
4705 Temp vec
= bld
.tmp(s4
);
4706 load
->definitions
[0] = Definition(vec
);
4707 ctx
->block
->instructions
.emplace_back(std::move(load
));
4708 emit_split_vector(ctx
, vec
, 4);
4710 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
4711 emit_extract_vector(ctx
, vec
, 0, s1
),
4712 emit_extract_vector(ctx
, vec
, 1, s1
),
4713 emit_extract_vector(ctx
, vec
, 2, s1
));
4715 ctx
->block
->instructions
.emplace_back(std::move(load
));
4720 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4722 Builder
bld(ctx
->program
, ctx
->block
);
4723 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4725 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4726 Temp addr
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4728 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4731 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
4732 unsigned num_bytes
= count
* elem_size_bytes
;
4734 Temp write_data
= data
;
4735 if (count
!= instr
->num_components
) {
4736 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
4737 for (int i
= 0; i
< count
; i
++)
4738 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
4739 write_data
= bld
.tmp(RegType::vgpr
, count
);
4740 vec
->definitions
[0] = Definition(write_data
);
4741 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4744 unsigned offset
= start
* elem_size_bytes
;
4745 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
4746 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
4747 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
4748 Temp carry
= bld
.tmp(bld
.lm
);
4749 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
4751 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
4752 Operand(offset
), addr0
);
4753 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
4755 carry
).def(1).setHint(vcc
);
4757 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
4762 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
4763 bool global
= ctx
->options
->chip_class
>= GFX9
;
4765 switch (num_bytes
) {
4767 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
4770 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
4773 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
4776 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
4779 unreachable("store_global not implemented for this size.");
4781 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
4782 flat
->operands
[0] = Operand(addr
);
4783 flat
->operands
[1] = Operand(s1
);
4784 flat
->operands
[2] = Operand(data
);
4787 flat
->offset
= offset
;
4788 flat
->disable_wqm
= true;
4789 flat
->barrier
= barrier_buffer
;
4790 ctx
->program
->needs_exact
= true;
4791 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4795 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4797 /* return the previous value if dest is ever used */
4798 bool return_previous
= false;
4799 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
4800 return_previous
= true;
4803 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
4804 return_previous
= true;
4808 Builder
bld(ctx
->program
, ctx
->block
);
4809 Temp addr
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4810 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4812 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
4813 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
4814 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
4816 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4818 bool global
= ctx
->options
->chip_class
>= GFX9
;
4819 aco_opcode op32
, op64
;
4820 switch (instr
->intrinsic
) {
4821 case nir_intrinsic_global_atomic_add
:
4822 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
4823 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
4825 case nir_intrinsic_global_atomic_imin
:
4826 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
4827 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
4829 case nir_intrinsic_global_atomic_umin
:
4830 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
4831 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
4833 case nir_intrinsic_global_atomic_imax
:
4834 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
4835 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
4837 case nir_intrinsic_global_atomic_umax
:
4838 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
4839 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
4841 case nir_intrinsic_global_atomic_and
:
4842 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
4843 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
4845 case nir_intrinsic_global_atomic_or
:
4846 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
4847 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
4849 case nir_intrinsic_global_atomic_xor
:
4850 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
4851 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
4853 case nir_intrinsic_global_atomic_exchange
:
4854 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
4855 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
4857 case nir_intrinsic_global_atomic_comp_swap
:
4858 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
4859 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
4862 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
4864 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
4865 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
4866 flat
->operands
[0] = Operand(addr
);
4867 flat
->operands
[1] = Operand(s1
);
4868 flat
->operands
[2] = Operand(data
);
4869 if (return_previous
)
4870 flat
->definitions
[0] = Definition(dst
);
4871 flat
->glc
= return_previous
;
4872 flat
->dlc
= false; /* Not needed for atomics */
4874 flat
->disable_wqm
= true;
4875 flat
->barrier
= barrier_buffer
;
4876 ctx
->program
->needs_exact
= true;
4877 ctx
->block
->instructions
.emplace_back(std::move(flat
));
4880 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
4881 Builder
bld(ctx
->program
, ctx
->block
);
4882 switch(instr
->intrinsic
) {
4883 case nir_intrinsic_group_memory_barrier
:
4884 case nir_intrinsic_memory_barrier
:
4885 bld
.barrier(aco_opcode::p_memory_barrier_all
);
4887 case nir_intrinsic_memory_barrier_atomic_counter
:
4888 bld
.barrier(aco_opcode::p_memory_barrier_atomic
);
4890 case nir_intrinsic_memory_barrier_buffer
:
4891 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
4893 case nir_intrinsic_memory_barrier_image
:
4894 bld
.barrier(aco_opcode::p_memory_barrier_image
);
4896 case nir_intrinsic_memory_barrier_shared
:
4897 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
4900 unreachable("Unimplemented memory barrier intrinsic");
4905 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4907 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
4908 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4909 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
4910 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4911 Builder
bld(ctx
->program
, ctx
->block
);
4913 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4914 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
4915 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
4918 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4920 unsigned writemask
= nir_intrinsic_write_mask(instr
);
4921 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4922 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4923 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4924 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
4926 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
4927 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
4930 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4932 unsigned offset
= nir_intrinsic_base(instr
);
4933 Operand m
= load_lds_size_m0(ctx
);
4934 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
4935 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
4937 unsigned num_operands
= 3;
4938 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
4939 switch(instr
->intrinsic
) {
4940 case nir_intrinsic_shared_atomic_add
:
4941 op32
= aco_opcode::ds_add_u32
;
4942 op64
= aco_opcode::ds_add_u64
;
4943 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
4944 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
4946 case nir_intrinsic_shared_atomic_imin
:
4947 op32
= aco_opcode::ds_min_i32
;
4948 op64
= aco_opcode::ds_min_i64
;
4949 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
4950 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
4952 case nir_intrinsic_shared_atomic_umin
:
4953 op32
= aco_opcode::ds_min_u32
;
4954 op64
= aco_opcode::ds_min_u64
;
4955 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
4956 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
4958 case nir_intrinsic_shared_atomic_imax
:
4959 op32
= aco_opcode::ds_max_i32
;
4960 op64
= aco_opcode::ds_max_i64
;
4961 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
4962 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
4964 case nir_intrinsic_shared_atomic_umax
:
4965 op32
= aco_opcode::ds_max_u32
;
4966 op64
= aco_opcode::ds_max_u64
;
4967 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
4968 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
4970 case nir_intrinsic_shared_atomic_and
:
4971 op32
= aco_opcode::ds_and_b32
;
4972 op64
= aco_opcode::ds_and_b64
;
4973 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
4974 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
4976 case nir_intrinsic_shared_atomic_or
:
4977 op32
= aco_opcode::ds_or_b32
;
4978 op64
= aco_opcode::ds_or_b64
;
4979 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
4980 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
4982 case nir_intrinsic_shared_atomic_xor
:
4983 op32
= aco_opcode::ds_xor_b32
;
4984 op64
= aco_opcode::ds_xor_b64
;
4985 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
4986 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
4988 case nir_intrinsic_shared_atomic_exchange
:
4989 op32
= aco_opcode::ds_write_b32
;
4990 op64
= aco_opcode::ds_write_b64
;
4991 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
4992 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
4994 case nir_intrinsic_shared_atomic_comp_swap
:
4995 op32
= aco_opcode::ds_cmpst_b32
;
4996 op64
= aco_opcode::ds_cmpst_b64
;
4997 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
4998 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
5002 unreachable("Unhandled shared atomic intrinsic");
5005 /* return the previous value if dest is ever used */
5006 bool return_previous
= false;
5007 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5008 return_previous
= true;
5011 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5012 return_previous
= true;
5017 if (data
.size() == 1) {
5018 assert(instr
->dest
.ssa
.bit_size
== 32);
5019 op
= return_previous
? op32_rtn
: op32
;
5021 assert(instr
->dest
.ssa
.bit_size
== 64);
5022 op
= return_previous
? op64_rtn
: op64
;
5025 if (offset
> 65535) {
5026 Builder
bld(ctx
->program
, ctx
->block
);
5027 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
5031 aco_ptr
<DS_instruction
> ds
;
5032 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
5033 ds
->operands
[0] = Operand(address
);
5034 ds
->operands
[1] = Operand(data
);
5035 if (num_operands
== 4)
5036 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
5037 ds
->operands
[num_operands
- 1] = m
;
5038 ds
->offset0
= offset
;
5039 if (return_previous
)
5040 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5041 ctx
->block
->instructions
.emplace_back(std::move(ds
));
5044 Temp
get_scratch_resource(isel_context
*ctx
)
5046 Builder
bld(ctx
->program
, ctx
->block
);
5047 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
5048 if (ctx
->stage
!= compute_cs
)
5049 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
5051 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
5052 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
5054 if (ctx
->program
->chip_class
>= GFX10
) {
5055 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5056 S_008F0C_OOB_SELECT(3) |
5057 S_008F0C_RESOURCE_LEVEL(1);
5058 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
5059 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5060 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5063 /* older generations need element size = 16 bytes. element size removed in GFX9 */
5064 if (ctx
->program
->chip_class
<= GFX8
)
5065 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
5067 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
5070 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5071 assert(instr
->dest
.ssa
.bit_size
== 32 || instr
->dest
.ssa
.bit_size
== 64);
5072 Builder
bld(ctx
->program
, ctx
->block
);
5073 Temp rsrc
= get_scratch_resource(ctx
);
5074 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5075 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5078 switch (dst
.size()) {
5080 op
= aco_opcode::buffer_load_dword
;
5083 op
= aco_opcode::buffer_load_dwordx2
;
5086 op
= aco_opcode::buffer_load_dwordx3
;
5089 op
= aco_opcode::buffer_load_dwordx4
;
5093 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5094 Temp lower
= bld
.mubuf(aco_opcode::buffer_load_dwordx4
,
5095 bld
.def(v4
), offset
, rsrc
,
5096 ctx
->program
->scratch_offset
, 0, true);
5097 Temp upper
= bld
.mubuf(dst
.size() == 6 ? aco_opcode::buffer_load_dwordx2
:
5098 aco_opcode::buffer_load_dwordx4
,
5099 dst
.size() == 6 ? bld
.def(v2
) : bld
.def(v4
),
5100 offset
, rsrc
, ctx
->program
->scratch_offset
, 16, true);
5101 emit_split_vector(ctx
, lower
, 2);
5102 elems
[0] = emit_extract_vector(ctx
, lower
, 0, v2
);
5103 elems
[1] = emit_extract_vector(ctx
, lower
, 1, v2
);
5104 if (dst
.size() == 8) {
5105 emit_split_vector(ctx
, upper
, 2);
5106 elems
[2] = emit_extract_vector(ctx
, upper
, 0, v2
);
5107 elems
[3] = emit_extract_vector(ctx
, upper
, 1, v2
);
5112 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
5113 Format::PSEUDO
, dst
.size() / 2, 1)};
5114 for (unsigned i
= 0; i
< dst
.size() / 2; i
++)
5115 vec
->operands
[i
] = Operand(elems
[i
]);
5116 vec
->definitions
[0] = Definition(dst
);
5117 bld
.insert(std::move(vec
));
5118 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5122 unreachable("Wrong dst size for nir_intrinsic_load_scratch");
5125 bld
.mubuf(op
, Definition(dst
), offset
, rsrc
, ctx
->program
->scratch_offset
, 0, true);
5126 emit_split_vector(ctx
, dst
, instr
->num_components
);
5129 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5130 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
5131 Builder
bld(ctx
->program
, ctx
->block
);
5132 Temp rsrc
= get_scratch_resource(ctx
);
5133 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5134 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
5136 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
5137 unsigned writemask
= nir_intrinsic_write_mask(instr
);
5141 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
5142 int num_bytes
= count
* elem_size_bytes
;
5144 if (num_bytes
> 16) {
5145 assert(elem_size_bytes
== 8);
5146 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
5151 // TODO: check alignment of sub-dword stores
5152 // TODO: split 3 bytes. there is no store instruction for that
5155 if (count
!= instr
->num_components
) {
5156 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5157 for (int i
= 0; i
< count
; i
++) {
5158 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
5159 vec
->operands
[i
] = Operand(elem
);
5161 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
5162 vec
->definitions
[0] = Definition(write_data
);
5163 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5169 switch (num_bytes
) {
5171 op
= aco_opcode::buffer_store_dword
;
5174 op
= aco_opcode::buffer_store_dwordx2
;
5177 op
= aco_opcode::buffer_store_dwordx3
;
5180 op
= aco_opcode::buffer_store_dwordx4
;
5183 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
5186 bld
.mubuf(op
, offset
, rsrc
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
5190 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
5191 uint8_t log2_ps_iter_samples
;
5192 if (ctx
->program
->info
->ps
.force_persample
) {
5193 log2_ps_iter_samples
=
5194 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
5196 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
5199 /* The bit pattern matches that used by fixed function fragment
5201 static const unsigned ps_iter_masks
[] = {
5202 0xffff, /* not used */
5208 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
5210 Builder
bld(ctx
->program
, ctx
->block
);
5212 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
5213 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
5214 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
5215 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
5216 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5217 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
5220 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
5222 Builder
bld(ctx
->program
, ctx
->block
);
5224 if (cluster_size
== 1) {
5226 } if (op
== nir_op_iand
&& cluster_size
== 4) {
5227 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
5228 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5229 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5230 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
5231 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
5232 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
5233 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
5234 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
5235 } else if (op
== nir_op_iand
&& cluster_size
== 64) {
5236 //subgroupAnd(val) -> (exec & ~val) == 0
5237 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5238 return bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(0u), Operand(-1u), bld
.scc(tmp
));
5239 } else if (op
== nir_op_ior
&& cluster_size
== 64) {
5240 //subgroupOr(val) -> (val & exec) != 0
5241 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
5242 return bool_to_vector_condition(ctx
, tmp
);
5243 } else if (op
== nir_op_ixor
&& cluster_size
== 64) {
5244 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
5245 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5246 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
5247 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
5248 return bool_to_vector_condition(ctx
, tmp
);
5250 //subgroupClustered{And,Or,Xor}(val, n) ->
5251 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
5252 //cluster_offset = ~(n - 1) & lane_id
5253 //cluster_mask = ((1 << n) - 1)
5254 //subgroupClusteredAnd():
5255 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
5256 //subgroupClusteredOr():
5257 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
5258 //subgroupClusteredXor():
5259 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
5260 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
5261 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
5264 if (op
== nir_op_iand
)
5265 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5267 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5269 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
5270 if (ctx
->program
->wave_size
== 64)
5271 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
5273 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
5274 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
5275 if (cluster_mask
!= 0xffffffff)
5276 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
5278 Definition cmp_def
= Definition();
5279 if (op
== nir_op_iand
) {
5280 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
5281 } else if (op
== nir_op_ior
) {
5282 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5283 } else if (op
== nir_op_ixor
) {
5284 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
5285 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
5286 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
5288 cmp_def
.setHint(vcc
);
5289 return cmp_def
.getTemp();
5293 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5295 Builder
bld(ctx
->program
, ctx
->block
);
5297 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
5298 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
5299 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
5301 if (op
== nir_op_iand
)
5302 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5304 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5306 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
5307 Temp lo
= lohi
.def(0).getTemp();
5308 Temp hi
= lohi
.def(1).getTemp();
5309 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
5311 Definition cmp_def
= Definition();
5312 if (op
== nir_op_iand
)
5313 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5314 else if (op
== nir_op_ior
)
5315 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
5316 else if (op
== nir_op_ixor
)
5317 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
5318 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
5319 cmp_def
.setHint(vcc
);
5320 return cmp_def
.getTemp();
5323 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
5325 Builder
bld(ctx
->program
, ctx
->block
);
5327 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
5328 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
5329 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
5330 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
5331 if (op
== nir_op_iand
)
5332 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5333 else if (op
== nir_op_ior
)
5334 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5335 else if (op
== nir_op_ixor
)
5336 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
5342 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
5344 Builder
bld(ctx
->program
, ctx
->block
);
5345 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
5346 if (src
.regClass().type() == RegType::vgpr
) {
5347 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
5348 } else if (src
.regClass() == s1
) {
5349 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
5350 } else if (src
.regClass() == s2
) {
5351 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
5353 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5354 nir_print_instr(&instr
->instr
, stderr
);
5355 fprintf(stderr
, "\n");
5359 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
5361 Builder
bld(ctx
->program
, ctx
->block
);
5362 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5363 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
5364 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
5367 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_quad_perm(0, 0, 0, 0));
5368 Temp ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_quad_perm(1, 1, 1, 1));
5369 Temp ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_quad_perm(2, 2, 2, 2));
5370 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_quad_perm(0, 0, 0, 0));
5371 Temp ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_quad_perm(1, 1, 1, 1));
5372 Temp ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_quad_perm(2, 2, 2, 2));
5374 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
5375 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
5376 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
5377 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
5378 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
5379 Temp wqm1
= bld
.tmp(v1
);
5380 emit_wqm(ctx
, tmp1
, wqm1
, true);
5381 Temp wqm2
= bld
.tmp(v1
);
5382 emit_wqm(ctx
, tmp2
, wqm2
, true);
5383 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
5387 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5389 Builder
bld(ctx
->program
, ctx
->block
);
5390 switch(instr
->intrinsic
) {
5391 case nir_intrinsic_load_barycentric_sample
:
5392 case nir_intrinsic_load_barycentric_pixel
:
5393 case nir_intrinsic_load_barycentric_centroid
: {
5394 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
5395 Temp bary
= Temp(0, s2
);
5397 case INTERP_MODE_SMOOTH
:
5398 case INTERP_MODE_NONE
:
5399 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5400 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
5401 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5402 bary
= ctx
->persp_centroid
;
5403 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5404 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
5406 case INTERP_MODE_NOPERSPECTIVE
:
5407 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
5408 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
5409 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
5410 bary
= ctx
->linear_centroid
;
5411 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
5412 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
5417 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5418 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
5419 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
5420 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5421 Operand(p1
), Operand(p2
));
5422 emit_split_vector(ctx
, dst
, 2);
5425 case nir_intrinsic_load_barycentric_at_sample
: {
5426 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
5427 switch (ctx
->options
->key
.fs
.num_samples
) {
5428 case 2: sample_pos_offset
+= 1 << 3; break;
5429 case 4: sample_pos_offset
+= 3 << 3; break;
5430 case 8: sample_pos_offset
+= 7 << 3; break;
5434 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5435 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
5436 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
5437 if (addr
.type() == RegType::sgpr
) {
5440 sample_pos_offset
+= const_addr
->u32
<< 3;
5441 offset
= Operand(sample_pos_offset
);
5442 } else if (ctx
->options
->chip_class
>= GFX9
) {
5443 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5445 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
5446 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
5448 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, Operand(offset
));
5450 } else if (ctx
->options
->chip_class
>= GFX9
) {
5451 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5452 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
5454 /* addr += private_segment_buffer + sample_pos_offset */
5455 Temp tmp0
= bld
.tmp(s1
);
5456 Temp tmp1
= bld
.tmp(s1
);
5457 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
5458 Definition scc_tmp
= bld
.def(s1
, scc
);
5459 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
5460 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
5461 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
5462 Temp pck0
= bld
.tmp(v1
);
5463 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
5464 tmp1
= as_vgpr(ctx
, tmp1
);
5465 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
5466 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
5468 /* sample_pos = flat_load_dwordx2 addr */
5469 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
5472 /* sample_pos -= 0.5 */
5473 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
5474 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
5475 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
5476 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
5477 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
5479 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
5482 case nir_intrinsic_load_barycentric_at_offset
: {
5483 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5484 RegClass rc
= RegClass(offset
.type(), 1);
5485 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
5486 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
5487 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
5490 case nir_intrinsic_load_front_face
: {
5491 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5492 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
5495 case nir_intrinsic_load_view_index
:
5496 case nir_intrinsic_load_layer_id
: {
5497 if (instr
->intrinsic
== nir_intrinsic_load_view_index
&& (ctx
->stage
& sw_vs
)) {
5498 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5499 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
5503 unsigned idx
= nir_intrinsic_base(instr
);
5504 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5505 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
5508 case nir_intrinsic_load_frag_coord
: {
5509 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
5512 case nir_intrinsic_load_sample_pos
: {
5513 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
5514 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
5515 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5516 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
5517 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
5520 case nir_intrinsic_load_interpolated_input
:
5521 visit_load_interpolated_input(ctx
, instr
);
5523 case nir_intrinsic_store_output
:
5524 visit_store_output(ctx
, instr
);
5526 case nir_intrinsic_load_input
:
5527 visit_load_input(ctx
, instr
);
5529 case nir_intrinsic_load_ubo
:
5530 visit_load_ubo(ctx
, instr
);
5532 case nir_intrinsic_load_push_constant
:
5533 visit_load_push_constant(ctx
, instr
);
5535 case nir_intrinsic_load_constant
:
5536 visit_load_constant(ctx
, instr
);
5538 case nir_intrinsic_vulkan_resource_index
:
5539 visit_load_resource(ctx
, instr
);
5541 case nir_intrinsic_discard
:
5542 visit_discard(ctx
, instr
);
5544 case nir_intrinsic_discard_if
:
5545 visit_discard_if(ctx
, instr
);
5547 case nir_intrinsic_load_shared
:
5548 visit_load_shared(ctx
, instr
);
5550 case nir_intrinsic_store_shared
:
5551 visit_store_shared(ctx
, instr
);
5553 case nir_intrinsic_shared_atomic_add
:
5554 case nir_intrinsic_shared_atomic_imin
:
5555 case nir_intrinsic_shared_atomic_umin
:
5556 case nir_intrinsic_shared_atomic_imax
:
5557 case nir_intrinsic_shared_atomic_umax
:
5558 case nir_intrinsic_shared_atomic_and
:
5559 case nir_intrinsic_shared_atomic_or
:
5560 case nir_intrinsic_shared_atomic_xor
:
5561 case nir_intrinsic_shared_atomic_exchange
:
5562 case nir_intrinsic_shared_atomic_comp_swap
:
5563 visit_shared_atomic(ctx
, instr
);
5565 case nir_intrinsic_image_deref_load
:
5566 visit_image_load(ctx
, instr
);
5568 case nir_intrinsic_image_deref_store
:
5569 visit_image_store(ctx
, instr
);
5571 case nir_intrinsic_image_deref_atomic_add
:
5572 case nir_intrinsic_image_deref_atomic_umin
:
5573 case nir_intrinsic_image_deref_atomic_imin
:
5574 case nir_intrinsic_image_deref_atomic_umax
:
5575 case nir_intrinsic_image_deref_atomic_imax
:
5576 case nir_intrinsic_image_deref_atomic_and
:
5577 case nir_intrinsic_image_deref_atomic_or
:
5578 case nir_intrinsic_image_deref_atomic_xor
:
5579 case nir_intrinsic_image_deref_atomic_exchange
:
5580 case nir_intrinsic_image_deref_atomic_comp_swap
:
5581 visit_image_atomic(ctx
, instr
);
5583 case nir_intrinsic_image_deref_size
:
5584 visit_image_size(ctx
, instr
);
5586 case nir_intrinsic_load_ssbo
:
5587 visit_load_ssbo(ctx
, instr
);
5589 case nir_intrinsic_store_ssbo
:
5590 visit_store_ssbo(ctx
, instr
);
5592 case nir_intrinsic_load_global
:
5593 visit_load_global(ctx
, instr
);
5595 case nir_intrinsic_store_global
:
5596 visit_store_global(ctx
, instr
);
5598 case nir_intrinsic_global_atomic_add
:
5599 case nir_intrinsic_global_atomic_imin
:
5600 case nir_intrinsic_global_atomic_umin
:
5601 case nir_intrinsic_global_atomic_imax
:
5602 case nir_intrinsic_global_atomic_umax
:
5603 case nir_intrinsic_global_atomic_and
:
5604 case nir_intrinsic_global_atomic_or
:
5605 case nir_intrinsic_global_atomic_xor
:
5606 case nir_intrinsic_global_atomic_exchange
:
5607 case nir_intrinsic_global_atomic_comp_swap
:
5608 visit_global_atomic(ctx
, instr
);
5610 case nir_intrinsic_ssbo_atomic_add
:
5611 case nir_intrinsic_ssbo_atomic_imin
:
5612 case nir_intrinsic_ssbo_atomic_umin
:
5613 case nir_intrinsic_ssbo_atomic_imax
:
5614 case nir_intrinsic_ssbo_atomic_umax
:
5615 case nir_intrinsic_ssbo_atomic_and
:
5616 case nir_intrinsic_ssbo_atomic_or
:
5617 case nir_intrinsic_ssbo_atomic_xor
:
5618 case nir_intrinsic_ssbo_atomic_exchange
:
5619 case nir_intrinsic_ssbo_atomic_comp_swap
:
5620 visit_atomic_ssbo(ctx
, instr
);
5622 case nir_intrinsic_load_scratch
:
5623 visit_load_scratch(ctx
, instr
);
5625 case nir_intrinsic_store_scratch
:
5626 visit_store_scratch(ctx
, instr
);
5628 case nir_intrinsic_get_buffer_size
:
5629 visit_get_buffer_size(ctx
, instr
);
5631 case nir_intrinsic_barrier
: {
5632 unsigned* bsize
= ctx
->program
->info
->cs
.block_size
;
5633 unsigned workgroup_size
= bsize
[0] * bsize
[1] * bsize
[2];
5634 if (workgroup_size
> 64)
5635 bld
.sopp(aco_opcode::s_barrier
);
5638 case nir_intrinsic_group_memory_barrier
:
5639 case nir_intrinsic_memory_barrier
:
5640 case nir_intrinsic_memory_barrier_atomic_counter
:
5641 case nir_intrinsic_memory_barrier_buffer
:
5642 case nir_intrinsic_memory_barrier_image
:
5643 case nir_intrinsic_memory_barrier_shared
:
5644 emit_memory_barrier(ctx
, instr
);
5646 case nir_intrinsic_load_num_work_groups
: {
5647 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5648 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
5649 emit_split_vector(ctx
, dst
, 3);
5652 case nir_intrinsic_load_local_invocation_id
: {
5653 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5654 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
5655 emit_split_vector(ctx
, dst
, 3);
5658 case nir_intrinsic_load_work_group_id
: {
5659 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5660 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
5661 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5662 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
5663 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
5664 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
5665 emit_split_vector(ctx
, dst
, 3);
5668 case nir_intrinsic_load_local_invocation_index
: {
5669 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
5670 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
5671 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
5672 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
5675 case nir_intrinsic_load_subgroup_id
: {
5676 if (ctx
->stage
== compute_cs
) {
5677 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
5678 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
5680 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
5684 case nir_intrinsic_load_subgroup_invocation
: {
5685 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
5688 case nir_intrinsic_load_num_subgroups
: {
5689 if (ctx
->stage
== compute_cs
)
5690 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
5691 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
5693 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
5696 case nir_intrinsic_ballot
: {
5697 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5698 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5699 Definition tmp
= bld
.def(dst
.regClass());
5700 if (instr
->src
[0].ssa
->bit_size
== 1) {
5701 assert(src
.regClass() == bld
.lm
);
5702 bld
.sop2(Builder::s_and
, tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
5703 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
5704 bld
.vopc(aco_opcode::v_cmp_lg_u32
, tmp
, Operand(0u), src
);
5705 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
5706 bld
.vopc(aco_opcode::v_cmp_lg_u64
, tmp
, Operand(0u), src
);
5708 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5709 nir_print_instr(&instr
->instr
, stderr
);
5710 fprintf(stderr
, "\n");
5712 emit_wqm(ctx
, tmp
.getTemp(), dst
);
5715 case nir_intrinsic_shuffle
:
5716 case nir_intrinsic_read_invocation
: {
5717 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5718 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
5719 emit_uniform_subgroup(ctx
, instr
, src
);
5721 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5722 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
5723 tid
= bld
.as_uniform(tid
);
5724 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5725 if (src
.regClass() == v1
) {
5726 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
5727 } else if (src
.regClass() == v2
) {
5728 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5729 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5730 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
5731 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
5732 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5733 emit_split_vector(ctx
, dst
, 2);
5734 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
5735 assert(src
.regClass() == bld
.lm
);
5736 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
5737 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
5738 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
5739 assert(src
.regClass() == bld
.lm
);
5741 if (ctx
->program
->wave_size
== 64)
5742 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
5744 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
5745 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
5746 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
5747 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
5749 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5750 nir_print_instr(&instr
->instr
, stderr
);
5751 fprintf(stderr
, "\n");
5756 case nir_intrinsic_load_sample_id
: {
5757 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
5758 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
5761 case nir_intrinsic_load_sample_mask_in
: {
5762 visit_load_sample_mask_in(ctx
, instr
);
5765 case nir_intrinsic_read_first_invocation
: {
5766 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5767 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5768 if (src
.regClass() == v1
) {
5770 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
5772 } else if (src
.regClass() == v2
) {
5773 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5774 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5775 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
5776 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
5777 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5778 emit_split_vector(ctx
, dst
, 2);
5779 } else if (instr
->dest
.ssa
.bit_size
== 1) {
5780 assert(src
.regClass() == bld
.lm
);
5781 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
5782 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
5783 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
5784 } else if (src
.regClass() == s1
) {
5785 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
5786 } else if (src
.regClass() == s2
) {
5787 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
5789 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5790 nir_print_instr(&instr
->instr
, stderr
);
5791 fprintf(stderr
, "\n");
5795 case nir_intrinsic_vote_all
: {
5796 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5797 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5798 assert(src
.regClass() == bld
.lm
);
5799 assert(dst
.regClass() == bld
.lm
);
5801 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5802 Temp val
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(0u), Operand(-1u), bld
.scc(tmp
));
5803 emit_wqm(ctx
, val
, dst
);
5806 case nir_intrinsic_vote_any
: {
5807 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5808 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5809 assert(src
.regClass() == bld
.lm
);
5810 assert(dst
.regClass() == bld
.lm
);
5812 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
5813 Temp val
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), Operand(0u), bld
.scc(tmp
));
5814 emit_wqm(ctx
, val
, dst
);
5817 case nir_intrinsic_reduce
:
5818 case nir_intrinsic_inclusive_scan
:
5819 case nir_intrinsic_exclusive_scan
: {
5820 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5821 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5822 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
5823 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
5824 nir_intrinsic_cluster_size(instr
) : 0;
5825 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: 64, 64));
5827 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
5828 emit_uniform_subgroup(ctx
, instr
, src
);
5829 } else if (instr
->dest
.ssa
.bit_size
== 1) {
5830 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
5832 else if (op
== nir_op_iadd
)
5834 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
5836 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
5838 switch (instr
->intrinsic
) {
5839 case nir_intrinsic_reduce
:
5840 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
5842 case nir_intrinsic_exclusive_scan
:
5843 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
5845 case nir_intrinsic_inclusive_scan
:
5846 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
5851 } else if (cluster_size
== 1) {
5852 bld
.copy(Definition(dst
), src
);
5854 src
= as_vgpr(ctx
, src
);
5858 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
5873 unreachable("unknown reduction op");
5878 switch (instr
->intrinsic
) {
5879 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
5880 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
5881 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
5883 unreachable("unknown reduce intrinsic");
5886 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
5887 reduce
->operands
[0] = Operand(src
);
5888 // filled in by aco_reduce_assign.cpp, used internally as part of the
5890 assert(dst
.size() == 1 || dst
.size() == 2);
5891 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
5892 reduce
->operands
[2] = Operand(v1
.as_linear());
5894 Temp tmp_dst
= bld
.tmp(dst
.regClass());
5895 reduce
->definitions
[0] = Definition(tmp_dst
);
5896 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
5897 reduce
->definitions
[2] = Definition();
5898 reduce
->definitions
[3] = Definition(scc
, s1
);
5899 reduce
->definitions
[4] = Definition();
5900 reduce
->reduce_op
= reduce_op
;
5901 reduce
->cluster_size
= cluster_size
;
5902 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
5904 emit_wqm(ctx
, tmp_dst
, dst
);
5908 case nir_intrinsic_quad_broadcast
: {
5909 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5910 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
5911 emit_uniform_subgroup(ctx
, instr
, src
);
5913 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5914 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
5915 if (instr
->dest
.ssa
.bit_size
== 1) {
5916 assert(src
.regClass() == bld
.lm
);
5917 assert(dst
.regClass() == bld
.lm
);
5918 uint32_t half_mask
= 0x11111111u
<< lane
;
5919 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
5920 Temp tmp
= bld
.tmp(bld
.lm
);
5921 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
5922 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
5923 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
5924 emit_wqm(ctx
, tmp
, dst
);
5925 } else if (instr
->dest
.ssa
.bit_size
== 32) {
5927 bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
,
5928 dpp_quad_perm(lane
, lane
, lane
, lane
)),
5930 } else if (instr
->dest
.ssa
.bit_size
== 64) {
5931 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5933 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_quad_perm(lane
, lane
, lane
, lane
)));
5934 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_quad_perm(lane
, lane
, lane
, lane
)));
5935 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5936 emit_split_vector(ctx
, dst
, 2);
5938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5939 nir_print_instr(&instr
->instr
, stderr
);
5940 fprintf(stderr
, "\n");
5945 case nir_intrinsic_quad_swap_horizontal
:
5946 case nir_intrinsic_quad_swap_vertical
:
5947 case nir_intrinsic_quad_swap_diagonal
:
5948 case nir_intrinsic_quad_swizzle_amd
: {
5949 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5950 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
5951 emit_uniform_subgroup(ctx
, instr
, src
);
5954 uint16_t dpp_ctrl
= 0;
5955 switch (instr
->intrinsic
) {
5956 case nir_intrinsic_quad_swap_horizontal
:
5957 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
5959 case nir_intrinsic_quad_swap_vertical
:
5960 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
5962 case nir_intrinsic_quad_swap_diagonal
:
5963 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
5965 case nir_intrinsic_quad_swizzle_amd
: {
5966 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
5973 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5974 if (instr
->dest
.ssa
.bit_size
== 1) {
5975 assert(src
.regClass() == bld
.lm
);
5976 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
5977 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
5978 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
5979 emit_wqm(ctx
, tmp
, dst
);
5980 } else if (instr
->dest
.ssa
.bit_size
== 32) {
5981 Temp tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
5982 emit_wqm(ctx
, tmp
, dst
);
5983 } else if (instr
->dest
.ssa
.bit_size
== 64) {
5984 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
5985 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
5986 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
5987 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
5988 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
5989 emit_split_vector(ctx
, dst
, 2);
5991 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
5992 nir_print_instr(&instr
->instr
, stderr
);
5993 fprintf(stderr
, "\n");
5997 case nir_intrinsic_masked_swizzle_amd
: {
5998 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5999 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
6000 emit_uniform_subgroup(ctx
, instr
, src
);
6003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6004 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
6005 if (dst
.regClass() == v1
) {
6007 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
6009 } else if (dst
.regClass() == v2
) {
6010 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
6011 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
6012 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
6013 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
6014 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6015 emit_split_vector(ctx
, dst
, 2);
6017 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6018 nir_print_instr(&instr
->instr
, stderr
);
6019 fprintf(stderr
, "\n");
6023 case nir_intrinsic_write_invocation_amd
: {
6024 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6025 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6026 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6027 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6028 if (dst
.regClass() == v1
) {
6029 /* src2 is ignored for writelane. RA assigns the same reg for dst */
6030 emit_wqm(ctx
, bld
.vop3(aco_opcode::v_writelane_b32
, bld
.def(v1
), val
, lane
, src
), dst
);
6031 } else if (dst
.regClass() == v2
) {
6032 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
6033 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
6034 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
6035 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
6036 Temp lo
= emit_wqm(ctx
, bld
.vop3(aco_opcode::v_writelane_b32
, bld
.def(v1
), val_lo
, lane
, src_hi
));
6037 Temp hi
= emit_wqm(ctx
, bld
.vop3(aco_opcode::v_writelane_b32
, bld
.def(v1
), val_hi
, lane
, src_hi
));
6038 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
6039 emit_split_vector(ctx
, dst
, 2);
6041 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
6042 nir_print_instr(&instr
->instr
, stderr
);
6043 fprintf(stderr
, "\n");
6047 case nir_intrinsic_mbcnt_amd
: {
6048 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6049 RegClass rc
= RegClass(src
.type(), 1);
6050 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
6051 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
6052 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6053 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
6054 emit_wqm(ctx
, wqm_tmp
, dst
);
6057 case nir_intrinsic_load_helper_invocation
: {
6058 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6059 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
6060 ctx
->block
->kind
|= block_kind_needs_lowering
;
6061 ctx
->program
->needs_exact
= true;
6064 case nir_intrinsic_is_helper_invocation
: {
6065 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6066 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
6067 ctx
->block
->kind
|= block_kind_needs_lowering
;
6068 ctx
->program
->needs_exact
= true;
6071 case nir_intrinsic_demote
:
6072 bld
.pseudo(aco_opcode::p_demote_to_helper
);
6073 ctx
->block
->kind
|= block_kind_uses_demote
;
6074 ctx
->program
->needs_exact
= true;
6076 case nir_intrinsic_demote_if
: {
6077 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6078 assert(src
.regClass() == bld
.lm
);
6079 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6080 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
6081 ctx
->block
->kind
|= block_kind_uses_demote
;
6082 ctx
->program
->needs_exact
= true;
6085 case nir_intrinsic_first_invocation
: {
6086 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
6087 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6090 case nir_intrinsic_shader_clock
:
6091 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
6092 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
6094 case nir_intrinsic_load_vertex_id_zero_base
: {
6095 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6096 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
6099 case nir_intrinsic_load_first_vertex
: {
6100 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6101 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
6104 case nir_intrinsic_load_base_instance
: {
6105 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6106 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
6109 case nir_intrinsic_load_instance_id
: {
6110 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6111 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
6114 case nir_intrinsic_load_draw_id
: {
6115 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6116 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
6120 fprintf(stderr
, "Unimplemented intrinsic instr: ");
6121 nir_print_instr(&instr
->instr
, stderr
);
6122 fprintf(stderr
, "\n");
6130 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
6131 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
6132 enum glsl_base_type
*stype
)
6134 nir_deref_instr
*texture_deref_instr
= NULL
;
6135 nir_deref_instr
*sampler_deref_instr
= NULL
;
6138 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6139 switch (instr
->src
[i
].src_type
) {
6140 case nir_tex_src_texture_deref
:
6141 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6143 case nir_tex_src_sampler_deref
:
6144 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
6146 case nir_tex_src_plane
:
6147 plane
= nir_src_as_int(instr
->src
[i
].src
);
6154 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
6156 if (!sampler_deref_instr
)
6157 sampler_deref_instr
= texture_deref_instr
;
6160 assert(instr
->op
!= nir_texop_txf_ms
&&
6161 instr
->op
!= nir_texop_samples_identical
);
6162 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
6163 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
6164 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
6165 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
6167 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
6170 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
6171 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
6172 fprintf(stderr
, "Unimplemented sampler descriptor: ");
6173 nir_print_instr(&instr
->instr
, stderr
);
6174 fprintf(stderr
, "\n");
6176 // TODO: build samp_ptr = and(samp_ptr, res_ptr)
6179 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
6180 instr
->op
== nir_texop_samples_identical
))
6181 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
6184 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
6185 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
6187 Builder
bld(ctx
->program
, ctx
->block
);
6189 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
6190 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
6191 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
6193 Operand
neg_one(0xbf800000u
);
6194 Operand
one(0x3f800000u
);
6195 Operand
two(0x40000000u
);
6196 Operand
four(0x40800000u
);
6198 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
6199 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
6200 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
6202 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
6203 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(s2
), two
, id
);
6204 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
6205 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
6208 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
6209 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6210 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
6212 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6215 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
6216 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
6217 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
6220 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6221 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
6223 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
6224 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
6227 void prepare_cube_coords(isel_context
*ctx
, Temp
* coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
6229 Builder
bld(ctx
->program
, ctx
->block
);
6230 Temp coord_args
[4], ma
, tc
, sc
, id
;
6231 for (unsigned i
= 0; i
< (is_array
? 4 : 3); i
++)
6232 coord_args
[i
] = emit_extract_vector(ctx
, *coords
, i
, v1
);
6235 coord_args
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_args
[3]);
6237 // see comment in ac_prepare_cube_coords()
6238 if (ctx
->options
->chip_class
<= GFX8
)
6239 coord_args
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coord_args
[3]);
6242 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6244 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
6245 vop3a
->operands
[0] = Operand(ma
);
6246 vop3a
->abs
[0] = true;
6247 Temp invma
= bld
.tmp(v1
);
6248 vop3a
->definitions
[0] = Definition(invma
);
6249 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
6251 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6253 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6255 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6257 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
6259 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coord_args
[0], coord_args
[1], coord_args
[2]);
6262 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
6263 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
6265 for (unsigned i
= 0; i
< 2; i
++) {
6266 // see comment in ac_prepare_cube_coords()
6268 Temp deriv_sc
, deriv_tc
;
6269 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
6270 &deriv_ma
, &deriv_sc
, &deriv_tc
);
6272 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
6274 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6275 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
6276 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
6277 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
6278 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
6279 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
6280 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
6283 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
6284 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
6288 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coord_args
[3], id
, Operand(0x41000000u
/*8.0*/));
6289 *coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), sc
, tc
, id
);
6293 Temp
apply_round_slice(isel_context
*ctx
, Temp coords
, unsigned idx
)
6296 for (unsigned i
= 0; i
< coords
.size(); i
++)
6297 coord_vec
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
6299 Builder
bld(ctx
->program
, ctx
->block
);
6300 coord_vec
[idx
] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coord_vec
[idx
]);
6302 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
6303 for (unsigned i
= 0; i
< coords
.size(); i
++)
6304 vec
->operands
[i
] = Operand(coord_vec
[i
]);
6305 Temp res
= bld
.tmp(RegType::vgpr
, coords
.size());
6306 vec
->definitions
[0] = Definition(res
);
6307 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6311 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
6313 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
6315 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
6316 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
6319 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
6320 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
6321 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
6325 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
6327 Builder
bld(ctx
->program
, ctx
->block
);
6328 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
6329 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
6330 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), coords
, compare
= Temp(), sample_index
= Temp(),
6331 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(), derivs
= Temp();
6332 nir_const_value
*sample_index_cv
= NULL
;
6333 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
6334 enum glsl_base_type stype
;
6335 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
6337 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
6338 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
6339 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
6340 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
6342 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
6343 switch (instr
->src
[i
].src_type
) {
6344 case nir_tex_src_coord
:
6345 coords
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
));
6347 case nir_tex_src_bias
:
6348 if (instr
->op
== nir_texop_txb
) {
6349 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6353 case nir_tex_src_lod
: {
6354 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
6356 if (val
&& val
->f32
<= 0.0) {
6359 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6364 case nir_tex_src_comparator
:
6365 if (instr
->is_shadow
) {
6366 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6370 case nir_tex_src_offset
:
6371 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6372 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
6375 case nir_tex_src_ddx
:
6376 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6379 case nir_tex_src_ddy
:
6380 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6383 case nir_tex_src_ms_index
:
6384 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
6385 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
6386 has_sample_index
= true;
6388 case nir_tex_src_texture_offset
:
6389 case nir_tex_src_sampler_offset
:
6394 // TODO: all other cases: structure taken from ac_nir_to_llvm.c
6395 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
6396 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6398 if (instr
->op
== nir_texop_texture_samples
) {
6399 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
6401 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
6402 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
6403 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
6404 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
6406 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
6407 samples
, Operand(1u), bld
.scc(is_msaa
));
6411 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
6412 aco_ptr
<Instruction
> tmp_instr
;
6413 Temp acc
, pack
= Temp();
6415 uint32_t pack_const
= 0;
6416 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6417 if (!const_offset
[i
])
6419 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
6422 if (offset
.type() == RegType::sgpr
) {
6423 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6424 if (const_offset
[i
])
6427 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
6428 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
6431 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
6434 if (pack
== Temp()) {
6437 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
6441 if (pack_const
&& pack
!= Temp())
6442 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
6444 for (unsigned i
= 0; i
< offset
.size(); i
++) {
6445 if (const_offset
[i
])
6448 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
6449 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
6452 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
6455 if (pack
== Temp()) {
6458 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
6462 if (pack_const
&& pack
!= Temp())
6463 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
6465 if (pack_const
&& pack
== Temp())
6466 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
6467 else if (pack
== Temp())
6473 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
6474 prepare_cube_coords(ctx
, &coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
6476 /* pack derivatives */
6477 if (has_ddx
|| has_ddy
) {
6478 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
6479 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v4
),
6480 ddx
, Operand(0u), ddy
, Operand(0u));
6482 derivs
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, ddx
.size() + ddy
.size()), ddx
, ddy
);
6487 if (instr
->coord_components
> 1 &&
6488 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6490 instr
->op
!= nir_texop_txf
)
6491 coords
= apply_round_slice(ctx
, coords
, 1);
6493 if (instr
->coord_components
> 2 &&
6494 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
6495 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
6496 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
6497 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
6499 instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
)
6500 coords
= apply_round_slice(ctx
, coords
, 2);
6502 if (ctx
->options
->chip_class
== GFX9
&&
6503 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6504 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
6505 assert(coords
.size() > 0 && coords
.size() < 3);
6507 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size() + 1, 1)};
6508 vec
->operands
[0] = Operand(emit_extract_vector(ctx
, coords
, 0, v1
));
6509 vec
->operands
[1] = instr
->op
== nir_texop_txf
? Operand((uint32_t) 0) : Operand((uint32_t) 0x3f000000);
6510 if (coords
.size() > 1)
6511 vec
->operands
[2] = Operand(emit_extract_vector(ctx
, coords
, 1, v1
));
6512 coords
= bld
.tmp(RegType::vgpr
, coords
.size() + 1);
6513 vec
->definitions
[0] = Definition(coords
);
6514 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6517 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
6519 if (instr
->op
== nir_texop_samples_identical
)
6520 resource
= fmask_ptr
;
6522 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
6523 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
6524 instr
->op
!= nir_texop_txs
) {
6525 assert(has_sample_index
);
6526 Operand
op(sample_index
);
6527 if (sample_index_cv
)
6528 op
= Operand(sample_index_cv
->u32
);
6529 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
6532 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
6533 Temp split_coords
[coords
.size()];
6534 emit_split_vector(ctx
, coords
, coords
.size());
6535 for (unsigned i
= 0; i
< coords
.size(); i
++)
6536 split_coords
[i
] = emit_extract_vector(ctx
, coords
, i
, v1
);
6539 for (; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
6540 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
6541 split_coords
[i
] = bld
.vadd32(bld
.def(v1
), split_coords
[i
], off
);
6544 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
6545 for (unsigned i
= 0; i
< coords
.size(); i
++)
6546 vec
->operands
[i
] = Operand(split_coords
[i
]);
6547 coords
= bld
.tmp(coords
.regClass());
6548 vec
->definitions
[0] = Definition(coords
);
6549 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6554 /* Build tex instruction */
6555 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
6556 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
6557 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
6559 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6562 /* gather4 selects the component by dmask and always returns vec4 */
6563 if (instr
->op
== nir_texop_tg4
) {
6564 assert(instr
->dest
.ssa
.num_components
== 4);
6565 if (instr
->is_shadow
)
6568 dmask
= 1 << instr
->component
;
6569 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
6570 tmp_dst
= bld
.tmp(v4
);
6571 } else if (instr
->op
== nir_texop_samples_identical
) {
6572 tmp_dst
= bld
.tmp(v1
);
6573 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
6574 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
6577 aco_ptr
<MIMG_instruction
> tex
;
6578 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
6580 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6582 bool div_by_6
= instr
->op
== nir_texop_txs
&&
6583 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
6586 if (tmp_dst
.id() == dst
.id() && div_by_6
)
6587 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
6589 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
6590 tex
->operands
[0] = Operand(as_vgpr(ctx
,lod
));
6591 tex
->operands
[1] = Operand(resource
);
6592 if (ctx
->options
->chip_class
== GFX9
&&
6593 instr
->op
== nir_texop_txs
&&
6594 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
6596 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
6597 } else if (instr
->op
== nir_texop_query_levels
) {
6598 tex
->dmask
= 1 << 3;
6603 tex
->definitions
[0] = Definition(tmp_dst
);
6605 tex
->can_reorder
= true;
6606 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6609 /* divide 3rd value by 6 by multiplying with magic number */
6610 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
6611 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6612 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
6613 assert(instr
->dest
.ssa
.num_components
== 3);
6614 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
6615 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
6616 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
6617 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
6622 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
6626 Temp tg4_compare_cube_wa64
= Temp();
6628 if (tg4_integer_workarounds
) {
6629 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 2, 1));
6630 tex
->operands
[0] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6631 tex
->operands
[1] = Operand(resource
);
6635 Temp size
= bld
.tmp(v2
);
6636 tex
->definitions
[0] = Definition(size
);
6637 tex
->can_reorder
= true;
6638 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6639 emit_split_vector(ctx
, size
, size
.size());
6642 for (unsigned i
= 0; i
< 2; i
++) {
6643 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
6644 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
6645 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
6646 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
6649 Temp orig_coords
[2] = {
6650 emit_extract_vector(ctx
, coords
, 0, v1
),
6651 emit_extract_vector(ctx
, coords
, 1, v1
)};
6652 Temp new_coords
[2] = {
6653 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[0], half_texel
[0]),
6654 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), orig_coords
[1], half_texel
[1])
6657 if (tg4_integer_cube_workaround
) {
6658 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
6659 Temp desc
[resource
.size()];
6660 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
6661 Format::PSEUDO
, 1, resource
.size())};
6662 split
->operands
[0] = Operand(resource
);
6663 for (unsigned i
= 0; i
< resource
.size(); i
++) {
6664 desc
[i
] = bld
.tmp(s1
);
6665 split
->definitions
[i
] = Definition(desc
[i
]);
6667 ctx
->block
->instructions
.emplace_back(std::move(split
));
6669 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
6670 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
6671 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
6674 if (stype
== GLSL_TYPE_UINT
) {
6675 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
6676 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
6677 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
6678 bld
.scc(compare_cube_wa
));
6680 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
6681 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
6682 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
6683 bld
.scc(compare_cube_wa
));
6685 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
6686 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
6688 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
6690 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
6691 Operand((uint32_t)C_008F14_NUM_FORMAT
));
6692 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
6694 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
6695 Format::PSEUDO
, resource
.size(), 1)};
6696 for (unsigned i
= 0; i
< resource
.size(); i
++)
6697 vec
->operands
[i
] = Operand(desc
[i
]);
6698 resource
= bld
.tmp(resource
.regClass());
6699 vec
->definitions
[0] = Definition(resource
);
6700 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6702 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6703 new_coords
[0], orig_coords
[0], tg4_compare_cube_wa64
);
6704 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
6705 new_coords
[1], orig_coords
[1], tg4_compare_cube_wa64
);
6708 if (coords
.size() == 3) {
6709 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
),
6710 new_coords
[0], new_coords
[1],
6711 emit_extract_vector(ctx
, coords
, 2, v1
));
6713 assert(coords
.size() == 2);
6714 coords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
),
6715 new_coords
[0], new_coords
[1]);
6719 std::vector
<Operand
> args
;
6721 args
.emplace_back(Operand(offset
));
6723 args
.emplace_back(Operand(bias
));
6725 args
.emplace_back(Operand(compare
));
6727 args
.emplace_back(Operand(derivs
));
6728 args
.emplace_back(Operand(coords
));
6729 if (has_sample_index
)
6730 args
.emplace_back(Operand(sample_index
));
6732 args
.emplace_back(lod
);
6735 if (args
.size() > 1) {
6736 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
6738 for (unsigned i
= 0; i
< args
.size(); i
++) {
6739 size
+= args
[i
].size();
6740 vec
->operands
[i
] = args
[i
];
6742 RegClass rc
= RegClass(RegType::vgpr
, size
);
6743 Temp tmp
= bld
.tmp(rc
);
6744 vec
->definitions
[0] = Definition(tmp
);
6745 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6748 assert(args
[0].isTemp());
6749 arg
= as_vgpr(ctx
, args
[0].getTemp());
6752 /* we don't need the bias, sample index, compare value or offset to be
6753 * computed in WQM but if the p_create_vector copies the coordinates, then it
6754 * needs to be in WQM */
6755 if (!(has_ddx
&& has_ddy
) && !has_lod
&& !level_zero
&&
6756 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
6757 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
6758 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
6760 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
6761 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
6763 assert(coords
.size() == 1);
6764 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
6768 op
= aco_opcode::buffer_load_format_x
; break;
6770 op
= aco_opcode::buffer_load_format_xy
; break;
6772 op
= aco_opcode::buffer_load_format_xyz
; break;
6774 op
= aco_opcode::buffer_load_format_xyzw
; break;
6776 unreachable("Tex instruction loads more than 4 components.");
6779 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
6780 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
6783 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
6785 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
6786 mubuf
->operands
[0] = Operand(coords
);
6787 mubuf
->operands
[1] = Operand(resource
);
6788 mubuf
->operands
[2] = Operand((uint32_t) 0);
6789 mubuf
->definitions
[0] = Definition(tmp_dst
);
6790 mubuf
->idxen
= true;
6791 mubuf
->can_reorder
= true;
6792 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6794 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
6799 if (instr
->op
== nir_texop_txf
||
6800 instr
->op
== nir_texop_txf_ms
||
6801 instr
->op
== nir_texop_samples_identical
) {
6802 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
6803 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 2, 1));
6804 tex
->operands
[0] = Operand(arg
);
6805 tex
->operands
[1] = Operand(resource
);
6810 tex
->definitions
[0] = Definition(tmp_dst
);
6811 tex
->can_reorder
= true;
6812 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6814 if (instr
->op
== nir_texop_samples_identical
) {
6815 assert(dmask
== 1 && dst
.regClass() == v1
);
6816 assert(dst
.id() != tmp_dst
.id());
6818 Temp tmp
= bld
.tmp(bld
.lm
);
6819 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
6820 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
6823 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
6828 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
6829 aco_opcode opcode
= aco_opcode::image_sample
;
6830 if (has_offset
) { /* image_sample_*_o */
6832 opcode
= aco_opcode::image_sample_c_o
;
6834 opcode
= aco_opcode::image_sample_c_d_o
;
6836 opcode
= aco_opcode::image_sample_c_b_o
;
6838 opcode
= aco_opcode::image_sample_c_lz_o
;
6840 opcode
= aco_opcode::image_sample_c_l_o
;
6842 opcode
= aco_opcode::image_sample_o
;
6844 opcode
= aco_opcode::image_sample_d_o
;
6846 opcode
= aco_opcode::image_sample_b_o
;
6848 opcode
= aco_opcode::image_sample_lz_o
;
6850 opcode
= aco_opcode::image_sample_l_o
;
6852 } else { /* no offset */
6854 opcode
= aco_opcode::image_sample_c
;
6856 opcode
= aco_opcode::image_sample_c_d
;
6858 opcode
= aco_opcode::image_sample_c_b
;
6860 opcode
= aco_opcode::image_sample_c_lz
;
6862 opcode
= aco_opcode::image_sample_c_l
;
6864 opcode
= aco_opcode::image_sample
;
6866 opcode
= aco_opcode::image_sample_d
;
6868 opcode
= aco_opcode::image_sample_b
;
6870 opcode
= aco_opcode::image_sample_lz
;
6872 opcode
= aco_opcode::image_sample_l
;
6876 if (instr
->op
== nir_texop_tg4
) {
6878 opcode
= aco_opcode::image_gather4_lz_o
;
6880 opcode
= aco_opcode::image_gather4_c_lz_o
;
6882 opcode
= aco_opcode::image_gather4_lz
;
6884 opcode
= aco_opcode::image_gather4_c_lz
;
6886 } else if (instr
->op
== nir_texop_lod
) {
6887 opcode
= aco_opcode::image_get_lod
;
6890 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
6891 tex
->operands
[0] = Operand(arg
);
6892 tex
->operands
[1] = Operand(resource
);
6893 tex
->operands
[2] = Operand(sampler
);
6897 tex
->definitions
[0] = Definition(tmp_dst
);
6898 tex
->can_reorder
= true;
6899 ctx
->block
->instructions
.emplace_back(std::move(tex
));
6901 if (tg4_integer_cube_workaround
) {
6902 assert(tmp_dst
.id() != dst
.id());
6903 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
6905 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
6907 for (unsigned i
= 0; i
< dst
.size(); i
++) {
6908 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
6910 if (stype
== GLSL_TYPE_UINT
)
6911 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
6913 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
6914 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
6916 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
6917 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
6918 val
[0], val
[1], val
[2], val
[3]);
6920 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
6921 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
6926 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
6928 Temp tmp
= get_ssa_temp(ctx
, ssa
);
6929 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
6930 return Operand(tmp
.regClass());
6932 return Operand(tmp
);
6935 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
6937 aco_ptr
<Pseudo_instruction
> phi
;
6938 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6939 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
6941 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
6942 logical
|= ctx
->block
->kind
& block_kind_merge
;
6943 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
6945 /* we want a sorted list of sources, since the predecessor list is also sorted */
6946 std::map
<unsigned, nir_ssa_def
*> phi_src
;
6947 nir_foreach_phi_src(src
, instr
)
6948 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
6950 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
6951 unsigned num_operands
= 0;
6952 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size())];
6953 unsigned num_defined
= 0;
6954 unsigned cur_pred_idx
= 0;
6955 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
6956 if (cur_pred_idx
< preds
.size()) {
6957 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
6958 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
6959 unsigned skipped
= 0;
6960 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
6962 if (cur_pred_idx
+ skipped
< preds
.size()) {
6963 for (unsigned i
= 0; i
< skipped
; i
++)
6964 operands
[num_operands
++] = Operand(dst
.regClass());
6965 cur_pred_idx
+= skipped
;
6971 Operand op
= get_phi_operand(ctx
, src
.second
);
6972 operands
[num_operands
++] = op
;
6973 num_defined
+= !op
.isUndefined();
6975 /* handle block_kind_continue_or_break at loop exit blocks */
6976 while (cur_pred_idx
++ < preds
.size())
6977 operands
[num_operands
++] = Operand(dst
.regClass());
6979 if (num_defined
== 0) {
6980 Builder
bld(ctx
->program
, ctx
->block
);
6981 if (dst
.regClass() == s1
) {
6982 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
6983 } else if (dst
.regClass() == v1
) {
6984 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
6986 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
6987 for (unsigned i
= 0; i
< dst
.size(); i
++)
6988 vec
->operands
[i
] = Operand(0u);
6989 vec
->definitions
[0] = Definition(dst
);
6990 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6995 /* we can use a linear phi in some cases if one src is undef */
6996 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
6997 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
6999 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
7000 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
7001 assert(invert
->kind
& block_kind_invert
);
7003 unsigned then_block
= invert
->linear_preds
[0];
7005 Block
* insert_block
= NULL
;
7006 for (unsigned i
= 0; i
< num_operands
; i
++) {
7007 Operand op
= operands
[i
];
7008 if (op
.isUndefined())
7010 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
7011 phi
->operands
[0] = op
;
7014 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
7015 phi
->operands
[1] = Operand(dst
.regClass());
7016 phi
->definitions
[0] = Definition(dst
);
7017 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
7021 /* try to scalarize vector phis */
7022 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
7023 // TODO: scalarize linear phis on divergent ifs
7024 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
7025 std::array
<Temp
, 4> new_vec
;
7026 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
7027 Operand src
= operands
[i
];
7028 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
7029 can_scalarize
= false;
7031 if (can_scalarize
) {
7032 unsigned num_components
= instr
->dest
.ssa
.num_components
;
7033 assert(dst
.size() % num_components
== 0);
7034 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
7036 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
7037 for (unsigned k
= 0; k
< num_components
; k
++) {
7038 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7039 for (unsigned i
= 0; i
< num_operands
; i
++) {
7040 Operand src
= operands
[i
];
7041 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
7043 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
7044 phi
->definitions
[0] = Definition(phi_dst
);
7045 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7046 new_vec
[k
] = phi_dst
;
7047 vec
->operands
[k
] = Operand(phi_dst
);
7049 vec
->definitions
[0] = Definition(dst
);
7050 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7051 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
7056 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
7057 for (unsigned i
= 0; i
< num_operands
; i
++)
7058 phi
->operands
[i
] = operands
[i
];
7059 phi
->definitions
[0] = Definition(dst
);
7060 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
7064 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
7066 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
7068 assert(dst
.type() == RegType::sgpr
);
7070 if (dst
.size() == 1) {
7071 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
7073 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
7074 for (unsigned i
= 0; i
< dst
.size(); i
++)
7075 vec
->operands
[i
] = Operand(0u);
7076 vec
->definitions
[0] = Definition(dst
);
7077 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7081 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
7083 Builder
bld(ctx
->program
, ctx
->block
);
7084 Block
*logical_target
;
7085 append_logical_end(ctx
->block
);
7086 unsigned idx
= ctx
->block
->index
;
7088 switch (instr
->type
) {
7089 case nir_jump_break
:
7090 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
7091 add_logical_edge(idx
, logical_target
);
7092 ctx
->block
->kind
|= block_kind_break
;
7094 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
7095 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
7096 /* uniform break - directly jump out of the loop */
7097 ctx
->block
->kind
|= block_kind_uniform
;
7098 ctx
->cf_info
.has_branch
= true;
7099 bld
.branch(aco_opcode::p_branch
);
7100 add_linear_edge(idx
, logical_target
);
7103 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7104 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7106 case nir_jump_continue
:
7107 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7108 add_logical_edge(idx
, logical_target
);
7109 ctx
->block
->kind
|= block_kind_continue
;
7111 if (ctx
->cf_info
.parent_if
.is_divergent
) {
7112 /* for potential uniform breaks after this continue,
7113 we must ensure that they are handled correctly */
7114 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
7115 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
7116 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
7118 /* uniform continue - directly jump to the loop header */
7119 ctx
->block
->kind
|= block_kind_uniform
;
7120 ctx
->cf_info
.has_branch
= true;
7121 bld
.branch(aco_opcode::p_branch
);
7122 add_linear_edge(idx
, logical_target
);
7127 fprintf(stderr
, "Unknown NIR jump instr: ");
7128 nir_print_instr(&instr
->instr
, stderr
);
7129 fprintf(stderr
, "\n");
7133 /* remove critical edges from linear CFG */
7134 bld
.branch(aco_opcode::p_branch
);
7135 Block
* break_block
= ctx
->program
->create_and_insert_block();
7136 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7137 break_block
->kind
|= block_kind_uniform
;
7138 add_linear_edge(idx
, break_block
);
7139 /* the loop_header pointer might be invalidated by this point */
7140 if (instr
->type
== nir_jump_continue
)
7141 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
7142 add_linear_edge(break_block
->index
, logical_target
);
7143 bld
.reset(break_block
);
7144 bld
.branch(aco_opcode::p_branch
);
7146 Block
* continue_block
= ctx
->program
->create_and_insert_block();
7147 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7148 add_linear_edge(idx
, continue_block
);
7149 append_logical_start(continue_block
);
7150 ctx
->block
= continue_block
;
7154 void visit_block(isel_context
*ctx
, nir_block
*block
)
7156 nir_foreach_instr(instr
, block
) {
7157 switch (instr
->type
) {
7158 case nir_instr_type_alu
:
7159 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
7161 case nir_instr_type_load_const
:
7162 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
7164 case nir_instr_type_intrinsic
:
7165 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
7167 case nir_instr_type_tex
:
7168 visit_tex(ctx
, nir_instr_as_tex(instr
));
7170 case nir_instr_type_phi
:
7171 visit_phi(ctx
, nir_instr_as_phi(instr
));
7173 case nir_instr_type_ssa_undef
:
7174 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
7176 case nir_instr_type_deref
:
7178 case nir_instr_type_jump
:
7179 visit_jump(ctx
, nir_instr_as_jump(instr
));
7182 fprintf(stderr
, "Unknown NIR instr type: ");
7183 nir_print_instr(instr
, stderr
);
7184 fprintf(stderr
, "\n");
7189 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7190 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
7195 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
7197 append_logical_end(ctx
->block
);
7198 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
7199 Builder
bld(ctx
->program
, ctx
->block
);
7200 bld
.branch(aco_opcode::p_branch
);
7201 unsigned loop_preheader_idx
= ctx
->block
->index
;
7203 Block loop_exit
= Block();
7204 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7205 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
7207 Block
* loop_header
= ctx
->program
->create_and_insert_block();
7208 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
7209 loop_header
->kind
|= block_kind_loop_header
;
7210 add_edge(loop_preheader_idx
, loop_header
);
7211 ctx
->block
= loop_header
;
7213 /* emit loop body */
7214 unsigned loop_header_idx
= loop_header
->index
;
7215 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
7216 append_logical_start(ctx
->block
);
7217 visit_cf_list(ctx
, &loop
->body
);
7219 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
7220 if (!ctx
->cf_info
.has_branch
) {
7221 append_logical_end(ctx
->block
);
7222 if (ctx
->cf_info
.exec_potentially_empty
) {
7223 /* Discards can result in code running with an empty exec mask.
7224 * This would result in divergent breaks not ever being taken. As a
7225 * workaround, break the loop when the loop mask is empty instead of
7226 * always continuing. */
7227 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
7228 unsigned block_idx
= ctx
->block
->index
;
7230 /* create helper blocks to avoid critical edges */
7231 Block
*break_block
= ctx
->program
->create_and_insert_block();
7232 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7233 break_block
->kind
= block_kind_uniform
;
7234 bld
.reset(break_block
);
7235 bld
.branch(aco_opcode::p_branch
);
7236 add_linear_edge(block_idx
, break_block
);
7237 add_linear_edge(break_block
->index
, &loop_exit
);
7239 Block
*continue_block
= ctx
->program
->create_and_insert_block();
7240 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7241 continue_block
->kind
= block_kind_uniform
;
7242 bld
.reset(continue_block
);
7243 bld
.branch(aco_opcode::p_branch
);
7244 add_linear_edge(block_idx
, continue_block
);
7245 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7247 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
7248 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
7250 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
7251 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7252 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7254 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
7257 bld
.reset(ctx
->block
);
7258 bld
.branch(aco_opcode::p_branch
);
7261 /* fixup phis in loop header from unreachable blocks */
7262 if (ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
) {
7263 bool linear
= ctx
->cf_info
.has_branch
;
7264 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7265 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
7266 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
7267 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
7268 /* the last operand should be the one that needs to be removed */
7269 instr
->operands
.pop_back();
7270 } else if (!is_phi(instr
)) {
7276 ctx
->cf_info
.has_branch
= false;
7278 // TODO: if the loop has not a single exit, we must add one °°
7279 /* emit loop successor block */
7280 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
7281 append_logical_start(ctx
->block
);
7284 // TODO: check if it is beneficial to not branch on continues
7285 /* trim linear phis in loop header */
7286 for (auto&& instr
: loop_entry
->instructions
) {
7287 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
7288 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
7289 new_phi
->definitions
[0] = instr
->definitions
[0];
7290 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
7291 new_phi
->operands
[i
] = instr
->operands
[i
];
7292 /* check that the remaining operands are all the same */
7293 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
7294 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
7295 instr
.swap(new_phi
);
7296 } else if (instr
->opcode
== aco_opcode::p_phi
) {
7305 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
7309 append_logical_end(ctx
->block
);
7310 ctx
->block
->kind
|= block_kind_branch
;
7312 /* branch to linear then block */
7313 assert(cond
.regClass() == ctx
->program
->lane_mask
);
7314 aco_ptr
<Pseudo_branch_instruction
> branch
;
7315 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
7316 branch
->operands
[0] = Operand(cond
);
7317 ctx
->block
->instructions
.push_back(std::move(branch
));
7319 ic
->BB_if_idx
= ctx
->block
->index
;
7320 ic
->BB_invert
= Block();
7321 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7322 /* Invert blocks are intentionally not marked as top level because they
7323 * are not part of the logical cfg. */
7324 ic
->BB_invert
.kind
|= block_kind_invert
;
7325 ic
->BB_endif
= Block();
7326 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7327 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
7329 ic
->exec_potentially_empty_old
= ctx
->cf_info
.exec_potentially_empty
;
7330 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
7331 ctx
->cf_info
.parent_if
.is_divergent
= true;
7332 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
7334 /** emit logical then block */
7335 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
7336 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7337 add_edge(ic
->BB_if_idx
, BB_then_logical
);
7338 ctx
->block
= BB_then_logical
;
7339 append_logical_start(BB_then_logical
);
7342 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
7344 Block
*BB_then_logical
= ctx
->block
;
7345 append_logical_end(BB_then_logical
);
7346 /* branch from logical then block to invert block */
7347 aco_ptr
<Pseudo_branch_instruction
> branch
;
7348 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7349 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
7350 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
7351 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7352 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
7353 BB_then_logical
->kind
|= block_kind_uniform
;
7354 assert(!ctx
->cf_info
.has_branch
);
7355 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7356 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
7358 /** emit linear then block */
7359 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
7360 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7361 BB_then_linear
->kind
|= block_kind_uniform
;
7362 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
7363 /* branch from linear then block to invert block */
7364 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7365 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
7366 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
7368 /** emit invert merge block */
7369 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
7370 ic
->invert_idx
= ctx
->block
->index
;
7372 /* branch to linear else block (skip else) */
7373 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
7374 branch
->operands
[0] = Operand(ic
->cond
);
7375 ctx
->block
->instructions
.push_back(std::move(branch
));
7377 ic
->exec_potentially_empty_old
|= ctx
->cf_info
.exec_potentially_empty
;
7378 ctx
->cf_info
.exec_potentially_empty
= false; /* divergent branches use cbranch_execz */
7380 /** emit logical else block */
7381 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
7382 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7383 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
7384 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
7385 ctx
->block
= BB_else_logical
;
7386 append_logical_start(BB_else_logical
);
7389 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
7391 Block
*BB_else_logical
= ctx
->block
;
7392 append_logical_end(BB_else_logical
);
7394 /* branch from logical else block to endif block */
7395 aco_ptr
<Pseudo_branch_instruction
> branch
;
7396 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7397 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
7398 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
7399 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7400 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
7401 BB_else_logical
->kind
|= block_kind_uniform
;
7403 assert(!ctx
->cf_info
.has_branch
);
7404 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
7407 /** emit linear else block */
7408 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
7409 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7410 BB_else_linear
->kind
|= block_kind_uniform
;
7411 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
7413 /* branch from linear else block to endif block */
7414 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7415 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
7416 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
7419 /** emit endif merge block */
7420 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
7421 append_logical_start(ctx
->block
);
7424 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
7425 ctx
->cf_info
.exec_potentially_empty
|= ic
->exec_potentially_empty_old
;
7426 /* uniform control flow never has an empty exec-mask */
7427 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
7428 ctx
->cf_info
.exec_potentially_empty
= false;
7431 static void visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
7433 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
7434 Builder
bld(ctx
->program
, ctx
->block
);
7435 aco_ptr
<Pseudo_branch_instruction
> branch
;
7437 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
7439 * Uniform conditionals are represented in the following way*) :
7441 * The linear and logical CFG:
7444 * BB_THEN (logical) BB_ELSE (logical)
7448 * *) Exceptions may be due to break and continue statements within loops
7449 * If a break/continue happens within uniform control flow, it branches
7450 * to the loop exit/entry block. Otherwise, it branches to the next
7453 append_logical_end(ctx
->block
);
7454 ctx
->block
->kind
|= block_kind_uniform
;
7457 assert(cond
.regClass() == bld
.lm
);
7458 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
7459 cond
= bool_to_scalar_condition(ctx
, cond
);
7461 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
7462 branch
->operands
[0] = Operand(cond
);
7463 branch
->operands
[0].setFixed(scc
);
7464 ctx
->block
->instructions
.emplace_back(std::move(branch
));
7466 unsigned BB_if_idx
= ctx
->block
->index
;
7467 Block BB_endif
= Block();
7468 BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7469 BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
7471 /** emit then block */
7472 Block
* BB_then
= ctx
->program
->create_and_insert_block();
7473 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7474 add_edge(BB_if_idx
, BB_then
);
7475 append_logical_start(BB_then
);
7476 ctx
->block
= BB_then
;
7477 visit_cf_list(ctx
, &if_stmt
->then_list
);
7478 BB_then
= ctx
->block
;
7479 bool then_branch
= ctx
->cf_info
.has_branch
;
7480 bool then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
7483 append_logical_end(BB_then
);
7484 /* branch from then block to endif block */
7485 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7486 BB_then
->instructions
.emplace_back(std::move(branch
));
7487 add_linear_edge(BB_then
->index
, &BB_endif
);
7488 if (!then_branch_divergent
)
7489 add_logical_edge(BB_then
->index
, &BB_endif
);
7490 BB_then
->kind
|= block_kind_uniform
;
7493 ctx
->cf_info
.has_branch
= false;
7494 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
7496 /** emit else block */
7497 Block
* BB_else
= ctx
->program
->create_and_insert_block();
7498 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
7499 add_edge(BB_if_idx
, BB_else
);
7500 append_logical_start(BB_else
);
7501 ctx
->block
= BB_else
;
7502 visit_cf_list(ctx
, &if_stmt
->else_list
);
7503 BB_else
= ctx
->block
;
7505 if (!ctx
->cf_info
.has_branch
) {
7506 append_logical_end(BB_else
);
7507 /* branch from then block to endif block */
7508 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
7509 BB_else
->instructions
.emplace_back(std::move(branch
));
7510 add_linear_edge(BB_else
->index
, &BB_endif
);
7511 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
7512 add_logical_edge(BB_else
->index
, &BB_endif
);
7513 BB_else
->kind
|= block_kind_uniform
;
7516 ctx
->cf_info
.has_branch
&= then_branch
;
7517 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= then_branch_divergent
;
7519 /** emit endif merge block */
7520 if (!ctx
->cf_info
.has_branch
) {
7521 ctx
->block
= ctx
->program
->insert_block(std::move(BB_endif
));
7522 append_logical_start(ctx
->block
);
7524 } else { /* non-uniform condition */
7526 * To maintain a logical and linear CFG without critical edges,
7527 * non-uniform conditionals are represented in the following way*) :
7532 * BB_THEN (logical) BB_THEN (linear)
7534 * BB_INVERT (linear)
7536 * BB_ELSE (logical) BB_ELSE (linear)
7543 * BB_THEN (logical) BB_ELSE (logical)
7547 * *) Exceptions may be due to break and continue statements within loops
7552 begin_divergent_if_then(ctx
, &ic
, cond
);
7553 visit_cf_list(ctx
, &if_stmt
->then_list
);
7555 begin_divergent_if_else(ctx
, &ic
);
7556 visit_cf_list(ctx
, &if_stmt
->else_list
);
7558 end_divergent_if(ctx
, &ic
);
7562 static void visit_cf_list(isel_context
*ctx
,
7563 struct exec_list
*list
)
7565 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
7566 switch (node
->type
) {
7567 case nir_cf_node_block
:
7568 visit_block(ctx
, nir_cf_node_as_block(node
));
7570 case nir_cf_node_if
:
7571 visit_if(ctx
, nir_cf_node_as_if(node
));
7573 case nir_cf_node_loop
:
7574 visit_loop(ctx
, nir_cf_node_as_loop(node
));
7577 unreachable("unimplemented cf list type");
7582 static void export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
7584 int offset
= ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
7585 uint64_t mask
= ctx
->vs_output
.mask
[slot
];
7586 if (!is_pos
&& !mask
)
7588 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
7590 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
7591 exp
->enabled_mask
= mask
;
7592 for (unsigned i
= 0; i
< 4; ++i
) {
7593 if (mask
& (1 << i
))
7594 exp
->operands
[i
] = Operand(ctx
->vs_output
.outputs
[slot
][i
]);
7596 exp
->operands
[i
] = Operand(v1
);
7598 exp
->valid_mask
= false;
7600 exp
->compressed
= false;
7602 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
7604 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
7605 ctx
->block
->instructions
.emplace_back(std::move(exp
));
7608 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
7610 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
7611 exp
->enabled_mask
= 0;
7612 for (unsigned i
= 0; i
< 4; ++i
)
7613 exp
->operands
[i
] = Operand(v1
);
7614 if (ctx
->vs_output
.mask
[VARYING_SLOT_PSIZ
]) {
7615 exp
->operands
[0] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_PSIZ
][0]);
7616 exp
->enabled_mask
|= 0x1;
7618 if (ctx
->vs_output
.mask
[VARYING_SLOT_LAYER
]) {
7619 exp
->operands
[2] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_LAYER
][0]);
7620 exp
->enabled_mask
|= 0x4;
7622 if (ctx
->vs_output
.mask
[VARYING_SLOT_VIEWPORT
]) {
7623 if (ctx
->options
->chip_class
< GFX9
) {
7624 exp
->operands
[3] = Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_VIEWPORT
][0]);
7625 exp
->enabled_mask
|= 0x8;
7627 Builder
bld(ctx
->program
, ctx
->block
);
7629 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
7630 Operand(ctx
->vs_output
.outputs
[VARYING_SLOT_VIEWPORT
][0]));
7631 if (exp
->operands
[2].isTemp())
7632 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
7634 exp
->operands
[2] = Operand(out
);
7635 exp
->enabled_mask
|= 0x4;
7638 exp
->valid_mask
= false;
7640 exp
->compressed
= false;
7641 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
7642 ctx
->block
->instructions
.emplace_back(std::move(exp
));
7645 static void create_vs_exports(isel_context
*ctx
)
7647 radv_vs_output_info
*outinfo
= &ctx
->program
->info
->vs
.outinfo
;
7649 if (outinfo
->export_prim_id
) {
7650 ctx
->vs_output
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
7651 ctx
->vs_output
.outputs
[VARYING_SLOT_PRIMITIVE_ID
][0] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
7654 if (ctx
->options
->key
.has_multiview_view_index
) {
7655 ctx
->vs_output
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
7656 ctx
->vs_output
.outputs
[VARYING_SLOT_LAYER
][0] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
7659 /* the order these position exports are created is important */
7661 export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
7662 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
7663 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
7665 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
7666 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
7667 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
7668 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
7670 if (ctx
->options
->key
.vs_common_out
.export_clip_dists
) {
7671 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
7672 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
7673 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
7674 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
7677 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
7678 if (i
< VARYING_SLOT_VAR0
&& i
!= VARYING_SLOT_LAYER
&&
7679 i
!= VARYING_SLOT_PRIMITIVE_ID
)
7682 export_vs_varying(ctx
, i
, false, NULL
);
7686 static void emit_stream_output(isel_context
*ctx
,
7687 Temp
const *so_buffers
,
7688 Temp
const *so_write_offset
,
7689 const struct radv_stream_output
*output
)
7691 unsigned num_comps
= util_bitcount(output
->component_mask
);
7692 unsigned loc
= output
->location
;
7693 unsigned buf
= output
->buffer
;
7694 unsigned offset
= output
->offset
;
7696 assert(num_comps
&& num_comps
<= 4);
7697 if (!num_comps
|| num_comps
> 4)
7700 unsigned start
= ffs(output
->component_mask
) - 1;
7703 bool all_undef
= true;
7704 assert(ctx
->stage
== vertex_vs
);
7705 for (unsigned i
= 0; i
< num_comps
; i
++) {
7706 out
[i
] = ctx
->vs_output
.outputs
[loc
][start
+ i
];
7707 all_undef
= all_undef
&& !out
[i
].id();
7712 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_comps
)};
7713 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_comps
, 1)};
7714 for (unsigned i
= 0; i
< num_comps
; ++i
)
7715 vec
->operands
[i
] = (ctx
->vs_output
.mask
[loc
] & 1 << i
) ? Operand(out
[i
]) : Operand(0u);
7716 vec
->definitions
[0] = Definition(write_data
);
7717 ctx
->block
->instructions
.emplace_back(std::move(vec
));
7720 switch (num_comps
) {
7722 opcode
= aco_opcode::buffer_store_dword
;
7725 opcode
= aco_opcode::buffer_store_dwordx2
;
7728 opcode
= aco_opcode::buffer_store_dwordx3
;
7731 opcode
= aco_opcode::buffer_store_dwordx4
;
7735 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
7736 store
->operands
[0] = Operand(so_write_offset
[buf
]);
7737 store
->operands
[1] = Operand(so_buffers
[buf
]);
7738 store
->operands
[2] = Operand((uint32_t) 0);
7739 store
->operands
[3] = Operand(write_data
);
7740 if (offset
> 4095) {
7741 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
7742 Builder
bld(ctx
->program
, ctx
->block
);
7743 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
7745 store
->offset
= offset
;
7747 store
->offen
= true;
7751 store
->can_reorder
= true;
7752 ctx
->block
->instructions
.emplace_back(std::move(store
));
7755 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
7757 Builder
bld(ctx
->program
, ctx
->block
);
7760 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
7761 for (unsigned i
= 0; i
< 4; i
++) {
7762 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
7766 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, Operand(i
* 16u));
7769 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7770 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
7772 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
7774 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), so_vtx_count
, tid
);
7777 begin_divergent_if_then(ctx
, &ic
, can_emit
);
7779 bld
.reset(ctx
->block
);
7781 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
7783 Temp so_write_offset
[4];
7785 for (unsigned i
= 0; i
< 4; i
++) {
7786 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
7791 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
7792 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
7793 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
7794 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
7796 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
7798 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
7799 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
7800 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
7801 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
7805 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
7806 struct radv_stream_output
*output
=
7807 &ctx
->program
->info
->so
.outputs
[i
];
7808 if (stream
!= output
->stream
)
7811 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
7814 begin_divergent_if_else(ctx
, &ic
);
7815 end_divergent_if(ctx
, &ic
);
7818 } /* end namespace */
7820 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
7822 /* Split all arguments except for the first (ring_offsets) and the last
7823 * (exec) so that the dead channels don't stay live throughout the program.
7825 for (unsigned i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
7826 if (startpgm
->definitions
[i
].regClass().size() > 1) {
7827 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
7828 startpgm
->definitions
[i
].regClass().size());
7833 void handle_bc_optimize(isel_context
*ctx
)
7835 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
7836 Builder
bld(ctx
->program
, ctx
->block
);
7837 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
7838 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
7839 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
7840 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
7841 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
7842 if (uses_center
&& uses_centroid
) {
7843 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
7844 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
7846 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
7848 for (unsigned i
= 0; i
< 2; i
++) {
7849 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
7850 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
7851 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7852 persp_centroid
, persp_center
, sel
);
7854 ctx
->persp_centroid
= bld
.tmp(v2
);
7855 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
7856 Operand(new_coord
[0]), Operand(new_coord
[1]));
7857 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
7860 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
7862 for (unsigned i
= 0; i
< 2; i
++) {
7863 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
7864 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
7865 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
7866 linear_centroid
, linear_center
, sel
);
7868 ctx
->linear_centroid
= bld
.tmp(v2
);
7869 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
7870 Operand(new_coord
[0]), Operand(new_coord
[1]));
7871 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
7876 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
7878 Program
*program
= ctx
->program
;
7880 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
7882 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
7883 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
7884 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
7885 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
7886 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
7888 program
->next_fp_mode
.must_flush_denorms32
=
7889 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
7890 program
->next_fp_mode
.must_flush_denorms16_64
=
7891 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
7892 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
7894 program
->next_fp_mode
.care_about_round32
=
7895 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
7897 program
->next_fp_mode
.care_about_round16_64
=
7898 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
7899 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
7901 /* default to preserving fp16 and fp64 denorms, since it's free */
7902 if (program
->next_fp_mode
.must_flush_denorms16_64
)
7903 program
->next_fp_mode
.denorm16_64
= 0;
7905 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
7907 /* preserving fp32 denorms is expensive, so only do it if asked */
7908 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
7909 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
7911 program
->next_fp_mode
.denorm32
= 0;
7913 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
7914 program
->next_fp_mode
.round32
= fp_round_tz
;
7916 program
->next_fp_mode
.round32
= fp_round_ne
;
7918 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
7919 program
->next_fp_mode
.round16_64
= fp_round_tz
;
7921 program
->next_fp_mode
.round16_64
= fp_round_ne
;
7923 ctx
->block
->fp_mode
= program
->next_fp_mode
;
7926 void select_program(Program
*program
,
7927 unsigned shader_count
,
7928 struct nir_shader
*const *shaders
,
7929 ac_shader_config
* config
,
7930 struct radv_shader_args
*args
)
7932 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
);
7934 for (unsigned i
= 0; i
< shader_count
; i
++) {
7935 nir_shader
*nir
= shaders
[i
];
7936 init_context(&ctx
, nir
);
7938 setup_fp_mode(&ctx
, nir
);
7941 /* needs to be after init_context() for FS */
7942 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
7943 append_logical_start(ctx
.block
);
7944 split_arguments(&ctx
, startpgm
);
7948 if (shader_count
>= 2) {
7949 Builder
bld(ctx
.program
, ctx
.block
);
7950 Temp count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), ctx
.merged_wave_info
, Operand((8u << 16) | (i
* 8u)));
7951 Temp thread_id
= emit_mbcnt(&ctx
, bld
.def(v1
));
7952 Temp cond
= bld
.vopc(aco_opcode::v_cmp_gt_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), count
, thread_id
);
7954 begin_divergent_if_then(&ctx
, &ic
, cond
);
7958 Builder
bld(ctx
.program
, ctx
.block
);
7959 bld
.barrier(aco_opcode::p_memory_barrier_shared
); //TODO: different barriers are needed for different stages
7960 bld
.sopp(aco_opcode::s_barrier
);
7963 if (ctx
.stage
== fragment_fs
)
7964 handle_bc_optimize(&ctx
);
7966 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
7967 visit_cf_list(&ctx
, &func
->body
);
7969 if (ctx
.program
->info
->so
.num_outputs
/*&& !ctx->is_gs_copy_shader */)
7970 emit_streamout(&ctx
, 0);
7972 if (ctx
.stage
== vertex_vs
)
7973 create_vs_exports(&ctx
);
7975 if (shader_count
>= 2) {
7976 begin_divergent_if_else(&ctx
, &ic
);
7977 end_divergent_if(&ctx
, &ic
);
7980 ralloc_free(ctx
.divergent_vals
);
7983 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
7985 append_logical_end(ctx
.block
);
7986 ctx
.block
->kind
|= block_kind_uniform
;
7987 Builder
bld(ctx
.program
, ctx
.block
);
7988 if (ctx
.program
->wb_smem_l1_on_end
)
7989 bld
.smem(aco_opcode::s_dcache_wb
, false);
7990 bld
.sopp(aco_opcode::s_endpgm
);
7993 for (Block
& BB
: program
->blocks
) {
7994 for (unsigned idx
: BB
.linear_preds
)
7995 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
7996 for (unsigned idx
: BB
.logical_preds
)
7997 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);