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3 * Copyright © 2018 Google
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10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 class loop_info_RAII
{
43 unsigned header_idx_old
;
45 bool divergent_cont_old
;
46 bool divergent_branch_old
;
47 bool divergent_if_old
;
50 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
52 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
53 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
54 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
55 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
57 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
58 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
59 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
60 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
61 ctx
->cf_info
.parent_if
.is_divergent
= false;
62 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
67 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
68 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
69 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
70 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
71 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
72 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
73 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.exec_potentially_empty_discard
= false;
82 bool exec_potentially_empty_discard_old
;
83 bool exec_potentially_empty_break_old
;
84 uint16_t exec_potentially_empty_break_depth_old
;
88 bool uniform_has_then_branch
;
89 bool then_branch_divergent
;
94 static bool visit_cf_list(struct isel_context
*ctx
,
95 struct exec_list
*list
);
97 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
99 succ
->logical_preds
.emplace_back(pred_idx
);
103 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
105 succ
->linear_preds
.emplace_back(pred_idx
);
108 static void add_edge(unsigned pred_idx
, Block
*succ
)
110 add_logical_edge(pred_idx
, succ
);
111 add_linear_edge(pred_idx
, succ
);
114 static void append_logical_start(Block
*b
)
116 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
119 static void append_logical_end(Block
*b
)
121 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
124 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
126 assert(ctx
->allocated
[def
->index
].id());
127 return ctx
->allocated
[def
->index
];
130 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
131 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
133 Builder
bld(ctx
->program
, ctx
->block
);
134 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
135 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
137 if (ctx
->program
->wave_size
== 32) {
140 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
145 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
147 Builder
bld(ctx
->program
, ctx
->block
);
150 dst
= bld
.tmp(src
.regClass());
152 assert(src
.size() == dst
.size());
154 if (ctx
->stage
!= fragment_fs
) {
158 bld
.copy(Definition(dst
), src
);
162 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
163 ctx
->program
->needs_wqm
|= program_needs_wqm
;
167 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
169 if (index
.regClass() == s1
)
170 return bld
.readlane(bld
.def(s1
), data
, index
);
172 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
174 /* Currently not implemented on GFX6-7 */
175 assert(ctx
->options
->chip_class
>= GFX8
);
177 if (ctx
->options
->chip_class
<= GFX9
|| ctx
->program
->wave_size
== 32) {
178 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
181 /* GFX10, wave64 mode:
182 * The bpermute instruction is limited to half-wave operation, which means that it can't
183 * properly support subgroup shuffle like older generations (or wave32 mode), so we
186 if (!ctx
->has_gfx10_wave64_bpermute
) {
187 ctx
->has_gfx10_wave64_bpermute
= true;
188 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
189 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
192 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
193 Temp lane_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), lane_id
);
194 Temp index_is_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x20u
), index
);
195 Temp cmp
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
, vcc
), lane_is_hi
, index_is_hi
);
197 return bld
.reduction(aco_opcode::p_wave64_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
),
198 bld
.vcc(cmp
), Operand(v2
.as_linear()), index_x4
, data
, gfx10_wave64_bpermute
);
201 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
203 if (val
.type() == RegType::sgpr
) {
204 Builder
bld(ctx
->program
, ctx
->block
);
205 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
207 assert(val
.type() == RegType::vgpr
);
211 //assumes a != 0xffffffff
212 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
215 Builder
bld(ctx
->program
, ctx
->block
);
217 if (util_is_power_of_two_or_zero(b
)) {
218 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
222 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
224 assert(info
.multiplier
<= 0xffffffff);
226 bool pre_shift
= info
.pre_shift
!= 0;
227 bool increment
= info
.increment
!= 0;
228 bool multiply
= true;
229 bool post_shift
= info
.post_shift
!= 0;
231 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
232 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
236 Temp pre_shift_dst
= a
;
238 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
239 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
242 Temp increment_dst
= pre_shift_dst
;
244 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
245 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
248 Temp multiply_dst
= increment_dst
;
250 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
251 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
252 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
256 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
260 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
262 Builder
bld(ctx
->program
, ctx
->block
);
263 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
267 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
269 /* no need to extract the whole vector */
270 if (src
.regClass() == dst_rc
) {
275 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
276 Builder
bld(ctx
->program
, ctx
->block
);
277 auto it
= ctx
->allocated_vec
.find(src
.id());
278 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
279 if (it
->second
[idx
].regClass() == dst_rc
) {
280 return it
->second
[idx
];
282 assert(!dst_rc
.is_subdword());
283 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
284 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
288 if (dst_rc
.is_subdword())
289 src
= as_vgpr(ctx
, src
);
291 if (src
.bytes() == dst_rc
.bytes()) {
293 return bld
.copy(bld
.def(dst_rc
), src
);
295 Temp dst
= bld
.tmp(dst_rc
);
296 emit_extract_vector(ctx
, src
, idx
, dst
);
301 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
303 if (num_components
== 1)
305 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
307 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
308 split
->operands
[0] = Operand(vec_src
);
309 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
311 if (num_components
> vec_src
.size()) {
312 if (vec_src
.type() == RegType::sgpr
)
315 /* sub-dword split */
316 assert(vec_src
.type() == RegType::vgpr
);
317 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
319 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
321 for (unsigned i
= 0; i
< num_components
; i
++) {
322 elems
[i
] = {ctx
->program
->allocateId(), rc
};
323 split
->definitions
[i
] = Definition(elems
[i
]);
325 ctx
->block
->instructions
.emplace_back(std::move(split
));
326 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
329 /* This vector expansion uses a mask to determine which elements in the new vector
330 * come from the original vector. The other elements are undefined. */
331 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
333 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
338 Builder
bld(ctx
->program
, ctx
->block
);
339 if (num_components
== 1) {
340 if (dst
.type() == RegType::sgpr
)
341 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
343 bld
.copy(Definition(dst
), vec_src
);
347 unsigned component_size
= dst
.size() / num_components
;
348 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
350 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
351 vec
->definitions
[0] = Definition(dst
);
353 for (unsigned i
= 0; i
< num_components
; i
++) {
354 if (mask
& (1 << i
)) {
355 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
356 if (dst
.type() == RegType::sgpr
)
357 src
= bld
.as_uniform(src
);
358 vec
->operands
[i
] = Operand(src
);
360 vec
->operands
[i
] = Operand(0u);
362 elems
[i
] = vec
->operands
[i
].getTemp();
364 ctx
->block
->instructions
.emplace_back(std::move(vec
));
365 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
368 /* adjust misaligned small bit size loads */
369 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
371 Builder
bld(ctx
->program
, ctx
->block
);
373 Temp select
= Temp();
374 if (offset
.isConstant()) {
375 assert(offset
.constantValue() && offset
.constantValue() < 4);
376 shift
= Operand(offset
.constantValue() * 8);
378 /* bit_offset = 8 * (offset & 0x3) */
379 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
380 select
= bld
.tmp(s1
);
381 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
384 if (vec
.size() == 1) {
385 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
386 } else if (vec
.size() == 2) {
387 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
388 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
390 emit_split_vector(ctx
, dst
, 2);
392 emit_extract_vector(ctx
, tmp
, 0, dst
);
393 } else if (vec
.size() == 4) {
394 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
395 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
396 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
397 if (select
!= Temp())
398 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), select
);
399 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
400 Temp mid
= bld
.tmp(s1
);
401 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
402 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
403 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
404 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
405 emit_split_vector(ctx
, dst
, 2);
409 /* this function trims subdword vectors:
410 * if dst is vgpr - split the src and create a shrunk version according to the mask.
411 * if dst is sgpr - split the src, but move the original to sgpr. */
412 void trim_subdword_vector(isel_context
*ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
414 assert(vec_src
.type() == RegType::vgpr
);
415 emit_split_vector(ctx
, vec_src
, num_components
);
417 Builder
bld(ctx
->program
, ctx
->block
);
418 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
419 unsigned component_size
= vec_src
.bytes() / num_components
;
420 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
423 for (unsigned i
= 0; i
< num_components
; i
++) {
425 elems
[k
++] = emit_extract_vector(ctx
, vec_src
, i
, rc
);
428 if (dst
.type() == RegType::vgpr
) {
429 assert(dst
.bytes() == k
* component_size
);
430 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, k
, 1)};
431 for (unsigned i
= 0; i
< k
; i
++)
432 vec
->operands
[i
] = Operand(elems
[i
]);
433 vec
->definitions
[0] = Definition(dst
);
434 bld
.insert(std::move(vec
));
436 // TODO: alignbyte if mask doesn't start with 1?
438 assert(dst
.size() == vec_src
.size());
439 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
441 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
444 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
446 Builder
bld(ctx
->program
, ctx
->block
);
448 dst
= bld
.tmp(bld
.lm
);
450 assert(val
.regClass() == s1
);
451 assert(dst
.regClass() == bld
.lm
);
453 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
456 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
458 Builder
bld(ctx
->program
, ctx
->block
);
462 assert(val
.regClass() == bld
.lm
);
463 assert(dst
.regClass() == s1
);
465 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
466 Temp tmp
= bld
.tmp(s1
);
467 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
468 return emit_wqm(ctx
, tmp
, dst
);
471 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
473 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
474 return get_ssa_temp(ctx
, src
.src
.ssa
);
476 if (src
.src
.ssa
->num_components
== size
) {
477 bool identity_swizzle
= true;
478 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
479 if (src
.swizzle
[i
] != i
)
480 identity_swizzle
= false;
482 if (identity_swizzle
)
483 return get_ssa_temp(ctx
, src
.src
.ssa
);
486 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
487 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
488 assert(elem_size
> 0);
489 assert(vec
.bytes() % elem_size
== 0);
491 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
492 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
494 unsigned swizzle
= src
.swizzle
[0];
495 if (vec
.size() > 1) {
496 assert(src
.src
.ssa
->bit_size
== 16);
497 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
498 swizzle
= swizzle
& 1;
503 Temp dst
{ctx
->program
->allocateId(), s1
};
504 aco_ptr
<SOP2_instruction
> bfe
{create_instruction
<SOP2_instruction
>(aco_opcode::s_bfe_u32
, Format::SOP2
, 2, 1)};
505 bfe
->operands
[0] = Operand(vec
);
506 bfe
->operands
[1] = Operand(uint32_t((src
.src
.ssa
->bit_size
<< 16) | (src
.src
.ssa
->bit_size
* swizzle
)));
507 bfe
->definitions
[0] = Definition(dst
);
508 ctx
->block
->instructions
.emplace_back(std::move(bfe
));
512 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
514 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
517 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
518 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
519 for (unsigned i
= 0; i
< size
; ++i
) {
520 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
521 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
523 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
524 vec_instr
->definitions
[0] = Definition(dst
);
525 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
526 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
531 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
535 Builder
bld(ctx
->program
, ctx
->block
);
536 if (ptr
.type() == RegType::vgpr
)
537 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
538 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
539 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
542 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
544 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
545 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
546 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
547 sop2
->definitions
[0] = Definition(dst
);
549 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
550 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
553 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
554 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
556 Builder
bld(ctx
->program
, ctx
->block
);
557 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
558 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
559 if (src1
.type() == RegType::sgpr
) {
560 if (commutative
&& src0
.type() == RegType::vgpr
) {
565 src1
= as_vgpr(ctx
, src1
);
569 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
570 assert(dst
.size() == 1);
571 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
572 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
574 bld
.vop2(op
, Definition(dst
), src0
, src1
);
578 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
579 bool flush_denorms
= false)
581 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
582 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
583 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
585 /* ensure that the instruction has at most 1 sgpr operand
586 * The optimizer will inline constants for us */
587 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
588 src0
= as_vgpr(ctx
, src0
);
589 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
590 src1
= as_vgpr(ctx
, src1
);
591 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
592 src2
= as_vgpr(ctx
, src2
);
594 Builder
bld(ctx
->program
, ctx
->block
);
595 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
596 assert(dst
.size() == 1);
597 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
598 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
600 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
604 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
606 Builder
bld(ctx
->program
, ctx
->block
);
607 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
610 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
613 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
614 assert(src0
.size() == src1
.size());
616 aco_ptr
<Instruction
> vopc
;
617 if (src1
.type() == RegType::sgpr
) {
618 if (src0
.type() == RegType::vgpr
) {
619 /* to swap the operands, we might also have to change the opcode */
621 case aco_opcode::v_cmp_lt_f16
:
622 op
= aco_opcode::v_cmp_gt_f16
;
624 case aco_opcode::v_cmp_ge_f16
:
625 op
= aco_opcode::v_cmp_le_f16
;
627 case aco_opcode::v_cmp_lt_i16
:
628 op
= aco_opcode::v_cmp_gt_i16
;
630 case aco_opcode::v_cmp_ge_i16
:
631 op
= aco_opcode::v_cmp_le_i16
;
633 case aco_opcode::v_cmp_lt_u16
:
634 op
= aco_opcode::v_cmp_gt_u16
;
636 case aco_opcode::v_cmp_ge_u16
:
637 op
= aco_opcode::v_cmp_le_u16
;
639 case aco_opcode::v_cmp_lt_f32
:
640 op
= aco_opcode::v_cmp_gt_f32
;
642 case aco_opcode::v_cmp_ge_f32
:
643 op
= aco_opcode::v_cmp_le_f32
;
645 case aco_opcode::v_cmp_lt_i32
:
646 op
= aco_opcode::v_cmp_gt_i32
;
648 case aco_opcode::v_cmp_ge_i32
:
649 op
= aco_opcode::v_cmp_le_i32
;
651 case aco_opcode::v_cmp_lt_u32
:
652 op
= aco_opcode::v_cmp_gt_u32
;
654 case aco_opcode::v_cmp_ge_u32
:
655 op
= aco_opcode::v_cmp_le_u32
;
657 case aco_opcode::v_cmp_lt_f64
:
658 op
= aco_opcode::v_cmp_gt_f64
;
660 case aco_opcode::v_cmp_ge_f64
:
661 op
= aco_opcode::v_cmp_le_f64
;
663 case aco_opcode::v_cmp_lt_i64
:
664 op
= aco_opcode::v_cmp_gt_i64
;
666 case aco_opcode::v_cmp_ge_i64
:
667 op
= aco_opcode::v_cmp_le_i64
;
669 case aco_opcode::v_cmp_lt_u64
:
670 op
= aco_opcode::v_cmp_gt_u64
;
672 case aco_opcode::v_cmp_ge_u64
:
673 op
= aco_opcode::v_cmp_le_u64
;
675 default: /* eq and ne are commutative */
682 src1
= as_vgpr(ctx
, src1
);
686 Builder
bld(ctx
->program
, ctx
->block
);
687 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
690 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
692 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
693 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
694 Builder
bld(ctx
->program
, ctx
->block
);
696 assert(dst
.regClass() == bld
.lm
);
697 assert(src0
.type() == RegType::sgpr
);
698 assert(src1
.type() == RegType::sgpr
);
699 assert(src0
.regClass() == src1
.regClass());
701 /* Emit the SALU comparison instruction */
702 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
703 /* Turn the result into a per-lane bool */
704 bool_to_vector_condition(ctx
, cmp
, dst
);
707 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
708 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
710 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
711 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
712 bool divergent_vals
= ctx
->divergent_vals
[instr
->dest
.dest
.ssa
.index
];
713 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
715 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
716 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
717 aco_opcode op
= use_valu
? v_op
: s_op
;
718 assert(op
!= aco_opcode::num_opcodes
);
719 assert(dst
.regClass() == ctx
->program
->lane_mask
);
722 emit_vopc_instruction(ctx
, instr
, op
, dst
);
724 emit_sopc_instruction(ctx
, instr
, op
, dst
);
727 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
729 Builder
bld(ctx
->program
, ctx
->block
);
730 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
731 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
733 assert(dst
.regClass() == bld
.lm
);
734 assert(src0
.regClass() == bld
.lm
);
735 assert(src1
.regClass() == bld
.lm
);
737 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
740 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
742 Builder
bld(ctx
->program
, ctx
->block
);
743 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
744 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
745 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
747 assert(cond
.regClass() == bld
.lm
);
749 if (dst
.type() == RegType::vgpr
) {
750 aco_ptr
<Instruction
> bcsel
;
751 if (dst
.regClass() == v2b
) {
752 then
= as_vgpr(ctx
, then
);
753 els
= as_vgpr(ctx
, els
);
755 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), els
, then
, cond
);
756 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
757 } else if (dst
.regClass() == v1
) {
758 then
= as_vgpr(ctx
, then
);
759 els
= as_vgpr(ctx
, els
);
761 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
762 } else if (dst
.regClass() == v2
) {
763 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
764 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
765 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
766 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
768 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
769 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
771 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
773 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
774 nir_print_instr(&instr
->instr
, stderr
);
775 fprintf(stderr
, "\n");
780 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
781 assert(dst
.regClass() == bld
.lm
);
782 assert(then
.regClass() == bld
.lm
);
783 assert(els
.regClass() == bld
.lm
);
786 if (!ctx
->divergent_vals
[instr
->src
[0].src
.ssa
->index
]) { /* uniform condition and values in sgpr */
787 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
788 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
789 assert(dst
.size() == then
.size());
790 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
791 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
793 fprintf(stderr
, "Unimplemented uniform bcsel bit size: ");
794 nir_print_instr(&instr
->instr
, stderr
);
795 fprintf(stderr
, "\n");
800 /* divergent boolean bcsel
801 * this implements bcsel on bools: dst = s0 ? s1 : s2
802 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
803 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
805 if (cond
.id() != then
.id())
806 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
808 if (cond
.id() == els
.id())
809 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
811 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
812 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
815 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
816 aco_opcode op
, uint32_t undo
)
818 /* multiply by 16777216 to handle denormals */
819 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
820 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
821 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
822 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
823 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
825 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
827 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
830 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
832 if (ctx
->block
->fp_mode
.denorm32
== 0) {
833 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
837 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
840 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
842 if (ctx
->block
->fp_mode
.denorm32
== 0) {
843 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
847 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
850 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
852 if (ctx
->block
->fp_mode
.denorm32
== 0) {
853 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
857 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
860 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
862 if (ctx
->block
->fp_mode
.denorm32
== 0) {
863 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
867 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
870 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
872 if (ctx
->options
->chip_class
>= GFX7
)
873 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
875 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
876 /* TODO: create more efficient code! */
877 if (val
.type() == RegType::sgpr
)
878 val
= as_vgpr(ctx
, val
);
880 /* Split the input value. */
881 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
882 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
884 /* Extract the exponent and compute the unbiased value. */
885 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, bld
.def(v1
), val
);
887 /* Extract the fractional part. */
888 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
889 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
891 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
892 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
894 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
895 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
896 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
897 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
898 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
900 /* Get the sign bit. */
901 Temp sign
= bld
.vop2(aco_opcode::v_ashr_i32
, bld
.def(v1
), Operand(31u), val_hi
);
903 /* Decide the operation to apply depending on the unbiased exponent. */
904 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
905 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
906 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
907 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
908 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
909 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
911 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
914 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
916 if (ctx
->options
->chip_class
>= GFX7
)
917 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
919 /* GFX6 doesn't support V_FLOOR_F64, lower it. */
920 Temp src0
= as_vgpr(ctx
, val
);
922 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
923 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
925 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
926 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
927 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
929 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
930 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
931 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
934 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
935 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
937 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
939 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
940 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
942 return add
->definitions
[0].getTemp();
945 Temp
convert_int(Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp()) {
947 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
948 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
950 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
953 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
954 return bld
.copy(Definition(dst
), src
);
955 else if (dst
.bytes() < src
.bytes())
956 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
960 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
963 } else if (src
.regClass() == s1
) {
965 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
967 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
969 assert(src_bits
!= 8 || src
.regClass() == v1b
);
970 assert(src_bits
!= 16 || src
.regClass() == v2b
);
971 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
972 sdwa
->operands
[0] = Operand(src
);
973 sdwa
->definitions
[0] = Definition(tmp
);
975 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
977 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
978 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
979 bld
.insert(std::move(sdwa
));
982 if (dst_bits
== 64) {
983 if (is_signed
&& dst
.regClass() == s2
) {
984 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
985 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
986 } else if (is_signed
&& dst
.regClass() == v2
) {
987 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
988 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
990 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
997 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
999 if (!instr
->dest
.dest
.is_ssa
) {
1000 fprintf(stderr
, "nir alu dst not in ssa: ");
1001 nir_print_instr(&instr
->instr
, stderr
);
1002 fprintf(stderr
, "\n");
1005 Builder
bld(ctx
->program
, ctx
->block
);
1006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1011 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1012 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1013 for (unsigned i
= 0; i
< num
; ++i
)
1014 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1016 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1017 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1018 for (unsigned i
= 0; i
< num
; ++i
)
1019 vec
->operands
[i
] = Operand
{elems
[i
]};
1020 vec
->definitions
[0] = Definition(dst
);
1021 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1022 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1024 // TODO: that is a bit suboptimal..
1025 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1026 for (unsigned i
= 0; i
< num
- 1; ++i
)
1027 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1028 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1029 for (unsigned i
= 0; i
< num
; ++i
) {
1030 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1031 if (bit
% 32 == 0) {
1032 elems
[bit
/ 32] = elems
[i
];
1034 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1035 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1036 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1039 if (dst
.size() == 1)
1040 bld
.copy(Definition(dst
), elems
[0]);
1042 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1047 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1048 aco_ptr
<Instruction
> mov
;
1049 if (dst
.type() == RegType::sgpr
) {
1050 if (src
.type() == RegType::vgpr
)
1051 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1052 else if (src
.regClass() == s1
)
1053 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1054 else if (src
.regClass() == s2
)
1055 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1057 unreachable("wrong src register class for nir_op_imov");
1058 } else if (dst
.regClass() == v1
) {
1059 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1060 } else if (dst
.regClass() == v2
) {
1061 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1063 nir_print_instr(&instr
->instr
, stderr
);
1064 unreachable("Should have been lowered to scalar.");
1069 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1070 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1071 assert(src
.regClass() == bld
.lm
);
1072 assert(dst
.regClass() == bld
.lm
);
1073 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1074 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1075 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1076 } else if (dst
.regClass() == v1
) {
1077 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1078 } else if (dst
.type() == RegType::sgpr
) {
1079 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1080 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1082 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1083 nir_print_instr(&instr
->instr
, stderr
);
1084 fprintf(stderr
, "\n");
1089 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1090 if (dst
.regClass() == v1
) {
1091 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1092 } else if (dst
.regClass() == s1
) {
1093 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1094 } else if (dst
.size() == 2) {
1095 Temp src0
= bld
.tmp(dst
.type(), 1);
1096 Temp src1
= bld
.tmp(dst
.type(), 1);
1097 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1099 if (dst
.regClass() == s2
) {
1100 Temp carry
= bld
.tmp(s1
);
1101 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1102 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1103 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1105 Temp lower
= bld
.tmp(v1
);
1106 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1107 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1108 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1111 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1112 nir_print_instr(&instr
->instr
, stderr
);
1113 fprintf(stderr
, "\n");
1118 if (dst
.regClass() == s1
) {
1119 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1120 } else if (dst
.regClass() == v1
) {
1121 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1122 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1124 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1125 nir_print_instr(&instr
->instr
, stderr
);
1126 fprintf(stderr
, "\n");
1130 case nir_op_isign
: {
1131 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1132 if (dst
.regClass() == s1
) {
1133 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1134 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1135 } else if (dst
.regClass() == s2
) {
1136 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1138 if (ctx
->program
->chip_class
>= GFX8
)
1139 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1141 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1142 /* SCC gets zero-extended to 64 bit */
1143 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1144 } else if (dst
.regClass() == v1
) {
1145 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1146 } else if (dst
.regClass() == v2
) {
1147 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1148 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1149 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1150 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1151 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1152 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1154 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1155 nir_print_instr(&instr
->instr
, stderr
);
1156 fprintf(stderr
, "\n");
1161 if (dst
.regClass() == v1
) {
1162 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1163 } else if (dst
.regClass() == s1
) {
1164 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1166 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1167 nir_print_instr(&instr
->instr
, stderr
);
1168 fprintf(stderr
, "\n");
1173 if (dst
.regClass() == v1
) {
1174 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1175 } else if (dst
.regClass() == s1
) {
1176 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1178 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1179 nir_print_instr(&instr
->instr
, stderr
);
1180 fprintf(stderr
, "\n");
1185 if (dst
.regClass() == v1
) {
1186 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1187 } else if (dst
.regClass() == s1
) {
1188 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1190 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1191 nir_print_instr(&instr
->instr
, stderr
);
1192 fprintf(stderr
, "\n");
1197 if (dst
.regClass() == v1
) {
1198 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1199 } else if (dst
.regClass() == s1
) {
1200 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1202 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1203 nir_print_instr(&instr
->instr
, stderr
);
1204 fprintf(stderr
, "\n");
1209 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1210 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1211 } else if (dst
.regClass() == v1
) {
1212 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1213 } else if (dst
.regClass() == s1
) {
1214 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1215 } else if (dst
.regClass() == s2
) {
1216 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1218 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1219 nir_print_instr(&instr
->instr
, stderr
);
1220 fprintf(stderr
, "\n");
1225 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1226 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1227 } else if (dst
.regClass() == v1
) {
1228 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1229 } else if (dst
.regClass() == s1
) {
1230 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1231 } else if (dst
.regClass() == s2
) {
1232 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1234 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1235 nir_print_instr(&instr
->instr
, stderr
);
1236 fprintf(stderr
, "\n");
1241 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1242 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1243 } else if (dst
.regClass() == v1
) {
1244 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1245 } else if (dst
.regClass() == s1
) {
1246 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1247 } else if (dst
.regClass() == s2
) {
1248 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1250 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1251 nir_print_instr(&instr
->instr
, stderr
);
1252 fprintf(stderr
, "\n");
1257 if (dst
.regClass() == v1
) {
1258 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1259 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1260 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1261 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1262 } else if (dst
.regClass() == v2
) {
1263 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1264 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1265 } else if (dst
.regClass() == s2
) {
1266 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1267 } else if (dst
.regClass() == s1
) {
1268 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1270 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1271 nir_print_instr(&instr
->instr
, stderr
);
1272 fprintf(stderr
, "\n");
1277 if (dst
.regClass() == v1
) {
1278 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1279 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1280 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1281 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1282 } else if (dst
.regClass() == v2
) {
1283 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1284 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1285 } else if (dst
.regClass() == s1
) {
1286 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1287 } else if (dst
.regClass() == s2
) {
1288 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1290 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1291 nir_print_instr(&instr
->instr
, stderr
);
1292 fprintf(stderr
, "\n");
1297 if (dst
.regClass() == v1
) {
1298 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1299 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1300 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1301 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1302 } else if (dst
.regClass() == v2
) {
1303 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1304 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1305 } else if (dst
.regClass() == s1
) {
1306 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1307 } else if (dst
.regClass() == s2
) {
1308 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1310 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1311 nir_print_instr(&instr
->instr
, stderr
);
1312 fprintf(stderr
, "\n");
1316 case nir_op_find_lsb
: {
1317 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1318 if (src
.regClass() == s1
) {
1319 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1320 } else if (src
.regClass() == v1
) {
1321 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1322 } else if (src
.regClass() == s2
) {
1323 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1325 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1326 nir_print_instr(&instr
->instr
, stderr
);
1327 fprintf(stderr
, "\n");
1331 case nir_op_ufind_msb
:
1332 case nir_op_ifind_msb
: {
1333 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1334 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1335 aco_opcode op
= src
.regClass() == s2
?
1336 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1337 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1338 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1340 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1341 Operand(src
.size() * 32u - 1u), msb_rev
);
1342 Temp msb
= sub
.def(0).getTemp();
1343 Temp carry
= sub
.def(1).getTemp();
1345 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1346 } else if (src
.regClass() == v1
) {
1347 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1348 Temp msb_rev
= bld
.tmp(v1
);
1349 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1350 Temp msb
= bld
.tmp(v1
);
1351 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1352 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1354 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1355 nir_print_instr(&instr
->instr
, stderr
);
1356 fprintf(stderr
, "\n");
1360 case nir_op_bitfield_reverse
: {
1361 if (dst
.regClass() == s1
) {
1362 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1363 } else if (dst
.regClass() == v1
) {
1364 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1366 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1367 nir_print_instr(&instr
->instr
, stderr
);
1368 fprintf(stderr
, "\n");
1373 if (dst
.regClass() == s1
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1378 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1379 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1380 if (dst
.regClass() == v1
) {
1381 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1385 assert(src0
.size() == 2 && src1
.size() == 2);
1386 Temp src00
= bld
.tmp(src0
.type(), 1);
1387 Temp src01
= bld
.tmp(dst
.type(), 1);
1388 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1389 Temp src10
= bld
.tmp(src1
.type(), 1);
1390 Temp src11
= bld
.tmp(dst
.type(), 1);
1391 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1393 if (dst
.regClass() == s2
) {
1394 Temp carry
= bld
.tmp(s1
);
1395 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1396 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1397 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1398 } else if (dst
.regClass() == v2
) {
1399 Temp dst0
= bld
.tmp(v1
);
1400 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1401 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1402 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1404 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1405 nir_print_instr(&instr
->instr
, stderr
);
1406 fprintf(stderr
, "\n");
1410 case nir_op_uadd_sat
: {
1411 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1412 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1413 if (dst
.regClass() == s1
) {
1414 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1415 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1418 } else if (dst
.regClass() == v1
) {
1419 if (ctx
->options
->chip_class
>= GFX9
) {
1420 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1421 add
->operands
[0] = Operand(src0
);
1422 add
->operands
[1] = Operand(src1
);
1423 add
->definitions
[0] = Definition(dst
);
1425 ctx
->block
->instructions
.emplace_back(std::move(add
));
1427 if (src1
.regClass() != v1
)
1428 std::swap(src0
, src1
);
1429 assert(src1
.regClass() == v1
);
1430 Temp tmp
= bld
.tmp(v1
);
1431 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1432 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1435 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1436 nir_print_instr(&instr
->instr
, stderr
);
1437 fprintf(stderr
, "\n");
1441 case nir_op_uadd_carry
: {
1442 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1443 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1444 if (dst
.regClass() == s1
) {
1445 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1448 if (dst
.regClass() == v1
) {
1449 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1450 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1454 Temp src00
= bld
.tmp(src0
.type(), 1);
1455 Temp src01
= bld
.tmp(dst
.type(), 1);
1456 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1457 Temp src10
= bld
.tmp(src1
.type(), 1);
1458 Temp src11
= bld
.tmp(dst
.type(), 1);
1459 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1460 if (dst
.regClass() == s2
) {
1461 Temp carry
= bld
.tmp(s1
);
1462 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1463 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1464 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1465 } else if (dst
.regClass() == v2
) {
1466 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1467 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1468 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1469 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1471 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1472 nir_print_instr(&instr
->instr
, stderr
);
1473 fprintf(stderr
, "\n");
1478 if (dst
.regClass() == s1
) {
1479 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1483 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1484 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1485 if (dst
.regClass() == v1
) {
1486 bld
.vsub32(Definition(dst
), src0
, src1
);
1490 Temp src00
= bld
.tmp(src0
.type(), 1);
1491 Temp src01
= bld
.tmp(dst
.type(), 1);
1492 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1493 Temp src10
= bld
.tmp(src1
.type(), 1);
1494 Temp src11
= bld
.tmp(dst
.type(), 1);
1495 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1496 if (dst
.regClass() == s2
) {
1497 Temp carry
= bld
.tmp(s1
);
1498 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1499 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1500 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1501 } else if (dst
.regClass() == v2
) {
1502 Temp lower
= bld
.tmp(v1
);
1503 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1504 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1505 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1507 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1508 nir_print_instr(&instr
->instr
, stderr
);
1509 fprintf(stderr
, "\n");
1513 case nir_op_usub_borrow
: {
1514 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1515 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1516 if (dst
.regClass() == s1
) {
1517 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1519 } else if (dst
.regClass() == v1
) {
1520 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1521 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1525 Temp src00
= bld
.tmp(src0
.type(), 1);
1526 Temp src01
= bld
.tmp(dst
.type(), 1);
1527 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1528 Temp src10
= bld
.tmp(src1
.type(), 1);
1529 Temp src11
= bld
.tmp(dst
.type(), 1);
1530 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1531 if (dst
.regClass() == s2
) {
1532 Temp borrow
= bld
.tmp(s1
);
1533 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1534 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1535 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1536 } else if (dst
.regClass() == v2
) {
1537 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1538 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1539 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1540 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1542 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1543 nir_print_instr(&instr
->instr
, stderr
);
1544 fprintf(stderr
, "\n");
1549 if (dst
.regClass() == v1
) {
1550 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1551 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1552 } else if (dst
.regClass() == s1
) {
1553 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1555 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1556 nir_print_instr(&instr
->instr
, stderr
);
1557 fprintf(stderr
, "\n");
1561 case nir_op_umul_high
: {
1562 if (dst
.regClass() == v1
) {
1563 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1564 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1565 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1566 } else if (dst
.regClass() == s1
) {
1567 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1568 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1569 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1571 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1572 nir_print_instr(&instr
->instr
, stderr
);
1573 fprintf(stderr
, "\n");
1577 case nir_op_imul_high
: {
1578 if (dst
.regClass() == v1
) {
1579 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1580 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1581 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1582 } else if (dst
.regClass() == s1
) {
1583 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1584 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1585 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1587 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1588 nir_print_instr(&instr
->instr
, stderr
);
1589 fprintf(stderr
, "\n");
1594 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1595 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1596 if (dst
.regClass() == v2b
) {
1597 Temp tmp
= bld
.tmp(v1
);
1598 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, tmp
, true);
1599 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1600 } else if (dst
.regClass() == v1
) {
1601 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1602 } else if (dst
.regClass() == v2
) {
1603 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1605 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1606 nir_print_instr(&instr
->instr
, stderr
);
1607 fprintf(stderr
, "\n");
1612 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1613 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1614 if (dst
.regClass() == v2b
) {
1615 Temp tmp
= bld
.tmp(v1
);
1616 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, tmp
, true);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1618 } else if (dst
.regClass() == v1
) {
1619 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1620 } else if (dst
.regClass() == v2
) {
1621 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1623 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1624 nir_print_instr(&instr
->instr
, stderr
);
1625 fprintf(stderr
, "\n");
1630 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1631 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1632 if (dst
.regClass() == v2b
) {
1633 Temp tmp
= bld
.tmp(v1
);
1634 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1635 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, tmp
, false);
1637 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, tmp
, true);
1638 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1639 } else if (dst
.regClass() == v1
) {
1640 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1641 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1643 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1644 } else if (dst
.regClass() == v2
) {
1645 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1646 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1647 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1650 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1651 nir_print_instr(&instr
->instr
, stderr
);
1652 fprintf(stderr
, "\n");
1657 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1658 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1659 if (dst
.regClass() == v2b
) {
1660 // TODO: check fp_mode.must_flush_denorms16_64
1661 Temp tmp
= bld
.tmp(v1
);
1662 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, tmp
, true);
1663 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1664 } else if (dst
.regClass() == v1
) {
1665 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1666 } else if (dst
.regClass() == v2
) {
1667 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1668 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1669 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1671 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1675 nir_print_instr(&instr
->instr
, stderr
);
1676 fprintf(stderr
, "\n");
1681 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1682 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1683 if (dst
.regClass() == v2b
) {
1684 // TODO: check fp_mode.must_flush_denorms16_64
1685 Temp tmp
= bld
.tmp(v1
);
1686 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, tmp
, true);
1687 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1688 } else if (dst
.regClass() == v1
) {
1689 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1690 } else if (dst
.regClass() == v2
) {
1691 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1692 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1693 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1695 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1698 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1699 nir_print_instr(&instr
->instr
, stderr
);
1700 fprintf(stderr
, "\n");
1704 case nir_op_fmax3
: {
1705 if (dst
.regClass() == v2b
) {
1706 Temp tmp
= bld
.tmp(v1
);
1707 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f16
, tmp
, false);
1708 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1709 } else if (dst
.regClass() == v1
) {
1710 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1712 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1713 nir_print_instr(&instr
->instr
, stderr
);
1714 fprintf(stderr
, "\n");
1718 case nir_op_fmin3
: {
1719 if (dst
.regClass() == v2b
) {
1720 Temp tmp
= bld
.tmp(v1
);
1721 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f16
, tmp
, false);
1722 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1723 } else if (dst
.regClass() == v1
) {
1724 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1726 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1727 nir_print_instr(&instr
->instr
, stderr
);
1728 fprintf(stderr
, "\n");
1732 case nir_op_fmed3
: {
1733 if (dst
.regClass() == v2b
) {
1734 Temp tmp
= bld
.tmp(v1
);
1735 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f16
, tmp
, false);
1736 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1737 } else if (dst
.regClass() == v1
) {
1738 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_f32
, dst
, ctx
->block
->fp_mode
.must_flush_denorms32
);
1740 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1741 nir_print_instr(&instr
->instr
, stderr
);
1742 fprintf(stderr
, "\n");
1746 case nir_op_umax3
: {
1747 if (dst
.size() == 1) {
1748 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_u32
, dst
);
1750 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1751 nir_print_instr(&instr
->instr
, stderr
);
1752 fprintf(stderr
, "\n");
1756 case nir_op_umin3
: {
1757 if (dst
.size() == 1) {
1758 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_u32
, dst
);
1760 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1761 nir_print_instr(&instr
->instr
, stderr
);
1762 fprintf(stderr
, "\n");
1766 case nir_op_umed3
: {
1767 if (dst
.size() == 1) {
1768 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_u32
, dst
);
1770 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1771 nir_print_instr(&instr
->instr
, stderr
);
1772 fprintf(stderr
, "\n");
1776 case nir_op_imax3
: {
1777 if (dst
.size() == 1) {
1778 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_max3_i32
, dst
);
1780 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1781 nir_print_instr(&instr
->instr
, stderr
);
1782 fprintf(stderr
, "\n");
1786 case nir_op_imin3
: {
1787 if (dst
.size() == 1) {
1788 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_min3_i32
, dst
);
1790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1791 nir_print_instr(&instr
->instr
, stderr
);
1792 fprintf(stderr
, "\n");
1796 case nir_op_imed3
: {
1797 if (dst
.size() == 1) {
1798 emit_vop3a_instruction(ctx
, instr
, aco_opcode::v_med3_i32
, dst
);
1800 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1801 nir_print_instr(&instr
->instr
, stderr
);
1802 fprintf(stderr
, "\n");
1806 case nir_op_cube_face_coord
: {
1807 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1808 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1809 emit_extract_vector(ctx
, in
, 1, v1
),
1810 emit_extract_vector(ctx
, in
, 2, v1
) };
1811 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1812 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1813 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1814 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1815 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, ma
, Operand(0x3f000000u
/*0.5*/));
1816 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, ma
, Operand(0x3f000000u
/*0.5*/));
1817 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1820 case nir_op_cube_face_index
: {
1821 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1822 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1823 emit_extract_vector(ctx
, in
, 1, v1
),
1824 emit_extract_vector(ctx
, in
, 2, v1
) };
1825 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1828 case nir_op_bcsel
: {
1829 emit_bcsel(ctx
, instr
, dst
);
1833 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1834 if (dst
.regClass() == v2b
) {
1835 Temp tmp
= bld
.vop1(aco_opcode::v_rsq_f16
, bld
.def(v1
), src
);
1836 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1837 } else if (dst
.regClass() == v1
) {
1838 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1839 } else if (dst
.regClass() == v2
) {
1840 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1842 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1843 nir_print_instr(&instr
->instr
, stderr
);
1844 fprintf(stderr
, "\n");
1849 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1850 if (dst
.regClass() == v2b
) {
1851 Temp tmp
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1852 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1853 } else if (dst
.regClass() == v1
) {
1854 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1855 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1856 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1857 } else if (dst
.regClass() == v2
) {
1858 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1859 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1860 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1861 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1862 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1863 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1865 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1866 nir_print_instr(&instr
->instr
, stderr
);
1867 fprintf(stderr
, "\n");
1872 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1873 if (dst
.regClass() == v2b
) {
1874 Temp tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1875 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1876 } else if (dst
.regClass() == v1
) {
1877 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1878 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1879 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1880 } else if (dst
.regClass() == v2
) {
1881 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1882 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1883 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1884 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1885 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1886 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1888 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1889 nir_print_instr(&instr
->instr
, stderr
);
1890 fprintf(stderr
, "\n");
1895 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1896 if (dst
.regClass() == v2b
) {
1897 Temp tmp
= bld
.vop3(aco_opcode::v_med3_f16
, bld
.def(v1
), Operand(0u), Operand(0x3f800000u
), src
);
1898 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1899 } else if (dst
.regClass() == v1
) {
1900 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1901 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1902 // TODO: confirm that this holds under any circumstances
1903 } else if (dst
.regClass() == v2
) {
1904 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1905 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1908 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1909 nir_print_instr(&instr
->instr
, stderr
);
1910 fprintf(stderr
, "\n");
1914 case nir_op_flog2
: {
1915 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1916 if (dst
.regClass() == v2b
) {
1917 Temp tmp
= bld
.vop1(aco_opcode::v_log_f16
, bld
.def(v1
), src
);
1918 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1919 } else if (dst
.regClass() == v1
) {
1920 emit_log2(ctx
, bld
, Definition(dst
), src
);
1922 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1923 nir_print_instr(&instr
->instr
, stderr
);
1924 fprintf(stderr
, "\n");
1929 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1930 if (dst
.regClass() == v2b
) {
1931 Temp tmp
= bld
.vop1(aco_opcode::v_rcp_f16
, bld
.def(v1
), src
);
1932 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1933 } else if (dst
.regClass() == v1
) {
1934 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1935 } else if (dst
.regClass() == v2
) {
1936 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1938 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1939 nir_print_instr(&instr
->instr
, stderr
);
1940 fprintf(stderr
, "\n");
1944 case nir_op_fexp2
: {
1945 if (dst
.regClass() == v2b
) {
1946 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1947 Temp tmp
= bld
.vop1(aco_opcode::v_exp_f16
, bld
.def(v1
), src
);
1948 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1949 } else if (dst
.regClass() == v1
) {
1950 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1952 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1953 nir_print_instr(&instr
->instr
, stderr
);
1954 fprintf(stderr
, "\n");
1958 case nir_op_fsqrt
: {
1959 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1960 if (dst
.regClass() == v2b
) {
1961 Temp tmp
= bld
.vop1(aco_opcode::v_sqrt_f16
, bld
.def(v1
), src
);
1962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1963 } else if (dst
.regClass() == v1
) {
1964 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1965 } else if (dst
.regClass() == v2
) {
1966 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1968 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1969 nir_print_instr(&instr
->instr
, stderr
);
1970 fprintf(stderr
, "\n");
1974 case nir_op_ffract
: {
1975 if (dst
.regClass() == v2b
) {
1976 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1977 Temp tmp
= bld
.vop1(aco_opcode::v_fract_f16
, bld
.def(v1
), src
);
1978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1981 } else if (dst
.regClass() == v2
) {
1982 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1984 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
1985 nir_print_instr(&instr
->instr
, stderr
);
1986 fprintf(stderr
, "\n");
1990 case nir_op_ffloor
: {
1991 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1992 if (dst
.regClass() == v2b
) {
1993 Temp tmp
= bld
.vop1(aco_opcode::v_floor_f16
, bld
.def(v1
), src
);
1994 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
1995 } else if (dst
.regClass() == v1
) {
1996 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1997 } else if (dst
.regClass() == v2
) {
1998 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
2000 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2001 nir_print_instr(&instr
->instr
, stderr
);
2002 fprintf(stderr
, "\n");
2006 case nir_op_fceil
: {
2007 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2008 if (dst
.regClass() == v2b
) {
2009 Temp tmp
= bld
.vop1(aco_opcode::v_ceil_f16
, bld
.def(v1
), src0
);
2010 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2011 } else if (dst
.regClass() == v1
) {
2012 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
2013 } else if (dst
.regClass() == v2
) {
2014 if (ctx
->options
->chip_class
>= GFX7
) {
2015 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
2017 /* GFX6 doesn't support V_CEIL_F64, lower it. */
2018 /* trunc = trunc(src0)
2019 * if (src0 > 0.0 && src0 != trunc)
2022 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
2023 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
2024 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
2025 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
2026 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
2027 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
2028 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
2031 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2032 nir_print_instr(&instr
->instr
, stderr
);
2033 fprintf(stderr
, "\n");
2037 case nir_op_ftrunc
: {
2038 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2039 if (dst
.regClass() == v2b
) {
2040 Temp tmp
= bld
.vop1(aco_opcode::v_trunc_f16
, bld
.def(v1
), src
);
2041 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2042 } else if (dst
.regClass() == v1
) {
2043 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2044 } else if (dst
.regClass() == v2
) {
2045 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2047 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2048 nir_print_instr(&instr
->instr
, stderr
);
2049 fprintf(stderr
, "\n");
2053 case nir_op_fround_even
: {
2054 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2055 if (dst
.regClass() == v2b
) {
2056 Temp tmp
= bld
.vop1(aco_opcode::v_rndne_f16
, bld
.def(v1
), src0
);
2057 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2058 } else if (dst
.regClass() == v1
) {
2059 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2060 } else if (dst
.regClass() == v2
) {
2061 if (ctx
->options
->chip_class
>= GFX7
) {
2062 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2064 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2065 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2066 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2068 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2069 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2070 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2071 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2072 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2073 tmp
= sub
->definitions
[0].getTemp();
2075 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2076 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2077 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2078 Temp cond
= vop3
->definitions
[0].getTemp();
2080 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2082 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2083 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2085 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2088 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2089 nir_print_instr(&instr
->instr
, stderr
);
2090 fprintf(stderr
, "\n");
2096 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2097 aco_ptr
<Instruction
> norm
;
2098 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2099 if (dst
.regClass() == v2b
) {
2100 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2101 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2102 tmp
= bld
.vop1(opcode
, bld
.def(v1
), tmp
);
2103 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2104 } else if (dst
.regClass() == v1
) {
2105 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2107 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2108 if (ctx
->options
->chip_class
< GFX9
)
2109 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2111 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2112 bld
.vop1(opcode
, Definition(dst
), tmp
);
2114 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2115 nir_print_instr(&instr
->instr
, stderr
);
2116 fprintf(stderr
, "\n");
2120 case nir_op_ldexp
: {
2121 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2122 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2123 if (dst
.regClass() == v2b
) {
2124 Temp tmp
= bld
.tmp(v1
);
2125 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, tmp
, false);
2126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2127 } else if (dst
.regClass() == v1
) {
2128 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2129 } else if (dst
.regClass() == v2
) {
2130 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2132 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2133 nir_print_instr(&instr
->instr
, stderr
);
2134 fprintf(stderr
, "\n");
2138 case nir_op_frexp_sig
: {
2139 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2140 if (dst
.regClass() == v2b
) {
2141 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_mant_f16
, bld
.def(v1
), src
);
2142 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2143 } else if (dst
.regClass() == v1
) {
2144 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2145 } else if (dst
.regClass() == v2
) {
2146 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2148 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2149 nir_print_instr(&instr
->instr
, stderr
);
2150 fprintf(stderr
, "\n");
2154 case nir_op_frexp_exp
: {
2155 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2156 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2157 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2158 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2159 convert_int(bld
, tmp
, 8, 32, true, dst
);
2160 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2161 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2162 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2163 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2165 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2166 nir_print_instr(&instr
->instr
, stderr
);
2167 fprintf(stderr
, "\n");
2171 case nir_op_fsign
: {
2172 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2173 if (dst
.regClass() == v2b
) {
2174 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2175 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2176 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2177 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2178 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2179 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), minus_one
, src
, cond
);
2180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2181 } else if (dst
.regClass() == v1
) {
2182 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2183 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2184 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2185 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2186 } else if (dst
.regClass() == v2
) {
2187 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2188 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2189 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2191 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2192 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2193 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2195 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2197 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2198 nir_print_instr(&instr
->instr
, stderr
);
2199 fprintf(stderr
, "\n");
2204 case nir_op_f2f16_rtne
: {
2205 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2206 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2207 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2208 src
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2209 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2212 case nir_op_f2f16_rtz
: {
2213 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2214 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2215 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2216 src
= bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, bld
.def(v1
), src
, Operand(0u));
2217 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), src
);
2220 case nir_op_f2f32
: {
2221 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2222 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2223 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2224 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2226 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2227 nir_print_instr(&instr
->instr
, stderr
);
2228 fprintf(stderr
, "\n");
2232 case nir_op_f2f64
: {
2233 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2234 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2235 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2236 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2239 case nir_op_i2f16
: {
2240 assert(dst
.regClass() == v2b
);
2241 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2243 src
= convert_int(bld
, src
, 8, 16, true);
2244 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_i16
, bld
.def(v1
), src
);
2245 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2248 case nir_op_i2f32
: {
2249 assert(dst
.size() == 1);
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2252 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2253 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2256 case nir_op_i2f64
: {
2257 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2258 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2259 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2260 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2261 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2262 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2263 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2264 RegClass rc
= RegClass(src
.type(), 1);
2265 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2266 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2267 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2268 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2269 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2270 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2273 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2274 nir_print_instr(&instr
->instr
, stderr
);
2275 fprintf(stderr
, "\n");
2279 case nir_op_u2f16
: {
2280 assert(dst
.regClass() == v2b
);
2281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2282 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2283 src
= convert_int(bld
, src
, 8, 16, false);
2284 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f16_u16
, bld
.def(v1
), src
);
2285 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2288 case nir_op_u2f32
: {
2289 assert(dst
.size() == 1);
2290 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2291 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2292 //TODO: we should use v_cvt_f32_ubyte1/v_cvt_f32_ubyte2/etc depending on the register assignment
2293 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2295 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2296 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2297 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2301 case nir_op_u2f64
: {
2302 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2303 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2304 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2305 src
= convert_int(bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2306 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2307 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 RegClass rc
= RegClass(src
.type(), 1);
2310 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2311 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2312 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2313 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2314 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2315 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2317 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2318 nir_print_instr(&instr
->instr
, stderr
);
2319 fprintf(stderr
, "\n");
2324 case nir_op_f2i16
: {
2325 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2326 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2327 src
= bld
.vop1(aco_opcode::v_cvt_i16_f16
, bld
.def(v1
), src
);
2328 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2329 src
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
);
2331 src
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
);
2333 if (dst
.type() == RegType::vgpr
)
2334 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2336 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2340 case nir_op_f2u16
: {
2341 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2342 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2343 src
= bld
.vop1(aco_opcode::v_cvt_u16_f16
, bld
.def(v1
), src
);
2344 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2345 src
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
);
2347 src
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
);
2349 if (dst
.type() == RegType::vgpr
)
2350 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
2352 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
2355 case nir_op_f2i32
: {
2356 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2357 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2358 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2359 if (dst
.type() == RegType::vgpr
) {
2360 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2362 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2363 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2365 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2366 if (dst
.type() == RegType::vgpr
)
2367 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), src
);
2369 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2370 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), src
));
2372 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2373 if (dst
.type() == RegType::vgpr
)
2374 bld
.vop1(aco_opcode::v_cvt_i32_f64
, Definition(dst
), src
);
2376 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2377 bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), src
));
2380 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2381 nir_print_instr(&instr
->instr
, stderr
);
2382 fprintf(stderr
, "\n");
2386 case nir_op_f2u32
: {
2387 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2388 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2389 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2390 if (dst
.type() == RegType::vgpr
) {
2391 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2393 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2394 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2396 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2397 if (dst
.type() == RegType::vgpr
)
2398 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), src
);
2400 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2401 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), src
));
2403 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2404 if (dst
.type() == RegType::vgpr
)
2405 bld
.vop1(aco_opcode::v_cvt_u32_f64
, Definition(dst
), src
);
2407 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2408 bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), src
));
2411 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2412 nir_print_instr(&instr
->instr
, stderr
);
2413 fprintf(stderr
, "\n");
2417 case nir_op_f2i64
: {
2418 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2419 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2420 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2422 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2423 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2424 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2425 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2426 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2427 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2428 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2429 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2430 Temp new_exponent
= bld
.tmp(v1
);
2431 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2432 if (ctx
->program
->chip_class
>= GFX8
)
2433 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2435 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2436 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2437 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2438 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2439 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2440 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2441 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2442 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2443 Temp new_lower
= bld
.tmp(v1
);
2444 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2445 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2446 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2448 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2449 if (src
.type() == RegType::vgpr
)
2450 src
= bld
.as_uniform(src
);
2451 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2452 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2453 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2454 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2455 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2456 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2457 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2458 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2459 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2460 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2461 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2462 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2463 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2464 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2465 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2466 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2467 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2468 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2469 Temp borrow
= bld
.tmp(s1
);
2470 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2471 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2472 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2474 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2475 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2476 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2477 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2478 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2479 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2480 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2481 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2482 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2483 if (dst
.type() == RegType::sgpr
) {
2484 lower
= bld
.as_uniform(lower
);
2485 upper
= bld
.as_uniform(upper
);
2487 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2490 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2491 nir_print_instr(&instr
->instr
, stderr
);
2492 fprintf(stderr
, "\n");
2496 case nir_op_f2u64
: {
2497 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2498 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2499 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2501 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2502 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2503 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2504 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2505 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2506 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2507 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2508 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2509 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2510 Temp new_exponent
= bld
.tmp(v1
);
2511 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2512 if (ctx
->program
->chip_class
>= GFX8
)
2513 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2515 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2516 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2517 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2518 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2519 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2520 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2521 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2522 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2524 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2525 if (src
.type() == RegType::vgpr
)
2526 src
= bld
.as_uniform(src
);
2527 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2528 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2529 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2530 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2531 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2532 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2533 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2534 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2535 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2536 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2537 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2538 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2539 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2540 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2541 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2542 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2543 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2544 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2546 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2547 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2548 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2549 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2550 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2551 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2552 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2553 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2554 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2555 if (dst
.type() == RegType::sgpr
) {
2556 lower
= bld
.as_uniform(lower
);
2557 upper
= bld
.as_uniform(upper
);
2559 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2562 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2563 nir_print_instr(&instr
->instr
, stderr
);
2564 fprintf(stderr
, "\n");
2568 case nir_op_b2f16
: {
2569 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2570 assert(src
.regClass() == bld
.lm
);
2572 if (dst
.regClass() == s1
) {
2573 src
= bool_to_scalar_condition(ctx
, src
);
2574 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2575 } else if (dst
.regClass() == v2b
) {
2576 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2577 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2578 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
2580 unreachable("Wrong destination register class for nir_op_b2f16.");
2584 case nir_op_b2f32
: {
2585 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2586 assert(src
.regClass() == bld
.lm
);
2588 if (dst
.regClass() == s1
) {
2589 src
= bool_to_scalar_condition(ctx
, src
);
2590 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2591 } else if (dst
.regClass() == v1
) {
2592 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2594 unreachable("Wrong destination register class for nir_op_b2f32.");
2598 case nir_op_b2f64
: {
2599 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2600 assert(src
.regClass() == bld
.lm
);
2602 if (dst
.regClass() == s2
) {
2603 src
= bool_to_scalar_condition(ctx
, src
);
2604 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2605 } else if (dst
.regClass() == v2
) {
2606 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2607 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2608 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2610 unreachable("Wrong destination register class for nir_op_b2f64.");
2617 case nir_op_i2i64
: {
2618 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2619 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2625 case nir_op_u2u64
: {
2626 convert_int(bld
, get_alu_src(ctx
, instr
->src
[0]),
2627 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2631 case nir_op_b2i32
: {
2632 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2633 assert(src
.regClass() == bld
.lm
);
2635 if (dst
.regClass() == s1
) {
2636 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2637 bool_to_scalar_condition(ctx
, src
, dst
);
2638 } else if (dst
.regClass() == v1
) {
2639 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), src
);
2641 unreachable("Invalid register class for b2i32");
2647 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2648 assert(dst
.regClass() == bld
.lm
);
2650 if (src
.type() == RegType::vgpr
) {
2651 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2652 assert(dst
.regClass() == bld
.lm
);
2653 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2654 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2656 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2658 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2659 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2661 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2662 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2664 bool_to_vector_condition(ctx
, tmp
, dst
);
2668 case nir_op_pack_64_2x32_split
: {
2669 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2670 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2672 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2675 case nir_op_unpack_64_2x32_split_x
:
2676 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2678 case nir_op_unpack_64_2x32_split_y
:
2679 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2681 case nir_op_unpack_32_2x16_split_x
:
2682 if (dst
.type() == RegType::vgpr
) {
2683 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2685 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2688 case nir_op_unpack_32_2x16_split_y
:
2689 if (dst
.type() == RegType::vgpr
) {
2690 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2692 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2695 case nir_op_pack_32_2x16_split
: {
2696 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2697 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2698 if (dst
.regClass() == v1
) {
2699 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2700 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2701 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2703 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2704 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2705 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2709 case nir_op_pack_half_2x16
: {
2710 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2712 if (dst
.regClass() == v1
) {
2713 Temp src0
= bld
.tmp(v1
);
2714 Temp src1
= bld
.tmp(v1
);
2715 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2716 if (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)
2717 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2719 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
),
2720 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src0
),
2721 bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src1
));
2723 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2724 nir_print_instr(&instr
->instr
, stderr
);
2725 fprintf(stderr
, "\n");
2729 case nir_op_unpack_half_2x16_split_x
: {
2730 if (dst
.regClass() == v1
) {
2731 Builder
bld(ctx
->program
, ctx
->block
);
2732 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2734 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2735 nir_print_instr(&instr
->instr
, stderr
);
2736 fprintf(stderr
, "\n");
2740 case nir_op_unpack_half_2x16_split_y
: {
2741 if (dst
.regClass() == v1
) {
2742 Builder
bld(ctx
->program
, ctx
->block
);
2743 /* TODO: use SDWA here */
2744 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2745 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2747 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2748 nir_print_instr(&instr
->instr
, stderr
);
2749 fprintf(stderr
, "\n");
2753 case nir_op_fquantize2f16
: {
2754 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2755 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2758 if (ctx
->program
->chip_class
>= GFX8
) {
2759 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2760 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2761 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2763 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2764 * so compare the result and flush to 0 if it's smaller.
2766 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2767 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2768 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2769 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2770 cmp_res
= vop3
->definitions
[0].getTemp();
2773 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2774 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2775 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2777 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2782 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2783 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2785 if (dst
.regClass() == s1
) {
2786 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2787 } else if (dst
.regClass() == v1
) {
2788 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2790 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2791 nir_print_instr(&instr
->instr
, stderr
);
2792 fprintf(stderr
, "\n");
2796 case nir_op_bitfield_select
: {
2797 /* (mask & insert) | (~mask & base) */
2798 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2799 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2800 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2802 /* dst = (insert & bitmask) | (base & ~bitmask) */
2803 if (dst
.regClass() == s1
) {
2804 aco_ptr
<Instruction
> sop2
;
2805 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2806 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2808 if (const_insert
&& const_bitmask
) {
2809 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2811 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2812 lhs
= Operand(insert
);
2816 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2817 if (const_base
&& const_bitmask
) {
2818 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2820 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2821 rhs
= Operand(base
);
2824 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2826 } else if (dst
.regClass() == v1
) {
2827 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2828 base
= as_vgpr(ctx
, base
);
2829 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2830 insert
= as_vgpr(ctx
, insert
);
2832 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2835 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2836 nir_print_instr(&instr
->instr
, stderr
);
2837 fprintf(stderr
, "\n");
2843 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2844 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2845 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2847 if (dst
.type() == RegType::sgpr
) {
2849 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2850 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2851 if (const_offset
&& const_bits
) {
2852 uint32_t const_extract
= (const_bits
->u32
<< 16) | const_offset
->u32
;
2853 extract
= Operand(const_extract
);
2857 width
= Operand(const_bits
->u32
<< 16);
2859 width
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2861 extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, width
);
2865 if (dst
.regClass() == s1
) {
2866 if (instr
->op
== nir_op_ubfe
)
2867 opcode
= aco_opcode::s_bfe_u32
;
2869 opcode
= aco_opcode::s_bfe_i32
;
2870 } else if (dst
.regClass() == s2
) {
2871 if (instr
->op
== nir_op_ubfe
)
2872 opcode
= aco_opcode::s_bfe_u64
;
2874 opcode
= aco_opcode::s_bfe_i64
;
2876 unreachable("Unsupported BFE bit size");
2879 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2883 if (dst
.regClass() == v1
) {
2884 if (instr
->op
== nir_op_ubfe
)
2885 opcode
= aco_opcode::v_bfe_u32
;
2887 opcode
= aco_opcode::v_bfe_i32
;
2889 unreachable("Unsupported BFE bit size");
2892 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2896 case nir_op_bit_count
: {
2897 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2898 if (src
.regClass() == s1
) {
2899 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2900 } else if (src
.regClass() == v1
) {
2901 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2902 } else if (src
.regClass() == v2
) {
2903 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2904 emit_extract_vector(ctx
, src
, 1, v1
),
2905 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2906 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2907 } else if (src
.regClass() == s2
) {
2908 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2910 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
2911 nir_print_instr(&instr
->instr
, stderr
);
2912 fprintf(stderr
, "\n");
2917 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2921 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2925 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2929 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2933 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2937 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2941 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2942 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2944 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2945 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2949 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2950 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2952 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2953 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2957 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2961 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2966 case nir_op_fddx_fine
:
2967 case nir_op_fddy_fine
:
2968 case nir_op_fddx_coarse
:
2969 case nir_op_fddy_coarse
: {
2970 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2971 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2972 if (instr
->op
== nir_op_fddx_fine
) {
2973 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2974 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2975 } else if (instr
->op
== nir_op_fddy_fine
) {
2976 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2977 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2979 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2980 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2981 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2983 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2987 if (ctx
->program
->chip_class
>= GFX8
) {
2988 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2989 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2991 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2992 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2993 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2995 emit_wqm(ctx
, tmp
, dst
, true);
2999 fprintf(stderr
, "Unknown NIR ALU instr: ");
3000 nir_print_instr(&instr
->instr
, stderr
);
3001 fprintf(stderr
, "\n");
3005 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
3007 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
3009 // TODO: we really want to have the resulting type as this would allow for 64bit literals
3010 // which get truncated the lsb if double and msb if int
3011 // for now, we only use s_mov_b64 with 64bit inline constants
3012 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
3013 assert(dst
.type() == RegType::sgpr
);
3015 Builder
bld(ctx
->program
, ctx
->block
);
3017 if (instr
->def
.bit_size
== 1) {
3018 assert(dst
.regClass() == bld
.lm
);
3019 int val
= instr
->value
[0].b
? -1 : 0;
3020 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
3021 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
3022 } else if (instr
->def
.bit_size
== 8) {
3023 /* ensure that the value is correctly represented in the low byte of the register */
3024 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
3025 } else if (instr
->def
.bit_size
== 16) {
3026 /* ensure that the value is correctly represented in the low half of the register */
3027 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
3028 } else if (dst
.size() == 1) {
3029 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
3031 assert(dst
.size() != 1);
3032 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
3033 if (instr
->def
.bit_size
== 64)
3034 for (unsigned i
= 0; i
< dst
.size(); i
++)
3035 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
3037 for (unsigned i
= 0; i
< dst
.size(); i
++)
3038 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
3040 vec
->definitions
[0] = Definition(dst
);
3041 ctx
->block
->instructions
.emplace_back(std::move(vec
));
3045 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
3047 uint32_t new_mask
= 0;
3048 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
3049 if (mask
& (1u << i
))
3050 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
3054 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
3056 Builder
bld(ctx
->program
, ctx
->block
);
3057 if (offset
.isTemp()) {
3058 Temp tmp
[3] = {vec
, vec
, vec
};
3060 if (vec
.size() == 3) {
3061 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
3062 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
3063 } else if (vec
.size() == 2) {
3064 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
3065 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
3067 for (unsigned i
= 0; i
< dst
.size(); i
++)
3068 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
3071 if (dst
.size() == 2)
3072 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
3074 offset
= Operand(0u);
3077 if (vec
.bytes() == dst
.bytes() && offset
.constantValue() == 0)
3078 bld
.copy(Definition(dst
), vec
);
3080 trim_subdword_vector(ctx
, vec
, dst
, vec
.bytes(), ((1 << dst
.bytes()) - 1) << offset
.constantValue());
3083 struct LoadEmitInfo
{
3086 unsigned num_components
;
3087 unsigned component_size
;
3088 Temp resource
= Temp(0, s1
);
3089 unsigned component_stride
= 0;
3090 unsigned const_offset
= 0;
3091 unsigned align_mul
= 0;
3092 unsigned align_offset
= 0;
3095 unsigned swizzle_component_size
= 0;
3096 barrier_interaction barrier
= barrier_none
;
3097 bool can_reorder
= true;
3098 Temp soffset
= Temp(0, s1
);
3101 using LoadCallback
= Temp(*)(
3102 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
3103 unsigned align
, unsigned const_offset
, Temp dst_hint
);
3105 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
3106 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
3108 unsigned load_size
= info
->num_components
* info
->component_size
;
3109 unsigned component_size
= info
->component_size
;
3111 unsigned num_vals
= 0;
3112 Temp vals
[info
->dst
.bytes()];
3114 unsigned const_offset
= info
->const_offset
;
3116 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
3117 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
3119 unsigned bytes_read
= 0;
3120 while (bytes_read
< load_size
) {
3121 unsigned bytes_needed
= load_size
- bytes_read
;
3123 /* add buffer for unaligned loads */
3124 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
3127 if ((bytes_needed
> 2 || !supports_8bit_16bit_loads
) && byte_align_loads
) {
3128 if (info
->component_stride
) {
3129 assert(supports_8bit_16bit_loads
&& "unimplemented");
3133 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3134 bytes_needed
= align(bytes_needed
, 4);
3141 if (info
->swizzle_component_size
)
3142 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3143 if (info
->component_stride
)
3144 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3146 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3148 /* reduce constant offset */
3149 Operand offset
= info
->offset
;
3150 unsigned reduced_const_offset
= const_offset
;
3151 bool remove_const_offset_completely
= need_to_align_offset
;
3152 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3153 unsigned to_add
= const_offset
;
3154 if (remove_const_offset_completely
) {
3155 reduced_const_offset
= 0;
3157 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3158 reduced_const_offset
%= max_const_offset_plus_one
;
3160 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3161 if (offset
.isConstant()) {
3162 offset
= Operand(offset
.constantValue() + to_add
);
3163 } else if (offset_tmp
.regClass() == s1
) {
3164 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3165 offset_tmp
, Operand(to_add
));
3166 } else if (offset_tmp
.regClass() == v1
) {
3167 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3169 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3170 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3171 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3173 if (offset_tmp
.regClass() == s2
) {
3174 Temp carry
= bld
.tmp(s1
);
3175 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3176 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3177 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3179 Temp new_lo
= bld
.tmp(v1
);
3180 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3181 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3182 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3187 /* align offset down if needed */
3188 Operand aligned_offset
= offset
;
3189 if (need_to_align_offset
) {
3190 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3191 if (offset
.isConstant()) {
3192 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3193 } else if (offset_tmp
.regClass() == s1
) {
3194 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3195 } else if (offset_tmp
.regClass() == s2
) {
3196 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3197 } else if (offset_tmp
.regClass() == v1
) {
3198 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3199 } else if (offset_tmp
.regClass() == v2
) {
3200 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3201 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3202 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3203 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3206 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3207 bld
.copy(bld
.def(s1
), aligned_offset
);
3209 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3210 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3211 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3213 /* shift result right if needed */
3215 Operand
align((uint32_t)byte_align
);
3216 if (byte_align
== -1) {
3217 if (offset
.isConstant())
3218 align
= Operand(offset
.constantValue() % 4u);
3219 else if (offset
.size() == 2)
3220 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3225 if (align
.isTemp() || align
.constantValue()) {
3226 assert(val
.bytes() >= load_size
&& "unimplemented");
3227 Temp new_val
= bld
.tmp(RegClass::get(val
.type(), load_size
));
3228 if (val
.type() == RegType::sgpr
)
3229 byte_align_scalar(ctx
, val
, align
, new_val
);
3231 byte_align_vector(ctx
, val
, align
, new_val
);
3236 /* add result to list and advance */
3237 if (info
->component_stride
) {
3238 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3239 const_offset
+= info
->component_stride
;
3240 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3242 const_offset
+= val
.bytes();
3243 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3245 bytes_read
+= val
.bytes();
3246 vals
[num_vals
++] = val
;
3249 /* the callback wrote directly to dst */
3250 if (vals
[0] == info
->dst
) {
3251 assert(num_vals
== 1);
3252 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3256 /* create array of components */
3257 unsigned components_split
= 0;
3258 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3259 bool has_vgprs
= false;
3260 for (unsigned i
= 0; i
< num_vals
;) {
3262 unsigned num_tmps
= 0;
3263 unsigned tmp_size
= 0;
3264 RegType reg_type
= RegType::sgpr
;
3265 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3266 if (vals
[i
].type() == RegType::vgpr
)
3267 reg_type
= RegType::vgpr
;
3268 tmp_size
+= vals
[i
].bytes();
3269 tmp
[num_tmps
++] = vals
[i
++];
3272 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3273 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3274 for (unsigned i
= 0; i
< num_vals
; i
++)
3275 vec
->operands
[i
] = Operand(tmp
[i
]);
3276 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3277 vec
->definitions
[0] = Definition(tmp
[0]);
3278 bld
.insert(std::move(vec
));
3281 if (tmp
[0].bytes() % component_size
) {
3283 assert(i
== num_vals
);
3284 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3285 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3288 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3290 unsigned start
= components_split
;
3292 if (tmp_size
== elem_rc
.bytes()) {
3293 allocated_vec
[components_split
++] = tmp
[0];
3295 assert(tmp_size
% elem_rc
.bytes() == 0);
3296 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3297 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3298 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3299 Temp component
= bld
.tmp(elem_rc
);
3300 allocated_vec
[components_split
++] = component
;
3301 split
->definitions
[i
] = Definition(component
);
3303 split
->operands
[0] = Operand(tmp
[0]);
3304 bld
.insert(std::move(split
));
3307 /* try to p_as_uniform early so we can create more optimizable code and
3308 * also update allocated_vec */
3309 for (unsigned j
= start
; j
< components_split
; j
++) {
3310 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3311 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3312 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3316 /* concatenate components and p_as_uniform() result if needed */
3317 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3318 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3320 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3322 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3323 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3324 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3325 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3327 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3328 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3329 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3330 vec
->definitions
[0] = Definition(tmp
);
3331 bld
.insert(std::move(vec
));
3332 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3334 vec
->definitions
[0] = Definition(info
->dst
);
3335 bld
.insert(std::move(vec
));
3339 Operand
load_lds_size_m0(Builder
& bld
)
3341 /* TODO: m0 does not need to be initialized on GFX9+ */
3342 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3345 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3346 Temp offset
, unsigned bytes_needed
,
3347 unsigned align
, unsigned const_offset
,
3350 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3352 Operand m
= load_lds_size_m0(bld
);
3354 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3355 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3360 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3361 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3363 op
= aco_opcode::ds_read_b128
;
3364 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3367 op
= aco_opcode::ds_read2_b64
;
3368 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3370 op
= aco_opcode::ds_read_b96
;
3371 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3373 op
= aco_opcode::ds_read_b64
;
3374 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3377 op
= aco_opcode::ds_read2_b32
;
3378 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3380 op
= aco_opcode::ds_read_b32
;
3381 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3383 op
= aco_opcode::ds_read_u16
;
3386 op
= aco_opcode::ds_read_u8
;
3389 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3390 if (const_offset
>= max_offset_plus_one
) {
3391 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3392 const_offset
%= max_offset_plus_one
;
3396 const_offset
/= (size
/ 2u);
3398 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3399 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3401 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3403 bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3406 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3411 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3413 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3414 Temp offset
, unsigned bytes_needed
,
3415 unsigned align
, unsigned const_offset
,
3420 if (bytes_needed
<= 4) {
3422 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3423 } else if (bytes_needed
<= 8) {
3425 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3426 } else if (bytes_needed
<= 16) {
3428 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3429 } else if (bytes_needed
<= 32) {
3431 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3434 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3436 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3437 if (info
->resource
.id()) {
3438 load
->operands
[0] = Operand(info
->resource
);
3439 load
->operands
[1] = Operand(offset
);
3441 load
->operands
[0] = Operand(offset
);
3442 load
->operands
[1] = Operand(0u);
3444 RegClass
rc(RegType::sgpr
, size
);
3445 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3446 load
->definitions
[0] = Definition(val
);
3447 load
->glc
= info
->glc
;
3448 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3449 load
->barrier
= info
->barrier
;
3450 load
->can_reorder
= false; // FIXME: currently, it doesn't seem beneficial due to how our scheduler works
3451 bld
.insert(std::move(load
));
3455 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3457 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3458 Temp offset
, unsigned bytes_needed
,
3459 unsigned align_
, unsigned const_offset
,
3462 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3463 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3465 if (info
->soffset
.id()) {
3466 if (soffset
.isTemp())
3467 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3468 soffset
= Operand(info
->soffset
);
3471 unsigned bytes_size
= 0;
3473 if (bytes_needed
== 1) {
3475 op
= aco_opcode::buffer_load_ubyte
;
3476 } else if (bytes_needed
== 2) {
3478 op
= aco_opcode::buffer_load_ushort
;
3479 } else if (bytes_needed
<= 4) {
3481 op
= aco_opcode::buffer_load_dword
;
3482 } else if (bytes_needed
<= 8) {
3484 op
= aco_opcode::buffer_load_dwordx2
;
3485 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3487 op
= aco_opcode::buffer_load_dwordx3
;
3490 op
= aco_opcode::buffer_load_dwordx4
;
3492 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3493 mubuf
->operands
[0] = Operand(info
->resource
);
3494 mubuf
->operands
[1] = vaddr
;
3495 mubuf
->operands
[2] = soffset
;
3496 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3497 mubuf
->glc
= info
->glc
;
3498 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3499 mubuf
->barrier
= info
->barrier
;
3500 mubuf
->can_reorder
= info
->can_reorder
;
3501 mubuf
->offset
= const_offset
;
3502 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3503 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3504 mubuf
->definitions
[0] = Definition(val
);
3505 bld
.insert(std::move(mubuf
));
3508 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3513 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3515 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3517 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3518 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3520 if (addr
.type() == RegType::vgpr
)
3521 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3522 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3525 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3526 Temp offset
, unsigned bytes_needed
,
3527 unsigned align_
, unsigned const_offset
,
3530 unsigned bytes_size
= 0;
3531 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3532 bool global
= bld
.program
->chip_class
>= GFX9
;
3534 if (bytes_needed
== 1) {
3536 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3537 } else if (bytes_needed
== 2) {
3539 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3540 } else if (bytes_needed
<= 4) {
3542 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3543 } else if (bytes_needed
<= 8) {
3545 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3546 } else if (bytes_needed
<= 12 && !mubuf
) {
3548 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3551 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3553 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3554 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3556 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3557 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3558 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3559 mubuf
->operands
[2] = Operand(0u);
3560 mubuf
->glc
= info
->glc
;
3563 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3564 mubuf
->disable_wqm
= false;
3565 mubuf
->barrier
= info
->barrier
;
3566 mubuf
->definitions
[0] = Definition(val
);
3567 bld
.insert(std::move(mubuf
));
3569 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3571 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3572 flat
->operands
[0] = Operand(offset
);
3573 flat
->operands
[1] = Operand(s1
);
3574 flat
->glc
= info
->glc
;
3575 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3576 flat
->barrier
= info
->barrier
;
3578 flat
->definitions
[0] = Definition(val
);
3579 bld
.insert(std::move(flat
));
3583 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, bytes_size
)), val
, Operand(0u));
3588 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3590 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3591 Temp address
, unsigned base_offset
, unsigned align
)
3593 assert(util_is_power_of_two_nonzero(align
));
3595 Builder
bld(ctx
->program
, ctx
->block
);
3597 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3598 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3599 info
.align_mul
= align
;
3600 info
.align_offset
= 0;
3601 info
.barrier
= barrier_shared
;
3602 info
.can_reorder
= false;
3603 info
.const_offset
= base_offset
;
3604 emit_lds_load(ctx
, bld
, &info
);
3609 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3614 Builder
bld(ctx
->program
, ctx
->block
);
3616 ASSERTED
bool is_subdword
= false;
3617 for (unsigned i
= 0; i
< count
; i
++)
3618 is_subdword
|= offsets
[i
] % 4;
3619 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3620 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3622 /* count == 1 fast path */
3624 if (dst_type
== RegType::sgpr
)
3625 dst
[0] = bld
.as_uniform(src
);
3627 dst
[0] = as_vgpr(ctx
, src
);
3631 for (unsigned i
= 0; i
< count
- 1; i
++)
3632 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3633 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3635 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3636 src
= as_vgpr(ctx
, src
);
3638 /* use allocated_vec if possible */
3639 auto it
= ctx
->allocated_vec
.find(src
.id());
3640 if (it
!= ctx
->allocated_vec
.end()) {
3641 unsigned total_size
= 0;
3642 for (unsigned i
= 0; it
->second
[i
].bytes() && (i
< NIR_MAX_VEC_COMPONENTS
); i
++)
3643 total_size
+= it
->second
[i
].bytes();
3644 if (total_size
!= src
.bytes())
3647 unsigned elem_size
= it
->second
[0].bytes();
3649 for (unsigned i
= 0; i
< count
; i
++) {
3650 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3654 for (unsigned i
= 0; i
< count
; i
++) {
3655 unsigned start_idx
= offsets
[i
] / elem_size
;
3656 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3657 if (op_count
== 1) {
3658 if (dst_type
== RegType::sgpr
)
3659 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3661 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3665 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3666 for (unsigned j
= 0; j
< op_count
; j
++) {
3667 Temp tmp
= it
->second
[start_idx
+ j
];
3668 if (dst_type
== RegType::sgpr
)
3669 tmp
= bld
.as_uniform(tmp
);
3670 vec
->operands
[j
] = Operand(tmp
);
3672 vec
->definitions
[0] = Definition(dst
[i
]);
3673 bld
.insert(std::move(vec
));
3679 if (dst_type
== RegType::sgpr
)
3680 src
= bld
.as_uniform(src
);
3684 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3685 split
->operands
[0] = Operand(src
);
3686 for (unsigned i
= 0; i
< count
; i
++)
3687 split
->definitions
[i
] = Definition(dst
[i
]);
3688 bld
.insert(std::move(split
));
3691 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3692 int *start
, int *count
)
3694 unsigned start_elem
= ffs(todo_mask
) - 1;
3695 bool skip
= !(mask
& (1 << start_elem
));
3697 mask
= ~mask
& todo_mask
;
3701 u_bit_scan_consecutive_range(&mask
, start
, count
);
3706 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3708 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3711 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3712 Temp address
, unsigned base_offset
, unsigned align
)
3714 assert(util_is_power_of_two_nonzero(align
));
3715 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3717 Builder
bld(ctx
->program
, ctx
->block
);
3718 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3719 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3721 unsigned write_count
= 0;
3722 Temp write_datas
[32];
3723 unsigned offsets
[32];
3724 aco_opcode opcodes
[32];
3726 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3728 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3731 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3732 offsets
[write_count
] = offset
;
3733 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3735 advance_write_mask(&todo
, offset
, bytes
);
3739 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3740 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3741 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3742 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3744 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3745 aco_opcode op
= aco_opcode::num_opcodes
;
3746 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3747 op
= aco_opcode::ds_write_b128
;
3749 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3750 op
= aco_opcode::ds_write_b96
;
3752 } else if (bytes
>= 8 && aligned8
) {
3753 op
= aco_opcode::ds_write_b64
;
3755 } else if (bytes
>= 4 && aligned4
) {
3756 op
= aco_opcode::ds_write_b32
;
3758 } else if (bytes
>= 2 && aligned2
) {
3759 op
= aco_opcode::ds_write_b16
;
3761 } else if (bytes
>= 1) {
3762 op
= aco_opcode::ds_write_b8
;
3768 offsets
[write_count
] = offset
;
3769 opcodes
[write_count
] = op
;
3771 advance_write_mask(&todo
, offset
, bytes
);
3774 Operand m
= load_lds_size_m0(bld
);
3776 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3778 for (unsigned i
= 0; i
< write_count
; i
++) {
3779 aco_opcode op
= opcodes
[i
];
3780 if (op
== aco_opcode::num_opcodes
)
3783 Temp data
= write_datas
[i
];
3785 unsigned second
= write_count
;
3786 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3787 for (second
= i
+ 1; second
< write_count
; second
++) {
3788 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3789 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3790 opcodes
[second
] = aco_opcode::num_opcodes
;
3796 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3797 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3799 unsigned inline_offset
= base_offset
+ offsets
[i
];
3800 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3801 Temp address_offset
= address
;
3802 if (inline_offset
> max_offset
) {
3803 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3804 inline_offset
= offsets
[i
];
3806 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3809 Temp second_data
= write_datas
[second
];
3810 inline_offset
/= data
.bytes();
3811 bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3813 bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3818 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3820 unsigned align
= 16;
3822 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3828 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3829 Temp data
, unsigned writemask
, int swizzle_element_size
,
3830 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3832 unsigned write_count_with_skips
= 0;
3835 /* determine how to split the data */
3836 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3839 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3840 offsets
[write_count_with_skips
] = offset
;
3841 if (skips
[write_count_with_skips
]) {
3842 advance_write_mask(&todo
, offset
, bytes
);
3843 write_count_with_skips
++;
3847 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3848 * larger than swizzle_element_size */
3849 bytes
= MIN2(bytes
, swizzle_element_size
);
3851 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3853 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3854 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3857 /* dword or larger stores have to be dword-aligned */
3858 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3859 unsigned align_offset
= instr
? nir_intrinsic_align_mul(instr
) : 0;
3860 bool dword_aligned
= (align_offset
+ offset
) % 4 == 0 && align_mul
% 4 == 0;
3861 if (bytes
>= 4 && !dword_aligned
)
3862 bytes
= MIN2(bytes
, 2);
3864 advance_write_mask(&todo
, offset
, bytes
);
3865 write_count_with_skips
++;
3868 /* actually split data */
3869 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3872 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3875 write_datas
[*write_count
] = write_datas
[i
];
3876 offsets
[*write_count
] = offsets
[i
];
3881 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3882 unsigned split_cnt
= 0u, Temp dst
= Temp())
3884 Builder
bld(ctx
->program
, ctx
->block
);
3885 unsigned dword_size
= elem_size_bytes
/ 4;
3888 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3890 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3891 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3892 instr
->definitions
[0] = Definition(dst
);
3894 for (unsigned i
= 0; i
< cnt
; ++i
) {
3896 assert(arr
[i
].size() == dword_size
);
3897 allocated_vec
[i
] = arr
[i
];
3898 instr
->operands
[i
] = Operand(arr
[i
]);
3900 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3901 allocated_vec
[i
] = zero
;
3902 instr
->operands
[i
] = Operand(zero
);
3906 bld
.insert(std::move(instr
));
3909 emit_split_vector(ctx
, dst
, split_cnt
);
3911 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3916 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3918 if (const_offset
>= 4096) {
3919 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3920 const_offset
%= 4096u;
3923 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3924 else if (unlikely(voffset
.regClass() == s1
))
3925 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3926 else if (likely(voffset
.regClass() == v1
))
3927 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3929 unreachable("Unsupported register class of voffset");
3932 return const_offset
;
3935 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3936 unsigned const_offset
= 0u, bool allow_reorder
= true, bool slc
= false)
3939 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3940 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3942 Builder
bld(ctx
->program
, ctx
->block
);
3943 aco_opcode op
= (aco_opcode
) ((unsigned) aco_opcode::buffer_store_dword
+ vdata
.size() - 1);
3944 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3946 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3947 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3948 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3949 /* offen */ !voffset_op
.isUndefined(), /* idxen*/ false, /* addr64 */ false,
3950 /* disable_wqm */ false, /* glc */ true, /* dlc*/ false, /* slc */ slc
);
3952 static_cast<MUBUF_instruction
*>(r
.instr
)->can_reorder
= allow_reorder
;
3955 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3956 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3957 bool allow_combining
= true, bool reorder
= true, bool slc
= false)
3959 Builder
bld(ctx
->program
, ctx
->block
);
3960 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3962 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3964 unsigned write_count
= 0;
3965 Temp write_datas
[32];
3966 unsigned offsets
[32];
3967 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3968 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3970 for (unsigned i
= 0; i
< write_count
; i
++) {
3971 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3972 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, reorder
, slc
);
3976 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3977 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3978 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3980 assert(elem_size_bytes
== 4 || elem_size_bytes
== 8);
3981 assert((num_components
* elem_size_bytes
/ 4) == dst
.size());
3982 assert(!!stride
!= allow_combining
);
3984 Builder
bld(ctx
->program
, ctx
->block
);
3986 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3987 info
.component_stride
= allow_combining
? 0 : stride
;
3989 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3990 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3991 info
.align_offset
= 0;
3992 info
.soffset
= soffset
;
3993 info
.const_offset
= base_const_offset
;
3994 emit_mubuf_load(ctx
, bld
, &info
);
3997 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3999 Builder
bld(ctx
->program
, ctx
->block
);
4000 Temp offset
= base_offset
.first
;
4001 unsigned const_offset
= base_offset
.second
;
4003 if (!nir_src_is_const(*off_src
)) {
4004 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
4007 /* Calculate indirect offset with stride */
4008 if (likely(indirect_offset_arg
.regClass() == v1
))
4009 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
4010 else if (indirect_offset_arg
.regClass() == s1
)
4011 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
4013 unreachable("Unsupported register class of indirect offset");
4015 /* Add to the supplied base offset */
4016 if (offset
.id() == 0)
4017 offset
= with_stride
;
4018 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
4019 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
4020 else if (offset
.size() == 1 && with_stride
.size() == 1)
4021 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
4023 unreachable("Unsupported register class of indirect offset");
4025 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
4026 const_offset
+= const_offset_arg
* stride
;
4029 return std::make_pair(offset
, const_offset
);
4032 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
4034 Builder
bld(ctx
->program
, ctx
->block
);
4037 if (off1
.first
.id() && off2
.first
.id()) {
4038 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
4039 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
4040 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
4041 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
4043 unreachable("Unsupported register class of indirect offset");
4045 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
4048 return std::make_pair(offset
, off1
.second
+ off2
.second
);
4051 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
4053 Builder
bld(ctx
->program
, ctx
->block
);
4054 unsigned const_offset
= offs
.second
* multiplier
;
4056 if (!offs
.first
.id())
4057 return std::make_pair(offs
.first
, const_offset
);
4059 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
4060 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
4061 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
4063 return std::make_pair(offset
, const_offset
);
4066 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
4068 Builder
bld(ctx
->program
, ctx
->block
);
4070 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
4071 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
4072 /* component is in bytes */
4073 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
4075 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
4076 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4077 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
4080 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
4082 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
4085 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
4087 Builder
bld(ctx
->program
, ctx
->block
);
4089 switch (ctx
->shader
->info
.stage
) {
4090 case MESA_SHADER_TESS_CTRL
:
4091 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
4092 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
4093 case MESA_SHADER_TESS_EVAL
:
4094 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
4096 unreachable("Unsupported stage in get_tess_rel_patch_id");
4100 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4102 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4103 Builder
bld(ctx
->program
, ctx
->block
);
4105 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4106 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4108 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4110 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4111 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4113 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4114 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4115 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4117 return offset_mul(ctx
, offs
, 4u);
4120 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4122 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4123 Builder
bld(ctx
->program
, ctx
->block
);
4125 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4126 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
4127 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
4128 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
4129 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4130 uint32_t output_patch_stride
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
4132 std::pair
<Temp
, unsigned> offs
= instr
4133 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4134 : std::make_pair(Temp(), 0u);
4136 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4137 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4142 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4143 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4145 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4146 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4148 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4149 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4155 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4157 Builder
bld(ctx
->program
, ctx
->block
);
4159 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4160 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4162 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4164 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4165 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4166 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4168 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4169 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4174 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4176 Builder
bld(ctx
->program
, ctx
->block
);
4178 unsigned num_tcs_outputs
= ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
4179 ? util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
)
4180 : ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
4182 unsigned output_vertex_size
= num_tcs_outputs
* 16;
4183 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4184 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4185 unsigned attr_stride
= ctx
->tcs_num_patches
;
4187 std::pair
<Temp
, unsigned> offs
= instr
4188 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4189 : std::make_pair(Temp(), 0u);
4191 if (const_base_offset
)
4192 offs
.second
+= const_base_offset
* attr_stride
;
4194 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4195 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4196 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4201 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4206 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4207 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4209 if (!nir_src_is_const(*off_src
)) {
4215 off
+= nir_src_as_uint(*off_src
) * 16u;
4218 unsigned slot
= u_bit_scan64(&mask
) + (per_vertex
? 0 : VARYING_SLOT_PATCH0
);
4219 if (off
== shader_io_get_unique_index((gl_varying_slot
) slot
) * 16u)
4226 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4228 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4229 unsigned component
= nir_intrinsic_component(instr
);
4230 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4232 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4233 if (off_instr
->type
!= nir_instr_type_load_const
)
4236 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4237 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4239 if (instr
->src
[0].ssa
->bit_size
== 64)
4240 write_mask
= widen_mask(write_mask
, 2);
4242 for (unsigned i
= 0; i
< 8; ++i
) {
4243 if (write_mask
& (1 << i
)) {
4244 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4245 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, v1
);
4253 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4255 /* Only TCS per-vertex inputs are supported by this function.
4256 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4258 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4261 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4262 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4263 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4264 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4265 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4266 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4271 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4272 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4273 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4278 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4280 Builder
bld(ctx
->program
, ctx
->block
);
4282 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4283 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4284 bool indirect_write
;
4285 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4286 if (temp_only_input
&& !indirect_write
)
4290 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4291 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4292 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4293 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4295 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4296 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4297 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4298 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4299 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, true, true);
4303 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4304 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4305 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4306 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4307 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4308 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4309 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4310 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4311 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4312 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4313 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4314 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4315 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4317 unsigned num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
4318 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4319 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, num_tcs_inputs
* 16u);
4321 unreachable("Invalid LS or ES stage");
4324 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4325 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4326 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4330 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4335 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4336 return off
== ctx
->tcs_tess_lvl_out_loc
||
4337 off
== ctx
->tcs_tess_lvl_in_loc
;
4341 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4343 uint64_t mask
= per_vertex
4344 ? ctx
->program
->info
->tcs
.tes_inputs_read
4345 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4347 bool indirect_write
= false;
4348 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4349 return indirect_write
|| output_read_by_tes
;
4352 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4354 uint64_t mask
= per_vertex
4355 ? ctx
->shader
->info
.outputs_read
4356 : ctx
->shader
->info
.patch_outputs_read
;
4358 bool indirect_write
= false;
4359 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4360 return indirect_write
|| output_read
;
4363 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4365 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4366 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4368 Builder
bld(ctx
->program
, ctx
->block
);
4370 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4371 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4372 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4374 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4375 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4376 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4378 if (write_to_vmem
) {
4379 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4380 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4381 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4383 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4384 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4385 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, false);
4389 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4390 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4391 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4395 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4397 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4398 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4400 Builder
bld(ctx
->program
, ctx
->block
);
4402 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4403 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4404 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4405 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4407 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4410 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4412 if (ctx
->stage
== vertex_vs
||
4413 ctx
->stage
== tess_eval_vs
||
4414 ctx
->stage
== fragment_fs
||
4415 ctx
->stage
== ngg_vertex_gs
||
4416 ctx
->stage
== ngg_tess_eval_gs
||
4417 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4418 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4419 if (!stored_to_temps
) {
4420 fprintf(stderr
, "Unimplemented output offset instruction:\n");
4421 nir_print_instr(instr
->src
[1].ssa
->parent_instr
, stderr
);
4422 fprintf(stderr
, "\n");
4425 } else if (ctx
->stage
== vertex_es
||
4426 ctx
->stage
== vertex_ls
||
4427 ctx
->stage
== tess_eval_es
||
4428 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4429 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4430 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4431 visit_store_ls_or_es_output(ctx
, instr
);
4432 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4433 visit_store_tcs_output(ctx
, instr
, false);
4435 unreachable("Shader stage not implemented");
4439 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4441 visit_load_tcs_output(ctx
, instr
, false);
4444 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4446 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4447 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4449 Builder
bld(ctx
->program
, ctx
->block
);
4450 Builder::Result interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
, bld
.m0(prim_mask
), idx
, component
);
4451 if (ctx
->program
->has_16bank_lds
)
4452 interp_p1
.instr
->operands
[0].setLateKill(true);
4453 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4456 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4458 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4459 for (unsigned i
= 0; i
< num_components
; i
++)
4460 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4461 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4462 assert(num_components
== 4);
4463 Builder
bld(ctx
->program
, ctx
->block
);
4464 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4467 for (Operand
& op
: vec
->operands
)
4468 op
= op
.isUndefined() ? Operand(0u) : op
;
4470 vec
->definitions
[0] = Definition(dst
);
4471 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4472 emit_split_vector(ctx
, dst
, num_components
);
4476 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4478 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4479 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4480 unsigned idx
= nir_intrinsic_base(instr
);
4481 unsigned component
= nir_intrinsic_component(instr
);
4482 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4484 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4486 assert(offset
->u32
== 0);
4488 /* the lower 15bit of the prim_mask contain the offset into LDS
4489 * while the upper bits contain the number of prims */
4490 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4491 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4492 Builder
bld(ctx
->program
, ctx
->block
);
4493 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4494 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4495 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4496 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4497 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4500 if (instr
->dest
.ssa
.num_components
== 1) {
4501 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4503 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4504 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4506 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4507 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4508 vec
->operands
[i
] = Operand(tmp
);
4510 vec
->definitions
[0] = Definition(dst
);
4511 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4515 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4516 unsigned offset
, unsigned stride
, unsigned channels
)
4518 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4519 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4521 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4522 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4525 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4526 unsigned offset
, unsigned stride
, unsigned *channels
)
4528 if (!vtx_info
->chan_byte_size
) {
4529 *channels
= vtx_info
->num_channels
;
4530 return vtx_info
->chan_format
;
4533 unsigned num_channels
= *channels
;
4534 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4535 unsigned new_channels
= num_channels
+ 1;
4536 /* first, assume more loads is worse and try using a larger data format */
4537 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4539 /* don't make the attribute potentially out-of-bounds */
4540 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4544 if (new_channels
== 5) {
4545 /* then try decreasing load size (at the cost of more loads) */
4546 new_channels
= *channels
;
4547 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4551 if (new_channels
< *channels
)
4552 *channels
= new_channels
;
4553 num_channels
= new_channels
;
4556 switch (vtx_info
->chan_format
) {
4557 case V_008F0C_BUF_DATA_FORMAT_8
:
4558 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4559 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4560 case V_008F0C_BUF_DATA_FORMAT_16
:
4561 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4562 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4563 case V_008F0C_BUF_DATA_FORMAT_32
:
4564 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4565 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4567 unreachable("shouldn't reach here");
4568 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4571 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4572 * so we may need to fix it up. */
4573 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4575 Builder
bld(ctx
->program
, ctx
->block
);
4577 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4578 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4580 /* For the integer-like cases, do a natural sign extension.
4582 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4583 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4586 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4587 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4589 /* Convert back to the right type. */
4590 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4591 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4592 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4593 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4594 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4595 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4601 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4603 Builder
bld(ctx
->program
, ctx
->block
);
4604 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4605 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4607 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4608 if (off_instr
->type
!= nir_instr_type_load_const
) {
4609 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4610 nir_print_instr(off_instr
, stderr
);
4611 fprintf(stderr
, "\n");
4613 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4615 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4617 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4618 unsigned component
= nir_intrinsic_component(instr
);
4619 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4620 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4621 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4622 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4624 unsigned dfmt
= attrib_format
& 0xf;
4625 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4626 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4628 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4629 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4630 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4631 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4633 num_channels
= MAX2(num_channels
, 3);
4635 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4636 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4639 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4640 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4641 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4643 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4645 Temp divided
= bld
.tmp(v1
);
4646 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4647 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4649 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4652 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4655 index
= bld
.vadd32(bld
.def(v1
),
4656 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4657 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4660 Temp channels
[num_channels
];
4661 unsigned channel_start
= 0;
4662 bool direct_fetch
= false;
4664 /* skip unused channels at the start */
4665 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4666 channel_start
= ffs(mask
) - 1;
4667 for (unsigned i
= 0; i
< channel_start
; i
++)
4668 channels
[i
] = Temp(0, s1
);
4669 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4670 num_channels
= 3 - (ffs(mask
) - 1);
4674 while (channel_start
< num_channels
) {
4675 unsigned fetch_size
= num_channels
- channel_start
;
4676 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4677 bool expanded
= false;
4679 /* use MUBUF when possible to avoid possible alignment issues */
4680 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4681 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4682 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4683 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4684 vtx_info
->chan_byte_size
== 4;
4685 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4687 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_size
);
4689 if (fetch_size
== 3 && ctx
->options
->chip_class
== GFX6
) {
4690 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4696 Temp fetch_index
= index
;
4697 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4698 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4699 fetch_offset
= fetch_offset
% attrib_stride
;
4702 Operand
soffset(0u);
4703 if (fetch_offset
>= 4096) {
4704 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4705 fetch_offset
%= 4096;
4709 switch (fetch_size
) {
4711 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4714 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4717 assert(ctx
->options
->chip_class
>= GFX7
||
4718 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4719 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4722 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4725 unreachable("Unimplemented load_input vector size");
4729 if (channel_start
== 0 && fetch_size
== dst
.size() && !post_shuffle
&&
4730 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4731 num_channels
<= 3)) {
4732 direct_fetch
= true;
4735 fetch_dst
= bld
.tmp(RegType::vgpr
, fetch_size
);
4739 Instruction
*mubuf
= bld
.mubuf(opcode
,
4740 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4741 fetch_offset
, false, true).instr
;
4742 static_cast<MUBUF_instruction
*>(mubuf
)->can_reorder
= true;
4744 Instruction
*mtbuf
= bld
.mtbuf(opcode
,
4745 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4746 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4747 static_cast<MTBUF_instruction
*>(mtbuf
)->can_reorder
= true;
4750 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4752 if (fetch_size
== 1) {
4753 channels
[channel_start
] = fetch_dst
;
4755 for (unsigned i
= 0; i
< MIN2(fetch_size
, num_channels
- channel_start
); i
++)
4756 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
, v1
);
4759 channel_start
+= fetch_size
;
4762 if (!direct_fetch
) {
4763 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4764 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4766 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4767 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4768 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4770 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4771 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4772 unsigned num_temp
= 0;
4773 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4774 unsigned idx
= i
+ component
;
4775 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4776 Temp channel
= channels
[swizzle
[idx
]];
4777 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4778 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4779 vec
->operands
[i
] = Operand(channel
);
4783 } else if (is_float
&& idx
== 3) {
4784 vec
->operands
[i
] = Operand(0x3f800000u
);
4785 } else if (!is_float
&& idx
== 3) {
4786 vec
->operands
[i
] = Operand(1u);
4788 vec
->operands
[i
] = Operand(0u);
4791 vec
->definitions
[0] = Definition(dst
);
4792 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4793 emit_split_vector(ctx
, dst
, dst
.size());
4795 if (num_temp
== dst
.size())
4796 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4798 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4799 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4800 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4801 if (off_instr
->type
!= nir_instr_type_load_const
||
4802 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4803 fprintf(stderr
, "Unimplemented nir_intrinsic_load_input offset\n");
4804 nir_print_instr(off_instr
, stderr
);
4805 fprintf(stderr
, "\n");
4808 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4809 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4811 assert(offset
->u32
== 0);
4813 /* the lower 15bit of the prim_mask contain the offset into LDS
4814 * while the upper bits contain the number of prims */
4815 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4816 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4817 Builder
bld(ctx
->program
, ctx
->block
);
4818 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4819 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4820 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4821 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4822 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4825 unsigned idx
= nir_intrinsic_base(instr
);
4826 unsigned component
= nir_intrinsic_component(instr
);
4827 unsigned vertex_id
= 2; /* P0 */
4829 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4830 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4831 switch (src0
->u32
) {
4833 vertex_id
= 2; /* P0 */
4836 vertex_id
= 0; /* P10 */
4839 vertex_id
= 1; /* P20 */
4842 unreachable("invalid vertex index");
4846 if (dst
.size() == 1) {
4847 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4849 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4850 for (unsigned i
= 0; i
< dst
.size(); i
++)
4851 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4852 vec
->definitions
[0] = Definition(dst
);
4853 bld
.insert(std::move(vec
));
4856 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4857 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4858 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4859 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4860 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4862 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4864 unreachable("Shader stage not implemented");
4868 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4870 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4872 Builder
bld(ctx
->program
, ctx
->block
);
4873 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4876 if (!nir_src_is_const(*vertex_src
)) {
4877 /* better code could be created, but this case probably doesn't happen
4878 * much in practice */
4879 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4880 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4883 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4884 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4886 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4888 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4891 if (vertex_offset
.id()) {
4892 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4893 Operand(i
), indirect_vertex
);
4894 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4896 vertex_offset
= elem
;
4900 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4901 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4903 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4904 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4905 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4906 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4907 Operand((vertex
% 2u) * 16u), Operand(16u));
4909 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4912 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4913 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4914 return offset_mul(ctx
, offs
, 4u);
4917 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4919 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4921 Builder
bld(ctx
->program
, ctx
->block
);
4922 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4923 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4925 if (ctx
->stage
== geometry_gs
) {
4926 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4927 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4928 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4929 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4930 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4931 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4932 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4934 unreachable("Unsupported GS stage.");
4938 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4940 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4942 Builder
bld(ctx
->program
, ctx
->block
);
4943 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4945 if (load_input_from_temps(ctx
, instr
, dst
))
4948 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4949 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4950 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4952 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4955 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4957 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4959 Builder
bld(ctx
->program
, ctx
->block
);
4961 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4962 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4963 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4965 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4966 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4968 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4971 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4973 switch (ctx
->shader
->info
.stage
) {
4974 case MESA_SHADER_GEOMETRY
:
4975 visit_load_gs_per_vertex_input(ctx
, instr
);
4977 case MESA_SHADER_TESS_CTRL
:
4978 visit_load_tcs_per_vertex_input(ctx
, instr
);
4980 case MESA_SHADER_TESS_EVAL
:
4981 visit_load_tes_per_vertex_input(ctx
, instr
);
4984 unreachable("Unimplemented shader stage");
4988 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4990 visit_load_tcs_output(ctx
, instr
, true);
4993 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4995 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4996 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4998 visit_store_tcs_output(ctx
, instr
, true);
5001 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5003 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
5005 Builder
bld(ctx
->program
, ctx
->block
);
5006 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5008 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
5009 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
5012 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
5013 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
5014 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
5015 tes_w
= Operand(tmp
);
5018 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
5019 emit_split_vector(ctx
, tess_coord
, 3);
5022 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
5024 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
5025 Builder
bld(ctx
->program
, ctx
->block
);
5026 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
5027 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
5028 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
5031 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
5035 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5037 Builder
bld(ctx
->program
, ctx
->block
);
5038 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5039 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
])
5040 index
= bld
.as_uniform(index
);
5041 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
5042 unsigned binding
= nir_intrinsic_binding(instr
);
5045 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
5046 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
5047 unsigned offset
= layout
->binding
[binding
].offset
;
5049 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
5050 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
5051 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
5052 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
5053 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
5056 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
5057 stride
= layout
->binding
[binding
].size
;
5060 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
5061 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
5063 if (nir_const_index
) {
5064 const_index
= const_index
* stride
;
5065 } else if (index
.type() == RegType::vgpr
) {
5066 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
5067 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5069 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5073 if (nir_const_index
) {
5074 const_index
= const_index
+ offset
;
5075 } else if (index
.type() == RegType::vgpr
) {
5076 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5078 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5082 if (nir_const_index
&& const_index
== 0) {
5084 } else if (index
.type() == RegType::vgpr
) {
5085 index
= bld
.vadd32(bld
.def(v1
),
5086 nir_const_index
? Operand(const_index
) : Operand(index
),
5089 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5090 nir_const_index
? Operand(const_index
) : Operand(index
),
5094 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5097 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5098 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5099 bool glc
=false, bool readonly
=true)
5101 Builder
bld(ctx
->program
, ctx
->block
);
5103 bool use_smem
= dst
.type() != RegType::vgpr
&& ((ctx
->options
->chip_class
>= GFX8
&& component_size
>= 4) || readonly
);
5105 offset
= bld
.as_uniform(offset
);
5107 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5109 info
.barrier
= readonly
? barrier_none
: barrier_buffer
;
5110 info
.can_reorder
= readonly
;
5111 info
.align_mul
= align_mul
;
5112 info
.align_offset
= align_offset
;
5114 emit_smem_load(ctx
, bld
, &info
);
5116 emit_mubuf_load(ctx
, bld
, &info
);
5119 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5121 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5122 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5124 Builder
bld(ctx
->program
, ctx
->block
);
5126 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5127 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5128 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5129 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5131 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5132 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5133 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5134 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5135 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5136 if (ctx
->options
->chip_class
>= GFX10
) {
5137 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5138 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5139 S_008F0C_RESOURCE_LEVEL(1);
5141 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5142 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5144 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5145 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5146 Operand(0xFFFFFFFFu
),
5147 Operand(desc_type
));
5148 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5149 rsrc
, upper_dwords
);
5151 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5152 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5154 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5155 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5156 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5159 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5161 Builder
bld(ctx
->program
, ctx
->block
);
5162 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5163 unsigned offset
= nir_intrinsic_base(instr
);
5164 unsigned count
= instr
->dest
.ssa
.num_components
;
5165 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5167 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5168 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5169 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5170 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5171 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5172 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5173 for (unsigned i
= 0; i
< count
; ++i
) {
5174 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5175 vec
->operands
[i
] = Operand
{elems
[i
]};
5177 vec
->definitions
[0] = Definition(dst
);
5178 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5179 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5184 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5185 if (offset
!= 0) // TODO check if index != 0 as well
5186 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5187 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5190 bool aligned
= true;
5192 if (instr
->dest
.ssa
.bit_size
== 8) {
5193 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5194 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5196 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5197 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5198 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5200 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5205 switch (vec
.size()) {
5207 op
= aco_opcode::s_load_dword
;
5210 op
= aco_opcode::s_load_dwordx2
;
5216 op
= aco_opcode::s_load_dwordx4
;
5222 op
= aco_opcode::s_load_dwordx8
;
5225 unreachable("unimplemented or forbidden load_push_constant.");
5228 bld
.smem(op
, Definition(vec
), ptr
, index
);
5231 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5232 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5237 emit_split_vector(ctx
, vec
, 4);
5238 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5239 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5240 emit_extract_vector(ctx
, vec
, 0, rc
),
5241 emit_extract_vector(ctx
, vec
, 1, rc
),
5242 emit_extract_vector(ctx
, vec
, 2, rc
));
5245 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5248 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5250 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5252 Builder
bld(ctx
->program
, ctx
->block
);
5254 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5255 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5256 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5257 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5258 if (ctx
->options
->chip_class
>= GFX10
) {
5259 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5260 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5261 S_008F0C_RESOURCE_LEVEL(1);
5263 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5264 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5267 unsigned base
= nir_intrinsic_base(instr
);
5268 unsigned range
= nir_intrinsic_range(instr
);
5270 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5271 if (base
&& offset
.type() == RegType::sgpr
)
5272 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5273 else if (base
&& offset
.type() == RegType::vgpr
)
5274 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5276 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5277 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5278 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5279 Operand(desc_type
));
5280 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5281 // TODO: get alignment information for subdword constants
5282 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5285 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5287 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5288 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5290 ctx
->program
->needs_exact
= true;
5292 // TODO: optimize uniform conditions
5293 Builder
bld(ctx
->program
, ctx
->block
);
5294 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5295 assert(src
.regClass() == bld
.lm
);
5296 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5297 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5298 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5302 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5304 Builder
bld(ctx
->program
, ctx
->block
);
5306 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5307 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5309 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5310 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5312 if (ctx
->block
->loop_nest_depth
&&
5313 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5314 /* we handle discards the same way as jump instructions */
5315 append_logical_end(ctx
->block
);
5317 /* in loops, discard behaves like break */
5318 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5319 ctx
->block
->kind
|= block_kind_discard
;
5322 /* uniform discard - loop ends here */
5323 assert(nir_instr_is_last(&instr
->instr
));
5324 ctx
->block
->kind
|= block_kind_uniform
;
5325 ctx
->cf_info
.has_branch
= true;
5326 bld
.branch(aco_opcode::p_branch
);
5327 add_linear_edge(ctx
->block
->index
, linear_target
);
5331 /* we add a break right behind the discard() instructions */
5332 ctx
->block
->kind
|= block_kind_break
;
5333 unsigned idx
= ctx
->block
->index
;
5335 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5336 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5338 /* remove critical edges from linear CFG */
5339 bld
.branch(aco_opcode::p_branch
);
5340 Block
* break_block
= ctx
->program
->create_and_insert_block();
5341 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5342 break_block
->kind
|= block_kind_uniform
;
5343 add_linear_edge(idx
, break_block
);
5344 add_linear_edge(break_block
->index
, linear_target
);
5345 bld
.reset(break_block
);
5346 bld
.branch(aco_opcode::p_branch
);
5348 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5349 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5350 add_linear_edge(idx
, continue_block
);
5351 append_logical_start(continue_block
);
5352 ctx
->block
= continue_block
;
5357 /* it can currently happen that NIR doesn't remove the unreachable code */
5358 if (!nir_instr_is_last(&instr
->instr
)) {
5359 ctx
->program
->needs_exact
= true;
5360 /* save exec somewhere temporarily so that it doesn't get
5361 * overwritten before the discard from outer exec masks */
5362 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5363 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5364 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5368 /* This condition is incorrect for uniformly branched discards in a loop
5369 * predicated by a divergent condition, but the above code catches that case
5370 * and the discard would end up turning into a discard_if.
5380 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5381 /* program just ends here */
5382 ctx
->block
->kind
|= block_kind_uniform
;
5383 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5384 0 /* enabled mask */, 9 /* dest */,
5385 false /* compressed */, true/* done */, true /* valid mask */);
5386 bld
.sopp(aco_opcode::s_endpgm
);
5387 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5389 ctx
->block
->kind
|= block_kind_discard
;
5390 /* branch and linear edge is added by visit_if() */
5394 enum aco_descriptor_type
{
5405 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5406 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5408 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5409 return dim
== ac_image_cube
||
5410 dim
== ac_image_1darray
||
5411 dim
== ac_image_2darray
||
5412 dim
== ac_image_2darraymsaa
;
5415 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5416 enum aco_descriptor_type desc_type
,
5417 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5419 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5420 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5421 if (it != ctx->tex_desc.end())
5424 Temp index
= Temp();
5425 bool index_set
= false;
5426 unsigned constant_index
= 0;
5427 unsigned descriptor_set
;
5428 unsigned base_index
;
5429 Builder
bld(ctx
->program
, ctx
->block
);
5432 assert(tex_instr
&& !image
);
5434 base_index
= tex_instr
->sampler_index
;
5436 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5437 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5441 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5442 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5444 constant_index
+= array_size
* const_value
->u32
;
5446 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5447 if (indirect
.type() == RegType::vgpr
)
5448 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5450 if (array_size
!= 1)
5451 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5457 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5461 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5463 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5464 base_index
= deref_instr
->var
->data
.binding
;
5467 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5468 list
= convert_pointer_to_64_bit(ctx
, list
);
5470 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5471 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5472 unsigned offset
= binding
->offset
;
5473 unsigned stride
= binding
->size
;
5477 assert(base_index
< layout
->binding_count
);
5479 switch (desc_type
) {
5480 case ACO_DESC_IMAGE
:
5482 opcode
= aco_opcode::s_load_dwordx8
;
5484 case ACO_DESC_FMASK
:
5486 opcode
= aco_opcode::s_load_dwordx8
;
5489 case ACO_DESC_SAMPLER
:
5491 opcode
= aco_opcode::s_load_dwordx4
;
5492 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5493 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5495 case ACO_DESC_BUFFER
:
5497 opcode
= aco_opcode::s_load_dwordx4
;
5499 case ACO_DESC_PLANE_0
:
5500 case ACO_DESC_PLANE_1
:
5502 opcode
= aco_opcode::s_load_dwordx8
;
5503 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5505 case ACO_DESC_PLANE_2
:
5507 opcode
= aco_opcode::s_load_dwordx4
;
5511 unreachable("invalid desc_type\n");
5514 offset
+= constant_index
* stride
;
5516 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5517 (!index_set
|| binding
->immutable_samplers_equal
)) {
5518 if (binding
->immutable_samplers_equal
)
5521 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5522 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5523 Operand(samplers
[constant_index
* 4 + 0]),
5524 Operand(samplers
[constant_index
* 4 + 1]),
5525 Operand(samplers
[constant_index
* 4 + 2]),
5526 Operand(samplers
[constant_index
* 4 + 3]));
5531 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5533 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5534 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5537 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5539 if (desc_type
== ACO_DESC_PLANE_2
) {
5541 for (unsigned i
= 0; i
< 8; i
++)
5542 components
[i
] = bld
.tmp(s1
);
5543 bld
.pseudo(aco_opcode::p_split_vector
,
5544 Definition(components
[0]),
5545 Definition(components
[1]),
5546 Definition(components
[2]),
5547 Definition(components
[3]),
5550 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5551 bld
.pseudo(aco_opcode::p_split_vector
,
5552 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5553 Definition(components
[4]),
5554 Definition(components
[5]),
5555 Definition(components
[6]),
5556 Definition(components
[7]),
5559 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5560 components
[0], components
[1], components
[2], components
[3],
5561 components
[4], components
[5], components
[6], components
[7]);
5567 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5570 case GLSL_SAMPLER_DIM_BUF
:
5572 case GLSL_SAMPLER_DIM_1D
:
5573 return array
? 2 : 1;
5574 case GLSL_SAMPLER_DIM_2D
:
5575 return array
? 3 : 2;
5576 case GLSL_SAMPLER_DIM_MS
:
5577 return array
? 4 : 3;
5578 case GLSL_SAMPLER_DIM_3D
:
5579 case GLSL_SAMPLER_DIM_CUBE
:
5581 case GLSL_SAMPLER_DIM_RECT
:
5582 case GLSL_SAMPLER_DIM_SUBPASS
:
5584 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5593 /* Adjust the sample index according to FMASK.
5595 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5596 * which is the identity mapping. Each nibble says which physical sample
5597 * should be fetched to get that sample.
5599 * For example, 0x11111100 means there are only 2 samples stored and
5600 * the second sample covers 3/4 of the pixel. When reading samples 0
5601 * and 1, return physical sample 0 (determined by the first two 0s
5602 * in FMASK), otherwise return physical sample 1.
5604 * The sample index should be adjusted as follows:
5605 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5607 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5609 Builder
bld(ctx
->program
, ctx
->block
);
5610 Temp fmask
= bld
.tmp(v1
);
5611 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5612 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5615 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5616 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5617 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5618 load
->operands
[0] = Operand(fmask_desc_ptr
);
5619 load
->operands
[1] = Operand(s4
); /* no sampler */
5620 load
->operands
[2] = Operand(coord
);
5621 load
->definitions
[0] = Definition(fmask
);
5628 load
->can_reorder
= true; /* fmask images shouldn't be modified */
5629 ctx
->block
->instructions
.emplace_back(std::move(load
));
5631 Operand sample_index4
;
5632 if (sample_index
.isConstant() && sample_index
.constantValue() < 16) {
5633 sample_index4
= Operand(sample_index
.constantValue() << 2);
5634 } else if (sample_index
.regClass() == s1
) {
5635 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5637 assert(sample_index
.regClass() == v1
);
5638 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5642 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5643 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5644 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5645 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5647 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5649 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5650 * resource descriptor is 0 (invalid),
5652 Temp compare
= bld
.tmp(bld
.lm
);
5653 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5654 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5656 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5658 /* Replace the MSAA sample index. */
5659 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5662 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5665 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5666 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5667 bool is_array
= glsl_sampler_type_is_array(type
);
5668 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5669 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5670 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5671 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5672 int count
= image_type_to_components_count(dim
, is_array
);
5673 std::vector
<Temp
> coords(count
);
5674 Builder
bld(ctx
->program
, ctx
->block
);
5678 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5679 /* get sample index */
5680 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5681 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5682 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5683 std::vector
<Temp
> fmask_load_address
;
5684 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5685 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5687 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5688 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5690 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5695 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5696 coords
.resize(coords
.size() + 1);
5697 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5699 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5701 for (int i
= 0; i
< count
; i
++)
5702 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5705 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5706 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5707 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5708 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5711 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5714 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5715 for (unsigned i
= 0; i
< coords
.size(); i
++)
5716 vec
->operands
[i
] = Operand(coords
[i
]);
5717 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5718 vec
->definitions
[0] = Definition(res
);
5719 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5724 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5726 Builder
bld(ctx
->program
, ctx
->block
);
5727 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5728 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5729 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5730 bool is_array
= glsl_sampler_type_is_array(type
);
5731 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5733 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5734 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5735 unsigned num_channels
= util_last_bit(mask
);
5736 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5737 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5740 switch (num_channels
) {
5742 opcode
= aco_opcode::buffer_load_format_x
;
5745 opcode
= aco_opcode::buffer_load_format_xy
;
5748 opcode
= aco_opcode::buffer_load_format_xyz
;
5751 opcode
= aco_opcode::buffer_load_format_xyzw
;
5754 unreachable(">4 channel buffer image load");
5756 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5757 load
->operands
[0] = Operand(rsrc
);
5758 load
->operands
[1] = Operand(vindex
);
5759 load
->operands
[2] = Operand((uint32_t) 0);
5761 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5764 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5765 load
->definitions
[0] = Definition(tmp
);
5767 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5768 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5769 load
->barrier
= barrier_image
;
5770 ctx
->block
->instructions
.emplace_back(std::move(load
));
5772 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5776 Temp coords
= get_image_coords(ctx
, instr
, type
);
5777 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5779 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5780 unsigned num_components
= util_bitcount(dmask
);
5782 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5785 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5787 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5788 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5790 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5791 load
->operands
[0] = Operand(resource
);
5792 load
->operands
[1] = Operand(s4
); /* no sampler */
5793 load
->operands
[2] = Operand(coords
);
5794 load
->definitions
[0] = Definition(tmp
);
5795 load
->glc
= var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5796 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5797 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5798 load
->dmask
= dmask
;
5800 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5801 load
->barrier
= barrier_image
;
5802 ctx
->block
->instructions
.emplace_back(std::move(load
));
5804 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5808 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5810 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5811 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5812 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5813 bool is_array
= glsl_sampler_type_is_array(type
);
5814 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5816 bool glc
= ctx
->options
->chip_class
== GFX6
|| var
->data
.access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5818 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5819 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5820 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5822 switch (data
.size()) {
5824 opcode
= aco_opcode::buffer_store_format_x
;
5827 opcode
= aco_opcode::buffer_store_format_xy
;
5830 opcode
= aco_opcode::buffer_store_format_xyz
;
5833 opcode
= aco_opcode::buffer_store_format_xyzw
;
5836 unreachable(">4 channel buffer image store");
5838 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5839 store
->operands
[0] = Operand(rsrc
);
5840 store
->operands
[1] = Operand(vindex
);
5841 store
->operands
[2] = Operand((uint32_t) 0);
5842 store
->operands
[3] = Operand(data
);
5843 store
->idxen
= true;
5846 store
->disable_wqm
= true;
5847 store
->barrier
= barrier_image
;
5848 ctx
->program
->needs_exact
= true;
5849 ctx
->block
->instructions
.emplace_back(std::move(store
));
5853 assert(data
.type() == RegType::vgpr
);
5854 Temp coords
= get_image_coords(ctx
, instr
, type
);
5855 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5857 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5858 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5860 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5861 store
->operands
[0] = Operand(resource
);
5862 store
->operands
[1] = Operand(data
);
5863 store
->operands
[2] = Operand(coords
);
5866 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5867 store
->dmask
= (1 << data
.size()) - 1;
5869 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5870 store
->disable_wqm
= true;
5871 store
->barrier
= barrier_image
;
5872 ctx
->program
->needs_exact
= true;
5873 ctx
->block
->instructions
.emplace_back(std::move(store
));
5877 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5879 /* return the previous value if dest is ever used */
5880 bool return_previous
= false;
5881 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5882 return_previous
= true;
5885 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5886 return_previous
= true;
5890 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5891 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5892 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5893 bool is_array
= glsl_sampler_type_is_array(type
);
5894 Builder
bld(ctx
->program
, ctx
->block
);
5896 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5897 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5899 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5900 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5902 aco_opcode buf_op
, image_op
;
5903 switch (instr
->intrinsic
) {
5904 case nir_intrinsic_image_deref_atomic_add
:
5905 buf_op
= aco_opcode::buffer_atomic_add
;
5906 image_op
= aco_opcode::image_atomic_add
;
5908 case nir_intrinsic_image_deref_atomic_umin
:
5909 buf_op
= aco_opcode::buffer_atomic_umin
;
5910 image_op
= aco_opcode::image_atomic_umin
;
5912 case nir_intrinsic_image_deref_atomic_imin
:
5913 buf_op
= aco_opcode::buffer_atomic_smin
;
5914 image_op
= aco_opcode::image_atomic_smin
;
5916 case nir_intrinsic_image_deref_atomic_umax
:
5917 buf_op
= aco_opcode::buffer_atomic_umax
;
5918 image_op
= aco_opcode::image_atomic_umax
;
5920 case nir_intrinsic_image_deref_atomic_imax
:
5921 buf_op
= aco_opcode::buffer_atomic_smax
;
5922 image_op
= aco_opcode::image_atomic_smax
;
5924 case nir_intrinsic_image_deref_atomic_and
:
5925 buf_op
= aco_opcode::buffer_atomic_and
;
5926 image_op
= aco_opcode::image_atomic_and
;
5928 case nir_intrinsic_image_deref_atomic_or
:
5929 buf_op
= aco_opcode::buffer_atomic_or
;
5930 image_op
= aco_opcode::image_atomic_or
;
5932 case nir_intrinsic_image_deref_atomic_xor
:
5933 buf_op
= aco_opcode::buffer_atomic_xor
;
5934 image_op
= aco_opcode::image_atomic_xor
;
5936 case nir_intrinsic_image_deref_atomic_exchange
:
5937 buf_op
= aco_opcode::buffer_atomic_swap
;
5938 image_op
= aco_opcode::image_atomic_swap
;
5940 case nir_intrinsic_image_deref_atomic_comp_swap
:
5941 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5942 image_op
= aco_opcode::image_atomic_cmpswap
;
5945 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5948 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5950 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5951 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5952 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5953 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5954 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5955 mubuf
->operands
[0] = Operand(resource
);
5956 mubuf
->operands
[1] = Operand(vindex
);
5957 mubuf
->operands
[2] = Operand((uint32_t)0);
5958 mubuf
->operands
[3] = Operand(data
);
5959 if (return_previous
)
5960 mubuf
->definitions
[0] = Definition(dst
);
5962 mubuf
->idxen
= true;
5963 mubuf
->glc
= return_previous
;
5964 mubuf
->dlc
= false; /* Not needed for atomics */
5965 mubuf
->disable_wqm
= true;
5966 mubuf
->barrier
= barrier_image
;
5967 ctx
->program
->needs_exact
= true;
5968 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5972 Temp coords
= get_image_coords(ctx
, instr
, type
);
5973 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5974 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5975 mimg
->operands
[0] = Operand(resource
);
5976 mimg
->operands
[1] = Operand(data
);
5977 mimg
->operands
[2] = Operand(coords
);
5978 if (return_previous
)
5979 mimg
->definitions
[0] = Definition(dst
);
5980 mimg
->glc
= return_previous
;
5981 mimg
->dlc
= false; /* Not needed for atomics */
5982 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5983 mimg
->dmask
= (1 << data
.size()) - 1;
5985 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5986 mimg
->disable_wqm
= true;
5987 mimg
->barrier
= barrier_image
;
5988 ctx
->program
->needs_exact
= true;
5989 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5993 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5995 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5996 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5997 Builder
bld(ctx
->program
, ctx
->block
);
5999 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
6001 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
6002 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
6004 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
6005 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
6007 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
6008 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
6010 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
6011 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
6012 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
6013 if (dst
.type() == RegType::vgpr
)
6014 bld
.copy(Definition(dst
), shr_dst
);
6016 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
6018 emit_extract_vector(ctx
, desc
, 2, dst
);
6022 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6024 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
6025 const struct glsl_type
*type
= glsl_without_array(var
->type
);
6026 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
6027 bool is_array
= glsl_sampler_type_is_array(type
);
6028 Builder
bld(ctx
->program
, ctx
->block
);
6030 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
6031 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
6032 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
6036 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
6039 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
6041 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6043 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6044 mimg
->operands
[0] = Operand(resource
);
6045 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6046 mimg
->operands
[2] = Operand(lod
);
6047 uint8_t& dmask
= mimg
->dmask
;
6048 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6049 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6050 mimg
->da
= glsl_sampler_type_is_array(type
);
6051 mimg
->can_reorder
= true;
6052 Definition
& def
= mimg
->definitions
[0];
6053 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6055 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6056 glsl_sampler_type_is_array(type
)) {
6058 assert(instr
->dest
.ssa
.num_components
== 3);
6059 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6060 def
= Definition(tmp
);
6061 emit_split_vector(ctx
, tmp
, 3);
6063 /* divide 3rd value by 6 by multiplying with magic number */
6064 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6065 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6067 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6068 emit_extract_vector(ctx
, tmp
, 0, v1
),
6069 emit_extract_vector(ctx
, tmp
, 1, v1
),
6072 } else if (ctx
->options
->chip_class
== GFX9
&&
6073 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6074 glsl_sampler_type_is_array(type
)) {
6075 assert(instr
->dest
.ssa
.num_components
== 2);
6076 def
= Definition(dst
);
6079 def
= Definition(dst
);
6082 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6085 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6087 Builder
bld(ctx
->program
, ctx
->block
);
6088 unsigned num_components
= instr
->num_components
;
6090 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6091 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6092 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6094 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6095 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6096 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6097 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, false);
6100 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6102 Builder
bld(ctx
->program
, ctx
->block
);
6103 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6104 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6105 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6106 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6108 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6109 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6111 bool smem
= !ctx
->divergent_vals
[instr
->src
[2].ssa
->index
] &&
6112 ctx
->options
->chip_class
>= GFX8
&&
6113 elem_size_bytes
>= 4;
6115 offset
= bld
.as_uniform(offset
);
6116 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6120 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6121 if (count
== 3 && (smem
|| ctx
->options
->chip_class
== GFX6
)) {
6122 /* GFX6 doesn't support storing vec3, split it. */
6123 writemask
|= 1u << (start
+ 2);
6126 int num_bytes
= count
* elem_size_bytes
;
6128 /* dword or larger stores have to be dword-aligned */
6129 if (elem_size_bytes
< 4 && num_bytes
> 2) {
6130 // TODO: improve alignment check of sub-dword stores
6131 unsigned count_new
= 2 / elem_size_bytes
;
6132 writemask
|= ((1 << (count
- count_new
)) - 1) << (start
+ count_new
);
6137 if (num_bytes
> 16) {
6138 assert(elem_size_bytes
== 8);
6139 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6145 if (elem_size_bytes
< 4) {
6146 if (data
.type() == RegType::sgpr
) {
6147 data
= as_vgpr(ctx
, data
);
6148 emit_split_vector(ctx
, data
, 4 * data
.size() / elem_size_bytes
);
6150 RegClass rc
= RegClass(RegType::vgpr
, elem_size_bytes
).as_subdword();
6151 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6152 for (int i
= 0; i
< count
; i
++)
6153 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, rc
));
6154 write_data
= bld
.tmp(RegClass(RegType::vgpr
, num_bytes
).as_subdword());
6155 vec
->definitions
[0] = Definition(write_data
);
6156 bld
.insert(std::move(vec
));
6157 } else if (count
!= instr
->num_components
) {
6158 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6159 for (int i
= 0; i
< count
; i
++) {
6160 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(data
.type(), elem_size_bytes
/ 4));
6161 vec
->operands
[i
] = Operand(smem_nonfs
? bld
.as_uniform(elem
) : elem
);
6163 write_data
= bld
.tmp(!smem
? RegType::vgpr
: smem_nonfs
? RegType::sgpr
: data
.type(), count
* elem_size_bytes
/ 4);
6164 vec
->definitions
[0] = Definition(write_data
);
6165 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6166 } else if (!smem
&& data
.type() != RegType::vgpr
) {
6167 assert(num_bytes
% 4 == 0);
6168 write_data
= bld
.copy(bld
.def(RegType::vgpr
, num_bytes
/ 4), data
);
6169 } else if (smem_nonfs
&& data
.type() == RegType::vgpr
) {
6170 assert(num_bytes
% 4 == 0);
6171 write_data
= bld
.as_uniform(data
);
6176 aco_opcode vmem_op
, smem_op
= aco_opcode::last_opcode
;
6177 switch (num_bytes
) {
6179 vmem_op
= aco_opcode::buffer_store_byte
;
6182 vmem_op
= aco_opcode::buffer_store_short
;
6185 vmem_op
= aco_opcode::buffer_store_dword
;
6186 smem_op
= aco_opcode::s_buffer_store_dword
;
6189 vmem_op
= aco_opcode::buffer_store_dwordx2
;
6190 smem_op
= aco_opcode::s_buffer_store_dwordx2
;
6193 vmem_op
= aco_opcode::buffer_store_dwordx3
;
6194 assert(!smem
&& ctx
->options
->chip_class
> GFX6
);
6197 vmem_op
= aco_opcode::buffer_store_dwordx4
;
6198 smem_op
= aco_opcode::s_buffer_store_dwordx4
;
6201 unreachable("Store SSBO not implemented for this size.");
6203 if (ctx
->stage
== fragment_fs
)
6204 smem_op
= aco_opcode::p_fs_buffer_store_smem
;
6207 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(smem_op
, Format::SMEM
, 3, 0)};
6208 store
->operands
[0] = Operand(rsrc
);
6210 Temp off
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6211 offset
, Operand(start
* elem_size_bytes
));
6212 store
->operands
[1] = Operand(off
);
6214 store
->operands
[1] = Operand(offset
);
6216 if (smem_op
!= aco_opcode::p_fs_buffer_store_smem
)
6217 store
->operands
[1].setFixed(m0
);
6218 store
->operands
[2] = Operand(write_data
);
6219 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6221 store
->disable_wqm
= true;
6222 store
->barrier
= barrier_buffer
;
6223 ctx
->block
->instructions
.emplace_back(std::move(store
));
6224 ctx
->program
->wb_smem_l1_on_end
= true;
6225 if (smem_op
== aco_opcode::p_fs_buffer_store_smem
) {
6226 ctx
->block
->kind
|= block_kind_needs_lowering
;
6227 ctx
->program
->needs_exact
= true;
6230 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(vmem_op
, Format::MUBUF
, 4, 0)};
6231 store
->operands
[0] = Operand(rsrc
);
6232 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6233 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6234 store
->operands
[3] = Operand(write_data
);
6235 store
->offset
= start
* elem_size_bytes
;
6236 store
->offen
= (offset
.type() == RegType::vgpr
);
6237 store
->glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6239 store
->disable_wqm
= true;
6240 store
->barrier
= barrier_buffer
;
6241 ctx
->program
->needs_exact
= true;
6242 ctx
->block
->instructions
.emplace_back(std::move(store
));
6247 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6249 /* return the previous value if dest is ever used */
6250 bool return_previous
= false;
6251 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6252 return_previous
= true;
6255 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6256 return_previous
= true;
6260 Builder
bld(ctx
->program
, ctx
->block
);
6261 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6263 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6264 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6265 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6267 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6268 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6269 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6271 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6273 aco_opcode op32
, op64
;
6274 switch (instr
->intrinsic
) {
6275 case nir_intrinsic_ssbo_atomic_add
:
6276 op32
= aco_opcode::buffer_atomic_add
;
6277 op64
= aco_opcode::buffer_atomic_add_x2
;
6279 case nir_intrinsic_ssbo_atomic_imin
:
6280 op32
= aco_opcode::buffer_atomic_smin
;
6281 op64
= aco_opcode::buffer_atomic_smin_x2
;
6283 case nir_intrinsic_ssbo_atomic_umin
:
6284 op32
= aco_opcode::buffer_atomic_umin
;
6285 op64
= aco_opcode::buffer_atomic_umin_x2
;
6287 case nir_intrinsic_ssbo_atomic_imax
:
6288 op32
= aco_opcode::buffer_atomic_smax
;
6289 op64
= aco_opcode::buffer_atomic_smax_x2
;
6291 case nir_intrinsic_ssbo_atomic_umax
:
6292 op32
= aco_opcode::buffer_atomic_umax
;
6293 op64
= aco_opcode::buffer_atomic_umax_x2
;
6295 case nir_intrinsic_ssbo_atomic_and
:
6296 op32
= aco_opcode::buffer_atomic_and
;
6297 op64
= aco_opcode::buffer_atomic_and_x2
;
6299 case nir_intrinsic_ssbo_atomic_or
:
6300 op32
= aco_opcode::buffer_atomic_or
;
6301 op64
= aco_opcode::buffer_atomic_or_x2
;
6303 case nir_intrinsic_ssbo_atomic_xor
:
6304 op32
= aco_opcode::buffer_atomic_xor
;
6305 op64
= aco_opcode::buffer_atomic_xor_x2
;
6307 case nir_intrinsic_ssbo_atomic_exchange
:
6308 op32
= aco_opcode::buffer_atomic_swap
;
6309 op64
= aco_opcode::buffer_atomic_swap_x2
;
6311 case nir_intrinsic_ssbo_atomic_comp_swap
:
6312 op32
= aco_opcode::buffer_atomic_cmpswap
;
6313 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6316 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6318 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6319 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6320 mubuf
->operands
[0] = Operand(rsrc
);
6321 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6322 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6323 mubuf
->operands
[3] = Operand(data
);
6324 if (return_previous
)
6325 mubuf
->definitions
[0] = Definition(dst
);
6327 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6328 mubuf
->glc
= return_previous
;
6329 mubuf
->dlc
= false; /* Not needed for atomics */
6330 mubuf
->disable_wqm
= true;
6331 mubuf
->barrier
= barrier_buffer
;
6332 ctx
->program
->needs_exact
= true;
6333 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6336 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6338 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6339 Builder
bld(ctx
->program
, ctx
->block
);
6340 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6341 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6344 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6346 Builder
bld(ctx
->program
, ctx
->block
);
6347 unsigned num_components
= instr
->num_components
;
6348 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6350 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6351 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6352 num_components
, component_size
};
6353 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6354 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6355 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6356 info
.barrier
= barrier_buffer
;
6357 info
.can_reorder
= false;
6358 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6359 * it's safe to use SMEM */
6360 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6361 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6362 emit_global_load(ctx
, bld
, &info
);
6364 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6365 emit_smem_load(ctx
, bld
, &info
);
6369 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6371 Builder
bld(ctx
->program
, ctx
->block
);
6372 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6374 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6375 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6377 if (ctx
->options
->chip_class
>= GFX7
)
6378 addr
= as_vgpr(ctx
, addr
);
6380 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6383 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6384 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
6385 /* GFX6 doesn't support storing vec3, split it. */
6386 writemask
|= 1u << (start
+ 2);
6389 unsigned num_bytes
= count
* elem_size_bytes
;
6391 Temp write_data
= data
;
6392 if (count
!= instr
->num_components
) {
6393 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6394 for (int i
= 0; i
< count
; i
++)
6395 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, data
, start
+ i
, v1
));
6396 write_data
= bld
.tmp(RegType::vgpr
, count
);
6397 vec
->definitions
[0] = Definition(write_data
);
6398 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6401 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6402 unsigned offset
= start
* elem_size_bytes
;
6404 if (ctx
->options
->chip_class
>= GFX7
) {
6405 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6406 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6407 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6408 Temp carry
= bld
.tmp(bld
.lm
);
6409 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6411 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6412 Operand(offset
), addr0
);
6413 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6415 carry
).def(1).setHint(vcc
);
6417 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6422 bool global
= ctx
->options
->chip_class
>= GFX9
;
6424 switch (num_bytes
) {
6426 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6429 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6432 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6435 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6438 unreachable("store_global not implemented for this size.");
6441 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6442 flat
->operands
[0] = Operand(addr
);
6443 flat
->operands
[1] = Operand(s1
);
6444 flat
->operands
[2] = Operand(data
);
6447 flat
->offset
= offset
;
6448 flat
->disable_wqm
= true;
6449 flat
->barrier
= barrier_buffer
;
6450 ctx
->program
->needs_exact
= true;
6451 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6453 assert(ctx
->options
->chip_class
== GFX6
);
6456 switch (num_bytes
) {
6458 op
= aco_opcode::buffer_store_dword
;
6461 op
= aco_opcode::buffer_store_dwordx2
;
6464 op
= aco_opcode::buffer_store_dwordx4
;
6467 unreachable("store_global not implemented for this size.");
6470 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6472 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6473 mubuf
->operands
[0] = Operand(rsrc
);
6474 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6475 mubuf
->operands
[2] = Operand(0u);
6476 mubuf
->operands
[3] = Operand(write_data
);
6479 mubuf
->offset
= offset
;
6480 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6481 mubuf
->disable_wqm
= true;
6482 mubuf
->barrier
= barrier_buffer
;
6483 ctx
->program
->needs_exact
= true;
6484 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6489 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6491 /* return the previous value if dest is ever used */
6492 bool return_previous
= false;
6493 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6494 return_previous
= true;
6497 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6498 return_previous
= true;
6502 Builder
bld(ctx
->program
, ctx
->block
);
6503 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6504 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6506 if (ctx
->options
->chip_class
>= GFX7
)
6507 addr
= as_vgpr(ctx
, addr
);
6509 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6510 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6511 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6513 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6515 aco_opcode op32
, op64
;
6517 if (ctx
->options
->chip_class
>= GFX7
) {
6518 bool global
= ctx
->options
->chip_class
>= GFX9
;
6519 switch (instr
->intrinsic
) {
6520 case nir_intrinsic_global_atomic_add
:
6521 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6522 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6524 case nir_intrinsic_global_atomic_imin
:
6525 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6526 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6528 case nir_intrinsic_global_atomic_umin
:
6529 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6530 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6532 case nir_intrinsic_global_atomic_imax
:
6533 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6534 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6536 case nir_intrinsic_global_atomic_umax
:
6537 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6538 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6540 case nir_intrinsic_global_atomic_and
:
6541 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6542 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6544 case nir_intrinsic_global_atomic_or
:
6545 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6546 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6548 case nir_intrinsic_global_atomic_xor
:
6549 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6550 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6552 case nir_intrinsic_global_atomic_exchange
:
6553 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6554 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6556 case nir_intrinsic_global_atomic_comp_swap
:
6557 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6558 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6561 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6564 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6565 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6566 flat
->operands
[0] = Operand(addr
);
6567 flat
->operands
[1] = Operand(s1
);
6568 flat
->operands
[2] = Operand(data
);
6569 if (return_previous
)
6570 flat
->definitions
[0] = Definition(dst
);
6571 flat
->glc
= return_previous
;
6572 flat
->dlc
= false; /* Not needed for atomics */
6574 flat
->disable_wqm
= true;
6575 flat
->barrier
= barrier_buffer
;
6576 ctx
->program
->needs_exact
= true;
6577 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6579 assert(ctx
->options
->chip_class
== GFX6
);
6581 switch (instr
->intrinsic
) {
6582 case nir_intrinsic_global_atomic_add
:
6583 op32
= aco_opcode::buffer_atomic_add
;
6584 op64
= aco_opcode::buffer_atomic_add_x2
;
6586 case nir_intrinsic_global_atomic_imin
:
6587 op32
= aco_opcode::buffer_atomic_smin
;
6588 op64
= aco_opcode::buffer_atomic_smin_x2
;
6590 case nir_intrinsic_global_atomic_umin
:
6591 op32
= aco_opcode::buffer_atomic_umin
;
6592 op64
= aco_opcode::buffer_atomic_umin_x2
;
6594 case nir_intrinsic_global_atomic_imax
:
6595 op32
= aco_opcode::buffer_atomic_smax
;
6596 op64
= aco_opcode::buffer_atomic_smax_x2
;
6598 case nir_intrinsic_global_atomic_umax
:
6599 op32
= aco_opcode::buffer_atomic_umax
;
6600 op64
= aco_opcode::buffer_atomic_umax_x2
;
6602 case nir_intrinsic_global_atomic_and
:
6603 op32
= aco_opcode::buffer_atomic_and
;
6604 op64
= aco_opcode::buffer_atomic_and_x2
;
6606 case nir_intrinsic_global_atomic_or
:
6607 op32
= aco_opcode::buffer_atomic_or
;
6608 op64
= aco_opcode::buffer_atomic_or_x2
;
6610 case nir_intrinsic_global_atomic_xor
:
6611 op32
= aco_opcode::buffer_atomic_xor
;
6612 op64
= aco_opcode::buffer_atomic_xor_x2
;
6614 case nir_intrinsic_global_atomic_exchange
:
6615 op32
= aco_opcode::buffer_atomic_swap
;
6616 op64
= aco_opcode::buffer_atomic_swap_x2
;
6618 case nir_intrinsic_global_atomic_comp_swap
:
6619 op32
= aco_opcode::buffer_atomic_cmpswap
;
6620 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6623 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6626 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6628 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6630 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6631 mubuf
->operands
[0] = Operand(rsrc
);
6632 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6633 mubuf
->operands
[2] = Operand(0u);
6634 mubuf
->operands
[3] = Operand(data
);
6635 if (return_previous
)
6636 mubuf
->definitions
[0] = Definition(dst
);
6637 mubuf
->glc
= return_previous
;
6640 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6641 mubuf
->disable_wqm
= true;
6642 mubuf
->barrier
= barrier_buffer
;
6643 ctx
->program
->needs_exact
= true;
6644 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6648 void emit_memory_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6649 Builder
bld(ctx
->program
, ctx
->block
);
6650 switch(instr
->intrinsic
) {
6651 case nir_intrinsic_group_memory_barrier
:
6652 case nir_intrinsic_memory_barrier
:
6653 bld
.barrier(aco_opcode::p_memory_barrier_common
);
6655 case nir_intrinsic_memory_barrier_buffer
:
6656 bld
.barrier(aco_opcode::p_memory_barrier_buffer
);
6658 case nir_intrinsic_memory_barrier_image
:
6659 bld
.barrier(aco_opcode::p_memory_barrier_image
);
6661 case nir_intrinsic_memory_barrier_tcs_patch
:
6662 case nir_intrinsic_memory_barrier_shared
:
6663 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
6666 unreachable("Unimplemented memory barrier intrinsic");
6671 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6673 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6674 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6675 assert(instr
->dest
.ssa
.bit_size
>= 32 && "Bitsize not supported in load_shared.");
6676 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6677 Builder
bld(ctx
->program
, ctx
->block
);
6679 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6680 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6681 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6684 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6686 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6687 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6688 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6689 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6690 assert(elem_size_bytes
>= 4 && "Only 32bit & 64bit store_shared currently supported.");
6692 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6693 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6696 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6698 unsigned offset
= nir_intrinsic_base(instr
);
6699 Builder
bld(ctx
->program
, ctx
->block
);
6700 Operand m
= load_lds_size_m0(bld
);
6701 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6702 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6704 unsigned num_operands
= 3;
6705 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6706 switch(instr
->intrinsic
) {
6707 case nir_intrinsic_shared_atomic_add
:
6708 op32
= aco_opcode::ds_add_u32
;
6709 op64
= aco_opcode::ds_add_u64
;
6710 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6711 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6713 case nir_intrinsic_shared_atomic_imin
:
6714 op32
= aco_opcode::ds_min_i32
;
6715 op64
= aco_opcode::ds_min_i64
;
6716 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6717 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6719 case nir_intrinsic_shared_atomic_umin
:
6720 op32
= aco_opcode::ds_min_u32
;
6721 op64
= aco_opcode::ds_min_u64
;
6722 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6723 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6725 case nir_intrinsic_shared_atomic_imax
:
6726 op32
= aco_opcode::ds_max_i32
;
6727 op64
= aco_opcode::ds_max_i64
;
6728 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6729 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6731 case nir_intrinsic_shared_atomic_umax
:
6732 op32
= aco_opcode::ds_max_u32
;
6733 op64
= aco_opcode::ds_max_u64
;
6734 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6735 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6737 case nir_intrinsic_shared_atomic_and
:
6738 op32
= aco_opcode::ds_and_b32
;
6739 op64
= aco_opcode::ds_and_b64
;
6740 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6741 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6743 case nir_intrinsic_shared_atomic_or
:
6744 op32
= aco_opcode::ds_or_b32
;
6745 op64
= aco_opcode::ds_or_b64
;
6746 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6747 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6749 case nir_intrinsic_shared_atomic_xor
:
6750 op32
= aco_opcode::ds_xor_b32
;
6751 op64
= aco_opcode::ds_xor_b64
;
6752 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6753 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6755 case nir_intrinsic_shared_atomic_exchange
:
6756 op32
= aco_opcode::ds_write_b32
;
6757 op64
= aco_opcode::ds_write_b64
;
6758 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6759 op64_rtn
= aco_opcode::ds_wrxchg2_rtn_b64
;
6761 case nir_intrinsic_shared_atomic_comp_swap
:
6762 op32
= aco_opcode::ds_cmpst_b32
;
6763 op64
= aco_opcode::ds_cmpst_b64
;
6764 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6765 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6769 unreachable("Unhandled shared atomic intrinsic");
6772 /* return the previous value if dest is ever used */
6773 bool return_previous
= false;
6774 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6775 return_previous
= true;
6778 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6779 return_previous
= true;
6784 if (data
.size() == 1) {
6785 assert(instr
->dest
.ssa
.bit_size
== 32);
6786 op
= return_previous
? op32_rtn
: op32
;
6788 assert(instr
->dest
.ssa
.bit_size
== 64);
6789 op
= return_previous
? op64_rtn
: op64
;
6792 if (offset
> 65535) {
6793 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6797 aco_ptr
<DS_instruction
> ds
;
6798 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6799 ds
->operands
[0] = Operand(address
);
6800 ds
->operands
[1] = Operand(data
);
6801 if (num_operands
== 4)
6802 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6803 ds
->operands
[num_operands
- 1] = m
;
6804 ds
->offset0
= offset
;
6805 if (return_previous
)
6806 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6807 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6810 Temp
get_scratch_resource(isel_context
*ctx
)
6812 Builder
bld(ctx
->program
, ctx
->block
);
6813 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6814 if (ctx
->stage
!= compute_cs
)
6815 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6817 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6818 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);;
6820 if (ctx
->program
->chip_class
>= GFX10
) {
6821 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6822 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6823 S_008F0C_RESOURCE_LEVEL(1);
6824 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6825 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6826 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6829 /* older generations need element size = 16 bytes. element size removed in GFX9 */
6830 if (ctx
->program
->chip_class
<= GFX8
)
6831 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(3);
6833 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6836 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6837 Builder
bld(ctx
->program
, ctx
->block
);
6838 Temp rsrc
= get_scratch_resource(ctx
);
6839 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6840 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6842 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6843 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6844 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6845 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6846 info
.swizzle_component_size
= 16;
6847 info
.can_reorder
= false;
6848 info
.soffset
= ctx
->program
->scratch_offset
;
6849 emit_mubuf_load(ctx
, bld
, &info
);
6852 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6853 assert(instr
->src
[0].ssa
->bit_size
== 32 || instr
->src
[0].ssa
->bit_size
== 64);
6854 Builder
bld(ctx
->program
, ctx
->block
);
6855 Temp rsrc
= get_scratch_resource(ctx
);
6856 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6857 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6859 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6860 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6864 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
6865 int num_bytes
= count
* elem_size_bytes
;
6867 if (num_bytes
> 16) {
6868 assert(elem_size_bytes
== 8);
6869 writemask
|= (((count
- 2) << 1) - 1) << (start
+ 2);
6874 // TODO: check alignment of sub-dword stores
6875 // TODO: split 3 bytes. there is no store instruction for that
6878 if (count
!= instr
->num_components
) {
6879 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
6880 for (int i
= 0; i
< count
; i
++) {
6881 Temp elem
= emit_extract_vector(ctx
, data
, start
+ i
, RegClass(RegType::vgpr
, elem_size_bytes
/ 4));
6882 vec
->operands
[i
] = Operand(elem
);
6884 write_data
= bld
.tmp(RegClass(RegType::vgpr
, count
* elem_size_bytes
/ 4));
6885 vec
->definitions
[0] = Definition(write_data
);
6886 ctx
->block
->instructions
.emplace_back(std::move(vec
));
6892 switch (num_bytes
) {
6894 op
= aco_opcode::buffer_store_dword
;
6897 op
= aco_opcode::buffer_store_dwordx2
;
6900 op
= aco_opcode::buffer_store_dwordx3
;
6903 op
= aco_opcode::buffer_store_dwordx4
;
6906 unreachable("Invalid data size for nir_intrinsic_store_scratch.");
6909 bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_data
, start
* elem_size_bytes
, true);
6913 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6914 uint8_t log2_ps_iter_samples
;
6915 if (ctx
->program
->info
->ps
.force_persample
) {
6916 log2_ps_iter_samples
=
6917 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6919 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6922 /* The bit pattern matches that used by fixed function fragment
6924 static const unsigned ps_iter_masks
[] = {
6925 0xffff, /* not used */
6931 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6933 Builder
bld(ctx
->program
, ctx
->block
);
6935 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6936 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6937 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6938 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6940 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6943 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6944 Builder
bld(ctx
->program
, ctx
->block
);
6946 unsigned stream
= nir_intrinsic_stream_id(instr
);
6947 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6948 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6949 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6952 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6954 unsigned num_components
=
6955 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6956 assert(num_components
);
6958 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6959 unsigned stream_offset
= 0;
6960 for (unsigned i
= 0; i
< stream
; i
++) {
6961 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6962 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6965 /* Limit on the stride field for <= GFX7. */
6966 assert(stride
< (1 << 14));
6968 Temp gsvs_dwords
[4];
6969 for (unsigned i
= 0; i
< 4; i
++)
6970 gsvs_dwords
[i
] = bld
.tmp(s1
);
6971 bld
.pseudo(aco_opcode::p_split_vector
,
6972 Definition(gsvs_dwords
[0]),
6973 Definition(gsvs_dwords
[1]),
6974 Definition(gsvs_dwords
[2]),
6975 Definition(gsvs_dwords
[3]),
6978 if (stream_offset
) {
6979 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6981 Temp carry
= bld
.tmp(s1
);
6982 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6983 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6986 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6987 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6989 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6990 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6992 unsigned offset
= 0;
6993 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6994 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6997 for (unsigned j
= 0; j
< 4; j
++) {
6998 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
7001 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
7002 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
7003 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
7004 if (const_offset
>= 4096u) {
7005 if (vaddr_offset
.isUndefined())
7006 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
7008 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
7009 const_offset
%= 4096u;
7012 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
7013 mtbuf
->operands
[0] = Operand(gsvs_ring
);
7014 mtbuf
->operands
[1] = vaddr_offset
;
7015 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
7016 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
7017 mtbuf
->offen
= !vaddr_offset
.isUndefined();
7018 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
7019 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
7020 mtbuf
->offset
= const_offset
;
7023 mtbuf
->barrier
= barrier_gs_data
;
7024 mtbuf
->can_reorder
= true;
7025 bld
.insert(std::move(mtbuf
));
7028 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
7031 /* outputs for the next vertex are undefined and keeping them around can
7032 * create invalid IR with control flow */
7033 ctx
->outputs
.mask
[i
] = 0;
7036 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
7039 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
7041 Builder
bld(ctx
->program
, ctx
->block
);
7043 if (cluster_size
== 1) {
7045 } if (op
== nir_op_iand
&& cluster_size
== 4) {
7046 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
7047 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7048 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7049 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
7050 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
7051 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
7052 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
7053 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
7054 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
7055 //subgroupAnd(val) -> (exec & ~val) == 0
7056 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7057 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7058 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
7059 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
7060 //subgroupOr(val) -> (val & exec) != 0
7061 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
7062 return bool_to_vector_condition(ctx
, tmp
);
7063 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
7064 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
7065 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7066 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
7067 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
7068 return bool_to_vector_condition(ctx
, tmp
);
7070 //subgroupClustered{And,Or,Xor}(val, n) ->
7071 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
7072 //cluster_offset = ~(n - 1) & lane_id
7073 //cluster_mask = ((1 << n) - 1)
7074 //subgroupClusteredAnd():
7075 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
7076 //subgroupClusteredOr():
7077 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
7078 //subgroupClusteredXor():
7079 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
7080 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
7081 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
7084 if (op
== nir_op_iand
)
7085 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7087 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7089 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
7091 if (ctx
->program
->chip_class
<= GFX7
)
7092 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
7093 else if (ctx
->program
->wave_size
== 64)
7094 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
7096 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
7097 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7098 if (cluster_mask
!= 0xffffffff)
7099 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
7101 Definition cmp_def
= Definition();
7102 if (op
== nir_op_iand
) {
7103 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
7104 } else if (op
== nir_op_ior
) {
7105 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7106 } else if (op
== nir_op_ixor
) {
7107 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
7108 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
7109 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
7111 cmp_def
.setHint(vcc
);
7112 return cmp_def
.getTemp();
7116 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7118 Builder
bld(ctx
->program
, ctx
->block
);
7120 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
7121 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
7122 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
7124 if (op
== nir_op_iand
)
7125 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7127 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7129 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
7130 Temp lo
= lohi
.def(0).getTemp();
7131 Temp hi
= lohi
.def(1).getTemp();
7132 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7134 Definition cmp_def
= Definition();
7135 if (op
== nir_op_iand
)
7136 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7137 else if (op
== nir_op_ior
)
7138 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7139 else if (op
== nir_op_ixor
)
7140 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7141 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7142 cmp_def
.setHint(vcc
);
7143 return cmp_def
.getTemp();
7146 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7148 Builder
bld(ctx
->program
, ctx
->block
);
7150 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7151 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7152 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7153 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7154 if (op
== nir_op_iand
)
7155 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7156 else if (op
== nir_op_ior
)
7157 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7158 else if (op
== nir_op_ixor
)
7159 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7165 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7167 Builder
bld(ctx
->program
, ctx
->block
);
7168 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7169 if (src
.regClass().type() == RegType::vgpr
) {
7170 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7171 } else if (src
.regClass() == s1
) {
7172 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7173 } else if (src
.regClass() == s2
) {
7174 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7176 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7177 nir_print_instr(&instr
->instr
, stderr
);
7178 fprintf(stderr
, "\n");
7182 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7184 Builder
bld(ctx
->program
, ctx
->block
);
7185 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7186 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7187 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7189 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7190 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7191 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7192 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7195 if (ctx
->program
->chip_class
>= GFX8
) {
7196 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7197 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7198 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7199 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7200 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7201 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7203 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7204 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7205 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7206 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7207 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7208 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7209 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7210 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7211 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7212 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7215 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7216 Temp tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7217 Temp tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7218 tmp1
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7219 tmp2
= bld
.vop3(aco_opcode::v_mad_f32
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7220 Temp wqm1
= bld
.tmp(v1
);
7221 emit_wqm(ctx
, tmp1
, wqm1
, true);
7222 Temp wqm2
= bld
.tmp(v1
);
7223 emit_wqm(ctx
, tmp2
, wqm2
, true);
7224 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7228 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7230 Builder
bld(ctx
->program
, ctx
->block
);
7231 switch(instr
->intrinsic
) {
7232 case nir_intrinsic_load_barycentric_sample
:
7233 case nir_intrinsic_load_barycentric_pixel
:
7234 case nir_intrinsic_load_barycentric_centroid
: {
7235 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7236 Temp bary
= Temp(0, s2
);
7238 case INTERP_MODE_SMOOTH
:
7239 case INTERP_MODE_NONE
:
7240 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7241 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7242 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7243 bary
= ctx
->persp_centroid
;
7244 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7245 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7247 case INTERP_MODE_NOPERSPECTIVE
:
7248 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7249 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7250 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7251 bary
= ctx
->linear_centroid
;
7252 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7253 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7258 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7259 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7260 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7261 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7262 Operand(p1
), Operand(p2
));
7263 emit_split_vector(ctx
, dst
, 2);
7266 case nir_intrinsic_load_barycentric_model
: {
7267 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7269 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7270 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7271 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7272 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7273 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7274 Operand(p1
), Operand(p2
), Operand(p3
));
7275 emit_split_vector(ctx
, dst
, 3);
7278 case nir_intrinsic_load_barycentric_at_sample
: {
7279 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7280 switch (ctx
->options
->key
.fs
.num_samples
) {
7281 case 2: sample_pos_offset
+= 1 << 3; break;
7282 case 4: sample_pos_offset
+= 3 << 3; break;
7283 case 8: sample_pos_offset
+= 7 << 3; break;
7287 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7288 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7289 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7290 if (addr
.type() == RegType::sgpr
) {
7293 sample_pos_offset
+= const_addr
->u32
<< 3;
7294 offset
= Operand(sample_pos_offset
);
7295 } else if (ctx
->options
->chip_class
>= GFX9
) {
7296 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7298 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7299 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7302 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7303 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7305 } else if (ctx
->options
->chip_class
>= GFX9
) {
7306 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7307 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7308 } else if (ctx
->options
->chip_class
>= GFX7
) {
7309 /* addr += private_segment_buffer + sample_pos_offset */
7310 Temp tmp0
= bld
.tmp(s1
);
7311 Temp tmp1
= bld
.tmp(s1
);
7312 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7313 Definition scc_tmp
= bld
.def(s1
, scc
);
7314 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7315 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7316 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7317 Temp pck0
= bld
.tmp(v1
);
7318 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7319 tmp1
= as_vgpr(ctx
, tmp1
);
7320 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7321 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7323 /* sample_pos = flat_load_dwordx2 addr */
7324 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7326 assert(ctx
->options
->chip_class
== GFX6
);
7328 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7329 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7330 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7332 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7333 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7335 sample_pos
= bld
.tmp(v2
);
7337 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7338 load
->definitions
[0] = Definition(sample_pos
);
7339 load
->operands
[0] = Operand(rsrc
);
7340 load
->operands
[1] = Operand(addr
);
7341 load
->operands
[2] = Operand(0u);
7342 load
->offset
= sample_pos_offset
;
7344 load
->addr64
= true;
7347 load
->disable_wqm
= false;
7348 load
->barrier
= barrier_none
;
7349 load
->can_reorder
= true;
7350 ctx
->block
->instructions
.emplace_back(std::move(load
));
7353 /* sample_pos -= 0.5 */
7354 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7355 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7356 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7357 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7358 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7360 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7363 case nir_intrinsic_load_barycentric_at_offset
: {
7364 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7365 RegClass rc
= RegClass(offset
.type(), 1);
7366 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7367 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7368 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7371 case nir_intrinsic_load_front_face
: {
7372 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7373 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7376 case nir_intrinsic_load_view_index
: {
7377 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7378 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7379 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7385 case nir_intrinsic_load_layer_id
: {
7386 unsigned idx
= nir_intrinsic_base(instr
);
7387 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7388 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7391 case nir_intrinsic_load_frag_coord
: {
7392 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7395 case nir_intrinsic_load_sample_pos
: {
7396 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7397 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7398 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7399 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7400 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7403 case nir_intrinsic_load_tess_coord
:
7404 visit_load_tess_coord(ctx
, instr
);
7406 case nir_intrinsic_load_interpolated_input
:
7407 visit_load_interpolated_input(ctx
, instr
);
7409 case nir_intrinsic_store_output
:
7410 visit_store_output(ctx
, instr
);
7412 case nir_intrinsic_load_input
:
7413 case nir_intrinsic_load_input_vertex
:
7414 visit_load_input(ctx
, instr
);
7416 case nir_intrinsic_load_output
:
7417 visit_load_output(ctx
, instr
);
7419 case nir_intrinsic_load_per_vertex_input
:
7420 visit_load_per_vertex_input(ctx
, instr
);
7422 case nir_intrinsic_load_per_vertex_output
:
7423 visit_load_per_vertex_output(ctx
, instr
);
7425 case nir_intrinsic_store_per_vertex_output
:
7426 visit_store_per_vertex_output(ctx
, instr
);
7428 case nir_intrinsic_load_ubo
:
7429 visit_load_ubo(ctx
, instr
);
7431 case nir_intrinsic_load_push_constant
:
7432 visit_load_push_constant(ctx
, instr
);
7434 case nir_intrinsic_load_constant
:
7435 visit_load_constant(ctx
, instr
);
7437 case nir_intrinsic_vulkan_resource_index
:
7438 visit_load_resource(ctx
, instr
);
7440 case nir_intrinsic_discard
:
7441 visit_discard(ctx
, instr
);
7443 case nir_intrinsic_discard_if
:
7444 visit_discard_if(ctx
, instr
);
7446 case nir_intrinsic_load_shared
:
7447 visit_load_shared(ctx
, instr
);
7449 case nir_intrinsic_store_shared
:
7450 visit_store_shared(ctx
, instr
);
7452 case nir_intrinsic_shared_atomic_add
:
7453 case nir_intrinsic_shared_atomic_imin
:
7454 case nir_intrinsic_shared_atomic_umin
:
7455 case nir_intrinsic_shared_atomic_imax
:
7456 case nir_intrinsic_shared_atomic_umax
:
7457 case nir_intrinsic_shared_atomic_and
:
7458 case nir_intrinsic_shared_atomic_or
:
7459 case nir_intrinsic_shared_atomic_xor
:
7460 case nir_intrinsic_shared_atomic_exchange
:
7461 case nir_intrinsic_shared_atomic_comp_swap
:
7462 visit_shared_atomic(ctx
, instr
);
7464 case nir_intrinsic_image_deref_load
:
7465 visit_image_load(ctx
, instr
);
7467 case nir_intrinsic_image_deref_store
:
7468 visit_image_store(ctx
, instr
);
7470 case nir_intrinsic_image_deref_atomic_add
:
7471 case nir_intrinsic_image_deref_atomic_umin
:
7472 case nir_intrinsic_image_deref_atomic_imin
:
7473 case nir_intrinsic_image_deref_atomic_umax
:
7474 case nir_intrinsic_image_deref_atomic_imax
:
7475 case nir_intrinsic_image_deref_atomic_and
:
7476 case nir_intrinsic_image_deref_atomic_or
:
7477 case nir_intrinsic_image_deref_atomic_xor
:
7478 case nir_intrinsic_image_deref_atomic_exchange
:
7479 case nir_intrinsic_image_deref_atomic_comp_swap
:
7480 visit_image_atomic(ctx
, instr
);
7482 case nir_intrinsic_image_deref_size
:
7483 visit_image_size(ctx
, instr
);
7485 case nir_intrinsic_load_ssbo
:
7486 visit_load_ssbo(ctx
, instr
);
7488 case nir_intrinsic_store_ssbo
:
7489 visit_store_ssbo(ctx
, instr
);
7491 case nir_intrinsic_load_global
:
7492 visit_load_global(ctx
, instr
);
7494 case nir_intrinsic_store_global
:
7495 visit_store_global(ctx
, instr
);
7497 case nir_intrinsic_global_atomic_add
:
7498 case nir_intrinsic_global_atomic_imin
:
7499 case nir_intrinsic_global_atomic_umin
:
7500 case nir_intrinsic_global_atomic_imax
:
7501 case nir_intrinsic_global_atomic_umax
:
7502 case nir_intrinsic_global_atomic_and
:
7503 case nir_intrinsic_global_atomic_or
:
7504 case nir_intrinsic_global_atomic_xor
:
7505 case nir_intrinsic_global_atomic_exchange
:
7506 case nir_intrinsic_global_atomic_comp_swap
:
7507 visit_global_atomic(ctx
, instr
);
7509 case nir_intrinsic_ssbo_atomic_add
:
7510 case nir_intrinsic_ssbo_atomic_imin
:
7511 case nir_intrinsic_ssbo_atomic_umin
:
7512 case nir_intrinsic_ssbo_atomic_imax
:
7513 case nir_intrinsic_ssbo_atomic_umax
:
7514 case nir_intrinsic_ssbo_atomic_and
:
7515 case nir_intrinsic_ssbo_atomic_or
:
7516 case nir_intrinsic_ssbo_atomic_xor
:
7517 case nir_intrinsic_ssbo_atomic_exchange
:
7518 case nir_intrinsic_ssbo_atomic_comp_swap
:
7519 visit_atomic_ssbo(ctx
, instr
);
7521 case nir_intrinsic_load_scratch
:
7522 visit_load_scratch(ctx
, instr
);
7524 case nir_intrinsic_store_scratch
:
7525 visit_store_scratch(ctx
, instr
);
7527 case nir_intrinsic_get_buffer_size
:
7528 visit_get_buffer_size(ctx
, instr
);
7530 case nir_intrinsic_control_barrier
: {
7531 if (ctx
->program
->chip_class
== GFX6
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7532 /* GFX6 only (thanks to a hw bug workaround):
7533 * The real barrier instruction isn’t needed, because an entire patch
7534 * always fits into a single wave.
7539 if (ctx
->program
->workgroup_size
> ctx
->program
->wave_size
)
7540 bld
.sopp(aco_opcode::s_barrier
);
7544 case nir_intrinsic_memory_barrier_tcs_patch
:
7545 case nir_intrinsic_group_memory_barrier
:
7546 case nir_intrinsic_memory_barrier
:
7547 case nir_intrinsic_memory_barrier_buffer
:
7548 case nir_intrinsic_memory_barrier_image
:
7549 case nir_intrinsic_memory_barrier_shared
:
7550 emit_memory_barrier(ctx
, instr
);
7552 case nir_intrinsic_load_num_work_groups
: {
7553 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7554 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7555 emit_split_vector(ctx
, dst
, 3);
7558 case nir_intrinsic_load_local_invocation_id
: {
7559 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7560 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7561 emit_split_vector(ctx
, dst
, 3);
7564 case nir_intrinsic_load_work_group_id
: {
7565 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7566 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7567 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7568 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7569 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7570 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7571 emit_split_vector(ctx
, dst
, 3);
7574 case nir_intrinsic_load_local_invocation_index
: {
7575 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7577 /* The tg_size bits [6:11] contain the subgroup id,
7578 * we need this multiplied by the wave size, and then OR the thread id to it.
7580 if (ctx
->program
->wave_size
== 64) {
7581 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7582 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7583 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7584 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7586 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7587 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7588 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7589 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7593 case nir_intrinsic_load_subgroup_id
: {
7594 if (ctx
->stage
== compute_cs
) {
7595 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7596 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7598 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7602 case nir_intrinsic_load_subgroup_invocation
: {
7603 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7606 case nir_intrinsic_load_num_subgroups
: {
7607 if (ctx
->stage
== compute_cs
)
7608 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7609 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7611 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7614 case nir_intrinsic_ballot
: {
7615 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7616 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7617 Definition tmp
= bld
.def(dst
.regClass());
7618 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7619 if (instr
->src
[0].ssa
->bit_size
== 1) {
7620 assert(src
.regClass() == bld
.lm
);
7621 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7622 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7623 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7624 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7625 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7627 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7628 nir_print_instr(&instr
->instr
, stderr
);
7629 fprintf(stderr
, "\n");
7631 if (dst
.size() != bld
.lm
.size()) {
7632 /* Wave32 with ballot size set to 64 */
7633 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7635 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7638 case nir_intrinsic_shuffle
:
7639 case nir_intrinsic_read_invocation
: {
7640 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7641 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
]) {
7642 emit_uniform_subgroup(ctx
, instr
, src
);
7644 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7645 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !ctx
->divergent_vals
[instr
->src
[1].ssa
->index
])
7646 tid
= bld
.as_uniform(tid
);
7647 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7648 if (src
.regClass() == v1
) {
7649 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7650 } else if (src
.regClass() == v2
) {
7651 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7652 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7653 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7654 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7656 emit_split_vector(ctx
, dst
, 2);
7657 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7658 assert(src
.regClass() == bld
.lm
);
7659 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7660 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7661 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7662 assert(src
.regClass() == bld
.lm
);
7664 if (ctx
->program
->chip_class
<= GFX7
)
7665 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7666 else if (ctx
->program
->wave_size
== 64)
7667 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7669 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7670 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7671 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7672 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7674 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7675 nir_print_instr(&instr
->instr
, stderr
);
7676 fprintf(stderr
, "\n");
7681 case nir_intrinsic_load_sample_id
: {
7682 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7683 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7686 case nir_intrinsic_load_sample_mask_in
: {
7687 visit_load_sample_mask_in(ctx
, instr
);
7690 case nir_intrinsic_read_first_invocation
: {
7691 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7692 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7693 if (src
.regClass() == v1
) {
7695 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7697 } else if (src
.regClass() == v2
) {
7698 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7699 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7700 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7701 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7702 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7703 emit_split_vector(ctx
, dst
, 2);
7704 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7705 assert(src
.regClass() == bld
.lm
);
7706 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7707 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7708 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7709 } else if (src
.regClass() == s1
) {
7710 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7711 } else if (src
.regClass() == s2
) {
7712 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7714 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7715 nir_print_instr(&instr
->instr
, stderr
);
7716 fprintf(stderr
, "\n");
7720 case nir_intrinsic_vote_all
: {
7721 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7722 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7723 assert(src
.regClass() == bld
.lm
);
7724 assert(dst
.regClass() == bld
.lm
);
7726 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7727 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7728 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7731 case nir_intrinsic_vote_any
: {
7732 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7733 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7734 assert(src
.regClass() == bld
.lm
);
7735 assert(dst
.regClass() == bld
.lm
);
7737 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7738 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7741 case nir_intrinsic_reduce
:
7742 case nir_intrinsic_inclusive_scan
:
7743 case nir_intrinsic_exclusive_scan
: {
7744 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7745 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7746 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7747 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7748 nir_intrinsic_cluster_size(instr
) : 0;
7749 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7751 if (!ctx
->divergent_vals
[instr
->src
[0].ssa
->index
] && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7752 emit_uniform_subgroup(ctx
, instr
, src
);
7753 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7754 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7756 else if (op
== nir_op_iadd
)
7758 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7760 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7762 switch (instr
->intrinsic
) {
7763 case nir_intrinsic_reduce
:
7764 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7766 case nir_intrinsic_exclusive_scan
:
7767 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7769 case nir_intrinsic_inclusive_scan
:
7770 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7775 } else if (cluster_size
== 1) {
7776 bld
.copy(Definition(dst
), src
);
7778 src
= as_vgpr(ctx
, src
);
7782 #define CASE(name) case nir_op_##name: reduce_op = (src.regClass() == v1) ? name##32 : name##64; break;
7797 unreachable("unknown reduction op");
7802 switch (instr
->intrinsic
) {
7803 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7804 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7805 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7807 unreachable("unknown reduce intrinsic");
7810 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7811 reduce
->operands
[0] = Operand(src
);
7812 // filled in by aco_reduce_assign.cpp, used internally as part of the
7814 assert(dst
.size() == 1 || dst
.size() == 2);
7815 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7816 reduce
->operands
[2] = Operand(v1
.as_linear());
7818 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7819 reduce
->definitions
[0] = Definition(tmp_dst
);
7820 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7821 reduce
->definitions
[2] = Definition();
7822 reduce
->definitions
[3] = Definition(scc
, s1
);
7823 reduce
->definitions
[4] = Definition();
7824 reduce
->reduce_op
= reduce_op
;
7825 reduce
->cluster_size
= cluster_size
;
7826 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7828 emit_wqm(ctx
, tmp_dst
, dst
);
7832 case nir_intrinsic_quad_broadcast
: {
7833 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7834 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7835 emit_uniform_subgroup(ctx
, instr
, src
);
7837 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7838 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7839 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7841 if (instr
->dest
.ssa
.bit_size
== 1) {
7842 assert(src
.regClass() == bld
.lm
);
7843 assert(dst
.regClass() == bld
.lm
);
7844 uint32_t half_mask
= 0x11111111u
<< lane
;
7845 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7846 Temp tmp
= bld
.tmp(bld
.lm
);
7847 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7848 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7849 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7850 emit_wqm(ctx
, tmp
, dst
);
7851 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7852 if (ctx
->program
->chip_class
>= GFX8
)
7853 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7855 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7856 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7857 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7858 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7859 if (ctx
->program
->chip_class
>= GFX8
) {
7860 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7861 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7863 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7864 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7866 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7867 emit_split_vector(ctx
, dst
, 2);
7869 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7870 nir_print_instr(&instr
->instr
, stderr
);
7871 fprintf(stderr
, "\n");
7876 case nir_intrinsic_quad_swap_horizontal
:
7877 case nir_intrinsic_quad_swap_vertical
:
7878 case nir_intrinsic_quad_swap_diagonal
:
7879 case nir_intrinsic_quad_swizzle_amd
: {
7880 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7881 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7882 emit_uniform_subgroup(ctx
, instr
, src
);
7885 uint16_t dpp_ctrl
= 0;
7886 switch (instr
->intrinsic
) {
7887 case nir_intrinsic_quad_swap_horizontal
:
7888 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7890 case nir_intrinsic_quad_swap_vertical
:
7891 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7893 case nir_intrinsic_quad_swap_diagonal
:
7894 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7896 case nir_intrinsic_quad_swizzle_amd
:
7897 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7902 if (ctx
->program
->chip_class
< GFX8
)
7903 dpp_ctrl
|= (1 << 15);
7905 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7906 if (instr
->dest
.ssa
.bit_size
== 1) {
7907 assert(src
.regClass() == bld
.lm
);
7908 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7909 if (ctx
->program
->chip_class
>= GFX8
)
7910 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7912 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7913 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7914 emit_wqm(ctx
, tmp
, dst
);
7915 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7917 if (ctx
->program
->chip_class
>= GFX8
)
7918 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7920 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7921 emit_wqm(ctx
, tmp
, dst
);
7922 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7923 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7924 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7925 if (ctx
->program
->chip_class
>= GFX8
) {
7926 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7927 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7929 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7930 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7932 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7933 emit_split_vector(ctx
, dst
, 2);
7935 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7936 nir_print_instr(&instr
->instr
, stderr
);
7937 fprintf(stderr
, "\n");
7941 case nir_intrinsic_masked_swizzle_amd
: {
7942 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7943 if (!ctx
->divergent_vals
[instr
->dest
.ssa
.index
]) {
7944 emit_uniform_subgroup(ctx
, instr
, src
);
7947 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7948 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7949 if (dst
.regClass() == v1
) {
7951 bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false),
7953 } else if (dst
.regClass() == v2
) {
7954 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7955 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7956 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, mask
, 0, false));
7957 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, mask
, 0, false));
7958 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7959 emit_split_vector(ctx
, dst
, 2);
7961 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7962 nir_print_instr(&instr
->instr
, stderr
);
7963 fprintf(stderr
, "\n");
7967 case nir_intrinsic_write_invocation_amd
: {
7968 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7969 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7970 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7971 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7972 if (dst
.regClass() == v1
) {
7973 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7974 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7975 } else if (dst
.regClass() == v2
) {
7976 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7977 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7978 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7979 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7980 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7981 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7982 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7983 emit_split_vector(ctx
, dst
, 2);
7985 fprintf(stderr
, "Unimplemented NIR instr bit size: ");
7986 nir_print_instr(&instr
->instr
, stderr
);
7987 fprintf(stderr
, "\n");
7991 case nir_intrinsic_mbcnt_amd
: {
7992 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7993 RegClass rc
= RegClass(src
.type(), 1);
7994 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7995 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7996 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7997 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7998 emit_wqm(ctx
, wqm_tmp
, dst
);
8001 case nir_intrinsic_load_helper_invocation
: {
8002 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8003 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
8004 ctx
->block
->kind
|= block_kind_needs_lowering
;
8005 ctx
->program
->needs_exact
= true;
8008 case nir_intrinsic_is_helper_invocation
: {
8009 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8010 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
8011 ctx
->block
->kind
|= block_kind_needs_lowering
;
8012 ctx
->program
->needs_exact
= true;
8015 case nir_intrinsic_demote
:
8016 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
8018 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8019 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8020 ctx
->block
->kind
|= block_kind_uses_demote
;
8021 ctx
->program
->needs_exact
= true;
8023 case nir_intrinsic_demote_if
: {
8024 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
8025 assert(src
.regClass() == bld
.lm
);
8026 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
8027 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
8029 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
8030 ctx
->cf_info
.exec_potentially_empty_discard
= true;
8031 ctx
->block
->kind
|= block_kind_uses_demote
;
8032 ctx
->program
->needs_exact
= true;
8035 case nir_intrinsic_first_invocation
: {
8036 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
8037 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
8040 case nir_intrinsic_shader_clock
:
8041 bld
.smem(aco_opcode::s_memtime
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), false);
8042 emit_split_vector(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 2);
8044 case nir_intrinsic_load_vertex_id_zero_base
: {
8045 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8046 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
8049 case nir_intrinsic_load_first_vertex
: {
8050 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8051 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
8054 case nir_intrinsic_load_base_instance
: {
8055 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8056 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
8059 case nir_intrinsic_load_instance_id
: {
8060 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8061 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
8064 case nir_intrinsic_load_draw_id
: {
8065 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8066 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
8069 case nir_intrinsic_load_invocation_id
: {
8070 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8072 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
8073 if (ctx
->options
->chip_class
>= GFX10
)
8074 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8076 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
8077 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
8078 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
8079 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
8081 unreachable("Unsupported stage for load_invocation_id");
8086 case nir_intrinsic_load_primitive_id
: {
8087 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8089 switch (ctx
->shader
->info
.stage
) {
8090 case MESA_SHADER_GEOMETRY
:
8091 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
8093 case MESA_SHADER_TESS_CTRL
:
8094 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
8096 case MESA_SHADER_TESS_EVAL
:
8097 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
8100 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
8105 case nir_intrinsic_load_patch_vertices_in
: {
8106 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8107 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8109 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8110 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8113 case nir_intrinsic_emit_vertex_with_counter
: {
8114 visit_emit_vertex_with_counter(ctx
, instr
);
8117 case nir_intrinsic_end_primitive_with_counter
: {
8118 unsigned stream
= nir_intrinsic_stream_id(instr
);
8119 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8122 case nir_intrinsic_set_vertex_count
: {
8123 /* unused, the HW keeps track of this for us */
8127 fprintf(stderr
, "Unimplemented intrinsic instr: ");
8128 nir_print_instr(&instr
->instr
, stderr
);
8129 fprintf(stderr
, "\n");
8137 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8138 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8139 enum glsl_base_type
*stype
)
8141 nir_deref_instr
*texture_deref_instr
= NULL
;
8142 nir_deref_instr
*sampler_deref_instr
= NULL
;
8145 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8146 switch (instr
->src
[i
].src_type
) {
8147 case nir_tex_src_texture_deref
:
8148 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8150 case nir_tex_src_sampler_deref
:
8151 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8153 case nir_tex_src_plane
:
8154 plane
= nir_src_as_int(instr
->src
[i
].src
);
8161 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8163 if (!sampler_deref_instr
)
8164 sampler_deref_instr
= texture_deref_instr
;
8167 assert(instr
->op
!= nir_texop_txf_ms
&&
8168 instr
->op
!= nir_texop_samples_identical
);
8169 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8170 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8171 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8172 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8173 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8174 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8176 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8179 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8181 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8182 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8183 Builder
bld(ctx
->program
, ctx
->block
);
8185 /* to avoid unnecessary moves, we split and recombine sampler and image */
8186 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8187 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8188 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8189 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8190 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8191 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8192 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8193 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8195 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8196 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8197 img
[0], img
[1], img
[2], img
[3],
8198 img
[4], img
[5], img
[6], img
[7]);
8199 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8200 samp
[0], samp
[1], samp
[2], samp
[3]);
8203 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8204 instr
->op
== nir_texop_samples_identical
))
8205 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8208 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8209 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8211 Builder
bld(ctx
->program
, ctx
->block
);
8213 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8214 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8215 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8217 Operand
neg_one(0xbf800000u
);
8218 Operand
one(0x3f800000u
);
8219 Operand
two(0x40000000u
);
8220 Operand
four(0x40800000u
);
8222 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8223 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8224 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8226 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8227 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8228 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8229 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8232 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8233 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8234 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8236 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8239 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8240 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8241 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8244 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8245 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8247 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8248 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8251 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8253 Builder
bld(ctx
->program
, ctx
->block
);
8254 Temp ma
, tc
, sc
, id
;
8257 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8259 // see comment in ac_prepare_cube_coords()
8260 if (ctx
->options
->chip_class
<= GFX8
)
8261 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8264 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8266 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8267 vop3a
->operands
[0] = Operand(ma
);
8268 vop3a
->abs
[0] = true;
8269 Temp invma
= bld
.tmp(v1
);
8270 vop3a
->definitions
[0] = Definition(invma
);
8271 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8273 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8275 sc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8277 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8279 tc
= bld
.vop2(aco_opcode::v_madak_f32
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8281 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8284 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8285 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8287 for (unsigned i
= 0; i
< 2; i
++) {
8288 // see comment in ac_prepare_cube_coords()
8290 Temp deriv_sc
, deriv_tc
;
8291 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8292 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8294 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8296 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8297 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8298 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8299 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8300 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8301 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8302 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8305 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8306 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8310 id
= bld
.vop2(aco_opcode::v_madmk_f32
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8317 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8319 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8321 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8322 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8325 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8326 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8327 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8331 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8333 Builder
bld(ctx
->program
, ctx
->block
);
8334 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8335 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false;
8336 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8337 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp();
8338 std::vector
<Temp
> coords
;
8339 std::vector
<Temp
> derivs
;
8340 nir_const_value
*sample_index_cv
= NULL
;
8341 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8342 enum glsl_base_type stype
;
8343 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8345 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8346 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8347 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8348 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8350 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8351 switch (instr
->src
[i
].src_type
) {
8352 case nir_tex_src_coord
: {
8353 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8354 for (unsigned i
= 0; i
< coord
.size(); i
++)
8355 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8358 case nir_tex_src_bias
:
8359 if (instr
->op
== nir_texop_txb
) {
8360 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8364 case nir_tex_src_lod
: {
8365 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8367 if (val
&& val
->f32
<= 0.0) {
8370 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8375 case nir_tex_src_comparator
:
8376 if (instr
->is_shadow
) {
8377 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8381 case nir_tex_src_offset
:
8382 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8383 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8386 case nir_tex_src_ddx
:
8387 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8390 case nir_tex_src_ddy
:
8391 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8394 case nir_tex_src_ms_index
:
8395 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8396 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8397 has_sample_index
= true;
8399 case nir_tex_src_texture_offset
:
8400 case nir_tex_src_sampler_offset
:
8406 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8407 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8409 if (instr
->op
== nir_texop_texture_samples
) {
8410 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8412 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8413 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8414 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8415 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8417 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8418 samples
, Operand(1u), bld
.scc(is_msaa
));
8422 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8423 aco_ptr
<Instruction
> tmp_instr
;
8424 Temp acc
, pack
= Temp();
8426 uint32_t pack_const
= 0;
8427 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8428 if (!const_offset
[i
])
8430 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8433 if (offset
.type() == RegType::sgpr
) {
8434 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8435 if (const_offset
[i
])
8438 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8439 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8442 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8445 if (pack
== Temp()) {
8448 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8452 if (pack_const
&& pack
!= Temp())
8453 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8455 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8456 if (const_offset
[i
])
8459 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8460 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8463 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8466 if (pack
== Temp()) {
8469 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8473 if (pack_const
&& pack
!= Temp())
8474 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8476 if (pack_const
&& pack
== Temp())
8477 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8478 else if (pack
== Temp())
8484 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8485 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8487 /* pack derivatives */
8488 if (has_ddx
|| has_ddy
) {
8489 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8490 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8491 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8492 derivs
= {ddx
, zero
, ddy
, zero
};
8494 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8495 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8496 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8497 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8502 if (instr
->coord_components
> 1 &&
8503 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8505 instr
->op
!= nir_texop_txf
)
8506 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8508 if (instr
->coord_components
> 2 &&
8509 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8510 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8511 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8512 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8514 instr
->op
!= nir_texop_txf
&&
8515 instr
->op
!= nir_texop_txf_ms
&&
8516 instr
->op
!= nir_texop_fragment_fetch
&&
8517 instr
->op
!= nir_texop_fragment_mask_fetch
)
8518 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8520 if (ctx
->options
->chip_class
== GFX9
&&
8521 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8522 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8523 assert(coords
.size() > 0 && coords
.size() < 3);
8525 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8526 Operand((uint32_t) 0) :
8527 Operand((uint32_t) 0x3f000000)));
8530 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8532 if (instr
->op
== nir_texop_samples_identical
)
8533 resource
= fmask_ptr
;
8535 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8536 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8537 instr
->op
!= nir_texop_txs
&&
8538 instr
->op
!= nir_texop_fragment_fetch
&&
8539 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8540 assert(has_sample_index
);
8541 Operand
op(sample_index
);
8542 if (sample_index_cv
)
8543 op
= Operand(sample_index_cv
->u32
);
8544 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8547 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8548 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8549 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8550 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8555 /* Build tex instruction */
8556 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8557 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8558 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8560 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8563 /* gather4 selects the component by dmask and always returns vec4 */
8564 if (instr
->op
== nir_texop_tg4
) {
8565 assert(instr
->dest
.ssa
.num_components
== 4);
8566 if (instr
->is_shadow
)
8569 dmask
= 1 << instr
->component
;
8570 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8571 tmp_dst
= bld
.tmp(v4
);
8572 } else if (instr
->op
== nir_texop_samples_identical
) {
8573 tmp_dst
= bld
.tmp(v1
);
8574 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8575 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8578 aco_ptr
<MIMG_instruction
> tex
;
8579 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8581 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8583 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8584 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8587 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8588 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8590 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8591 tex
->operands
[0] = Operand(resource
);
8592 tex
->operands
[1] = Operand(s4
); /* no sampler */
8593 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8594 if (ctx
->options
->chip_class
== GFX9
&&
8595 instr
->op
== nir_texop_txs
&&
8596 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8598 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8599 } else if (instr
->op
== nir_texop_query_levels
) {
8600 tex
->dmask
= 1 << 3;
8605 tex
->definitions
[0] = Definition(tmp_dst
);
8607 tex
->can_reorder
= true;
8608 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8611 /* divide 3rd value by 6 by multiplying with magic number */
8612 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8613 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8614 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8615 assert(instr
->dest
.ssa
.num_components
== 3);
8616 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8617 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8618 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8619 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8624 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8628 Temp tg4_compare_cube_wa64
= Temp();
8630 if (tg4_integer_workarounds
) {
8631 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8632 tex
->operands
[0] = Operand(resource
);
8633 tex
->operands
[1] = Operand(s4
); /* no sampler */
8634 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8638 Temp size
= bld
.tmp(v2
);
8639 tex
->definitions
[0] = Definition(size
);
8640 tex
->can_reorder
= true;
8641 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8642 emit_split_vector(ctx
, size
, size
.size());
8645 for (unsigned i
= 0; i
< 2; i
++) {
8646 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8647 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8648 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8649 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8652 Temp new_coords
[2] = {
8653 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8654 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8657 if (tg4_integer_cube_workaround
) {
8658 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8659 Temp desc
[resource
.size()];
8660 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8661 Format::PSEUDO
, 1, resource
.size())};
8662 split
->operands
[0] = Operand(resource
);
8663 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8664 desc
[i
] = bld
.tmp(s1
);
8665 split
->definitions
[i
] = Definition(desc
[i
]);
8667 ctx
->block
->instructions
.emplace_back(std::move(split
));
8669 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8670 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8671 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8674 if (stype
== GLSL_TYPE_UINT
) {
8675 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8676 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8677 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8678 bld
.scc(compare_cube_wa
));
8680 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8681 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8682 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8683 bld
.scc(compare_cube_wa
));
8685 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8686 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8688 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8690 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8691 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8692 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8694 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8695 Format::PSEUDO
, resource
.size(), 1)};
8696 for (unsigned i
= 0; i
< resource
.size(); i
++)
8697 vec
->operands
[i
] = Operand(desc
[i
]);
8698 resource
= bld
.tmp(resource
.regClass());
8699 vec
->definitions
[0] = Definition(resource
);
8700 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8702 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8703 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8704 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8705 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8707 coords
[0] = new_coords
[0];
8708 coords
[1] = new_coords
[1];
8711 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8712 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8714 assert(coords
.size() == 1);
8715 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8719 op
= aco_opcode::buffer_load_format_x
; break;
8721 op
= aco_opcode::buffer_load_format_xy
; break;
8723 op
= aco_opcode::buffer_load_format_xyz
; break;
8725 op
= aco_opcode::buffer_load_format_xyzw
; break;
8727 unreachable("Tex instruction loads more than 4 components.");
8730 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8731 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8734 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8736 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8737 mubuf
->operands
[0] = Operand(resource
);
8738 mubuf
->operands
[1] = Operand(coords
[0]);
8739 mubuf
->operands
[2] = Operand((uint32_t) 0);
8740 mubuf
->definitions
[0] = Definition(tmp_dst
);
8741 mubuf
->idxen
= true;
8742 mubuf
->can_reorder
= true;
8743 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8745 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8749 /* gather MIMG address components */
8750 std::vector
<Temp
> args
;
8752 args
.emplace_back(offset
);
8754 args
.emplace_back(bias
);
8756 args
.emplace_back(compare
);
8758 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8760 args
.insert(args
.end(), coords
.begin(), coords
.end());
8761 if (has_sample_index
)
8762 args
.emplace_back(sample_index
);
8764 args
.emplace_back(lod
);
8766 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8767 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8768 vec
->definitions
[0] = Definition(arg
);
8769 for (unsigned i
= 0; i
< args
.size(); i
++)
8770 vec
->operands
[i
] = Operand(args
[i
]);
8771 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8774 if (instr
->op
== nir_texop_txf
||
8775 instr
->op
== nir_texop_txf_ms
||
8776 instr
->op
== nir_texop_samples_identical
||
8777 instr
->op
== nir_texop_fragment_fetch
||
8778 instr
->op
== nir_texop_fragment_mask_fetch
) {
8779 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8780 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8781 tex
->operands
[0] = Operand(resource
);
8782 tex
->operands
[1] = Operand(s4
); /* no sampler */
8783 tex
->operands
[2] = Operand(arg
);
8788 tex
->definitions
[0] = Definition(tmp_dst
);
8789 tex
->can_reorder
= true;
8790 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8792 if (instr
->op
== nir_texop_samples_identical
) {
8793 assert(dmask
== 1 && dst
.regClass() == v1
);
8794 assert(dst
.id() != tmp_dst
.id());
8796 Temp tmp
= bld
.tmp(bld
.lm
);
8797 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8798 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8801 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8806 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8807 aco_opcode opcode
= aco_opcode::image_sample
;
8808 if (has_offset
) { /* image_sample_*_o */
8810 opcode
= aco_opcode::image_sample_c_o
;
8812 opcode
= aco_opcode::image_sample_c_d_o
;
8814 opcode
= aco_opcode::image_sample_c_b_o
;
8816 opcode
= aco_opcode::image_sample_c_lz_o
;
8818 opcode
= aco_opcode::image_sample_c_l_o
;
8820 opcode
= aco_opcode::image_sample_o
;
8822 opcode
= aco_opcode::image_sample_d_o
;
8824 opcode
= aco_opcode::image_sample_b_o
;
8826 opcode
= aco_opcode::image_sample_lz_o
;
8828 opcode
= aco_opcode::image_sample_l_o
;
8830 } else { /* no offset */
8832 opcode
= aco_opcode::image_sample_c
;
8834 opcode
= aco_opcode::image_sample_c_d
;
8836 opcode
= aco_opcode::image_sample_c_b
;
8838 opcode
= aco_opcode::image_sample_c_lz
;
8840 opcode
= aco_opcode::image_sample_c_l
;
8842 opcode
= aco_opcode::image_sample
;
8844 opcode
= aco_opcode::image_sample_d
;
8846 opcode
= aco_opcode::image_sample_b
;
8848 opcode
= aco_opcode::image_sample_lz
;
8850 opcode
= aco_opcode::image_sample_l
;
8854 if (instr
->op
== nir_texop_tg4
) {
8856 opcode
= aco_opcode::image_gather4_lz_o
;
8858 opcode
= aco_opcode::image_gather4_c_lz_o
;
8860 opcode
= aco_opcode::image_gather4_lz
;
8862 opcode
= aco_opcode::image_gather4_c_lz
;
8864 } else if (instr
->op
== nir_texop_lod
) {
8865 opcode
= aco_opcode::image_get_lod
;
8868 /* we don't need the bias, sample index, compare value or offset to be
8869 * computed in WQM but if the p_create_vector copies the coordinates, then it
8870 * needs to be in WQM */
8871 if (ctx
->stage
== fragment_fs
&&
8872 !has_derivs
&& !has_lod
&& !level_zero
&&
8873 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8874 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8875 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8877 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8878 tex
->operands
[0] = Operand(resource
);
8879 tex
->operands
[1] = Operand(sampler
);
8880 tex
->operands
[2] = Operand(arg
);
8884 tex
->definitions
[0] = Definition(tmp_dst
);
8885 tex
->can_reorder
= true;
8886 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8888 if (tg4_integer_cube_workaround
) {
8889 assert(tmp_dst
.id() != dst
.id());
8890 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8892 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8894 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8895 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8897 if (stype
== GLSL_TYPE_UINT
)
8898 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8900 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8901 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8903 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8904 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8905 val
[0], val
[1], val
[2], val
[3]);
8907 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8908 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8913 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
)
8915 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8916 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
)
8917 return Operand(tmp
.regClass());
8919 return Operand(tmp
);
8922 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8924 aco_ptr
<Pseudo_instruction
> phi
;
8925 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8926 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8928 bool logical
= !dst
.is_linear() || ctx
->divergent_vals
[instr
->dest
.ssa
.index
];
8929 logical
|= ctx
->block
->kind
& block_kind_merge
;
8930 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8932 /* we want a sorted list of sources, since the predecessor list is also sorted */
8933 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8934 nir_foreach_phi_src(src
, instr
)
8935 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8937 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8938 unsigned num_operands
= 0;
8939 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8940 unsigned num_defined
= 0;
8941 unsigned cur_pred_idx
= 0;
8942 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8943 if (cur_pred_idx
< preds
.size()) {
8944 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8945 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8946 unsigned skipped
= 0;
8947 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8949 if (cur_pred_idx
+ skipped
< preds
.size()) {
8950 for (unsigned i
= 0; i
< skipped
; i
++)
8951 operands
[num_operands
++] = Operand(dst
.regClass());
8952 cur_pred_idx
+= skipped
;
8957 /* Handle missing predecessors at the end. This shouldn't happen with loop
8958 * headers and we can't ignore these sources for loop header phis. */
8959 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8962 Operand op
= get_phi_operand(ctx
, src
.second
);
8963 operands
[num_operands
++] = op
;
8964 num_defined
+= !op
.isUndefined();
8966 /* handle block_kind_continue_or_break at loop exit blocks */
8967 while (cur_pred_idx
++ < preds
.size())
8968 operands
[num_operands
++] = Operand(dst
.regClass());
8970 /* If the loop ends with a break, still add a linear continue edge in case
8971 * that break is divergent or continue_or_break is used. We'll either remove
8972 * this operand later in visit_loop() if it's not necessary or replace the
8973 * undef with something correct. */
8974 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8975 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8976 nir_block
*last
= nir_loop_last_block(loop
);
8977 if (last
->successors
[0] != instr
->instr
.block
)
8978 operands
[num_operands
++] = Operand(RegClass());
8981 if (num_defined
== 0) {
8982 Builder
bld(ctx
->program
, ctx
->block
);
8983 if (dst
.regClass() == s1
) {
8984 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8985 } else if (dst
.regClass() == v1
) {
8986 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8988 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8989 for (unsigned i
= 0; i
< dst
.size(); i
++)
8990 vec
->operands
[i
] = Operand(0u);
8991 vec
->definitions
[0] = Definition(dst
);
8992 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8997 /* we can use a linear phi in some cases if one src is undef */
8998 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8999 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
9001 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
9002 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
9003 assert(invert
->kind
& block_kind_invert
);
9005 unsigned then_block
= invert
->linear_preds
[0];
9007 Block
* insert_block
= NULL
;
9008 for (unsigned i
= 0; i
< num_operands
; i
++) {
9009 Operand op
= operands
[i
];
9010 if (op
.isUndefined())
9012 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
9013 phi
->operands
[0] = op
;
9016 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
9017 phi
->operands
[1] = Operand(dst
.regClass());
9018 phi
->definitions
[0] = Definition(dst
);
9019 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
9023 /* try to scalarize vector phis */
9024 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
9025 // TODO: scalarize linear phis on divergent ifs
9026 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
9027 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
9028 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
9029 Operand src
= operands
[i
];
9030 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
9031 can_scalarize
= false;
9033 if (can_scalarize
) {
9034 unsigned num_components
= instr
->dest
.ssa
.num_components
;
9035 assert(dst
.size() % num_components
== 0);
9036 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
9038 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
9039 for (unsigned k
= 0; k
< num_components
; k
++) {
9040 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9041 for (unsigned i
= 0; i
< num_operands
; i
++) {
9042 Operand src
= operands
[i
];
9043 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9045 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9046 phi
->definitions
[0] = Definition(phi_dst
);
9047 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9048 new_vec
[k
] = phi_dst
;
9049 vec
->operands
[k
] = Operand(phi_dst
);
9051 vec
->definitions
[0] = Definition(dst
);
9052 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9053 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9058 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9059 for (unsigned i
= 0; i
< num_operands
; i
++)
9060 phi
->operands
[i
] = operands
[i
];
9061 phi
->definitions
[0] = Definition(dst
);
9062 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9066 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9068 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9070 assert(dst
.type() == RegType::sgpr
);
9072 if (dst
.size() == 1) {
9073 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9075 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9076 for (unsigned i
= 0; i
< dst
.size(); i
++)
9077 vec
->operands
[i
] = Operand(0u);
9078 vec
->definitions
[0] = Definition(dst
);
9079 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9083 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9085 Builder
bld(ctx
->program
, ctx
->block
);
9086 Block
*logical_target
;
9087 append_logical_end(ctx
->block
);
9088 unsigned idx
= ctx
->block
->index
;
9090 switch (instr
->type
) {
9091 case nir_jump_break
:
9092 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9093 add_logical_edge(idx
, logical_target
);
9094 ctx
->block
->kind
|= block_kind_break
;
9096 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9097 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9098 /* uniform break - directly jump out of the loop */
9099 ctx
->block
->kind
|= block_kind_uniform
;
9100 ctx
->cf_info
.has_branch
= true;
9101 bld
.branch(aco_opcode::p_branch
);
9102 add_linear_edge(idx
, logical_target
);
9105 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9106 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9108 case nir_jump_continue
:
9109 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9110 add_logical_edge(idx
, logical_target
);
9111 ctx
->block
->kind
|= block_kind_continue
;
9113 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9114 /* for potential uniform breaks after this continue,
9115 we must ensure that they are handled correctly */
9116 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9117 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9118 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9120 /* uniform continue - directly jump to the loop header */
9121 ctx
->block
->kind
|= block_kind_uniform
;
9122 ctx
->cf_info
.has_branch
= true;
9123 bld
.branch(aco_opcode::p_branch
);
9124 add_linear_edge(idx
, logical_target
);
9129 fprintf(stderr
, "Unknown NIR jump instr: ");
9130 nir_print_instr(&instr
->instr
, stderr
);
9131 fprintf(stderr
, "\n");
9135 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9136 ctx
->cf_info
.exec_potentially_empty_break
= true;
9137 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9140 /* remove critical edges from linear CFG */
9141 bld
.branch(aco_opcode::p_branch
);
9142 Block
* break_block
= ctx
->program
->create_and_insert_block();
9143 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9144 break_block
->kind
|= block_kind_uniform
;
9145 add_linear_edge(idx
, break_block
);
9146 /* the loop_header pointer might be invalidated by this point */
9147 if (instr
->type
== nir_jump_continue
)
9148 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9149 add_linear_edge(break_block
->index
, logical_target
);
9150 bld
.reset(break_block
);
9151 bld
.branch(aco_opcode::p_branch
);
9153 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9154 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9155 add_linear_edge(idx
, continue_block
);
9156 append_logical_start(continue_block
);
9157 ctx
->block
= continue_block
;
9161 void visit_block(isel_context
*ctx
, nir_block
*block
)
9163 nir_foreach_instr(instr
, block
) {
9164 switch (instr
->type
) {
9165 case nir_instr_type_alu
:
9166 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9168 case nir_instr_type_load_const
:
9169 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9171 case nir_instr_type_intrinsic
:
9172 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9174 case nir_instr_type_tex
:
9175 visit_tex(ctx
, nir_instr_as_tex(instr
));
9177 case nir_instr_type_phi
:
9178 visit_phi(ctx
, nir_instr_as_phi(instr
));
9180 case nir_instr_type_ssa_undef
:
9181 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9183 case nir_instr_type_deref
:
9185 case nir_instr_type_jump
:
9186 visit_jump(ctx
, nir_instr_as_jump(instr
));
9189 fprintf(stderr
, "Unknown NIR instr type: ");
9190 nir_print_instr(instr
, stderr
);
9191 fprintf(stderr
, "\n");
9196 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9197 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9202 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9203 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9205 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9206 RegClass rc
= vals
[0].regClass();
9208 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9210 unsigned next_pred
= 1;
9212 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9213 Block
& block
= ctx
->program
->blocks
[idx
];
9214 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9215 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9219 if (block
.kind
& block_kind_continue
) {
9220 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9225 bool all_same
= true;
9226 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9227 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9231 val
= vals
[block
.linear_preds
[0] - first
];
9233 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9234 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9235 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9236 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9237 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9238 phi
->definitions
[0] = Definition(val
.getTemp());
9239 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9241 vals
[idx
- first
] = val
;
9244 return vals
[last
- first
];
9247 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9249 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9250 append_logical_end(ctx
->block
);
9251 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9252 Builder
bld(ctx
->program
, ctx
->block
);
9253 bld
.branch(aco_opcode::p_branch
);
9254 unsigned loop_preheader_idx
= ctx
->block
->index
;
9256 Block loop_exit
= Block();
9257 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9258 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9260 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9261 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9262 loop_header
->kind
|= block_kind_loop_header
;
9263 add_edge(loop_preheader_idx
, loop_header
);
9264 ctx
->block
= loop_header
;
9266 /* emit loop body */
9267 unsigned loop_header_idx
= loop_header
->index
;
9268 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9269 append_logical_start(ctx
->block
);
9270 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9272 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9273 if (!ctx
->cf_info
.has_branch
) {
9274 append_logical_end(ctx
->block
);
9275 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9276 /* Discards can result in code running with an empty exec mask.
9277 * This would result in divergent breaks not ever being taken. As a
9278 * workaround, break the loop when the loop mask is empty instead of
9279 * always continuing. */
9280 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9281 unsigned block_idx
= ctx
->block
->index
;
9283 /* create helper blocks to avoid critical edges */
9284 Block
*break_block
= ctx
->program
->create_and_insert_block();
9285 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9286 break_block
->kind
= block_kind_uniform
;
9287 bld
.reset(break_block
);
9288 bld
.branch(aco_opcode::p_branch
);
9289 add_linear_edge(block_idx
, break_block
);
9290 add_linear_edge(break_block
->index
, &loop_exit
);
9292 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9293 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9294 continue_block
->kind
= block_kind_uniform
;
9295 bld
.reset(continue_block
);
9296 bld
.branch(aco_opcode::p_branch
);
9297 add_linear_edge(block_idx
, continue_block
);
9298 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9300 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9301 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9302 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9304 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9305 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9306 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9308 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9311 bld
.reset(ctx
->block
);
9312 bld
.branch(aco_opcode::p_branch
);
9315 /* Fixup phis in loop header from unreachable blocks.
9316 * has_branch/has_divergent_branch also indicates if the loop ends with a
9317 * break/continue instruction, but we don't emit those if unreachable=true */
9319 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9320 bool linear
= ctx
->cf_info
.has_branch
;
9321 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9322 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9323 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9324 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9325 /* the last operand should be the one that needs to be removed */
9326 instr
->operands
.pop_back();
9327 } else if (!is_phi(instr
)) {
9333 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9334 * and the previous one shouldn't both happen at once because a break in the
9335 * merge block would get CSE'd */
9336 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9337 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9338 Operand vals
[num_vals
];
9339 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9340 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9341 if (ctx
->cf_info
.has_branch
)
9342 instr
->operands
.pop_back();
9344 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9345 } else if (!is_phi(instr
)) {
9351 ctx
->cf_info
.has_branch
= false;
9353 // TODO: if the loop has not a single exit, we must add one °°
9354 /* emit loop successor block */
9355 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9356 append_logical_start(ctx
->block
);
9359 // TODO: check if it is beneficial to not branch on continues
9360 /* trim linear phis in loop header */
9361 for (auto&& instr
: loop_entry
->instructions
) {
9362 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9363 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9364 new_phi
->definitions
[0] = instr
->definitions
[0];
9365 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9366 new_phi
->operands
[i
] = instr
->operands
[i
];
9367 /* check that the remaining operands are all the same */
9368 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9369 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9370 instr
.swap(new_phi
);
9371 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9380 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9384 append_logical_end(ctx
->block
);
9385 ctx
->block
->kind
|= block_kind_branch
;
9387 /* branch to linear then block */
9388 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9389 aco_ptr
<Pseudo_branch_instruction
> branch
;
9390 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 0));
9391 branch
->operands
[0] = Operand(cond
);
9392 ctx
->block
->instructions
.push_back(std::move(branch
));
9394 ic
->BB_if_idx
= ctx
->block
->index
;
9395 ic
->BB_invert
= Block();
9396 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9397 /* Invert blocks are intentionally not marked as top level because they
9398 * are not part of the logical cfg. */
9399 ic
->BB_invert
.kind
|= block_kind_invert
;
9400 ic
->BB_endif
= Block();
9401 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9402 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9404 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9405 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9406 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9407 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9408 ctx
->cf_info
.parent_if
.is_divergent
= true;
9410 /* divergent branches use cbranch_execz */
9411 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9412 ctx
->cf_info
.exec_potentially_empty_break
= false;
9413 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9415 /** emit logical then block */
9416 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9417 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9418 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9419 ctx
->block
= BB_then_logical
;
9420 append_logical_start(BB_then_logical
);
9423 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9425 Block
*BB_then_logical
= ctx
->block
;
9426 append_logical_end(BB_then_logical
);
9427 /* branch from logical then block to invert block */
9428 aco_ptr
<Pseudo_branch_instruction
> branch
;
9429 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9430 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9431 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9432 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9433 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9434 BB_then_logical
->kind
|= block_kind_uniform
;
9435 assert(!ctx
->cf_info
.has_branch
);
9436 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9437 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9439 /** emit linear then block */
9440 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9441 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9442 BB_then_linear
->kind
|= block_kind_uniform
;
9443 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9444 /* branch from linear then block to invert block */
9445 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9446 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9447 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9449 /** emit invert merge block */
9450 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9451 ic
->invert_idx
= ctx
->block
->index
;
9453 /* branch to linear else block (skip else) */
9454 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 0));
9455 branch
->operands
[0] = Operand(ic
->cond
);
9456 ctx
->block
->instructions
.push_back(std::move(branch
));
9458 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9459 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9460 ic
->exec_potentially_empty_break_depth_old
=
9461 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9462 /* divergent branches use cbranch_execz */
9463 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9464 ctx
->cf_info
.exec_potentially_empty_break
= false;
9465 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9467 /** emit logical else block */
9468 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9469 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9470 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9471 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9472 ctx
->block
= BB_else_logical
;
9473 append_logical_start(BB_else_logical
);
9476 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9478 Block
*BB_else_logical
= ctx
->block
;
9479 append_logical_end(BB_else_logical
);
9481 /* branch from logical else block to endif block */
9482 aco_ptr
<Pseudo_branch_instruction
> branch
;
9483 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9484 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9485 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9486 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9487 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9488 BB_else_logical
->kind
|= block_kind_uniform
;
9490 assert(!ctx
->cf_info
.has_branch
);
9491 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9494 /** emit linear else block */
9495 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9496 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9497 BB_else_linear
->kind
|= block_kind_uniform
;
9498 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9500 /* branch from linear else block to endif block */
9501 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9502 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9503 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9506 /** emit endif merge block */
9507 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9508 append_logical_start(ctx
->block
);
9511 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9512 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9513 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9514 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9515 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9516 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9517 !ctx
->cf_info
.parent_if
.is_divergent
) {
9518 ctx
->cf_info
.exec_potentially_empty_break
= false;
9519 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9521 /* uniform control flow never has an empty exec-mask */
9522 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9523 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9524 ctx
->cf_info
.exec_potentially_empty_break
= false;
9525 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9529 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9531 assert(cond
.regClass() == s1
);
9533 append_logical_end(ctx
->block
);
9534 ctx
->block
->kind
|= block_kind_uniform
;
9536 aco_ptr
<Pseudo_branch_instruction
> branch
;
9537 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9538 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 0));
9539 branch
->operands
[0] = Operand(cond
);
9540 branch
->operands
[0].setFixed(scc
);
9541 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9543 ic
->BB_if_idx
= ctx
->block
->index
;
9544 ic
->BB_endif
= Block();
9545 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9546 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9548 ctx
->cf_info
.has_branch
= false;
9549 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9551 /** emit then block */
9552 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9553 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9554 add_edge(ic
->BB_if_idx
, BB_then
);
9555 append_logical_start(BB_then
);
9556 ctx
->block
= BB_then
;
9559 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9561 Block
*BB_then
= ctx
->block
;
9563 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9564 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9566 if (!ic
->uniform_has_then_branch
) {
9567 append_logical_end(BB_then
);
9568 /* branch from then block to endif block */
9569 aco_ptr
<Pseudo_branch_instruction
> branch
;
9570 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9571 BB_then
->instructions
.emplace_back(std::move(branch
));
9572 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9573 if (!ic
->then_branch_divergent
)
9574 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9575 BB_then
->kind
|= block_kind_uniform
;
9578 ctx
->cf_info
.has_branch
= false;
9579 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9581 /** emit else block */
9582 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9583 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9584 add_edge(ic
->BB_if_idx
, BB_else
);
9585 append_logical_start(BB_else
);
9586 ctx
->block
= BB_else
;
9589 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9591 Block
*BB_else
= ctx
->block
;
9593 if (!ctx
->cf_info
.has_branch
) {
9594 append_logical_end(BB_else
);
9595 /* branch from then block to endif block */
9596 aco_ptr
<Pseudo_branch_instruction
> branch
;
9597 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 0));
9598 BB_else
->instructions
.emplace_back(std::move(branch
));
9599 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9600 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9601 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9602 BB_else
->kind
|= block_kind_uniform
;
9605 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9606 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9608 /** emit endif merge block */
9609 if (!ctx
->cf_info
.has_branch
) {
9610 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9611 append_logical_start(ctx
->block
);
9615 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9617 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9618 Builder
bld(ctx
->program
, ctx
->block
);
9619 aco_ptr
<Pseudo_branch_instruction
> branch
;
9622 if (!ctx
->divergent_vals
[if_stmt
->condition
.ssa
->index
]) { /* uniform condition */
9624 * Uniform conditionals are represented in the following way*) :
9626 * The linear and logical CFG:
9629 * BB_THEN (logical) BB_ELSE (logical)
9633 * *) Exceptions may be due to break and continue statements within loops
9634 * If a break/continue happens within uniform control flow, it branches
9635 * to the loop exit/entry block. Otherwise, it branches to the next
9639 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9640 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9641 cond
= bool_to_scalar_condition(ctx
, cond
);
9643 begin_uniform_if_then(ctx
, &ic
, cond
);
9644 visit_cf_list(ctx
, &if_stmt
->then_list
);
9646 begin_uniform_if_else(ctx
, &ic
);
9647 visit_cf_list(ctx
, &if_stmt
->else_list
);
9649 end_uniform_if(ctx
, &ic
);
9651 return !ctx
->cf_info
.has_branch
;
9652 } else { /* non-uniform condition */
9654 * To maintain a logical and linear CFG without critical edges,
9655 * non-uniform conditionals are represented in the following way*) :
9660 * BB_THEN (logical) BB_THEN (linear)
9662 * BB_INVERT (linear)
9664 * BB_ELSE (logical) BB_ELSE (linear)
9671 * BB_THEN (logical) BB_ELSE (logical)
9675 * *) Exceptions may be due to break and continue statements within loops
9678 begin_divergent_if_then(ctx
, &ic
, cond
);
9679 visit_cf_list(ctx
, &if_stmt
->then_list
);
9681 begin_divergent_if_else(ctx
, &ic
);
9682 visit_cf_list(ctx
, &if_stmt
->else_list
);
9684 end_divergent_if(ctx
, &ic
);
9690 static bool visit_cf_list(isel_context
*ctx
,
9691 struct exec_list
*list
)
9693 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9694 switch (node
->type
) {
9695 case nir_cf_node_block
:
9696 visit_block(ctx
, nir_cf_node_as_block(node
));
9698 case nir_cf_node_if
:
9699 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9702 case nir_cf_node_loop
:
9703 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9706 unreachable("unimplemented cf list type");
9712 static void create_null_export(isel_context
*ctx
)
9714 /* Some shader stages always need to have exports.
9715 * So when there is none, we need to add a null export.
9718 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9719 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9720 Builder
bld(ctx
->program
, ctx
->block
);
9721 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9722 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9725 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9727 assert(ctx
->stage
== vertex_vs
||
9728 ctx
->stage
== tess_eval_vs
||
9729 ctx
->stage
== gs_copy_vs
||
9730 ctx
->stage
== ngg_vertex_gs
||
9731 ctx
->stage
== ngg_tess_eval_gs
);
9733 int offset
= (ctx
->stage
& sw_tes
)
9734 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9735 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9736 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9737 if (!is_pos
&& !mask
)
9739 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9741 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9742 exp
->enabled_mask
= mask
;
9743 for (unsigned i
= 0; i
< 4; ++i
) {
9744 if (mask
& (1 << i
))
9745 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9747 exp
->operands
[i
] = Operand(v1
);
9749 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9750 * Setting valid_mask=1 prevents it and has no other effect.
9752 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& is_pos
&& *next_pos
== 0;
9754 exp
->compressed
= false;
9756 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9758 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9759 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9764 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9766 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9767 exp
->enabled_mask
= 0;
9768 for (unsigned i
= 0; i
< 4; ++i
)
9769 exp
->operands
[i
] = Operand(v1
);
9770 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9771 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9772 exp
->enabled_mask
|= 0x1;
9774 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9775 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9776 exp
->enabled_mask
|= 0x4;
9778 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9779 if (ctx
->options
->chip_class
< GFX9
) {
9780 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9781 exp
->enabled_mask
|= 0x8;
9783 Builder
bld(ctx
->program
, ctx
->block
);
9785 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9786 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9787 if (exp
->operands
[2].isTemp())
9788 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9790 exp
->operands
[2] = Operand(out
);
9791 exp
->enabled_mask
|= 0x4;
9794 exp
->valid_mask
= ctx
->options
->chip_class
>= GFX10
&& *next_pos
== 0;
9796 exp
->compressed
= false;
9797 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9798 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9801 static void create_export_phis(isel_context
*ctx
)
9803 /* Used when exports are needed, but the output temps are defined in a preceding block.
9804 * This function will set up phis in order to access the outputs in the next block.
9807 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9808 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9809 ctx
->block
->instructions
.pop_back();
9811 Builder
bld(ctx
->program
, ctx
->block
);
9813 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9814 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9815 for (unsigned i
= 0; i
< 4; ++i
) {
9816 if (!(mask
& (1 << i
)))
9819 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9820 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9821 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9825 bld
.insert(std::move(logical_start
));
9828 static void create_vs_exports(isel_context
*ctx
)
9830 assert(ctx
->stage
== vertex_vs
||
9831 ctx
->stage
== tess_eval_vs
||
9832 ctx
->stage
== gs_copy_vs
||
9833 ctx
->stage
== ngg_vertex_gs
||
9834 ctx
->stage
== ngg_tess_eval_gs
);
9836 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9837 ? &ctx
->program
->info
->tes
.outinfo
9838 : &ctx
->program
->info
->vs
.outinfo
;
9840 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9841 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9842 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9845 if (ctx
->options
->key
.has_multiview_view_index
) {
9846 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9847 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9850 /* the order these position exports are created is important */
9852 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9853 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9854 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9855 exported_pos
= true;
9857 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9858 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9859 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9860 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9862 if (ctx
->export_clip_dists
) {
9863 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9864 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9865 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9866 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9869 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9870 if (i
< VARYING_SLOT_VAR0
&&
9871 i
!= VARYING_SLOT_LAYER
&&
9872 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9873 i
!= VARYING_SLOT_VIEWPORT
)
9876 export_vs_varying(ctx
, i
, false, NULL
);
9880 create_null_export(ctx
);
9883 static bool export_fs_mrt_z(isel_context
*ctx
)
9885 Builder
bld(ctx
->program
, ctx
->block
);
9886 unsigned enabled_channels
= 0;
9890 for (unsigned i
= 0; i
< 4; ++i
) {
9891 values
[i
] = Operand(v1
);
9894 /* Both stencil and sample mask only need 16-bits. */
9895 if (!ctx
->program
->info
->ps
.writes_z
&&
9896 (ctx
->program
->info
->ps
.writes_stencil
||
9897 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9898 compr
= true; /* COMPR flag */
9900 if (ctx
->program
->info
->ps
.writes_stencil
) {
9901 /* Stencil should be in X[23:16]. */
9902 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9903 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9904 enabled_channels
|= 0x3;
9907 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9908 /* SampleMask should be in Y[15:0]. */
9909 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9910 enabled_channels
|= 0xc;
9913 if (ctx
->program
->info
->ps
.writes_z
) {
9914 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9915 enabled_channels
|= 0x1;
9918 if (ctx
->program
->info
->ps
.writes_stencil
) {
9919 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9920 enabled_channels
|= 0x2;
9923 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9924 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9925 enabled_channels
|= 0x4;
9929 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9930 * writemask component.
9932 if (ctx
->options
->chip_class
== GFX6
&&
9933 ctx
->options
->family
!= CHIP_OLAND
&&
9934 ctx
->options
->family
!= CHIP_HAINAN
) {
9935 enabled_channels
|= 0x1;
9938 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9939 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9944 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9946 Builder
bld(ctx
->program
, ctx
->block
);
9947 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9950 for (unsigned i
= 0; i
< 4; ++i
) {
9951 if (write_mask
& (1 << i
)) {
9952 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9954 values
[i
] = Operand(v1
);
9958 unsigned target
, col_format
;
9959 unsigned enabled_channels
= 0;
9960 aco_opcode compr_op
= (aco_opcode
)0;
9962 slot
-= FRAG_RESULT_DATA0
;
9963 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9964 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9966 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9967 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9971 case V_028714_SPI_SHADER_ZERO
:
9972 enabled_channels
= 0; /* writemask */
9973 target
= V_008DFC_SQ_EXP_NULL
;
9976 case V_028714_SPI_SHADER_32_R
:
9977 enabled_channels
= 1;
9980 case V_028714_SPI_SHADER_32_GR
:
9981 enabled_channels
= 0x3;
9984 case V_028714_SPI_SHADER_32_AR
:
9985 if (ctx
->options
->chip_class
>= GFX10
) {
9986 /* Special case: on GFX10, the outputs are different for 32_AR */
9987 enabled_channels
= 0x3;
9988 values
[1] = values
[3];
9989 values
[3] = Operand(v1
);
9991 enabled_channels
= 0x9;
9995 case V_028714_SPI_SHADER_FP16_ABGR
:
9996 enabled_channels
= 0x5;
9997 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
10000 case V_028714_SPI_SHADER_UNORM16_ABGR
:
10001 enabled_channels
= 0x5;
10002 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
10005 case V_028714_SPI_SHADER_SNORM16_ABGR
:
10006 enabled_channels
= 0x5;
10007 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10010 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10011 enabled_channels
= 0x5;
10012 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10013 if (is_int8
|| is_int10
) {
10015 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10016 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10018 for (unsigned i
= 0; i
< 4; i
++) {
10019 if ((write_mask
>> i
) & 1) {
10020 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10021 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10029 case V_028714_SPI_SHADER_SINT16_ABGR
:
10030 enabled_channels
= 0x5;
10031 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10032 if (is_int8
|| is_int10
) {
10034 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10035 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10036 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10037 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10039 for (unsigned i
= 0; i
< 4; i
++) {
10040 if ((write_mask
>> i
) & 1) {
10041 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10042 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10044 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10045 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10052 case V_028714_SPI_SHADER_32_ABGR
:
10053 enabled_channels
= 0xF;
10060 if (target
== V_008DFC_SQ_EXP_NULL
)
10063 if ((bool) compr_op
) {
10064 for (int i
= 0; i
< 2; i
++) {
10065 /* check if at least one of the values to be compressed is enabled */
10066 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10068 enabled_channels
|= enabled
<< (i
*2);
10069 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10070 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10071 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10073 values
[i
] = Operand(v1
);
10076 values
[2] = Operand(v1
);
10077 values
[3] = Operand(v1
);
10079 for (int i
= 0; i
< 4; i
++)
10080 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10083 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10084 enabled_channels
, target
, (bool) compr_op
);
10088 static void create_fs_exports(isel_context
*ctx
)
10090 bool exported
= false;
10092 /* Export depth, stencil and sample mask. */
10093 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10094 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10095 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10096 exported
|= export_fs_mrt_z(ctx
);
10098 /* Export all color render targets. */
10099 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10100 if (ctx
->outputs
.mask
[i
])
10101 exported
|= export_fs_mrt_color(ctx
, i
);
10104 create_null_export(ctx
);
10107 static void write_tcs_tess_factors(isel_context
*ctx
)
10109 unsigned outer_comps
;
10110 unsigned inner_comps
;
10112 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10129 Builder
bld(ctx
->program
, ctx
->block
);
10131 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10132 if (unlikely(ctx
->program
->chip_class
!= GFX6
&& ctx
->program
->workgroup_size
> ctx
->program
->wave_size
))
10133 bld
.sopp(aco_opcode::s_barrier
);
10135 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10136 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10138 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10139 if_context ic_invocation_id_is_zero
;
10140 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10141 bld
.reset(ctx
->block
);
10143 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10145 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10146 unsigned stride
= inner_comps
+ outer_comps
;
10147 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10151 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10153 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10155 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10156 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10157 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10159 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10160 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10162 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10163 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10164 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10165 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10168 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10169 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10170 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10171 unsigned tf_const_offset
= 0;
10173 if (ctx
->program
->chip_class
<= GFX8
) {
10174 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10175 if_context ic_rel_patch_id_is_zero
;
10176 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10177 bld
.reset(ctx
->block
);
10179 /* Store the dynamic HS control word. */
10180 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10181 bld
.mubuf(aco_opcode::buffer_store_dword
,
10182 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10183 /* immediate OFFSET */ 0, /* OFFEN */ false, /* idxen*/ false, /* addr64 */ false,
10184 /* disable_wqm */ false, /* glc */ true);
10185 tf_const_offset
+= 4;
10187 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10188 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10189 bld
.reset(ctx
->block
);
10192 assert(stride
== 2 || stride
== 4 || stride
== 6);
10193 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10194 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, false);
10196 /* Store to offchip for TES to read - only if TES reads them */
10197 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10198 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10199 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10201 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10202 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, false);
10204 if (likely(inner_comps
)) {
10205 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10206 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, false);
10210 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10211 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10214 static void emit_stream_output(isel_context
*ctx
,
10215 Temp
const *so_buffers
,
10216 Temp
const *so_write_offset
,
10217 const struct radv_stream_output
*output
)
10219 unsigned num_comps
= util_bitcount(output
->component_mask
);
10220 unsigned writemask
= (1 << num_comps
) - 1;
10221 unsigned loc
= output
->location
;
10222 unsigned buf
= output
->buffer
;
10224 assert(num_comps
&& num_comps
<= 4);
10225 if (!num_comps
|| num_comps
> 4)
10228 unsigned start
= ffs(output
->component_mask
) - 1;
10231 bool all_undef
= true;
10232 assert(ctx
->stage
& hw_vs
);
10233 for (unsigned i
= 0; i
< num_comps
; i
++) {
10234 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10235 all_undef
= all_undef
&& !out
[i
].id();
10240 while (writemask
) {
10242 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10243 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10244 /* GFX6 doesn't support storing vec3, split it. */
10245 writemask
|= 1u << (start
+ 2);
10249 unsigned offset
= output
->offset
+ start
* 4;
10251 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10252 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10253 for (int i
= 0; i
< count
; ++i
)
10254 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10255 vec
->definitions
[0] = Definition(write_data
);
10256 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10261 opcode
= aco_opcode::buffer_store_dword
;
10264 opcode
= aco_opcode::buffer_store_dwordx2
;
10267 opcode
= aco_opcode::buffer_store_dwordx3
;
10270 opcode
= aco_opcode::buffer_store_dwordx4
;
10273 unreachable("Unsupported dword count.");
10276 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10277 store
->operands
[0] = Operand(so_buffers
[buf
]);
10278 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10279 store
->operands
[2] = Operand((uint32_t) 0);
10280 store
->operands
[3] = Operand(write_data
);
10281 if (offset
> 4095) {
10282 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10283 Builder
bld(ctx
->program
, ctx
->block
);
10284 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10286 store
->offset
= offset
;
10288 store
->offen
= true;
10290 store
->dlc
= false;
10292 store
->can_reorder
= true;
10293 ctx
->block
->instructions
.emplace_back(std::move(store
));
10297 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10299 Builder
bld(ctx
->program
, ctx
->block
);
10301 Temp so_buffers
[4];
10302 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10303 for (unsigned i
= 0; i
< 4; i
++) {
10304 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10308 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10309 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10312 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10313 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10315 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10317 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10320 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10322 bld
.reset(ctx
->block
);
10324 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10326 Temp so_write_offset
[4];
10328 for (unsigned i
= 0; i
< 4; i
++) {
10329 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10334 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10335 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10336 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10337 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10339 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10341 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10342 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10343 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10344 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10348 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10349 struct radv_stream_output
*output
=
10350 &ctx
->program
->info
->so
.outputs
[i
];
10351 if (stream
!= output
->stream
)
10354 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10357 begin_divergent_if_else(ctx
, &ic
);
10358 end_divergent_if(ctx
, &ic
);
10361 } /* end namespace */
10363 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10365 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10366 Builder
bld(ctx
->program
, ctx
->block
);
10367 constexpr unsigned hs_idx
= 1u;
10368 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10369 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10370 Operand((8u << 16) | (hs_idx
* 8u)));
10371 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10373 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10375 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10376 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10377 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10378 ls_has_nonzero_hs_threads
);
10379 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10380 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10381 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10382 ls_has_nonzero_hs_threads
);
10383 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10384 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10385 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10386 ls_has_nonzero_hs_threads
);
10388 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10389 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10390 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10393 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10395 /* Split all arguments except for the first (ring_offsets) and the last
10396 * (exec) so that the dead channels don't stay live throughout the program.
10398 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10399 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10400 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10401 startpgm
->definitions
[i
].regClass().size());
10406 void handle_bc_optimize(isel_context
*ctx
)
10408 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10409 Builder
bld(ctx
->program
, ctx
->block
);
10410 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10411 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10412 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10413 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10414 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10415 if (uses_center
&& uses_centroid
) {
10416 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10417 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10419 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10421 for (unsigned i
= 0; i
< 2; i
++) {
10422 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10423 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10424 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10425 persp_centroid
, persp_center
, sel
);
10427 ctx
->persp_centroid
= bld
.tmp(v2
);
10428 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10429 Operand(new_coord
[0]), Operand(new_coord
[1]));
10430 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10433 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10435 for (unsigned i
= 0; i
< 2; i
++) {
10436 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10437 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10438 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10439 linear_centroid
, linear_center
, sel
);
10441 ctx
->linear_centroid
= bld
.tmp(v2
);
10442 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10443 Operand(new_coord
[0]), Operand(new_coord
[1]));
10444 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10449 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10451 Program
*program
= ctx
->program
;
10453 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10455 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10456 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10457 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10458 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10459 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10461 program
->next_fp_mode
.must_flush_denorms32
=
10462 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10463 program
->next_fp_mode
.must_flush_denorms16_64
=
10464 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10465 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10467 program
->next_fp_mode
.care_about_round32
=
10468 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10470 program
->next_fp_mode
.care_about_round16_64
=
10471 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10472 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10474 /* default to preserving fp16 and fp64 denorms, since it's free */
10475 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10476 program
->next_fp_mode
.denorm16_64
= 0;
10478 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10480 /* preserving fp32 denorms is expensive, so only do it if asked */
10481 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10482 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10484 program
->next_fp_mode
.denorm32
= 0;
10486 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10487 program
->next_fp_mode
.round32
= fp_round_tz
;
10489 program
->next_fp_mode
.round32
= fp_round_ne
;
10491 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10492 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10494 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10496 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10499 void cleanup_cfg(Program
*program
)
10501 /* create linear_succs/logical_succs */
10502 for (Block
& BB
: program
->blocks
) {
10503 for (unsigned idx
: BB
.linear_preds
)
10504 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10505 for (unsigned idx
: BB
.logical_preds
)
10506 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10510 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10512 Builder
bld(ctx
->program
, ctx
->block
);
10514 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10515 Temp count
= i
== 0
10516 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10517 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10518 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10520 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10523 if (ctx
->program
->wave_size
== 64) {
10524 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10525 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10526 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10528 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10529 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10535 bool ngg_early_prim_export(isel_context
*ctx
)
10537 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10541 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10543 Builder
bld(ctx
->program
, ctx
->block
);
10545 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10546 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10548 /* Get the id of the current wave within the threadgroup (workgroup) */
10549 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10550 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10552 /* Execute the following code only on the first wave (wave id 0),
10553 * use the SCC def to tell if the wave id is zero or not.
10555 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10557 begin_uniform_if_then(ctx
, &ic
, cond
);
10558 begin_uniform_if_else(ctx
, &ic
);
10559 bld
.reset(ctx
->block
);
10561 /* Number of vertices output by VS/TES */
10562 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10563 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10564 /* Number of primitives output by VS/TES */
10565 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10566 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10568 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10569 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10570 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10572 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10573 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10575 end_uniform_if(ctx
, &ic
);
10577 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10578 bld
.reset(ctx
->block
);
10579 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10582 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10584 Builder
bld(ctx
->program
, ctx
->block
);
10586 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10587 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10590 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10593 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10594 assert(vtxindex
[i
].id());
10597 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10601 /* The initial edge flag is always false in tess eval shaders. */
10602 if (ctx
->stage
== ngg_vertex_gs
) {
10603 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10604 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10608 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10613 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10615 Builder
bld(ctx
->program
, ctx
->block
);
10616 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10618 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10619 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10620 false /* compressed */, true/* done */, false /* valid mask */);
10623 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10625 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10626 * These must always come before VS exports.
10628 * It is recommended to do these as early as possible. They can be at the beginning when
10629 * there is no SW GS and the shader doesn't write edge flags.
10633 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10634 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10636 Builder
bld(ctx
->program
, ctx
->block
);
10637 constexpr unsigned max_vertices_per_primitive
= 3;
10638 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10640 if (ctx
->stage
== ngg_vertex_gs
) {
10641 /* TODO: optimize for points & lines */
10642 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10643 if (ctx
->shader
->info
.tess
.point_mode
)
10644 num_vertices_per_primitive
= 1;
10645 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10646 num_vertices_per_primitive
= 2;
10648 unreachable("Unsupported NGG shader stage");
10651 Temp vtxindex
[max_vertices_per_primitive
];
10652 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10653 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10654 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10655 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10656 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10657 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10658 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10659 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10661 /* Export primitive data to the index buffer. */
10662 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10664 /* Export primitive ID. */
10665 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10666 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10667 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10668 Temp provoking_vtx_index
= vtxindex
[0];
10669 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10671 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10674 begin_divergent_if_else(ctx
, &ic
);
10675 end_divergent_if(ctx
, &ic
);
10678 void ngg_emit_nogs_output(isel_context
*ctx
)
10680 /* Emits NGG GS output, for stages that don't have SW GS. */
10683 Builder
bld(ctx
->program
, ctx
->block
);
10684 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10686 /* NGG streamout is currently disabled by default. */
10687 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10689 if (late_prim_export
) {
10690 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10691 create_export_phis(ctx
);
10692 /* Do what we need to do in the GS threads. */
10693 ngg_emit_nogs_gsthreads(ctx
);
10695 /* What comes next should be executed on ES threads. */
10696 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10697 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10698 bld
.reset(ctx
->block
);
10701 /* Export VS outputs */
10702 ctx
->block
->kind
|= block_kind_export_end
;
10703 create_vs_exports(ctx
);
10705 /* Export primitive ID */
10706 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10709 if (ctx
->stage
== ngg_vertex_gs
) {
10710 /* Wait for GS threads to store primitive ID in LDS. */
10711 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10712 bld
.sopp(aco_opcode::s_barrier
);
10714 /* Calculate LDS address where the GS threads stored the primitive ID. */
10715 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10716 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10717 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10718 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10719 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10720 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10722 /* Load primitive ID from LDS. */
10723 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10724 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10725 /* TES: Just use the patch ID as the primitive ID. */
10726 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10728 unreachable("unsupported NGG shader stage.");
10731 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10732 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10734 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10737 if (late_prim_export
) {
10738 begin_divergent_if_else(ctx
, &ic
);
10739 end_divergent_if(ctx
, &ic
);
10740 bld
.reset(ctx
->block
);
10744 void select_program(Program
*program
,
10745 unsigned shader_count
,
10746 struct nir_shader
*const *shaders
,
10747 ac_shader_config
* config
,
10748 struct radv_shader_args
*args
)
10750 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10751 if_context ic_merged_wave_info
;
10752 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10754 for (unsigned i
= 0; i
< shader_count
; i
++) {
10755 nir_shader
*nir
= shaders
[i
];
10756 init_context(&ctx
, nir
);
10758 setup_fp_mode(&ctx
, nir
);
10761 /* needs to be after init_context() for FS */
10762 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10763 append_logical_start(ctx
.block
);
10765 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10766 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10768 split_arguments(&ctx
, startpgm
);
10772 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10774 if (ngg_early_prim_export(&ctx
))
10775 ngg_emit_nogs_gsthreads(&ctx
);
10778 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10779 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10780 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10781 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10782 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10783 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10784 ctx
.stage
== tess_eval_geometry_gs
));
10786 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10787 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10788 if (check_merged_wave_info
) {
10789 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10790 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10794 Builder
bld(ctx
.program
, ctx
.block
);
10796 bld
.barrier(aco_opcode::p_memory_barrier_shared
);
10797 bld
.sopp(aco_opcode::s_barrier
);
10799 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10800 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10802 } else if (ctx
.stage
== geometry_gs
)
10803 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10805 if (ctx
.stage
== fragment_fs
)
10806 handle_bc_optimize(&ctx
);
10808 visit_cf_list(&ctx
, &func
->body
);
10810 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10811 emit_streamout(&ctx
, 0);
10813 if (ctx
.stage
& hw_vs
) {
10814 create_vs_exports(&ctx
);
10815 ctx
.block
->kind
|= block_kind_export_end
;
10816 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10817 ngg_emit_nogs_output(&ctx
);
10818 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10819 Builder
bld(ctx
.program
, ctx
.block
);
10820 bld
.barrier(aco_opcode::p_memory_barrier_gs_data
);
10821 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10822 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10823 write_tcs_tess_factors(&ctx
);
10826 if (ctx
.stage
== fragment_fs
) {
10827 create_fs_exports(&ctx
);
10828 ctx
.block
->kind
|= block_kind_export_end
;
10831 if (endif_merged_wave_info
) {
10832 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10833 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10836 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10837 ngg_emit_nogs_output(&ctx
);
10839 ralloc_free(ctx
.divergent_vals
);
10841 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10842 /* Outputs of the previous stage are inputs to the next stage */
10843 ctx
.inputs
= ctx
.outputs
;
10844 ctx
.outputs
= shader_io_state();
10848 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10850 append_logical_end(ctx
.block
);
10851 ctx
.block
->kind
|= block_kind_uniform
;
10852 Builder
bld(ctx
.program
, ctx
.block
);
10853 if (ctx
.program
->wb_smem_l1_on_end
)
10854 bld
.smem(aco_opcode::s_dcache_wb
, false);
10855 bld
.sopp(aco_opcode::s_endpgm
);
10857 cleanup_cfg(program
);
10860 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10861 ac_shader_config
* config
,
10862 struct radv_shader_args
*args
)
10864 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10866 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
= false;
10867 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
= false;
10868 program
->next_fp_mode
.must_flush_denorms32
= false;
10869 program
->next_fp_mode
.must_flush_denorms16_64
= false;
10870 program
->next_fp_mode
.care_about_round32
= false;
10871 program
->next_fp_mode
.care_about_round16_64
= false;
10872 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10873 program
->next_fp_mode
.denorm32
= 0;
10874 program
->next_fp_mode
.round32
= fp_round_ne
;
10875 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10876 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10878 add_startpgm(&ctx
);
10879 append_logical_start(ctx
.block
);
10881 Builder
bld(ctx
.program
, ctx
.block
);
10883 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10885 Operand
stream_id(0u);
10886 if (args
->shader_info
->so
.num_outputs
)
10887 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10888 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10890 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10892 std::stack
<Block
> endif_blocks
;
10894 for (unsigned stream
= 0; stream
< 4; stream
++) {
10895 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10898 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10899 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10902 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10904 unsigned BB_if_idx
= ctx
.block
->index
;
10905 Block BB_endif
= Block();
10906 if (!stream_id
.isConstant()) {
10908 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10909 append_logical_end(ctx
.block
);
10910 ctx
.block
->kind
|= block_kind_uniform
;
10911 bld
.branch(aco_opcode::p_cbranch_z
, cond
);
10913 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10915 ctx
.block
= ctx
.program
->create_and_insert_block();
10916 add_edge(BB_if_idx
, ctx
.block
);
10917 bld
.reset(ctx
.block
);
10918 append_logical_start(ctx
.block
);
10921 unsigned offset
= 0;
10922 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10923 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10926 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10927 unsigned length
= util_last_bit(output_usage_mask
);
10928 for (unsigned j
= 0; j
< length
; ++j
) {
10929 if (!(output_usage_mask
& (1 << j
)))
10932 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10933 Temp voffset
= vtx_offset
;
10934 if (const_offset
>= 4096u) {
10935 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10936 const_offset
%= 4096u;
10939 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10940 mubuf
->definitions
[0] = bld
.def(v1
);
10941 mubuf
->operands
[0] = Operand(gsvs_ring
);
10942 mubuf
->operands
[1] = Operand(voffset
);
10943 mubuf
->operands
[2] = Operand(0u);
10944 mubuf
->offen
= true;
10945 mubuf
->offset
= const_offset
;
10948 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10949 mubuf
->barrier
= barrier_none
;
10950 mubuf
->can_reorder
= true;
10952 ctx
.outputs
.mask
[i
] |= 1 << j
;
10953 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10955 bld
.insert(std::move(mubuf
));
10961 if (args
->shader_info
->so
.num_outputs
) {
10962 emit_streamout(&ctx
, stream
);
10963 bld
.reset(ctx
.block
);
10967 create_vs_exports(&ctx
);
10968 ctx
.block
->kind
|= block_kind_export_end
;
10971 if (!stream_id
.isConstant()) {
10972 append_logical_end(ctx
.block
);
10974 /* branch from then block to endif block */
10975 bld
.branch(aco_opcode::p_branch
);
10976 add_edge(ctx
.block
->index
, &BB_endif
);
10977 ctx
.block
->kind
|= block_kind_uniform
;
10979 /* emit else block */
10980 ctx
.block
= ctx
.program
->create_and_insert_block();
10981 add_edge(BB_if_idx
, ctx
.block
);
10982 bld
.reset(ctx
.block
);
10983 append_logical_start(ctx
.block
);
10985 endif_blocks
.push(std::move(BB_endif
));
10989 while (!endif_blocks
.empty()) {
10990 Block BB_endif
= std::move(endif_blocks
.top());
10991 endif_blocks
.pop();
10993 Block
*BB_else
= ctx
.block
;
10995 append_logical_end(BB_else
);
10996 /* branch from else block to endif block */
10997 bld
.branch(aco_opcode::p_branch
);
10998 add_edge(BB_else
->index
, &BB_endif
);
10999 BB_else
->kind
|= block_kind_uniform
;
11001 /** emit endif merge block */
11002 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11003 bld
.reset(ctx
.block
);
11004 append_logical_start(ctx
.block
);
11007 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11009 append_logical_end(ctx
.block
);
11010 ctx
.block
->kind
|= block_kind_uniform
;
11011 bld
.sopp(aco_opcode::s_endpgm
);
11013 cleanup_cfg(program
);