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radv: bail out when binding the same vertex buffers
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
207 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
208 cmd_buffer->device = device;
209 cmd_buffer->pool = pool;
210 cmd_buffer->level = level;
211
212 if (pool) {
213 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
214 cmd_buffer->queue_family_index = pool->queue_family_index;
215
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
222 }
223
224 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
225
226 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
227 if (!cmd_buffer->cs) {
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230 }
231
232 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
233
234 cmd_buffer->upload.offset = 0;
235 cmd_buffer->upload.size = 0;
236 list_inithead(&cmd_buffer->upload.list);
237
238 return VK_SUCCESS;
239 }
240
241 static void
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
243 {
244 list_del(&cmd_buffer->pool_link);
245
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
247 &cmd_buffer->upload.list, list) {
248 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
249 list_del(&up->list);
250 free(up);
251 }
252
253 if (cmd_buffer->upload.upload_bo)
254 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
255 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
256 free(cmd_buffer->push_descriptors.set.mapped_ptr);
257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
258 }
259
260 static VkResult
261 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
262 {
263
264 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
265
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
267 &cmd_buffer->upload.list, list) {
268 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
269 list_del(&up->list);
270 free(up);
271 }
272
273 cmd_buffer->push_constant_stages = 0;
274 cmd_buffer->scratch_size_needed = 0;
275 cmd_buffer->compute_scratch_size_needed = 0;
276 cmd_buffer->esgs_ring_size_needed = 0;
277 cmd_buffer->gsvs_ring_size_needed = 0;
278 cmd_buffer->tess_rings_needed = false;
279 cmd_buffer->sample_positions_needed = false;
280
281 if (cmd_buffer->upload.upload_bo)
282 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
283 cmd_buffer->upload.upload_bo, 8);
284 cmd_buffer->upload.offset = 0;
285
286 cmd_buffer->record_result = VK_SUCCESS;
287
288 cmd_buffer->ring_offsets_idx = -1;
289
290 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
291 void *fence_ptr;
292 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
293 &cmd_buffer->gfx9_fence_offset,
294 &fence_ptr);
295 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
296 }
297
298 return cmd_buffer->record_result;
299 }
300
301 static bool
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
303 uint64_t min_needed)
304 {
305 uint64_t new_size;
306 struct radeon_winsys_bo *bo;
307 struct radv_cmd_buffer_upload *upload;
308 struct radv_device *device = cmd_buffer->device;
309
310 new_size = MAX2(min_needed, 16 * 1024);
311 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
312
313 bo = device->ws->buffer_create(device->ws,
314 new_size, 4096,
315 RADEON_DOMAIN_GTT,
316 RADEON_FLAG_CPU_ACCESS|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING);
318
319 if (!bo) {
320 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
321 return false;
322 }
323
324 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
325 if (cmd_buffer->upload.upload_bo) {
326 upload = malloc(sizeof(*upload));
327
328 if (!upload) {
329 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
330 device->ws->buffer_destroy(bo);
331 return false;
332 }
333
334 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
335 list_add(&upload->list, &cmd_buffer->upload.list);
336 }
337
338 cmd_buffer->upload.upload_bo = bo;
339 cmd_buffer->upload.size = new_size;
340 cmd_buffer->upload.offset = 0;
341 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
342
343 if (!cmd_buffer->upload.map) {
344 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
345 return false;
346 }
347
348 return true;
349 }
350
351 bool
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
353 unsigned size,
354 unsigned alignment,
355 unsigned *out_offset,
356 void **ptr)
357 {
358 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
359 if (offset + size > cmd_buffer->upload.size) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
361 return false;
362 offset = 0;
363 }
364
365 *out_offset = offset;
366 *ptr = cmd_buffer->upload.map + offset;
367
368 cmd_buffer->upload.offset = offset + size;
369 return true;
370 }
371
372 bool
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
374 unsigned size, unsigned alignment,
375 const void *data, unsigned *out_offset)
376 {
377 uint8_t *ptr;
378
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
380 out_offset, (void **)&ptr))
381 return false;
382
383 if (ptr)
384 memcpy(ptr, data, size);
385
386 return true;
387 }
388
389 static void
390 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
391 unsigned count, const uint32_t *data)
392 {
393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME));
397 radeon_emit(cs, va);
398 radeon_emit(cs, va >> 32);
399 radeon_emit_array(cs, data, count);
400 }
401
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
403 {
404 struct radv_device *device = cmd_buffer->device;
405 struct radeon_winsys_cs *cs = cmd_buffer->cs;
406 uint64_t va;
407
408 if (!device->trace_bo)
409 return;
410
411 va = radv_buffer_get_va(device->trace_bo);
412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
413 va += 4;
414
415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
416
417 ++cmd_buffer->state.trace_id;
418 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
419 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
421 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
422 }
423
424 static void
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
426 {
427 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
428 enum radv_cmd_flush_bits flags;
429
430 /* Force wait for graphics/compute engines to be idle. */
431 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
433
434 si_cs_emit_cache_flush(cmd_buffer->cs, false,
435 cmd_buffer->device->physical_device->rad_info.chip_class,
436 NULL, 0,
437 radv_cmd_buffer_uses_mec(cmd_buffer),
438 flags);
439 }
440
441 radv_cmd_buffer_trace_emit(cmd_buffer);
442 }
443
444 static void
445 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
446 struct radv_pipeline *pipeline, enum ring_type ring)
447 {
448 struct radv_device *device = cmd_buffer->device;
449 struct radeon_winsys_cs *cs = cmd_buffer->cs;
450 uint32_t data[2];
451 uint64_t va;
452
453 if (!device->trace_bo)
454 return;
455
456 va = radv_buffer_get_va(device->trace_bo);
457
458 switch (ring) {
459 case RING_GFX:
460 va += 8;
461 break;
462 case RING_COMPUTE:
463 va += 16;
464 break;
465 default:
466 assert(!"invalid ring type");
467 }
468
469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
470 cmd_buffer->cs, 6);
471
472 data[0] = (uintptr_t)pipeline;
473 data[1] = (uintptr_t)pipeline >> 32;
474
475 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
476 radv_emit_write_data_packet(cs, va, 2, data);
477 }
478
479 static void
480 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
481 {
482 struct radv_device *device = cmd_buffer->device;
483 struct radeon_winsys_cs *cs = cmd_buffer->cs;
484 uint32_t data[MAX_SETS * 2] = {};
485 uint64_t va;
486
487 if (!device->trace_bo)
488 return;
489
490 va = radv_buffer_get_va(device->trace_bo) + 24;
491
492 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
493 cmd_buffer->cs, 4 + MAX_SETS * 2);
494
495 for (int i = 0; i < MAX_SETS; i++) {
496 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
497 if (!set)
498 continue;
499
500 data[i * 2] = (uintptr_t)set;
501 data[i * 2 + 1] = (uintptr_t)set >> 32;
502 }
503
504 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
505 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
506 }
507
508 static void
509 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
510 struct radv_pipeline *pipeline)
511 {
512 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
513 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
514 8);
515 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
516 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
517
518 if (cmd_buffer->device->physical_device->has_rbplus) {
519
520 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
521 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
522
523 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
524 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
525 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
526 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
527 }
528 }
529
530 static void
531 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
532 struct radv_pipeline *pipeline)
533 {
534 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
535 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
536 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
537
538 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
539 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
540 }
541
542 struct ac_userdata_info *
543 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
544 gl_shader_stage stage,
545 int idx)
546 {
547 if (stage == MESA_SHADER_VERTEX) {
548 if (pipeline->shaders[MESA_SHADER_VERTEX])
549 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
550 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
551 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
552 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
553 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
554 } else if (stage == MESA_SHADER_TESS_EVAL) {
555 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
556 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
557 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
558 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
559 }
560 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
561 }
562
563 static void
564 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
565 struct radv_pipeline *pipeline,
566 gl_shader_stage stage,
567 int idx, uint64_t va)
568 {
569 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
570 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
571 if (loc->sgpr_idx == -1)
572 return;
573 assert(loc->num_sgprs == 2);
574 assert(!loc->indirect);
575 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
576 radeon_emit(cmd_buffer->cs, va);
577 radeon_emit(cmd_buffer->cs, va >> 32);
578 }
579
580 static void
581 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
582 struct radv_pipeline *pipeline)
583 {
584 int num_samples = pipeline->graphics.ms.num_samples;
585 struct radv_multisample_state *ms = &pipeline->graphics.ms;
586 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
587
588 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
589 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
590 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
591
592 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
593 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
594
595 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
596 return;
597
598 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
599 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
600 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
601
602 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
603
604 /* GFX9: Flush DFSM when the AA mode changes. */
605 if (cmd_buffer->device->dfsm_allowed) {
606 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
607 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
608 }
609 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
610 uint32_t offset;
611 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
612 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
613 if (loc->sgpr_idx == -1)
614 return;
615 assert(loc->num_sgprs == 1);
616 assert(!loc->indirect);
617 switch (num_samples) {
618 default:
619 offset = 0;
620 break;
621 case 2:
622 offset = 1;
623 break;
624 case 4:
625 offset = 3;
626 break;
627 case 8:
628 offset = 7;
629 break;
630 case 16:
631 offset = 15;
632 break;
633 }
634
635 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
636 cmd_buffer->sample_positions_needed = true;
637 }
638 }
639
640 static void
641 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
642 struct radv_pipeline *pipeline)
643 {
644 struct radv_raster_state *raster = &pipeline->graphics.raster;
645
646 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
647 raster->pa_cl_clip_cntl);
648 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
649 raster->spi_interp_control);
650 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
651 raster->pa_su_vtx_cntl);
652 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
653 raster->pa_su_sc_mode_cntl);
654 }
655
656 static void
657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
658 struct radv_shader_variant *shader)
659 {
660 struct radeon_winsys *ws = cmd_buffer->device->ws;
661 struct radeon_winsys_cs *cs = cmd_buffer->cs;
662 uint64_t va;
663
664 if (!shader)
665 return;
666
667 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
668
669 ws->cs_add_buffer(cs, shader->bo, 8);
670 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
671 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
672 }
673
674 static void
675 radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
676 struct radv_pipeline *pipeline)
677 {
678 radv_emit_shader_prefetch(cmd_buffer,
679 pipeline->shaders[MESA_SHADER_VERTEX]);
680 radv_emit_shader_prefetch(cmd_buffer,
681 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
682 radv_emit_shader_prefetch(cmd_buffer,
683 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
684 radv_emit_shader_prefetch(cmd_buffer,
685 pipeline->shaders[MESA_SHADER_GEOMETRY]);
686 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
687 radv_emit_shader_prefetch(cmd_buffer,
688 pipeline->shaders[MESA_SHADER_FRAGMENT]);
689 }
690
691 static void
692 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
693 struct radv_pipeline *pipeline,
694 struct radv_shader_variant *shader,
695 struct ac_vs_output_info *outinfo)
696 {
697 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
698 unsigned export_count;
699
700 export_count = MAX2(1, outinfo->param_exports);
701 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
702 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
703
704 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
705 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
706 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
707 V_02870C_SPI_SHADER_4COMP :
708 V_02870C_SPI_SHADER_NONE) |
709 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
710 V_02870C_SPI_SHADER_4COMP :
711 V_02870C_SPI_SHADER_NONE) |
712 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
713 V_02870C_SPI_SHADER_4COMP :
714 V_02870C_SPI_SHADER_NONE));
715
716
717 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
718 radeon_emit(cmd_buffer->cs, va >> 8);
719 radeon_emit(cmd_buffer->cs, va >> 40);
720 radeon_emit(cmd_buffer->cs, shader->rsrc1);
721 radeon_emit(cmd_buffer->cs, shader->rsrc2);
722
723 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
724 S_028818_VTX_W0_FMT(1) |
725 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
726 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
727 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
728
729
730 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
731 pipeline->graphics.pa_cl_vs_out_cntl);
732
733 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
734 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
735 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
736 }
737
738 static void
739 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
740 struct radv_shader_variant *shader,
741 struct ac_es_output_info *outinfo)
742 {
743 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
744
745 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
746 outinfo->esgs_itemsize / 4);
747 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
748 radeon_emit(cmd_buffer->cs, va >> 8);
749 radeon_emit(cmd_buffer->cs, va >> 40);
750 radeon_emit(cmd_buffer->cs, shader->rsrc1);
751 radeon_emit(cmd_buffer->cs, shader->rsrc2);
752 }
753
754 static void
755 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
756 struct radv_shader_variant *shader)
757 {
758 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
759 uint32_t rsrc2 = shader->rsrc2;
760
761 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
762 radeon_emit(cmd_buffer->cs, va >> 8);
763 radeon_emit(cmd_buffer->cs, va >> 40);
764
765 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
766 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
767 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
768 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
769
770 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
771 radeon_emit(cmd_buffer->cs, shader->rsrc1);
772 radeon_emit(cmd_buffer->cs, rsrc2);
773 }
774
775 static void
776 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
777 struct radv_shader_variant *shader)
778 {
779 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
780
781 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
782 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
783 radeon_emit(cmd_buffer->cs, va >> 8);
784 radeon_emit(cmd_buffer->cs, va >> 40);
785
786 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
787 radeon_emit(cmd_buffer->cs, shader->rsrc1);
788 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
789 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
790 } else {
791 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
792 radeon_emit(cmd_buffer->cs, va >> 8);
793 radeon_emit(cmd_buffer->cs, va >> 40);
794 radeon_emit(cmd_buffer->cs, shader->rsrc1);
795 radeon_emit(cmd_buffer->cs, shader->rsrc2);
796 }
797 }
798
799 static void
800 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
801 struct radv_pipeline *pipeline)
802 {
803 struct radv_shader_variant *vs;
804
805 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
806
807 /* Skip shaders merged into HS/GS */
808 vs = pipeline->shaders[MESA_SHADER_VERTEX];
809 if (!vs)
810 return;
811
812 if (vs->info.vs.as_ls)
813 radv_emit_hw_ls(cmd_buffer, vs);
814 else if (vs->info.vs.as_es)
815 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
816 else
817 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
818 }
819
820
821 static void
822 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
823 struct radv_pipeline *pipeline)
824 {
825 if (!radv_pipeline_has_tess(pipeline))
826 return;
827
828 struct radv_shader_variant *tes, *tcs;
829
830 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
831 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
832
833 if (tes) {
834 if (tes->info.tes.as_es)
835 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
836 else
837 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
838 }
839
840 radv_emit_hw_hs(cmd_buffer, tcs);
841
842 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
843 pipeline->graphics.tess.tf_param);
844
845 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
846 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
847 pipeline->graphics.tess.ls_hs_config);
848 else
849 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
850 pipeline->graphics.tess.ls_hs_config);
851
852 struct ac_userdata_info *loc;
853
854 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
855 if (loc->sgpr_idx != -1) {
856 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
857 assert(loc->num_sgprs == 4);
858 assert(!loc->indirect);
859 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
860 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
861 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
862 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
863 pipeline->graphics.tess.num_tcs_input_cp << 26);
864 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
865 }
866
867 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
868 if (loc->sgpr_idx != -1) {
869 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
870 assert(loc->num_sgprs == 1);
871 assert(!loc->indirect);
872
873 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
874 pipeline->graphics.tess.offchip_layout);
875 }
876
877 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
878 if (loc->sgpr_idx != -1) {
879 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
880 assert(loc->num_sgprs == 1);
881 assert(!loc->indirect);
882
883 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
884 pipeline->graphics.tess.tcs_in_layout);
885 }
886 }
887
888 static void
889 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
890 struct radv_pipeline *pipeline)
891 {
892 struct radv_shader_variant *gs;
893 uint64_t va;
894
895 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
896
897 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
898 if (!gs)
899 return;
900
901 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
902
903 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
904 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
905 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
906 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
907
908 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
909
910 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
911
912 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
913 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
914 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
915 radeon_emit(cmd_buffer->cs, 0);
916 radeon_emit(cmd_buffer->cs, 0);
917 radeon_emit(cmd_buffer->cs, 0);
918
919 uint32_t gs_num_invocations = gs->info.gs.invocations;
920 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
921 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
922 S_028B90_ENABLE(gs_num_invocations > 0));
923
924 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
925
926 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
927 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
928 radeon_emit(cmd_buffer->cs, va >> 8);
929 radeon_emit(cmd_buffer->cs, va >> 40);
930
931 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
932 radeon_emit(cmd_buffer->cs, gs->rsrc1);
933 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
934 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
935
936 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
937 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
938 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize);
939 } else {
940 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
941 radeon_emit(cmd_buffer->cs, va >> 8);
942 radeon_emit(cmd_buffer->cs, va >> 40);
943 radeon_emit(cmd_buffer->cs, gs->rsrc1);
944 radeon_emit(cmd_buffer->cs, gs->rsrc2);
945 }
946
947 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
948
949 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
950 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
951 if (loc->sgpr_idx != -1) {
952 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
953 uint32_t num_entries = 64;
954 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
955
956 if (is_vi)
957 num_entries *= stride;
958
959 stride = S_008F04_STRIDE(stride);
960 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
961 radeon_emit(cmd_buffer->cs, stride);
962 radeon_emit(cmd_buffer->cs, num_entries);
963 }
964 }
965
966 static void
967 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
968 struct radv_pipeline *pipeline)
969 {
970 struct radv_shader_variant *ps;
971 uint64_t va;
972 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
973 struct radv_blend_state *blend = &pipeline->graphics.blend;
974 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
975
976 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
977 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
978
979 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
980 radeon_emit(cmd_buffer->cs, va >> 8);
981 radeon_emit(cmd_buffer->cs, va >> 40);
982 radeon_emit(cmd_buffer->cs, ps->rsrc1);
983 radeon_emit(cmd_buffer->cs, ps->rsrc2);
984
985 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
986 pipeline->graphics.db_shader_control);
987
988 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
989 ps->config.spi_ps_input_ena);
990
991 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
992 ps->config.spi_ps_input_addr);
993
994 if (ps->info.info.ps.force_persample)
995 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
996
997 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
998 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
999
1000 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1001
1002 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1003 pipeline->graphics.shader_z_format);
1004
1005 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1006
1007 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1008 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1009
1010 if (cmd_buffer->device->dfsm_allowed) {
1011 /* optimise this? */
1012 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1013 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1014 }
1015
1016 if (pipeline->graphics.ps_input_cntl_num) {
1017 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1018 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1019 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1020 }
1021 }
1022 }
1023
1024 static void
1025 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1026 struct radv_pipeline *pipeline)
1027 {
1028 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1029
1030 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1031 return;
1032
1033 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1034 pipeline->graphics.vtx_reuse_depth);
1035 }
1036
1037 static void
1038 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1039 {
1040 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1041
1042 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1043 return;
1044
1045 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1046 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1047 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1048 radv_update_multisample_state(cmd_buffer, pipeline);
1049 radv_emit_vertex_shader(cmd_buffer, pipeline);
1050 radv_emit_tess_shaders(cmd_buffer, pipeline);
1051 radv_emit_geometry_shader(cmd_buffer, pipeline);
1052 radv_emit_fragment_shader(cmd_buffer, pipeline);
1053 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1054
1055 cmd_buffer->scratch_size_needed =
1056 MAX2(cmd_buffer->scratch_size_needed,
1057 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1058
1059 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1060 S_0286E8_WAVES(pipeline->max_waves) |
1061 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1062
1063 if (!cmd_buffer->state.emitted_pipeline ||
1064 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1065 pipeline->graphics.can_use_guardband)
1066 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1067
1068 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1069
1070 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1071 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1072 } else {
1073 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1074 }
1075 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1076
1077 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1078
1079 cmd_buffer->state.emitted_pipeline = pipeline;
1080
1081 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1082 }
1083
1084 static void
1085 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1086 {
1087 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1088 cmd_buffer->state.dynamic.viewport.viewports);
1089 }
1090
1091 static void
1092 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1093 {
1094 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1095
1096 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1097 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1098 si_emit_cache_flush(cmd_buffer);
1099 }
1100 si_write_scissors(cmd_buffer->cs, 0, count,
1101 cmd_buffer->state.dynamic.scissor.scissors,
1102 cmd_buffer->state.dynamic.viewport.viewports,
1103 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1104 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1105 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1106 }
1107
1108 static void
1109 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1110 {
1111 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1112
1113 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1114 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1115 }
1116
1117 static void
1118 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1119 {
1120 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1121
1122 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1123 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1124 }
1125
1126 static void
1127 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1128 {
1129 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1130
1131 radeon_set_context_reg_seq(cmd_buffer->cs,
1132 R_028430_DB_STENCILREFMASK, 2);
1133 radeon_emit(cmd_buffer->cs,
1134 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1135 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1136 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1137 S_028430_STENCILOPVAL(1));
1138 radeon_emit(cmd_buffer->cs,
1139 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1140 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1141 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1142 S_028434_STENCILOPVAL_BF(1));
1143 }
1144
1145 static void
1146 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1147 {
1148 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1149
1150 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1151 fui(d->depth_bounds.min));
1152 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1153 fui(d->depth_bounds.max));
1154 }
1155
1156 static void
1157 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1158 {
1159 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1160 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1161 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1162 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1163
1164 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1165 radeon_set_context_reg_seq(cmd_buffer->cs,
1166 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1167 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1168 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1169 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1170 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1171 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1172 }
1173 }
1174
1175 static void
1176 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1177 int index,
1178 struct radv_color_buffer_info *cb)
1179 {
1180 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1181
1182 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1183 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1184 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1185 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1186 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1187 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1188 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1189 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1190 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1191 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1192 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1193 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1194 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1195
1196 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1197 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1198 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1199
1200 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1201 cb->gfx9_epitch);
1202 } else {
1203 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1204 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1205 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1206 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1207 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1208 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1209 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1210 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1211 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1212 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1213 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1214 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1215
1216 if (is_vi) { /* DCC BASE */
1217 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1218 }
1219 }
1220 }
1221
1222 static void
1223 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1224 struct radv_ds_buffer_info *ds,
1225 struct radv_image *image,
1226 VkImageLayout layout)
1227 {
1228 uint32_t db_z_info = ds->db_z_info;
1229 uint32_t db_stencil_info = ds->db_stencil_info;
1230
1231 if (!radv_layout_has_htile(image, layout,
1232 radv_image_queue_family_mask(image,
1233 cmd_buffer->queue_family_index,
1234 cmd_buffer->queue_family_index))) {
1235 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1236 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1237 }
1238
1239 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1240 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1241
1242
1243 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1244 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1245 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1246 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1247 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1248
1249 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1250 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1251 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1252 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1253 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1254 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1255 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1256 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1257 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1258 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1259 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1260
1261 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1262 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1263 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1264 } else {
1265 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1266
1267 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1268 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1269 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1270 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1271 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1272 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1273 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1274 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1275 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1276 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1277
1278 }
1279
1280 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1281 ds->pa_su_poly_offset_db_fmt_cntl);
1282 }
1283
1284 void
1285 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1286 struct radv_image *image,
1287 VkClearDepthStencilValue ds_clear_value,
1288 VkImageAspectFlags aspects)
1289 {
1290 uint64_t va = radv_buffer_get_va(image->bo);
1291 va += image->offset + image->clear_value_offset;
1292 unsigned reg_offset = 0, reg_count = 0;
1293
1294 if (!image->surface.htile_size || !aspects)
1295 return;
1296
1297 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1298 ++reg_count;
1299 } else {
1300 ++reg_offset;
1301 va += 4;
1302 }
1303 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1304 ++reg_count;
1305
1306 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1307
1308 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1309 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1310 S_370_WR_CONFIRM(1) |
1311 S_370_ENGINE_SEL(V_370_PFP));
1312 radeon_emit(cmd_buffer->cs, va);
1313 radeon_emit(cmd_buffer->cs, va >> 32);
1314 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1315 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1316 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1317 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1318
1319 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1320 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1321 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1322 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1323 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1324 }
1325
1326 static void
1327 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1328 struct radv_image *image)
1329 {
1330 uint64_t va = radv_buffer_get_va(image->bo);
1331 va += image->offset + image->clear_value_offset;
1332
1333 if (!image->surface.htile_size)
1334 return;
1335
1336 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1337
1338 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1339 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1340 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1341 COPY_DATA_COUNT_SEL);
1342 radeon_emit(cmd_buffer->cs, va);
1343 radeon_emit(cmd_buffer->cs, va >> 32);
1344 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1345 radeon_emit(cmd_buffer->cs, 0);
1346
1347 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1348 radeon_emit(cmd_buffer->cs, 0);
1349 }
1350
1351 /*
1352 *with DCC some colors don't require CMASK elimiation before being
1353 * used as a texture. This sets a predicate value to determine if the
1354 * cmask eliminate is required.
1355 */
1356 void
1357 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1358 struct radv_image *image,
1359 bool value)
1360 {
1361 uint64_t pred_val = value;
1362 uint64_t va = radv_buffer_get_va(image->bo);
1363 va += image->offset + image->dcc_pred_offset;
1364
1365 if (!image->surface.dcc_size)
1366 return;
1367
1368 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1369
1370 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1371 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1372 S_370_WR_CONFIRM(1) |
1373 S_370_ENGINE_SEL(V_370_PFP));
1374 radeon_emit(cmd_buffer->cs, va);
1375 radeon_emit(cmd_buffer->cs, va >> 32);
1376 radeon_emit(cmd_buffer->cs, pred_val);
1377 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1378 }
1379
1380 void
1381 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1382 struct radv_image *image,
1383 int idx,
1384 uint32_t color_values[2])
1385 {
1386 uint64_t va = radv_buffer_get_va(image->bo);
1387 va += image->offset + image->clear_value_offset;
1388
1389 if (!image->cmask.size && !image->surface.dcc_size)
1390 return;
1391
1392 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1393
1394 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1395 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1396 S_370_WR_CONFIRM(1) |
1397 S_370_ENGINE_SEL(V_370_PFP));
1398 radeon_emit(cmd_buffer->cs, va);
1399 radeon_emit(cmd_buffer->cs, va >> 32);
1400 radeon_emit(cmd_buffer->cs, color_values[0]);
1401 radeon_emit(cmd_buffer->cs, color_values[1]);
1402
1403 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1404 radeon_emit(cmd_buffer->cs, color_values[0]);
1405 radeon_emit(cmd_buffer->cs, color_values[1]);
1406 }
1407
1408 static void
1409 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1410 struct radv_image *image,
1411 int idx)
1412 {
1413 uint64_t va = radv_buffer_get_va(image->bo);
1414 va += image->offset + image->clear_value_offset;
1415
1416 if (!image->cmask.size && !image->surface.dcc_size)
1417 return;
1418
1419 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1420 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1421
1422 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1423 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1424 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1425 COPY_DATA_COUNT_SEL);
1426 radeon_emit(cmd_buffer->cs, va);
1427 radeon_emit(cmd_buffer->cs, va >> 32);
1428 radeon_emit(cmd_buffer->cs, reg >> 2);
1429 radeon_emit(cmd_buffer->cs, 0);
1430
1431 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1432 radeon_emit(cmd_buffer->cs, 0);
1433 }
1434
1435 void
1436 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1437 {
1438 int i;
1439 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1440 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1441
1442 /* this may happen for inherited secondary recording */
1443 if (!framebuffer)
1444 return;
1445
1446 for (i = 0; i < 8; ++i) {
1447 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1448 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1449 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1450 continue;
1451 }
1452
1453 int idx = subpass->color_attachments[i].attachment;
1454 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1455
1456 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1457
1458 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1459 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1460
1461 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1462 }
1463
1464 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1465 int idx = subpass->depth_stencil_attachment.attachment;
1466 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1467 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1468 struct radv_image *image = att->attachment->image;
1469 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1470 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1471 cmd_buffer->queue_family_index,
1472 cmd_buffer->queue_family_index);
1473 /* We currently don't support writing decompressed HTILE */
1474 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1475 radv_layout_is_htile_compressed(image, layout, queue_mask));
1476
1477 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1478
1479 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1480 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1481 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1482 }
1483 radv_load_depth_clear_regs(cmd_buffer, image);
1484 } else {
1485 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1486 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1487 else
1488 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1489
1490 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1491 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1492 }
1493 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1494 S_028208_BR_X(framebuffer->width) |
1495 S_028208_BR_Y(framebuffer->height));
1496
1497 if (cmd_buffer->device->dfsm_allowed) {
1498 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1499 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1500 }
1501
1502 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1503 }
1504
1505 static void
1506 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1507 {
1508 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1509
1510 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1511 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1512 2, cmd_buffer->state.index_type);
1513 } else {
1514 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1515 radeon_emit(cs, cmd_buffer->state.index_type);
1516 }
1517
1518 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1519 radeon_emit(cs, cmd_buffer->state.index_va);
1520 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1521
1522 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1523 radeon_emit(cs, cmd_buffer->state.max_index_count);
1524
1525 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1526 }
1527
1528 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1529 {
1530 uint32_t db_count_control;
1531
1532 if(!cmd_buffer->state.active_occlusion_queries) {
1533 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1534 db_count_control = 0;
1535 } else {
1536 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1537 }
1538 } else {
1539 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1540 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1541 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1542 S_028004_ZPASS_ENABLE(1) |
1543 S_028004_SLICE_EVEN_ENABLE(1) |
1544 S_028004_SLICE_ODD_ENABLE(1);
1545 } else {
1546 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1547 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1548 }
1549 }
1550
1551 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1552 }
1553
1554 static void
1555 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1556 {
1557 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1558 return;
1559
1560 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1561 radv_emit_viewport(cmd_buffer);
1562
1563 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1564 radv_emit_scissor(cmd_buffer);
1565
1566 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1567 radv_emit_line_width(cmd_buffer);
1568
1569 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1570 radv_emit_blend_constants(cmd_buffer);
1571
1572 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1573 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1574 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1575 radv_emit_stencil(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1578 radv_emit_depth_bounds(cmd_buffer);
1579
1580 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1581 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1582 radv_emit_depth_biais(cmd_buffer);
1583
1584 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1585 }
1586
1587 static void
1588 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1589 struct radv_pipeline *pipeline,
1590 int idx,
1591 uint64_t va,
1592 gl_shader_stage stage)
1593 {
1594 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1595 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1596
1597 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1598 return;
1599
1600 assert(!desc_set_loc->indirect);
1601 assert(desc_set_loc->num_sgprs == 2);
1602 radeon_set_sh_reg_seq(cmd_buffer->cs,
1603 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1604 radeon_emit(cmd_buffer->cs, va);
1605 radeon_emit(cmd_buffer->cs, va >> 32);
1606 }
1607
1608 static void
1609 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1610 VkShaderStageFlags stages,
1611 struct radv_descriptor_set *set,
1612 unsigned idx)
1613 {
1614 if (cmd_buffer->state.pipeline) {
1615 radv_foreach_stage(stage, stages) {
1616 if (cmd_buffer->state.pipeline->shaders[stage])
1617 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1618 idx, set->va,
1619 stage);
1620 }
1621 }
1622
1623 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1624 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1625 idx, set->va,
1626 MESA_SHADER_COMPUTE);
1627 }
1628
1629 static void
1630 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1631 {
1632 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1633 unsigned bo_offset;
1634
1635 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1636 set->mapped_ptr,
1637 &bo_offset))
1638 return;
1639
1640 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1641 set->va += bo_offset;
1642 }
1643
1644 static void
1645 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1646 {
1647 uint32_t size = MAX_SETS * 2 * 4;
1648 uint32_t offset;
1649 void *ptr;
1650
1651 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1652 256, &offset, &ptr))
1653 return;
1654
1655 for (unsigned i = 0; i < MAX_SETS; i++) {
1656 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1657 uint64_t set_va = 0;
1658 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1659 if (set)
1660 set_va = set->va;
1661 uptr[0] = set_va & 0xffffffff;
1662 uptr[1] = set_va >> 32;
1663 }
1664
1665 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1666 va += offset;
1667
1668 if (cmd_buffer->state.pipeline) {
1669 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1670 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1671 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1672
1673 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1674 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1675 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1676
1677 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1678 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1679 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680
1681 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1682 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1683 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1684
1685 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1686 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1687 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1688 }
1689
1690 if (cmd_buffer->state.compute_pipeline)
1691 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1692 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1693 }
1694
1695 static void
1696 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1697 VkShaderStageFlags stages)
1698 {
1699 unsigned i;
1700
1701 if (!cmd_buffer->state.descriptors_dirty)
1702 return;
1703
1704 if (cmd_buffer->state.push_descriptors_dirty)
1705 radv_flush_push_descriptors(cmd_buffer);
1706
1707 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1708 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1709 radv_flush_indirect_descriptor_sets(cmd_buffer);
1710 }
1711
1712 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1713 cmd_buffer->cs,
1714 MAX_SETS * MESA_SHADER_STAGES * 4);
1715
1716 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1717 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1718 if (!set)
1719 continue;
1720
1721 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1722 }
1723 cmd_buffer->state.descriptors_dirty = 0;
1724 cmd_buffer->state.push_descriptors_dirty = false;
1725
1726 radv_save_descriptors(cmd_buffer);
1727
1728 assert(cmd_buffer->cs->cdw <= cdw_max);
1729 }
1730
1731 static void
1732 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1733 struct radv_pipeline *pipeline,
1734 VkShaderStageFlags stages)
1735 {
1736 struct radv_pipeline_layout *layout = pipeline->layout;
1737 unsigned offset;
1738 void *ptr;
1739 uint64_t va;
1740
1741 stages &= cmd_buffer->push_constant_stages;
1742 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1743 return;
1744
1745 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1746 16 * layout->dynamic_offset_count,
1747 256, &offset, &ptr))
1748 return;
1749
1750 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1751 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1752 16 * layout->dynamic_offset_count);
1753
1754 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1755 va += offset;
1756
1757 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1758 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1759
1760 radv_foreach_stage(stage, stages) {
1761 if (pipeline->shaders[stage]) {
1762 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1763 AC_UD_PUSH_CONSTANTS, va);
1764 }
1765 }
1766
1767 cmd_buffer->push_constant_stages &= ~stages;
1768 assert(cmd_buffer->cs->cdw <= cdw_max);
1769 }
1770
1771 static bool
1772 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1773 {
1774 struct radv_device *device = cmd_buffer->device;
1775
1776 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1777 cmd_buffer->state.pipeline->vertex_elements.count &&
1778 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1779 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1780 unsigned vb_offset;
1781 void *vb_ptr;
1782 uint32_t i = 0;
1783 uint32_t count = velems->count;
1784 uint64_t va;
1785
1786 /* allocate some descriptor state for vertex buffers */
1787 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1788 &vb_offset, &vb_ptr))
1789 return false;
1790
1791 for (i = 0; i < count; i++) {
1792 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1793 uint32_t offset;
1794 int vb = velems->binding[i];
1795 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1796 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1797
1798 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1799 va = radv_buffer_get_va(buffer->bo);
1800
1801 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1802 va += offset + buffer->offset;
1803 desc[0] = va;
1804 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1805 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1806 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1807 else
1808 desc[2] = buffer->size - offset;
1809 desc[3] = velems->rsrc_word3[i];
1810 }
1811
1812 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1813 va += vb_offset;
1814
1815 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1816 AC_UD_VS_VERTEX_BUFFERS, va);
1817 }
1818 cmd_buffer->state.vb_dirty = false;
1819
1820 return true;
1821 }
1822
1823 static bool
1824 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1825 {
1826 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1827 return false;
1828
1829 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1830 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1831 VK_SHADER_STAGE_ALL_GRAPHICS);
1832
1833 return true;
1834 }
1835
1836 static void
1837 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1838 bool instanced_draw, bool indirect_draw,
1839 uint32_t draw_vertex_count)
1840 {
1841 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1842 struct radv_cmd_state *state = &cmd_buffer->state;
1843 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1844 uint32_t ia_multi_vgt_param;
1845 int32_t primitive_reset_en;
1846
1847 /* Draw state. */
1848 ia_multi_vgt_param =
1849 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1850 indirect_draw, draw_vertex_count);
1851
1852 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1853 if (info->chip_class >= GFX9) {
1854 radeon_set_uconfig_reg_idx(cs,
1855 R_030960_IA_MULTI_VGT_PARAM,
1856 4, ia_multi_vgt_param);
1857 } else if (info->chip_class >= CIK) {
1858 radeon_set_context_reg_idx(cs,
1859 R_028AA8_IA_MULTI_VGT_PARAM,
1860 1, ia_multi_vgt_param);
1861 } else {
1862 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1863 ia_multi_vgt_param);
1864 }
1865 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1866 }
1867
1868 /* Primitive restart. */
1869 primitive_reset_en =
1870 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1871
1872 if (primitive_reset_en != state->last_primitive_reset_en) {
1873 state->last_primitive_reset_en = primitive_reset_en;
1874 if (info->chip_class >= GFX9) {
1875 radeon_set_uconfig_reg(cs,
1876 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1877 primitive_reset_en);
1878 } else {
1879 radeon_set_context_reg(cs,
1880 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1881 primitive_reset_en);
1882 }
1883 }
1884
1885 if (primitive_reset_en) {
1886 uint32_t primitive_reset_index =
1887 state->index_type ? 0xffffffffu : 0xffffu;
1888
1889 if (primitive_reset_index != state->last_primitive_reset_index) {
1890 radeon_set_context_reg(cs,
1891 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1892 primitive_reset_index);
1893 state->last_primitive_reset_index = primitive_reset_index;
1894 }
1895 }
1896 }
1897
1898 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1899 VkPipelineStageFlags src_stage_mask)
1900 {
1901 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1902 VK_PIPELINE_STAGE_TRANSFER_BIT |
1903 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1904 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1905 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1906 }
1907
1908 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1909 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1910 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1911 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1912 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1913 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1914 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1915 VK_PIPELINE_STAGE_TRANSFER_BIT |
1916 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1917 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1918 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1919 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1920 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1921 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1922 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1924 }
1925 }
1926
1927 static enum radv_cmd_flush_bits
1928 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1929 VkAccessFlags src_flags)
1930 {
1931 enum radv_cmd_flush_bits flush_bits = 0;
1932 uint32_t b;
1933 for_each_bit(b, src_flags) {
1934 switch ((VkAccessFlagBits)(1 << b)) {
1935 case VK_ACCESS_SHADER_WRITE_BIT:
1936 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1937 break;
1938 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1939 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1940 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1941 break;
1942 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1943 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1944 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1945 break;
1946 case VK_ACCESS_TRANSFER_WRITE_BIT:
1947 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1948 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1949 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1950 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1951 RADV_CMD_FLAG_INV_GLOBAL_L2;
1952 break;
1953 default:
1954 break;
1955 }
1956 }
1957 return flush_bits;
1958 }
1959
1960 static enum radv_cmd_flush_bits
1961 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1962 VkAccessFlags dst_flags,
1963 struct radv_image *image)
1964 {
1965 enum radv_cmd_flush_bits flush_bits = 0;
1966 uint32_t b;
1967 for_each_bit(b, dst_flags) {
1968 switch ((VkAccessFlagBits)(1 << b)) {
1969 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1970 case VK_ACCESS_INDEX_READ_BIT:
1971 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1972 break;
1973 case VK_ACCESS_UNIFORM_READ_BIT:
1974 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1975 break;
1976 case VK_ACCESS_SHADER_READ_BIT:
1977 case VK_ACCESS_TRANSFER_READ_BIT:
1978 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1979 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1980 RADV_CMD_FLAG_INV_GLOBAL_L2;
1981 break;
1982 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1983 /* TODO: change to image && when the image gets passed
1984 * through from the subpass. */
1985 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1986 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1987 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1988 break;
1989 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1990 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1991 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1992 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1993 break;
1994 default:
1995 break;
1996 }
1997 }
1998 return flush_bits;
1999 }
2000
2001 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2002 {
2003 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2004 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2005 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2006 NULL);
2007 }
2008
2009 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2010 VkAttachmentReference att)
2011 {
2012 unsigned idx = att.attachment;
2013 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2014 VkImageSubresourceRange range;
2015 range.aspectMask = 0;
2016 range.baseMipLevel = view->base_mip;
2017 range.levelCount = 1;
2018 range.baseArrayLayer = view->base_layer;
2019 range.layerCount = cmd_buffer->state.framebuffer->layers;
2020
2021 radv_handle_image_transition(cmd_buffer,
2022 view->image,
2023 cmd_buffer->state.attachments[idx].current_layout,
2024 att.layout, 0, 0, &range,
2025 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2026
2027 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2028
2029
2030 }
2031
2032 void
2033 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2034 const struct radv_subpass *subpass, bool transitions)
2035 {
2036 if (transitions) {
2037 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2038
2039 for (unsigned i = 0; i < subpass->color_count; ++i) {
2040 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2041 radv_handle_subpass_image_transition(cmd_buffer,
2042 subpass->color_attachments[i]);
2043 }
2044
2045 for (unsigned i = 0; i < subpass->input_count; ++i) {
2046 radv_handle_subpass_image_transition(cmd_buffer,
2047 subpass->input_attachments[i]);
2048 }
2049
2050 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2051 radv_handle_subpass_image_transition(cmd_buffer,
2052 subpass->depth_stencil_attachment);
2053 }
2054 }
2055
2056 cmd_buffer->state.subpass = subpass;
2057
2058 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2059 }
2060
2061 static VkResult
2062 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2063 struct radv_render_pass *pass,
2064 const VkRenderPassBeginInfo *info)
2065 {
2066 struct radv_cmd_state *state = &cmd_buffer->state;
2067
2068 if (pass->attachment_count == 0) {
2069 state->attachments = NULL;
2070 return VK_SUCCESS;
2071 }
2072
2073 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2074 pass->attachment_count *
2075 sizeof(state->attachments[0]),
2076 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2077 if (state->attachments == NULL) {
2078 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2079 return cmd_buffer->record_result;
2080 }
2081
2082 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2083 struct radv_render_pass_attachment *att = &pass->attachments[i];
2084 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2085 VkImageAspectFlags clear_aspects = 0;
2086
2087 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2088 /* color attachment */
2089 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2090 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2091 }
2092 } else {
2093 /* depthstencil attachment */
2094 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2095 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2096 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2097 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2098 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2099 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2100 }
2101 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2102 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2103 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2104 }
2105 }
2106
2107 state->attachments[i].pending_clear_aspects = clear_aspects;
2108 state->attachments[i].cleared_views = 0;
2109 if (clear_aspects && info) {
2110 assert(info->clearValueCount > i);
2111 state->attachments[i].clear_value = info->pClearValues[i];
2112 }
2113
2114 state->attachments[i].current_layout = att->initial_layout;
2115 }
2116
2117 return VK_SUCCESS;
2118 }
2119
2120 VkResult radv_AllocateCommandBuffers(
2121 VkDevice _device,
2122 const VkCommandBufferAllocateInfo *pAllocateInfo,
2123 VkCommandBuffer *pCommandBuffers)
2124 {
2125 RADV_FROM_HANDLE(radv_device, device, _device);
2126 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2127
2128 VkResult result = VK_SUCCESS;
2129 uint32_t i;
2130
2131 memset(pCommandBuffers, 0,
2132 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2133
2134 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2135
2136 if (!list_empty(&pool->free_cmd_buffers)) {
2137 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2138
2139 list_del(&cmd_buffer->pool_link);
2140 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2141
2142 result = radv_reset_cmd_buffer(cmd_buffer);
2143 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2144 cmd_buffer->level = pAllocateInfo->level;
2145
2146 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2147 } else {
2148 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2149 &pCommandBuffers[i]);
2150 }
2151 if (result != VK_SUCCESS)
2152 break;
2153 }
2154
2155 if (result != VK_SUCCESS)
2156 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2157 i, pCommandBuffers);
2158
2159 return result;
2160 }
2161
2162 void radv_FreeCommandBuffers(
2163 VkDevice device,
2164 VkCommandPool commandPool,
2165 uint32_t commandBufferCount,
2166 const VkCommandBuffer *pCommandBuffers)
2167 {
2168 for (uint32_t i = 0; i < commandBufferCount; i++) {
2169 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2170
2171 if (cmd_buffer) {
2172 if (cmd_buffer->pool) {
2173 list_del(&cmd_buffer->pool_link);
2174 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2175 } else
2176 radv_cmd_buffer_destroy(cmd_buffer);
2177
2178 }
2179 }
2180 }
2181
2182 VkResult radv_ResetCommandBuffer(
2183 VkCommandBuffer commandBuffer,
2184 VkCommandBufferResetFlags flags)
2185 {
2186 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2187 return radv_reset_cmd_buffer(cmd_buffer);
2188 }
2189
2190 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2191 {
2192 struct radv_device *device = cmd_buffer->device;
2193 if (device->gfx_init) {
2194 uint64_t va = radv_buffer_get_va(device->gfx_init);
2195 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2196 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2197 radeon_emit(cmd_buffer->cs, va);
2198 radeon_emit(cmd_buffer->cs, va >> 32);
2199 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2200 } else
2201 si_init_config(cmd_buffer);
2202 }
2203
2204 VkResult radv_BeginCommandBuffer(
2205 VkCommandBuffer commandBuffer,
2206 const VkCommandBufferBeginInfo *pBeginInfo)
2207 {
2208 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2209 VkResult result;
2210
2211 result = radv_reset_cmd_buffer(cmd_buffer);
2212 if (result != VK_SUCCESS)
2213 return result;
2214
2215 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2216 cmd_buffer->state.last_primitive_reset_en = -1;
2217 cmd_buffer->usage_flags = pBeginInfo->flags;
2218
2219 /* setup initial configuration into command buffer */
2220 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2221 switch (cmd_buffer->queue_family_index) {
2222 case RADV_QUEUE_GENERAL:
2223 emit_gfx_buffer_state(cmd_buffer);
2224 break;
2225 case RADV_QUEUE_COMPUTE:
2226 si_init_compute(cmd_buffer);
2227 break;
2228 case RADV_QUEUE_TRANSFER:
2229 default:
2230 break;
2231 }
2232 }
2233
2234 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2235 assert(pBeginInfo->pInheritanceInfo);
2236 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2237 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2238
2239 struct radv_subpass *subpass =
2240 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2241
2242 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2243 if (result != VK_SUCCESS)
2244 return result;
2245
2246 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2247 }
2248
2249 radv_cmd_buffer_trace_emit(cmd_buffer);
2250 return result;
2251 }
2252
2253 void radv_CmdBindVertexBuffers(
2254 VkCommandBuffer commandBuffer,
2255 uint32_t firstBinding,
2256 uint32_t bindingCount,
2257 const VkBuffer* pBuffers,
2258 const VkDeviceSize* pOffsets)
2259 {
2260 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2261 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2262 bool changed = false;
2263
2264 /* We have to defer setting up vertex buffer since we need the buffer
2265 * stride from the pipeline. */
2266
2267 assert(firstBinding + bindingCount <= MAX_VBS);
2268 for (uint32_t i = 0; i < bindingCount; i++) {
2269 uint32_t idx = firstBinding + i;
2270
2271 if (!changed &&
2272 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2273 vb[idx].offset != pOffsets[i])) {
2274 changed = true;
2275 }
2276
2277 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2278 vb[idx].offset = pOffsets[i];
2279 }
2280
2281 if (!changed) {
2282 /* No state changes. */
2283 return;
2284 }
2285
2286 cmd_buffer->state.vb_dirty = true;
2287 }
2288
2289 void radv_CmdBindIndexBuffer(
2290 VkCommandBuffer commandBuffer,
2291 VkBuffer buffer,
2292 VkDeviceSize offset,
2293 VkIndexType indexType)
2294 {
2295 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2296 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2297
2298 if (cmd_buffer->state.index_buffer == index_buffer &&
2299 cmd_buffer->state.index_offset == offset &&
2300 cmd_buffer->state.index_type == indexType) {
2301 /* No state changes. */
2302 return;
2303 }
2304
2305 cmd_buffer->state.index_buffer = index_buffer;
2306 cmd_buffer->state.index_offset = offset;
2307 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2308 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2309 cmd_buffer->state.index_va += index_buffer->offset + offset;
2310
2311 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2312 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2313 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2314 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2315 }
2316
2317
2318 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2319 struct radv_descriptor_set *set,
2320 unsigned idx)
2321 {
2322 struct radeon_winsys *ws = cmd_buffer->device->ws;
2323
2324 cmd_buffer->state.descriptors[idx] = set;
2325 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2326 if (!set)
2327 return;
2328
2329 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2330
2331 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2332 if (set->descriptors[j])
2333 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2334
2335 if(set->bo)
2336 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2337 }
2338
2339 void radv_CmdBindDescriptorSets(
2340 VkCommandBuffer commandBuffer,
2341 VkPipelineBindPoint pipelineBindPoint,
2342 VkPipelineLayout _layout,
2343 uint32_t firstSet,
2344 uint32_t descriptorSetCount,
2345 const VkDescriptorSet* pDescriptorSets,
2346 uint32_t dynamicOffsetCount,
2347 const uint32_t* pDynamicOffsets)
2348 {
2349 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2350 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2351 unsigned dyn_idx = 0;
2352
2353 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2354 unsigned idx = i + firstSet;
2355 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2356 radv_bind_descriptor_set(cmd_buffer, set, idx);
2357
2358 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2359 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2360 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2361 assert(dyn_idx < dynamicOffsetCount);
2362
2363 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2364 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2365 dst[0] = va;
2366 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2367 dst[2] = range->size;
2368 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2369 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2370 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2371 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2372 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2373 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2374 cmd_buffer->push_constant_stages |=
2375 set->layout->dynamic_shader_stages;
2376 }
2377 }
2378 }
2379
2380 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2381 struct radv_descriptor_set *set,
2382 struct radv_descriptor_set_layout *layout)
2383 {
2384 set->size = layout->size;
2385 set->layout = layout;
2386
2387 if (cmd_buffer->push_descriptors.capacity < set->size) {
2388 size_t new_size = MAX2(set->size, 1024);
2389 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2390 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2391
2392 free(set->mapped_ptr);
2393 set->mapped_ptr = malloc(new_size);
2394
2395 if (!set->mapped_ptr) {
2396 cmd_buffer->push_descriptors.capacity = 0;
2397 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2398 return false;
2399 }
2400
2401 cmd_buffer->push_descriptors.capacity = new_size;
2402 }
2403
2404 return true;
2405 }
2406
2407 void radv_meta_push_descriptor_set(
2408 struct radv_cmd_buffer* cmd_buffer,
2409 VkPipelineBindPoint pipelineBindPoint,
2410 VkPipelineLayout _layout,
2411 uint32_t set,
2412 uint32_t descriptorWriteCount,
2413 const VkWriteDescriptorSet* pDescriptorWrites)
2414 {
2415 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2416 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2417 unsigned bo_offset;
2418
2419 assert(set == 0);
2420 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2421
2422 push_set->size = layout->set[set].layout->size;
2423 push_set->layout = layout->set[set].layout;
2424
2425 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2426 &bo_offset,
2427 (void**) &push_set->mapped_ptr))
2428 return;
2429
2430 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2431 push_set->va += bo_offset;
2432
2433 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2434 radv_descriptor_set_to_handle(push_set),
2435 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2436
2437 cmd_buffer->state.descriptors[set] = push_set;
2438 cmd_buffer->state.descriptors_dirty |= (1u << set);
2439 }
2440
2441 void radv_CmdPushDescriptorSetKHR(
2442 VkCommandBuffer commandBuffer,
2443 VkPipelineBindPoint pipelineBindPoint,
2444 VkPipelineLayout _layout,
2445 uint32_t set,
2446 uint32_t descriptorWriteCount,
2447 const VkWriteDescriptorSet* pDescriptorWrites)
2448 {
2449 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2451 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2452
2453 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2454
2455 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2456 return;
2457
2458 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2459 radv_descriptor_set_to_handle(push_set),
2460 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2461
2462 cmd_buffer->state.descriptors[set] = push_set;
2463 cmd_buffer->state.descriptors_dirty |= (1u << set);
2464 cmd_buffer->state.push_descriptors_dirty = true;
2465 }
2466
2467 void radv_CmdPushDescriptorSetWithTemplateKHR(
2468 VkCommandBuffer commandBuffer,
2469 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2470 VkPipelineLayout _layout,
2471 uint32_t set,
2472 const void* pData)
2473 {
2474 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2475 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2476 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2477
2478 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2479
2480 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2481 return;
2482
2483 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2484 descriptorUpdateTemplate, pData);
2485
2486 cmd_buffer->state.descriptors[set] = push_set;
2487 cmd_buffer->state.descriptors_dirty |= (1u << set);
2488 cmd_buffer->state.push_descriptors_dirty = true;
2489 }
2490
2491 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2492 VkPipelineLayout layout,
2493 VkShaderStageFlags stageFlags,
2494 uint32_t offset,
2495 uint32_t size,
2496 const void* pValues)
2497 {
2498 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2499 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2500 cmd_buffer->push_constant_stages |= stageFlags;
2501 }
2502
2503 VkResult radv_EndCommandBuffer(
2504 VkCommandBuffer commandBuffer)
2505 {
2506 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2507
2508 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2509 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2510 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2511 si_emit_cache_flush(cmd_buffer);
2512 }
2513
2514 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2515 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2516
2517 return cmd_buffer->record_result;
2518 }
2519
2520 static void
2521 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2522 {
2523 struct radv_shader_variant *compute_shader;
2524 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2525 uint64_t va;
2526
2527 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2528 return;
2529
2530 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2531
2532 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2533 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2534
2535 radv_emit_shader_prefetch(cmd_buffer, compute_shader);
2536
2537 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2538 cmd_buffer->cs, 16);
2539
2540 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2541 radeon_emit(cmd_buffer->cs, va >> 8);
2542 radeon_emit(cmd_buffer->cs, va >> 40);
2543
2544 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2545 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2546 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2547
2548
2549 cmd_buffer->compute_scratch_size_needed =
2550 MAX2(cmd_buffer->compute_scratch_size_needed,
2551 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2552
2553 /* change these once we have scratch support */
2554 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2555 S_00B860_WAVES(pipeline->max_waves) |
2556 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2557
2558 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2559 radeon_emit(cmd_buffer->cs,
2560 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2561 radeon_emit(cmd_buffer->cs,
2562 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2563 radeon_emit(cmd_buffer->cs,
2564 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2565
2566 assert(cmd_buffer->cs->cdw <= cdw_max);
2567 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2568 }
2569
2570 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2571 {
2572 for (unsigned i = 0; i < MAX_SETS; i++) {
2573 if (cmd_buffer->state.descriptors[i])
2574 cmd_buffer->state.descriptors_dirty |= (1u << i);
2575 }
2576 }
2577
2578 void radv_CmdBindPipeline(
2579 VkCommandBuffer commandBuffer,
2580 VkPipelineBindPoint pipelineBindPoint,
2581 VkPipeline _pipeline)
2582 {
2583 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2585
2586 switch (pipelineBindPoint) {
2587 case VK_PIPELINE_BIND_POINT_COMPUTE:
2588 if (cmd_buffer->state.compute_pipeline == pipeline)
2589 return;
2590 radv_mark_descriptor_sets_dirty(cmd_buffer);
2591
2592 cmd_buffer->state.compute_pipeline = pipeline;
2593 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2594 break;
2595 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2596 if (cmd_buffer->state.pipeline == pipeline)
2597 return;
2598 radv_mark_descriptor_sets_dirty(cmd_buffer);
2599
2600 cmd_buffer->state.pipeline = pipeline;
2601 if (!pipeline)
2602 break;
2603
2604 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2605 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2606
2607 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2608
2609 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2610 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2611 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2612 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2613
2614 if (radv_pipeline_has_tess(pipeline))
2615 cmd_buffer->tess_rings_needed = true;
2616
2617 if (radv_pipeline_has_gs(pipeline)) {
2618 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2619 AC_UD_SCRATCH_RING_OFFSETS);
2620 if (cmd_buffer->ring_offsets_idx == -1)
2621 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2622 else if (loc->sgpr_idx != -1)
2623 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2624 }
2625 break;
2626 default:
2627 assert(!"invalid bind point");
2628 break;
2629 }
2630 }
2631
2632 void radv_CmdSetViewport(
2633 VkCommandBuffer commandBuffer,
2634 uint32_t firstViewport,
2635 uint32_t viewportCount,
2636 const VkViewport* pViewports)
2637 {
2638 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2639 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2640
2641 assert(firstViewport < MAX_VIEWPORTS);
2642 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2643
2644 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2645 pViewports, viewportCount * sizeof(*pViewports));
2646
2647 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2648 }
2649
2650 void radv_CmdSetScissor(
2651 VkCommandBuffer commandBuffer,
2652 uint32_t firstScissor,
2653 uint32_t scissorCount,
2654 const VkRect2D* pScissors)
2655 {
2656 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2657 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2658
2659 assert(firstScissor < MAX_SCISSORS);
2660 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2661
2662 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2663 pScissors, scissorCount * sizeof(*pScissors));
2664 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2665 }
2666
2667 void radv_CmdSetLineWidth(
2668 VkCommandBuffer commandBuffer,
2669 float lineWidth)
2670 {
2671 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2672 cmd_buffer->state.dynamic.line_width = lineWidth;
2673 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2674 }
2675
2676 void radv_CmdSetDepthBias(
2677 VkCommandBuffer commandBuffer,
2678 float depthBiasConstantFactor,
2679 float depthBiasClamp,
2680 float depthBiasSlopeFactor)
2681 {
2682 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2683
2684 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2685 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2686 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2687
2688 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2689 }
2690
2691 void radv_CmdSetBlendConstants(
2692 VkCommandBuffer commandBuffer,
2693 const float blendConstants[4])
2694 {
2695 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2696
2697 memcpy(cmd_buffer->state.dynamic.blend_constants,
2698 blendConstants, sizeof(float) * 4);
2699
2700 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2701 }
2702
2703 void radv_CmdSetDepthBounds(
2704 VkCommandBuffer commandBuffer,
2705 float minDepthBounds,
2706 float maxDepthBounds)
2707 {
2708 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2709
2710 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2711 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2712
2713 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2714 }
2715
2716 void radv_CmdSetStencilCompareMask(
2717 VkCommandBuffer commandBuffer,
2718 VkStencilFaceFlags faceMask,
2719 uint32_t compareMask)
2720 {
2721 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2722
2723 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2724 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2725 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2726 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2727
2728 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2729 }
2730
2731 void radv_CmdSetStencilWriteMask(
2732 VkCommandBuffer commandBuffer,
2733 VkStencilFaceFlags faceMask,
2734 uint32_t writeMask)
2735 {
2736 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2737
2738 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2739 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2740 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2741 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2742
2743 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2744 }
2745
2746 void radv_CmdSetStencilReference(
2747 VkCommandBuffer commandBuffer,
2748 VkStencilFaceFlags faceMask,
2749 uint32_t reference)
2750 {
2751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2752
2753 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2754 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2755 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2756 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2757
2758 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2759 }
2760
2761 void radv_CmdExecuteCommands(
2762 VkCommandBuffer commandBuffer,
2763 uint32_t commandBufferCount,
2764 const VkCommandBuffer* pCmdBuffers)
2765 {
2766 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2767
2768 assert(commandBufferCount > 0);
2769
2770 /* Emit pending flushes on primary prior to executing secondary */
2771 si_emit_cache_flush(primary);
2772
2773 for (uint32_t i = 0; i < commandBufferCount; i++) {
2774 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2775
2776 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2777 secondary->scratch_size_needed);
2778 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2779 secondary->compute_scratch_size_needed);
2780
2781 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2782 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2783 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2784 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2785 if (secondary->tess_rings_needed)
2786 primary->tess_rings_needed = true;
2787 if (secondary->sample_positions_needed)
2788 primary->sample_positions_needed = true;
2789
2790 if (secondary->ring_offsets_idx != -1) {
2791 if (primary->ring_offsets_idx == -1)
2792 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2793 else
2794 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2795 }
2796 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2797
2798
2799 /* When the secondary command buffer is compute only we don't
2800 * need to re-emit the current graphics pipeline.
2801 */
2802 if (secondary->state.emitted_pipeline) {
2803 primary->state.emitted_pipeline =
2804 secondary->state.emitted_pipeline;
2805 }
2806
2807 /* When the secondary command buffer is graphics only we don't
2808 * need to re-emit the current compute pipeline.
2809 */
2810 if (secondary->state.emitted_compute_pipeline) {
2811 primary->state.emitted_compute_pipeline =
2812 secondary->state.emitted_compute_pipeline;
2813 }
2814
2815 /* Only re-emit the draw packets when needed. */
2816 if (secondary->state.last_primitive_reset_en != -1) {
2817 primary->state.last_primitive_reset_en =
2818 secondary->state.last_primitive_reset_en;
2819 }
2820
2821 if (secondary->state.last_primitive_reset_index) {
2822 primary->state.last_primitive_reset_index =
2823 secondary->state.last_primitive_reset_index;
2824 }
2825
2826 if (secondary->state.last_ia_multi_vgt_param) {
2827 primary->state.last_ia_multi_vgt_param =
2828 secondary->state.last_ia_multi_vgt_param;
2829 }
2830 }
2831
2832 /* After executing commands from secondary buffers we have to dirty
2833 * some states.
2834 */
2835 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2836 RADV_CMD_DIRTY_INDEX_BUFFER |
2837 RADV_CMD_DIRTY_DYNAMIC_ALL;
2838 radv_mark_descriptor_sets_dirty(primary);
2839 }
2840
2841 VkResult radv_CreateCommandPool(
2842 VkDevice _device,
2843 const VkCommandPoolCreateInfo* pCreateInfo,
2844 const VkAllocationCallbacks* pAllocator,
2845 VkCommandPool* pCmdPool)
2846 {
2847 RADV_FROM_HANDLE(radv_device, device, _device);
2848 struct radv_cmd_pool *pool;
2849
2850 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2851 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2852 if (pool == NULL)
2853 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2854
2855 if (pAllocator)
2856 pool->alloc = *pAllocator;
2857 else
2858 pool->alloc = device->alloc;
2859
2860 list_inithead(&pool->cmd_buffers);
2861 list_inithead(&pool->free_cmd_buffers);
2862
2863 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2864
2865 *pCmdPool = radv_cmd_pool_to_handle(pool);
2866
2867 return VK_SUCCESS;
2868
2869 }
2870
2871 void radv_DestroyCommandPool(
2872 VkDevice _device,
2873 VkCommandPool commandPool,
2874 const VkAllocationCallbacks* pAllocator)
2875 {
2876 RADV_FROM_HANDLE(radv_device, device, _device);
2877 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2878
2879 if (!pool)
2880 return;
2881
2882 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2883 &pool->cmd_buffers, pool_link) {
2884 radv_cmd_buffer_destroy(cmd_buffer);
2885 }
2886
2887 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2888 &pool->free_cmd_buffers, pool_link) {
2889 radv_cmd_buffer_destroy(cmd_buffer);
2890 }
2891
2892 vk_free2(&device->alloc, pAllocator, pool);
2893 }
2894
2895 VkResult radv_ResetCommandPool(
2896 VkDevice device,
2897 VkCommandPool commandPool,
2898 VkCommandPoolResetFlags flags)
2899 {
2900 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2901 VkResult result;
2902
2903 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2904 &pool->cmd_buffers, pool_link) {
2905 result = radv_reset_cmd_buffer(cmd_buffer);
2906 if (result != VK_SUCCESS)
2907 return result;
2908 }
2909
2910 return VK_SUCCESS;
2911 }
2912
2913 void radv_TrimCommandPoolKHR(
2914 VkDevice device,
2915 VkCommandPool commandPool,
2916 VkCommandPoolTrimFlagsKHR flags)
2917 {
2918 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2919
2920 if (!pool)
2921 return;
2922
2923 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2924 &pool->free_cmd_buffers, pool_link) {
2925 radv_cmd_buffer_destroy(cmd_buffer);
2926 }
2927 }
2928
2929 void radv_CmdBeginRenderPass(
2930 VkCommandBuffer commandBuffer,
2931 const VkRenderPassBeginInfo* pRenderPassBegin,
2932 VkSubpassContents contents)
2933 {
2934 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2935 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2936 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2937
2938 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2939 cmd_buffer->cs, 2048);
2940 MAYBE_UNUSED VkResult result;
2941
2942 cmd_buffer->state.framebuffer = framebuffer;
2943 cmd_buffer->state.pass = pass;
2944 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2945
2946 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2947 if (result != VK_SUCCESS)
2948 return;
2949
2950 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2951 assert(cmd_buffer->cs->cdw <= cdw_max);
2952
2953 radv_cmd_buffer_clear_subpass(cmd_buffer);
2954 }
2955
2956 void radv_CmdNextSubpass(
2957 VkCommandBuffer commandBuffer,
2958 VkSubpassContents contents)
2959 {
2960 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2961
2962 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2963
2964 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2965 2048);
2966
2967 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2968 radv_cmd_buffer_clear_subpass(cmd_buffer);
2969 }
2970
2971 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2972 {
2973 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2974 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2975 if (!pipeline->shaders[stage])
2976 continue;
2977 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2978 if (loc->sgpr_idx == -1)
2979 continue;
2980 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2981 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2982
2983 }
2984 if (pipeline->gs_copy_shader) {
2985 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2986 if (loc->sgpr_idx != -1) {
2987 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2988 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2989 }
2990 }
2991 }
2992
2993 static void
2994 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2995 uint32_t vertex_count)
2996 {
2997 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2998 radeon_emit(cmd_buffer->cs, vertex_count);
2999 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3000 S_0287F0_USE_OPAQUE(0));
3001 }
3002
3003 static void
3004 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3005 uint64_t index_va,
3006 uint32_t index_count)
3007 {
3008 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3009 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3010 radeon_emit(cmd_buffer->cs, index_va);
3011 radeon_emit(cmd_buffer->cs, index_va >> 32);
3012 radeon_emit(cmd_buffer->cs, index_count);
3013 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3014 }
3015
3016 static void
3017 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3018 bool indexed,
3019 uint32_t draw_count,
3020 uint64_t count_va,
3021 uint32_t stride)
3022 {
3023 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3024 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3025 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3026 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3027 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3028 assert(base_reg);
3029
3030 if (draw_count == 1 && !count_va && !draw_id_enable) {
3031 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3032 PKT3_DRAW_INDIRECT, 3, false));
3033 radeon_emit(cs, 0);
3034 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3035 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3036 radeon_emit(cs, di_src_sel);
3037 } else {
3038 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3039 PKT3_DRAW_INDIRECT_MULTI,
3040 8, false));
3041 radeon_emit(cs, 0);
3042 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3043 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3044 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3045 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3046 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3047 radeon_emit(cs, draw_count); /* count */
3048 radeon_emit(cs, count_va); /* count_addr */
3049 radeon_emit(cs, count_va >> 32);
3050 radeon_emit(cs, stride); /* stride */
3051 radeon_emit(cs, di_src_sel);
3052 }
3053 }
3054
3055 struct radv_draw_info {
3056 /**
3057 * Number of vertices.
3058 */
3059 uint32_t count;
3060
3061 /**
3062 * Index of the first vertex.
3063 */
3064 int32_t vertex_offset;
3065
3066 /**
3067 * First instance id.
3068 */
3069 uint32_t first_instance;
3070
3071 /**
3072 * Number of instances.
3073 */
3074 uint32_t instance_count;
3075
3076 /**
3077 * First index (indexed draws only).
3078 */
3079 uint32_t first_index;
3080
3081 /**
3082 * Whether it's an indexed draw.
3083 */
3084 bool indexed;
3085
3086 /**
3087 * Indirect draw parameters resource.
3088 */
3089 struct radv_buffer *indirect;
3090 uint64_t indirect_offset;
3091 uint32_t stride;
3092
3093 /**
3094 * Draw count parameters resource.
3095 */
3096 struct radv_buffer *count_buffer;
3097 uint64_t count_buffer_offset;
3098 };
3099
3100 static void
3101 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3102 const struct radv_draw_info *info)
3103 {
3104 struct radv_cmd_state *state = &cmd_buffer->state;
3105 struct radeon_winsys *ws = cmd_buffer->device->ws;
3106 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3107
3108 if (info->indirect) {
3109 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3110 uint64_t count_va = 0;
3111
3112 va += info->indirect->offset + info->indirect_offset;
3113
3114 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3115
3116 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3117 radeon_emit(cs, 1);
3118 radeon_emit(cs, va);
3119 radeon_emit(cs, va >> 32);
3120
3121 if (info->count_buffer) {
3122 count_va = radv_buffer_get_va(info->count_buffer->bo);
3123 count_va += info->count_buffer->offset +
3124 info->count_buffer_offset;
3125
3126 ws->cs_add_buffer(cs, info->count_buffer->bo, 8);
3127 }
3128
3129 if (!state->subpass->view_mask) {
3130 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3131 info->indexed,
3132 info->count,
3133 count_va,
3134 info->stride);
3135 } else {
3136 unsigned i;
3137 for_each_bit(i, state->subpass->view_mask) {
3138 radv_emit_view_index(cmd_buffer, i);
3139
3140 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3141 info->indexed,
3142 info->count,
3143 count_va,
3144 info->stride);
3145 }
3146 }
3147 } else {
3148 assert(state->pipeline->graphics.vtx_base_sgpr);
3149 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3150 state->pipeline->graphics.vtx_emit_num);
3151 radeon_emit(cs, info->vertex_offset);
3152 radeon_emit(cs, info->first_instance);
3153 if (state->pipeline->graphics.vtx_emit_num == 3)
3154 radeon_emit(cs, 0);
3155
3156 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3157 radeon_emit(cs, info->instance_count);
3158
3159 if (info->indexed) {
3160 int index_size = state->index_type ? 4 : 2;
3161 uint64_t index_va;
3162
3163 index_va = state->index_va;
3164 index_va += info->first_index * index_size;
3165
3166 if (!state->subpass->view_mask) {
3167 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3168 index_va,
3169 info->count);
3170 } else {
3171 unsigned i;
3172 for_each_bit(i, state->subpass->view_mask) {
3173 radv_emit_view_index(cmd_buffer, i);
3174
3175 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3176 index_va,
3177 info->count);
3178 }
3179 }
3180 } else {
3181 if (!state->subpass->view_mask) {
3182 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3183 } else {
3184 unsigned i;
3185 for_each_bit(i, state->subpass->view_mask) {
3186 radv_emit_view_index(cmd_buffer, i);
3187
3188 radv_cs_emit_draw_packet(cmd_buffer,
3189 info->count);
3190 }
3191 }
3192 }
3193 }
3194 }
3195
3196 static void
3197 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3198 const struct radv_draw_info *info)
3199 {
3200 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3201 radv_emit_graphics_pipeline(cmd_buffer);
3202
3203 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3204 radv_emit_framebuffer_state(cmd_buffer);
3205
3206 if (info->indexed) {
3207 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3208 radv_emit_index_buffer(cmd_buffer);
3209 } else {
3210 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3211 * so the state must be re-emitted before the next indexed
3212 * draw.
3213 */
3214 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3215 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3216 }
3217
3218 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3219
3220 radv_emit_draw_registers(cmd_buffer, info->indexed,
3221 info->instance_count > 1, info->indirect,
3222 info->indirect ? 0 : info->count);
3223 }
3224
3225 static void
3226 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3227 const struct radv_draw_info *info)
3228 {
3229 bool pipeline_is_dirty =
3230 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3231 cmd_buffer->state.pipeline &&
3232 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3233
3234 MAYBE_UNUSED unsigned cdw_max =
3235 radeon_check_space(cmd_buffer->device->ws,
3236 cmd_buffer->cs, 4096);
3237
3238 /* Use optimal packet order based on whether we need to sync the
3239 * pipeline.
3240 */
3241 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3242 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3243 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3244 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3245 /* If we have to wait for idle, set all states first, so that
3246 * all SET packets are processed in parallel with previous draw
3247 * calls. Then upload descriptors, set shader pointers, and
3248 * draw, and prefetch at the end. This ensures that the time
3249 * the CUs are idle is very short. (there are only SET_SH
3250 * packets between the wait and the draw)
3251 */
3252 radv_emit_all_graphics_states(cmd_buffer, info);
3253 si_emit_cache_flush(cmd_buffer);
3254 /* <-- CUs are idle here --> */
3255
3256 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3257 return;
3258
3259 radv_emit_draw_packets(cmd_buffer, info);
3260 /* <-- CUs are busy here --> */
3261
3262 /* Start prefetches after the draw has been started. Both will
3263 * run in parallel, but starting the draw first is more
3264 * important.
3265 */
3266 if (pipeline_is_dirty) {
3267 radv_emit_shaders_prefetch(cmd_buffer,
3268 cmd_buffer->state.pipeline);
3269 }
3270 } else {
3271 /* If we don't wait for idle, start prefetches first, then set
3272 * states, and draw at the end.
3273 */
3274 si_emit_cache_flush(cmd_buffer);
3275
3276 if (pipeline_is_dirty) {
3277 radv_emit_shaders_prefetch(cmd_buffer,
3278 cmd_buffer->state.pipeline);
3279 }
3280
3281 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3282 return;
3283
3284 radv_emit_all_graphics_states(cmd_buffer, info);
3285 radv_emit_draw_packets(cmd_buffer, info);
3286 }
3287
3288 assert(cmd_buffer->cs->cdw <= cdw_max);
3289 radv_cmd_buffer_after_draw(cmd_buffer);
3290 }
3291
3292 void radv_CmdDraw(
3293 VkCommandBuffer commandBuffer,
3294 uint32_t vertexCount,
3295 uint32_t instanceCount,
3296 uint32_t firstVertex,
3297 uint32_t firstInstance)
3298 {
3299 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3300 struct radv_draw_info info = {};
3301
3302 info.count = vertexCount;
3303 info.instance_count = instanceCount;
3304 info.first_instance = firstInstance;
3305 info.vertex_offset = firstVertex;
3306
3307 radv_draw(cmd_buffer, &info);
3308 }
3309
3310 void radv_CmdDrawIndexed(
3311 VkCommandBuffer commandBuffer,
3312 uint32_t indexCount,
3313 uint32_t instanceCount,
3314 uint32_t firstIndex,
3315 int32_t vertexOffset,
3316 uint32_t firstInstance)
3317 {
3318 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3319 struct radv_draw_info info = {};
3320
3321 info.indexed = true;
3322 info.count = indexCount;
3323 info.instance_count = instanceCount;
3324 info.first_index = firstIndex;
3325 info.vertex_offset = vertexOffset;
3326 info.first_instance = firstInstance;
3327
3328 radv_draw(cmd_buffer, &info);
3329 }
3330
3331 void radv_CmdDrawIndirect(
3332 VkCommandBuffer commandBuffer,
3333 VkBuffer _buffer,
3334 VkDeviceSize offset,
3335 uint32_t drawCount,
3336 uint32_t stride)
3337 {
3338 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3339 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3340 struct radv_draw_info info = {};
3341
3342 info.count = drawCount;
3343 info.indirect = buffer;
3344 info.indirect_offset = offset;
3345 info.stride = stride;
3346
3347 radv_draw(cmd_buffer, &info);
3348 }
3349
3350 void radv_CmdDrawIndexedIndirect(
3351 VkCommandBuffer commandBuffer,
3352 VkBuffer _buffer,
3353 VkDeviceSize offset,
3354 uint32_t drawCount,
3355 uint32_t stride)
3356 {
3357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3358 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3359 struct radv_draw_info info = {};
3360
3361 info.indexed = true;
3362 info.count = drawCount;
3363 info.indirect = buffer;
3364 info.indirect_offset = offset;
3365 info.stride = stride;
3366
3367 radv_draw(cmd_buffer, &info);
3368 }
3369
3370 void radv_CmdDrawIndirectCountAMD(
3371 VkCommandBuffer commandBuffer,
3372 VkBuffer _buffer,
3373 VkDeviceSize offset,
3374 VkBuffer _countBuffer,
3375 VkDeviceSize countBufferOffset,
3376 uint32_t maxDrawCount,
3377 uint32_t stride)
3378 {
3379 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3380 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3381 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3382 struct radv_draw_info info = {};
3383
3384 info.count = maxDrawCount;
3385 info.indirect = buffer;
3386 info.indirect_offset = offset;
3387 info.count_buffer = count_buffer;
3388 info.count_buffer_offset = countBufferOffset;
3389 info.stride = stride;
3390
3391 radv_draw(cmd_buffer, &info);
3392 }
3393
3394 void radv_CmdDrawIndexedIndirectCountAMD(
3395 VkCommandBuffer commandBuffer,
3396 VkBuffer _buffer,
3397 VkDeviceSize offset,
3398 VkBuffer _countBuffer,
3399 VkDeviceSize countBufferOffset,
3400 uint32_t maxDrawCount,
3401 uint32_t stride)
3402 {
3403 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3404 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3405 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3406 struct radv_draw_info info = {};
3407
3408 info.indexed = true;
3409 info.count = maxDrawCount;
3410 info.indirect = buffer;
3411 info.indirect_offset = offset;
3412 info.count_buffer = count_buffer;
3413 info.count_buffer_offset = countBufferOffset;
3414 info.stride = stride;
3415
3416 radv_draw(cmd_buffer, &info);
3417 }
3418
3419 struct radv_dispatch_info {
3420 /**
3421 * Determine the layout of the grid (in block units) to be used.
3422 */
3423 uint32_t blocks[3];
3424
3425 /**
3426 * Whether it's an unaligned compute dispatch.
3427 */
3428 bool unaligned;
3429
3430 /**
3431 * Indirect compute parameters resource.
3432 */
3433 struct radv_buffer *indirect;
3434 uint64_t indirect_offset;
3435 };
3436
3437 static void
3438 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3439 const struct radv_dispatch_info *info)
3440 {
3441 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3442 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3443 struct radeon_winsys *ws = cmd_buffer->device->ws;
3444 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3445 struct ac_userdata_info *loc;
3446 unsigned dispatch_initiator;
3447 uint8_t grid_used;
3448
3449 grid_used = compute_shader->info.info.cs.grid_components_used;
3450
3451 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3452 AC_UD_CS_GRID_SIZE);
3453
3454 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3455
3456 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3457 S_00B800_FORCE_START_AT_000(1);
3458
3459 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3460 /* If the KMD allows it (there is a KMD hw register for it),
3461 * allow launching waves out-of-order.
3462 */
3463 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3464 }
3465
3466 if (info->indirect) {
3467 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3468
3469 va += info->indirect->offset + info->indirect_offset;
3470
3471 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3472
3473 if (loc->sgpr_idx != -1) {
3474 for (unsigned i = 0; i < grid_used; ++i) {
3475 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3476 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3477 COPY_DATA_DST_SEL(COPY_DATA_REG));
3478 radeon_emit(cs, (va + 4 * i));
3479 radeon_emit(cs, (va + 4 * i) >> 32);
3480 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3481 + loc->sgpr_idx * 4) >> 2) + i);
3482 radeon_emit(cs, 0);
3483 }
3484 }
3485
3486 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3487 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3488 PKT3_SHADER_TYPE_S(1));
3489 radeon_emit(cs, va);
3490 radeon_emit(cs, va >> 32);
3491 radeon_emit(cs, dispatch_initiator);
3492 } else {
3493 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3494 PKT3_SHADER_TYPE_S(1));
3495 radeon_emit(cs, 1);
3496 radeon_emit(cs, va);
3497 radeon_emit(cs, va >> 32);
3498
3499 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3500 PKT3_SHADER_TYPE_S(1));
3501 radeon_emit(cs, 0);
3502 radeon_emit(cs, dispatch_initiator);
3503 }
3504 } else {
3505 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3506
3507 if (info->unaligned) {
3508 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3509 unsigned remainder[3];
3510
3511 /* If aligned, these should be an entire block size,
3512 * not 0.
3513 */
3514 remainder[0] = blocks[0] + cs_block_size[0] -
3515 align_u32_npot(blocks[0], cs_block_size[0]);
3516 remainder[1] = blocks[1] + cs_block_size[1] -
3517 align_u32_npot(blocks[1], cs_block_size[1]);
3518 remainder[2] = blocks[2] + cs_block_size[2] -
3519 align_u32_npot(blocks[2], cs_block_size[2]);
3520
3521 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3522 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3523 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3524
3525 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3526 radeon_emit(cs,
3527 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3528 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3529 radeon_emit(cs,
3530 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3531 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3532 radeon_emit(cs,
3533 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3534 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3535
3536 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3537 }
3538
3539 if (loc->sgpr_idx != -1) {
3540 assert(!loc->indirect);
3541 assert(loc->num_sgprs == grid_used);
3542
3543 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3544 loc->sgpr_idx * 4, grid_used);
3545 radeon_emit(cs, blocks[0]);
3546 if (grid_used > 1)
3547 radeon_emit(cs, blocks[1]);
3548 if (grid_used > 2)
3549 radeon_emit(cs, blocks[2]);
3550 }
3551
3552 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3553 PKT3_SHADER_TYPE_S(1));
3554 radeon_emit(cs, blocks[0]);
3555 radeon_emit(cs, blocks[1]);
3556 radeon_emit(cs, blocks[2]);
3557 radeon_emit(cs, dispatch_initiator);
3558 }
3559
3560 assert(cmd_buffer->cs->cdw <= cdw_max);
3561 }
3562
3563 static void
3564 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3565 const struct radv_dispatch_info *info)
3566 {
3567 radv_emit_compute_pipeline(cmd_buffer);
3568
3569 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3570 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3571 VK_SHADER_STAGE_COMPUTE_BIT);
3572
3573 si_emit_cache_flush(cmd_buffer);
3574
3575 radv_emit_dispatch_packets(cmd_buffer, info);
3576
3577 radv_cmd_buffer_after_draw(cmd_buffer);
3578 }
3579
3580 void radv_CmdDispatch(
3581 VkCommandBuffer commandBuffer,
3582 uint32_t x,
3583 uint32_t y,
3584 uint32_t z)
3585 {
3586 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3587 struct radv_dispatch_info info = {};
3588
3589 info.blocks[0] = x;
3590 info.blocks[1] = y;
3591 info.blocks[2] = z;
3592
3593 radv_dispatch(cmd_buffer, &info);
3594 }
3595
3596 void radv_CmdDispatchIndirect(
3597 VkCommandBuffer commandBuffer,
3598 VkBuffer _buffer,
3599 VkDeviceSize offset)
3600 {
3601 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3602 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3603 struct radv_dispatch_info info = {};
3604
3605 info.indirect = buffer;
3606 info.indirect_offset = offset;
3607
3608 radv_dispatch(cmd_buffer, &info);
3609 }
3610
3611 void radv_unaligned_dispatch(
3612 struct radv_cmd_buffer *cmd_buffer,
3613 uint32_t x,
3614 uint32_t y,
3615 uint32_t z)
3616 {
3617 struct radv_dispatch_info info = {};
3618
3619 info.blocks[0] = x;
3620 info.blocks[1] = y;
3621 info.blocks[2] = z;
3622 info.unaligned = 1;
3623
3624 radv_dispatch(cmd_buffer, &info);
3625 }
3626
3627 void radv_CmdEndRenderPass(
3628 VkCommandBuffer commandBuffer)
3629 {
3630 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3631
3632 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3633
3634 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3635
3636 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3637 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3638 radv_handle_subpass_image_transition(cmd_buffer,
3639 (VkAttachmentReference){i, layout});
3640 }
3641
3642 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3643
3644 cmd_buffer->state.pass = NULL;
3645 cmd_buffer->state.subpass = NULL;
3646 cmd_buffer->state.attachments = NULL;
3647 cmd_buffer->state.framebuffer = NULL;
3648 }
3649
3650 /*
3651 * For HTILE we have the following interesting clear words:
3652 * 0x0000030f: Uncompressed.
3653 * 0xfffffff0: Clear depth to 1.0
3654 * 0x00000000: Clear depth to 0.0
3655 */
3656 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3657 struct radv_image *image,
3658 const VkImageSubresourceRange *range,
3659 uint32_t clear_word)
3660 {
3661 assert(range->baseMipLevel == 0);
3662 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3663 unsigned layer_count = radv_get_layerCount(image, range);
3664 uint64_t size = image->surface.htile_slice_size * layer_count;
3665 uint64_t offset = image->offset + image->htile_offset +
3666 image->surface.htile_slice_size * range->baseArrayLayer;
3667 struct radv_cmd_state *state = &cmd_buffer->state;
3668
3669 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3670 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3671
3672 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3673 size, clear_word);
3674
3675 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3676 }
3677
3678 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3679 struct radv_image *image,
3680 VkImageLayout src_layout,
3681 VkImageLayout dst_layout,
3682 unsigned src_queue_mask,
3683 unsigned dst_queue_mask,
3684 const VkImageSubresourceRange *range,
3685 VkImageAspectFlags pending_clears)
3686 {
3687 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3688 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3689 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3690 cmd_buffer->state.render_area.extent.width == image->info.width &&
3691 cmd_buffer->state.render_area.extent.height == image->info.height) {
3692 /* The clear will initialize htile. */
3693 return;
3694 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3695 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3696 /* TODO: merge with the clear if applicable */
3697 radv_initialize_htile(cmd_buffer, image, range, 0);
3698 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3699 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3700 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3701 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3702 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3703 VkImageSubresourceRange local_range = *range;
3704 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3705 local_range.baseMipLevel = 0;
3706 local_range.levelCount = 1;
3707
3708 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3709 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3710
3711 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3712
3713 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3714 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3715 }
3716 }
3717
3718 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3719 struct radv_image *image, uint32_t value)
3720 {
3721 struct radv_cmd_state *state = &cmd_buffer->state;
3722
3723 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3724 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3725
3726 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3727 image->offset + image->cmask.offset,
3728 image->cmask.size, value);
3729
3730 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3731 }
3732
3733 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3734 struct radv_image *image,
3735 VkImageLayout src_layout,
3736 VkImageLayout dst_layout,
3737 unsigned src_queue_mask,
3738 unsigned dst_queue_mask,
3739 const VkImageSubresourceRange *range)
3740 {
3741 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3742 if (image->fmask.size)
3743 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3744 else
3745 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3746 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3747 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3748 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3749 }
3750 }
3751
3752 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3753 struct radv_image *image, uint32_t value)
3754 {
3755 struct radv_cmd_state *state = &cmd_buffer->state;
3756
3757 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3758 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3759
3760 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3761 image->offset + image->dcc_offset,
3762 image->surface.dcc_size, value);
3763
3764 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3765 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3766 }
3767
3768 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3769 struct radv_image *image,
3770 VkImageLayout src_layout,
3771 VkImageLayout dst_layout,
3772 unsigned src_queue_mask,
3773 unsigned dst_queue_mask,
3774 const VkImageSubresourceRange *range)
3775 {
3776 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3777 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3778 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3779 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3780 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3781 }
3782 }
3783
3784 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3785 struct radv_image *image,
3786 VkImageLayout src_layout,
3787 VkImageLayout dst_layout,
3788 uint32_t src_family,
3789 uint32_t dst_family,
3790 const VkImageSubresourceRange *range,
3791 VkImageAspectFlags pending_clears)
3792 {
3793 if (image->exclusive && src_family != dst_family) {
3794 /* This is an acquire or a release operation and there will be
3795 * a corresponding release/acquire. Do the transition in the
3796 * most flexible queue. */
3797
3798 assert(src_family == cmd_buffer->queue_family_index ||
3799 dst_family == cmd_buffer->queue_family_index);
3800
3801 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3802 return;
3803
3804 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3805 (src_family == RADV_QUEUE_GENERAL ||
3806 dst_family == RADV_QUEUE_GENERAL))
3807 return;
3808 }
3809
3810 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3811 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3812
3813 if (image->surface.htile_size)
3814 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3815 dst_layout, src_queue_mask,
3816 dst_queue_mask, range,
3817 pending_clears);
3818
3819 if (image->cmask.size || image->fmask.size)
3820 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3821 dst_layout, src_queue_mask,
3822 dst_queue_mask, range);
3823
3824 if (image->surface.dcc_size)
3825 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3826 dst_layout, src_queue_mask,
3827 dst_queue_mask, range);
3828 }
3829
3830 void radv_CmdPipelineBarrier(
3831 VkCommandBuffer commandBuffer,
3832 VkPipelineStageFlags srcStageMask,
3833 VkPipelineStageFlags destStageMask,
3834 VkBool32 byRegion,
3835 uint32_t memoryBarrierCount,
3836 const VkMemoryBarrier* pMemoryBarriers,
3837 uint32_t bufferMemoryBarrierCount,
3838 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3839 uint32_t imageMemoryBarrierCount,
3840 const VkImageMemoryBarrier* pImageMemoryBarriers)
3841 {
3842 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3843 enum radv_cmd_flush_bits src_flush_bits = 0;
3844 enum radv_cmd_flush_bits dst_flush_bits = 0;
3845
3846 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3847 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3848 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3849 NULL);
3850 }
3851
3852 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3853 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3854 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3855 NULL);
3856 }
3857
3858 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3859 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3860 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3861 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3862 image);
3863 }
3864
3865 radv_stage_flush(cmd_buffer, srcStageMask);
3866 cmd_buffer->state.flush_bits |= src_flush_bits;
3867
3868 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3869 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3870 radv_handle_image_transition(cmd_buffer, image,
3871 pImageMemoryBarriers[i].oldLayout,
3872 pImageMemoryBarriers[i].newLayout,
3873 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3874 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3875 &pImageMemoryBarriers[i].subresourceRange,
3876 0);
3877 }
3878
3879 cmd_buffer->state.flush_bits |= dst_flush_bits;
3880 }
3881
3882
3883 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3884 struct radv_event *event,
3885 VkPipelineStageFlags stageMask,
3886 unsigned value)
3887 {
3888 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3889 uint64_t va = radv_buffer_get_va(event->bo);
3890
3891 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3892
3893 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3894
3895 /* TODO: this is overkill. Probably should figure something out from
3896 * the stage mask. */
3897
3898 si_cs_emit_write_event_eop(cs,
3899 cmd_buffer->state.predicating,
3900 cmd_buffer->device->physical_device->rad_info.chip_class,
3901 false,
3902 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3903 1, va, 2, value);
3904
3905 assert(cmd_buffer->cs->cdw <= cdw_max);
3906 }
3907
3908 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3909 VkEvent _event,
3910 VkPipelineStageFlags stageMask)
3911 {
3912 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3913 RADV_FROM_HANDLE(radv_event, event, _event);
3914
3915 write_event(cmd_buffer, event, stageMask, 1);
3916 }
3917
3918 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3919 VkEvent _event,
3920 VkPipelineStageFlags stageMask)
3921 {
3922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3923 RADV_FROM_HANDLE(radv_event, event, _event);
3924
3925 write_event(cmd_buffer, event, stageMask, 0);
3926 }
3927
3928 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3929 uint32_t eventCount,
3930 const VkEvent* pEvents,
3931 VkPipelineStageFlags srcStageMask,
3932 VkPipelineStageFlags dstStageMask,
3933 uint32_t memoryBarrierCount,
3934 const VkMemoryBarrier* pMemoryBarriers,
3935 uint32_t bufferMemoryBarrierCount,
3936 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3937 uint32_t imageMemoryBarrierCount,
3938 const VkImageMemoryBarrier* pImageMemoryBarriers)
3939 {
3940 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3941 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3942
3943 for (unsigned i = 0; i < eventCount; ++i) {
3944 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3945 uint64_t va = radv_buffer_get_va(event->bo);
3946
3947 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3948
3949 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3950
3951 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3952 assert(cmd_buffer->cs->cdw <= cdw_max);
3953 }
3954
3955
3956 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3957 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3958
3959 radv_handle_image_transition(cmd_buffer, image,
3960 pImageMemoryBarriers[i].oldLayout,
3961 pImageMemoryBarriers[i].newLayout,
3962 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3963 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3964 &pImageMemoryBarriers[i].subresourceRange,
3965 0);
3966 }
3967
3968 /* TODO: figure out how to do memory barriers without waiting */
3969 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3970 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3971 RADV_CMD_FLAG_INV_VMEM_L1 |
3972 RADV_CMD_FLAG_INV_SMEM_L1;
3973 }