projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Optimize calling radv_save_descriptors.
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
44 uint32_t src_family,
45 uint32_t dst_family,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
48
49 const struct radv_dynamic_state default_dynamic_state = {
50 .viewport = {
51 .count = 0,
52 },
53 .scissor = {
54 .count = 0,
55 },
56 .line_width = 1.0f,
57 .depth_bias = {
58 .bias = 0.0f,
59 .clamp = 0.0f,
60 .slope = 0.0f,
61 },
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
63 .depth_bounds = {
64 .min = 0.0f,
65 .max = 1.0f,
66 },
67 .stencil_compare_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_write_mask = {
72 .front = ~0u,
73 .back = ~0u,
74 },
75 .stencil_reference = {
76 .front = 0u,
77 .back = 0u,
78 },
79 };
80
81 static void
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
84 {
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
88
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
91 */
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94
95 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
96 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
97 src->viewport.count * sizeof(VkViewport))) {
98 typed_memcpy(dest->viewport.viewports,
99 src->viewport.viewports,
100 src->viewport.count);
101 dest_mask |= 1 << VK_DYNAMIC_STATE_VIEWPORT;
102 }
103 }
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
106 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
107 src->scissor.count * sizeof(VkRect2D))) {
108 typed_memcpy(dest->scissor.scissors,
109 src->scissor.scissors, src->scissor.count);
110 dest_mask |= 1 << VK_DYNAMIC_STATE_SCISSOR;
111 }
112 }
113
114 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
115 if (dest->line_width != src->line_width) {
116 dest->line_width = src->line_width;
117 dest_mask |= 1 << VK_DYNAMIC_STATE_LINE_WIDTH;
118 }
119 }
120
121 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
122 if (memcmp(&dest->depth_bias, &src->depth_bias,
123 sizeof(src->depth_bias))) {
124 dest->depth_bias = src->depth_bias;
125 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BIAS;
126 }
127 }
128
129 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
130 if (memcmp(&dest->blend_constants, &src->blend_constants,
131 sizeof(src->blend_constants))) {
132 typed_memcpy(dest->blend_constants,
133 src->blend_constants, 4);
134 dest_mask |= 1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS;
135 }
136 }
137
138 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
139 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
140 sizeof(src->depth_bounds))) {
141 dest->depth_bounds = src->depth_bounds;
142 dest_mask |= 1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS;
143 }
144 }
145
146 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
147 if (memcmp(&dest->stencil_compare_mask,
148 &src->stencil_compare_mask,
149 sizeof(src->stencil_compare_mask))) {
150 dest->stencil_compare_mask = src->stencil_compare_mask;
151 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK;
152 }
153 }
154
155 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
156 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
157 sizeof(src->stencil_write_mask))) {
158 dest->stencil_write_mask = src->stencil_write_mask;
159 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK;
160 }
161 }
162
163 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
164 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
165 sizeof(src->stencil_reference))) {
166 dest->stencil_reference = src->stencil_reference;
167 dest_mask |= 1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE;
168 }
169 }
170
171 cmd_buffer->state.dirty |= dest_mask;
172 }
173
174 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
175 {
176 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
177 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
178 }
179
180 enum ring_type radv_queue_family_to_ring(int f) {
181 switch (f) {
182 case RADV_QUEUE_GENERAL:
183 return RING_GFX;
184 case RADV_QUEUE_COMPUTE:
185 return RING_COMPUTE;
186 case RADV_QUEUE_TRANSFER:
187 return RING_DMA;
188 default:
189 unreachable("Unknown queue family");
190 }
191 }
192
193 static VkResult radv_create_cmd_buffer(
194 struct radv_device * device,
195 struct radv_cmd_pool * pool,
196 VkCommandBufferLevel level,
197 VkCommandBuffer* pCommandBuffer)
198 {
199 struct radv_cmd_buffer *cmd_buffer;
200 unsigned ring;
201 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
203 if (cmd_buffer == NULL)
204 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
205
206 memset(cmd_buffer, 0, sizeof(*cmd_buffer));
207 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
208 cmd_buffer->device = device;
209 cmd_buffer->pool = pool;
210 cmd_buffer->level = level;
211
212 if (pool) {
213 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
214 cmd_buffer->queue_family_index = pool->queue_family_index;
215
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
222 }
223
224 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
225
226 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
227 if (!cmd_buffer->cs) {
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
230 }
231
232 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
233
234 cmd_buffer->upload.offset = 0;
235 cmd_buffer->upload.size = 0;
236 list_inithead(&cmd_buffer->upload.list);
237
238 return VK_SUCCESS;
239 }
240
241 static void
242 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
243 {
244 list_del(&cmd_buffer->pool_link);
245
246 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
247 &cmd_buffer->upload.list, list) {
248 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
249 list_del(&up->list);
250 free(up);
251 }
252
253 if (cmd_buffer->upload.upload_bo)
254 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
255 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
256 free(cmd_buffer->push_descriptors.set.mapped_ptr);
257 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
258 }
259
260 static VkResult
261 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
262 {
263
264 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
265
266 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
267 &cmd_buffer->upload.list, list) {
268 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
269 list_del(&up->list);
270 free(up);
271 }
272
273 cmd_buffer->push_constant_stages = 0;
274 cmd_buffer->scratch_size_needed = 0;
275 cmd_buffer->compute_scratch_size_needed = 0;
276 cmd_buffer->esgs_ring_size_needed = 0;
277 cmd_buffer->gsvs_ring_size_needed = 0;
278 cmd_buffer->tess_rings_needed = false;
279 cmd_buffer->sample_positions_needed = false;
280
281 if (cmd_buffer->upload.upload_bo)
282 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs,
283 cmd_buffer->upload.upload_bo, 8);
284 cmd_buffer->upload.offset = 0;
285
286 cmd_buffer->record_result = VK_SUCCESS;
287
288 cmd_buffer->ring_offsets_idx = -1;
289
290 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
291 void *fence_ptr;
292 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
293 &cmd_buffer->gfx9_fence_offset,
294 &fence_ptr);
295 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
296 }
297
298 return cmd_buffer->record_result;
299 }
300
301 static bool
302 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
303 uint64_t min_needed)
304 {
305 uint64_t new_size;
306 struct radeon_winsys_bo *bo;
307 struct radv_cmd_buffer_upload *upload;
308 struct radv_device *device = cmd_buffer->device;
309
310 new_size = MAX2(min_needed, 16 * 1024);
311 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
312
313 bo = device->ws->buffer_create(device->ws,
314 new_size, 4096,
315 RADEON_DOMAIN_GTT,
316 RADEON_FLAG_CPU_ACCESS|
317 RADEON_FLAG_NO_INTERPROCESS_SHARING);
318
319 if (!bo) {
320 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
321 return false;
322 }
323
324 device->ws->cs_add_buffer(cmd_buffer->cs, bo, 8);
325 if (cmd_buffer->upload.upload_bo) {
326 upload = malloc(sizeof(*upload));
327
328 if (!upload) {
329 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
330 device->ws->buffer_destroy(bo);
331 return false;
332 }
333
334 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
335 list_add(&upload->list, &cmd_buffer->upload.list);
336 }
337
338 cmd_buffer->upload.upload_bo = bo;
339 cmd_buffer->upload.size = new_size;
340 cmd_buffer->upload.offset = 0;
341 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
342
343 if (!cmd_buffer->upload.map) {
344 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
345 return false;
346 }
347
348 return true;
349 }
350
351 bool
352 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
353 unsigned size,
354 unsigned alignment,
355 unsigned *out_offset,
356 void **ptr)
357 {
358 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
359 if (offset + size > cmd_buffer->upload.size) {
360 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
361 return false;
362 offset = 0;
363 }
364
365 *out_offset = offset;
366 *ptr = cmd_buffer->upload.map + offset;
367
368 cmd_buffer->upload.offset = offset + size;
369 return true;
370 }
371
372 bool
373 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
374 unsigned size, unsigned alignment,
375 const void *data, unsigned *out_offset)
376 {
377 uint8_t *ptr;
378
379 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
380 out_offset, (void **)&ptr))
381 return false;
382
383 if (ptr)
384 memcpy(ptr, data, size);
385
386 return true;
387 }
388
389 static void
390 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
391 unsigned count, const uint32_t *data)
392 {
393 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
394 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
395 S_370_WR_CONFIRM(1) |
396 S_370_ENGINE_SEL(V_370_ME));
397 radeon_emit(cs, va);
398 radeon_emit(cs, va >> 32);
399 radeon_emit_array(cs, data, count);
400 }
401
402 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
403 {
404 struct radv_device *device = cmd_buffer->device;
405 struct radeon_winsys_cs *cs = cmd_buffer->cs;
406 uint64_t va;
407
408 if (!device->trace_bo)
409 return;
410
411 va = radv_buffer_get_va(device->trace_bo);
412 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
413 va += 4;
414
415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
416
417 ++cmd_buffer->state.trace_id;
418 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
419 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
420 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
421 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
422 }
423
424 static void
425 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
426 {
427 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
428 enum radv_cmd_flush_bits flags;
429
430 /* Force wait for graphics/compute engines to be idle. */
431 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
432 RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
433
434 si_cs_emit_cache_flush(cmd_buffer->cs, false,
435 cmd_buffer->device->physical_device->rad_info.chip_class,
436 NULL, 0,
437 radv_cmd_buffer_uses_mec(cmd_buffer),
438 flags);
439 }
440
441 radv_cmd_buffer_trace_emit(cmd_buffer);
442 }
443
444 static void
445 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
446 struct radv_pipeline *pipeline, enum ring_type ring)
447 {
448 struct radv_device *device = cmd_buffer->device;
449 struct radeon_winsys_cs *cs = cmd_buffer->cs;
450 uint32_t data[2];
451 uint64_t va;
452
453 if (!device->trace_bo)
454 return;
455
456 va = radv_buffer_get_va(device->trace_bo);
457
458 switch (ring) {
459 case RING_GFX:
460 va += 8;
461 break;
462 case RING_COMPUTE:
463 va += 16;
464 break;
465 default:
466 assert(!"invalid ring type");
467 }
468
469 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
470 cmd_buffer->cs, 6);
471
472 data[0] = (uintptr_t)pipeline;
473 data[1] = (uintptr_t)pipeline >> 32;
474
475 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
476 radv_emit_write_data_packet(cs, va, 2, data);
477 }
478
479 static void
480 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
481 {
482 struct radv_device *device = cmd_buffer->device;
483 struct radeon_winsys_cs *cs = cmd_buffer->cs;
484 uint32_t data[MAX_SETS * 2] = {};
485 uint64_t va;
486
487 va = radv_buffer_get_va(device->trace_bo) + 24;
488
489 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
490 cmd_buffer->cs, 4 + MAX_SETS * 2);
491
492 for (int i = 0; i < MAX_SETS; i++) {
493 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
494 if (!set)
495 continue;
496
497 data[i * 2] = (uintptr_t)set;
498 data[i * 2 + 1] = (uintptr_t)set >> 32;
499 }
500
501 device->ws->cs_add_buffer(cs, device->trace_bo, 8);
502 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
503 }
504
505 static void
506 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
507 struct radv_pipeline *pipeline)
508 {
509 radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
510 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
511 8);
512 radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
513 radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
514
515 if (cmd_buffer->device->physical_device->has_rbplus) {
516
517 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
518 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
519
520 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
521 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
522 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
523 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
524 }
525 }
526
527 static void
528 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
529 struct radv_pipeline *pipeline)
530 {
531 struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
532 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
533 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
534
535 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
536 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
537 }
538
539 struct ac_userdata_info *
540 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
541 gl_shader_stage stage,
542 int idx)
543 {
544 if (stage == MESA_SHADER_VERTEX) {
545 if (pipeline->shaders[MESA_SHADER_VERTEX])
546 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
547 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
548 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
549 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
550 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
551 } else if (stage == MESA_SHADER_TESS_EVAL) {
552 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
553 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
554 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
555 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
556 }
557 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
558 }
559
560 static void
561 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
562 struct radv_pipeline *pipeline,
563 gl_shader_stage stage,
564 int idx, uint64_t va)
565 {
566 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
567 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
568 if (loc->sgpr_idx == -1)
569 return;
570 assert(loc->num_sgprs == 2);
571 assert(!loc->indirect);
572 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
573 radeon_emit(cmd_buffer->cs, va);
574 radeon_emit(cmd_buffer->cs, va >> 32);
575 }
576
577 static void
578 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
579 struct radv_pipeline *pipeline)
580 {
581 int num_samples = pipeline->graphics.ms.num_samples;
582 struct radv_multisample_state *ms = &pipeline->graphics.ms;
583 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
584
585 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
586 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
587 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
588
589 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
590 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
591
592 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
593 return;
594
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
596 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
597 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
598
599 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
600
601 /* GFX9: Flush DFSM when the AA mode changes. */
602 if (cmd_buffer->device->dfsm_allowed) {
603 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
604 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
605 }
606 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
607 uint32_t offset;
608 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
609 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_FRAGMENT, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
610 if (loc->sgpr_idx == -1)
611 return;
612 assert(loc->num_sgprs == 1);
613 assert(!loc->indirect);
614 switch (num_samples) {
615 default:
616 offset = 0;
617 break;
618 case 2:
619 offset = 1;
620 break;
621 case 4:
622 offset = 3;
623 break;
624 case 8:
625 offset = 7;
626 break;
627 case 16:
628 offset = 15;
629 break;
630 }
631
632 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
633 cmd_buffer->sample_positions_needed = true;
634 }
635 }
636
637 static void
638 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_pipeline *pipeline)
640 {
641 struct radv_raster_state *raster = &pipeline->graphics.raster;
642
643 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
644 raster->pa_cl_clip_cntl);
645 radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
646 raster->spi_interp_control);
647 radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
648 raster->pa_su_vtx_cntl);
649 radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
650 raster->pa_su_sc_mode_cntl);
651 }
652
653 static void
654 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
655 struct radv_shader_variant *shader)
656 {
657 struct radeon_winsys *ws = cmd_buffer->device->ws;
658 struct radeon_winsys_cs *cs = cmd_buffer->cs;
659 uint64_t va;
660
661 if (!shader)
662 return;
663
664 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
665
666 ws->cs_add_buffer(cs, shader->bo, 8);
667 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
668 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
669 }
670
671 static void
672 radv_emit_shaders_prefetch(struct radv_cmd_buffer *cmd_buffer,
673 struct radv_pipeline *pipeline)
674 {
675 radv_emit_shader_prefetch(cmd_buffer,
676 pipeline->shaders[MESA_SHADER_VERTEX]);
677 radv_emit_shader_prefetch(cmd_buffer,
678 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
679 radv_emit_shader_prefetch(cmd_buffer,
680 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
681 radv_emit_shader_prefetch(cmd_buffer,
682 pipeline->shaders[MESA_SHADER_GEOMETRY]);
683 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
684 radv_emit_shader_prefetch(cmd_buffer,
685 pipeline->shaders[MESA_SHADER_FRAGMENT]);
686 }
687
688 static void
689 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
690 struct radv_pipeline *pipeline,
691 struct radv_shader_variant *shader,
692 struct ac_vs_output_info *outinfo)
693 {
694 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
695 unsigned export_count;
696
697 export_count = MAX2(1, outinfo->param_exports);
698 radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
699 S_0286C4_VS_EXPORT_COUNT(export_count - 1));
700
701 radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
702 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
703 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
704 V_02870C_SPI_SHADER_4COMP :
705 V_02870C_SPI_SHADER_NONE) |
706 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
707 V_02870C_SPI_SHADER_4COMP :
708 V_02870C_SPI_SHADER_NONE) |
709 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
710 V_02870C_SPI_SHADER_4COMP :
711 V_02870C_SPI_SHADER_NONE));
712
713
714 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
715 radeon_emit(cmd_buffer->cs, va >> 8);
716 radeon_emit(cmd_buffer->cs, va >> 40);
717 radeon_emit(cmd_buffer->cs, shader->rsrc1);
718 radeon_emit(cmd_buffer->cs, shader->rsrc2);
719
720 radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
721 S_028818_VTX_W0_FMT(1) |
722 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
723 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
724 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
725
726
727 radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
728 pipeline->graphics.pa_cl_vs_out_cntl);
729
730 if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
731 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
732 S_028AB4_REUSE_OFF(outinfo->writes_viewport_index));
733 }
734
735 static void
736 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
737 struct radv_shader_variant *shader,
738 struct ac_es_output_info *outinfo)
739 {
740 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
741
742 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
743 outinfo->esgs_itemsize / 4);
744 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
745 radeon_emit(cmd_buffer->cs, va >> 8);
746 radeon_emit(cmd_buffer->cs, va >> 40);
747 radeon_emit(cmd_buffer->cs, shader->rsrc1);
748 radeon_emit(cmd_buffer->cs, shader->rsrc2);
749 }
750
751 static void
752 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
753 struct radv_shader_variant *shader)
754 {
755 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
756 uint32_t rsrc2 = shader->rsrc2;
757
758 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
759 radeon_emit(cmd_buffer->cs, va >> 8);
760 radeon_emit(cmd_buffer->cs, va >> 40);
761
762 rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
763 if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
764 cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
765 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
766
767 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
768 radeon_emit(cmd_buffer->cs, shader->rsrc1);
769 radeon_emit(cmd_buffer->cs, rsrc2);
770 }
771
772 static void
773 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
774 struct radv_shader_variant *shader)
775 {
776 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
777
778 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
779 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
780 radeon_emit(cmd_buffer->cs, va >> 8);
781 radeon_emit(cmd_buffer->cs, va >> 40);
782
783 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
784 radeon_emit(cmd_buffer->cs, shader->rsrc1);
785 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
786 S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
787 } else {
788 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
789 radeon_emit(cmd_buffer->cs, va >> 8);
790 radeon_emit(cmd_buffer->cs, va >> 40);
791 radeon_emit(cmd_buffer->cs, shader->rsrc1);
792 radeon_emit(cmd_buffer->cs, shader->rsrc2);
793 }
794 }
795
796 static void
797 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
798 struct radv_pipeline *pipeline)
799 {
800 struct radv_shader_variant *vs;
801
802 radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
803
804 /* Skip shaders merged into HS/GS */
805 vs = pipeline->shaders[MESA_SHADER_VERTEX];
806 if (!vs)
807 return;
808
809 if (vs->info.vs.as_ls)
810 radv_emit_hw_ls(cmd_buffer, vs);
811 else if (vs->info.vs.as_es)
812 radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info);
813 else
814 radv_emit_hw_vs(cmd_buffer, pipeline, vs, &vs->info.vs.outinfo);
815 }
816
817
818 static void
819 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
820 struct radv_pipeline *pipeline)
821 {
822 if (!radv_pipeline_has_tess(pipeline))
823 return;
824
825 struct radv_shader_variant *tes, *tcs;
826
827 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
828 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
829
830 if (tes) {
831 if (tes->info.tes.as_es)
832 radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info);
833 else
834 radv_emit_hw_vs(cmd_buffer, pipeline, tes, &tes->info.tes.outinfo);
835 }
836
837 radv_emit_hw_hs(cmd_buffer, tcs);
838
839 radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
840 pipeline->graphics.tess.tf_param);
841
842 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
843 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
844 pipeline->graphics.tess.ls_hs_config);
845 else
846 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
847 pipeline->graphics.tess.ls_hs_config);
848
849 struct ac_userdata_info *loc;
850
851 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
852 if (loc->sgpr_idx != -1) {
853 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_CTRL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
854 assert(loc->num_sgprs == 4);
855 assert(!loc->indirect);
856 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
857 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
858 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
859 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
860 pipeline->graphics.tess.num_tcs_input_cp << 26);
861 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
862 }
863
864 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
865 if (loc->sgpr_idx != -1) {
866 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_TESS_EVAL, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
867 assert(loc->num_sgprs == 1);
868 assert(!loc->indirect);
869
870 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
871 pipeline->graphics.tess.offchip_layout);
872 }
873
874 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
875 if (loc->sgpr_idx != -1) {
876 uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
877 assert(loc->num_sgprs == 1);
878 assert(!loc->indirect);
879
880 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
881 pipeline->graphics.tess.tcs_in_layout);
882 }
883 }
884
885 static void
886 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
887 struct radv_pipeline *pipeline)
888 {
889 struct radv_shader_variant *gs;
890 uint64_t va;
891
892 radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
893
894 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
895 if (!gs)
896 return;
897
898 uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
899
900 radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
901 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
902 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
903 radeon_emit(cmd_buffer->cs, gsvs_itemsize);
904
905 radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
906
907 radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
908
909 uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
910 radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
911 radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
912 radeon_emit(cmd_buffer->cs, 0);
913 radeon_emit(cmd_buffer->cs, 0);
914 radeon_emit(cmd_buffer->cs, 0);
915
916 uint32_t gs_num_invocations = gs->info.gs.invocations;
917 radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
918 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
919 S_028B90_ENABLE(gs_num_invocations > 0));
920
921 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
922
923 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
924 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
925 radeon_emit(cmd_buffer->cs, va >> 8);
926 radeon_emit(cmd_buffer->cs, va >> 40);
927
928 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
929 radeon_emit(cmd_buffer->cs, gs->rsrc1);
930 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
931 S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
932
933 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
934 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
935 radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize);
936 } else {
937 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
938 radeon_emit(cmd_buffer->cs, va >> 8);
939 radeon_emit(cmd_buffer->cs, va >> 40);
940 radeon_emit(cmd_buffer->cs, gs->rsrc1);
941 radeon_emit(cmd_buffer->cs, gs->rsrc2);
942 }
943
944 radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader, &pipeline->gs_copy_shader->info.vs.outinfo);
945
946 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
947 AC_UD_GS_VS_RING_STRIDE_ENTRIES);
948 if (loc->sgpr_idx != -1) {
949 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
950 uint32_t num_entries = 64;
951 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
952
953 if (is_vi)
954 num_entries *= stride;
955
956 stride = S_008F04_STRIDE(stride);
957 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
958 radeon_emit(cmd_buffer->cs, stride);
959 radeon_emit(cmd_buffer->cs, num_entries);
960 }
961 }
962
963 static void
964 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
965 struct radv_pipeline *pipeline)
966 {
967 struct radv_shader_variant *ps;
968 uint64_t va;
969 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
970 struct radv_blend_state *blend = &pipeline->graphics.blend;
971 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
972
973 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
974 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
975
976 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
977 radeon_emit(cmd_buffer->cs, va >> 8);
978 radeon_emit(cmd_buffer->cs, va >> 40);
979 radeon_emit(cmd_buffer->cs, ps->rsrc1);
980 radeon_emit(cmd_buffer->cs, ps->rsrc2);
981
982 radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
983 pipeline->graphics.db_shader_control);
984
985 radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
986 ps->config.spi_ps_input_ena);
987
988 radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
989 ps->config.spi_ps_input_addr);
990
991 if (ps->info.info.ps.force_persample)
992 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
993
994 radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
995 S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
996
997 radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
998
999 radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1000 pipeline->graphics.shader_z_format);
1001
1002 radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1003
1004 radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1005 radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1006
1007 if (cmd_buffer->device->dfsm_allowed) {
1008 /* optimise this? */
1009 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1010 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1011 }
1012
1013 if (pipeline->graphics.ps_input_cntl_num) {
1014 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1015 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1016 radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1017 }
1018 }
1019 }
1020
1021 static void
1022 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1023 struct radv_pipeline *pipeline)
1024 {
1025 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1026
1027 if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1028 return;
1029
1030 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1031 pipeline->graphics.vtx_reuse_depth);
1032 }
1033
1034 static void
1035 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1036 {
1037 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1038
1039 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1040 return;
1041
1042 radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1043 radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1044 radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1045 radv_update_multisample_state(cmd_buffer, pipeline);
1046 radv_emit_vertex_shader(cmd_buffer, pipeline);
1047 radv_emit_tess_shaders(cmd_buffer, pipeline);
1048 radv_emit_geometry_shader(cmd_buffer, pipeline);
1049 radv_emit_fragment_shader(cmd_buffer, pipeline);
1050 radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1051
1052 cmd_buffer->scratch_size_needed =
1053 MAX2(cmd_buffer->scratch_size_needed,
1054 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1055
1056 radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1057 S_0286E8_WAVES(pipeline->max_waves) |
1058 S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1059
1060 if (!cmd_buffer->state.emitted_pipeline ||
1061 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1062 pipeline->graphics.can_use_guardband)
1063 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1064
1065 radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1066
1067 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1068 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1069 } else {
1070 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1071 }
1072 radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1073
1074 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1075
1076 cmd_buffer->state.emitted_pipeline = pipeline;
1077
1078 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1079 }
1080
1081 static void
1082 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1083 {
1084 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1085 cmd_buffer->state.dynamic.viewport.viewports);
1086 }
1087
1088 static void
1089 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1090 {
1091 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1092
1093 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1094 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1095 si_emit_cache_flush(cmd_buffer);
1096 }
1097 si_write_scissors(cmd_buffer->cs, 0, count,
1098 cmd_buffer->state.dynamic.scissor.scissors,
1099 cmd_buffer->state.dynamic.viewport.viewports,
1100 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1101 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0,
1102 cmd_buffer->state.pipeline->graphics.ms.pa_sc_mode_cntl_0 | S_028A48_VPORT_SCISSOR_ENABLE(count ? 1 : 0));
1103 }
1104
1105 static void
1106 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1107 {
1108 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1109
1110 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1111 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1112 }
1113
1114 static void
1115 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1116 {
1117 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1118
1119 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1120 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1121 }
1122
1123 static void
1124 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1125 {
1126 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1127
1128 radeon_set_context_reg_seq(cmd_buffer->cs,
1129 R_028430_DB_STENCILREFMASK, 2);
1130 radeon_emit(cmd_buffer->cs,
1131 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1132 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1133 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1134 S_028430_STENCILOPVAL(1));
1135 radeon_emit(cmd_buffer->cs,
1136 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1137 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1138 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1139 S_028434_STENCILOPVAL_BF(1));
1140 }
1141
1142 static void
1143 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1144 {
1145 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1146
1147 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1148 fui(d->depth_bounds.min));
1149 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1150 fui(d->depth_bounds.max));
1151 }
1152
1153 static void
1154 radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer)
1155 {
1156 struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1157 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1158 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1159 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1160
1161 if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1162 radeon_set_context_reg_seq(cmd_buffer->cs,
1163 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1164 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1165 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1166 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1167 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1168 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1169 }
1170 }
1171
1172 static void
1173 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1174 int index,
1175 struct radv_color_buffer_info *cb)
1176 {
1177 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1178
1179 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1180 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1181 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1182 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1183 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1184 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1185 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1186 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1187 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1188 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1189 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1190 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1191 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1192
1193 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1194 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1195 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1196
1197 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1198 cb->gfx9_epitch);
1199 } else {
1200 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1201 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1202 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1203 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1204 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1205 radeon_emit(cmd_buffer->cs, cb->cb_color_info);
1206 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1207 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1208 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1209 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1210 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1211 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1212
1213 if (is_vi) { /* DCC BASE */
1214 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1215 }
1216 }
1217 }
1218
1219 static void
1220 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1221 struct radv_ds_buffer_info *ds,
1222 struct radv_image *image,
1223 VkImageLayout layout)
1224 {
1225 uint32_t db_z_info = ds->db_z_info;
1226 uint32_t db_stencil_info = ds->db_stencil_info;
1227
1228 if (!radv_layout_has_htile(image, layout,
1229 radv_image_queue_family_mask(image,
1230 cmd_buffer->queue_family_index,
1231 cmd_buffer->queue_family_index))) {
1232 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1233 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1234 }
1235
1236 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1237 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1238
1239
1240 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1241 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1242 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1243 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1244 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1245
1246 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1247 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1248 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1249 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1250 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
1251 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1252 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1253 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1254 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1255 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1256 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1257
1258 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1259 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1260 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1261 } else {
1262 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1263
1264 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1265 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1266 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1267 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1268 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1269 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1270 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1271 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1272 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1273 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1274
1275 }
1276
1277 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1278 ds->pa_su_poly_offset_db_fmt_cntl);
1279 }
1280
1281 void
1282 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1283 struct radv_image *image,
1284 VkClearDepthStencilValue ds_clear_value,
1285 VkImageAspectFlags aspects)
1286 {
1287 uint64_t va = radv_buffer_get_va(image->bo);
1288 va += image->offset + image->clear_value_offset;
1289 unsigned reg_offset = 0, reg_count = 0;
1290
1291 if (!image->surface.htile_size || !aspects)
1292 return;
1293
1294 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1295 ++reg_count;
1296 } else {
1297 ++reg_offset;
1298 va += 4;
1299 }
1300 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1301 ++reg_count;
1302
1303 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1304
1305 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1306 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1307 S_370_WR_CONFIRM(1) |
1308 S_370_ENGINE_SEL(V_370_PFP));
1309 radeon_emit(cmd_buffer->cs, va);
1310 radeon_emit(cmd_buffer->cs, va >> 32);
1311 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1312 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1313 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1314 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1315
1316 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1317 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1318 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1319 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1320 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1321 }
1322
1323 static void
1324 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1325 struct radv_image *image)
1326 {
1327 uint64_t va = radv_buffer_get_va(image->bo);
1328 va += image->offset + image->clear_value_offset;
1329
1330 if (!image->surface.htile_size)
1331 return;
1332
1333 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1334
1335 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1336 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1337 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1338 COPY_DATA_COUNT_SEL);
1339 radeon_emit(cmd_buffer->cs, va);
1340 radeon_emit(cmd_buffer->cs, va >> 32);
1341 radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1342 radeon_emit(cmd_buffer->cs, 0);
1343
1344 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1345 radeon_emit(cmd_buffer->cs, 0);
1346 }
1347
1348 /*
1349 *with DCC some colors don't require CMASK elimiation before being
1350 * used as a texture. This sets a predicate value to determine if the
1351 * cmask eliminate is required.
1352 */
1353 void
1354 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1355 struct radv_image *image,
1356 bool value)
1357 {
1358 uint64_t pred_val = value;
1359 uint64_t va = radv_buffer_get_va(image->bo);
1360 va += image->offset + image->dcc_pred_offset;
1361
1362 if (!image->surface.dcc_size)
1363 return;
1364
1365 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1366
1367 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1368 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1369 S_370_WR_CONFIRM(1) |
1370 S_370_ENGINE_SEL(V_370_PFP));
1371 radeon_emit(cmd_buffer->cs, va);
1372 radeon_emit(cmd_buffer->cs, va >> 32);
1373 radeon_emit(cmd_buffer->cs, pred_val);
1374 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1375 }
1376
1377 void
1378 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1379 struct radv_image *image,
1380 int idx,
1381 uint32_t color_values[2])
1382 {
1383 uint64_t va = radv_buffer_get_va(image->bo);
1384 va += image->offset + image->clear_value_offset;
1385
1386 if (!image->cmask.size && !image->surface.dcc_size)
1387 return;
1388
1389 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1390
1391 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1392 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1393 S_370_WR_CONFIRM(1) |
1394 S_370_ENGINE_SEL(V_370_PFP));
1395 radeon_emit(cmd_buffer->cs, va);
1396 radeon_emit(cmd_buffer->cs, va >> 32);
1397 radeon_emit(cmd_buffer->cs, color_values[0]);
1398 radeon_emit(cmd_buffer->cs, color_values[1]);
1399
1400 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1401 radeon_emit(cmd_buffer->cs, color_values[0]);
1402 radeon_emit(cmd_buffer->cs, color_values[1]);
1403 }
1404
1405 static void
1406 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1407 struct radv_image *image,
1408 int idx)
1409 {
1410 uint64_t va = radv_buffer_get_va(image->bo);
1411 va += image->offset + image->clear_value_offset;
1412
1413 if (!image->cmask.size && !image->surface.dcc_size)
1414 return;
1415
1416 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1417 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, image->bo, 8);
1418
1419 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1420 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1421 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1422 COPY_DATA_COUNT_SEL);
1423 radeon_emit(cmd_buffer->cs, va);
1424 radeon_emit(cmd_buffer->cs, va >> 32);
1425 radeon_emit(cmd_buffer->cs, reg >> 2);
1426 radeon_emit(cmd_buffer->cs, 0);
1427
1428 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1429 radeon_emit(cmd_buffer->cs, 0);
1430 }
1431
1432 void
1433 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1434 {
1435 int i;
1436 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1437 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1438
1439 /* this may happen for inherited secondary recording */
1440 if (!framebuffer)
1441 return;
1442
1443 for (i = 0; i < 8; ++i) {
1444 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1445 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1446 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1447 continue;
1448 }
1449
1450 int idx = subpass->color_attachments[i].attachment;
1451 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1452
1453 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1454
1455 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1456 radv_emit_fb_color_state(cmd_buffer, i, &att->cb);
1457
1458 radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i);
1459 }
1460
1461 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1462 int idx = subpass->depth_stencil_attachment.attachment;
1463 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1464 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1465 struct radv_image *image = att->attachment->image;
1466 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, att->attachment->bo, 8);
1467 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1468 cmd_buffer->queue_family_index,
1469 cmd_buffer->queue_family_index);
1470 /* We currently don't support writing decompressed HTILE */
1471 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1472 radv_layout_is_htile_compressed(image, layout, queue_mask));
1473
1474 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1475
1476 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1477 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1478 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1479 }
1480 radv_load_depth_clear_regs(cmd_buffer, image);
1481 } else {
1482 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1483 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1484 else
1485 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1486
1487 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1488 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1489 }
1490 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1491 S_028208_BR_X(framebuffer->width) |
1492 S_028208_BR_Y(framebuffer->height));
1493
1494 if (cmd_buffer->device->dfsm_allowed) {
1495 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1496 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1497 }
1498
1499 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1500 }
1501
1502 static void
1503 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1504 {
1505 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1506
1507 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1508 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1509 2, cmd_buffer->state.index_type);
1510 } else {
1511 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1512 radeon_emit(cs, cmd_buffer->state.index_type);
1513 }
1514
1515 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1516 radeon_emit(cs, cmd_buffer->state.index_va);
1517 radeon_emit(cs, cmd_buffer->state.index_va >> 32);
1518
1519 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1520 radeon_emit(cs, cmd_buffer->state.max_index_count);
1521
1522 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1523 }
1524
1525 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1526 {
1527 uint32_t db_count_control;
1528
1529 if(!cmd_buffer->state.active_occlusion_queries) {
1530 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1531 db_count_control = 0;
1532 } else {
1533 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1534 }
1535 } else {
1536 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1537 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1538 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1539 S_028004_ZPASS_ENABLE(1) |
1540 S_028004_SLICE_EVEN_ENABLE(1) |
1541 S_028004_SLICE_ODD_ENABLE(1);
1542 } else {
1543 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1544 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1545 }
1546 }
1547
1548 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1549 }
1550
1551 static void
1552 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1553 {
1554 if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1555 return;
1556
1557 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1558 radv_emit_viewport(cmd_buffer);
1559
1560 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1561 radv_emit_scissor(cmd_buffer);
1562
1563 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1564 radv_emit_line_width(cmd_buffer);
1565
1566 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1567 radv_emit_blend_constants(cmd_buffer);
1568
1569 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1570 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1571 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1572 radv_emit_stencil(cmd_buffer);
1573
1574 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1575 radv_emit_depth_bounds(cmd_buffer);
1576
1577 if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1578 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1579 radv_emit_depth_biais(cmd_buffer);
1580
1581 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1582 }
1583
1584 static void
1585 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1586 struct radv_pipeline *pipeline,
1587 int idx,
1588 uint64_t va,
1589 gl_shader_stage stage)
1590 {
1591 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1592 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
1593
1594 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1595 return;
1596
1597 assert(!desc_set_loc->indirect);
1598 assert(desc_set_loc->num_sgprs == 2);
1599 radeon_set_sh_reg_seq(cmd_buffer->cs,
1600 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1601 radeon_emit(cmd_buffer->cs, va);
1602 radeon_emit(cmd_buffer->cs, va >> 32);
1603 }
1604
1605 static void
1606 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1607 VkShaderStageFlags stages,
1608 struct radv_descriptor_set *set,
1609 unsigned idx)
1610 {
1611 if (cmd_buffer->state.pipeline) {
1612 radv_foreach_stage(stage, stages) {
1613 if (cmd_buffer->state.pipeline->shaders[stage])
1614 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1615 idx, set->va,
1616 stage);
1617 }
1618 }
1619
1620 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1621 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1622 idx, set->va,
1623 MESA_SHADER_COMPUTE);
1624 }
1625
1626 static void
1627 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1628 {
1629 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1630 unsigned bo_offset;
1631
1632 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1633 set->mapped_ptr,
1634 &bo_offset))
1635 return;
1636
1637 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1638 set->va += bo_offset;
1639 }
1640
1641 static void
1642 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1643 {
1644 uint32_t size = MAX_SETS * 2 * 4;
1645 uint32_t offset;
1646 void *ptr;
1647
1648 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1649 256, &offset, &ptr))
1650 return;
1651
1652 for (unsigned i = 0; i < MAX_SETS; i++) {
1653 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1654 uint64_t set_va = 0;
1655 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1656 if (set)
1657 set_va = set->va;
1658 uptr[0] = set_va & 0xffffffff;
1659 uptr[1] = set_va >> 32;
1660 }
1661
1662 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1663 va += offset;
1664
1665 if (cmd_buffer->state.pipeline) {
1666 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1667 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1668 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1669
1670 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1671 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1672 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1673
1674 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1675 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1676 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1677
1678 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1679 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1680 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1681
1682 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1683 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1684 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1685 }
1686
1687 if (cmd_buffer->state.compute_pipeline)
1688 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1689 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1690 }
1691
1692 static void
1693 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1694 VkShaderStageFlags stages)
1695 {
1696 unsigned i;
1697
1698 if (!cmd_buffer->state.descriptors_dirty)
1699 return;
1700
1701 if (cmd_buffer->state.push_descriptors_dirty)
1702 radv_flush_push_descriptors(cmd_buffer);
1703
1704 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1705 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1706 radv_flush_indirect_descriptor_sets(cmd_buffer);
1707 }
1708
1709 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1710 cmd_buffer->cs,
1711 MAX_SETS * MESA_SHADER_STAGES * 4);
1712
1713 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1714 struct radv_descriptor_set *set = cmd_buffer->state.descriptors[i];
1715 if (!set)
1716 continue;
1717
1718 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1719 }
1720 cmd_buffer->state.descriptors_dirty = 0;
1721 cmd_buffer->state.push_descriptors_dirty = false;
1722
1723 if (cmd_buffer->device->trace_bo)
1724 radv_save_descriptors(cmd_buffer);
1725
1726 assert(cmd_buffer->cs->cdw <= cdw_max);
1727 }
1728
1729 static void
1730 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1731 struct radv_pipeline *pipeline,
1732 VkShaderStageFlags stages)
1733 {
1734 struct radv_pipeline_layout *layout = pipeline->layout;
1735 unsigned offset;
1736 void *ptr;
1737 uint64_t va;
1738
1739 stages &= cmd_buffer->push_constant_stages;
1740 if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
1741 return;
1742
1743 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1744 16 * layout->dynamic_offset_count,
1745 256, &offset, &ptr))
1746 return;
1747
1748 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1749 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1750 16 * layout->dynamic_offset_count);
1751
1752 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1753 va += offset;
1754
1755 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1756 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1757
1758 radv_foreach_stage(stage, stages) {
1759 if (pipeline->shaders[stage]) {
1760 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1761 AC_UD_PUSH_CONSTANTS, va);
1762 }
1763 }
1764
1765 cmd_buffer->push_constant_stages &= ~stages;
1766 assert(cmd_buffer->cs->cdw <= cdw_max);
1767 }
1768
1769 static bool
1770 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1771 {
1772 struct radv_device *device = cmd_buffer->device;
1773
1774 if ((pipeline_is_dirty || cmd_buffer->state.vb_dirty) &&
1775 cmd_buffer->state.pipeline->vertex_elements.count &&
1776 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1777 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1778 unsigned vb_offset;
1779 void *vb_ptr;
1780 uint32_t i = 0;
1781 uint32_t count = velems->count;
1782 uint64_t va;
1783
1784 /* allocate some descriptor state for vertex buffers */
1785 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1786 &vb_offset, &vb_ptr))
1787 return false;
1788
1789 for (i = 0; i < count; i++) {
1790 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1791 uint32_t offset;
1792 int vb = velems->binding[i];
1793 struct radv_buffer *buffer = cmd_buffer->state.vertex_bindings[vb].buffer;
1794 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1795
1796 device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
1797 va = radv_buffer_get_va(buffer->bo);
1798
1799 offset = cmd_buffer->state.vertex_bindings[vb].offset + velems->offset[i];
1800 va += offset + buffer->offset;
1801 desc[0] = va;
1802 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1803 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1804 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1805 else
1806 desc[2] = buffer->size - offset;
1807 desc[3] = velems->rsrc_word3[i];
1808 }
1809
1810 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1811 va += vb_offset;
1812
1813 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1814 AC_UD_VS_VERTEX_BUFFERS, va);
1815 }
1816 cmd_buffer->state.vb_dirty = false;
1817
1818 return true;
1819 }
1820
1821 static bool
1822 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1823 {
1824 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1825 return false;
1826
1827 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1828 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1829 VK_SHADER_STAGE_ALL_GRAPHICS);
1830
1831 return true;
1832 }
1833
1834 static void
1835 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1836 bool instanced_draw, bool indirect_draw,
1837 uint32_t draw_vertex_count)
1838 {
1839 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1840 struct radv_cmd_state *state = &cmd_buffer->state;
1841 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1842 uint32_t ia_multi_vgt_param;
1843 int32_t primitive_reset_en;
1844
1845 /* Draw state. */
1846 ia_multi_vgt_param =
1847 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1848 indirect_draw, draw_vertex_count);
1849
1850 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1851 if (info->chip_class >= GFX9) {
1852 radeon_set_uconfig_reg_idx(cs,
1853 R_030960_IA_MULTI_VGT_PARAM,
1854 4, ia_multi_vgt_param);
1855 } else if (info->chip_class >= CIK) {
1856 radeon_set_context_reg_idx(cs,
1857 R_028AA8_IA_MULTI_VGT_PARAM,
1858 1, ia_multi_vgt_param);
1859 } else {
1860 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1861 ia_multi_vgt_param);
1862 }
1863 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1864 }
1865
1866 /* Primitive restart. */
1867 primitive_reset_en =
1868 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1869
1870 if (primitive_reset_en != state->last_primitive_reset_en) {
1871 state->last_primitive_reset_en = primitive_reset_en;
1872 if (info->chip_class >= GFX9) {
1873 radeon_set_uconfig_reg(cs,
1874 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1875 primitive_reset_en);
1876 } else {
1877 radeon_set_context_reg(cs,
1878 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1879 primitive_reset_en);
1880 }
1881 }
1882
1883 if (primitive_reset_en) {
1884 uint32_t primitive_reset_index =
1885 state->index_type ? 0xffffffffu : 0xffffu;
1886
1887 if (primitive_reset_index != state->last_primitive_reset_index) {
1888 radeon_set_context_reg(cs,
1889 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1890 primitive_reset_index);
1891 state->last_primitive_reset_index = primitive_reset_index;
1892 }
1893 }
1894 }
1895
1896 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1897 VkPipelineStageFlags src_stage_mask)
1898 {
1899 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1900 VK_PIPELINE_STAGE_TRANSFER_BIT |
1901 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1902 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1903 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1904 }
1905
1906 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1907 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1908 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1909 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1910 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1911 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1912 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1913 VK_PIPELINE_STAGE_TRANSFER_BIT |
1914 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1915 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1916 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1917 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1918 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1919 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1920 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1921 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1922 }
1923 }
1924
1925 static enum radv_cmd_flush_bits
1926 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1927 VkAccessFlags src_flags)
1928 {
1929 enum radv_cmd_flush_bits flush_bits = 0;
1930 uint32_t b;
1931 for_each_bit(b, src_flags) {
1932 switch ((VkAccessFlagBits)(1 << b)) {
1933 case VK_ACCESS_SHADER_WRITE_BIT:
1934 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1935 break;
1936 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1937 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1938 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1939 break;
1940 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1941 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1942 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1943 break;
1944 case VK_ACCESS_TRANSFER_WRITE_BIT:
1945 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1946 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1947 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1948 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1949 RADV_CMD_FLAG_INV_GLOBAL_L2;
1950 break;
1951 default:
1952 break;
1953 }
1954 }
1955 return flush_bits;
1956 }
1957
1958 static enum radv_cmd_flush_bits
1959 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1960 VkAccessFlags dst_flags,
1961 struct radv_image *image)
1962 {
1963 enum radv_cmd_flush_bits flush_bits = 0;
1964 uint32_t b;
1965 for_each_bit(b, dst_flags) {
1966 switch ((VkAccessFlagBits)(1 << b)) {
1967 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1968 case VK_ACCESS_INDEX_READ_BIT:
1969 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1970 break;
1971 case VK_ACCESS_UNIFORM_READ_BIT:
1972 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1973 break;
1974 case VK_ACCESS_SHADER_READ_BIT:
1975 case VK_ACCESS_TRANSFER_READ_BIT:
1976 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1977 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1978 RADV_CMD_FLAG_INV_GLOBAL_L2;
1979 break;
1980 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1981 /* TODO: change to image && when the image gets passed
1982 * through from the subpass. */
1983 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1984 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1985 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1986 break;
1987 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1988 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1989 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1990 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1991 break;
1992 default:
1993 break;
1994 }
1995 }
1996 return flush_bits;
1997 }
1998
1999 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2000 {
2001 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2002 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2003 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2004 NULL);
2005 }
2006
2007 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2008 VkAttachmentReference att)
2009 {
2010 unsigned idx = att.attachment;
2011 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2012 VkImageSubresourceRange range;
2013 range.aspectMask = 0;
2014 range.baseMipLevel = view->base_mip;
2015 range.levelCount = 1;
2016 range.baseArrayLayer = view->base_layer;
2017 range.layerCount = cmd_buffer->state.framebuffer->layers;
2018
2019 radv_handle_image_transition(cmd_buffer,
2020 view->image,
2021 cmd_buffer->state.attachments[idx].current_layout,
2022 att.layout, 0, 0, &range,
2023 cmd_buffer->state.attachments[idx].pending_clear_aspects);
2024
2025 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2026
2027
2028 }
2029
2030 void
2031 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2032 const struct radv_subpass *subpass, bool transitions)
2033 {
2034 if (transitions) {
2035 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2036
2037 for (unsigned i = 0; i < subpass->color_count; ++i) {
2038 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2039 radv_handle_subpass_image_transition(cmd_buffer,
2040 subpass->color_attachments[i]);
2041 }
2042
2043 for (unsigned i = 0; i < subpass->input_count; ++i) {
2044 radv_handle_subpass_image_transition(cmd_buffer,
2045 subpass->input_attachments[i]);
2046 }
2047
2048 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2049 radv_handle_subpass_image_transition(cmd_buffer,
2050 subpass->depth_stencil_attachment);
2051 }
2052 }
2053
2054 cmd_buffer->state.subpass = subpass;
2055
2056 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2057 }
2058
2059 static VkResult
2060 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2061 struct radv_render_pass *pass,
2062 const VkRenderPassBeginInfo *info)
2063 {
2064 struct radv_cmd_state *state = &cmd_buffer->state;
2065
2066 if (pass->attachment_count == 0) {
2067 state->attachments = NULL;
2068 return VK_SUCCESS;
2069 }
2070
2071 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2072 pass->attachment_count *
2073 sizeof(state->attachments[0]),
2074 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2075 if (state->attachments == NULL) {
2076 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2077 return cmd_buffer->record_result;
2078 }
2079
2080 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2081 struct radv_render_pass_attachment *att = &pass->attachments[i];
2082 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2083 VkImageAspectFlags clear_aspects = 0;
2084
2085 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2086 /* color attachment */
2087 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2088 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2089 }
2090 } else {
2091 /* depthstencil attachment */
2092 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2093 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2094 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2095 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2096 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2097 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2098 }
2099 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2100 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2101 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2102 }
2103 }
2104
2105 state->attachments[i].pending_clear_aspects = clear_aspects;
2106 state->attachments[i].cleared_views = 0;
2107 if (clear_aspects && info) {
2108 assert(info->clearValueCount > i);
2109 state->attachments[i].clear_value = info->pClearValues[i];
2110 }
2111
2112 state->attachments[i].current_layout = att->initial_layout;
2113 }
2114
2115 return VK_SUCCESS;
2116 }
2117
2118 VkResult radv_AllocateCommandBuffers(
2119 VkDevice _device,
2120 const VkCommandBufferAllocateInfo *pAllocateInfo,
2121 VkCommandBuffer *pCommandBuffers)
2122 {
2123 RADV_FROM_HANDLE(radv_device, device, _device);
2124 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2125
2126 VkResult result = VK_SUCCESS;
2127 uint32_t i;
2128
2129 memset(pCommandBuffers, 0,
2130 sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount);
2131
2132 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2133
2134 if (!list_empty(&pool->free_cmd_buffers)) {
2135 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2136
2137 list_del(&cmd_buffer->pool_link);
2138 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2139
2140 result = radv_reset_cmd_buffer(cmd_buffer);
2141 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2142 cmd_buffer->level = pAllocateInfo->level;
2143
2144 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2145 } else {
2146 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2147 &pCommandBuffers[i]);
2148 }
2149 if (result != VK_SUCCESS)
2150 break;
2151 }
2152
2153 if (result != VK_SUCCESS)
2154 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2155 i, pCommandBuffers);
2156
2157 return result;
2158 }
2159
2160 void radv_FreeCommandBuffers(
2161 VkDevice device,
2162 VkCommandPool commandPool,
2163 uint32_t commandBufferCount,
2164 const VkCommandBuffer *pCommandBuffers)
2165 {
2166 for (uint32_t i = 0; i < commandBufferCount; i++) {
2167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2168
2169 if (cmd_buffer) {
2170 if (cmd_buffer->pool) {
2171 list_del(&cmd_buffer->pool_link);
2172 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2173 } else
2174 radv_cmd_buffer_destroy(cmd_buffer);
2175
2176 }
2177 }
2178 }
2179
2180 VkResult radv_ResetCommandBuffer(
2181 VkCommandBuffer commandBuffer,
2182 VkCommandBufferResetFlags flags)
2183 {
2184 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2185 return radv_reset_cmd_buffer(cmd_buffer);
2186 }
2187
2188 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2189 {
2190 struct radv_device *device = cmd_buffer->device;
2191 if (device->gfx_init) {
2192 uint64_t va = radv_buffer_get_va(device->gfx_init);
2193 device->ws->cs_add_buffer(cmd_buffer->cs, device->gfx_init, 8);
2194 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2195 radeon_emit(cmd_buffer->cs, va);
2196 radeon_emit(cmd_buffer->cs, va >> 32);
2197 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2198 } else
2199 si_init_config(cmd_buffer);
2200 }
2201
2202 VkResult radv_BeginCommandBuffer(
2203 VkCommandBuffer commandBuffer,
2204 const VkCommandBufferBeginInfo *pBeginInfo)
2205 {
2206 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2207 VkResult result;
2208
2209 result = radv_reset_cmd_buffer(cmd_buffer);
2210 if (result != VK_SUCCESS)
2211 return result;
2212
2213 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2214 cmd_buffer->state.last_primitive_reset_en = -1;
2215 cmd_buffer->usage_flags = pBeginInfo->flags;
2216
2217 /* setup initial configuration into command buffer */
2218 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2219 switch (cmd_buffer->queue_family_index) {
2220 case RADV_QUEUE_GENERAL:
2221 emit_gfx_buffer_state(cmd_buffer);
2222 break;
2223 case RADV_QUEUE_COMPUTE:
2224 si_init_compute(cmd_buffer);
2225 break;
2226 case RADV_QUEUE_TRANSFER:
2227 default:
2228 break;
2229 }
2230 }
2231
2232 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2233 assert(pBeginInfo->pInheritanceInfo);
2234 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2235 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2236
2237 struct radv_subpass *subpass =
2238 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2239
2240 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2241 if (result != VK_SUCCESS)
2242 return result;
2243
2244 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2245 }
2246
2247 radv_cmd_buffer_trace_emit(cmd_buffer);
2248 return result;
2249 }
2250
2251 void radv_CmdBindVertexBuffers(
2252 VkCommandBuffer commandBuffer,
2253 uint32_t firstBinding,
2254 uint32_t bindingCount,
2255 const VkBuffer* pBuffers,
2256 const VkDeviceSize* pOffsets)
2257 {
2258 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2259 struct radv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
2260 bool changed = false;
2261
2262 /* We have to defer setting up vertex buffer since we need the buffer
2263 * stride from the pipeline. */
2264
2265 assert(firstBinding + bindingCount <= MAX_VBS);
2266 for (uint32_t i = 0; i < bindingCount; i++) {
2267 uint32_t idx = firstBinding + i;
2268
2269 if (!changed &&
2270 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2271 vb[idx].offset != pOffsets[i])) {
2272 changed = true;
2273 }
2274
2275 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2276 vb[idx].offset = pOffsets[i];
2277 }
2278
2279 if (!changed) {
2280 /* No state changes. */
2281 return;
2282 }
2283
2284 cmd_buffer->state.vb_dirty = true;
2285 }
2286
2287 void radv_CmdBindIndexBuffer(
2288 VkCommandBuffer commandBuffer,
2289 VkBuffer buffer,
2290 VkDeviceSize offset,
2291 VkIndexType indexType)
2292 {
2293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2294 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2295
2296 if (cmd_buffer->state.index_buffer == index_buffer &&
2297 cmd_buffer->state.index_offset == offset &&
2298 cmd_buffer->state.index_type == indexType) {
2299 /* No state changes. */
2300 return;
2301 }
2302
2303 cmd_buffer->state.index_buffer = index_buffer;
2304 cmd_buffer->state.index_offset = offset;
2305 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2306 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2307 cmd_buffer->state.index_va += index_buffer->offset + offset;
2308
2309 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2310 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2311 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2312 cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, index_buffer->bo, 8);
2313 }
2314
2315
2316 static void
2317 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2318 struct radv_descriptor_set *set, unsigned idx)
2319 {
2320 struct radeon_winsys *ws = cmd_buffer->device->ws;
2321
2322 cmd_buffer->state.descriptors[idx] = set;
2323 cmd_buffer->state.descriptors_dirty |= (1u << idx);
2324 if (!set)
2325 return;
2326
2327 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2328
2329 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2330 if (set->descriptors[j])
2331 ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
2332
2333 if(set->bo)
2334 ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
2335 }
2336
2337 void radv_CmdBindDescriptorSets(
2338 VkCommandBuffer commandBuffer,
2339 VkPipelineBindPoint pipelineBindPoint,
2340 VkPipelineLayout _layout,
2341 uint32_t firstSet,
2342 uint32_t descriptorSetCount,
2343 const VkDescriptorSet* pDescriptorSets,
2344 uint32_t dynamicOffsetCount,
2345 const uint32_t* pDynamicOffsets)
2346 {
2347 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2348 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2349 unsigned dyn_idx = 0;
2350
2351 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2352 unsigned idx = i + firstSet;
2353 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2354 radv_bind_descriptor_set(cmd_buffer, set, idx);
2355
2356 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2357 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2358 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2359 assert(dyn_idx < dynamicOffsetCount);
2360
2361 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2362 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2363 dst[0] = va;
2364 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2365 dst[2] = range->size;
2366 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2367 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2368 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2369 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2370 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2371 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2372 cmd_buffer->push_constant_stages |=
2373 set->layout->dynamic_shader_stages;
2374 }
2375 }
2376 }
2377
2378 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2379 struct radv_descriptor_set *set,
2380 struct radv_descriptor_set_layout *layout)
2381 {
2382 set->size = layout->size;
2383 set->layout = layout;
2384
2385 if (cmd_buffer->push_descriptors.capacity < set->size) {
2386 size_t new_size = MAX2(set->size, 1024);
2387 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2388 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2389
2390 free(set->mapped_ptr);
2391 set->mapped_ptr = malloc(new_size);
2392
2393 if (!set->mapped_ptr) {
2394 cmd_buffer->push_descriptors.capacity = 0;
2395 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2396 return false;
2397 }
2398
2399 cmd_buffer->push_descriptors.capacity = new_size;
2400 }
2401
2402 return true;
2403 }
2404
2405 void radv_meta_push_descriptor_set(
2406 struct radv_cmd_buffer* cmd_buffer,
2407 VkPipelineBindPoint pipelineBindPoint,
2408 VkPipelineLayout _layout,
2409 uint32_t set,
2410 uint32_t descriptorWriteCount,
2411 const VkWriteDescriptorSet* pDescriptorWrites)
2412 {
2413 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2414 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2415 unsigned bo_offset;
2416
2417 assert(set == 0);
2418 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2419
2420 push_set->size = layout->set[set].layout->size;
2421 push_set->layout = layout->set[set].layout;
2422
2423 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2424 &bo_offset,
2425 (void**) &push_set->mapped_ptr))
2426 return;
2427
2428 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2429 push_set->va += bo_offset;
2430
2431 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2432 radv_descriptor_set_to_handle(push_set),
2433 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2434
2435 cmd_buffer->state.descriptors[set] = push_set;
2436 cmd_buffer->state.descriptors_dirty |= (1u << set);
2437 }
2438
2439 void radv_CmdPushDescriptorSetKHR(
2440 VkCommandBuffer commandBuffer,
2441 VkPipelineBindPoint pipelineBindPoint,
2442 VkPipelineLayout _layout,
2443 uint32_t set,
2444 uint32_t descriptorWriteCount,
2445 const VkWriteDescriptorSet* pDescriptorWrites)
2446 {
2447 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2448 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2449 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2450
2451 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2452
2453 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2454 return;
2455
2456 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2457 radv_descriptor_set_to_handle(push_set),
2458 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2459
2460 cmd_buffer->state.descriptors[set] = push_set;
2461 cmd_buffer->state.descriptors_dirty |= (1u << set);
2462 cmd_buffer->state.push_descriptors_dirty = true;
2463 }
2464
2465 void radv_CmdPushDescriptorSetWithTemplateKHR(
2466 VkCommandBuffer commandBuffer,
2467 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2468 VkPipelineLayout _layout,
2469 uint32_t set,
2470 const void* pData)
2471 {
2472 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2473 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2474 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2475
2476 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2477
2478 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2479 return;
2480
2481 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2482 descriptorUpdateTemplate, pData);
2483
2484 cmd_buffer->state.descriptors[set] = push_set;
2485 cmd_buffer->state.descriptors_dirty |= (1u << set);
2486 cmd_buffer->state.push_descriptors_dirty = true;
2487 }
2488
2489 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2490 VkPipelineLayout layout,
2491 VkShaderStageFlags stageFlags,
2492 uint32_t offset,
2493 uint32_t size,
2494 const void* pValues)
2495 {
2496 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2497 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2498 cmd_buffer->push_constant_stages |= stageFlags;
2499 }
2500
2501 VkResult radv_EndCommandBuffer(
2502 VkCommandBuffer commandBuffer)
2503 {
2504 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2505
2506 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2507 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2508 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2509 si_emit_cache_flush(cmd_buffer);
2510 }
2511
2512 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2513 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2514
2515 return cmd_buffer->record_result;
2516 }
2517
2518 static void
2519 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2520 {
2521 struct radv_shader_variant *compute_shader;
2522 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2523 uint64_t va;
2524
2525 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2526 return;
2527
2528 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2529
2530 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2531 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2532
2533 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2534 cmd_buffer->cs, 16);
2535
2536 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2537 radeon_emit(cmd_buffer->cs, va >> 8);
2538 radeon_emit(cmd_buffer->cs, va >> 40);
2539
2540 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2541 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2542 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2543
2544
2545 cmd_buffer->compute_scratch_size_needed =
2546 MAX2(cmd_buffer->compute_scratch_size_needed,
2547 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2548
2549 /* change these once we have scratch support */
2550 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2551 S_00B860_WAVES(pipeline->max_waves) |
2552 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2553
2554 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2555 radeon_emit(cmd_buffer->cs,
2556 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2557 radeon_emit(cmd_buffer->cs,
2558 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2559 radeon_emit(cmd_buffer->cs,
2560 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2561
2562 assert(cmd_buffer->cs->cdw <= cdw_max);
2563 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2564 }
2565
2566 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2567 {
2568 for (unsigned i = 0; i < MAX_SETS; i++) {
2569 if (cmd_buffer->state.descriptors[i])
2570 cmd_buffer->state.descriptors_dirty |= (1u << i);
2571 }
2572 }
2573
2574 void radv_CmdBindPipeline(
2575 VkCommandBuffer commandBuffer,
2576 VkPipelineBindPoint pipelineBindPoint,
2577 VkPipeline _pipeline)
2578 {
2579 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2580 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2581
2582 switch (pipelineBindPoint) {
2583 case VK_PIPELINE_BIND_POINT_COMPUTE:
2584 if (cmd_buffer->state.compute_pipeline == pipeline)
2585 return;
2586 radv_mark_descriptor_sets_dirty(cmd_buffer);
2587
2588 cmd_buffer->state.compute_pipeline = pipeline;
2589 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2590 break;
2591 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2592 if (cmd_buffer->state.pipeline == pipeline)
2593 return;
2594 radv_mark_descriptor_sets_dirty(cmd_buffer);
2595
2596 cmd_buffer->state.pipeline = pipeline;
2597 if (!pipeline)
2598 break;
2599
2600 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2601 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2602
2603 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2604
2605 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2606 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2607 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2608 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2609
2610 if (radv_pipeline_has_tess(pipeline))
2611 cmd_buffer->tess_rings_needed = true;
2612
2613 if (radv_pipeline_has_gs(pipeline)) {
2614 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2615 AC_UD_SCRATCH_RING_OFFSETS);
2616 if (cmd_buffer->ring_offsets_idx == -1)
2617 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2618 else if (loc->sgpr_idx != -1)
2619 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2620 }
2621 break;
2622 default:
2623 assert(!"invalid bind point");
2624 break;
2625 }
2626 }
2627
2628 void radv_CmdSetViewport(
2629 VkCommandBuffer commandBuffer,
2630 uint32_t firstViewport,
2631 uint32_t viewportCount,
2632 const VkViewport* pViewports)
2633 {
2634 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2635 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2636
2637 assert(firstViewport < MAX_VIEWPORTS);
2638 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2639
2640 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
2641 pViewports, viewportCount * sizeof(*pViewports));
2642
2643 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2644 }
2645
2646 void radv_CmdSetScissor(
2647 VkCommandBuffer commandBuffer,
2648 uint32_t firstScissor,
2649 uint32_t scissorCount,
2650 const VkRect2D* pScissors)
2651 {
2652 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2654
2655 assert(firstScissor < MAX_SCISSORS);
2656 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2657
2658 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
2659 pScissors, scissorCount * sizeof(*pScissors));
2660 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2661 }
2662
2663 void radv_CmdSetLineWidth(
2664 VkCommandBuffer commandBuffer,
2665 float lineWidth)
2666 {
2667 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2668 cmd_buffer->state.dynamic.line_width = lineWidth;
2669 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2670 }
2671
2672 void radv_CmdSetDepthBias(
2673 VkCommandBuffer commandBuffer,
2674 float depthBiasConstantFactor,
2675 float depthBiasClamp,
2676 float depthBiasSlopeFactor)
2677 {
2678 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2679
2680 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2681 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2682 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2683
2684 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2685 }
2686
2687 void radv_CmdSetBlendConstants(
2688 VkCommandBuffer commandBuffer,
2689 const float blendConstants[4])
2690 {
2691 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2692
2693 memcpy(cmd_buffer->state.dynamic.blend_constants,
2694 blendConstants, sizeof(float) * 4);
2695
2696 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2697 }
2698
2699 void radv_CmdSetDepthBounds(
2700 VkCommandBuffer commandBuffer,
2701 float minDepthBounds,
2702 float maxDepthBounds)
2703 {
2704 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2705
2706 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2707 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2708
2709 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2710 }
2711
2712 void radv_CmdSetStencilCompareMask(
2713 VkCommandBuffer commandBuffer,
2714 VkStencilFaceFlags faceMask,
2715 uint32_t compareMask)
2716 {
2717 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2718
2719 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2720 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2721 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2722 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2723
2724 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2725 }
2726
2727 void radv_CmdSetStencilWriteMask(
2728 VkCommandBuffer commandBuffer,
2729 VkStencilFaceFlags faceMask,
2730 uint32_t writeMask)
2731 {
2732 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2733
2734 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2735 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2736 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2737 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2738
2739 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2740 }
2741
2742 void radv_CmdSetStencilReference(
2743 VkCommandBuffer commandBuffer,
2744 VkStencilFaceFlags faceMask,
2745 uint32_t reference)
2746 {
2747 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2748
2749 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2750 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2751 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2752 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2753
2754 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2755 }
2756
2757 void radv_CmdExecuteCommands(
2758 VkCommandBuffer commandBuffer,
2759 uint32_t commandBufferCount,
2760 const VkCommandBuffer* pCmdBuffers)
2761 {
2762 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2763
2764 assert(commandBufferCount > 0);
2765
2766 /* Emit pending flushes on primary prior to executing secondary */
2767 si_emit_cache_flush(primary);
2768
2769 for (uint32_t i = 0; i < commandBufferCount; i++) {
2770 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2771
2772 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2773 secondary->scratch_size_needed);
2774 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2775 secondary->compute_scratch_size_needed);
2776
2777 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2778 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2779 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2780 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2781 if (secondary->tess_rings_needed)
2782 primary->tess_rings_needed = true;
2783 if (secondary->sample_positions_needed)
2784 primary->sample_positions_needed = true;
2785
2786 if (secondary->ring_offsets_idx != -1) {
2787 if (primary->ring_offsets_idx == -1)
2788 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2789 else
2790 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2791 }
2792 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2793
2794
2795 /* When the secondary command buffer is compute only we don't
2796 * need to re-emit the current graphics pipeline.
2797 */
2798 if (secondary->state.emitted_pipeline) {
2799 primary->state.emitted_pipeline =
2800 secondary->state.emitted_pipeline;
2801 }
2802
2803 /* When the secondary command buffer is graphics only we don't
2804 * need to re-emit the current compute pipeline.
2805 */
2806 if (secondary->state.emitted_compute_pipeline) {
2807 primary->state.emitted_compute_pipeline =
2808 secondary->state.emitted_compute_pipeline;
2809 }
2810
2811 /* Only re-emit the draw packets when needed. */
2812 if (secondary->state.last_primitive_reset_en != -1) {
2813 primary->state.last_primitive_reset_en =
2814 secondary->state.last_primitive_reset_en;
2815 }
2816
2817 if (secondary->state.last_primitive_reset_index) {
2818 primary->state.last_primitive_reset_index =
2819 secondary->state.last_primitive_reset_index;
2820 }
2821
2822 if (secondary->state.last_ia_multi_vgt_param) {
2823 primary->state.last_ia_multi_vgt_param =
2824 secondary->state.last_ia_multi_vgt_param;
2825 }
2826 }
2827
2828 /* After executing commands from secondary buffers we have to dirty
2829 * some states.
2830 */
2831 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2832 RADV_CMD_DIRTY_INDEX_BUFFER |
2833 RADV_CMD_DIRTY_DYNAMIC_ALL;
2834 radv_mark_descriptor_sets_dirty(primary);
2835 }
2836
2837 VkResult radv_CreateCommandPool(
2838 VkDevice _device,
2839 const VkCommandPoolCreateInfo* pCreateInfo,
2840 const VkAllocationCallbacks* pAllocator,
2841 VkCommandPool* pCmdPool)
2842 {
2843 RADV_FROM_HANDLE(radv_device, device, _device);
2844 struct radv_cmd_pool *pool;
2845
2846 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2847 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2848 if (pool == NULL)
2849 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2850
2851 if (pAllocator)
2852 pool->alloc = *pAllocator;
2853 else
2854 pool->alloc = device->alloc;
2855
2856 list_inithead(&pool->cmd_buffers);
2857 list_inithead(&pool->free_cmd_buffers);
2858
2859 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2860
2861 *pCmdPool = radv_cmd_pool_to_handle(pool);
2862
2863 return VK_SUCCESS;
2864
2865 }
2866
2867 void radv_DestroyCommandPool(
2868 VkDevice _device,
2869 VkCommandPool commandPool,
2870 const VkAllocationCallbacks* pAllocator)
2871 {
2872 RADV_FROM_HANDLE(radv_device, device, _device);
2873 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2874
2875 if (!pool)
2876 return;
2877
2878 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2879 &pool->cmd_buffers, pool_link) {
2880 radv_cmd_buffer_destroy(cmd_buffer);
2881 }
2882
2883 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2884 &pool->free_cmd_buffers, pool_link) {
2885 radv_cmd_buffer_destroy(cmd_buffer);
2886 }
2887
2888 vk_free2(&device->alloc, pAllocator, pool);
2889 }
2890
2891 VkResult radv_ResetCommandPool(
2892 VkDevice device,
2893 VkCommandPool commandPool,
2894 VkCommandPoolResetFlags flags)
2895 {
2896 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2897 VkResult result;
2898
2899 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2900 &pool->cmd_buffers, pool_link) {
2901 result = radv_reset_cmd_buffer(cmd_buffer);
2902 if (result != VK_SUCCESS)
2903 return result;
2904 }
2905
2906 return VK_SUCCESS;
2907 }
2908
2909 void radv_TrimCommandPoolKHR(
2910 VkDevice device,
2911 VkCommandPool commandPool,
2912 VkCommandPoolTrimFlagsKHR flags)
2913 {
2914 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2915
2916 if (!pool)
2917 return;
2918
2919 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2920 &pool->free_cmd_buffers, pool_link) {
2921 radv_cmd_buffer_destroy(cmd_buffer);
2922 }
2923 }
2924
2925 void radv_CmdBeginRenderPass(
2926 VkCommandBuffer commandBuffer,
2927 const VkRenderPassBeginInfo* pRenderPassBegin,
2928 VkSubpassContents contents)
2929 {
2930 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2931 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2932 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2933
2934 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2935 cmd_buffer->cs, 2048);
2936 MAYBE_UNUSED VkResult result;
2937
2938 cmd_buffer->state.framebuffer = framebuffer;
2939 cmd_buffer->state.pass = pass;
2940 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2941
2942 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2943 if (result != VK_SUCCESS)
2944 return;
2945
2946 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2947 assert(cmd_buffer->cs->cdw <= cdw_max);
2948
2949 radv_cmd_buffer_clear_subpass(cmd_buffer);
2950 }
2951
2952 void radv_CmdNextSubpass(
2953 VkCommandBuffer commandBuffer,
2954 VkSubpassContents contents)
2955 {
2956 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2957
2958 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2959
2960 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2961 2048);
2962
2963 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2964 radv_cmd_buffer_clear_subpass(cmd_buffer);
2965 }
2966
2967 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2968 {
2969 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2970 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2971 if (!pipeline->shaders[stage])
2972 continue;
2973 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2974 if (loc->sgpr_idx == -1)
2975 continue;
2976 uint32_t base_reg = radv_shader_stage_to_user_data_0(stage, cmd_buffer->device->physical_device->rad_info.chip_class, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
2977 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2978
2979 }
2980 if (pipeline->gs_copy_shader) {
2981 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2982 if (loc->sgpr_idx != -1) {
2983 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2984 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2985 }
2986 }
2987 }
2988
2989 static void
2990 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2991 uint32_t vertex_count)
2992 {
2993 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2994 radeon_emit(cmd_buffer->cs, vertex_count);
2995 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2996 S_0287F0_USE_OPAQUE(0));
2997 }
2998
2999 static void
3000 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3001 uint64_t index_va,
3002 uint32_t index_count)
3003 {
3004 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3005 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3006 radeon_emit(cmd_buffer->cs, index_va);
3007 radeon_emit(cmd_buffer->cs, index_va >> 32);
3008 radeon_emit(cmd_buffer->cs, index_count);
3009 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3010 }
3011
3012 static void
3013 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3014 bool indexed,
3015 uint32_t draw_count,
3016 uint64_t count_va,
3017 uint32_t stride)
3018 {
3019 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3020 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3021 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3022 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3023 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3024 assert(base_reg);
3025
3026 if (draw_count == 1 && !count_va && !draw_id_enable) {
3027 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3028 PKT3_DRAW_INDIRECT, 3, false));
3029 radeon_emit(cs, 0);
3030 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3031 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3032 radeon_emit(cs, di_src_sel);
3033 } else {
3034 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3035 PKT3_DRAW_INDIRECT_MULTI,
3036 8, false));
3037 radeon_emit(cs, 0);
3038 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3039 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3040 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3041 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3042 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3043 radeon_emit(cs, draw_count); /* count */
3044 radeon_emit(cs, count_va); /* count_addr */
3045 radeon_emit(cs, count_va >> 32);
3046 radeon_emit(cs, stride); /* stride */
3047 radeon_emit(cs, di_src_sel);
3048 }
3049 }
3050
3051 struct radv_draw_info {
3052 /**
3053 * Number of vertices.
3054 */
3055 uint32_t count;
3056
3057 /**
3058 * Index of the first vertex.
3059 */
3060 int32_t vertex_offset;
3061
3062 /**
3063 * First instance id.
3064 */
3065 uint32_t first_instance;
3066
3067 /**
3068 * Number of instances.
3069 */
3070 uint32_t instance_count;
3071
3072 /**
3073 * First index (indexed draws only).
3074 */
3075 uint32_t first_index;
3076
3077 /**
3078 * Whether it's an indexed draw.
3079 */
3080 bool indexed;
3081
3082 /**
3083 * Indirect draw parameters resource.
3084 */
3085 struct radv_buffer *indirect;
3086 uint64_t indirect_offset;
3087 uint32_t stride;
3088
3089 /**
3090 * Draw count parameters resource.
3091 */
3092 struct radv_buffer *count_buffer;
3093 uint64_t count_buffer_offset;
3094 };
3095
3096 static void
3097 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3098 const struct radv_draw_info *info)
3099 {
3100 struct radv_cmd_state *state = &cmd_buffer->state;
3101 struct radeon_winsys *ws = cmd_buffer->device->ws;
3102 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3103
3104 if (info->indirect) {
3105 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3106 uint64_t count_va = 0;
3107
3108 va += info->indirect->offset + info->indirect_offset;
3109
3110 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3111
3112 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3113 radeon_emit(cs, 1);
3114 radeon_emit(cs, va);
3115 radeon_emit(cs, va >> 32);
3116
3117 if (info->count_buffer) {
3118 count_va = radv_buffer_get_va(info->count_buffer->bo);
3119 count_va += info->count_buffer->offset +
3120 info->count_buffer_offset;
3121
3122 ws->cs_add_buffer(cs, info->count_buffer->bo, 8);
3123 }
3124
3125 if (!state->subpass->view_mask) {
3126 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3127 info->indexed,
3128 info->count,
3129 count_va,
3130 info->stride);
3131 } else {
3132 unsigned i;
3133 for_each_bit(i, state->subpass->view_mask) {
3134 radv_emit_view_index(cmd_buffer, i);
3135
3136 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3137 info->indexed,
3138 info->count,
3139 count_va,
3140 info->stride);
3141 }
3142 }
3143 } else {
3144 assert(state->pipeline->graphics.vtx_base_sgpr);
3145 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3146 state->pipeline->graphics.vtx_emit_num);
3147 radeon_emit(cs, info->vertex_offset);
3148 radeon_emit(cs, info->first_instance);
3149 if (state->pipeline->graphics.vtx_emit_num == 3)
3150 radeon_emit(cs, 0);
3151
3152 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3153 radeon_emit(cs, info->instance_count);
3154
3155 if (info->indexed) {
3156 int index_size = state->index_type ? 4 : 2;
3157 uint64_t index_va;
3158
3159 index_va = state->index_va;
3160 index_va += info->first_index * index_size;
3161
3162 if (!state->subpass->view_mask) {
3163 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3164 index_va,
3165 info->count);
3166 } else {
3167 unsigned i;
3168 for_each_bit(i, state->subpass->view_mask) {
3169 radv_emit_view_index(cmd_buffer, i);
3170
3171 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3172 index_va,
3173 info->count);
3174 }
3175 }
3176 } else {
3177 if (!state->subpass->view_mask) {
3178 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3179 } else {
3180 unsigned i;
3181 for_each_bit(i, state->subpass->view_mask) {
3182 radv_emit_view_index(cmd_buffer, i);
3183
3184 radv_cs_emit_draw_packet(cmd_buffer,
3185 info->count);
3186 }
3187 }
3188 }
3189 }
3190 }
3191
3192 static void
3193 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3194 const struct radv_draw_info *info)
3195 {
3196 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3197 radv_emit_graphics_pipeline(cmd_buffer);
3198
3199 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3200 radv_emit_framebuffer_state(cmd_buffer);
3201
3202 if (info->indexed) {
3203 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3204 radv_emit_index_buffer(cmd_buffer);
3205 } else {
3206 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3207 * so the state must be re-emitted before the next indexed
3208 * draw.
3209 */
3210 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
3211 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3212 }
3213
3214 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3215
3216 radv_emit_draw_registers(cmd_buffer, info->indexed,
3217 info->instance_count > 1, info->indirect,
3218 info->indirect ? 0 : info->count);
3219 }
3220
3221 static void
3222 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3223 const struct radv_draw_info *info)
3224 {
3225 bool pipeline_is_dirty =
3226 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3227 cmd_buffer->state.pipeline &&
3228 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3229
3230 MAYBE_UNUSED unsigned cdw_max =
3231 radeon_check_space(cmd_buffer->device->ws,
3232 cmd_buffer->cs, 4096);
3233
3234 /* Use optimal packet order based on whether we need to sync the
3235 * pipeline.
3236 */
3237 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3238 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3239 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3240 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3241 /* If we have to wait for idle, set all states first, so that
3242 * all SET packets are processed in parallel with previous draw
3243 * calls. Then upload descriptors, set shader pointers, and
3244 * draw, and prefetch at the end. This ensures that the time
3245 * the CUs are idle is very short. (there are only SET_SH
3246 * packets between the wait and the draw)
3247 */
3248 radv_emit_all_graphics_states(cmd_buffer, info);
3249 si_emit_cache_flush(cmd_buffer);
3250 /* <-- CUs are idle here --> */
3251
3252 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3253 return;
3254
3255 radv_emit_draw_packets(cmd_buffer, info);
3256 /* <-- CUs are busy here --> */
3257
3258 /* Start prefetches after the draw has been started. Both will
3259 * run in parallel, but starting the draw first is more
3260 * important.
3261 */
3262 if (pipeline_is_dirty) {
3263 radv_emit_shaders_prefetch(cmd_buffer,
3264 cmd_buffer->state.pipeline);
3265 }
3266 } else {
3267 /* If we don't wait for idle, start prefetches first, then set
3268 * states, and draw at the end.
3269 */
3270 si_emit_cache_flush(cmd_buffer);
3271
3272 if (pipeline_is_dirty) {
3273 radv_emit_shaders_prefetch(cmd_buffer,
3274 cmd_buffer->state.pipeline);
3275 }
3276
3277 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3278 return;
3279
3280 radv_emit_all_graphics_states(cmd_buffer, info);
3281 radv_emit_draw_packets(cmd_buffer, info);
3282 }
3283
3284 assert(cmd_buffer->cs->cdw <= cdw_max);
3285 radv_cmd_buffer_after_draw(cmd_buffer);
3286 }
3287
3288 void radv_CmdDraw(
3289 VkCommandBuffer commandBuffer,
3290 uint32_t vertexCount,
3291 uint32_t instanceCount,
3292 uint32_t firstVertex,
3293 uint32_t firstInstance)
3294 {
3295 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3296 struct radv_draw_info info = {};
3297
3298 info.count = vertexCount;
3299 info.instance_count = instanceCount;
3300 info.first_instance = firstInstance;
3301 info.vertex_offset = firstVertex;
3302
3303 radv_draw(cmd_buffer, &info);
3304 }
3305
3306 void radv_CmdDrawIndexed(
3307 VkCommandBuffer commandBuffer,
3308 uint32_t indexCount,
3309 uint32_t instanceCount,
3310 uint32_t firstIndex,
3311 int32_t vertexOffset,
3312 uint32_t firstInstance)
3313 {
3314 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3315 struct radv_draw_info info = {};
3316
3317 info.indexed = true;
3318 info.count = indexCount;
3319 info.instance_count = instanceCount;
3320 info.first_index = firstIndex;
3321 info.vertex_offset = vertexOffset;
3322 info.first_instance = firstInstance;
3323
3324 radv_draw(cmd_buffer, &info);
3325 }
3326
3327 void radv_CmdDrawIndirect(
3328 VkCommandBuffer commandBuffer,
3329 VkBuffer _buffer,
3330 VkDeviceSize offset,
3331 uint32_t drawCount,
3332 uint32_t stride)
3333 {
3334 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3335 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3336 struct radv_draw_info info = {};
3337
3338 info.count = drawCount;
3339 info.indirect = buffer;
3340 info.indirect_offset = offset;
3341 info.stride = stride;
3342
3343 radv_draw(cmd_buffer, &info);
3344 }
3345
3346 void radv_CmdDrawIndexedIndirect(
3347 VkCommandBuffer commandBuffer,
3348 VkBuffer _buffer,
3349 VkDeviceSize offset,
3350 uint32_t drawCount,
3351 uint32_t stride)
3352 {
3353 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3354 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3355 struct radv_draw_info info = {};
3356
3357 info.indexed = true;
3358 info.count = drawCount;
3359 info.indirect = buffer;
3360 info.indirect_offset = offset;
3361 info.stride = stride;
3362
3363 radv_draw(cmd_buffer, &info);
3364 }
3365
3366 void radv_CmdDrawIndirectCountAMD(
3367 VkCommandBuffer commandBuffer,
3368 VkBuffer _buffer,
3369 VkDeviceSize offset,
3370 VkBuffer _countBuffer,
3371 VkDeviceSize countBufferOffset,
3372 uint32_t maxDrawCount,
3373 uint32_t stride)
3374 {
3375 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3376 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3377 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3378 struct radv_draw_info info = {};
3379
3380 info.count = maxDrawCount;
3381 info.indirect = buffer;
3382 info.indirect_offset = offset;
3383 info.count_buffer = count_buffer;
3384 info.count_buffer_offset = countBufferOffset;
3385 info.stride = stride;
3386
3387 radv_draw(cmd_buffer, &info);
3388 }
3389
3390 void radv_CmdDrawIndexedIndirectCountAMD(
3391 VkCommandBuffer commandBuffer,
3392 VkBuffer _buffer,
3393 VkDeviceSize offset,
3394 VkBuffer _countBuffer,
3395 VkDeviceSize countBufferOffset,
3396 uint32_t maxDrawCount,
3397 uint32_t stride)
3398 {
3399 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3400 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3401 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3402 struct radv_draw_info info = {};
3403
3404 info.indexed = true;
3405 info.count = maxDrawCount;
3406 info.indirect = buffer;
3407 info.indirect_offset = offset;
3408 info.count_buffer = count_buffer;
3409 info.count_buffer_offset = countBufferOffset;
3410 info.stride = stride;
3411
3412 radv_draw(cmd_buffer, &info);
3413 }
3414
3415 struct radv_dispatch_info {
3416 /**
3417 * Determine the layout of the grid (in block units) to be used.
3418 */
3419 uint32_t blocks[3];
3420
3421 /**
3422 * Whether it's an unaligned compute dispatch.
3423 */
3424 bool unaligned;
3425
3426 /**
3427 * Indirect compute parameters resource.
3428 */
3429 struct radv_buffer *indirect;
3430 uint64_t indirect_offset;
3431 };
3432
3433 static void
3434 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3435 const struct radv_dispatch_info *info)
3436 {
3437 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3438 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3439 struct radeon_winsys *ws = cmd_buffer->device->ws;
3440 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3441 struct ac_userdata_info *loc;
3442 unsigned dispatch_initiator;
3443 uint8_t grid_used;
3444
3445 grid_used = compute_shader->info.info.cs.grid_components_used;
3446
3447 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3448 AC_UD_CS_GRID_SIZE);
3449
3450 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3451
3452 dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
3453 S_00B800_FORCE_START_AT_000(1);
3454
3455 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3456 /* If the KMD allows it (there is a KMD hw register for it),
3457 * allow launching waves out-of-order.
3458 */
3459 dispatch_initiator |= S_00B800_ORDER_MODE(1);
3460 }
3461
3462 if (info->indirect) {
3463 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3464
3465 va += info->indirect->offset + info->indirect_offset;
3466
3467 ws->cs_add_buffer(cs, info->indirect->bo, 8);
3468
3469 if (loc->sgpr_idx != -1) {
3470 for (unsigned i = 0; i < grid_used; ++i) {
3471 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3472 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3473 COPY_DATA_DST_SEL(COPY_DATA_REG));
3474 radeon_emit(cs, (va + 4 * i));
3475 radeon_emit(cs, (va + 4 * i) >> 32);
3476 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3477 + loc->sgpr_idx * 4) >> 2) + i);
3478 radeon_emit(cs, 0);
3479 }
3480 }
3481
3482 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3483 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3484 PKT3_SHADER_TYPE_S(1));
3485 radeon_emit(cs, va);
3486 radeon_emit(cs, va >> 32);
3487 radeon_emit(cs, dispatch_initiator);
3488 } else {
3489 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3490 PKT3_SHADER_TYPE_S(1));
3491 radeon_emit(cs, 1);
3492 radeon_emit(cs, va);
3493 radeon_emit(cs, va >> 32);
3494
3495 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3496 PKT3_SHADER_TYPE_S(1));
3497 radeon_emit(cs, 0);
3498 radeon_emit(cs, dispatch_initiator);
3499 }
3500 } else {
3501 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3502
3503 if (info->unaligned) {
3504 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3505 unsigned remainder[3];
3506
3507 /* If aligned, these should be an entire block size,
3508 * not 0.
3509 */
3510 remainder[0] = blocks[0] + cs_block_size[0] -
3511 align_u32_npot(blocks[0], cs_block_size[0]);
3512 remainder[1] = blocks[1] + cs_block_size[1] -
3513 align_u32_npot(blocks[1], cs_block_size[1]);
3514 remainder[2] = blocks[2] + cs_block_size[2] -
3515 align_u32_npot(blocks[2], cs_block_size[2]);
3516
3517 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3518 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3519 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3520
3521 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3522 radeon_emit(cs,
3523 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3524 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3525 radeon_emit(cs,
3526 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3527 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3528 radeon_emit(cs,
3529 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3530 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3531
3532 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3533 }
3534
3535 if (loc->sgpr_idx != -1) {
3536 assert(!loc->indirect);
3537 assert(loc->num_sgprs == grid_used);
3538
3539 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3540 loc->sgpr_idx * 4, grid_used);
3541 radeon_emit(cs, blocks[0]);
3542 if (grid_used > 1)
3543 radeon_emit(cs, blocks[1]);
3544 if (grid_used > 2)
3545 radeon_emit(cs, blocks[2]);
3546 }
3547
3548 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3549 PKT3_SHADER_TYPE_S(1));
3550 radeon_emit(cs, blocks[0]);
3551 radeon_emit(cs, blocks[1]);
3552 radeon_emit(cs, blocks[2]);
3553 radeon_emit(cs, dispatch_initiator);
3554 }
3555
3556 assert(cmd_buffer->cs->cdw <= cdw_max);
3557 }
3558
3559 static void
3560 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3561 {
3562 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3563 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3564 VK_SHADER_STAGE_COMPUTE_BIT);
3565 }
3566
3567 static void
3568 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3569 const struct radv_dispatch_info *info)
3570 {
3571 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3572 bool pipeline_is_dirty = pipeline &&
3573 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3574
3575 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3576 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3577 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3578 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3579 /* If we have to wait for idle, set all states first, so that
3580 * all SET packets are processed in parallel with previous draw
3581 * calls. Then upload descriptors, set shader pointers, and
3582 * dispatch, and prefetch at the end. This ensures that the
3583 * time the CUs are idle is very short. (there are only SET_SH
3584 * packets between the wait and the draw)
3585 */
3586 radv_emit_compute_pipeline(cmd_buffer);
3587 si_emit_cache_flush(cmd_buffer);
3588 /* <-- CUs are idle here --> */
3589
3590 radv_upload_compute_shader_descriptors(cmd_buffer);
3591
3592 radv_emit_dispatch_packets(cmd_buffer, info);
3593 /* <-- CUs are busy here --> */
3594
3595 /* Start prefetches after the dispatch has been started. Both
3596 * will run in parallel, but starting the dispatch first is
3597 * more important.
3598 */
3599 if (pipeline_is_dirty) {
3600 radv_emit_shader_prefetch(cmd_buffer,
3601 pipeline->shaders[MESA_SHADER_COMPUTE]);
3602 }
3603 } else {
3604 /* If we don't wait for idle, start prefetches first, then set
3605 * states, and dispatch at the end.
3606 */
3607 si_emit_cache_flush(cmd_buffer);
3608
3609 if (pipeline_is_dirty) {
3610 radv_emit_shader_prefetch(cmd_buffer,
3611 pipeline->shaders[MESA_SHADER_COMPUTE]);
3612 }
3613
3614 radv_upload_compute_shader_descriptors(cmd_buffer);
3615
3616 radv_emit_compute_pipeline(cmd_buffer);
3617 radv_emit_dispatch_packets(cmd_buffer, info);
3618 }
3619
3620 radv_cmd_buffer_after_draw(cmd_buffer);
3621 }
3622
3623 void radv_CmdDispatch(
3624 VkCommandBuffer commandBuffer,
3625 uint32_t x,
3626 uint32_t y,
3627 uint32_t z)
3628 {
3629 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3630 struct radv_dispatch_info info = {};
3631
3632 info.blocks[0] = x;
3633 info.blocks[1] = y;
3634 info.blocks[2] = z;
3635
3636 radv_dispatch(cmd_buffer, &info);
3637 }
3638
3639 void radv_CmdDispatchIndirect(
3640 VkCommandBuffer commandBuffer,
3641 VkBuffer _buffer,
3642 VkDeviceSize offset)
3643 {
3644 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3645 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3646 struct radv_dispatch_info info = {};
3647
3648 info.indirect = buffer;
3649 info.indirect_offset = offset;
3650
3651 radv_dispatch(cmd_buffer, &info);
3652 }
3653
3654 void radv_unaligned_dispatch(
3655 struct radv_cmd_buffer *cmd_buffer,
3656 uint32_t x,
3657 uint32_t y,
3658 uint32_t z)
3659 {
3660 struct radv_dispatch_info info = {};
3661
3662 info.blocks[0] = x;
3663 info.blocks[1] = y;
3664 info.blocks[2] = z;
3665 info.unaligned = 1;
3666
3667 radv_dispatch(cmd_buffer, &info);
3668 }
3669
3670 void radv_CmdEndRenderPass(
3671 VkCommandBuffer commandBuffer)
3672 {
3673 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3674
3675 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3676
3677 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3678
3679 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3680 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3681 radv_handle_subpass_image_transition(cmd_buffer,
3682 (VkAttachmentReference){i, layout});
3683 }
3684
3685 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3686
3687 cmd_buffer->state.pass = NULL;
3688 cmd_buffer->state.subpass = NULL;
3689 cmd_buffer->state.attachments = NULL;
3690 cmd_buffer->state.framebuffer = NULL;
3691 }
3692
3693 /*
3694 * For HTILE we have the following interesting clear words:
3695 * 0x0000030f: Uncompressed.
3696 * 0xfffffff0: Clear depth to 1.0
3697 * 0x00000000: Clear depth to 0.0
3698 */
3699 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3700 struct radv_image *image,
3701 const VkImageSubresourceRange *range,
3702 uint32_t clear_word)
3703 {
3704 assert(range->baseMipLevel == 0);
3705 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3706 unsigned layer_count = radv_get_layerCount(image, range);
3707 uint64_t size = image->surface.htile_slice_size * layer_count;
3708 uint64_t offset = image->offset + image->htile_offset +
3709 image->surface.htile_slice_size * range->baseArrayLayer;
3710 struct radv_cmd_state *state = &cmd_buffer->state;
3711
3712 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3713 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3714
3715 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3716 size, clear_word);
3717
3718 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3719 }
3720
3721 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3722 struct radv_image *image,
3723 VkImageLayout src_layout,
3724 VkImageLayout dst_layout,
3725 unsigned src_queue_mask,
3726 unsigned dst_queue_mask,
3727 const VkImageSubresourceRange *range,
3728 VkImageAspectFlags pending_clears)
3729 {
3730 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3731 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3732 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3733 cmd_buffer->state.render_area.extent.width == image->info.width &&
3734 cmd_buffer->state.render_area.extent.height == image->info.height) {
3735 /* The clear will initialize htile. */
3736 return;
3737 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3738 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3739 /* TODO: merge with the clear if applicable */
3740 radv_initialize_htile(cmd_buffer, image, range, 0);
3741 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3742 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3743 radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
3744 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3745 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3746 VkImageSubresourceRange local_range = *range;
3747 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3748 local_range.baseMipLevel = 0;
3749 local_range.levelCount = 1;
3750
3751 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3752 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3753
3754 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3755
3756 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3757 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3758 }
3759 }
3760
3761 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3762 struct radv_image *image, uint32_t value)
3763 {
3764 struct radv_cmd_state *state = &cmd_buffer->state;
3765
3766 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3767 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3768
3769 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3770 image->offset + image->cmask.offset,
3771 image->cmask.size, value);
3772
3773 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3774 }
3775
3776 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3777 struct radv_image *image,
3778 VkImageLayout src_layout,
3779 VkImageLayout dst_layout,
3780 unsigned src_queue_mask,
3781 unsigned dst_queue_mask,
3782 const VkImageSubresourceRange *range)
3783 {
3784 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3785 if (image->fmask.size)
3786 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3787 else
3788 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3789 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3790 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3791 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3792 }
3793 }
3794
3795 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3796 struct radv_image *image, uint32_t value)
3797 {
3798 struct radv_cmd_state *state = &cmd_buffer->state;
3799
3800 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3801 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3802
3803 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3804 image->offset + image->dcc_offset,
3805 image->surface.dcc_size, value);
3806
3807 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3808 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3809 }
3810
3811 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3812 struct radv_image *image,
3813 VkImageLayout src_layout,
3814 VkImageLayout dst_layout,
3815 unsigned src_queue_mask,
3816 unsigned dst_queue_mask,
3817 const VkImageSubresourceRange *range)
3818 {
3819 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3820 radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
3821 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3822 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3823 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3824 }
3825 }
3826
3827 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3828 struct radv_image *image,
3829 VkImageLayout src_layout,
3830 VkImageLayout dst_layout,
3831 uint32_t src_family,
3832 uint32_t dst_family,
3833 const VkImageSubresourceRange *range,
3834 VkImageAspectFlags pending_clears)
3835 {
3836 if (image->exclusive && src_family != dst_family) {
3837 /* This is an acquire or a release operation and there will be
3838 * a corresponding release/acquire. Do the transition in the
3839 * most flexible queue. */
3840
3841 assert(src_family == cmd_buffer->queue_family_index ||
3842 dst_family == cmd_buffer->queue_family_index);
3843
3844 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3845 return;
3846
3847 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3848 (src_family == RADV_QUEUE_GENERAL ||
3849 dst_family == RADV_QUEUE_GENERAL))
3850 return;
3851 }
3852
3853 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3854 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3855
3856 if (image->surface.htile_size)
3857 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3858 dst_layout, src_queue_mask,
3859 dst_queue_mask, range,
3860 pending_clears);
3861
3862 if (image->cmask.size || image->fmask.size)
3863 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3864 dst_layout, src_queue_mask,
3865 dst_queue_mask, range);
3866
3867 if (image->surface.dcc_size)
3868 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3869 dst_layout, src_queue_mask,
3870 dst_queue_mask, range);
3871 }
3872
3873 void radv_CmdPipelineBarrier(
3874 VkCommandBuffer commandBuffer,
3875 VkPipelineStageFlags srcStageMask,
3876 VkPipelineStageFlags destStageMask,
3877 VkBool32 byRegion,
3878 uint32_t memoryBarrierCount,
3879 const VkMemoryBarrier* pMemoryBarriers,
3880 uint32_t bufferMemoryBarrierCount,
3881 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3882 uint32_t imageMemoryBarrierCount,
3883 const VkImageMemoryBarrier* pImageMemoryBarriers)
3884 {
3885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3886 enum radv_cmd_flush_bits src_flush_bits = 0;
3887 enum radv_cmd_flush_bits dst_flush_bits = 0;
3888
3889 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3890 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3891 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3892 NULL);
3893 }
3894
3895 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3896 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3897 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3898 NULL);
3899 }
3900
3901 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3902 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3903 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3904 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3905 image);
3906 }
3907
3908 radv_stage_flush(cmd_buffer, srcStageMask);
3909 cmd_buffer->state.flush_bits |= src_flush_bits;
3910
3911 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3912 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3913 radv_handle_image_transition(cmd_buffer, image,
3914 pImageMemoryBarriers[i].oldLayout,
3915 pImageMemoryBarriers[i].newLayout,
3916 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3917 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3918 &pImageMemoryBarriers[i].subresourceRange,
3919 0);
3920 }
3921
3922 cmd_buffer->state.flush_bits |= dst_flush_bits;
3923 }
3924
3925
3926 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3927 struct radv_event *event,
3928 VkPipelineStageFlags stageMask,
3929 unsigned value)
3930 {
3931 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3932 uint64_t va = radv_buffer_get_va(event->bo);
3933
3934 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3935
3936 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3937
3938 /* TODO: this is overkill. Probably should figure something out from
3939 * the stage mask. */
3940
3941 si_cs_emit_write_event_eop(cs,
3942 cmd_buffer->state.predicating,
3943 cmd_buffer->device->physical_device->rad_info.chip_class,
3944 false,
3945 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3946 1, va, 2, value);
3947
3948 assert(cmd_buffer->cs->cdw <= cdw_max);
3949 }
3950
3951 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3952 VkEvent _event,
3953 VkPipelineStageFlags stageMask)
3954 {
3955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3956 RADV_FROM_HANDLE(radv_event, event, _event);
3957
3958 write_event(cmd_buffer, event, stageMask, 1);
3959 }
3960
3961 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3962 VkEvent _event,
3963 VkPipelineStageFlags stageMask)
3964 {
3965 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3966 RADV_FROM_HANDLE(radv_event, event, _event);
3967
3968 write_event(cmd_buffer, event, stageMask, 0);
3969 }
3970
3971 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3972 uint32_t eventCount,
3973 const VkEvent* pEvents,
3974 VkPipelineStageFlags srcStageMask,
3975 VkPipelineStageFlags dstStageMask,
3976 uint32_t memoryBarrierCount,
3977 const VkMemoryBarrier* pMemoryBarriers,
3978 uint32_t bufferMemoryBarrierCount,
3979 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3980 uint32_t imageMemoryBarrierCount,
3981 const VkImageMemoryBarrier* pImageMemoryBarriers)
3982 {
3983 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3984 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3985
3986 for (unsigned i = 0; i < eventCount; ++i) {
3987 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3988 uint64_t va = radv_buffer_get_va(event->bo);
3989
3990 cmd_buffer->device->ws->cs_add_buffer(cs, event->bo, 8);
3991
3992 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3993
3994 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3995 assert(cmd_buffer->cs->cdw <= cdw_max);
3996 }
3997
3998
3999 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4000 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4001
4002 radv_handle_image_transition(cmd_buffer, image,
4003 pImageMemoryBarriers[i].oldLayout,
4004 pImageMemoryBarriers[i].newLayout,
4005 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4006 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4007 &pImageMemoryBarriers[i].subresourceRange,
4008 0);
4009 }
4010
4011 /* TODO: figure out how to do memory barriers without waiting */
4012 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4013 RADV_CMD_FLAG_INV_GLOBAL_L2 |
4014 RADV_CMD_FLAG_INV_VMEM_L1 |
4015 RADV_CMD_FLAG_INV_SMEM_L1;
4016 }