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radeonsi: correct WRITE_DATA.DST_SEL definitions
[mesa.git] / src / amd / vulkan / radv_cmd_buffer.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
31 #include "radv_cs.h"
32 #include "sid.h"
33 #include "gfx9d.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
37
38 #include "ac_debug.h"
39
40 enum {
41 RADV_PREFETCH_VBO_DESCRIPTORS = (1 << 0),
42 RADV_PREFETCH_VS = (1 << 1),
43 RADV_PREFETCH_TCS = (1 << 2),
44 RADV_PREFETCH_TES = (1 << 3),
45 RADV_PREFETCH_GS = (1 << 4),
46 RADV_PREFETCH_PS = (1 << 5),
47 RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS |
48 RADV_PREFETCH_TCS |
49 RADV_PREFETCH_TES |
50 RADV_PREFETCH_GS |
51 RADV_PREFETCH_PS)
52 };
53
54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
55 struct radv_image *image,
56 VkImageLayout src_layout,
57 VkImageLayout dst_layout,
58 uint32_t src_family,
59 uint32_t dst_family,
60 const VkImageSubresourceRange *range);
61
62 const struct radv_dynamic_state default_dynamic_state = {
63 .viewport = {
64 .count = 0,
65 },
66 .scissor = {
67 .count = 0,
68 },
69 .line_width = 1.0f,
70 .depth_bias = {
71 .bias = 0.0f,
72 .clamp = 0.0f,
73 .slope = 0.0f,
74 },
75 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
76 .depth_bounds = {
77 .min = 0.0f,
78 .max = 1.0f,
79 },
80 .stencil_compare_mask = {
81 .front = ~0u,
82 .back = ~0u,
83 },
84 .stencil_write_mask = {
85 .front = ~0u,
86 .back = ~0u,
87 },
88 .stencil_reference = {
89 .front = 0u,
90 .back = 0u,
91 },
92 };
93
94 static void
95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
96 const struct radv_dynamic_state *src)
97 {
98 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
99 uint32_t copy_mask = src->mask;
100 uint32_t dest_mask = 0;
101
102 /* Make sure to copy the number of viewports/scissors because they can
103 * only be specified at pipeline creation time.
104 */
105 dest->viewport.count = src->viewport.count;
106 dest->scissor.count = src->scissor.count;
107 dest->discard_rectangle.count = src->discard_rectangle.count;
108
109 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
110 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
111 src->viewport.count * sizeof(VkViewport))) {
112 typed_memcpy(dest->viewport.viewports,
113 src->viewport.viewports,
114 src->viewport.count);
115 dest_mask |= RADV_DYNAMIC_VIEWPORT;
116 }
117 }
118
119 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
120 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
121 src->scissor.count * sizeof(VkRect2D))) {
122 typed_memcpy(dest->scissor.scissors,
123 src->scissor.scissors, src->scissor.count);
124 dest_mask |= RADV_DYNAMIC_SCISSOR;
125 }
126 }
127
128 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
129 if (dest->line_width != src->line_width) {
130 dest->line_width = src->line_width;
131 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
132 }
133 }
134
135 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
136 if (memcmp(&dest->depth_bias, &src->depth_bias,
137 sizeof(src->depth_bias))) {
138 dest->depth_bias = src->depth_bias;
139 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
140 }
141 }
142
143 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
144 if (memcmp(&dest->blend_constants, &src->blend_constants,
145 sizeof(src->blend_constants))) {
146 typed_memcpy(dest->blend_constants,
147 src->blend_constants, 4);
148 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
149 }
150 }
151
152 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
153 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
154 sizeof(src->depth_bounds))) {
155 dest->depth_bounds = src->depth_bounds;
156 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
157 }
158 }
159
160 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
161 if (memcmp(&dest->stencil_compare_mask,
162 &src->stencil_compare_mask,
163 sizeof(src->stencil_compare_mask))) {
164 dest->stencil_compare_mask = src->stencil_compare_mask;
165 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
166 }
167 }
168
169 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
170 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
171 sizeof(src->stencil_write_mask))) {
172 dest->stencil_write_mask = src->stencil_write_mask;
173 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
174 }
175 }
176
177 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
178 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
179 sizeof(src->stencil_reference))) {
180 dest->stencil_reference = src->stencil_reference;
181 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
182 }
183 }
184
185 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
186 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
187 src->discard_rectangle.count * sizeof(VkRect2D))) {
188 typed_memcpy(dest->discard_rectangle.rectangles,
189 src->discard_rectangle.rectangles,
190 src->discard_rectangle.count);
191 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
192 }
193 }
194
195 cmd_buffer->state.dirty |= dest_mask;
196 }
197
198 static void
199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
200 struct radv_pipeline *pipeline)
201 {
202 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
203 struct radv_shader_info *info;
204
205 if (!pipeline->streamout_shader)
206 return;
207
208 info = &pipeline->streamout_shader->info.info;
209 for (int i = 0; i < MAX_SO_BUFFERS; i++)
210 so->stride_in_dw[i] = info->so.strides[i];
211
212 so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
213 }
214
215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
216 {
217 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
218 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
219 }
220
221 enum ring_type radv_queue_family_to_ring(int f) {
222 switch (f) {
223 case RADV_QUEUE_GENERAL:
224 return RING_GFX;
225 case RADV_QUEUE_COMPUTE:
226 return RING_COMPUTE;
227 case RADV_QUEUE_TRANSFER:
228 return RING_DMA;
229 default:
230 unreachable("Unknown queue family");
231 }
232 }
233
234 static VkResult radv_create_cmd_buffer(
235 struct radv_device * device,
236 struct radv_cmd_pool * pool,
237 VkCommandBufferLevel level,
238 VkCommandBuffer* pCommandBuffer)
239 {
240 struct radv_cmd_buffer *cmd_buffer;
241 unsigned ring;
242 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
243 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
244 if (cmd_buffer == NULL)
245 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
246
247 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 cmd_buffer->device = device;
249 cmd_buffer->pool = pool;
250 cmd_buffer->level = level;
251
252 if (pool) {
253 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
254 cmd_buffer->queue_family_index = pool->queue_family_index;
255
256 } else {
257 /* Init the pool_link so we can safely call list_del when we destroy
258 * the command buffer
259 */
260 list_inithead(&cmd_buffer->pool_link);
261 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
262 }
263
264 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
265
266 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
267 if (!cmd_buffer->cs) {
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
270 }
271
272 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
273
274 list_inithead(&cmd_buffer->upload.list);
275
276 return VK_SUCCESS;
277 }
278
279 static void
280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
281 {
282 list_del(&cmd_buffer->pool_link);
283
284 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
285 &cmd_buffer->upload.list, list) {
286 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
287 list_del(&up->list);
288 free(up);
289 }
290
291 if (cmd_buffer->upload.upload_bo)
292 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
293 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
294
295 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
296 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
297
298 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
299 }
300
301 static VkResult
302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
303 {
304
305 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
306
307 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
308 &cmd_buffer->upload.list, list) {
309 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
310 list_del(&up->list);
311 free(up);
312 }
313
314 cmd_buffer->push_constant_stages = 0;
315 cmd_buffer->scratch_size_needed = 0;
316 cmd_buffer->compute_scratch_size_needed = 0;
317 cmd_buffer->esgs_ring_size_needed = 0;
318 cmd_buffer->gsvs_ring_size_needed = 0;
319 cmd_buffer->tess_rings_needed = false;
320 cmd_buffer->sample_positions_needed = false;
321
322 if (cmd_buffer->upload.upload_bo)
323 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
324 cmd_buffer->upload.upload_bo);
325 cmd_buffer->upload.offset = 0;
326
327 cmd_buffer->record_result = VK_SUCCESS;
328
329 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
330 cmd_buffer->descriptors[i].dirty = 0;
331 cmd_buffer->descriptors[i].valid = 0;
332 cmd_buffer->descriptors[i].push_dirty = false;
333 }
334
335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
336 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
337 unsigned eop_bug_offset;
338 void *fence_ptr;
339
340 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
341 &cmd_buffer->gfx9_fence_offset,
342 &fence_ptr);
343 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
344
345 /* Allocate a buffer for the EOP bug on GFX9. */
346 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
347 &eop_bug_offset, &fence_ptr);
348 cmd_buffer->gfx9_eop_bug_va =
349 radv_buffer_get_va(cmd_buffer->upload.upload_bo);
350 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
351 }
352
353 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
354
355 return cmd_buffer->record_result;
356 }
357
358 static bool
359 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
360 uint64_t min_needed)
361 {
362 uint64_t new_size;
363 struct radeon_winsys_bo *bo;
364 struct radv_cmd_buffer_upload *upload;
365 struct radv_device *device = cmd_buffer->device;
366
367 new_size = MAX2(min_needed, 16 * 1024);
368 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
369
370 bo = device->ws->buffer_create(device->ws,
371 new_size, 4096,
372 RADEON_DOMAIN_GTT,
373 RADEON_FLAG_CPU_ACCESS|
374 RADEON_FLAG_NO_INTERPROCESS_SHARING |
375 RADEON_FLAG_32BIT);
376
377 if (!bo) {
378 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
379 return false;
380 }
381
382 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
383 if (cmd_buffer->upload.upload_bo) {
384 upload = malloc(sizeof(*upload));
385
386 if (!upload) {
387 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
388 device->ws->buffer_destroy(bo);
389 return false;
390 }
391
392 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
393 list_add(&upload->list, &cmd_buffer->upload.list);
394 }
395
396 cmd_buffer->upload.upload_bo = bo;
397 cmd_buffer->upload.size = new_size;
398 cmd_buffer->upload.offset = 0;
399 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
400
401 if (!cmd_buffer->upload.map) {
402 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
403 return false;
404 }
405
406 return true;
407 }
408
409 bool
410 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
411 unsigned size,
412 unsigned alignment,
413 unsigned *out_offset,
414 void **ptr)
415 {
416 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
417 if (offset + size > cmd_buffer->upload.size) {
418 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
419 return false;
420 offset = 0;
421 }
422
423 *out_offset = offset;
424 *ptr = cmd_buffer->upload.map + offset;
425
426 cmd_buffer->upload.offset = offset + size;
427 return true;
428 }
429
430 bool
431 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
432 unsigned size, unsigned alignment,
433 const void *data, unsigned *out_offset)
434 {
435 uint8_t *ptr;
436
437 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
438 out_offset, (void **)&ptr))
439 return false;
440
441 if (ptr)
442 memcpy(ptr, data, size);
443
444 return true;
445 }
446
447 static void
448 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
449 unsigned count, const uint32_t *data)
450 {
451 struct radeon_cmdbuf *cs = cmd_buffer->cs;
452
453 radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
454
455 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
456 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
457 S_370_WR_CONFIRM(1) |
458 S_370_ENGINE_SEL(V_370_ME));
459 radeon_emit(cs, va);
460 radeon_emit(cs, va >> 32);
461 radeon_emit_array(cs, data, count);
462 }
463
464 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
465 {
466 struct radv_device *device = cmd_buffer->device;
467 struct radeon_cmdbuf *cs = cmd_buffer->cs;
468 uint64_t va;
469
470 va = radv_buffer_get_va(device->trace_bo);
471 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
472 va += 4;
473
474 ++cmd_buffer->state.trace_id;
475 radv_emit_write_data_packet(cmd_buffer, va, 1,
476 &cmd_buffer->state.trace_id);
477
478 radeon_check_space(cmd_buffer->device->ws, cs, 2);
479
480 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
481 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
482 }
483
484 static void
485 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
486 enum radv_cmd_flush_bits flags)
487 {
488 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
489 uint32_t *ptr = NULL;
490 uint64_t va = 0;
491
492 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
493 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
494
495 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
496 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
497 cmd_buffer->gfx9_fence_offset;
498 ptr = &cmd_buffer->gfx9_fence_idx;
499 }
500
501 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
502
503 /* Force wait for graphics or compute engines to be idle. */
504 si_cs_emit_cache_flush(cmd_buffer->cs,
505 cmd_buffer->device->physical_device->rad_info.chip_class,
506 ptr, va,
507 radv_cmd_buffer_uses_mec(cmd_buffer),
508 flags, cmd_buffer->gfx9_eop_bug_va);
509 }
510
511 if (unlikely(cmd_buffer->device->trace_bo))
512 radv_cmd_buffer_trace_emit(cmd_buffer);
513 }
514
515 static void
516 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
517 struct radv_pipeline *pipeline, enum ring_type ring)
518 {
519 struct radv_device *device = cmd_buffer->device;
520 uint32_t data[2];
521 uint64_t va;
522
523 va = radv_buffer_get_va(device->trace_bo);
524
525 switch (ring) {
526 case RING_GFX:
527 va += 8;
528 break;
529 case RING_COMPUTE:
530 va += 16;
531 break;
532 default:
533 assert(!"invalid ring type");
534 }
535
536 data[0] = (uintptr_t)pipeline;
537 data[1] = (uintptr_t)pipeline >> 32;
538
539 radv_emit_write_data_packet(cmd_buffer, va, 2, data);
540 }
541
542 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
543 VkPipelineBindPoint bind_point,
544 struct radv_descriptor_set *set,
545 unsigned idx)
546 {
547 struct radv_descriptor_state *descriptors_state =
548 radv_get_descriptors_state(cmd_buffer, bind_point);
549
550 descriptors_state->sets[idx] = set;
551
552 descriptors_state->valid |= (1u << idx); /* active descriptors */
553 descriptors_state->dirty |= (1u << idx);
554 }
555
556 static void
557 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
558 VkPipelineBindPoint bind_point)
559 {
560 struct radv_descriptor_state *descriptors_state =
561 radv_get_descriptors_state(cmd_buffer, bind_point);
562 struct radv_device *device = cmd_buffer->device;
563 uint32_t data[MAX_SETS * 2] = {};
564 uint64_t va;
565 unsigned i;
566 va = radv_buffer_get_va(device->trace_bo) + 24;
567
568 for_each_bit(i, descriptors_state->valid) {
569 struct radv_descriptor_set *set = descriptors_state->sets[i];
570 data[i * 2] = (uintptr_t)set;
571 data[i * 2 + 1] = (uintptr_t)set >> 32;
572 }
573
574 radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
575 }
576
577 struct radv_userdata_info *
578 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
579 gl_shader_stage stage,
580 int idx)
581 {
582 struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
583 return &shader->info.user_sgprs_locs.shader_data[idx];
584 }
585
586 static void
587 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
588 struct radv_pipeline *pipeline,
589 gl_shader_stage stage,
590 int idx, uint64_t va)
591 {
592 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
593 uint32_t base_reg = pipeline->user_data_0[stage];
594 if (loc->sgpr_idx == -1)
595 return;
596
597 assert(loc->num_sgprs == 1);
598 assert(!loc->indirect);
599
600 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
601 base_reg + loc->sgpr_idx * 4, va, false);
602 }
603
604 static void
605 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
606 struct radv_pipeline *pipeline,
607 struct radv_descriptor_state *descriptors_state,
608 gl_shader_stage stage)
609 {
610 struct radv_device *device = cmd_buffer->device;
611 struct radeon_cmdbuf *cs = cmd_buffer->cs;
612 uint32_t sh_base = pipeline->user_data_0[stage];
613 struct radv_userdata_locations *locs =
614 &pipeline->shaders[stage]->info.user_sgprs_locs;
615 unsigned mask = locs->descriptor_sets_enabled;
616
617 mask &= descriptors_state->dirty & descriptors_state->valid;
618
619 while (mask) {
620 int start, count;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
625 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
626
627 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
628 for (int i = 0; i < count; i++) {
629 struct radv_descriptor_set *set =
630 descriptors_state->sets[start + i];
631
632 radv_emit_shader_pointer_body(device, cs, set->va, true);
633 }
634 }
635 }
636
637 static void
638 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
639 struct radv_pipeline *pipeline)
640 {
641 int num_samples = pipeline->graphics.ms.num_samples;
642 struct radv_multisample_state *ms = &pipeline->graphics.ms;
643 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
644
645 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
646 cmd_buffer->sample_positions_needed = true;
647
648 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
649 return;
650
651 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
652 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
653 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
654
655 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
656
657 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
658
659 /* GFX9: Flush DFSM when the AA mode changes. */
660 if (cmd_buffer->device->dfsm_allowed) {
661 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
662 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
663 }
664
665 cmd_buffer->state.context_roll_without_scissor_emitted = true;
666 }
667
668 static void
669 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
670 struct radv_shader_variant *shader)
671 {
672 uint64_t va;
673
674 if (!shader)
675 return;
676
677 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
678
679 si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
680 }
681
682 static void
683 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
684 struct radv_pipeline *pipeline,
685 bool vertex_stage_only)
686 {
687 struct radv_cmd_state *state = &cmd_buffer->state;
688 uint32_t mask = state->prefetch_L2_mask;
689
690 if (vertex_stage_only) {
691 /* Fast prefetch path for starting draws as soon as possible.
692 */
693 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
694 RADV_PREFETCH_VBO_DESCRIPTORS);
695 }
696
697 if (mask & RADV_PREFETCH_VS)
698 radv_emit_shader_prefetch(cmd_buffer,
699 pipeline->shaders[MESA_SHADER_VERTEX]);
700
701 if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
702 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
703
704 if (mask & RADV_PREFETCH_TCS)
705 radv_emit_shader_prefetch(cmd_buffer,
706 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
707
708 if (mask & RADV_PREFETCH_TES)
709 radv_emit_shader_prefetch(cmd_buffer,
710 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
711
712 if (mask & RADV_PREFETCH_GS) {
713 radv_emit_shader_prefetch(cmd_buffer,
714 pipeline->shaders[MESA_SHADER_GEOMETRY]);
715 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
716 }
717
718 if (mask & RADV_PREFETCH_PS)
719 radv_emit_shader_prefetch(cmd_buffer,
720 pipeline->shaders[MESA_SHADER_FRAGMENT]);
721
722 state->prefetch_L2_mask &= ~mask;
723 }
724
725 static void
726 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
727 {
728 if (!cmd_buffer->device->physical_device->rbplus_allowed)
729 return;
730
731 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
732 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
733 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
734
735 unsigned sx_ps_downconvert = 0;
736 unsigned sx_blend_opt_epsilon = 0;
737 unsigned sx_blend_opt_control = 0;
738
739 for (unsigned i = 0; i < subpass->color_count; ++i) {
740 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
741 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
742 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
743 continue;
744 }
745
746 int idx = subpass->color_attachments[i].attachment;
747 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
748
749 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
750 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
751 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
752 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
753
754 bool has_alpha, has_rgb;
755
756 /* Set if RGB and A are present. */
757 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
758
759 if (format == V_028C70_COLOR_8 ||
760 format == V_028C70_COLOR_16 ||
761 format == V_028C70_COLOR_32)
762 has_rgb = !has_alpha;
763 else
764 has_rgb = true;
765
766 /* Check the colormask and export format. */
767 if (!(colormask & 0x7))
768 has_rgb = false;
769 if (!(colormask & 0x8))
770 has_alpha = false;
771
772 if (spi_format == V_028714_SPI_SHADER_ZERO) {
773 has_rgb = false;
774 has_alpha = false;
775 }
776
777 /* Disable value checking for disabled channels. */
778 if (!has_rgb)
779 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
780 if (!has_alpha)
781 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
782
783 /* Enable down-conversion for 32bpp and smaller formats. */
784 switch (format) {
785 case V_028C70_COLOR_8:
786 case V_028C70_COLOR_8_8:
787 case V_028C70_COLOR_8_8_8_8:
788 /* For 1 and 2-channel formats, use the superset thereof. */
789 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
790 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
791 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
792 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
793 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
794 }
795 break;
796
797 case V_028C70_COLOR_5_6_5:
798 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
799 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
800 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
801 }
802 break;
803
804 case V_028C70_COLOR_1_5_5_5:
805 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
806 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
807 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
808 }
809 break;
810
811 case V_028C70_COLOR_4_4_4_4:
812 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
813 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
814 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
815 }
816 break;
817
818 case V_028C70_COLOR_32:
819 if (swap == V_028C70_SWAP_STD &&
820 spi_format == V_028714_SPI_SHADER_32_R)
821 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
822 else if (swap == V_028C70_SWAP_ALT_REV &&
823 spi_format == V_028714_SPI_SHADER_32_AR)
824 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
825 break;
826
827 case V_028C70_COLOR_16:
828 case V_028C70_COLOR_16_16:
829 /* For 1-channel formats, use the superset thereof. */
830 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
831 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
832 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
833 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
834 if (swap == V_028C70_SWAP_STD ||
835 swap == V_028C70_SWAP_STD_REV)
836 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
837 else
838 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
839 }
840 break;
841
842 case V_028C70_COLOR_10_11_11:
843 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
844 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
845 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
846 }
847 break;
848
849 case V_028C70_COLOR_2_10_10_10:
850 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
851 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
852 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
853 }
854 break;
855 }
856 }
857
858 for (unsigned i = subpass->color_count; i < 8; ++i) {
859 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
860 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
861 }
862 /* TODO: avoid redundantly setting context registers */
863 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
864 radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
865 radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
866 radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
867
868 cmd_buffer->state.context_roll_without_scissor_emitted = true;
869 }
870
871 static void
872 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
873 {
874 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
875
876 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
877 return;
878
879 radv_update_multisample_state(cmd_buffer, pipeline);
880
881 cmd_buffer->scratch_size_needed =
882 MAX2(cmd_buffer->scratch_size_needed,
883 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
884
885 if (!cmd_buffer->state.emitted_pipeline ||
886 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
887 pipeline->graphics.can_use_guardband)
888 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
889
890 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
891
892 if (!cmd_buffer->state.emitted_pipeline ||
893 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
894 cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
895 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
896 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
897 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
898 cmd_buffer->state.context_roll_without_scissor_emitted = true;
899 }
900
901 for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
902 if (!pipeline->shaders[i])
903 continue;
904
905 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
906 pipeline->shaders[i]->bo);
907 }
908
909 if (radv_pipeline_has_gs(pipeline))
910 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
911 pipeline->gs_copy_shader->bo);
912
913 if (unlikely(cmd_buffer->device->trace_bo))
914 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
915
916 cmd_buffer->state.emitted_pipeline = pipeline;
917
918 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
919 }
920
921 static void
922 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
923 {
924 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
925 cmd_buffer->state.dynamic.viewport.viewports);
926 }
927
928 static void
929 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
930 {
931 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
932
933 si_write_scissors(cmd_buffer->cs, 0, count,
934 cmd_buffer->state.dynamic.scissor.scissors,
935 cmd_buffer->state.dynamic.viewport.viewports,
936 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
937
938 cmd_buffer->state.context_roll_without_scissor_emitted = false;
939 }
940
941 static void
942 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
943 {
944 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
945 return;
946
947 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
948 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
949 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
950 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
951 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
952 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
953 S_028214_BR_Y(rect.offset.y + rect.extent.height));
954 }
955 }
956
957 static void
958 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
959 {
960 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
961
962 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
963 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
964 }
965
966 static void
967 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
968 {
969 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
970
971 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
972 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
973 }
974
975 static void
976 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
977 {
978 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
979
980 radeon_set_context_reg_seq(cmd_buffer->cs,
981 R_028430_DB_STENCILREFMASK, 2);
982 radeon_emit(cmd_buffer->cs,
983 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
984 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
985 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
986 S_028430_STENCILOPVAL(1));
987 radeon_emit(cmd_buffer->cs,
988 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
989 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
990 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
991 S_028434_STENCILOPVAL_BF(1));
992 }
993
994 static void
995 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
996 {
997 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
998
999 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1000 fui(d->depth_bounds.min));
1001 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1002 fui(d->depth_bounds.max));
1003 }
1004
1005 static void
1006 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1007 {
1008 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1009 unsigned slope = fui(d->depth_bias.slope * 16.0f);
1010 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1011
1012
1013 radeon_set_context_reg_seq(cmd_buffer->cs,
1014 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1015 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1016 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1017 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1018 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1019 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1020 }
1021
1022 static void
1023 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1024 int index,
1025 struct radv_attachment_info *att,
1026 struct radv_image *image,
1027 VkImageLayout layout)
1028 {
1029 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1030 struct radv_color_buffer_info *cb = &att->cb;
1031 uint32_t cb_color_info = cb->cb_color_info;
1032
1033 if (!radv_layout_dcc_compressed(image, layout,
1034 radv_image_queue_family_mask(image,
1035 cmd_buffer->queue_family_index,
1036 cmd_buffer->queue_family_index))) {
1037 cb_color_info &= C_028C70_DCC_ENABLE;
1038 }
1039
1040 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1041 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1042 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1043 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1044 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1045 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1046 radeon_emit(cmd_buffer->cs, cb_color_info);
1047 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1048 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1049 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1050 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1051 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1052 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1053
1054 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1055 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1056 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1057
1058 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1059 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1060 } else {
1061 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1062 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1063 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1064 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1065 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1066 radeon_emit(cmd_buffer->cs, cb_color_info);
1067 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1068 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1069 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1070 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1071 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1072 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1073
1074 if (is_vi) { /* DCC BASE */
1075 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1076 }
1077 }
1078
1079 if (radv_image_has_dcc(image)) {
1080 /* Drawing with DCC enabled also compresses colorbuffers. */
1081 radv_update_dcc_metadata(cmd_buffer, image, true);
1082 }
1083 }
1084
1085 static void
1086 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1087 struct radv_ds_buffer_info *ds,
1088 struct radv_image *image, VkImageLayout layout,
1089 bool requires_cond_exec)
1090 {
1091 uint32_t db_z_info = ds->db_z_info;
1092 uint32_t db_z_info_reg;
1093
1094 if (!radv_image_is_tc_compat_htile(image))
1095 return;
1096
1097 if (!radv_layout_has_htile(image, layout,
1098 radv_image_queue_family_mask(image,
1099 cmd_buffer->queue_family_index,
1100 cmd_buffer->queue_family_index))) {
1101 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1102 }
1103
1104 db_z_info &= C_028040_ZRANGE_PRECISION;
1105
1106 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1107 db_z_info_reg = R_028038_DB_Z_INFO;
1108 } else {
1109 db_z_info_reg = R_028040_DB_Z_INFO;
1110 }
1111
1112 /* When we don't know the last fast clear value we need to emit a
1113 * conditional packet that will eventually skip the following
1114 * SET_CONTEXT_REG packet.
1115 */
1116 if (requires_cond_exec) {
1117 uint64_t va = radv_buffer_get_va(image->bo);
1118 va += image->offset + image->tc_compat_zrange_offset;
1119
1120 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1121 radeon_emit(cmd_buffer->cs, va);
1122 radeon_emit(cmd_buffer->cs, va >> 32);
1123 radeon_emit(cmd_buffer->cs, 0);
1124 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1125 }
1126
1127 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1128 }
1129
1130 static void
1131 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1132 struct radv_ds_buffer_info *ds,
1133 struct radv_image *image,
1134 VkImageLayout layout)
1135 {
1136 uint32_t db_z_info = ds->db_z_info;
1137 uint32_t db_stencil_info = ds->db_stencil_info;
1138
1139 if (!radv_layout_has_htile(image, layout,
1140 radv_image_queue_family_mask(image,
1141 cmd_buffer->queue_family_index,
1142 cmd_buffer->queue_family_index))) {
1143 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1144 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1145 }
1146
1147 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1148 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1149
1150
1151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1152 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1153 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1154 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1155 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1156
1157 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1158 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
1159 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
1160 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
1161 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */
1162 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
1163 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1164 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
1165 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32)); /* DB_Z_WRITE_BASE_HI */
1166 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1167 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1168
1169 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1170 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1171 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1172 } else {
1173 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1174
1175 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1176 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1177 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
1178 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
1179 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
1180 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
1181 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
1182 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1183 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1184 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
1185
1186 }
1187
1188 /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1189 radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1190
1191 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1192 ds->pa_su_poly_offset_db_fmt_cntl);
1193 }
1194
1195 /**
1196 * Update the fast clear depth/stencil values if the image is bound as a
1197 * depth/stencil buffer.
1198 */
1199 static void
1200 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1201 struct radv_image *image,
1202 VkClearDepthStencilValue ds_clear_value,
1203 VkImageAspectFlags aspects)
1204 {
1205 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1206 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1207 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1208 struct radv_attachment_info *att;
1209 uint32_t att_idx;
1210
1211 if (!framebuffer || !subpass)
1212 return;
1213
1214 att_idx = subpass->depth_stencil_attachment.attachment;
1215 if (att_idx == VK_ATTACHMENT_UNUSED)
1216 return;
1217
1218 att = &framebuffer->attachments[att_idx];
1219 if (att->attachment->image != image)
1220 return;
1221
1222 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1223 radeon_emit(cs, ds_clear_value.stencil);
1224 radeon_emit(cs, fui(ds_clear_value.depth));
1225
1226 /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1227 * only needed when clearing Z to 0.0.
1228 */
1229 if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1230 ds_clear_value.depth == 0.0) {
1231 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1232
1233 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1234 layout, false);
1235 }
1236
1237 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1238 }
1239
1240 /**
1241 * Set the clear depth/stencil values to the image's metadata.
1242 */
1243 static void
1244 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1245 struct radv_image *image,
1246 VkClearDepthStencilValue ds_clear_value,
1247 VkImageAspectFlags aspects)
1248 {
1249 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1250 uint64_t va = radv_buffer_get_va(image->bo);
1251 unsigned reg_offset = 0, reg_count = 0;
1252
1253 va += image->offset + image->clear_value_offset;
1254
1255 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1256 ++reg_count;
1257 } else {
1258 ++reg_offset;
1259 va += 4;
1260 }
1261 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1262 ++reg_count;
1263
1264 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1265 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1266 S_370_WR_CONFIRM(1) |
1267 S_370_ENGINE_SEL(V_370_PFP));
1268 radeon_emit(cs, va);
1269 radeon_emit(cs, va >> 32);
1270 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1271 radeon_emit(cs, ds_clear_value.stencil);
1272 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1273 radeon_emit(cs, fui(ds_clear_value.depth));
1274 }
1275
1276 /**
1277 * Update the TC-compat metadata value for this image.
1278 */
1279 static void
1280 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1281 struct radv_image *image,
1282 uint32_t value)
1283 {
1284 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1285 uint64_t va = radv_buffer_get_va(image->bo);
1286 va += image->offset + image->tc_compat_zrange_offset;
1287
1288 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1289 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1290 S_370_WR_CONFIRM(1) |
1291 S_370_ENGINE_SEL(V_370_PFP));
1292 radeon_emit(cs, va);
1293 radeon_emit(cs, va >> 32);
1294 radeon_emit(cs, value);
1295 }
1296
1297 static void
1298 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1299 struct radv_image *image,
1300 VkClearDepthStencilValue ds_clear_value)
1301 {
1302 uint64_t va = radv_buffer_get_va(image->bo);
1303 va += image->offset + image->tc_compat_zrange_offset;
1304 uint32_t cond_val;
1305
1306 /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1307 * depth clear value is 0.0f.
1308 */
1309 cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1310
1311 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1312 }
1313
1314 /**
1315 * Update the clear depth/stencil values for this image.
1316 */
1317 void
1318 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1319 struct radv_image *image,
1320 VkClearDepthStencilValue ds_clear_value,
1321 VkImageAspectFlags aspects)
1322 {
1323 assert(radv_image_has_htile(image));
1324
1325 radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1326
1327 if (radv_image_is_tc_compat_htile(image) &&
1328 (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1329 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1330 ds_clear_value);
1331 }
1332
1333 radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1334 aspects);
1335 }
1336
1337 /**
1338 * Load the clear depth/stencil values from the image's metadata.
1339 */
1340 static void
1341 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1342 struct radv_image *image)
1343 {
1344 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1345 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1346 uint64_t va = radv_buffer_get_va(image->bo);
1347 unsigned reg_offset = 0, reg_count = 0;
1348
1349 va += image->offset + image->clear_value_offset;
1350
1351 if (!radv_image_has_htile(image))
1352 return;
1353
1354 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1355 ++reg_count;
1356 } else {
1357 ++reg_offset;
1358 va += 4;
1359 }
1360 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1361 ++reg_count;
1362
1363 uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1364
1365 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1366 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1367 radeon_emit(cs, va);
1368 radeon_emit(cs, va >> 32);
1369 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1370 radeon_emit(cs, reg_count);
1371 } else {
1372 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1373 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1374 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1375 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1376 radeon_emit(cs, va);
1377 radeon_emit(cs, va >> 32);
1378 radeon_emit(cs, reg >> 2);
1379 radeon_emit(cs, 0);
1380
1381 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1382 radeon_emit(cs, 0);
1383 }
1384 }
1385
1386 /*
1387 * With DCC some colors don't require CMASK elimination before being
1388 * used as a texture. This sets a predicate value to determine if the
1389 * cmask eliminate is required.
1390 */
1391 void
1392 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1393 struct radv_image *image, bool value)
1394 {
1395 uint64_t pred_val = value;
1396 uint64_t va = radv_buffer_get_va(image->bo);
1397 va += image->offset + image->fce_pred_offset;
1398
1399 assert(radv_image_has_dcc(image));
1400
1401 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1402 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1403 S_370_WR_CONFIRM(1) |
1404 S_370_ENGINE_SEL(V_370_PFP));
1405 radeon_emit(cmd_buffer->cs, va);
1406 radeon_emit(cmd_buffer->cs, va >> 32);
1407 radeon_emit(cmd_buffer->cs, pred_val);
1408 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1409 }
1410
1411 /**
1412 * Update the DCC predicate to reflect the compression state.
1413 */
1414 void
1415 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1416 struct radv_image *image, bool value)
1417 {
1418 uint64_t pred_val = value;
1419 uint64_t va = radv_buffer_get_va(image->bo);
1420 va += image->offset + image->dcc_pred_offset;
1421
1422 assert(radv_image_has_dcc(image));
1423
1424 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1425 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1426 S_370_WR_CONFIRM(1) |
1427 S_370_ENGINE_SEL(V_370_PFP));
1428 radeon_emit(cmd_buffer->cs, va);
1429 radeon_emit(cmd_buffer->cs, va >> 32);
1430 radeon_emit(cmd_buffer->cs, pred_val);
1431 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1432 }
1433
1434 /**
1435 * Update the fast clear color values if the image is bound as a color buffer.
1436 */
1437 static void
1438 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1439 struct radv_image *image,
1440 int cb_idx,
1441 uint32_t color_values[2])
1442 {
1443 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1444 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1445 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1446 struct radv_attachment_info *att;
1447 uint32_t att_idx;
1448
1449 if (!framebuffer || !subpass)
1450 return;
1451
1452 att_idx = subpass->color_attachments[cb_idx].attachment;
1453 if (att_idx == VK_ATTACHMENT_UNUSED)
1454 return;
1455
1456 att = &framebuffer->attachments[att_idx];
1457 if (att->attachment->image != image)
1458 return;
1459
1460 radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1461 radeon_emit(cs, color_values[0]);
1462 radeon_emit(cs, color_values[1]);
1463
1464 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1465 }
1466
1467 /**
1468 * Set the clear color values to the image's metadata.
1469 */
1470 static void
1471 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1472 struct radv_image *image,
1473 uint32_t color_values[2])
1474 {
1475 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1476 uint64_t va = radv_buffer_get_va(image->bo);
1477
1478 va += image->offset + image->clear_value_offset;
1479
1480 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1481
1482 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1483 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1484 S_370_WR_CONFIRM(1) |
1485 S_370_ENGINE_SEL(V_370_PFP));
1486 radeon_emit(cs, va);
1487 radeon_emit(cs, va >> 32);
1488 radeon_emit(cs, color_values[0]);
1489 radeon_emit(cs, color_values[1]);
1490 }
1491
1492 /**
1493 * Update the clear color values for this image.
1494 */
1495 void
1496 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1497 struct radv_image *image,
1498 int cb_idx,
1499 uint32_t color_values[2])
1500 {
1501 assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1502
1503 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1504
1505 radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1506 color_values);
1507 }
1508
1509 /**
1510 * Load the clear color values from the image's metadata.
1511 */
1512 static void
1513 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1514 struct radv_image *image,
1515 int cb_idx)
1516 {
1517 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1518 uint64_t va = radv_buffer_get_va(image->bo);
1519
1520 va += image->offset + image->clear_value_offset;
1521
1522 if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1523 return;
1524
1525 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1526
1527 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1528 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1529 radeon_emit(cs, va);
1530 radeon_emit(cs, va >> 32);
1531 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1532 radeon_emit(cs, 2);
1533 } else {
1534 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1535 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1536 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1537 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1538 COPY_DATA_COUNT_SEL);
1539 radeon_emit(cs, va);
1540 radeon_emit(cs, va >> 32);
1541 radeon_emit(cs, reg >> 2);
1542 radeon_emit(cs, 0);
1543
1544 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1545 radeon_emit(cs, 0);
1546 }
1547 }
1548
1549 static void
1550 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1551 {
1552 int i;
1553 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1554 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1555 unsigned num_bpp64_colorbufs = 0;
1556
1557 /* this may happen for inherited secondary recording */
1558 if (!framebuffer)
1559 return;
1560
1561 for (i = 0; i < 8; ++i) {
1562 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1563 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1564 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1565 continue;
1566 }
1567
1568 int idx = subpass->color_attachments[i].attachment;
1569 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1570 struct radv_image *image = att->attachment->image;
1571 VkImageLayout layout = subpass->color_attachments[i].layout;
1572
1573 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1574
1575 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1576 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1577
1578 radv_load_color_clear_metadata(cmd_buffer, image, i);
1579
1580 if (image->surface.bpe >= 8)
1581 num_bpp64_colorbufs++;
1582 }
1583
1584 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1585 int idx = subpass->depth_stencil_attachment.attachment;
1586 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1587 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1588 struct radv_image *image = att->attachment->image;
1589 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1590 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1591 cmd_buffer->queue_family_index,
1592 cmd_buffer->queue_family_index);
1593 /* We currently don't support writing decompressed HTILE */
1594 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1595 radv_layout_is_htile_compressed(image, layout, queue_mask));
1596
1597 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1598
1599 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1600 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1601 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1602 }
1603 radv_load_ds_clear_metadata(cmd_buffer, image);
1604 } else {
1605 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1606 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1607 else
1608 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1609
1610 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1611 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1612 }
1613 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1614 S_028208_BR_X(framebuffer->width) |
1615 S_028208_BR_Y(framebuffer->height));
1616
1617 if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1618 uint8_t watermark = 4; /* Default value for VI. */
1619
1620 /* For optimal DCC performance. */
1621 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1622 if (num_bpp64_colorbufs >= 5) {
1623 watermark = 8;
1624 } else {
1625 watermark = 6;
1626 }
1627 }
1628
1629 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1630 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1631 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1632 }
1633
1634 if (cmd_buffer->device->dfsm_allowed) {
1635 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1636 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1637 }
1638
1639 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1640 }
1641
1642 static void
1643 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1644 {
1645 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1646 struct radv_cmd_state *state = &cmd_buffer->state;
1647
1648 if (state->index_type != state->last_index_type) {
1649 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1650 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1651 2, state->index_type);
1652 } else {
1653 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1654 radeon_emit(cs, state->index_type);
1655 }
1656
1657 state->last_index_type = state->index_type;
1658 }
1659
1660 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1661 radeon_emit(cs, state->index_va);
1662 radeon_emit(cs, state->index_va >> 32);
1663
1664 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1665 radeon_emit(cs, state->max_index_count);
1666
1667 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1668 }
1669
1670 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1671 {
1672 bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1673 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1674 uint32_t pa_sc_mode_cntl_1 =
1675 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1676 uint32_t db_count_control;
1677
1678 if(!cmd_buffer->state.active_occlusion_queries) {
1679 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1680 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1681 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1682 has_perfect_queries) {
1683 /* Re-enable out-of-order rasterization if the
1684 * bound pipeline supports it and if it's has
1685 * been disabled before starting any perfect
1686 * occlusion queries.
1687 */
1688 radeon_set_context_reg(cmd_buffer->cs,
1689 R_028A4C_PA_SC_MODE_CNTL_1,
1690 pa_sc_mode_cntl_1);
1691 }
1692 }
1693 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1694 } else {
1695 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1696 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1697
1698 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1699 db_count_control =
1700 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1701 S_028004_SAMPLE_RATE(sample_rate) |
1702 S_028004_ZPASS_ENABLE(1) |
1703 S_028004_SLICE_EVEN_ENABLE(1) |
1704 S_028004_SLICE_ODD_ENABLE(1);
1705
1706 if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1707 pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1708 has_perfect_queries) {
1709 /* If the bound pipeline has enabled
1710 * out-of-order rasterization, we should
1711 * disable it before starting any perfect
1712 * occlusion queries.
1713 */
1714 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1715
1716 radeon_set_context_reg(cmd_buffer->cs,
1717 R_028A4C_PA_SC_MODE_CNTL_1,
1718 pa_sc_mode_cntl_1);
1719 }
1720 } else {
1721 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1722 S_028004_SAMPLE_RATE(sample_rate);
1723 }
1724 }
1725
1726 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1727
1728 cmd_buffer->state.context_roll_without_scissor_emitted = true;
1729 }
1730
1731 static void
1732 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1733 {
1734 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1735
1736 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1737 radv_emit_viewport(cmd_buffer);
1738
1739 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1740 !cmd_buffer->device->physical_device->has_scissor_bug)
1741 radv_emit_scissor(cmd_buffer);
1742
1743 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1744 radv_emit_line_width(cmd_buffer);
1745
1746 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1747 radv_emit_blend_constants(cmd_buffer);
1748
1749 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1750 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1751 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1752 radv_emit_stencil(cmd_buffer);
1753
1754 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1755 radv_emit_depth_bounds(cmd_buffer);
1756
1757 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1758 radv_emit_depth_bias(cmd_buffer);
1759
1760 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1761 radv_emit_discard_rectangle(cmd_buffer);
1762
1763 cmd_buffer->state.dirty &= ~states;
1764 }
1765
1766 static void
1767 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1768 VkPipelineBindPoint bind_point)
1769 {
1770 struct radv_descriptor_state *descriptors_state =
1771 radv_get_descriptors_state(cmd_buffer, bind_point);
1772 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1773 unsigned bo_offset;
1774
1775 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1776 set->mapped_ptr,
1777 &bo_offset))
1778 return;
1779
1780 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1781 set->va += bo_offset;
1782 }
1783
1784 static void
1785 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1786 VkPipelineBindPoint bind_point)
1787 {
1788 struct radv_descriptor_state *descriptors_state =
1789 radv_get_descriptors_state(cmd_buffer, bind_point);
1790 uint32_t size = MAX_SETS * 4;
1791 uint32_t offset;
1792 void *ptr;
1793
1794 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1795 256, &offset, &ptr))
1796 return;
1797
1798 for (unsigned i = 0; i < MAX_SETS; i++) {
1799 uint32_t *uptr = ((uint32_t *)ptr) + i;
1800 uint64_t set_va = 0;
1801 struct radv_descriptor_set *set = descriptors_state->sets[i];
1802 if (descriptors_state->valid & (1u << i))
1803 set_va = set->va;
1804 uptr[0] = set_va & 0xffffffff;
1805 }
1806
1807 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1808 va += offset;
1809
1810 if (cmd_buffer->state.pipeline) {
1811 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1812 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1813 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1814
1815 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1816 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1817 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1818
1819 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1820 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1821 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1822
1823 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1824 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1825 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1826
1827 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1828 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1829 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1830 }
1831
1832 if (cmd_buffer->state.compute_pipeline)
1833 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1834 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1835 }
1836
1837 static void
1838 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1839 VkShaderStageFlags stages)
1840 {
1841 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1842 VK_PIPELINE_BIND_POINT_COMPUTE :
1843 VK_PIPELINE_BIND_POINT_GRAPHICS;
1844 struct radv_descriptor_state *descriptors_state =
1845 radv_get_descriptors_state(cmd_buffer, bind_point);
1846 struct radv_cmd_state *state = &cmd_buffer->state;
1847 bool flush_indirect_descriptors;
1848
1849 if (!descriptors_state->dirty)
1850 return;
1851
1852 if (descriptors_state->push_dirty)
1853 radv_flush_push_descriptors(cmd_buffer, bind_point);
1854
1855 flush_indirect_descriptors =
1856 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1857 state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1858 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1859 state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1860
1861 if (flush_indirect_descriptors)
1862 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1863
1864 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1865 cmd_buffer->cs,
1866 MAX_SETS * MESA_SHADER_STAGES * 4);
1867
1868 if (cmd_buffer->state.pipeline) {
1869 radv_foreach_stage(stage, stages) {
1870 if (!cmd_buffer->state.pipeline->shaders[stage])
1871 continue;
1872
1873 radv_emit_descriptor_pointers(cmd_buffer,
1874 cmd_buffer->state.pipeline,
1875 descriptors_state, stage);
1876 }
1877 }
1878
1879 if (cmd_buffer->state.compute_pipeline &&
1880 (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1881 radv_emit_descriptor_pointers(cmd_buffer,
1882 cmd_buffer->state.compute_pipeline,
1883 descriptors_state,
1884 MESA_SHADER_COMPUTE);
1885 }
1886
1887 descriptors_state->dirty = 0;
1888 descriptors_state->push_dirty = false;
1889
1890 assert(cmd_buffer->cs->cdw <= cdw_max);
1891
1892 if (unlikely(cmd_buffer->device->trace_bo))
1893 radv_save_descriptors(cmd_buffer, bind_point);
1894 }
1895
1896 static void
1897 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1898 VkShaderStageFlags stages)
1899 {
1900 struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1901 ? cmd_buffer->state.compute_pipeline
1902 : cmd_buffer->state.pipeline;
1903 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1904 VK_PIPELINE_BIND_POINT_COMPUTE :
1905 VK_PIPELINE_BIND_POINT_GRAPHICS;
1906 struct radv_descriptor_state *descriptors_state =
1907 radv_get_descriptors_state(cmd_buffer, bind_point);
1908 struct radv_pipeline_layout *layout = pipeline->layout;
1909 struct radv_shader_variant *shader, *prev_shader;
1910 unsigned offset;
1911 void *ptr;
1912 uint64_t va;
1913
1914 stages &= cmd_buffer->push_constant_stages;
1915 if (!stages ||
1916 (!layout->push_constant_size && !layout->dynamic_offset_count))
1917 return;
1918
1919 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1920 16 * layout->dynamic_offset_count,
1921 256, &offset, &ptr))
1922 return;
1923
1924 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1925 memcpy((char*)ptr + layout->push_constant_size,
1926 descriptors_state->dynamic_buffers,
1927 16 * layout->dynamic_offset_count);
1928
1929 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1930 va += offset;
1931
1932 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1933 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1934
1935 prev_shader = NULL;
1936 radv_foreach_stage(stage, stages) {
1937 shader = radv_get_shader(pipeline, stage);
1938
1939 /* Avoid redundantly emitting the address for merged stages. */
1940 if (shader && shader != prev_shader) {
1941 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1942 AC_UD_PUSH_CONSTANTS, va);
1943
1944 prev_shader = shader;
1945 }
1946 }
1947
1948 cmd_buffer->push_constant_stages &= ~stages;
1949 assert(cmd_buffer->cs->cdw <= cdw_max);
1950 }
1951
1952 static void
1953 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1954 bool pipeline_is_dirty)
1955 {
1956 if ((pipeline_is_dirty ||
1957 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1958 cmd_buffer->state.pipeline->vertex_elements.count &&
1959 radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1960 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1961 unsigned vb_offset;
1962 void *vb_ptr;
1963 uint32_t i = 0;
1964 uint32_t count = velems->count;
1965 uint64_t va;
1966
1967 /* allocate some descriptor state for vertex buffers */
1968 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1969 &vb_offset, &vb_ptr))
1970 return;
1971
1972 for (i = 0; i < count; i++) {
1973 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1974 uint32_t offset;
1975 int vb = velems->binding[i];
1976 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1977 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1978
1979 va = radv_buffer_get_va(buffer->bo);
1980
1981 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1982 va += offset + buffer->offset;
1983 desc[0] = va;
1984 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1985 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1986 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1987 else
1988 desc[2] = buffer->size - offset;
1989 desc[3] = velems->rsrc_word3[i];
1990 }
1991
1992 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1993 va += vb_offset;
1994
1995 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1996 AC_UD_VS_VERTEX_BUFFERS, va);
1997
1998 cmd_buffer->state.vb_va = va;
1999 cmd_buffer->state.vb_size = count * 16;
2000 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2001 }
2002 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2003 }
2004
2005 static void
2006 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2007 {
2008 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2009 struct radv_userdata_info *loc;
2010 uint32_t base_reg;
2011
2012 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2013 if (!radv_get_shader(pipeline, stage))
2014 continue;
2015
2016 loc = radv_lookup_user_sgpr(pipeline, stage,
2017 AC_UD_STREAMOUT_BUFFERS);
2018 if (loc->sgpr_idx == -1)
2019 continue;
2020
2021 base_reg = pipeline->user_data_0[stage];
2022
2023 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2024 base_reg + loc->sgpr_idx * 4, va, false);
2025 }
2026
2027 if (pipeline->gs_copy_shader) {
2028 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2029 if (loc->sgpr_idx != -1) {
2030 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2031
2032 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2033 base_reg + loc->sgpr_idx * 4, va, false);
2034 }
2035 }
2036 }
2037
2038 static void
2039 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2040 {
2041 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2042 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2043 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2044 unsigned so_offset;
2045 void *so_ptr;
2046 uint64_t va;
2047
2048 /* Allocate some descriptor state for streamout buffers. */
2049 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2050 MAX_SO_BUFFERS * 16, 256,
2051 &so_offset, &so_ptr))
2052 return;
2053
2054 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2055 struct radv_buffer *buffer = sb[i].buffer;
2056 uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2057
2058 if (!(so->enabled_mask & (1 << i)))
2059 continue;
2060
2061 va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2062
2063 va += sb[i].offset;
2064
2065 /* Set the descriptor.
2066 *
2067 * On VI, the format must be non-INVALID, otherwise
2068 * the buffer will be considered not bound and store
2069 * instructions will be no-ops.
2070 */
2071 desc[0] = va;
2072 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2073 desc[2] = 0xffffffff;
2074 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2075 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2076 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2077 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2078 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2079 }
2080
2081 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2082 va += so_offset;
2083
2084 radv_emit_streamout_buffers(cmd_buffer, va);
2085 }
2086
2087 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2088 }
2089
2090 static void
2091 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2092 {
2093 radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2094 radv_flush_streamout_descriptors(cmd_buffer);
2095 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2096 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2097 }
2098
2099 struct radv_draw_info {
2100 /**
2101 * Number of vertices.
2102 */
2103 uint32_t count;
2104
2105 /**
2106 * Index of the first vertex.
2107 */
2108 int32_t vertex_offset;
2109
2110 /**
2111 * First instance id.
2112 */
2113 uint32_t first_instance;
2114
2115 /**
2116 * Number of instances.
2117 */
2118 uint32_t instance_count;
2119
2120 /**
2121 * First index (indexed draws only).
2122 */
2123 uint32_t first_index;
2124
2125 /**
2126 * Whether it's an indexed draw.
2127 */
2128 bool indexed;
2129
2130 /**
2131 * Indirect draw parameters resource.
2132 */
2133 struct radv_buffer *indirect;
2134 uint64_t indirect_offset;
2135 uint32_t stride;
2136
2137 /**
2138 * Draw count parameters resource.
2139 */
2140 struct radv_buffer *count_buffer;
2141 uint64_t count_buffer_offset;
2142
2143 /**
2144 * Stream output parameters resource.
2145 */
2146 struct radv_buffer *strmout_buffer;
2147 uint64_t strmout_buffer_offset;
2148 };
2149
2150 static void
2151 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2152 const struct radv_draw_info *draw_info)
2153 {
2154 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2155 struct radv_cmd_state *state = &cmd_buffer->state;
2156 struct radeon_cmdbuf *cs = cmd_buffer->cs;
2157 uint32_t ia_multi_vgt_param;
2158 int32_t primitive_reset_en;
2159
2160 /* Draw state. */
2161 ia_multi_vgt_param =
2162 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2163 draw_info->indirect,
2164 draw_info->indirect ? 0 : draw_info->count);
2165
2166 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2167 if (info->chip_class >= GFX9) {
2168 radeon_set_uconfig_reg_idx(cs,
2169 R_030960_IA_MULTI_VGT_PARAM,
2170 4, ia_multi_vgt_param);
2171 } else if (info->chip_class >= CIK) {
2172 radeon_set_context_reg_idx(cs,
2173 R_028AA8_IA_MULTI_VGT_PARAM,
2174 1, ia_multi_vgt_param);
2175 } else {
2176 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2177 ia_multi_vgt_param);
2178 }
2179 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2180 }
2181
2182 /* Primitive restart. */
2183 primitive_reset_en =
2184 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2185
2186 if (primitive_reset_en != state->last_primitive_reset_en) {
2187 state->last_primitive_reset_en = primitive_reset_en;
2188 if (info->chip_class >= GFX9) {
2189 radeon_set_uconfig_reg(cs,
2190 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2191 primitive_reset_en);
2192 } else {
2193 radeon_set_context_reg(cs,
2194 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2195 primitive_reset_en);
2196 }
2197 }
2198
2199 if (primitive_reset_en) {
2200 uint32_t primitive_reset_index =
2201 state->index_type ? 0xffffffffu : 0xffffu;
2202
2203 if (primitive_reset_index != state->last_primitive_reset_index) {
2204 radeon_set_context_reg(cs,
2205 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2206 primitive_reset_index);
2207 state->last_primitive_reset_index = primitive_reset_index;
2208 }
2209 }
2210
2211 if (draw_info->strmout_buffer) {
2212 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2213
2214 va += draw_info->strmout_buffer->offset +
2215 draw_info->strmout_buffer_offset;
2216
2217 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2218 draw_info->stride);
2219
2220 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2221 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2222 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2223 COPY_DATA_WR_CONFIRM);
2224 radeon_emit(cs, va);
2225 radeon_emit(cs, va >> 32);
2226 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2227 radeon_emit(cs, 0); /* unused */
2228
2229 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2230 }
2231 }
2232
2233 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2234 VkPipelineStageFlags src_stage_mask)
2235 {
2236 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2237 VK_PIPELINE_STAGE_TRANSFER_BIT |
2238 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2239 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2240 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2241 }
2242
2243 if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2244 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2245 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2246 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2247 VK_PIPELINE_STAGE_TRANSFER_BIT |
2248 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2249 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2250 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2251 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2252 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2253 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2254 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2255 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2256 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2257 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2258 VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2259 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2260 }
2261 }
2262
2263 static enum radv_cmd_flush_bits
2264 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2265 VkAccessFlags src_flags,
2266 struct radv_image *image)
2267 {
2268 bool flush_CB_meta = true, flush_DB_meta = true;
2269 enum radv_cmd_flush_bits flush_bits = 0;
2270 uint32_t b;
2271
2272 if (image) {
2273 if (!radv_image_has_CB_metadata(image))
2274 flush_CB_meta = false;
2275 if (!radv_image_has_htile(image))
2276 flush_DB_meta = false;
2277 }
2278
2279 for_each_bit(b, src_flags) {
2280 switch ((VkAccessFlagBits)(1 << b)) {
2281 case VK_ACCESS_SHADER_WRITE_BIT:
2282 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2283 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2284 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2285 break;
2286 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2287 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2288 if (flush_CB_meta)
2289 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2290 break;
2291 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2292 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2293 if (flush_DB_meta)
2294 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2295 break;
2296 case VK_ACCESS_TRANSFER_WRITE_BIT:
2297 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2298 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2299 RADV_CMD_FLAG_INV_GLOBAL_L2;
2300
2301 if (flush_CB_meta)
2302 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2303 if (flush_DB_meta)
2304 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2305 break;
2306 default:
2307 break;
2308 }
2309 }
2310 return flush_bits;
2311 }
2312
2313 static enum radv_cmd_flush_bits
2314 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2315 VkAccessFlags dst_flags,
2316 struct radv_image *image)
2317 {
2318 bool flush_CB_meta = true, flush_DB_meta = true;
2319 enum radv_cmd_flush_bits flush_bits = 0;
2320 bool flush_CB = true, flush_DB = true;
2321 bool image_is_coherent = false;
2322 uint32_t b;
2323
2324 if (image) {
2325 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2326 flush_CB = false;
2327 flush_DB = false;
2328 }
2329
2330 if (!radv_image_has_CB_metadata(image))
2331 flush_CB_meta = false;
2332 if (!radv_image_has_htile(image))
2333 flush_DB_meta = false;
2334
2335 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2336 if (image->info.samples == 1 &&
2337 (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2338 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2339 !vk_format_is_stencil(image->vk_format)) {
2340 /* Single-sample color and single-sample depth
2341 * (not stencil) are coherent with shaders on
2342 * GFX9.
2343 */
2344 image_is_coherent = true;
2345 }
2346 }
2347 }
2348
2349 for_each_bit(b, dst_flags) {
2350 switch ((VkAccessFlagBits)(1 << b)) {
2351 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2352 case VK_ACCESS_INDEX_READ_BIT:
2353 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2354 break;
2355 case VK_ACCESS_UNIFORM_READ_BIT:
2356 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2357 break;
2358 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2359 case VK_ACCESS_TRANSFER_READ_BIT:
2360 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2361 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2362 RADV_CMD_FLAG_INV_GLOBAL_L2;
2363 break;
2364 case VK_ACCESS_SHADER_READ_BIT:
2365 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2366
2367 if (!image_is_coherent)
2368 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2369 break;
2370 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2371 if (flush_CB)
2372 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2373 if (flush_CB_meta)
2374 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2375 break;
2376 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2377 if (flush_DB)
2378 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2379 if (flush_DB_meta)
2380 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2381 break;
2382 default:
2383 break;
2384 }
2385 }
2386 return flush_bits;
2387 }
2388
2389 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2390 const struct radv_subpass_barrier *barrier)
2391 {
2392 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2393 NULL);
2394 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2395 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2396 NULL);
2397 }
2398
2399 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2400 struct radv_subpass_attachment att)
2401 {
2402 unsigned idx = att.attachment;
2403 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2404 VkImageSubresourceRange range;
2405 range.aspectMask = 0;
2406 range.baseMipLevel = view->base_mip;
2407 range.levelCount = 1;
2408 range.baseArrayLayer = view->base_layer;
2409 range.layerCount = cmd_buffer->state.framebuffer->layers;
2410
2411 if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2412 /* If the current subpass uses multiview, the driver might have
2413 * performed a fast color/depth clear to the whole image
2414 * (including all layers). To make sure the driver will
2415 * decompress the image correctly (if needed), we have to
2416 * account for the "real" number of layers. If the view mask is
2417 * sparse, this will decompress more layers than needed.
2418 */
2419 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2420 }
2421
2422 radv_handle_image_transition(cmd_buffer,
2423 view->image,
2424 cmd_buffer->state.attachments[idx].current_layout,
2425 att.layout, 0, 0, &range);
2426
2427 cmd_buffer->state.attachments[idx].current_layout = att.layout;
2428
2429
2430 }
2431
2432 void
2433 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2434 const struct radv_subpass *subpass, bool transitions)
2435 {
2436 if (transitions) {
2437 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2438
2439 for (unsigned i = 0; i < subpass->color_count; ++i) {
2440 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2441 radv_handle_subpass_image_transition(cmd_buffer,
2442 subpass->color_attachments[i]);
2443 }
2444
2445 for (unsigned i = 0; i < subpass->input_count; ++i) {
2446 radv_handle_subpass_image_transition(cmd_buffer,
2447 subpass->input_attachments[i]);
2448 }
2449
2450 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2451 radv_handle_subpass_image_transition(cmd_buffer,
2452 subpass->depth_stencil_attachment);
2453 }
2454 }
2455
2456 cmd_buffer->state.subpass = subpass;
2457
2458 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2459 }
2460
2461 static VkResult
2462 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2463 struct radv_render_pass *pass,
2464 const VkRenderPassBeginInfo *info)
2465 {
2466 struct radv_cmd_state *state = &cmd_buffer->state;
2467
2468 if (pass->attachment_count == 0) {
2469 state->attachments = NULL;
2470 return VK_SUCCESS;
2471 }
2472
2473 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2474 pass->attachment_count *
2475 sizeof(state->attachments[0]),
2476 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2477 if (state->attachments == NULL) {
2478 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2479 return cmd_buffer->record_result;
2480 }
2481
2482 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2483 struct radv_render_pass_attachment *att = &pass->attachments[i];
2484 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2485 VkImageAspectFlags clear_aspects = 0;
2486
2487 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2488 /* color attachment */
2489 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2490 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2491 }
2492 } else {
2493 /* depthstencil attachment */
2494 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2495 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2496 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2497 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2498 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2499 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2500 }
2501 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2502 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2503 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2504 }
2505 }
2506
2507 state->attachments[i].pending_clear_aspects = clear_aspects;
2508 state->attachments[i].cleared_views = 0;
2509 if (clear_aspects && info) {
2510 assert(info->clearValueCount > i);
2511 state->attachments[i].clear_value = info->pClearValues[i];
2512 }
2513
2514 state->attachments[i].current_layout = att->initial_layout;
2515 }
2516
2517 return VK_SUCCESS;
2518 }
2519
2520 VkResult radv_AllocateCommandBuffers(
2521 VkDevice _device,
2522 const VkCommandBufferAllocateInfo *pAllocateInfo,
2523 VkCommandBuffer *pCommandBuffers)
2524 {
2525 RADV_FROM_HANDLE(radv_device, device, _device);
2526 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2527
2528 VkResult result = VK_SUCCESS;
2529 uint32_t i;
2530
2531 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2532
2533 if (!list_empty(&pool->free_cmd_buffers)) {
2534 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2535
2536 list_del(&cmd_buffer->pool_link);
2537 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2538
2539 result = radv_reset_cmd_buffer(cmd_buffer);
2540 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2541 cmd_buffer->level = pAllocateInfo->level;
2542
2543 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2544 } else {
2545 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2546 &pCommandBuffers[i]);
2547 }
2548 if (result != VK_SUCCESS)
2549 break;
2550 }
2551
2552 if (result != VK_SUCCESS) {
2553 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2554 i, pCommandBuffers);
2555
2556 /* From the Vulkan 1.0.66 spec:
2557 *
2558 * "vkAllocateCommandBuffers can be used to create multiple
2559 * command buffers. If the creation of any of those command
2560 * buffers fails, the implementation must destroy all
2561 * successfully created command buffer objects from this
2562 * command, set all entries of the pCommandBuffers array to
2563 * NULL and return the error."
2564 */
2565 memset(pCommandBuffers, 0,
2566 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2567 }
2568
2569 return result;
2570 }
2571
2572 void radv_FreeCommandBuffers(
2573 VkDevice device,
2574 VkCommandPool commandPool,
2575 uint32_t commandBufferCount,
2576 const VkCommandBuffer *pCommandBuffers)
2577 {
2578 for (uint32_t i = 0; i < commandBufferCount; i++) {
2579 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2580
2581 if (cmd_buffer) {
2582 if (cmd_buffer->pool) {
2583 list_del(&cmd_buffer->pool_link);
2584 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2585 } else
2586 radv_cmd_buffer_destroy(cmd_buffer);
2587
2588 }
2589 }
2590 }
2591
2592 VkResult radv_ResetCommandBuffer(
2593 VkCommandBuffer commandBuffer,
2594 VkCommandBufferResetFlags flags)
2595 {
2596 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2597 return radv_reset_cmd_buffer(cmd_buffer);
2598 }
2599
2600 VkResult radv_BeginCommandBuffer(
2601 VkCommandBuffer commandBuffer,
2602 const VkCommandBufferBeginInfo *pBeginInfo)
2603 {
2604 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2605 VkResult result = VK_SUCCESS;
2606
2607 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2608 /* If the command buffer has already been resetted with
2609 * vkResetCommandBuffer, no need to do it again.
2610 */
2611 result = radv_reset_cmd_buffer(cmd_buffer);
2612 if (result != VK_SUCCESS)
2613 return result;
2614 }
2615
2616 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2617 cmd_buffer->state.last_primitive_reset_en = -1;
2618 cmd_buffer->state.last_index_type = -1;
2619 cmd_buffer->state.last_num_instances = -1;
2620 cmd_buffer->state.last_vertex_offset = -1;
2621 cmd_buffer->state.last_first_instance = -1;
2622 cmd_buffer->state.predication_type = -1;
2623 cmd_buffer->usage_flags = pBeginInfo->flags;
2624
2625 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2626 (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2627 assert(pBeginInfo->pInheritanceInfo);
2628 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2629 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2630
2631 struct radv_subpass *subpass =
2632 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2633
2634 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2635 if (result != VK_SUCCESS)
2636 return result;
2637
2638 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2639 }
2640
2641 if (unlikely(cmd_buffer->device->trace_bo)) {
2642 struct radv_device *device = cmd_buffer->device;
2643
2644 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2645 device->trace_bo);
2646
2647 radv_cmd_buffer_trace_emit(cmd_buffer);
2648 }
2649
2650 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2651
2652 return result;
2653 }
2654
2655 void radv_CmdBindVertexBuffers(
2656 VkCommandBuffer commandBuffer,
2657 uint32_t firstBinding,
2658 uint32_t bindingCount,
2659 const VkBuffer* pBuffers,
2660 const VkDeviceSize* pOffsets)
2661 {
2662 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2663 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2664 bool changed = false;
2665
2666 /* We have to defer setting up vertex buffer since we need the buffer
2667 * stride from the pipeline. */
2668
2669 assert(firstBinding + bindingCount <= MAX_VBS);
2670 for (uint32_t i = 0; i < bindingCount; i++) {
2671 uint32_t idx = firstBinding + i;
2672
2673 if (!changed &&
2674 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2675 vb[idx].offset != pOffsets[i])) {
2676 changed = true;
2677 }
2678
2679 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2680 vb[idx].offset = pOffsets[i];
2681
2682 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2683 vb[idx].buffer->bo);
2684 }
2685
2686 if (!changed) {
2687 /* No state changes. */
2688 return;
2689 }
2690
2691 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2692 }
2693
2694 void radv_CmdBindIndexBuffer(
2695 VkCommandBuffer commandBuffer,
2696 VkBuffer buffer,
2697 VkDeviceSize offset,
2698 VkIndexType indexType)
2699 {
2700 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2701 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2702
2703 if (cmd_buffer->state.index_buffer == index_buffer &&
2704 cmd_buffer->state.index_offset == offset &&
2705 cmd_buffer->state.index_type == indexType) {
2706 /* No state changes. */
2707 return;
2708 }
2709
2710 cmd_buffer->state.index_buffer = index_buffer;
2711 cmd_buffer->state.index_offset = offset;
2712 cmd_buffer->state.index_type = indexType; /* vk matches hw */
2713 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2714 cmd_buffer->state.index_va += index_buffer->offset + offset;
2715
2716 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2717 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2718 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2719 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2720 }
2721
2722
2723 static void
2724 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2725 VkPipelineBindPoint bind_point,
2726 struct radv_descriptor_set *set, unsigned idx)
2727 {
2728 struct radeon_winsys *ws = cmd_buffer->device->ws;
2729
2730 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2731
2732 assert(set);
2733 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2734
2735 if (!cmd_buffer->device->use_global_bo_list) {
2736 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2737 if (set->descriptors[j])
2738 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2739 }
2740
2741 if(set->bo)
2742 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2743 }
2744
2745 void radv_CmdBindDescriptorSets(
2746 VkCommandBuffer commandBuffer,
2747 VkPipelineBindPoint pipelineBindPoint,
2748 VkPipelineLayout _layout,
2749 uint32_t firstSet,
2750 uint32_t descriptorSetCount,
2751 const VkDescriptorSet* pDescriptorSets,
2752 uint32_t dynamicOffsetCount,
2753 const uint32_t* pDynamicOffsets)
2754 {
2755 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2756 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2757 unsigned dyn_idx = 0;
2758
2759 const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2760 struct radv_descriptor_state *descriptors_state =
2761 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2762
2763 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2764 unsigned idx = i + firstSet;
2765 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2766 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2767
2768 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2769 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2770 uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2771 assert(dyn_idx < dynamicOffsetCount);
2772
2773 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2774 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2775 dst[0] = va;
2776 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2777 dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2778 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2779 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2780 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2781 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2782 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2783 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2784 cmd_buffer->push_constant_stages |=
2785 set->layout->dynamic_shader_stages;
2786 }
2787 }
2788 }
2789
2790 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2791 struct radv_descriptor_set *set,
2792 struct radv_descriptor_set_layout *layout,
2793 VkPipelineBindPoint bind_point)
2794 {
2795 struct radv_descriptor_state *descriptors_state =
2796 radv_get_descriptors_state(cmd_buffer, bind_point);
2797 set->size = layout->size;
2798 set->layout = layout;
2799
2800 if (descriptors_state->push_set.capacity < set->size) {
2801 size_t new_size = MAX2(set->size, 1024);
2802 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2803 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2804
2805 free(set->mapped_ptr);
2806 set->mapped_ptr = malloc(new_size);
2807
2808 if (!set->mapped_ptr) {
2809 descriptors_state->push_set.capacity = 0;
2810 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2811 return false;
2812 }
2813
2814 descriptors_state->push_set.capacity = new_size;
2815 }
2816
2817 return true;
2818 }
2819
2820 void radv_meta_push_descriptor_set(
2821 struct radv_cmd_buffer* cmd_buffer,
2822 VkPipelineBindPoint pipelineBindPoint,
2823 VkPipelineLayout _layout,
2824 uint32_t set,
2825 uint32_t descriptorWriteCount,
2826 const VkWriteDescriptorSet* pDescriptorWrites)
2827 {
2828 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2829 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2830 unsigned bo_offset;
2831
2832 assert(set == 0);
2833 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2834
2835 push_set->size = layout->set[set].layout->size;
2836 push_set->layout = layout->set[set].layout;
2837
2838 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2839 &bo_offset,
2840 (void**) &push_set->mapped_ptr))
2841 return;
2842
2843 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2844 push_set->va += bo_offset;
2845
2846 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2847 radv_descriptor_set_to_handle(push_set),
2848 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2849
2850 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2851 }
2852
2853 void radv_CmdPushDescriptorSetKHR(
2854 VkCommandBuffer commandBuffer,
2855 VkPipelineBindPoint pipelineBindPoint,
2856 VkPipelineLayout _layout,
2857 uint32_t set,
2858 uint32_t descriptorWriteCount,
2859 const VkWriteDescriptorSet* pDescriptorWrites)
2860 {
2861 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2862 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2863 struct radv_descriptor_state *descriptors_state =
2864 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2865 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2866
2867 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2868
2869 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2870 layout->set[set].layout,
2871 pipelineBindPoint))
2872 return;
2873
2874 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2875 radv_descriptor_set_to_handle(push_set),
2876 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2877
2878 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2879 descriptors_state->push_dirty = true;
2880 }
2881
2882 void radv_CmdPushDescriptorSetWithTemplateKHR(
2883 VkCommandBuffer commandBuffer,
2884 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
2885 VkPipelineLayout _layout,
2886 uint32_t set,
2887 const void* pData)
2888 {
2889 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2890 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2891 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2892 struct radv_descriptor_state *descriptors_state =
2893 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2894 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2895
2896 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2897
2898 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2899 layout->set[set].layout,
2900 templ->bind_point))
2901 return;
2902
2903 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2904 descriptorUpdateTemplate, pData);
2905
2906 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2907 descriptors_state->push_dirty = true;
2908 }
2909
2910 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2911 VkPipelineLayout layout,
2912 VkShaderStageFlags stageFlags,
2913 uint32_t offset,
2914 uint32_t size,
2915 const void* pValues)
2916 {
2917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2918 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2919 cmd_buffer->push_constant_stages |= stageFlags;
2920 }
2921
2922 VkResult radv_EndCommandBuffer(
2923 VkCommandBuffer commandBuffer)
2924 {
2925 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2926
2927 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2928 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2929 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2930 si_emit_cache_flush(cmd_buffer);
2931 }
2932
2933 /* Make sure CP DMA is idle at the end of IBs because the kernel
2934 * doesn't wait for it.
2935 */
2936 si_cp_dma_wait_for_idle(cmd_buffer);
2937
2938 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2939
2940 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2941 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2942
2943 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2944
2945 return cmd_buffer->record_result;
2946 }
2947
2948 static void
2949 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2950 {
2951 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2952
2953 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2954 return;
2955
2956 assert(!pipeline->ctx_cs.cdw);
2957
2958 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2959
2960 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2961 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2962
2963 cmd_buffer->compute_scratch_size_needed =
2964 MAX2(cmd_buffer->compute_scratch_size_needed,
2965 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2966
2967 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2968 pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2969
2970 if (unlikely(cmd_buffer->device->trace_bo))
2971 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2972 }
2973
2974 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2975 VkPipelineBindPoint bind_point)
2976 {
2977 struct radv_descriptor_state *descriptors_state =
2978 radv_get_descriptors_state(cmd_buffer, bind_point);
2979
2980 descriptors_state->dirty |= descriptors_state->valid;
2981 }
2982
2983 void radv_CmdBindPipeline(
2984 VkCommandBuffer commandBuffer,
2985 VkPipelineBindPoint pipelineBindPoint,
2986 VkPipeline _pipeline)
2987 {
2988 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2989 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2990
2991 switch (pipelineBindPoint) {
2992 case VK_PIPELINE_BIND_POINT_COMPUTE:
2993 if (cmd_buffer->state.compute_pipeline == pipeline)
2994 return;
2995 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2996
2997 cmd_buffer->state.compute_pipeline = pipeline;
2998 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2999 break;
3000 case VK_PIPELINE_BIND_POINT_GRAPHICS:
3001 if (cmd_buffer->state.pipeline == pipeline)
3002 return;
3003 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3004
3005 cmd_buffer->state.pipeline = pipeline;
3006 if (!pipeline)
3007 break;
3008
3009 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3010 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3011
3012 /* the new vertex shader might not have the same user regs */
3013 cmd_buffer->state.last_first_instance = -1;
3014 cmd_buffer->state.last_vertex_offset = -1;
3015
3016 /* Prefetch all pipeline shaders at first draw time. */
3017 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3018
3019 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3020 radv_bind_streamout_state(cmd_buffer, pipeline);
3021
3022 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3023 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3024 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3025 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3026
3027 if (radv_pipeline_has_tess(pipeline))
3028 cmd_buffer->tess_rings_needed = true;
3029 break;
3030 default:
3031 assert(!"invalid bind point");
3032 break;
3033 }
3034 }
3035
3036 void radv_CmdSetViewport(
3037 VkCommandBuffer commandBuffer,
3038 uint32_t firstViewport,
3039 uint32_t viewportCount,
3040 const VkViewport* pViewports)
3041 {
3042 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3043 struct radv_cmd_state *state = &cmd_buffer->state;
3044 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3045
3046 assert(firstViewport < MAX_VIEWPORTS);
3047 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3048
3049 if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3050 pViewports, viewportCount * sizeof(*pViewports))) {
3051 return;
3052 }
3053
3054 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3055 viewportCount * sizeof(*pViewports));
3056
3057 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3058 }
3059
3060 void radv_CmdSetScissor(
3061 VkCommandBuffer commandBuffer,
3062 uint32_t firstScissor,
3063 uint32_t scissorCount,
3064 const VkRect2D* pScissors)
3065 {
3066 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3067 struct radv_cmd_state *state = &cmd_buffer->state;
3068 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3069
3070 assert(firstScissor < MAX_SCISSORS);
3071 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3072
3073 if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3074 scissorCount * sizeof(*pScissors))) {
3075 return;
3076 }
3077
3078 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3079 scissorCount * sizeof(*pScissors));
3080
3081 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3082 }
3083
3084 void radv_CmdSetLineWidth(
3085 VkCommandBuffer commandBuffer,
3086 float lineWidth)
3087 {
3088 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3089
3090 if (cmd_buffer->state.dynamic.line_width == lineWidth)
3091 return;
3092
3093 cmd_buffer->state.dynamic.line_width = lineWidth;
3094 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3095 }
3096
3097 void radv_CmdSetDepthBias(
3098 VkCommandBuffer commandBuffer,
3099 float depthBiasConstantFactor,
3100 float depthBiasClamp,
3101 float depthBiasSlopeFactor)
3102 {
3103 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3104 struct radv_cmd_state *state = &cmd_buffer->state;
3105
3106 if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3107 state->dynamic.depth_bias.clamp == depthBiasClamp &&
3108 state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3109 return;
3110 }
3111
3112 state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3113 state->dynamic.depth_bias.clamp = depthBiasClamp;
3114 state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3115
3116 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3117 }
3118
3119 void radv_CmdSetBlendConstants(
3120 VkCommandBuffer commandBuffer,
3121 const float blendConstants[4])
3122 {
3123 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3124 struct radv_cmd_state *state = &cmd_buffer->state;
3125
3126 if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3127 return;
3128
3129 memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3130
3131 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3132 }
3133
3134 void radv_CmdSetDepthBounds(
3135 VkCommandBuffer commandBuffer,
3136 float minDepthBounds,
3137 float maxDepthBounds)
3138 {
3139 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3140 struct radv_cmd_state *state = &cmd_buffer->state;
3141
3142 if (state->dynamic.depth_bounds.min == minDepthBounds &&
3143 state->dynamic.depth_bounds.max == maxDepthBounds) {
3144 return;
3145 }
3146
3147 state->dynamic.depth_bounds.min = minDepthBounds;
3148 state->dynamic.depth_bounds.max = maxDepthBounds;
3149
3150 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3151 }
3152
3153 void radv_CmdSetStencilCompareMask(
3154 VkCommandBuffer commandBuffer,
3155 VkStencilFaceFlags faceMask,
3156 uint32_t compareMask)
3157 {
3158 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3159 struct radv_cmd_state *state = &cmd_buffer->state;
3160 bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3161 bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3162
3163 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3164 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3165 return;
3166 }
3167
3168 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3169 state->dynamic.stencil_compare_mask.front = compareMask;
3170 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3171 state->dynamic.stencil_compare_mask.back = compareMask;
3172
3173 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3174 }
3175
3176 void radv_CmdSetStencilWriteMask(
3177 VkCommandBuffer commandBuffer,
3178 VkStencilFaceFlags faceMask,
3179 uint32_t writeMask)
3180 {
3181 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3182 struct radv_cmd_state *state = &cmd_buffer->state;
3183 bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3184 bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3185
3186 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3187 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3188 return;
3189 }
3190
3191 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3192 state->dynamic.stencil_write_mask.front = writeMask;
3193 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3194 state->dynamic.stencil_write_mask.back = writeMask;
3195
3196 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3197 }
3198
3199 void radv_CmdSetStencilReference(
3200 VkCommandBuffer commandBuffer,
3201 VkStencilFaceFlags faceMask,
3202 uint32_t reference)
3203 {
3204 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3205 struct radv_cmd_state *state = &cmd_buffer->state;
3206 bool front_same = state->dynamic.stencil_reference.front == reference;
3207 bool back_same = state->dynamic.stencil_reference.back == reference;
3208
3209 if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3210 (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3211 return;
3212 }
3213
3214 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3215 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3216 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3217 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3218
3219 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3220 }
3221
3222 void radv_CmdSetDiscardRectangleEXT(
3223 VkCommandBuffer commandBuffer,
3224 uint32_t firstDiscardRectangle,
3225 uint32_t discardRectangleCount,
3226 const VkRect2D* pDiscardRectangles)
3227 {
3228 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3229 struct radv_cmd_state *state = &cmd_buffer->state;
3230 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3231
3232 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3233 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3234
3235 if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3236 pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3237 return;
3238 }
3239
3240 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3241 pDiscardRectangles, discardRectangleCount);
3242
3243 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3244 }
3245
3246 void radv_CmdExecuteCommands(
3247 VkCommandBuffer commandBuffer,
3248 uint32_t commandBufferCount,
3249 const VkCommandBuffer* pCmdBuffers)
3250 {
3251 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3252
3253 assert(commandBufferCount > 0);
3254
3255 /* Emit pending flushes on primary prior to executing secondary */
3256 si_emit_cache_flush(primary);
3257
3258 for (uint32_t i = 0; i < commandBufferCount; i++) {
3259 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3260
3261 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3262 secondary->scratch_size_needed);
3263 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3264 secondary->compute_scratch_size_needed);
3265
3266 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3267 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3268 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3269 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3270 if (secondary->tess_rings_needed)
3271 primary->tess_rings_needed = true;
3272 if (secondary->sample_positions_needed)
3273 primary->sample_positions_needed = true;
3274
3275 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3276
3277
3278 /* When the secondary command buffer is compute only we don't
3279 * need to re-emit the current graphics pipeline.
3280 */
3281 if (secondary->state.emitted_pipeline) {
3282 primary->state.emitted_pipeline =
3283 secondary->state.emitted_pipeline;
3284 }
3285
3286 /* When the secondary command buffer is graphics only we don't
3287 * need to re-emit the current compute pipeline.
3288 */
3289 if (secondary->state.emitted_compute_pipeline) {
3290 primary->state.emitted_compute_pipeline =
3291 secondary->state.emitted_compute_pipeline;
3292 }
3293
3294 /* Only re-emit the draw packets when needed. */
3295 if (secondary->state.last_primitive_reset_en != -1) {
3296 primary->state.last_primitive_reset_en =
3297 secondary->state.last_primitive_reset_en;
3298 }
3299
3300 if (secondary->state.last_primitive_reset_index) {
3301 primary->state.last_primitive_reset_index =
3302 secondary->state.last_primitive_reset_index;
3303 }
3304
3305 if (secondary->state.last_ia_multi_vgt_param) {
3306 primary->state.last_ia_multi_vgt_param =
3307 secondary->state.last_ia_multi_vgt_param;
3308 }
3309
3310 primary->state.last_first_instance = secondary->state.last_first_instance;
3311 primary->state.last_num_instances = secondary->state.last_num_instances;
3312 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3313
3314 if (secondary->state.last_index_type != -1) {
3315 primary->state.last_index_type =
3316 secondary->state.last_index_type;
3317 }
3318 }
3319
3320 /* After executing commands from secondary buffers we have to dirty
3321 * some states.
3322 */
3323 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3324 RADV_CMD_DIRTY_INDEX_BUFFER |
3325 RADV_CMD_DIRTY_DYNAMIC_ALL;
3326 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3327 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3328 }
3329
3330 VkResult radv_CreateCommandPool(
3331 VkDevice _device,
3332 const VkCommandPoolCreateInfo* pCreateInfo,
3333 const VkAllocationCallbacks* pAllocator,
3334 VkCommandPool* pCmdPool)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337 struct radv_cmd_pool *pool;
3338
3339 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3340 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3341 if (pool == NULL)
3342 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3343
3344 if (pAllocator)
3345 pool->alloc = *pAllocator;
3346 else
3347 pool->alloc = device->alloc;
3348
3349 list_inithead(&pool->cmd_buffers);
3350 list_inithead(&pool->free_cmd_buffers);
3351
3352 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3353
3354 *pCmdPool = radv_cmd_pool_to_handle(pool);
3355
3356 return VK_SUCCESS;
3357
3358 }
3359
3360 void radv_DestroyCommandPool(
3361 VkDevice _device,
3362 VkCommandPool commandPool,
3363 const VkAllocationCallbacks* pAllocator)
3364 {
3365 RADV_FROM_HANDLE(radv_device, device, _device);
3366 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3367
3368 if (!pool)
3369 return;
3370
3371 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3372 &pool->cmd_buffers, pool_link) {
3373 radv_cmd_buffer_destroy(cmd_buffer);
3374 }
3375
3376 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3377 &pool->free_cmd_buffers, pool_link) {
3378 radv_cmd_buffer_destroy(cmd_buffer);
3379 }
3380
3381 vk_free2(&device->alloc, pAllocator, pool);
3382 }
3383
3384 VkResult radv_ResetCommandPool(
3385 VkDevice device,
3386 VkCommandPool commandPool,
3387 VkCommandPoolResetFlags flags)
3388 {
3389 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3390 VkResult result;
3391
3392 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3393 &pool->cmd_buffers, pool_link) {
3394 result = radv_reset_cmd_buffer(cmd_buffer);
3395 if (result != VK_SUCCESS)
3396 return result;
3397 }
3398
3399 return VK_SUCCESS;
3400 }
3401
3402 void radv_TrimCommandPool(
3403 VkDevice device,
3404 VkCommandPool commandPool,
3405 VkCommandPoolTrimFlags flags)
3406 {
3407 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3408
3409 if (!pool)
3410 return;
3411
3412 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3413 &pool->free_cmd_buffers, pool_link) {
3414 radv_cmd_buffer_destroy(cmd_buffer);
3415 }
3416 }
3417
3418 void radv_CmdBeginRenderPass(
3419 VkCommandBuffer commandBuffer,
3420 const VkRenderPassBeginInfo* pRenderPassBegin,
3421 VkSubpassContents contents)
3422 {
3423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3424 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3425 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3426
3427 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3428 cmd_buffer->cs, 2048);
3429 MAYBE_UNUSED VkResult result;
3430
3431 cmd_buffer->state.framebuffer = framebuffer;
3432 cmd_buffer->state.pass = pass;
3433 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3434
3435 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3436 if (result != VK_SUCCESS)
3437 return;
3438
3439 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3440 assert(cmd_buffer->cs->cdw <= cdw_max);
3441
3442 radv_cmd_buffer_clear_subpass(cmd_buffer);
3443 }
3444
3445 void radv_CmdBeginRenderPass2KHR(
3446 VkCommandBuffer commandBuffer,
3447 const VkRenderPassBeginInfo* pRenderPassBeginInfo,
3448 const VkSubpassBeginInfoKHR* pSubpassBeginInfo)
3449 {
3450 radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3451 pSubpassBeginInfo->contents);
3452 }
3453
3454 void radv_CmdNextSubpass(
3455 VkCommandBuffer commandBuffer,
3456 VkSubpassContents contents)
3457 {
3458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3459
3460 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3461
3462 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3463 2048);
3464
3465 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3466 radv_cmd_buffer_clear_subpass(cmd_buffer);
3467 }
3468
3469 void radv_CmdNextSubpass2KHR(
3470 VkCommandBuffer commandBuffer,
3471 const VkSubpassBeginInfoKHR* pSubpassBeginInfo,
3472 const VkSubpassEndInfoKHR* pSubpassEndInfo)
3473 {
3474 radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3475 }
3476
3477 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3478 {
3479 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3480 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3481 if (!radv_get_shader(pipeline, stage))
3482 continue;
3483
3484 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3485 if (loc->sgpr_idx == -1)
3486 continue;
3487 uint32_t base_reg = pipeline->user_data_0[stage];
3488 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3489
3490 }
3491 if (pipeline->gs_copy_shader) {
3492 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3493 if (loc->sgpr_idx != -1) {
3494 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3495 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3496 }
3497 }
3498 }
3499
3500 static void
3501 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3502 uint32_t vertex_count,
3503 bool use_opaque)
3504 {
3505 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3506 radeon_emit(cmd_buffer->cs, vertex_count);
3507 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3508 S_0287F0_USE_OPAQUE(use_opaque));
3509 }
3510
3511 static void
3512 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3513 uint64_t index_va,
3514 uint32_t index_count)
3515 {
3516 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3517 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3518 radeon_emit(cmd_buffer->cs, index_va);
3519 radeon_emit(cmd_buffer->cs, index_va >> 32);
3520 radeon_emit(cmd_buffer->cs, index_count);
3521 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3522 }
3523
3524 static void
3525 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3526 bool indexed,
3527 uint32_t draw_count,
3528 uint64_t count_va,
3529 uint32_t stride)
3530 {
3531 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3532 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3533 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3534 bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3535 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3536 bool predicating = cmd_buffer->state.predicating;
3537 assert(base_reg);
3538
3539 /* just reset draw state for vertex data */
3540 cmd_buffer->state.last_first_instance = -1;
3541 cmd_buffer->state.last_num_instances = -1;
3542 cmd_buffer->state.last_vertex_offset = -1;
3543
3544 if (draw_count == 1 && !count_va && !draw_id_enable) {
3545 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3546 PKT3_DRAW_INDIRECT, 3, predicating));
3547 radeon_emit(cs, 0);
3548 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3549 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3550 radeon_emit(cs, di_src_sel);
3551 } else {
3552 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3553 PKT3_DRAW_INDIRECT_MULTI,
3554 8, predicating));
3555 radeon_emit(cs, 0);
3556 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3557 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3558 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3559 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3560 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3561 radeon_emit(cs, draw_count); /* count */
3562 radeon_emit(cs, count_va); /* count_addr */
3563 radeon_emit(cs, count_va >> 32);
3564 radeon_emit(cs, stride); /* stride */
3565 radeon_emit(cs, di_src_sel);
3566 }
3567 }
3568
3569 static void
3570 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3571 const struct radv_draw_info *info)
3572 {
3573 struct radv_cmd_state *state = &cmd_buffer->state;
3574 struct radeon_winsys *ws = cmd_buffer->device->ws;
3575 struct radeon_cmdbuf *cs = cmd_buffer->cs;
3576
3577 if (info->indirect) {
3578 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3579 uint64_t count_va = 0;
3580
3581 va += info->indirect->offset + info->indirect_offset;
3582
3583 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3584
3585 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3586 radeon_emit(cs, 1);
3587 radeon_emit(cs, va);
3588 radeon_emit(cs, va >> 32);
3589
3590 if (info->count_buffer) {
3591 count_va = radv_buffer_get_va(info->count_buffer->bo);
3592 count_va += info->count_buffer->offset +
3593 info->count_buffer_offset;
3594
3595 radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3596 }
3597
3598 if (!state->subpass->view_mask) {
3599 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3600 info->indexed,
3601 info->count,
3602 count_va,
3603 info->stride);
3604 } else {
3605 unsigned i;
3606 for_each_bit(i, state->subpass->view_mask) {
3607 radv_emit_view_index(cmd_buffer, i);
3608
3609 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3610 info->indexed,
3611 info->count,
3612 count_va,
3613 info->stride);
3614 }
3615 }
3616 } else {
3617 assert(state->pipeline->graphics.vtx_base_sgpr);
3618
3619 if (info->vertex_offset != state->last_vertex_offset ||
3620 info->first_instance != state->last_first_instance) {
3621 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3622 state->pipeline->graphics.vtx_emit_num);
3623
3624 radeon_emit(cs, info->vertex_offset);
3625 radeon_emit(cs, info->first_instance);
3626 if (state->pipeline->graphics.vtx_emit_num == 3)
3627 radeon_emit(cs, 0);
3628 state->last_first_instance = info->first_instance;
3629 state->last_vertex_offset = info->vertex_offset;
3630 }
3631
3632 if (state->last_num_instances != info->instance_count) {
3633 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3634 radeon_emit(cs, info->instance_count);
3635 state->last_num_instances = info->instance_count;
3636 }
3637
3638 if (info->indexed) {
3639 int index_size = state->index_type ? 4 : 2;
3640 uint64_t index_va;
3641
3642 index_va = state->index_va;
3643 index_va += info->first_index * index_size;
3644
3645 if (!state->subpass->view_mask) {
3646 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3647 index_va,
3648 info->count);
3649 } else {
3650 unsigned i;
3651 for_each_bit(i, state->subpass->view_mask) {
3652 radv_emit_view_index(cmd_buffer, i);
3653
3654 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3655 index_va,
3656 info->count);
3657 }
3658 }
3659 } else {
3660 if (!state->subpass->view_mask) {
3661 radv_cs_emit_draw_packet(cmd_buffer,
3662 info->count,
3663 !!info->strmout_buffer);
3664 } else {
3665 unsigned i;
3666 for_each_bit(i, state->subpass->view_mask) {
3667 radv_emit_view_index(cmd_buffer, i);
3668
3669 radv_cs_emit_draw_packet(cmd_buffer,
3670 info->count,
3671 !!info->strmout_buffer);
3672 }
3673 }
3674 }
3675 }
3676 }
3677
3678 /*
3679 * Vega and raven have a bug which triggers if there are multiple context
3680 * register contexts active at the same time with different scissor values.
3681 *
3682 * There are two possible workarounds:
3683 * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3684 * there is only ever 1 active set of scissor values at the same time.
3685 *
3686 * 2) Whenever the hardware switches contexts we have to set the scissor
3687 * registers again even if it is a noop. That way the new context gets
3688 * the correct scissor values.
3689 *
3690 * This implements option 2. radv_need_late_scissor_emission needs to
3691 * return true on affected HW if radv_emit_all_graphics_states sets
3692 * any context registers.
3693 */
3694 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3695 const struct radv_draw_info *info)
3696 {
3697 struct radv_cmd_state *state = &cmd_buffer->state;
3698
3699 if (!cmd_buffer->device->physical_device->has_scissor_bug)
3700 return false;
3701
3702 if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3703 return true;
3704
3705 uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3706
3707 /* Index, vertex and streamout buffers don't change context regs, and
3708 * pipeline is already handled.
3709 */
3710 used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3711 RADV_CMD_DIRTY_VERTEX_BUFFER |
3712 RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3713 RADV_CMD_DIRTY_PIPELINE);
3714
3715 if (cmd_buffer->state.dirty & used_states)
3716 return true;
3717
3718 if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3719 (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3720 return true;
3721
3722 return false;
3723 }
3724
3725 static void
3726 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3727 const struct radv_draw_info *info)
3728 {
3729 bool late_scissor_emission;
3730
3731 if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3732 cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3733 radv_emit_rbplus_state(cmd_buffer);
3734
3735 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3736 radv_emit_graphics_pipeline(cmd_buffer);
3737
3738 /* This should be before the cmd_buffer->state.dirty is cleared
3739 * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3740 * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3741 late_scissor_emission =
3742 radv_need_late_scissor_emission(cmd_buffer, info);
3743
3744 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3745 radv_emit_framebuffer_state(cmd_buffer);
3746
3747 if (info->indexed) {
3748 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3749 radv_emit_index_buffer(cmd_buffer);
3750 } else {
3751 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3752 * so the state must be re-emitted before the next indexed
3753 * draw.
3754 */
3755 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3756 cmd_buffer->state.last_index_type = -1;
3757 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3758 }
3759 }
3760
3761 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3762
3763 radv_emit_draw_registers(cmd_buffer, info);
3764
3765 if (late_scissor_emission)
3766 radv_emit_scissor(cmd_buffer);
3767 }
3768
3769 static void
3770 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3771 const struct radv_draw_info *info)
3772 {
3773 struct radeon_info *rad_info =
3774 &cmd_buffer->device->physical_device->rad_info;
3775 bool has_prefetch =
3776 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3777 bool pipeline_is_dirty =
3778 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3779 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3780
3781 MAYBE_UNUSED unsigned cdw_max =
3782 radeon_check_space(cmd_buffer->device->ws,
3783 cmd_buffer->cs, 4096);
3784
3785 if (likely(!info->indirect)) {
3786 /* SI-CI treat instance_count==0 as instance_count==1. There is
3787 * no workaround for indirect draws, but we can at least skip
3788 * direct draws.
3789 */
3790 if (unlikely(!info->instance_count))
3791 return;
3792
3793 /* Handle count == 0. */
3794 if (unlikely(!info->count && !info->strmout_buffer))
3795 return;
3796 }
3797
3798 /* Use optimal packet order based on whether we need to sync the
3799 * pipeline.
3800 */
3801 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3802 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3803 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3804 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3805 /* If we have to wait for idle, set all states first, so that
3806 * all SET packets are processed in parallel with previous draw
3807 * calls. Then upload descriptors, set shader pointers, and
3808 * draw, and prefetch at the end. This ensures that the time
3809 * the CUs are idle is very short. (there are only SET_SH
3810 * packets between the wait and the draw)
3811 */
3812 radv_emit_all_graphics_states(cmd_buffer, info);
3813 si_emit_cache_flush(cmd_buffer);
3814 /* <-- CUs are idle here --> */
3815
3816 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3817
3818 radv_emit_draw_packets(cmd_buffer, info);
3819 /* <-- CUs are busy here --> */
3820
3821 /* Start prefetches after the draw has been started. Both will
3822 * run in parallel, but starting the draw first is more
3823 * important.
3824 */
3825 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3826 radv_emit_prefetch_L2(cmd_buffer,
3827 cmd_buffer->state.pipeline, false);
3828 }
3829 } else {
3830 /* If we don't wait for idle, start prefetches first, then set
3831 * states, and draw at the end.
3832 */
3833 si_emit_cache_flush(cmd_buffer);
3834
3835 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3836 /* Only prefetch the vertex shader and VBO descriptors
3837 * in order to start the draw as soon as possible.
3838 */
3839 radv_emit_prefetch_L2(cmd_buffer,
3840 cmd_buffer->state.pipeline, true);
3841 }
3842
3843 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3844
3845 radv_emit_all_graphics_states(cmd_buffer, info);
3846 radv_emit_draw_packets(cmd_buffer, info);
3847
3848 /* Prefetch the remaining shaders after the draw has been
3849 * started.
3850 */
3851 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3852 radv_emit_prefetch_L2(cmd_buffer,
3853 cmd_buffer->state.pipeline, false);
3854 }
3855 }
3856
3857 /* Workaround for a VGT hang when streamout is enabled.
3858 * It must be done after drawing.
3859 */
3860 if (cmd_buffer->state.streamout.streamout_enabled &&
3861 (rad_info->family == CHIP_HAWAII ||
3862 rad_info->family == CHIP_TONGA ||
3863 rad_info->family == CHIP_FIJI)) {
3864 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3865 }
3866
3867 assert(cmd_buffer->cs->cdw <= cdw_max);
3868 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3869 }
3870
3871 void radv_CmdDraw(
3872 VkCommandBuffer commandBuffer,
3873 uint32_t vertexCount,
3874 uint32_t instanceCount,
3875 uint32_t firstVertex,
3876 uint32_t firstInstance)
3877 {
3878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3879 struct radv_draw_info info = {};
3880
3881 info.count = vertexCount;
3882 info.instance_count = instanceCount;
3883 info.first_instance = firstInstance;
3884 info.vertex_offset = firstVertex;
3885
3886 radv_draw(cmd_buffer, &info);
3887 }
3888
3889 void radv_CmdDrawIndexed(
3890 VkCommandBuffer commandBuffer,
3891 uint32_t indexCount,
3892 uint32_t instanceCount,
3893 uint32_t firstIndex,
3894 int32_t vertexOffset,
3895 uint32_t firstInstance)
3896 {
3897 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3898 struct radv_draw_info info = {};
3899
3900 info.indexed = true;
3901 info.count = indexCount;
3902 info.instance_count = instanceCount;
3903 info.first_index = firstIndex;
3904 info.vertex_offset = vertexOffset;
3905 info.first_instance = firstInstance;
3906
3907 radv_draw(cmd_buffer, &info);
3908 }
3909
3910 void radv_CmdDrawIndirect(
3911 VkCommandBuffer commandBuffer,
3912 VkBuffer _buffer,
3913 VkDeviceSize offset,
3914 uint32_t drawCount,
3915 uint32_t stride)
3916 {
3917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3918 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3919 struct radv_draw_info info = {};
3920
3921 info.count = drawCount;
3922 info.indirect = buffer;
3923 info.indirect_offset = offset;
3924 info.stride = stride;
3925
3926 radv_draw(cmd_buffer, &info);
3927 }
3928
3929 void radv_CmdDrawIndexedIndirect(
3930 VkCommandBuffer commandBuffer,
3931 VkBuffer _buffer,
3932 VkDeviceSize offset,
3933 uint32_t drawCount,
3934 uint32_t stride)
3935 {
3936 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3937 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3938 struct radv_draw_info info = {};
3939
3940 info.indexed = true;
3941 info.count = drawCount;
3942 info.indirect = buffer;
3943 info.indirect_offset = offset;
3944 info.stride = stride;
3945
3946 radv_draw(cmd_buffer, &info);
3947 }
3948
3949 void radv_CmdDrawIndirectCountAMD(
3950 VkCommandBuffer commandBuffer,
3951 VkBuffer _buffer,
3952 VkDeviceSize offset,
3953 VkBuffer _countBuffer,
3954 VkDeviceSize countBufferOffset,
3955 uint32_t maxDrawCount,
3956 uint32_t stride)
3957 {
3958 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3959 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3960 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3961 struct radv_draw_info info = {};
3962
3963 info.count = maxDrawCount;
3964 info.indirect = buffer;
3965 info.indirect_offset = offset;
3966 info.count_buffer = count_buffer;
3967 info.count_buffer_offset = countBufferOffset;
3968 info.stride = stride;
3969
3970 radv_draw(cmd_buffer, &info);
3971 }
3972
3973 void radv_CmdDrawIndexedIndirectCountAMD(
3974 VkCommandBuffer commandBuffer,
3975 VkBuffer _buffer,
3976 VkDeviceSize offset,
3977 VkBuffer _countBuffer,
3978 VkDeviceSize countBufferOffset,
3979 uint32_t maxDrawCount,
3980 uint32_t stride)
3981 {
3982 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3983 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3984 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3985 struct radv_draw_info info = {};
3986
3987 info.indexed = true;
3988 info.count = maxDrawCount;
3989 info.indirect = buffer;
3990 info.indirect_offset = offset;
3991 info.count_buffer = count_buffer;
3992 info.count_buffer_offset = countBufferOffset;
3993 info.stride = stride;
3994
3995 radv_draw(cmd_buffer, &info);
3996 }
3997
3998 void radv_CmdDrawIndirectCountKHR(
3999 VkCommandBuffer commandBuffer,
4000 VkBuffer _buffer,
4001 VkDeviceSize offset,
4002 VkBuffer _countBuffer,
4003 VkDeviceSize countBufferOffset,
4004 uint32_t maxDrawCount,
4005 uint32_t stride)
4006 {
4007 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4008 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4009 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4010 struct radv_draw_info info = {};
4011
4012 info.count = maxDrawCount;
4013 info.indirect = buffer;
4014 info.indirect_offset = offset;
4015 info.count_buffer = count_buffer;
4016 info.count_buffer_offset = countBufferOffset;
4017 info.stride = stride;
4018
4019 radv_draw(cmd_buffer, &info);
4020 }
4021
4022 void radv_CmdDrawIndexedIndirectCountKHR(
4023 VkCommandBuffer commandBuffer,
4024 VkBuffer _buffer,
4025 VkDeviceSize offset,
4026 VkBuffer _countBuffer,
4027 VkDeviceSize countBufferOffset,
4028 uint32_t maxDrawCount,
4029 uint32_t stride)
4030 {
4031 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4032 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4033 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4034 struct radv_draw_info info = {};
4035
4036 info.indexed = true;
4037 info.count = maxDrawCount;
4038 info.indirect = buffer;
4039 info.indirect_offset = offset;
4040 info.count_buffer = count_buffer;
4041 info.count_buffer_offset = countBufferOffset;
4042 info.stride = stride;
4043
4044 radv_draw(cmd_buffer, &info);
4045 }
4046
4047 struct radv_dispatch_info {
4048 /**
4049 * Determine the layout of the grid (in block units) to be used.
4050 */
4051 uint32_t blocks[3];
4052
4053 /**
4054 * A starting offset for the grid. If unaligned is set, the offset
4055 * must still be aligned.
4056 */
4057 uint32_t offsets[3];
4058 /**
4059 * Whether it's an unaligned compute dispatch.
4060 */
4061 bool unaligned;
4062
4063 /**
4064 * Indirect compute parameters resource.
4065 */
4066 struct radv_buffer *indirect;
4067 uint64_t indirect_offset;
4068 };
4069
4070 static void
4071 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4072 const struct radv_dispatch_info *info)
4073 {
4074 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4075 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4076 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4077 struct radeon_winsys *ws = cmd_buffer->device->ws;
4078 bool predicating = cmd_buffer->state.predicating;
4079 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4080 struct radv_userdata_info *loc;
4081
4082 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4083 AC_UD_CS_GRID_SIZE);
4084
4085 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4086
4087 if (info->indirect) {
4088 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4089
4090 va += info->indirect->offset + info->indirect_offset;
4091
4092 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4093
4094 if (loc->sgpr_idx != -1) {
4095 for (unsigned i = 0; i < 3; ++i) {
4096 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4097 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4098 COPY_DATA_DST_SEL(COPY_DATA_REG));
4099 radeon_emit(cs, (va + 4 * i));
4100 radeon_emit(cs, (va + 4 * i) >> 32);
4101 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4102 + loc->sgpr_idx * 4) >> 2) + i);
4103 radeon_emit(cs, 0);
4104 }
4105 }
4106
4107 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4108 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4109 PKT3_SHADER_TYPE_S(1));
4110 radeon_emit(cs, va);
4111 radeon_emit(cs, va >> 32);
4112 radeon_emit(cs, dispatch_initiator);
4113 } else {
4114 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4115 PKT3_SHADER_TYPE_S(1));
4116 radeon_emit(cs, 1);
4117 radeon_emit(cs, va);
4118 radeon_emit(cs, va >> 32);
4119
4120 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4121 PKT3_SHADER_TYPE_S(1));
4122 radeon_emit(cs, 0);
4123 radeon_emit(cs, dispatch_initiator);
4124 }
4125 } else {
4126 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4127 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4128
4129 if (info->unaligned) {
4130 unsigned *cs_block_size = compute_shader->info.cs.block_size;
4131 unsigned remainder[3];
4132
4133 /* If aligned, these should be an entire block size,
4134 * not 0.
4135 */
4136 remainder[0] = blocks[0] + cs_block_size[0] -
4137 align_u32_npot(blocks[0], cs_block_size[0]);
4138 remainder[1] = blocks[1] + cs_block_size[1] -
4139 align_u32_npot(blocks[1], cs_block_size[1]);
4140 remainder[2] = blocks[2] + cs_block_size[2] -
4141 align_u32_npot(blocks[2], cs_block_size[2]);
4142
4143 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4144 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4145 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4146
4147 for(unsigned i = 0; i < 3; ++i) {
4148 assert(offsets[i] % cs_block_size[i] == 0);
4149 offsets[i] /= cs_block_size[i];
4150 }
4151
4152 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4153 radeon_emit(cs,
4154 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4155 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4156 radeon_emit(cs,
4157 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4158 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4159 radeon_emit(cs,
4160 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4161 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4162
4163 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4164 }
4165
4166 if (loc->sgpr_idx != -1) {
4167 assert(!loc->indirect);
4168 assert(loc->num_sgprs == 3);
4169
4170 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4171 loc->sgpr_idx * 4, 3);
4172 radeon_emit(cs, blocks[0]);
4173 radeon_emit(cs, blocks[1]);
4174 radeon_emit(cs, blocks[2]);
4175 }
4176
4177 if (offsets[0] || offsets[1] || offsets[2]) {
4178 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4179 radeon_emit(cs, offsets[0]);
4180 radeon_emit(cs, offsets[1]);
4181 radeon_emit(cs, offsets[2]);
4182
4183 /* The blocks in the packet are not counts but end values. */
4184 for (unsigned i = 0; i < 3; ++i)
4185 blocks[i] += offsets[i];
4186 } else {
4187 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4188 }
4189
4190 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4191 PKT3_SHADER_TYPE_S(1));
4192 radeon_emit(cs, blocks[0]);
4193 radeon_emit(cs, blocks[1]);
4194 radeon_emit(cs, blocks[2]);
4195 radeon_emit(cs, dispatch_initiator);
4196 }
4197
4198 assert(cmd_buffer->cs->cdw <= cdw_max);
4199 }
4200
4201 static void
4202 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4203 {
4204 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4205 radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4206 }
4207
4208 static void
4209 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4210 const struct radv_dispatch_info *info)
4211 {
4212 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4213 bool has_prefetch =
4214 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4215 bool pipeline_is_dirty = pipeline &&
4216 pipeline != cmd_buffer->state.emitted_compute_pipeline;
4217
4218 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4219 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4220 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4221 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4222 /* If we have to wait for idle, set all states first, so that
4223 * all SET packets are processed in parallel with previous draw
4224 * calls. Then upload descriptors, set shader pointers, and
4225 * dispatch, and prefetch at the end. This ensures that the
4226 * time the CUs are idle is very short. (there are only SET_SH
4227 * packets between the wait and the draw)
4228 */
4229 radv_emit_compute_pipeline(cmd_buffer);
4230 si_emit_cache_flush(cmd_buffer);
4231 /* <-- CUs are idle here --> */
4232
4233 radv_upload_compute_shader_descriptors(cmd_buffer);
4234
4235 radv_emit_dispatch_packets(cmd_buffer, info);
4236 /* <-- CUs are busy here --> */
4237
4238 /* Start prefetches after the dispatch has been started. Both
4239 * will run in parallel, but starting the dispatch first is
4240 * more important.
4241 */
4242 if (has_prefetch && pipeline_is_dirty) {
4243 radv_emit_shader_prefetch(cmd_buffer,
4244 pipeline->shaders[MESA_SHADER_COMPUTE]);
4245 }
4246 } else {
4247 /* If we don't wait for idle, start prefetches first, then set
4248 * states, and dispatch at the end.
4249 */
4250 si_emit_cache_flush(cmd_buffer);
4251
4252 if (has_prefetch && pipeline_is_dirty) {
4253 radv_emit_shader_prefetch(cmd_buffer,
4254 pipeline->shaders[MESA_SHADER_COMPUTE]);
4255 }
4256
4257 radv_upload_compute_shader_descriptors(cmd_buffer);
4258
4259 radv_emit_compute_pipeline(cmd_buffer);
4260 radv_emit_dispatch_packets(cmd_buffer, info);
4261 }
4262
4263 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4264 }
4265
4266 void radv_CmdDispatchBase(
4267 VkCommandBuffer commandBuffer,
4268 uint32_t base_x,
4269 uint32_t base_y,
4270 uint32_t base_z,
4271 uint32_t x,
4272 uint32_t y,
4273 uint32_t z)
4274 {
4275 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4276 struct radv_dispatch_info info = {};
4277
4278 info.blocks[0] = x;
4279 info.blocks[1] = y;
4280 info.blocks[2] = z;
4281
4282 info.offsets[0] = base_x;
4283 info.offsets[1] = base_y;
4284 info.offsets[2] = base_z;
4285 radv_dispatch(cmd_buffer, &info);
4286 }
4287
4288 void radv_CmdDispatch(
4289 VkCommandBuffer commandBuffer,
4290 uint32_t x,
4291 uint32_t y,
4292 uint32_t z)
4293 {
4294 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4295 }
4296
4297 void radv_CmdDispatchIndirect(
4298 VkCommandBuffer commandBuffer,
4299 VkBuffer _buffer,
4300 VkDeviceSize offset)
4301 {
4302 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4303 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4304 struct radv_dispatch_info info = {};
4305
4306 info.indirect = buffer;
4307 info.indirect_offset = offset;
4308
4309 radv_dispatch(cmd_buffer, &info);
4310 }
4311
4312 void radv_unaligned_dispatch(
4313 struct radv_cmd_buffer *cmd_buffer,
4314 uint32_t x,
4315 uint32_t y,
4316 uint32_t z)
4317 {
4318 struct radv_dispatch_info info = {};
4319
4320 info.blocks[0] = x;
4321 info.blocks[1] = y;
4322 info.blocks[2] = z;
4323 info.unaligned = 1;
4324
4325 radv_dispatch(cmd_buffer, &info);
4326 }
4327
4328 void radv_CmdEndRenderPass(
4329 VkCommandBuffer commandBuffer)
4330 {
4331 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4332
4333 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4334
4335 radv_cmd_buffer_resolve_subpass(cmd_buffer);
4336
4337 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4338 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4339 radv_handle_subpass_image_transition(cmd_buffer,
4340 (struct radv_subpass_attachment){i, layout});
4341 }
4342
4343 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4344
4345 cmd_buffer->state.pass = NULL;
4346 cmd_buffer->state.subpass = NULL;
4347 cmd_buffer->state.attachments = NULL;
4348 cmd_buffer->state.framebuffer = NULL;
4349 }
4350
4351 void radv_CmdEndRenderPass2KHR(
4352 VkCommandBuffer commandBuffer,
4353 const VkSubpassEndInfoKHR* pSubpassEndInfo)
4354 {
4355 radv_CmdEndRenderPass(commandBuffer);
4356 }
4357
4358 /*
4359 * For HTILE we have the following interesting clear words:
4360 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4361 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4362 * 0xfffffff0: Clear depth to 1.0
4363 * 0x00000000: Clear depth to 0.0
4364 */
4365 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4366 struct radv_image *image,
4367 const VkImageSubresourceRange *range,
4368 uint32_t clear_word)
4369 {
4370 assert(range->baseMipLevel == 0);
4371 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4372 unsigned layer_count = radv_get_layerCount(image, range);
4373 uint64_t size = image->surface.htile_slice_size * layer_count;
4374 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4375 uint64_t offset = image->offset + image->htile_offset +
4376 image->surface.htile_slice_size * range->baseArrayLayer;
4377 struct radv_cmd_state *state = &cmd_buffer->state;
4378 VkClearDepthStencilValue value = {};
4379
4380 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4381 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4382
4383 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4384 size, clear_word);
4385
4386 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4387
4388 if (vk_format_is_stencil(image->vk_format))
4389 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4390
4391 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4392
4393 if (radv_image_is_tc_compat_htile(image)) {
4394 /* Initialize the TC-compat metada value to 0 because by
4395 * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4396 * need have to conditionally update its value when performing
4397 * a fast depth clear.
4398 */
4399 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4400 }
4401 }
4402
4403 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4404 struct radv_image *image,
4405 VkImageLayout src_layout,
4406 VkImageLayout dst_layout,
4407 unsigned src_queue_mask,
4408 unsigned dst_queue_mask,
4409 const VkImageSubresourceRange *range)
4410 {
4411 if (!radv_image_has_htile(image))
4412 return;
4413
4414 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4415 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4416 /* TODO: merge with the clear if applicable */
4417 radv_initialize_htile(cmd_buffer, image, range, 0);
4418 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4419 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4420 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4421 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4422 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4423 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4424 VkImageSubresourceRange local_range = *range;
4425 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4426 local_range.baseMipLevel = 0;
4427 local_range.levelCount = 1;
4428
4429 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4430 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4431
4432 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4433
4434 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4435 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4436 }
4437 }
4438
4439 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4440 struct radv_image *image, uint32_t value)
4441 {
4442 struct radv_cmd_state *state = &cmd_buffer->state;
4443
4444 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4445 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4446
4447 state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4448
4449 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4450 }
4451
4452 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4453 struct radv_image *image)
4454 {
4455 struct radv_cmd_state *state = &cmd_buffer->state;
4456 static const uint32_t fmask_clear_values[4] = {
4457 0x00000000,
4458 0x02020202,
4459 0xE4E4E4E4,
4460 0x76543210
4461 };
4462 uint32_t log2_samples = util_logbase2(image->info.samples);
4463 uint32_t value = fmask_clear_values[log2_samples];
4464
4465 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4466 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4467
4468 state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4469
4470 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4471 }
4472
4473 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4474 struct radv_image *image, uint32_t value)
4475 {
4476 struct radv_cmd_state *state = &cmd_buffer->state;
4477
4478 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4479 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4480
4481 state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4482
4483 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4484 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4485 }
4486
4487 /**
4488 * Initialize DCC/FMASK/CMASK metadata for a color image.
4489 */
4490 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4491 struct radv_image *image,
4492 VkImageLayout src_layout,
4493 VkImageLayout dst_layout,
4494 unsigned src_queue_mask,
4495 unsigned dst_queue_mask)
4496 {
4497 if (radv_image_has_cmask(image)) {
4498 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4499
4500 /* TODO: clarify this. */
4501 if (radv_image_has_fmask(image)) {
4502 value = 0xccccccccu;
4503 }
4504
4505 radv_initialise_cmask(cmd_buffer, image, value);
4506 }
4507
4508 if (radv_image_has_fmask(image)) {
4509 radv_initialize_fmask(cmd_buffer, image);
4510 }
4511
4512 if (radv_image_has_dcc(image)) {
4513 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4514 bool need_decompress_pass = false;
4515
4516 if (radv_layout_dcc_compressed(image, dst_layout,
4517 dst_queue_mask)) {
4518 value = 0x20202020u;
4519 need_decompress_pass = true;
4520 }
4521
4522 radv_initialize_dcc(cmd_buffer, image, value);
4523
4524 radv_update_fce_metadata(cmd_buffer, image,
4525 need_decompress_pass);
4526 }
4527
4528 if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4529 uint32_t color_values[2] = {};
4530 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4531 }
4532 }
4533
4534 /**
4535 * Handle color image transitions for DCC/FMASK/CMASK.
4536 */
4537 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4538 struct radv_image *image,
4539 VkImageLayout src_layout,
4540 VkImageLayout dst_layout,
4541 unsigned src_queue_mask,
4542 unsigned dst_queue_mask,
4543 const VkImageSubresourceRange *range)
4544 {
4545 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4546 radv_init_color_image_metadata(cmd_buffer, image,
4547 src_layout, dst_layout,
4548 src_queue_mask, dst_queue_mask);
4549 return;
4550 }
4551
4552 if (radv_image_has_dcc(image)) {
4553 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4554 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4555 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4556 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4557 radv_decompress_dcc(cmd_buffer, image, range);
4558 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4559 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4560 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4561 }
4562 } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4563 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4564 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4565 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4566 }
4567
4568 if (radv_image_has_fmask(image)) {
4569 if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4570 dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4571 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4572 }
4573 }
4574 }
4575 }
4576
4577 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4578 struct radv_image *image,
4579 VkImageLayout src_layout,
4580 VkImageLayout dst_layout,
4581 uint32_t src_family,
4582 uint32_t dst_family,
4583 const VkImageSubresourceRange *range)
4584 {
4585 if (image->exclusive && src_family != dst_family) {
4586 /* This is an acquire or a release operation and there will be
4587 * a corresponding release/acquire. Do the transition in the
4588 * most flexible queue. */
4589
4590 assert(src_family == cmd_buffer->queue_family_index ||
4591 dst_family == cmd_buffer->queue_family_index);
4592
4593 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4594 return;
4595
4596 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4597 (src_family == RADV_QUEUE_GENERAL ||
4598 dst_family == RADV_QUEUE_GENERAL))
4599 return;
4600 }
4601
4602 unsigned src_queue_mask =
4603 radv_image_queue_family_mask(image, src_family,
4604 cmd_buffer->queue_family_index);
4605 unsigned dst_queue_mask =
4606 radv_image_queue_family_mask(image, dst_family,
4607 cmd_buffer->queue_family_index);
4608
4609 if (vk_format_is_depth(image->vk_format)) {
4610 radv_handle_depth_image_transition(cmd_buffer, image,
4611 src_layout, dst_layout,
4612 src_queue_mask, dst_queue_mask,
4613 range);
4614 } else {
4615 radv_handle_color_image_transition(cmd_buffer, image,
4616 src_layout, dst_layout,
4617 src_queue_mask, dst_queue_mask,
4618 range);
4619 }
4620 }
4621
4622 struct radv_barrier_info {
4623 uint32_t eventCount;
4624 const VkEvent *pEvents;
4625 VkPipelineStageFlags srcStageMask;
4626 };
4627
4628 static void
4629 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4630 uint32_t memoryBarrierCount,
4631 const VkMemoryBarrier *pMemoryBarriers,
4632 uint32_t bufferMemoryBarrierCount,
4633 const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4634 uint32_t imageMemoryBarrierCount,
4635 const VkImageMemoryBarrier *pImageMemoryBarriers,
4636 const struct radv_barrier_info *info)
4637 {
4638 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4639 enum radv_cmd_flush_bits src_flush_bits = 0;
4640 enum radv_cmd_flush_bits dst_flush_bits = 0;
4641
4642 for (unsigned i = 0; i < info->eventCount; ++i) {
4643 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4644 uint64_t va = radv_buffer_get_va(event->bo);
4645
4646 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4647
4648 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4649
4650 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4651 assert(cmd_buffer->cs->cdw <= cdw_max);
4652 }
4653
4654 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4655 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4656 NULL);
4657 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4658 NULL);
4659 }
4660
4661 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4662 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4663 NULL);
4664 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4665 NULL);
4666 }
4667
4668 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4669 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4670
4671 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4672 image);
4673 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4674 image);
4675 }
4676
4677 radv_stage_flush(cmd_buffer, info->srcStageMask);
4678 cmd_buffer->state.flush_bits |= src_flush_bits;
4679
4680 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4681 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4682 radv_handle_image_transition(cmd_buffer, image,
4683 pImageMemoryBarriers[i].oldLayout,
4684 pImageMemoryBarriers[i].newLayout,
4685 pImageMemoryBarriers[i].srcQueueFamilyIndex,
4686 pImageMemoryBarriers[i].dstQueueFamilyIndex,
4687 &pImageMemoryBarriers[i].subresourceRange);
4688 }
4689
4690 /* Make sure CP DMA is idle because the driver might have performed a
4691 * DMA operation for copying or filling buffers/images.
4692 */
4693 if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4694 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4695 si_cp_dma_wait_for_idle(cmd_buffer);
4696
4697 cmd_buffer->state.flush_bits |= dst_flush_bits;
4698 }
4699
4700 void radv_CmdPipelineBarrier(
4701 VkCommandBuffer commandBuffer,
4702 VkPipelineStageFlags srcStageMask,
4703 VkPipelineStageFlags destStageMask,
4704 VkBool32 byRegion,
4705 uint32_t memoryBarrierCount,
4706 const VkMemoryBarrier* pMemoryBarriers,
4707 uint32_t bufferMemoryBarrierCount,
4708 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4709 uint32_t imageMemoryBarrierCount,
4710 const VkImageMemoryBarrier* pImageMemoryBarriers)
4711 {
4712 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4713 struct radv_barrier_info info;
4714
4715 info.eventCount = 0;
4716 info.pEvents = NULL;
4717 info.srcStageMask = srcStageMask;
4718
4719 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4720 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4721 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4722 }
4723
4724
4725 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4726 struct radv_event *event,
4727 VkPipelineStageFlags stageMask,
4728 unsigned value)
4729 {
4730 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4731 uint64_t va = radv_buffer_get_va(event->bo);
4732
4733 si_emit_cache_flush(cmd_buffer);
4734
4735 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4736
4737 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4738
4739 /* Flags that only require a top-of-pipe event. */
4740 VkPipelineStageFlags top_of_pipe_flags =
4741 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4742
4743 /* Flags that only require a post-index-fetch event. */
4744 VkPipelineStageFlags post_index_fetch_flags =
4745 top_of_pipe_flags |
4746 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4747 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4748
4749 /* Make sure CP DMA is idle because the driver might have performed a
4750 * DMA operation for copying or filling buffers/images.
4751 */
4752 if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4753 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4754 si_cp_dma_wait_for_idle(cmd_buffer);
4755
4756 /* TODO: Emit EOS events for syncing PS/CS stages. */
4757
4758 if (!(stageMask & ~top_of_pipe_flags)) {
4759 /* Just need to sync the PFP engine. */
4760 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4761 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4762 S_370_WR_CONFIRM(1) |
4763 S_370_ENGINE_SEL(V_370_PFP));
4764 radeon_emit(cs, va);
4765 radeon_emit(cs, va >> 32);
4766 radeon_emit(cs, value);
4767 } else if (!(stageMask & ~post_index_fetch_flags)) {
4768 /* Sync ME because PFP reads index and indirect buffers. */
4769 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4770 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4771 S_370_WR_CONFIRM(1) |
4772 S_370_ENGINE_SEL(V_370_ME));
4773 radeon_emit(cs, va);
4774 radeon_emit(cs, va >> 32);
4775 radeon_emit(cs, value);
4776 } else {
4777 /* Otherwise, sync all prior GPU work using an EOP event. */
4778 si_cs_emit_write_event_eop(cs,
4779 cmd_buffer->device->physical_device->rad_info.chip_class,
4780 radv_cmd_buffer_uses_mec(cmd_buffer),
4781 V_028A90_BOTTOM_OF_PIPE_TS, 0,
4782 EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4783 cmd_buffer->gfx9_eop_bug_va);
4784 }
4785
4786 assert(cmd_buffer->cs->cdw <= cdw_max);
4787 }
4788
4789 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4790 VkEvent _event,
4791 VkPipelineStageFlags stageMask)
4792 {
4793 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4794 RADV_FROM_HANDLE(radv_event, event, _event);
4795
4796 write_event(cmd_buffer, event, stageMask, 1);
4797 }
4798
4799 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4800 VkEvent _event,
4801 VkPipelineStageFlags stageMask)
4802 {
4803 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4804 RADV_FROM_HANDLE(radv_event, event, _event);
4805
4806 write_event(cmd_buffer, event, stageMask, 0);
4807 }
4808
4809 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4810 uint32_t eventCount,
4811 const VkEvent* pEvents,
4812 VkPipelineStageFlags srcStageMask,
4813 VkPipelineStageFlags dstStageMask,
4814 uint32_t memoryBarrierCount,
4815 const VkMemoryBarrier* pMemoryBarriers,
4816 uint32_t bufferMemoryBarrierCount,
4817 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4818 uint32_t imageMemoryBarrierCount,
4819 const VkImageMemoryBarrier* pImageMemoryBarriers)
4820 {
4821 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4822 struct radv_barrier_info info;
4823
4824 info.eventCount = eventCount;
4825 info.pEvents = pEvents;
4826 info.srcStageMask = 0;
4827
4828 radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4829 bufferMemoryBarrierCount, pBufferMemoryBarriers,
4830 imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4831 }
4832
4833
4834 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4835 uint32_t deviceMask)
4836 {
4837 /* No-op */
4838 }
4839
4840 /* VK_EXT_conditional_rendering */
4841 void radv_CmdBeginConditionalRenderingEXT(
4842 VkCommandBuffer commandBuffer,
4843 const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)
4844 {
4845 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4846 RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4847 bool draw_visible = true;
4848 uint64_t va;
4849
4850 va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4851
4852 /* By default, if the 32-bit value at offset in buffer memory is zero,
4853 * then the rendering commands are discarded, otherwise they are
4854 * executed as normal. If the inverted flag is set, all commands are
4855 * discarded if the value is non zero.
4856 */
4857 if (pConditionalRenderingBegin->flags &
4858 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4859 draw_visible = false;
4860 }
4861
4862 si_emit_cache_flush(cmd_buffer);
4863
4864 /* Enable predication for this command buffer. */
4865 si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4866 cmd_buffer->state.predicating = true;
4867
4868 /* Store conditional rendering user info. */
4869 cmd_buffer->state.predication_type = draw_visible;
4870 cmd_buffer->state.predication_va = va;
4871 }
4872
4873 void radv_CmdEndConditionalRenderingEXT(
4874 VkCommandBuffer commandBuffer)
4875 {
4876 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4877
4878 /* Disable predication for this command buffer. */
4879 si_emit_set_predication_state(cmd_buffer, false, 0);
4880 cmd_buffer->state.predicating = false;
4881
4882 /* Reset conditional rendering user info. */
4883 cmd_buffer->state.predication_type = -1;
4884 cmd_buffer->state.predication_va = 0;
4885 }
4886
4887 /* VK_EXT_transform_feedback */
4888 void radv_CmdBindTransformFeedbackBuffersEXT(
4889 VkCommandBuffer commandBuffer,
4890 uint32_t firstBinding,
4891 uint32_t bindingCount,
4892 const VkBuffer* pBuffers,
4893 const VkDeviceSize* pOffsets,
4894 const VkDeviceSize* pSizes)
4895 {
4896 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4897 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4898 uint8_t enabled_mask = 0;
4899
4900 assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4901 for (uint32_t i = 0; i < bindingCount; i++) {
4902 uint32_t idx = firstBinding + i;
4903
4904 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4905 sb[idx].offset = pOffsets[i];
4906 sb[idx].size = pSizes[i];
4907
4908 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4909 sb[idx].buffer->bo);
4910
4911 enabled_mask |= 1 << idx;
4912 }
4913
4914 cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4915
4916 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4917 }
4918
4919 static void
4920 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4921 {
4922 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4923 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4924
4925 radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4926 radeon_emit(cs,
4927 S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4928 S_028B94_RAST_STREAM(0) |
4929 S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4930 S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4931 S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4932 radeon_emit(cs, so->hw_enabled_mask &
4933 so->enabled_stream_buffers_mask);
4934
4935 cmd_buffer->state.context_roll_without_scissor_emitted = true;
4936 }
4937
4938 static void
4939 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4940 {
4941 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4942 bool old_streamout_enabled = so->streamout_enabled;
4943 uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4944
4945 so->streamout_enabled = enable;
4946
4947 so->hw_enabled_mask = so->enabled_mask |
4948 (so->enabled_mask << 4) |
4949 (so->enabled_mask << 8) |
4950 (so->enabled_mask << 12);
4951
4952 if ((old_streamout_enabled != so->streamout_enabled) ||
4953 (old_hw_enabled_mask != so->hw_enabled_mask))
4954 radv_emit_streamout_enable(cmd_buffer);
4955 }
4956
4957 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4958 {
4959 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4960 unsigned reg_strmout_cntl;
4961
4962 /* The register is at different places on different ASICs. */
4963 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4964 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4965 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4966 } else {
4967 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4968 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4969 }
4970
4971 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4972 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4973
4974 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4975 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4976 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
4977 radeon_emit(cs, 0);
4978 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4979 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4980 radeon_emit(cs, 4); /* poll interval */
4981 }
4982
4983 void radv_CmdBeginTransformFeedbackEXT(
4984 VkCommandBuffer commandBuffer,
4985 uint32_t firstCounterBuffer,
4986 uint32_t counterBufferCount,
4987 const VkBuffer* pCounterBuffers,
4988 const VkDeviceSize* pCounterBufferOffsets)
4989 {
4990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4991 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4992 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4993 struct radeon_cmdbuf *cs = cmd_buffer->cs;
4994 uint32_t i;
4995
4996 radv_flush_vgt_streamout(cmd_buffer);
4997
4998 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4999 for_each_bit(i, so->enabled_mask) {
5000 int32_t counter_buffer_idx = i - firstCounterBuffer;
5001 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5002 counter_buffer_idx = -1;
5003
5004 /* SI binds streamout buffers as shader resources.
5005 * VGT only counts primitives and tells the shader through
5006 * SGPRs what to do.
5007 */
5008 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5009 radeon_emit(cs, sb[i].size >> 2); /* BUFFER_SIZE (in DW) */
5010 radeon_emit(cs, so->stride_in_dw[i]); /* VTX_STRIDE (in DW) */
5011
5012 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5013
5014 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5015 /* The array of counter buffers is optional. */
5016 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5017 uint64_t va = radv_buffer_get_va(buffer->bo);
5018
5019 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5020
5021 /* Append */
5022 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5023 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5024 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5025 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5026 radeon_emit(cs, 0); /* unused */
5027 radeon_emit(cs, 0); /* unused */
5028 radeon_emit(cs, va); /* src address lo */
5029 radeon_emit(cs, va >> 32); /* src address hi */
5030
5031 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5032 } else {
5033 /* Start from the beginning. */
5034 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5035 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5036 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5037 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5038 radeon_emit(cs, 0); /* unused */
5039 radeon_emit(cs, 0); /* unused */
5040 radeon_emit(cs, 0); /* unused */
5041 radeon_emit(cs, 0); /* unused */
5042 }
5043 }
5044
5045 radv_set_streamout_enable(cmd_buffer, true);
5046 }
5047
5048 void radv_CmdEndTransformFeedbackEXT(
5049 VkCommandBuffer commandBuffer,
5050 uint32_t firstCounterBuffer,
5051 uint32_t counterBufferCount,
5052 const VkBuffer* pCounterBuffers,
5053 const VkDeviceSize* pCounterBufferOffsets)
5054 {
5055 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5056 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5057 struct radeon_cmdbuf *cs = cmd_buffer->cs;
5058 uint32_t i;
5059
5060 radv_flush_vgt_streamout(cmd_buffer);
5061
5062 assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5063 for_each_bit(i, so->enabled_mask) {
5064 int32_t counter_buffer_idx = i - firstCounterBuffer;
5065 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5066 counter_buffer_idx = -1;
5067
5068 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5069 /* The array of counters buffer is optional. */
5070 RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5071 uint64_t va = radv_buffer_get_va(buffer->bo);
5072
5073 va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5074
5075 radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5076 radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5077 STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5078 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5079 STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5080 radeon_emit(cs, va); /* dst address lo */
5081 radeon_emit(cs, va >> 32); /* dst address hi */
5082 radeon_emit(cs, 0); /* unused */
5083 radeon_emit(cs, 0); /* unused */
5084
5085 radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5086 }
5087
5088 /* Deactivate transform feedback by zeroing the buffer size.
5089 * The counters (primitives generated, primitives emitted) may
5090 * be enabled even if there is not buffer bound. This ensures
5091 * that the primitives-emitted query won't increment.
5092 */
5093 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5094
5095 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5096 }
5097
5098 radv_set_streamout_enable(cmd_buffer, false);
5099 }
5100
5101 void radv_CmdDrawIndirectByteCountEXT(
5102 VkCommandBuffer commandBuffer,
5103 uint32_t instanceCount,
5104 uint32_t firstInstance,
5105 VkBuffer _counterBuffer,
5106 VkDeviceSize counterBufferOffset,
5107 uint32_t counterOffset,
5108 uint32_t vertexStride)
5109 {
5110 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5111 RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5112 struct radv_draw_info info = {};
5113
5114 info.instance_count = instanceCount;
5115 info.first_instance = firstInstance;
5116 info.strmout_buffer = counterBuffer;
5117 info.strmout_buffer_offset = counterBufferOffset;
5118 info.stride = vertexStride;
5119
5120 radv_draw(cmd_buffer, &info);
5121 }