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radv: enable VK_KHR_shader_float_controls on GFX6-GFX7
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
36 #include "radv_cs.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
39 #include "vk_util.h"
40 #include <xf86drm.h>
41 #include <amdgpu.h>
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "git_sha1.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static uint64_t
89 radv_get_visible_vram_size(struct radv_physical_device *device)
90 {
91 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
92 }
93
94 static uint64_t
95 radv_get_vram_size(struct radv_physical_device *device)
96 {
97 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
98 }
99
100 static void
101 radv_physical_device_init_mem_types(struct radv_physical_device *device)
102 {
103 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
104 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
105 uint64_t vram_size = radv_get_vram_size(device);
106 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
107 device->memory_properties.memoryHeapCount = 0;
108 if (vram_size > 0) {
109 vram_index = device->memory_properties.memoryHeapCount++;
110 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
111 .size = vram_size,
112 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
113 };
114 }
115 if (visible_vram_size) {
116 visible_vram_index = device->memory_properties.memoryHeapCount++;
117 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
118 .size = visible_vram_size,
119 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
120 };
121 }
122 if (device->rad_info.gart_size > 0) {
123 gart_index = device->memory_properties.memoryHeapCount++;
124 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
125 .size = device->rad_info.gart_size,
126 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
127 };
128 }
129
130 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
131 unsigned type_count = 0;
132 if (vram_index >= 0) {
133 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
134 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
135 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
136 .heapIndex = vram_index,
137 };
138 }
139 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
140 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
141 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
142 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
143 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
144 .heapIndex = gart_index,
145 };
146 }
147 if (visible_vram_index >= 0) {
148 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
149 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
150 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
151 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
152 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
153 .heapIndex = visible_vram_index,
154 };
155 }
156 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
157 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
158 * as they have identical property flags, and according to the
159 * spec, for types with identical flags, the one with greater
160 * performance must be given a lower index. */
161 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
162 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
163 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
164 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
165 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
166 .heapIndex = gart_index,
167 };
168 }
169 if (gart_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
173 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
174 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
175 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
176 .heapIndex = gart_index,
177 };
178 }
179 device->memory_properties.memoryTypeCount = type_count;
180 }
181
182 static void
183 radv_handle_env_var_force_family(struct radv_physical_device *device)
184 {
185 const char *family = getenv("RADV_FORCE_FAMILY");
186 unsigned i;
187
188 if (!family)
189 return;
190
191 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
192 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
193 /* Override family and chip_class. */
194 device->rad_info.family = i;
195
196 if (i >= CHIP_NAVI10)
197 device->rad_info.chip_class = GFX10;
198 else if (i >= CHIP_VEGA10)
199 device->rad_info.chip_class = GFX9;
200 else if (i >= CHIP_TONGA)
201 device->rad_info.chip_class = GFX8;
202 else if (i >= CHIP_BONAIRE)
203 device->rad_info.chip_class = GFX7;
204 else
205 device->rad_info.chip_class = GFX6;
206
207 return;
208 }
209 }
210
211 fprintf(stderr, "radv: Unknown family: %s\n", family);
212 exit(1);
213 }
214
215 static VkResult
216 radv_physical_device_init(struct radv_physical_device *device,
217 struct radv_instance *instance,
218 drmDevicePtr drm_device)
219 {
220 const char *path = drm_device->nodes[DRM_NODE_RENDER];
221 VkResult result;
222 drmVersionPtr version;
223 int fd;
224 int master_fd = -1;
225
226 fd = open(path, O_RDWR | O_CLOEXEC);
227 if (fd < 0) {
228 if (instance->debug_flags & RADV_DEBUG_STARTUP)
229 radv_logi("Could not open device '%s'", path);
230
231 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
232 }
233
234 version = drmGetVersion(fd);
235 if (!version) {
236 close(fd);
237
238 if (instance->debug_flags & RADV_DEBUG_STARTUP)
239 radv_logi("Could not get the kernel driver version for device '%s'", path);
240
241 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
242 "failed to get version %s: %m", path);
243 }
244
245 if (strcmp(version->name, "amdgpu")) {
246 drmFreeVersion(version);
247 close(fd);
248
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
251
252 return VK_ERROR_INCOMPATIBLE_DRIVER;
253 }
254 drmFreeVersion(version);
255
256 if (instance->debug_flags & RADV_DEBUG_STARTUP)
257 radv_logi("Found compatible device '%s'.", path);
258
259 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
260 device->instance = instance;
261
262 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
263 instance->perftest_flags);
264 if (!device->ws) {
265 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
266 goto fail;
267 }
268
269 if (instance->enabled_extensions.KHR_display) {
270 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
271 if (master_fd >= 0) {
272 uint32_t accel_working = 0;
273 struct drm_amdgpu_info request = {
274 .return_pointer = (uintptr_t)&accel_working,
275 .return_size = sizeof(accel_working),
276 .query = AMDGPU_INFO_ACCEL_WORKING
277 };
278
279 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
280 close(master_fd);
281 master_fd = -1;
282 }
283 }
284 }
285
286 device->master_fd = master_fd;
287 device->local_fd = fd;
288 device->ws->query_info(device->ws, &device->rad_info);
289
290 radv_handle_env_var_force_family(device);
291
292 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
293 if ((device->rad_info.chip_class < GFX8 ||
294 device->rad_info.chip_class > GFX9) && device->use_aco) {
295 fprintf(stderr, "WARNING: disabling ACO on unsupported GPUs.\n");
296 device->use_aco = false;
297 }
298
299 snprintf(device->name, sizeof(device->name),
300 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
301 device->rad_info.name);
302
303 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
304 device->ws->destroy(device->ws);
305 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
306 "cannot generate UUID");
307 goto fail;
308 }
309
310 /* These flags affect shader compilation. */
311 uint64_t shader_env_flags =
312 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
313 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0) |
314 (device->use_aco ? 0x4 : 0);
315
316 /* The gpu id is already embedded in the uuid so we just pass "radv"
317 * when creating the cache.
318 */
319 char buf[VK_UUID_SIZE * 2 + 1];
320 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
321 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
322
323 if (device->rad_info.chip_class < GFX8 ||
324 device->rad_info.chip_class > GFX9)
325 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
326
327 radv_get_driver_uuid(&device->driver_uuid);
328 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
329
330 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
331 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
332
333 device->dcc_msaa_allowed =
334 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
335
336 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
337 (device->use_aco || device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
338
339 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
340 device->rad_info.family != CHIP_NAVI14 &&
341 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
342 if (device->use_aco && device->use_ngg) {
343 fprintf(stderr, "WARNING: disabling NGG because ACO is used.\n");
344 device->use_ngg = false;
345 }
346
347 device->use_ngg_streamout = false;
348
349 /* Determine the number of threads per wave for all stages. */
350 device->cs_wave_size = 64;
351 device->ps_wave_size = 64;
352 device->ge_wave_size = 64;
353
354 if (device->rad_info.chip_class >= GFX10) {
355 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
356 device->cs_wave_size = 32;
357
358 /* For pixel shaders, wave64 is recommanded. */
359 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
360 device->ps_wave_size = 32;
361
362 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
363 device->ge_wave_size = 32;
364 }
365
366 radv_physical_device_init_mem_types(device);
367 radv_fill_device_extension_table(device, &device->supported_extensions);
368
369 device->bus_info = *drm_device->businfo.pci;
370
371 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
372 ac_print_gpu_info(&device->rad_info);
373
374 /* The WSI is structured as a layer on top of the driver, so this has
375 * to be the last part of initialization (at least until we get other
376 * semi-layers).
377 */
378 result = radv_init_wsi(device);
379 if (result != VK_SUCCESS) {
380 device->ws->destroy(device->ws);
381 vk_error(instance, result);
382 goto fail;
383 }
384
385 return VK_SUCCESS;
386
387 fail:
388 close(fd);
389 if (master_fd != -1)
390 close(master_fd);
391 return result;
392 }
393
394 static void
395 radv_physical_device_finish(struct radv_physical_device *device)
396 {
397 radv_finish_wsi(device);
398 device->ws->destroy(device->ws);
399 disk_cache_destroy(device->disk_cache);
400 close(device->local_fd);
401 if (device->master_fd != -1)
402 close(device->master_fd);
403 }
404
405 static void *
406 default_alloc_func(void *pUserData, size_t size, size_t align,
407 VkSystemAllocationScope allocationScope)
408 {
409 return malloc(size);
410 }
411
412 static void *
413 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
414 size_t align, VkSystemAllocationScope allocationScope)
415 {
416 return realloc(pOriginal, size);
417 }
418
419 static void
420 default_free_func(void *pUserData, void *pMemory)
421 {
422 free(pMemory);
423 }
424
425 static const VkAllocationCallbacks default_alloc = {
426 .pUserData = NULL,
427 .pfnAllocation = default_alloc_func,
428 .pfnReallocation = default_realloc_func,
429 .pfnFree = default_free_func,
430 };
431
432 static const struct debug_control radv_debug_options[] = {
433 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
434 {"nodcc", RADV_DEBUG_NO_DCC},
435 {"shaders", RADV_DEBUG_DUMP_SHADERS},
436 {"nocache", RADV_DEBUG_NO_CACHE},
437 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
438 {"nohiz", RADV_DEBUG_NO_HIZ},
439 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
440 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
441 {"allbos", RADV_DEBUG_ALL_BOS},
442 {"noibs", RADV_DEBUG_NO_IBS},
443 {"spirv", RADV_DEBUG_DUMP_SPIRV},
444 {"vmfaults", RADV_DEBUG_VM_FAULTS},
445 {"zerovram", RADV_DEBUG_ZERO_VRAM},
446 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
447 {"nosisched", RADV_DEBUG_NO_SISCHED},
448 {"preoptir", RADV_DEBUG_PREOPTIR},
449 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
450 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
451 {"info", RADV_DEBUG_INFO},
452 {"errors", RADV_DEBUG_ERRORS},
453 {"startup", RADV_DEBUG_STARTUP},
454 {"checkir", RADV_DEBUG_CHECKIR},
455 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
456 {"nobinning", RADV_DEBUG_NOBINNING},
457 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
458 {"nongg", RADV_DEBUG_NO_NGG},
459 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
460 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
461 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
462 {NULL, 0}
463 };
464
465 const char *
466 radv_get_debug_option_name(int id)
467 {
468 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
469 return radv_debug_options[id].string;
470 }
471
472 static const struct debug_control radv_perftest_options[] = {
473 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
474 {"sisched", RADV_PERFTEST_SISCHED},
475 {"localbos", RADV_PERFTEST_LOCAL_BOS},
476 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
477 {"bolist", RADV_PERFTEST_BO_LIST},
478 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
479 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
480 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
481 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
482 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
483 {"dfsm", RADV_PERFTEST_DFSM},
484 {"aco", RADV_PERFTEST_ACO},
485 {NULL, 0}
486 };
487
488 const char *
489 radv_get_perftest_option_name(int id)
490 {
491 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
492 return radv_perftest_options[id].string;
493 }
494
495 static void
496 radv_handle_per_app_options(struct radv_instance *instance,
497 const VkApplicationInfo *info)
498 {
499 const char *name = info ? info->pApplicationName : NULL;
500
501 if (!name)
502 return;
503
504 if (!strcmp(name, "Talos - Linux - 32bit") ||
505 !strcmp(name, "Talos - Linux - 64bit")) {
506 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
507 /* Force enable LLVM sisched for Talos because it looks
508 * safe and it gives few more FPS.
509 */
510 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
511 }
512 } else if (!strcmp(name, "DOOM_VFR")) {
513 /* Work around a Doom VFR game bug */
514 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
515 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
516 /* Workaround for a WaW hazard when LLVM moves/merges
517 * load/store memory operations.
518 * See https://reviews.llvm.org/D61313
519 */
520 if (LLVM_VERSION_MAJOR < 9)
521 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
522 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
523 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
524 /* Force enable VK_AMD_shader_ballot because it looks
525 * safe and it gives a nice boost (+20% on Vega 56 at
526 * this time).
527 */
528 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
529 }
530 } else if (!strcmp(name, "Fledge")) {
531 /*
532 * Zero VRAM for "The Surge 2"
533 *
534 * This avoid a hang when when rendering any level. Likely
535 * uninitialized data in an indirect draw.
536 */
537 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
538 }
539 }
540
541 static int radv_get_instance_extension_index(const char *name)
542 {
543 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
544 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
545 return i;
546 }
547 return -1;
548 }
549
550 static const char radv_dri_options_xml[] =
551 DRI_CONF_BEGIN
552 DRI_CONF_SECTION_PERFORMANCE
553 DRI_CONF_ADAPTIVE_SYNC("true")
554 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
555 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
556 DRI_CONF_SECTION_END
557 DRI_CONF_END;
558
559 static void radv_init_dri_options(struct radv_instance *instance)
560 {
561 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
562 driParseConfigFiles(&instance->dri_options,
563 &instance->available_dri_options,
564 0, "radv", NULL,
565 instance->engineName,
566 instance->engineVersion);
567 }
568
569 VkResult radv_CreateInstance(
570 const VkInstanceCreateInfo* pCreateInfo,
571 const VkAllocationCallbacks* pAllocator,
572 VkInstance* pInstance)
573 {
574 struct radv_instance *instance;
575 VkResult result;
576
577 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
578
579 uint32_t client_version;
580 if (pCreateInfo->pApplicationInfo &&
581 pCreateInfo->pApplicationInfo->apiVersion != 0) {
582 client_version = pCreateInfo->pApplicationInfo->apiVersion;
583 } else {
584 client_version = VK_API_VERSION_1_0;
585 }
586
587 const char *engine_name = NULL;
588 uint32_t engine_version = 0;
589 if (pCreateInfo->pApplicationInfo) {
590 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
591 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
592 }
593
594 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
595 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
596 if (!instance)
597 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
598
599 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
600
601 if (pAllocator)
602 instance->alloc = *pAllocator;
603 else
604 instance->alloc = default_alloc;
605
606 instance->apiVersion = client_version;
607 instance->physicalDeviceCount = -1;
608
609 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
610 radv_debug_options);
611
612 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
613 radv_perftest_options);
614
615 if (instance->perftest_flags & RADV_PERFTEST_ACO)
616 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
617
618 if (instance->debug_flags & RADV_DEBUG_STARTUP)
619 radv_logi("Created an instance");
620
621 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
622 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
623 int index = radv_get_instance_extension_index(ext_name);
624
625 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
626 vk_free2(&default_alloc, pAllocator, instance);
627 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
628 }
629
630 instance->enabled_extensions.extensions[index] = true;
631 }
632
633 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
634 if (result != VK_SUCCESS) {
635 vk_free2(&default_alloc, pAllocator, instance);
636 return vk_error(instance, result);
637 }
638
639 instance->engineName = vk_strdup(&instance->alloc, engine_name,
640 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
641 instance->engineVersion = engine_version;
642
643 _mesa_locale_init();
644 glsl_type_singleton_init_or_ref();
645
646 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
647
648 radv_init_dri_options(instance);
649 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
650
651 *pInstance = radv_instance_to_handle(instance);
652
653 return VK_SUCCESS;
654 }
655
656 void radv_DestroyInstance(
657 VkInstance _instance,
658 const VkAllocationCallbacks* pAllocator)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661
662 if (!instance)
663 return;
664
665 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
666 radv_physical_device_finish(instance->physicalDevices + i);
667 }
668
669 vk_free(&instance->alloc, instance->engineName);
670
671 VG(VALGRIND_DESTROY_MEMPOOL(instance));
672
673 glsl_type_singleton_decref();
674 _mesa_locale_fini();
675
676 driDestroyOptionCache(&instance->dri_options);
677 driDestroyOptionInfo(&instance->available_dri_options);
678
679 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
680
681 vk_free(&instance->alloc, instance);
682 }
683
684 static VkResult
685 radv_enumerate_devices(struct radv_instance *instance)
686 {
687 /* TODO: Check for more devices ? */
688 drmDevicePtr devices[8];
689 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
690 int max_devices;
691
692 instance->physicalDeviceCount = 0;
693
694 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
695
696 if (instance->debug_flags & RADV_DEBUG_STARTUP)
697 radv_logi("Found %d drm nodes", max_devices);
698
699 if (max_devices < 1)
700 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
701
702 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
703 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
704 devices[i]->bustype == DRM_BUS_PCI &&
705 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
706
707 result = radv_physical_device_init(instance->physicalDevices +
708 instance->physicalDeviceCount,
709 instance,
710 devices[i]);
711 if (result == VK_SUCCESS)
712 ++instance->physicalDeviceCount;
713 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
714 break;
715 }
716 }
717 drmFreeDevices(devices, max_devices);
718
719 return result;
720 }
721
722 VkResult radv_EnumeratePhysicalDevices(
723 VkInstance _instance,
724 uint32_t* pPhysicalDeviceCount,
725 VkPhysicalDevice* pPhysicalDevices)
726 {
727 RADV_FROM_HANDLE(radv_instance, instance, _instance);
728 VkResult result;
729
730 if (instance->physicalDeviceCount < 0) {
731 result = radv_enumerate_devices(instance);
732 if (result != VK_SUCCESS &&
733 result != VK_ERROR_INCOMPATIBLE_DRIVER)
734 return result;
735 }
736
737 if (!pPhysicalDevices) {
738 *pPhysicalDeviceCount = instance->physicalDeviceCount;
739 } else {
740 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
741 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
742 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
743 }
744
745 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
746 : VK_SUCCESS;
747 }
748
749 VkResult radv_EnumeratePhysicalDeviceGroups(
750 VkInstance _instance,
751 uint32_t* pPhysicalDeviceGroupCount,
752 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
753 {
754 RADV_FROM_HANDLE(radv_instance, instance, _instance);
755 VkResult result;
756
757 if (instance->physicalDeviceCount < 0) {
758 result = radv_enumerate_devices(instance);
759 if (result != VK_SUCCESS &&
760 result != VK_ERROR_INCOMPATIBLE_DRIVER)
761 return result;
762 }
763
764 if (!pPhysicalDeviceGroupProperties) {
765 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
766 } else {
767 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
768 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
769 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
770 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
771 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
772 }
773 }
774 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
775 : VK_SUCCESS;
776 }
777
778 void radv_GetPhysicalDeviceFeatures(
779 VkPhysicalDevice physicalDevice,
780 VkPhysicalDeviceFeatures* pFeatures)
781 {
782 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
783 memset(pFeatures, 0, sizeof(*pFeatures));
784
785 *pFeatures = (VkPhysicalDeviceFeatures) {
786 .robustBufferAccess = true,
787 .fullDrawIndexUint32 = true,
788 .imageCubeArray = true,
789 .independentBlend = true,
790 .geometryShader = true,
791 .tessellationShader = true,
792 .sampleRateShading = true,
793 .dualSrcBlend = true,
794 .logicOp = true,
795 .multiDrawIndirect = true,
796 .drawIndirectFirstInstance = true,
797 .depthClamp = true,
798 .depthBiasClamp = true,
799 .fillModeNonSolid = true,
800 .depthBounds = true,
801 .wideLines = true,
802 .largePoints = true,
803 .alphaToOne = true,
804 .multiViewport = true,
805 .samplerAnisotropy = true,
806 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
807 .textureCompressionASTC_LDR = false,
808 .textureCompressionBC = true,
809 .occlusionQueryPrecise = true,
810 .pipelineStatisticsQuery = true,
811 .vertexPipelineStoresAndAtomics = true,
812 .fragmentStoresAndAtomics = true,
813 .shaderTessellationAndGeometryPointSize = true,
814 .shaderImageGatherExtended = true,
815 .shaderStorageImageExtendedFormats = true,
816 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
817 .shaderUniformBufferArrayDynamicIndexing = true,
818 .shaderSampledImageArrayDynamicIndexing = true,
819 .shaderStorageBufferArrayDynamicIndexing = true,
820 .shaderStorageImageArrayDynamicIndexing = true,
821 .shaderStorageImageReadWithoutFormat = true,
822 .shaderStorageImageWriteWithoutFormat = true,
823 .shaderClipDistance = true,
824 .shaderCullDistance = true,
825 .shaderFloat64 = true,
826 .shaderInt64 = true,
827 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
828 .sparseBinding = true,
829 .variableMultisampleRate = true,
830 .inheritedQueries = true,
831 };
832 }
833
834 void radv_GetPhysicalDeviceFeatures2(
835 VkPhysicalDevice physicalDevice,
836 VkPhysicalDeviceFeatures2 *pFeatures)
837 {
838 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
839 vk_foreach_struct(ext, pFeatures->pNext) {
840 switch (ext->sType) {
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
842 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
843 features->variablePointersStorageBuffer = true;
844 features->variablePointers = true;
845 break;
846 }
847 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
848 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
849 features->multiview = true;
850 features->multiviewGeometryShader = true;
851 features->multiviewTessellationShader = true;
852 break;
853 }
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
855 VkPhysicalDeviceShaderDrawParametersFeatures *features =
856 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
857 features->shaderDrawParameters = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
861 VkPhysicalDeviceProtectedMemoryFeatures *features =
862 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
863 features->protectedMemory = false;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
867 VkPhysicalDevice16BitStorageFeatures *features =
868 (VkPhysicalDevice16BitStorageFeatures*)ext;
869 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
870 features->storageBuffer16BitAccess = enabled;
871 features->uniformAndStorageBuffer16BitAccess = enabled;
872 features->storagePushConstant16 = enabled;
873 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
877 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
878 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
879 features->samplerYcbcrConversion = true;
880 break;
881 }
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
883 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
884 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
885 features->shaderInputAttachmentArrayDynamicIndexing = true;
886 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
887 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
888 features->shaderUniformBufferArrayNonUniformIndexing = true;
889 features->shaderSampledImageArrayNonUniformIndexing = true;
890 features->shaderStorageBufferArrayNonUniformIndexing = true;
891 features->shaderStorageImageArrayNonUniformIndexing = true;
892 features->shaderInputAttachmentArrayNonUniformIndexing = true;
893 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
894 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
895 features->descriptorBindingUniformBufferUpdateAfterBind = true;
896 features->descriptorBindingSampledImageUpdateAfterBind = true;
897 features->descriptorBindingStorageImageUpdateAfterBind = true;
898 features->descriptorBindingStorageBufferUpdateAfterBind = true;
899 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
900 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
901 features->descriptorBindingUpdateUnusedWhilePending = true;
902 features->descriptorBindingPartiallyBound = true;
903 features->descriptorBindingVariableDescriptorCount = true;
904 features->runtimeDescriptorArray = true;
905 break;
906 }
907 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
908 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
909 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
910 features->conditionalRendering = true;
911 features->inheritedConditionalRendering = false;
912 break;
913 }
914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
915 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
916 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
917 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
918 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
919 break;
920 }
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
922 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
923 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
924 features->transformFeedback = true;
925 features->geometryStreams = !pdevice->use_ngg_streamout;
926 break;
927 }
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
929 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
930 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
931 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
932 break;
933 }
934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
935 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
936 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
937 features->memoryPriority = VK_TRUE;
938 break;
939 }
940 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
941 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
942 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
943 features->bufferDeviceAddress = true;
944 features->bufferDeviceAddressCaptureReplay = false;
945 features->bufferDeviceAddressMultiDevice = false;
946 break;
947 }
948 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
949 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
950 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
951 features->depthClipEnable = true;
952 break;
953 }
954 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
955 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
956 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
957 features->hostQueryReset = true;
958 break;
959 }
960 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
961 VkPhysicalDevice8BitStorageFeaturesKHR *features =
962 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
963 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
964 features->storageBuffer8BitAccess = enabled;
965 features->uniformAndStorageBuffer8BitAccess = enabled;
966 features->storagePushConstant8 = enabled;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES_KHR: {
970 VkPhysicalDeviceShaderFloat16Int8FeaturesKHR *features =
971 (VkPhysicalDeviceShaderFloat16Int8FeaturesKHR*)ext;
972 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
973 features->shaderInt8 = !pdevice->use_aco;
974 break;
975 }
976 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
977 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
978 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
979 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
980 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
981 break;
982 }
983 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
984 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
985 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
986 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
987 break;
988 }
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
990 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
991 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
992
993 features->inlineUniformBlock = true;
994 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
995 break;
996 }
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
998 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
999 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1000 features->computeDerivativeGroupQuads = false;
1001 features->computeDerivativeGroupLinear = true;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1005 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1006 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1007 features->ycbcrImageArrays = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1011 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1012 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1013 features->uniformBufferStandardLayout = true;
1014 break;
1015 }
1016 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1017 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1018 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1019 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1020 break;
1021 }
1022 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1023 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1024 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1025 features->imagelessFramebuffer = true;
1026 break;
1027 }
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1029 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1030 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1031 features->pipelineExecutableInfo = true;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1035 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1036 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1037 features->shaderSubgroupClock = true;
1038 features->shaderDeviceClock = false;
1039 break;
1040 }
1041 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1042 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1043 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1044 features->texelBufferAlignment = true;
1045 break;
1046 }
1047 default:
1048 break;
1049 }
1050 }
1051 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1052 }
1053
1054 void radv_GetPhysicalDeviceProperties(
1055 VkPhysicalDevice physicalDevice,
1056 VkPhysicalDeviceProperties* pProperties)
1057 {
1058 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1059 VkSampleCountFlags sample_counts = 0xf;
1060
1061 /* make sure that the entire descriptor set is addressable with a signed
1062 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1063 * be at most 2 GiB. the combined image & samples object count as one of
1064 * both. This limit is for the pipeline layout, not for the set layout, but
1065 * there is no set limit, so we just set a pipeline limit. I don't think
1066 * any app is going to hit this soon. */
1067 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1068 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1069 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1070 32 /* sampler, largest when combined with image */ +
1071 64 /* sampled image */ +
1072 64 /* storage image */);
1073
1074 VkPhysicalDeviceLimits limits = {
1075 .maxImageDimension1D = (1 << 14),
1076 .maxImageDimension2D = (1 << 14),
1077 .maxImageDimension3D = (1 << 11),
1078 .maxImageDimensionCube = (1 << 14),
1079 .maxImageArrayLayers = (1 << 11),
1080 .maxTexelBufferElements = 128 * 1024 * 1024,
1081 .maxUniformBufferRange = UINT32_MAX,
1082 .maxStorageBufferRange = UINT32_MAX,
1083 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1084 .maxMemoryAllocationCount = UINT32_MAX,
1085 .maxSamplerAllocationCount = 64 * 1024,
1086 .bufferImageGranularity = 64, /* A cache line */
1087 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1088 .maxBoundDescriptorSets = MAX_SETS,
1089 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1090 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1091 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1092 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1093 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1094 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1095 .maxPerStageResources = max_descriptor_set_size,
1096 .maxDescriptorSetSamplers = max_descriptor_set_size,
1097 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1098 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1099 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1100 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1101 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1102 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1103 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1104 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1105 .maxVertexInputBindings = MAX_VBS,
1106 .maxVertexInputAttributeOffset = 2047,
1107 .maxVertexInputBindingStride = 2048,
1108 .maxVertexOutputComponents = 128,
1109 .maxTessellationGenerationLevel = 64,
1110 .maxTessellationPatchSize = 32,
1111 .maxTessellationControlPerVertexInputComponents = 128,
1112 .maxTessellationControlPerVertexOutputComponents = 128,
1113 .maxTessellationControlPerPatchOutputComponents = 120,
1114 .maxTessellationControlTotalOutputComponents = 4096,
1115 .maxTessellationEvaluationInputComponents = 128,
1116 .maxTessellationEvaluationOutputComponents = 128,
1117 .maxGeometryShaderInvocations = 127,
1118 .maxGeometryInputComponents = 64,
1119 .maxGeometryOutputComponents = 128,
1120 .maxGeometryOutputVertices = 256,
1121 .maxGeometryTotalOutputComponents = 1024,
1122 .maxFragmentInputComponents = 128,
1123 .maxFragmentOutputAttachments = 8,
1124 .maxFragmentDualSrcAttachments = 1,
1125 .maxFragmentCombinedOutputResources = 8,
1126 .maxComputeSharedMemorySize = 32768,
1127 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1128 .maxComputeWorkGroupInvocations = 2048,
1129 .maxComputeWorkGroupSize = {
1130 2048,
1131 2048,
1132 2048
1133 },
1134 .subPixelPrecisionBits = 8,
1135 .subTexelPrecisionBits = 8,
1136 .mipmapPrecisionBits = 8,
1137 .maxDrawIndexedIndexValue = UINT32_MAX,
1138 .maxDrawIndirectCount = UINT32_MAX,
1139 .maxSamplerLodBias = 16,
1140 .maxSamplerAnisotropy = 16,
1141 .maxViewports = MAX_VIEWPORTS,
1142 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1143 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1144 .viewportSubPixelBits = 8,
1145 .minMemoryMapAlignment = 4096, /* A page */
1146 .minTexelBufferOffsetAlignment = 4,
1147 .minUniformBufferOffsetAlignment = 4,
1148 .minStorageBufferOffsetAlignment = 4,
1149 .minTexelOffset = -32,
1150 .maxTexelOffset = 31,
1151 .minTexelGatherOffset = -32,
1152 .maxTexelGatherOffset = 31,
1153 .minInterpolationOffset = -2,
1154 .maxInterpolationOffset = 2,
1155 .subPixelInterpolationOffsetBits = 8,
1156 .maxFramebufferWidth = (1 << 14),
1157 .maxFramebufferHeight = (1 << 14),
1158 .maxFramebufferLayers = (1 << 10),
1159 .framebufferColorSampleCounts = sample_counts,
1160 .framebufferDepthSampleCounts = sample_counts,
1161 .framebufferStencilSampleCounts = sample_counts,
1162 .framebufferNoAttachmentsSampleCounts = sample_counts,
1163 .maxColorAttachments = MAX_RTS,
1164 .sampledImageColorSampleCounts = sample_counts,
1165 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1166 .sampledImageDepthSampleCounts = sample_counts,
1167 .sampledImageStencilSampleCounts = sample_counts,
1168 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1169 .maxSampleMaskWords = 1,
1170 .timestampComputeAndGraphics = true,
1171 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1172 .maxClipDistances = 8,
1173 .maxCullDistances = 8,
1174 .maxCombinedClipAndCullDistances = 8,
1175 .discreteQueuePriorities = 2,
1176 .pointSizeRange = { 0.0, 8192.0 },
1177 .lineWidthRange = { 0.0, 7.9921875 },
1178 .pointSizeGranularity = (1.0 / 8.0),
1179 .lineWidthGranularity = (1.0 / 128.0),
1180 .strictLines = false, /* FINISHME */
1181 .standardSampleLocations = true,
1182 .optimalBufferCopyOffsetAlignment = 128,
1183 .optimalBufferCopyRowPitchAlignment = 128,
1184 .nonCoherentAtomSize = 64,
1185 };
1186
1187 *pProperties = (VkPhysicalDeviceProperties) {
1188 .apiVersion = radv_physical_device_api_version(pdevice),
1189 .driverVersion = vk_get_driver_version(),
1190 .vendorID = ATI_VENDOR_ID,
1191 .deviceID = pdevice->rad_info.pci_id,
1192 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1193 .limits = limits,
1194 .sparseProperties = {0},
1195 };
1196
1197 strcpy(pProperties->deviceName, pdevice->name);
1198 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1199 }
1200
1201 void radv_GetPhysicalDeviceProperties2(
1202 VkPhysicalDevice physicalDevice,
1203 VkPhysicalDeviceProperties2 *pProperties)
1204 {
1205 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1206 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1207
1208 vk_foreach_struct(ext, pProperties->pNext) {
1209 switch (ext->sType) {
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1211 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1212 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1213 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1214 break;
1215 }
1216 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1217 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1218 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1219 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1220 properties->deviceLUIDValid = false;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1224 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1225 properties->maxMultiviewViewCount = MAX_VIEWS;
1226 properties->maxMultiviewInstanceIndex = INT_MAX;
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1230 VkPhysicalDevicePointClippingProperties *properties =
1231 (VkPhysicalDevicePointClippingProperties*)ext;
1232 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1236 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1237 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1238 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1239 break;
1240 }
1241 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1242 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1243 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1244 properties->minImportedHostPointerAlignment = 4096;
1245 break;
1246 }
1247 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1248 VkPhysicalDeviceSubgroupProperties *properties =
1249 (VkPhysicalDeviceSubgroupProperties*)ext;
1250 properties->subgroupSize = 64;
1251 properties->supportedStages = VK_SHADER_STAGE_ALL;
1252 properties->supportedOperations =
1253 VK_SUBGROUP_FEATURE_BASIC_BIT |
1254 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1255 VK_SUBGROUP_FEATURE_QUAD_BIT |
1256 VK_SUBGROUP_FEATURE_VOTE_BIT;
1257 if (pdevice->rad_info.chip_class >= GFX8) {
1258 properties->supportedOperations |=
1259 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1260 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1261 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1262 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1263 }
1264 properties->quadOperationsInAllStages = true;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1268 VkPhysicalDeviceMaintenance3Properties *properties =
1269 (VkPhysicalDeviceMaintenance3Properties*)ext;
1270 /* Make sure everything is addressable by a signed 32-bit int, and
1271 * our largest descriptors are 96 bytes. */
1272 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1273 /* Our buffer size fields allow only this much */
1274 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1278 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1279 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1280 /* GFX6-8 only support single channel min/max filter. */
1281 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1282 properties->filterMinmaxSingleComponentFormats = true;
1283 break;
1284 }
1285 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1286 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1287 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1288
1289 /* Shader engines. */
1290 properties->shaderEngineCount =
1291 pdevice->rad_info.max_se;
1292 properties->shaderArraysPerEngineCount =
1293 pdevice->rad_info.max_sh_per_se;
1294 properties->computeUnitsPerShaderArray =
1295 pdevice->rad_info.num_good_cu_per_sh;
1296 properties->simdPerComputeUnit = 4;
1297 properties->wavefrontsPerSimd =
1298 pdevice->rad_info.family == CHIP_TONGA ||
1299 pdevice->rad_info.family == CHIP_ICELAND ||
1300 pdevice->rad_info.family == CHIP_POLARIS10 ||
1301 pdevice->rad_info.family == CHIP_POLARIS11 ||
1302 pdevice->rad_info.family == CHIP_POLARIS12 ||
1303 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1304 properties->wavefrontSize = 64;
1305
1306 /* SGPR. */
1307 properties->sgprsPerSimd =
1308 pdevice->rad_info.num_physical_sgprs_per_simd;
1309 properties->minSgprAllocation =
1310 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1311 properties->maxSgprAllocation =
1312 pdevice->rad_info.family == CHIP_TONGA ||
1313 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1314 properties->sgprAllocationGranularity =
1315 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1316
1317 /* VGPR. */
1318 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1319 properties->minVgprAllocation = 4;
1320 properties->maxVgprAllocation = 256;
1321 properties->vgprAllocationGranularity = 4;
1322 break;
1323 }
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1325 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1326 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1327
1328 properties->shaderCoreFeatures = 0;
1329 properties->activeComputeUnitCount =
1330 pdevice->rad_info.num_good_compute_units;
1331 break;
1332 }
1333 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1334 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1335 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1336 properties->maxVertexAttribDivisor = UINT32_MAX;
1337 break;
1338 }
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1340 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1341 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1342 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1343 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1344 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1345 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1346 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1347 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1348 properties->robustBufferAccessUpdateAfterBind = false;
1349 properties->quadDivergentImplicitLod = false;
1350
1351 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1352 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1353 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1354 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1355 32 /* sampler, largest when combined with image */ +
1356 64 /* sampled image */ +
1357 64 /* storage image */);
1358 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1359 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1360 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1361 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1362 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1363 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1364 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1365 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1366 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1367 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1368 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1369 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1370 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1371 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1372 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1373 break;
1374 }
1375 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1376 VkPhysicalDeviceProtectedMemoryProperties *properties =
1377 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1378 properties->protectedNoFault = false;
1379 break;
1380 }
1381 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1382 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1383 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1384 properties->primitiveOverestimationSize = 0;
1385 properties->maxExtraPrimitiveOverestimationSize = 0;
1386 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1387 properties->primitiveUnderestimation = VK_FALSE;
1388 properties->conservativePointAndLineRasterization = VK_FALSE;
1389 properties->degenerateTrianglesRasterized = VK_FALSE;
1390 properties->degenerateLinesRasterized = VK_FALSE;
1391 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1392 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1393 break;
1394 }
1395 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1396 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1397 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1398 properties->pciDomain = pdevice->bus_info.domain;
1399 properties->pciBus = pdevice->bus_info.bus;
1400 properties->pciDevice = pdevice->bus_info.dev;
1401 properties->pciFunction = pdevice->bus_info.func;
1402 break;
1403 }
1404 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1405 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1406 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1407
1408 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1409 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1410 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1411 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1412 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1413
1414 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1415 .major = 1,
1416 .minor = 1,
1417 .subminor = 2,
1418 .patch = 0,
1419 };
1420 break;
1421 }
1422 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1423 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1424 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1425 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1426 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1427 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1428 properties->maxTransformFeedbackStreamDataSize = 512;
1429 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1430 properties->maxTransformFeedbackBufferDataStride = 512;
1431 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1432 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1433 properties->transformFeedbackRasterizationStreamSelect = false;
1434 properties->transformFeedbackDraw = true;
1435 break;
1436 }
1437 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1438 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1439 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1440
1441 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1442 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1443 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1444 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1445 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1446 break;
1447 }
1448 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1449 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1450 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1451 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1452 VK_SAMPLE_COUNT_4_BIT |
1453 VK_SAMPLE_COUNT_8_BIT;
1454 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1455 properties->sampleLocationCoordinateRange[0] = 0.0f;
1456 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1457 properties->sampleLocationSubPixelBits = 4;
1458 properties->variableSampleLocations = VK_FALSE;
1459 break;
1460 }
1461 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1462 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1463 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1464
1465 /* We support all of the depth resolve modes */
1466 properties->supportedDepthResolveModes =
1467 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1468 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1469 VK_RESOLVE_MODE_MIN_BIT_KHR |
1470 VK_RESOLVE_MODE_MAX_BIT_KHR;
1471
1472 /* Average doesn't make sense for stencil so we don't support that */
1473 properties->supportedStencilResolveModes =
1474 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1475 VK_RESOLVE_MODE_MIN_BIT_KHR |
1476 VK_RESOLVE_MODE_MAX_BIT_KHR;
1477
1478 properties->independentResolveNone = VK_TRUE;
1479 properties->independentResolve = VK_TRUE;
1480 break;
1481 }
1482 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1483 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1484 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1485 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1486 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1487 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1488 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1489 break;
1490 }
1491 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR : {
1492 VkPhysicalDeviceFloatControlsPropertiesKHR *properties =
1493 (VkPhysicalDeviceFloatControlsPropertiesKHR *)ext;
1494
1495 /* On AMD hardware, denormals and rounding modes for
1496 * fp16/fp64 are controlled by the same config
1497 * register.
1498 */
1499 properties->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1500 properties->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1501
1502 /* Do not allow both preserving and flushing denorms
1503 * because different shaders in the same pipeline can
1504 * have different settings and this won't work for
1505 * merged shaders. To make it work, this requires LLVM
1506 * support for changing the register. The same logic
1507 * applies for the rounding modes because they are
1508 * configured with the same config register.
1509 */
1510 properties->shaderDenormFlushToZeroFloat32 = true;
1511 properties->shaderDenormPreserveFloat32 = false;
1512 properties->shaderRoundingModeRTEFloat32 = true;
1513 properties->shaderRoundingModeRTZFloat32 = false;
1514 properties->shaderSignedZeroInfNanPreserveFloat32 = true;
1515
1516 properties->shaderDenormFlushToZeroFloat16 = false;
1517 properties->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1518 properties->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
1519 properties->shaderRoundingModeRTZFloat16 = false;
1520 properties->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1521
1522 properties->shaderDenormFlushToZeroFloat64 = false;
1523 properties->shaderDenormPreserveFloat64 = true;
1524 properties->shaderRoundingModeRTEFloat64 = true;
1525 properties->shaderRoundingModeRTZFloat64 = false;
1526 properties->shaderSignedZeroInfNanPreserveFloat64 = true;
1527 break;
1528 }
1529 default:
1530 break;
1531 }
1532 }
1533 }
1534
1535 static void radv_get_physical_device_queue_family_properties(
1536 struct radv_physical_device* pdevice,
1537 uint32_t* pCount,
1538 VkQueueFamilyProperties** pQueueFamilyProperties)
1539 {
1540 int num_queue_families = 1;
1541 int idx;
1542 if (pdevice->rad_info.num_compute_rings > 0 &&
1543 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1544 num_queue_families++;
1545
1546 if (pQueueFamilyProperties == NULL) {
1547 *pCount = num_queue_families;
1548 return;
1549 }
1550
1551 if (!*pCount)
1552 return;
1553
1554 idx = 0;
1555 if (*pCount >= 1) {
1556 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1557 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1558 VK_QUEUE_COMPUTE_BIT |
1559 VK_QUEUE_TRANSFER_BIT |
1560 VK_QUEUE_SPARSE_BINDING_BIT,
1561 .queueCount = 1,
1562 .timestampValidBits = 64,
1563 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1564 };
1565 idx++;
1566 }
1567
1568 if (pdevice->rad_info.num_compute_rings > 0 &&
1569 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1570 if (*pCount > idx) {
1571 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1572 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1573 VK_QUEUE_TRANSFER_BIT |
1574 VK_QUEUE_SPARSE_BINDING_BIT,
1575 .queueCount = pdevice->rad_info.num_compute_rings,
1576 .timestampValidBits = 64,
1577 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1578 };
1579 idx++;
1580 }
1581 }
1582 *pCount = idx;
1583 }
1584
1585 void radv_GetPhysicalDeviceQueueFamilyProperties(
1586 VkPhysicalDevice physicalDevice,
1587 uint32_t* pCount,
1588 VkQueueFamilyProperties* pQueueFamilyProperties)
1589 {
1590 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1591 if (!pQueueFamilyProperties) {
1592 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1593 return;
1594 }
1595 VkQueueFamilyProperties *properties[] = {
1596 pQueueFamilyProperties + 0,
1597 pQueueFamilyProperties + 1,
1598 pQueueFamilyProperties + 2,
1599 };
1600 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1601 assert(*pCount <= 3);
1602 }
1603
1604 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1605 VkPhysicalDevice physicalDevice,
1606 uint32_t* pCount,
1607 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1608 {
1609 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1610 if (!pQueueFamilyProperties) {
1611 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1612 return;
1613 }
1614 VkQueueFamilyProperties *properties[] = {
1615 &pQueueFamilyProperties[0].queueFamilyProperties,
1616 &pQueueFamilyProperties[1].queueFamilyProperties,
1617 &pQueueFamilyProperties[2].queueFamilyProperties,
1618 };
1619 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1620 assert(*pCount <= 3);
1621 }
1622
1623 void radv_GetPhysicalDeviceMemoryProperties(
1624 VkPhysicalDevice physicalDevice,
1625 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1626 {
1627 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1628
1629 *pMemoryProperties = physical_device->memory_properties;
1630 }
1631
1632 static void
1633 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1634 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1635 {
1636 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1637 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1638 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1639 uint64_t vram_size = radv_get_vram_size(device);
1640 uint64_t gtt_size = device->rad_info.gart_size;
1641 uint64_t heap_budget, heap_usage;
1642
1643 /* For all memory heaps, the computation of budget is as follow:
1644 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1645 *
1646 * The Vulkan spec 1.1.97 says that the budget should include any
1647 * currently allocated device memory.
1648 *
1649 * Note that the application heap usages are not really accurate (eg.
1650 * in presence of shared buffers).
1651 */
1652 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1653 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1654
1655 switch (device->mem_type_indices[i]) {
1656 case RADV_MEM_TYPE_VRAM:
1657 heap_usage = device->ws->query_value(device->ws,
1658 RADEON_ALLOCATED_VRAM);
1659
1660 heap_budget = vram_size -
1661 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1662 heap_usage;
1663
1664 memoryBudget->heapBudget[heap_index] = heap_budget;
1665 memoryBudget->heapUsage[heap_index] = heap_usage;
1666 break;
1667 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1668 heap_usage = device->ws->query_value(device->ws,
1669 RADEON_ALLOCATED_VRAM_VIS);
1670
1671 heap_budget = visible_vram_size -
1672 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1673 heap_usage;
1674
1675 memoryBudget->heapBudget[heap_index] = heap_budget;
1676 memoryBudget->heapUsage[heap_index] = heap_usage;
1677 break;
1678 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1679 heap_usage = device->ws->query_value(device->ws,
1680 RADEON_ALLOCATED_GTT);
1681
1682 heap_budget = gtt_size -
1683 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1684 heap_usage;
1685
1686 memoryBudget->heapBudget[heap_index] = heap_budget;
1687 memoryBudget->heapUsage[heap_index] = heap_usage;
1688 break;
1689 default:
1690 break;
1691 }
1692 }
1693
1694 /* The heapBudget and heapUsage values must be zero for array elements
1695 * greater than or equal to
1696 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1697 */
1698 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1699 memoryBudget->heapBudget[i] = 0;
1700 memoryBudget->heapUsage[i] = 0;
1701 }
1702 }
1703
1704 void radv_GetPhysicalDeviceMemoryProperties2(
1705 VkPhysicalDevice physicalDevice,
1706 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1707 {
1708 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1709 &pMemoryProperties->memoryProperties);
1710
1711 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1712 vk_find_struct(pMemoryProperties->pNext,
1713 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1714 if (memory_budget)
1715 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1716 }
1717
1718 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1719 VkDevice _device,
1720 VkExternalMemoryHandleTypeFlagBits handleType,
1721 const void *pHostPointer,
1722 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1723 {
1724 RADV_FROM_HANDLE(radv_device, device, _device);
1725
1726 switch (handleType)
1727 {
1728 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1729 const struct radv_physical_device *physical_device = device->physical_device;
1730 uint32_t memoryTypeBits = 0;
1731 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1732 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1733 memoryTypeBits = (1 << i);
1734 break;
1735 }
1736 }
1737 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1738 return VK_SUCCESS;
1739 }
1740 default:
1741 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1742 }
1743 }
1744
1745 static enum radeon_ctx_priority
1746 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1747 {
1748 /* Default to MEDIUM when a specific global priority isn't requested */
1749 if (!pObj)
1750 return RADEON_CTX_PRIORITY_MEDIUM;
1751
1752 switch(pObj->globalPriority) {
1753 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1754 return RADEON_CTX_PRIORITY_REALTIME;
1755 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1756 return RADEON_CTX_PRIORITY_HIGH;
1757 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1758 return RADEON_CTX_PRIORITY_MEDIUM;
1759 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1760 return RADEON_CTX_PRIORITY_LOW;
1761 default:
1762 unreachable("Illegal global priority value");
1763 return RADEON_CTX_PRIORITY_INVALID;
1764 }
1765 }
1766
1767 static int
1768 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1769 uint32_t queue_family_index, int idx,
1770 VkDeviceQueueCreateFlags flags,
1771 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1772 {
1773 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1774 queue->device = device;
1775 queue->queue_family_index = queue_family_index;
1776 queue->queue_idx = idx;
1777 queue->priority = radv_get_queue_global_priority(global_priority);
1778 queue->flags = flags;
1779
1780 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1781 if (!queue->hw_ctx)
1782 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1783
1784 return VK_SUCCESS;
1785 }
1786
1787 static void
1788 radv_queue_finish(struct radv_queue *queue)
1789 {
1790 if (queue->hw_ctx)
1791 queue->device->ws->ctx_destroy(queue->hw_ctx);
1792
1793 if (queue->initial_full_flush_preamble_cs)
1794 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1795 if (queue->initial_preamble_cs)
1796 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1797 if (queue->continue_preamble_cs)
1798 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1799 if (queue->descriptor_bo)
1800 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1801 if (queue->scratch_bo)
1802 queue->device->ws->buffer_destroy(queue->scratch_bo);
1803 if (queue->esgs_ring_bo)
1804 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1805 if (queue->gsvs_ring_bo)
1806 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1807 if (queue->tess_rings_bo)
1808 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1809 if (queue->gds_bo)
1810 queue->device->ws->buffer_destroy(queue->gds_bo);
1811 if (queue->gds_oa_bo)
1812 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1813 if (queue->compute_scratch_bo)
1814 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1815 }
1816
1817 static void
1818 radv_bo_list_init(struct radv_bo_list *bo_list)
1819 {
1820 pthread_mutex_init(&bo_list->mutex, NULL);
1821 bo_list->list.count = bo_list->capacity = 0;
1822 bo_list->list.bos = NULL;
1823 }
1824
1825 static void
1826 radv_bo_list_finish(struct radv_bo_list *bo_list)
1827 {
1828 free(bo_list->list.bos);
1829 pthread_mutex_destroy(&bo_list->mutex);
1830 }
1831
1832 static VkResult radv_bo_list_add(struct radv_device *device,
1833 struct radeon_winsys_bo *bo)
1834 {
1835 struct radv_bo_list *bo_list = &device->bo_list;
1836
1837 if (bo->is_local)
1838 return VK_SUCCESS;
1839
1840 if (unlikely(!device->use_global_bo_list))
1841 return VK_SUCCESS;
1842
1843 pthread_mutex_lock(&bo_list->mutex);
1844 if (bo_list->list.count == bo_list->capacity) {
1845 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1846 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1847
1848 if (!data) {
1849 pthread_mutex_unlock(&bo_list->mutex);
1850 return VK_ERROR_OUT_OF_HOST_MEMORY;
1851 }
1852
1853 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1854 bo_list->capacity = capacity;
1855 }
1856
1857 bo_list->list.bos[bo_list->list.count++] = bo;
1858 pthread_mutex_unlock(&bo_list->mutex);
1859 return VK_SUCCESS;
1860 }
1861
1862 static void radv_bo_list_remove(struct radv_device *device,
1863 struct radeon_winsys_bo *bo)
1864 {
1865 struct radv_bo_list *bo_list = &device->bo_list;
1866
1867 if (bo->is_local)
1868 return;
1869
1870 if (unlikely(!device->use_global_bo_list))
1871 return;
1872
1873 pthread_mutex_lock(&bo_list->mutex);
1874 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1875 if (bo_list->list.bos[i] == bo) {
1876 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1877 --bo_list->list.count;
1878 break;
1879 }
1880 }
1881 pthread_mutex_unlock(&bo_list->mutex);
1882 }
1883
1884 static void
1885 radv_device_init_gs_info(struct radv_device *device)
1886 {
1887 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1888 device->physical_device->rad_info.family);
1889 }
1890
1891 static int radv_get_device_extension_index(const char *name)
1892 {
1893 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1894 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1895 return i;
1896 }
1897 return -1;
1898 }
1899
1900 static int
1901 radv_get_int_debug_option(const char *name, int default_value)
1902 {
1903 const char *str;
1904 int result;
1905
1906 str = getenv(name);
1907 if (!str) {
1908 result = default_value;
1909 } else {
1910 char *endptr;
1911
1912 result = strtol(str, &endptr, 0);
1913 if (str == endptr) {
1914 /* No digits founs. */
1915 result = default_value;
1916 }
1917 }
1918
1919 return result;
1920 }
1921
1922 VkResult radv_CreateDevice(
1923 VkPhysicalDevice physicalDevice,
1924 const VkDeviceCreateInfo* pCreateInfo,
1925 const VkAllocationCallbacks* pAllocator,
1926 VkDevice* pDevice)
1927 {
1928 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1929 VkResult result;
1930 struct radv_device *device;
1931
1932 bool keep_shader_info = false;
1933
1934 /* Check enabled features */
1935 if (pCreateInfo->pEnabledFeatures) {
1936 VkPhysicalDeviceFeatures supported_features;
1937 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1938 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1939 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1940 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1941 for (uint32_t i = 0; i < num_features; i++) {
1942 if (enabled_feature[i] && !supported_feature[i])
1943 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1944 }
1945 }
1946
1947 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1948 sizeof(*device), 8,
1949 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1950 if (!device)
1951 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1952
1953 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1954 device->instance = physical_device->instance;
1955 device->physical_device = physical_device;
1956
1957 device->ws = physical_device->ws;
1958 if (pAllocator)
1959 device->alloc = *pAllocator;
1960 else
1961 device->alloc = physical_device->instance->alloc;
1962
1963 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1964 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1965 int index = radv_get_device_extension_index(ext_name);
1966 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1967 vk_free(&device->alloc, device);
1968 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1969 }
1970
1971 device->enabled_extensions.extensions[index] = true;
1972 }
1973
1974 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1975
1976 /* With update after bind we can't attach bo's to the command buffer
1977 * from the descriptor set anymore, so we have to use a global BO list.
1978 */
1979 device->use_global_bo_list =
1980 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1981 device->enabled_extensions.EXT_descriptor_indexing ||
1982 device->enabled_extensions.EXT_buffer_device_address;
1983
1984 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1985 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1986
1987 mtx_init(&device->shader_slab_mutex, mtx_plain);
1988 list_inithead(&device->shader_slabs);
1989
1990 radv_bo_list_init(&device->bo_list);
1991
1992 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1993 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1994 uint32_t qfi = queue_create->queueFamilyIndex;
1995 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1996 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1997
1998 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1999
2000 device->queues[qfi] = vk_alloc(&device->alloc,
2001 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2002 if (!device->queues[qfi]) {
2003 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2004 goto fail;
2005 }
2006
2007 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2008
2009 device->queue_count[qfi] = queue_create->queueCount;
2010
2011 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2012 result = radv_queue_init(device, &device->queues[qfi][q],
2013 qfi, q, queue_create->flags,
2014 global_priority);
2015 if (result != VK_SUCCESS)
2016 goto fail;
2017 }
2018 }
2019
2020 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2021 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2022
2023 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2024 device->dfsm_allowed = device->pbb_allowed &&
2025 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2026
2027 #ifdef ANDROID
2028 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2029 #endif
2030
2031 /* The maximum number of scratch waves. Scratch space isn't divided
2032 * evenly between CUs. The number is only a function of the number of CUs.
2033 * We can decrease the constant to decrease the scratch buffer size.
2034 *
2035 * sctx->scratch_waves must be >= the maximum possible size of
2036 * 1 threadgroup, so that the hw doesn't hang from being unable
2037 * to start any.
2038 *
2039 * The recommended value is 4 per CU at most. Higher numbers don't
2040 * bring much benefit, but they still occupy chip resources (think
2041 * async compute). I've seen ~2% performance difference between 4 and 32.
2042 */
2043 uint32_t max_threads_per_block = 2048;
2044 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2045 max_threads_per_block / 64);
2046
2047 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
2048 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
2049
2050 if (device->physical_device->rad_info.chip_class >= GFX7) {
2051 /* If the KMD allows it (there is a KMD hw register for it),
2052 * allow launching waves out-of-order.
2053 */
2054 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2055 }
2056
2057 radv_device_init_gs_info(device);
2058
2059 device->tess_offchip_block_dw_size =
2060 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2061
2062 if (getenv("RADV_TRACE_FILE")) {
2063 const char *filename = getenv("RADV_TRACE_FILE");
2064
2065 keep_shader_info = true;
2066
2067 if (!radv_init_trace(device))
2068 goto fail;
2069
2070 fprintf(stderr, "*****************************************************************************\n");
2071 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2072 fprintf(stderr, "*****************************************************************************\n");
2073
2074 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2075 radv_dump_enabled_options(device, stderr);
2076 }
2077
2078 device->keep_shader_info = keep_shader_info;
2079
2080 result = radv_device_init_meta(device);
2081 if (result != VK_SUCCESS)
2082 goto fail;
2083
2084 radv_device_init_msaa(device);
2085
2086 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2087 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2088 switch (family) {
2089 case RADV_QUEUE_GENERAL:
2090 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2091 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2092 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2093 break;
2094 case RADV_QUEUE_COMPUTE:
2095 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2096 radeon_emit(device->empty_cs[family], 0);
2097 break;
2098 }
2099 device->ws->cs_finalize(device->empty_cs[family]);
2100 }
2101
2102 if (device->physical_device->rad_info.chip_class >= GFX7)
2103 cik_create_gfx_config(device);
2104
2105 VkPipelineCacheCreateInfo ci;
2106 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2107 ci.pNext = NULL;
2108 ci.flags = 0;
2109 ci.pInitialData = NULL;
2110 ci.initialDataSize = 0;
2111 VkPipelineCache pc;
2112 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2113 &ci, NULL, &pc);
2114 if (result != VK_SUCCESS)
2115 goto fail_meta;
2116
2117 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2118
2119 device->force_aniso =
2120 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2121 if (device->force_aniso >= 0) {
2122 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2123 1 << util_logbase2(device->force_aniso));
2124 }
2125
2126 *pDevice = radv_device_to_handle(device);
2127 return VK_SUCCESS;
2128
2129 fail_meta:
2130 radv_device_finish_meta(device);
2131 fail:
2132 radv_bo_list_finish(&device->bo_list);
2133
2134 if (device->trace_bo)
2135 device->ws->buffer_destroy(device->trace_bo);
2136
2137 if (device->gfx_init)
2138 device->ws->buffer_destroy(device->gfx_init);
2139
2140 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2141 for (unsigned q = 0; q < device->queue_count[i]; q++)
2142 radv_queue_finish(&device->queues[i][q]);
2143 if (device->queue_count[i])
2144 vk_free(&device->alloc, device->queues[i]);
2145 }
2146
2147 vk_free(&device->alloc, device);
2148 return result;
2149 }
2150
2151 void radv_DestroyDevice(
2152 VkDevice _device,
2153 const VkAllocationCallbacks* pAllocator)
2154 {
2155 RADV_FROM_HANDLE(radv_device, device, _device);
2156
2157 if (!device)
2158 return;
2159
2160 if (device->trace_bo)
2161 device->ws->buffer_destroy(device->trace_bo);
2162
2163 if (device->gfx_init)
2164 device->ws->buffer_destroy(device->gfx_init);
2165
2166 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2167 for (unsigned q = 0; q < device->queue_count[i]; q++)
2168 radv_queue_finish(&device->queues[i][q]);
2169 if (device->queue_count[i])
2170 vk_free(&device->alloc, device->queues[i]);
2171 if (device->empty_cs[i])
2172 device->ws->cs_destroy(device->empty_cs[i]);
2173 }
2174 radv_device_finish_meta(device);
2175
2176 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2177 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2178
2179 radv_destroy_shader_slabs(device);
2180
2181 radv_bo_list_finish(&device->bo_list);
2182 vk_free(&device->alloc, device);
2183 }
2184
2185 VkResult radv_EnumerateInstanceLayerProperties(
2186 uint32_t* pPropertyCount,
2187 VkLayerProperties* pProperties)
2188 {
2189 if (pProperties == NULL) {
2190 *pPropertyCount = 0;
2191 return VK_SUCCESS;
2192 }
2193
2194 /* None supported at this time */
2195 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2196 }
2197
2198 VkResult radv_EnumerateDeviceLayerProperties(
2199 VkPhysicalDevice physicalDevice,
2200 uint32_t* pPropertyCount,
2201 VkLayerProperties* pProperties)
2202 {
2203 if (pProperties == NULL) {
2204 *pPropertyCount = 0;
2205 return VK_SUCCESS;
2206 }
2207
2208 /* None supported at this time */
2209 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2210 }
2211
2212 void radv_GetDeviceQueue2(
2213 VkDevice _device,
2214 const VkDeviceQueueInfo2* pQueueInfo,
2215 VkQueue* pQueue)
2216 {
2217 RADV_FROM_HANDLE(radv_device, device, _device);
2218 struct radv_queue *queue;
2219
2220 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2221 if (pQueueInfo->flags != queue->flags) {
2222 /* From the Vulkan 1.1.70 spec:
2223 *
2224 * "The queue returned by vkGetDeviceQueue2 must have the same
2225 * flags value from this structure as that used at device
2226 * creation time in a VkDeviceQueueCreateInfo instance. If no
2227 * matching flags were specified at device creation time then
2228 * pQueue will return VK_NULL_HANDLE."
2229 */
2230 *pQueue = VK_NULL_HANDLE;
2231 return;
2232 }
2233
2234 *pQueue = radv_queue_to_handle(queue);
2235 }
2236
2237 void radv_GetDeviceQueue(
2238 VkDevice _device,
2239 uint32_t queueFamilyIndex,
2240 uint32_t queueIndex,
2241 VkQueue* pQueue)
2242 {
2243 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2244 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2245 .queueFamilyIndex = queueFamilyIndex,
2246 .queueIndex = queueIndex
2247 };
2248
2249 radv_GetDeviceQueue2(_device, &info, pQueue);
2250 }
2251
2252 static void
2253 fill_geom_tess_rings(struct radv_queue *queue,
2254 uint32_t *map,
2255 bool add_sample_positions,
2256 uint32_t esgs_ring_size,
2257 struct radeon_winsys_bo *esgs_ring_bo,
2258 uint32_t gsvs_ring_size,
2259 struct radeon_winsys_bo *gsvs_ring_bo,
2260 uint32_t tess_factor_ring_size,
2261 uint32_t tess_offchip_ring_offset,
2262 uint32_t tess_offchip_ring_size,
2263 struct radeon_winsys_bo *tess_rings_bo)
2264 {
2265 uint32_t *desc = &map[4];
2266
2267 if (esgs_ring_bo) {
2268 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2269
2270 /* stride 0, num records - size, add tid, swizzle, elsize4,
2271 index stride 64 */
2272 desc[0] = esgs_va;
2273 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2274 S_008F04_SWIZZLE_ENABLE(true);
2275 desc[2] = esgs_ring_size;
2276 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2277 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2278 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2279 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2280 S_008F0C_INDEX_STRIDE(3) |
2281 S_008F0C_ADD_TID_ENABLE(1);
2282
2283 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2284 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2285 S_008F0C_OOB_SELECT(2) |
2286 S_008F0C_RESOURCE_LEVEL(1);
2287 } else {
2288 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2289 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2290 S_008F0C_ELEMENT_SIZE(1);
2291 }
2292
2293 /* GS entry for ES->GS ring */
2294 /* stride 0, num records - size, elsize0,
2295 index stride 0 */
2296 desc[4] = esgs_va;
2297 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2298 desc[6] = esgs_ring_size;
2299 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2300 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2301 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2302 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2303
2304 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2305 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2306 S_008F0C_OOB_SELECT(2) |
2307 S_008F0C_RESOURCE_LEVEL(1);
2308 } else {
2309 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2310 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2311 }
2312 }
2313
2314 desc += 8;
2315
2316 if (gsvs_ring_bo) {
2317 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2318
2319 /* VS entry for GS->VS ring */
2320 /* stride 0, num records - size, elsize0,
2321 index stride 0 */
2322 desc[0] = gsvs_va;
2323 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2324 desc[2] = gsvs_ring_size;
2325 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2326 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2327 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2328 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2329
2330 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2331 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2332 S_008F0C_OOB_SELECT(2) |
2333 S_008F0C_RESOURCE_LEVEL(1);
2334 } else {
2335 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2336 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2337 }
2338
2339 /* stride gsvs_itemsize, num records 64
2340 elsize 4, index stride 16 */
2341 /* shader will patch stride and desc[2] */
2342 desc[4] = gsvs_va;
2343 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2344 S_008F04_SWIZZLE_ENABLE(1);
2345 desc[6] = 0;
2346 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2347 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2348 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2349 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2350 S_008F0C_INDEX_STRIDE(1) |
2351 S_008F0C_ADD_TID_ENABLE(true);
2352
2353 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2354 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2355 S_008F0C_OOB_SELECT(2) |
2356 S_008F0C_RESOURCE_LEVEL(1);
2357 } else {
2358 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2359 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2360 S_008F0C_ELEMENT_SIZE(1);
2361 }
2362
2363 }
2364
2365 desc += 8;
2366
2367 if (tess_rings_bo) {
2368 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2369 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2370
2371 desc[0] = tess_va;
2372 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2373 desc[2] = tess_factor_ring_size;
2374 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2375 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2376 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2377 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2378
2379 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2380 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2381 S_008F0C_OOB_SELECT(3) |
2382 S_008F0C_RESOURCE_LEVEL(1);
2383 } else {
2384 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2385 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2386 }
2387
2388 desc[4] = tess_offchip_va;
2389 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2390 desc[6] = tess_offchip_ring_size;
2391 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2392 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2393 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2394 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2395
2396 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2397 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2398 S_008F0C_OOB_SELECT(3) |
2399 S_008F0C_RESOURCE_LEVEL(1);
2400 } else {
2401 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2402 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2403 }
2404 }
2405
2406 desc += 8;
2407
2408 if (add_sample_positions) {
2409 /* add sample positions after all rings */
2410 memcpy(desc, queue->device->sample_locations_1x, 8);
2411 desc += 2;
2412 memcpy(desc, queue->device->sample_locations_2x, 16);
2413 desc += 4;
2414 memcpy(desc, queue->device->sample_locations_4x, 32);
2415 desc += 8;
2416 memcpy(desc, queue->device->sample_locations_8x, 64);
2417 }
2418 }
2419
2420 static unsigned
2421 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2422 {
2423 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2424 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2425 device->physical_device->rad_info.family != CHIP_STONEY;
2426 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2427 unsigned max_offchip_buffers;
2428 unsigned offchip_granularity;
2429 unsigned hs_offchip_param;
2430
2431 /*
2432 * Per RadeonSI:
2433 * This must be one less than the maximum number due to a hw limitation.
2434 * Various hardware bugs need thGFX7
2435 *
2436 * Per AMDVLK:
2437 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2438 * Gfx7 should limit max_offchip_buffers to 508
2439 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2440 *
2441 * Follow AMDVLK here.
2442 */
2443 if (device->physical_device->rad_info.chip_class >= GFX10) {
2444 max_offchip_buffers_per_se = 256;
2445 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2446 device->physical_device->rad_info.chip_class == GFX7 ||
2447 device->physical_device->rad_info.chip_class == GFX6)
2448 --max_offchip_buffers_per_se;
2449
2450 max_offchip_buffers = max_offchip_buffers_per_se *
2451 device->physical_device->rad_info.max_se;
2452
2453 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2454 * around by setting 4K granularity.
2455 */
2456 if (device->tess_offchip_block_dw_size == 4096) {
2457 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2458 offchip_granularity = V_03093C_X_4K_DWORDS;
2459 } else {
2460 assert(device->tess_offchip_block_dw_size == 8192);
2461 offchip_granularity = V_03093C_X_8K_DWORDS;
2462 }
2463
2464 switch (device->physical_device->rad_info.chip_class) {
2465 case GFX6:
2466 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2467 break;
2468 case GFX7:
2469 case GFX8:
2470 case GFX9:
2471 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2472 break;
2473 case GFX10:
2474 break;
2475 default:
2476 break;
2477 }
2478
2479 *max_offchip_buffers_p = max_offchip_buffers;
2480 if (device->physical_device->rad_info.chip_class >= GFX7) {
2481 if (device->physical_device->rad_info.chip_class >= GFX8)
2482 --max_offchip_buffers;
2483 hs_offchip_param =
2484 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2485 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2486 } else {
2487 hs_offchip_param =
2488 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2489 }
2490 return hs_offchip_param;
2491 }
2492
2493 static void
2494 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2495 struct radeon_winsys_bo *esgs_ring_bo,
2496 uint32_t esgs_ring_size,
2497 struct radeon_winsys_bo *gsvs_ring_bo,
2498 uint32_t gsvs_ring_size)
2499 {
2500 if (!esgs_ring_bo && !gsvs_ring_bo)
2501 return;
2502
2503 if (esgs_ring_bo)
2504 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2505
2506 if (gsvs_ring_bo)
2507 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2508
2509 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2510 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2511 radeon_emit(cs, esgs_ring_size >> 8);
2512 radeon_emit(cs, gsvs_ring_size >> 8);
2513 } else {
2514 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2515 radeon_emit(cs, esgs_ring_size >> 8);
2516 radeon_emit(cs, gsvs_ring_size >> 8);
2517 }
2518 }
2519
2520 static void
2521 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2522 unsigned hs_offchip_param, unsigned tf_ring_size,
2523 struct radeon_winsys_bo *tess_rings_bo)
2524 {
2525 uint64_t tf_va;
2526
2527 if (!tess_rings_bo)
2528 return;
2529
2530 tf_va = radv_buffer_get_va(tess_rings_bo);
2531
2532 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2533
2534 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2535 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2536 S_030938_SIZE(tf_ring_size / 4));
2537 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2538 tf_va >> 8);
2539
2540 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2541 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2542 S_030984_BASE_HI(tf_va >> 40));
2543 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2544 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2545 S_030944_BASE_HI(tf_va >> 40));
2546 }
2547 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2548 hs_offchip_param);
2549 } else {
2550 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2551 S_008988_SIZE(tf_ring_size / 4));
2552 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2553 tf_va >> 8);
2554 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2555 hs_offchip_param);
2556 }
2557 }
2558
2559 static void
2560 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2561 struct radeon_winsys_bo *compute_scratch_bo)
2562 {
2563 uint64_t scratch_va;
2564
2565 if (!compute_scratch_bo)
2566 return;
2567
2568 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2569
2570 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2571
2572 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2573 radeon_emit(cs, scratch_va);
2574 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2575 S_008F04_SWIZZLE_ENABLE(1));
2576 }
2577
2578 static void
2579 radv_emit_global_shader_pointers(struct radv_queue *queue,
2580 struct radeon_cmdbuf *cs,
2581 struct radeon_winsys_bo *descriptor_bo)
2582 {
2583 uint64_t va;
2584
2585 if (!descriptor_bo)
2586 return;
2587
2588 va = radv_buffer_get_va(descriptor_bo);
2589
2590 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2591
2592 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2593 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2594 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2595 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2596 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2597
2598 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2599 radv_emit_shader_pointer(queue->device, cs, regs[i],
2600 va, true);
2601 }
2602 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2603 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2604 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2605 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2606 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2607
2608 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2609 radv_emit_shader_pointer(queue->device, cs, regs[i],
2610 va, true);
2611 }
2612 } else {
2613 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2614 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2615 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2616 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2617 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2618 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2619
2620 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2621 radv_emit_shader_pointer(queue->device, cs, regs[i],
2622 va, true);
2623 }
2624 }
2625 }
2626
2627 static void
2628 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2629 {
2630 struct radv_device *device = queue->device;
2631
2632 if (device->gfx_init) {
2633 uint64_t va = radv_buffer_get_va(device->gfx_init);
2634
2635 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2636 radeon_emit(cs, va);
2637 radeon_emit(cs, va >> 32);
2638 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2639
2640 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2641 } else {
2642 struct radv_physical_device *physical_device = device->physical_device;
2643 si_emit_graphics(physical_device, cs);
2644 }
2645 }
2646
2647 static void
2648 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2649 {
2650 struct radv_physical_device *physical_device = queue->device->physical_device;
2651 si_emit_compute(physical_device, cs);
2652 }
2653
2654 static VkResult
2655 radv_get_preamble_cs(struct radv_queue *queue,
2656 uint32_t scratch_size,
2657 uint32_t compute_scratch_size,
2658 uint32_t esgs_ring_size,
2659 uint32_t gsvs_ring_size,
2660 bool needs_tess_rings,
2661 bool needs_gds,
2662 bool needs_sample_positions,
2663 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2664 struct radeon_cmdbuf **initial_preamble_cs,
2665 struct radeon_cmdbuf **continue_preamble_cs)
2666 {
2667 struct radeon_winsys_bo *scratch_bo = NULL;
2668 struct radeon_winsys_bo *descriptor_bo = NULL;
2669 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2670 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2671 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2672 struct radeon_winsys_bo *tess_rings_bo = NULL;
2673 struct radeon_winsys_bo *gds_bo = NULL;
2674 struct radeon_winsys_bo *gds_oa_bo = NULL;
2675 struct radeon_cmdbuf *dest_cs[3] = {0};
2676 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
2677 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2678 unsigned max_offchip_buffers;
2679 unsigned hs_offchip_param = 0;
2680 unsigned tess_offchip_ring_offset;
2681 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2682 if (!queue->has_tess_rings) {
2683 if (needs_tess_rings)
2684 add_tess_rings = true;
2685 }
2686 if (!queue->has_gds) {
2687 if (needs_gds)
2688 add_gds = true;
2689 }
2690 if (!queue->has_sample_positions) {
2691 if (needs_sample_positions)
2692 add_sample_positions = true;
2693 }
2694 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2695 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2696 &max_offchip_buffers);
2697 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2698 tess_offchip_ring_size = max_offchip_buffers *
2699 queue->device->tess_offchip_block_dw_size * 4;
2700
2701 if (scratch_size <= queue->scratch_size &&
2702 compute_scratch_size <= queue->compute_scratch_size &&
2703 esgs_ring_size <= queue->esgs_ring_size &&
2704 gsvs_ring_size <= queue->gsvs_ring_size &&
2705 !add_tess_rings && !add_gds && !add_sample_positions &&
2706 queue->initial_preamble_cs) {
2707 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2708 *initial_preamble_cs = queue->initial_preamble_cs;
2709 *continue_preamble_cs = queue->continue_preamble_cs;
2710 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size &&
2711 !needs_tess_rings && !needs_gds && !needs_sample_positions)
2712 *continue_preamble_cs = NULL;
2713 return VK_SUCCESS;
2714 }
2715
2716 if (scratch_size > queue->scratch_size) {
2717 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2718 scratch_size,
2719 4096,
2720 RADEON_DOMAIN_VRAM,
2721 ring_bo_flags,
2722 RADV_BO_PRIORITY_SCRATCH);
2723 if (!scratch_bo)
2724 goto fail;
2725 } else
2726 scratch_bo = queue->scratch_bo;
2727
2728 if (compute_scratch_size > queue->compute_scratch_size) {
2729 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2730 compute_scratch_size,
2731 4096,
2732 RADEON_DOMAIN_VRAM,
2733 ring_bo_flags,
2734 RADV_BO_PRIORITY_SCRATCH);
2735 if (!compute_scratch_bo)
2736 goto fail;
2737
2738 } else
2739 compute_scratch_bo = queue->compute_scratch_bo;
2740
2741 if (esgs_ring_size > queue->esgs_ring_size) {
2742 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2743 esgs_ring_size,
2744 4096,
2745 RADEON_DOMAIN_VRAM,
2746 ring_bo_flags,
2747 RADV_BO_PRIORITY_SCRATCH);
2748 if (!esgs_ring_bo)
2749 goto fail;
2750 } else {
2751 esgs_ring_bo = queue->esgs_ring_bo;
2752 esgs_ring_size = queue->esgs_ring_size;
2753 }
2754
2755 if (gsvs_ring_size > queue->gsvs_ring_size) {
2756 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2757 gsvs_ring_size,
2758 4096,
2759 RADEON_DOMAIN_VRAM,
2760 ring_bo_flags,
2761 RADV_BO_PRIORITY_SCRATCH);
2762 if (!gsvs_ring_bo)
2763 goto fail;
2764 } else {
2765 gsvs_ring_bo = queue->gsvs_ring_bo;
2766 gsvs_ring_size = queue->gsvs_ring_size;
2767 }
2768
2769 if (add_tess_rings) {
2770 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2771 tess_offchip_ring_offset + tess_offchip_ring_size,
2772 256,
2773 RADEON_DOMAIN_VRAM,
2774 ring_bo_flags,
2775 RADV_BO_PRIORITY_SCRATCH);
2776 if (!tess_rings_bo)
2777 goto fail;
2778 } else {
2779 tess_rings_bo = queue->tess_rings_bo;
2780 }
2781
2782 if (add_gds) {
2783 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
2784
2785 /* 4 streamout GDS counters.
2786 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
2787 */
2788 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
2789 256, 4,
2790 RADEON_DOMAIN_GDS,
2791 ring_bo_flags,
2792 RADV_BO_PRIORITY_SCRATCH);
2793 if (!gds_bo)
2794 goto fail;
2795
2796 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
2797 4, 1,
2798 RADEON_DOMAIN_OA,
2799 ring_bo_flags,
2800 RADV_BO_PRIORITY_SCRATCH);
2801 if (!gds_oa_bo)
2802 goto fail;
2803 } else {
2804 gds_bo = queue->gds_bo;
2805 gds_oa_bo = queue->gds_oa_bo;
2806 }
2807
2808 if (scratch_bo != queue->scratch_bo ||
2809 esgs_ring_bo != queue->esgs_ring_bo ||
2810 gsvs_ring_bo != queue->gsvs_ring_bo ||
2811 tess_rings_bo != queue->tess_rings_bo ||
2812 add_sample_positions) {
2813 uint32_t size = 0;
2814 if (gsvs_ring_bo || esgs_ring_bo ||
2815 tess_rings_bo || add_sample_positions) {
2816 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2817 if (add_sample_positions)
2818 size += 128; /* 64+32+16+8 = 120 bytes */
2819 }
2820 else if (scratch_bo)
2821 size = 8; /* 2 dword */
2822
2823 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2824 size,
2825 4096,
2826 RADEON_DOMAIN_VRAM,
2827 RADEON_FLAG_CPU_ACCESS |
2828 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2829 RADEON_FLAG_READ_ONLY,
2830 RADV_BO_PRIORITY_DESCRIPTOR);
2831 if (!descriptor_bo)
2832 goto fail;
2833 } else
2834 descriptor_bo = queue->descriptor_bo;
2835
2836 if (descriptor_bo != queue->descriptor_bo) {
2837 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2838
2839 if (scratch_bo) {
2840 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2841 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2842 S_008F04_SWIZZLE_ENABLE(1);
2843 map[0] = scratch_va;
2844 map[1] = rsrc1;
2845 }
2846
2847 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2848 fill_geom_tess_rings(queue, map, add_sample_positions,
2849 esgs_ring_size, esgs_ring_bo,
2850 gsvs_ring_size, gsvs_ring_bo,
2851 tess_factor_ring_size,
2852 tess_offchip_ring_offset,
2853 tess_offchip_ring_size,
2854 tess_rings_bo);
2855
2856 queue->device->ws->buffer_unmap(descriptor_bo);
2857 }
2858
2859 for(int i = 0; i < 3; ++i) {
2860 struct radeon_cmdbuf *cs = NULL;
2861 cs = queue->device->ws->cs_create(queue->device->ws,
2862 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2863 if (!cs)
2864 goto fail;
2865
2866 dest_cs[i] = cs;
2867
2868 if (scratch_bo)
2869 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2870
2871 /* Emit initial configuration. */
2872 switch (queue->queue_family_index) {
2873 case RADV_QUEUE_GENERAL:
2874 radv_init_graphics_state(cs, queue);
2875 break;
2876 case RADV_QUEUE_COMPUTE:
2877 radv_init_compute_state(cs, queue);
2878 break;
2879 case RADV_QUEUE_TRANSFER:
2880 break;
2881 }
2882
2883 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2884 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2885 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2886
2887 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2888 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2889 }
2890
2891 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2892 gsvs_ring_bo, gsvs_ring_size);
2893 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2894 tess_factor_ring_size, tess_rings_bo);
2895 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2896 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2897
2898 if (gds_bo)
2899 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
2900 if (gds_oa_bo)
2901 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
2902
2903 if (i == 0) {
2904 si_cs_emit_cache_flush(cs,
2905 queue->device->physical_device->rad_info.chip_class,
2906 NULL, 0,
2907 queue->queue_family_index == RING_COMPUTE &&
2908 queue->device->physical_device->rad_info.chip_class >= GFX7,
2909 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2910 RADV_CMD_FLAG_INV_ICACHE |
2911 RADV_CMD_FLAG_INV_SCACHE |
2912 RADV_CMD_FLAG_INV_VCACHE |
2913 RADV_CMD_FLAG_INV_L2 |
2914 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2915 } else if (i == 1) {
2916 si_cs_emit_cache_flush(cs,
2917 queue->device->physical_device->rad_info.chip_class,
2918 NULL, 0,
2919 queue->queue_family_index == RING_COMPUTE &&
2920 queue->device->physical_device->rad_info.chip_class >= GFX7,
2921 RADV_CMD_FLAG_INV_ICACHE |
2922 RADV_CMD_FLAG_INV_SCACHE |
2923 RADV_CMD_FLAG_INV_VCACHE |
2924 RADV_CMD_FLAG_INV_L2 |
2925 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2926 }
2927
2928 if (!queue->device->ws->cs_finalize(cs))
2929 goto fail;
2930 }
2931
2932 if (queue->initial_full_flush_preamble_cs)
2933 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2934
2935 if (queue->initial_preamble_cs)
2936 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2937
2938 if (queue->continue_preamble_cs)
2939 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2940
2941 queue->initial_full_flush_preamble_cs = dest_cs[0];
2942 queue->initial_preamble_cs = dest_cs[1];
2943 queue->continue_preamble_cs = dest_cs[2];
2944
2945 if (scratch_bo != queue->scratch_bo) {
2946 if (queue->scratch_bo)
2947 queue->device->ws->buffer_destroy(queue->scratch_bo);
2948 queue->scratch_bo = scratch_bo;
2949 queue->scratch_size = scratch_size;
2950 }
2951
2952 if (compute_scratch_bo != queue->compute_scratch_bo) {
2953 if (queue->compute_scratch_bo)
2954 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2955 queue->compute_scratch_bo = compute_scratch_bo;
2956 queue->compute_scratch_size = compute_scratch_size;
2957 }
2958
2959 if (esgs_ring_bo != queue->esgs_ring_bo) {
2960 if (queue->esgs_ring_bo)
2961 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2962 queue->esgs_ring_bo = esgs_ring_bo;
2963 queue->esgs_ring_size = esgs_ring_size;
2964 }
2965
2966 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2967 if (queue->gsvs_ring_bo)
2968 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2969 queue->gsvs_ring_bo = gsvs_ring_bo;
2970 queue->gsvs_ring_size = gsvs_ring_size;
2971 }
2972
2973 if (tess_rings_bo != queue->tess_rings_bo) {
2974 queue->tess_rings_bo = tess_rings_bo;
2975 queue->has_tess_rings = true;
2976 }
2977
2978 if (gds_bo != queue->gds_bo) {
2979 queue->gds_bo = gds_bo;
2980 queue->has_gds = true;
2981 }
2982
2983 if (gds_oa_bo != queue->gds_oa_bo)
2984 queue->gds_oa_bo = gds_oa_bo;
2985
2986 if (descriptor_bo != queue->descriptor_bo) {
2987 if (queue->descriptor_bo)
2988 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2989
2990 queue->descriptor_bo = descriptor_bo;
2991 }
2992
2993 if (add_sample_positions)
2994 queue->has_sample_positions = true;
2995
2996 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2997 *initial_preamble_cs = queue->initial_preamble_cs;
2998 *continue_preamble_cs = queue->continue_preamble_cs;
2999 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3000 *continue_preamble_cs = NULL;
3001 return VK_SUCCESS;
3002 fail:
3003 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3004 if (dest_cs[i])
3005 queue->device->ws->cs_destroy(dest_cs[i]);
3006 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3007 queue->device->ws->buffer_destroy(descriptor_bo);
3008 if (scratch_bo && scratch_bo != queue->scratch_bo)
3009 queue->device->ws->buffer_destroy(scratch_bo);
3010 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3011 queue->device->ws->buffer_destroy(compute_scratch_bo);
3012 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3013 queue->device->ws->buffer_destroy(esgs_ring_bo);
3014 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3015 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3016 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3017 queue->device->ws->buffer_destroy(tess_rings_bo);
3018 if (gds_bo && gds_bo != queue->gds_bo)
3019 queue->device->ws->buffer_destroy(gds_bo);
3020 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3021 queue->device->ws->buffer_destroy(gds_oa_bo);
3022
3023 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3024 }
3025
3026 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
3027 struct radv_winsys_sem_counts *counts,
3028 int num_sems,
3029 const VkSemaphore *sems,
3030 VkFence _fence,
3031 bool reset_temp)
3032 {
3033 int syncobj_idx = 0, sem_idx = 0;
3034
3035 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3036 return VK_SUCCESS;
3037
3038 for (uint32_t i = 0; i < num_sems; i++) {
3039 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3040
3041 if (sem->temp_syncobj || sem->syncobj)
3042 counts->syncobj_count++;
3043 else
3044 counts->sem_count++;
3045 }
3046
3047 if (_fence != VK_NULL_HANDLE) {
3048 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3049 if (fence->temp_syncobj || fence->syncobj)
3050 counts->syncobj_count++;
3051 }
3052
3053 if (counts->syncobj_count) {
3054 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3055 if (!counts->syncobj)
3056 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3057 }
3058
3059 if (counts->sem_count) {
3060 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3061 if (!counts->sem) {
3062 free(counts->syncobj);
3063 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3064 }
3065 }
3066
3067 for (uint32_t i = 0; i < num_sems; i++) {
3068 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3069
3070 if (sem->temp_syncobj) {
3071 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
3072 }
3073 else if (sem->syncobj)
3074 counts->syncobj[syncobj_idx++] = sem->syncobj;
3075 else {
3076 assert(sem->sem);
3077 counts->sem[sem_idx++] = sem->sem;
3078 }
3079 }
3080
3081 if (_fence != VK_NULL_HANDLE) {
3082 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3083 if (fence->temp_syncobj)
3084 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3085 else if (fence->syncobj)
3086 counts->syncobj[syncobj_idx++] = fence->syncobj;
3087 }
3088
3089 return VK_SUCCESS;
3090 }
3091
3092 static void
3093 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3094 {
3095 free(sem_info->wait.syncobj);
3096 free(sem_info->wait.sem);
3097 free(sem_info->signal.syncobj);
3098 free(sem_info->signal.sem);
3099 }
3100
3101
3102 static void radv_free_temp_syncobjs(struct radv_device *device,
3103 int num_sems,
3104 const VkSemaphore *sems)
3105 {
3106 for (uint32_t i = 0; i < num_sems; i++) {
3107 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3108
3109 if (sem->temp_syncobj) {
3110 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
3111 sem->temp_syncobj = 0;
3112 }
3113 }
3114 }
3115
3116 static VkResult
3117 radv_alloc_sem_info(struct radv_instance *instance,
3118 struct radv_winsys_sem_info *sem_info,
3119 int num_wait_sems,
3120 const VkSemaphore *wait_sems,
3121 int num_signal_sems,
3122 const VkSemaphore *signal_sems,
3123 VkFence fence)
3124 {
3125 VkResult ret;
3126 memset(sem_info, 0, sizeof(*sem_info));
3127
3128 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3129 if (ret)
3130 return ret;
3131 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3132 if (ret)
3133 radv_free_sem_info(sem_info);
3134
3135 /* caller can override these */
3136 sem_info->cs_emit_wait = true;
3137 sem_info->cs_emit_signal = true;
3138 return ret;
3139 }
3140
3141 /* Signals fence as soon as all the work currently put on queue is done. */
3142 static VkResult radv_signal_fence(struct radv_queue *queue,
3143 struct radv_fence *fence)
3144 {
3145 int ret;
3146 VkResult result;
3147 struct radv_winsys_sem_info sem_info;
3148
3149 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3150 radv_fence_to_handle(fence));
3151 if (result != VK_SUCCESS)
3152 return result;
3153
3154 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3155 &queue->device->empty_cs[queue->queue_family_index],
3156 1, NULL, NULL, &sem_info, NULL,
3157 false, fence->fence);
3158 radv_free_sem_info(&sem_info);
3159
3160 if (ret)
3161 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3162
3163 return VK_SUCCESS;
3164 }
3165
3166 VkResult radv_QueueSubmit(
3167 VkQueue _queue,
3168 uint32_t submitCount,
3169 const VkSubmitInfo* pSubmits,
3170 VkFence _fence)
3171 {
3172 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3173 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3174 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3175 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3176 int ret;
3177 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3178 uint32_t scratch_size = 0;
3179 uint32_t compute_scratch_size = 0;
3180 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3181 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3182 VkResult result;
3183 bool fence_emitted = false;
3184 bool tess_rings_needed = false;
3185 bool gds_needed = false;
3186 bool sample_positions_needed = false;
3187
3188 /* Do this first so failing to allocate scratch buffers can't result in
3189 * partially executed submissions. */
3190 for (uint32_t i = 0; i < submitCount; i++) {
3191 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3192 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3193 pSubmits[i].pCommandBuffers[j]);
3194
3195 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3196 compute_scratch_size = MAX2(compute_scratch_size,
3197 cmd_buffer->compute_scratch_size_needed);
3198 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3199 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3200 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3201 gds_needed |= cmd_buffer->gds_needed;
3202 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3203 }
3204 }
3205
3206 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3207 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3208 gds_needed, sample_positions_needed,
3209 &initial_flush_preamble_cs,
3210 &initial_preamble_cs, &continue_preamble_cs);
3211 if (result != VK_SUCCESS)
3212 return result;
3213
3214 for (uint32_t i = 0; i < submitCount; i++) {
3215 struct radeon_cmdbuf **cs_array;
3216 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3217 bool can_patch = true;
3218 uint32_t advance;
3219 struct radv_winsys_sem_info sem_info;
3220
3221 result = radv_alloc_sem_info(queue->device->instance,
3222 &sem_info,
3223 pSubmits[i].waitSemaphoreCount,
3224 pSubmits[i].pWaitSemaphores,
3225 pSubmits[i].signalSemaphoreCount,
3226 pSubmits[i].pSignalSemaphores,
3227 _fence);
3228 if (result != VK_SUCCESS)
3229 return result;
3230
3231 if (!pSubmits[i].commandBufferCount) {
3232 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3233 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3234 &queue->device->empty_cs[queue->queue_family_index],
3235 1, NULL, NULL,
3236 &sem_info, NULL,
3237 false, base_fence);
3238 if (ret) {
3239 radv_loge("failed to submit CS %d\n", i);
3240 abort();
3241 }
3242 fence_emitted = true;
3243 }
3244 radv_free_sem_info(&sem_info);
3245 continue;
3246 }
3247
3248 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3249 (pSubmits[i].commandBufferCount));
3250
3251 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3252 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3253 pSubmits[i].pCommandBuffers[j]);
3254 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3255
3256 cs_array[j] = cmd_buffer->cs;
3257 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3258 can_patch = false;
3259
3260 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3261 }
3262
3263 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3264 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3265 const struct radv_winsys_bo_list *bo_list = NULL;
3266
3267 advance = MIN2(max_cs_submission,
3268 pSubmits[i].commandBufferCount - j);
3269
3270 if (queue->device->trace_bo)
3271 *queue->device->trace_id_ptr = 0;
3272
3273 sem_info.cs_emit_wait = j == 0;
3274 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3275
3276 if (unlikely(queue->device->use_global_bo_list)) {
3277 pthread_mutex_lock(&queue->device->bo_list.mutex);
3278 bo_list = &queue->device->bo_list.list;
3279 }
3280
3281 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3282 advance, initial_preamble, continue_preamble_cs,
3283 &sem_info, bo_list,
3284 can_patch, base_fence);
3285
3286 if (unlikely(queue->device->use_global_bo_list))
3287 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3288
3289 if (ret) {
3290 radv_loge("failed to submit CS %d\n", i);
3291 abort();
3292 }
3293 fence_emitted = true;
3294 if (queue->device->trace_bo) {
3295 radv_check_gpu_hangs(queue, cs_array[j]);
3296 }
3297 }
3298
3299 radv_free_temp_syncobjs(queue->device,
3300 pSubmits[i].waitSemaphoreCount,
3301 pSubmits[i].pWaitSemaphores);
3302 radv_free_sem_info(&sem_info);
3303 free(cs_array);
3304 }
3305
3306 if (fence) {
3307 if (!fence_emitted) {
3308 result = radv_signal_fence(queue, fence);
3309 if (result != VK_SUCCESS)
3310 return result;
3311 }
3312 }
3313
3314 return VK_SUCCESS;
3315 }
3316
3317 VkResult radv_QueueWaitIdle(
3318 VkQueue _queue)
3319 {
3320 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3321
3322 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3323 radv_queue_family_to_ring(queue->queue_family_index),
3324 queue->queue_idx);
3325 return VK_SUCCESS;
3326 }
3327
3328 VkResult radv_DeviceWaitIdle(
3329 VkDevice _device)
3330 {
3331 RADV_FROM_HANDLE(radv_device, device, _device);
3332
3333 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3334 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3335 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3336 }
3337 }
3338 return VK_SUCCESS;
3339 }
3340
3341 VkResult radv_EnumerateInstanceExtensionProperties(
3342 const char* pLayerName,
3343 uint32_t* pPropertyCount,
3344 VkExtensionProperties* pProperties)
3345 {
3346 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3347
3348 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3349 if (radv_supported_instance_extensions.extensions[i]) {
3350 vk_outarray_append(&out, prop) {
3351 *prop = radv_instance_extensions[i];
3352 }
3353 }
3354 }
3355
3356 return vk_outarray_status(&out);
3357 }
3358
3359 VkResult radv_EnumerateDeviceExtensionProperties(
3360 VkPhysicalDevice physicalDevice,
3361 const char* pLayerName,
3362 uint32_t* pPropertyCount,
3363 VkExtensionProperties* pProperties)
3364 {
3365 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3366 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3367
3368 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3369 if (device->supported_extensions.extensions[i]) {
3370 vk_outarray_append(&out, prop) {
3371 *prop = radv_device_extensions[i];
3372 }
3373 }
3374 }
3375
3376 return vk_outarray_status(&out);
3377 }
3378
3379 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3380 VkInstance _instance,
3381 const char* pName)
3382 {
3383 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3384 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3385
3386 if (unchecked) {
3387 return radv_lookup_entrypoint_unchecked(pName);
3388 } else {
3389 return radv_lookup_entrypoint_checked(pName,
3390 instance ? instance->apiVersion : 0,
3391 instance ? &instance->enabled_extensions : NULL,
3392 NULL);
3393 }
3394 }
3395
3396 /* The loader wants us to expose a second GetInstanceProcAddr function
3397 * to work around certain LD_PRELOAD issues seen in apps.
3398 */
3399 PUBLIC
3400 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3401 VkInstance instance,
3402 const char* pName);
3403
3404 PUBLIC
3405 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3406 VkInstance instance,
3407 const char* pName)
3408 {
3409 return radv_GetInstanceProcAddr(instance, pName);
3410 }
3411
3412 PUBLIC
3413 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3414 VkInstance _instance,
3415 const char* pName);
3416
3417 PUBLIC
3418 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3419 VkInstance _instance,
3420 const char* pName)
3421 {
3422 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3423
3424 return radv_lookup_physical_device_entrypoint_checked(pName,
3425 instance ? instance->apiVersion : 0,
3426 instance ? &instance->enabled_extensions : NULL);
3427 }
3428
3429 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3430 VkDevice _device,
3431 const char* pName)
3432 {
3433 RADV_FROM_HANDLE(radv_device, device, _device);
3434 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3435
3436 if (unchecked) {
3437 return radv_lookup_entrypoint_unchecked(pName);
3438 } else {
3439 return radv_lookup_entrypoint_checked(pName,
3440 device->instance->apiVersion,
3441 &device->instance->enabled_extensions,
3442 &device->enabled_extensions);
3443 }
3444 }
3445
3446 bool radv_get_memory_fd(struct radv_device *device,
3447 struct radv_device_memory *memory,
3448 int *pFD)
3449 {
3450 struct radeon_bo_metadata metadata;
3451
3452 if (memory->image) {
3453 radv_init_metadata(device, memory->image, &metadata);
3454 device->ws->buffer_set_metadata(memory->bo, &metadata);
3455 }
3456
3457 return device->ws->buffer_get_fd(device->ws, memory->bo,
3458 pFD);
3459 }
3460
3461
3462 static void radv_free_memory(struct radv_device *device,
3463 const VkAllocationCallbacks* pAllocator,
3464 struct radv_device_memory *mem)
3465 {
3466 if (mem == NULL)
3467 return;
3468
3469 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
3470 if (mem->android_hardware_buffer)
3471 AHardwareBuffer_release(mem->android_hardware_buffer);
3472 #endif
3473
3474 if (mem->bo) {
3475 radv_bo_list_remove(device, mem->bo);
3476 device->ws->buffer_destroy(mem->bo);
3477 mem->bo = NULL;
3478 }
3479
3480 vk_free2(&device->alloc, pAllocator, mem);
3481 }
3482
3483 static VkResult radv_alloc_memory(struct radv_device *device,
3484 const VkMemoryAllocateInfo* pAllocateInfo,
3485 const VkAllocationCallbacks* pAllocator,
3486 VkDeviceMemory* pMem)
3487 {
3488 struct radv_device_memory *mem;
3489 VkResult result;
3490 enum radeon_bo_domain domain;
3491 uint32_t flags = 0;
3492 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3493
3494 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3495
3496 const VkImportMemoryFdInfoKHR *import_info =
3497 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3498 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3499 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3500 const VkExportMemoryAllocateInfo *export_info =
3501 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3502 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
3503 vk_find_struct_const(pAllocateInfo->pNext,
3504 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
3505 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3506 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3507
3508 const struct wsi_memory_allocate_info *wsi_info =
3509 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3510
3511 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
3512 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
3513 /* Apparently, this is allowed */
3514 *pMem = VK_NULL_HANDLE;
3515 return VK_SUCCESS;
3516 }
3517
3518 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3519 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3520 if (mem == NULL)
3521 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3522
3523 if (wsi_info && wsi_info->implicit_sync)
3524 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3525
3526 if (dedicate_info) {
3527 mem->image = radv_image_from_handle(dedicate_info->image);
3528 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3529 } else {
3530 mem->image = NULL;
3531 mem->buffer = NULL;
3532 }
3533
3534 float priority_float = 0.5;
3535 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3536 vk_find_struct_const(pAllocateInfo->pNext,
3537 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3538 if (priority_ext)
3539 priority_float = priority_ext->priority;
3540
3541 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3542 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3543
3544 mem->user_ptr = NULL;
3545 mem->bo = NULL;
3546
3547 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
3548 mem->android_hardware_buffer = NULL;
3549 #endif
3550
3551 if (ahb_import_info) {
3552 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
3553 if (result != VK_SUCCESS)
3554 goto fail;
3555 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
3556 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
3557 if (result != VK_SUCCESS)
3558 goto fail;
3559 } else if (import_info) {
3560 assert(import_info->handleType ==
3561 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3562 import_info->handleType ==
3563 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3564 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3565 priority, NULL);
3566 if (!mem->bo) {
3567 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3568 goto fail;
3569 } else {
3570 close(import_info->fd);
3571 }
3572 } else if (host_ptr_info) {
3573 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3574 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3575 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3576 pAllocateInfo->allocationSize,
3577 priority);
3578 if (!mem->bo) {
3579 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3580 goto fail;
3581 } else {
3582 mem->user_ptr = host_ptr_info->pHostPointer;
3583 }
3584 } else {
3585 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3586 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3587 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3588 domain = RADEON_DOMAIN_GTT;
3589 else
3590 domain = RADEON_DOMAIN_VRAM;
3591
3592 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3593 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3594 else
3595 flags |= RADEON_FLAG_CPU_ACCESS;
3596
3597 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3598 flags |= RADEON_FLAG_GTT_WC;
3599
3600 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3601 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3602 if (device->use_global_bo_list) {
3603 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3604 }
3605 }
3606
3607 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3608 domain, flags, priority);
3609
3610 if (!mem->bo) {
3611 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3612 goto fail;
3613 }
3614 mem->type_index = mem_type_index;
3615 }
3616
3617 result = radv_bo_list_add(device, mem->bo);
3618 if (result != VK_SUCCESS)
3619 goto fail;
3620
3621 *pMem = radv_device_memory_to_handle(mem);
3622
3623 return VK_SUCCESS;
3624
3625 fail:
3626 radv_free_memory(device, pAllocator,mem);
3627 vk_free2(&device->alloc, pAllocator, mem);
3628
3629 return result;
3630 }
3631
3632 VkResult radv_AllocateMemory(
3633 VkDevice _device,
3634 const VkMemoryAllocateInfo* pAllocateInfo,
3635 const VkAllocationCallbacks* pAllocator,
3636 VkDeviceMemory* pMem)
3637 {
3638 RADV_FROM_HANDLE(radv_device, device, _device);
3639 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3640 }
3641
3642 void radv_FreeMemory(
3643 VkDevice _device,
3644 VkDeviceMemory _mem,
3645 const VkAllocationCallbacks* pAllocator)
3646 {
3647 RADV_FROM_HANDLE(radv_device, device, _device);
3648 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3649
3650 radv_free_memory(device, pAllocator, mem);
3651 }
3652
3653 VkResult radv_MapMemory(
3654 VkDevice _device,
3655 VkDeviceMemory _memory,
3656 VkDeviceSize offset,
3657 VkDeviceSize size,
3658 VkMemoryMapFlags flags,
3659 void** ppData)
3660 {
3661 RADV_FROM_HANDLE(radv_device, device, _device);
3662 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3663
3664 if (mem == NULL) {
3665 *ppData = NULL;
3666 return VK_SUCCESS;
3667 }
3668
3669 if (mem->user_ptr)
3670 *ppData = mem->user_ptr;
3671 else
3672 *ppData = device->ws->buffer_map(mem->bo);
3673
3674 if (*ppData) {
3675 *ppData += offset;
3676 return VK_SUCCESS;
3677 }
3678
3679 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3680 }
3681
3682 void radv_UnmapMemory(
3683 VkDevice _device,
3684 VkDeviceMemory _memory)
3685 {
3686 RADV_FROM_HANDLE(radv_device, device, _device);
3687 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3688
3689 if (mem == NULL)
3690 return;
3691
3692 if (mem->user_ptr == NULL)
3693 device->ws->buffer_unmap(mem->bo);
3694 }
3695
3696 VkResult radv_FlushMappedMemoryRanges(
3697 VkDevice _device,
3698 uint32_t memoryRangeCount,
3699 const VkMappedMemoryRange* pMemoryRanges)
3700 {
3701 return VK_SUCCESS;
3702 }
3703
3704 VkResult radv_InvalidateMappedMemoryRanges(
3705 VkDevice _device,
3706 uint32_t memoryRangeCount,
3707 const VkMappedMemoryRange* pMemoryRanges)
3708 {
3709 return VK_SUCCESS;
3710 }
3711
3712 void radv_GetBufferMemoryRequirements(
3713 VkDevice _device,
3714 VkBuffer _buffer,
3715 VkMemoryRequirements* pMemoryRequirements)
3716 {
3717 RADV_FROM_HANDLE(radv_device, device, _device);
3718 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3719
3720 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3721
3722 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3723 pMemoryRequirements->alignment = 4096;
3724 else
3725 pMemoryRequirements->alignment = 16;
3726
3727 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3728 }
3729
3730 void radv_GetBufferMemoryRequirements2(
3731 VkDevice device,
3732 const VkBufferMemoryRequirementsInfo2 *pInfo,
3733 VkMemoryRequirements2 *pMemoryRequirements)
3734 {
3735 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3736 &pMemoryRequirements->memoryRequirements);
3737 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3738 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3739 switch (ext->sType) {
3740 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3741 VkMemoryDedicatedRequirements *req =
3742 (VkMemoryDedicatedRequirements *) ext;
3743 req->requiresDedicatedAllocation = buffer->shareable;
3744 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3745 break;
3746 }
3747 default:
3748 break;
3749 }
3750 }
3751 }
3752
3753 void radv_GetImageMemoryRequirements(
3754 VkDevice _device,
3755 VkImage _image,
3756 VkMemoryRequirements* pMemoryRequirements)
3757 {
3758 RADV_FROM_HANDLE(radv_device, device, _device);
3759 RADV_FROM_HANDLE(radv_image, image, _image);
3760
3761 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3762
3763 pMemoryRequirements->size = image->size;
3764 pMemoryRequirements->alignment = image->alignment;
3765 }
3766
3767 void radv_GetImageMemoryRequirements2(
3768 VkDevice device,
3769 const VkImageMemoryRequirementsInfo2 *pInfo,
3770 VkMemoryRequirements2 *pMemoryRequirements)
3771 {
3772 radv_GetImageMemoryRequirements(device, pInfo->image,
3773 &pMemoryRequirements->memoryRequirements);
3774
3775 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3776
3777 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3778 switch (ext->sType) {
3779 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3780 VkMemoryDedicatedRequirements *req =
3781 (VkMemoryDedicatedRequirements *) ext;
3782 req->requiresDedicatedAllocation = image->shareable;
3783 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3784 break;
3785 }
3786 default:
3787 break;
3788 }
3789 }
3790 }
3791
3792 void radv_GetImageSparseMemoryRequirements(
3793 VkDevice device,
3794 VkImage image,
3795 uint32_t* pSparseMemoryRequirementCount,
3796 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3797 {
3798 stub();
3799 }
3800
3801 void radv_GetImageSparseMemoryRequirements2(
3802 VkDevice device,
3803 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3804 uint32_t* pSparseMemoryRequirementCount,
3805 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3806 {
3807 stub();
3808 }
3809
3810 void radv_GetDeviceMemoryCommitment(
3811 VkDevice device,
3812 VkDeviceMemory memory,
3813 VkDeviceSize* pCommittedMemoryInBytes)
3814 {
3815 *pCommittedMemoryInBytes = 0;
3816 }
3817
3818 VkResult radv_BindBufferMemory2(VkDevice device,
3819 uint32_t bindInfoCount,
3820 const VkBindBufferMemoryInfo *pBindInfos)
3821 {
3822 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3823 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3824 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3825
3826 if (mem) {
3827 buffer->bo = mem->bo;
3828 buffer->offset = pBindInfos[i].memoryOffset;
3829 } else {
3830 buffer->bo = NULL;
3831 }
3832 }
3833 return VK_SUCCESS;
3834 }
3835
3836 VkResult radv_BindBufferMemory(
3837 VkDevice device,
3838 VkBuffer buffer,
3839 VkDeviceMemory memory,
3840 VkDeviceSize memoryOffset)
3841 {
3842 const VkBindBufferMemoryInfo info = {
3843 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3844 .buffer = buffer,
3845 .memory = memory,
3846 .memoryOffset = memoryOffset
3847 };
3848
3849 return radv_BindBufferMemory2(device, 1, &info);
3850 }
3851
3852 VkResult radv_BindImageMemory2(VkDevice device,
3853 uint32_t bindInfoCount,
3854 const VkBindImageMemoryInfo *pBindInfos)
3855 {
3856 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3857 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3858 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3859
3860 if (mem) {
3861 image->bo = mem->bo;
3862 image->offset = pBindInfos[i].memoryOffset;
3863 } else {
3864 image->bo = NULL;
3865 image->offset = 0;
3866 }
3867 }
3868 return VK_SUCCESS;
3869 }
3870
3871
3872 VkResult radv_BindImageMemory(
3873 VkDevice device,
3874 VkImage image,
3875 VkDeviceMemory memory,
3876 VkDeviceSize memoryOffset)
3877 {
3878 const VkBindImageMemoryInfo info = {
3879 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3880 .image = image,
3881 .memory = memory,
3882 .memoryOffset = memoryOffset
3883 };
3884
3885 return radv_BindImageMemory2(device, 1, &info);
3886 }
3887
3888
3889 static void
3890 radv_sparse_buffer_bind_memory(struct radv_device *device,
3891 const VkSparseBufferMemoryBindInfo *bind)
3892 {
3893 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3894
3895 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3896 struct radv_device_memory *mem = NULL;
3897
3898 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3899 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3900
3901 device->ws->buffer_virtual_bind(buffer->bo,
3902 bind->pBinds[i].resourceOffset,
3903 bind->pBinds[i].size,
3904 mem ? mem->bo : NULL,
3905 bind->pBinds[i].memoryOffset);
3906 }
3907 }
3908
3909 static void
3910 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3911 const VkSparseImageOpaqueMemoryBindInfo *bind)
3912 {
3913 RADV_FROM_HANDLE(radv_image, image, bind->image);
3914
3915 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3916 struct radv_device_memory *mem = NULL;
3917
3918 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3919 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3920
3921 device->ws->buffer_virtual_bind(image->bo,
3922 bind->pBinds[i].resourceOffset,
3923 bind->pBinds[i].size,
3924 mem ? mem->bo : NULL,
3925 bind->pBinds[i].memoryOffset);
3926 }
3927 }
3928
3929 VkResult radv_QueueBindSparse(
3930 VkQueue _queue,
3931 uint32_t bindInfoCount,
3932 const VkBindSparseInfo* pBindInfo,
3933 VkFence _fence)
3934 {
3935 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3936 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3937 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3938 bool fence_emitted = false;
3939 VkResult result;
3940 int ret;
3941
3942 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3943 struct radv_winsys_sem_info sem_info;
3944 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3945 radv_sparse_buffer_bind_memory(queue->device,
3946 pBindInfo[i].pBufferBinds + j);
3947 }
3948
3949 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3950 radv_sparse_image_opaque_bind_memory(queue->device,
3951 pBindInfo[i].pImageOpaqueBinds + j);
3952 }
3953
3954 VkResult result;
3955 result = radv_alloc_sem_info(queue->device->instance,
3956 &sem_info,
3957 pBindInfo[i].waitSemaphoreCount,
3958 pBindInfo[i].pWaitSemaphores,
3959 pBindInfo[i].signalSemaphoreCount,
3960 pBindInfo[i].pSignalSemaphores,
3961 _fence);
3962 if (result != VK_SUCCESS)
3963 return result;
3964
3965 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3966 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3967 &queue->device->empty_cs[queue->queue_family_index],
3968 1, NULL, NULL,
3969 &sem_info, NULL,
3970 false, base_fence);
3971 if (ret) {
3972 radv_loge("failed to submit CS %d\n", i);
3973 abort();
3974 }
3975
3976 fence_emitted = true;
3977 }
3978
3979 radv_free_sem_info(&sem_info);
3980
3981 }
3982
3983 if (fence) {
3984 if (!fence_emitted) {
3985 result = radv_signal_fence(queue, fence);
3986 if (result != VK_SUCCESS)
3987 return result;
3988 }
3989 }
3990
3991 return VK_SUCCESS;
3992 }
3993
3994 VkResult radv_CreateFence(
3995 VkDevice _device,
3996 const VkFenceCreateInfo* pCreateInfo,
3997 const VkAllocationCallbacks* pAllocator,
3998 VkFence* pFence)
3999 {
4000 RADV_FROM_HANDLE(radv_device, device, _device);
4001 const VkExportFenceCreateInfo *export =
4002 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
4003 VkExternalFenceHandleTypeFlags handleTypes =
4004 export ? export->handleTypes : 0;
4005
4006 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
4007 sizeof(*fence), 8,
4008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4009
4010 if (!fence)
4011 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4012
4013 fence->fence_wsi = NULL;
4014 fence->temp_syncobj = 0;
4015 if (device->always_use_syncobj || handleTypes) {
4016 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
4017 if (ret) {
4018 vk_free2(&device->alloc, pAllocator, fence);
4019 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4020 }
4021 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
4022 device->ws->signal_syncobj(device->ws, fence->syncobj);
4023 }
4024 fence->fence = NULL;
4025 } else {
4026 fence->fence = device->ws->create_fence();
4027 if (!fence->fence) {
4028 vk_free2(&device->alloc, pAllocator, fence);
4029 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4030 }
4031 fence->syncobj = 0;
4032 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
4033 device->ws->signal_fence(fence->fence);
4034 }
4035
4036 *pFence = radv_fence_to_handle(fence);
4037
4038 return VK_SUCCESS;
4039 }
4040
4041 void radv_DestroyFence(
4042 VkDevice _device,
4043 VkFence _fence,
4044 const VkAllocationCallbacks* pAllocator)
4045 {
4046 RADV_FROM_HANDLE(radv_device, device, _device);
4047 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4048
4049 if (!fence)
4050 return;
4051
4052 if (fence->temp_syncobj)
4053 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4054 if (fence->syncobj)
4055 device->ws->destroy_syncobj(device->ws, fence->syncobj);
4056 if (fence->fence)
4057 device->ws->destroy_fence(fence->fence);
4058 if (fence->fence_wsi)
4059 fence->fence_wsi->destroy(fence->fence_wsi);
4060 vk_free2(&device->alloc, pAllocator, fence);
4061 }
4062
4063
4064 uint64_t radv_get_current_time(void)
4065 {
4066 struct timespec tv;
4067 clock_gettime(CLOCK_MONOTONIC, &tv);
4068 return tv.tv_nsec + tv.tv_sec*1000000000ull;
4069 }
4070
4071 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
4072 {
4073 uint64_t current_time = radv_get_current_time();
4074
4075 timeout = MIN2(UINT64_MAX - current_time, timeout);
4076
4077 return current_time + timeout;
4078 }
4079
4080
4081 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
4082 uint32_t fenceCount, const VkFence *pFences)
4083 {
4084 for (uint32_t i = 0; i < fenceCount; ++i) {
4085 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4086 if (fence->fence == NULL || fence->syncobj ||
4087 fence->temp_syncobj || fence->fence_wsi ||
4088 (!device->ws->is_fence_waitable(fence->fence)))
4089 return false;
4090 }
4091 return true;
4092 }
4093
4094 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
4095 {
4096 for (uint32_t i = 0; i < fenceCount; ++i) {
4097 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4098 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
4099 return false;
4100 }
4101 return true;
4102 }
4103
4104 VkResult radv_WaitForFences(
4105 VkDevice _device,
4106 uint32_t fenceCount,
4107 const VkFence* pFences,
4108 VkBool32 waitAll,
4109 uint64_t timeout)
4110 {
4111 RADV_FROM_HANDLE(radv_device, device, _device);
4112 timeout = radv_get_absolute_timeout(timeout);
4113
4114 if (device->always_use_syncobj &&
4115 radv_all_fences_syncobj(fenceCount, pFences))
4116 {
4117 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
4118 if (!handles)
4119 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4120
4121 for (uint32_t i = 0; i < fenceCount; ++i) {
4122 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4123 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
4124 }
4125
4126 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
4127
4128 free(handles);
4129 return success ? VK_SUCCESS : VK_TIMEOUT;
4130 }
4131
4132 if (!waitAll && fenceCount > 1) {
4133 /* Not doing this by default for waitAll, due to needing to allocate twice. */
4134 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
4135 uint32_t wait_count = 0;
4136 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
4137 if (!fences)
4138 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4139
4140 for (uint32_t i = 0; i < fenceCount; ++i) {
4141 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4142
4143 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
4144 free(fences);
4145 return VK_SUCCESS;
4146 }
4147
4148 fences[wait_count++] = fence->fence;
4149 }
4150
4151 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
4152 waitAll, timeout - radv_get_current_time());
4153
4154 free(fences);
4155 return success ? VK_SUCCESS : VK_TIMEOUT;
4156 }
4157
4158 while(radv_get_current_time() <= timeout) {
4159 for (uint32_t i = 0; i < fenceCount; ++i) {
4160 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4161 return VK_SUCCESS;
4162 }
4163 }
4164 return VK_TIMEOUT;
4165 }
4166
4167 for (uint32_t i = 0; i < fenceCount; ++i) {
4168 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4169 bool expired = false;
4170
4171 if (fence->temp_syncobj) {
4172 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4173 return VK_TIMEOUT;
4174 continue;
4175 }
4176
4177 if (fence->syncobj) {
4178 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4179 return VK_TIMEOUT;
4180 continue;
4181 }
4182
4183 if (fence->fence) {
4184 if (!device->ws->is_fence_waitable(fence->fence)) {
4185 while(!device->ws->is_fence_waitable(fence->fence) &&
4186 radv_get_current_time() <= timeout)
4187 /* Do nothing */;
4188 }
4189
4190 expired = device->ws->fence_wait(device->ws,
4191 fence->fence,
4192 true, timeout);
4193 if (!expired)
4194 return VK_TIMEOUT;
4195 }
4196
4197 if (fence->fence_wsi) {
4198 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4199 if (result != VK_SUCCESS)
4200 return result;
4201 }
4202 }
4203
4204 return VK_SUCCESS;
4205 }
4206
4207 VkResult radv_ResetFences(VkDevice _device,
4208 uint32_t fenceCount,
4209 const VkFence *pFences)
4210 {
4211 RADV_FROM_HANDLE(radv_device, device, _device);
4212
4213 for (unsigned i = 0; i < fenceCount; ++i) {
4214 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4215 if (fence->fence)
4216 device->ws->reset_fence(fence->fence);
4217
4218 /* Per spec, we first restore the permanent payload, and then reset, so
4219 * having a temp syncobj should not skip resetting the permanent syncobj. */
4220 if (fence->temp_syncobj) {
4221 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4222 fence->temp_syncobj = 0;
4223 }
4224
4225 if (fence->syncobj) {
4226 device->ws->reset_syncobj(device->ws, fence->syncobj);
4227 }
4228 }
4229
4230 return VK_SUCCESS;
4231 }
4232
4233 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4234 {
4235 RADV_FROM_HANDLE(radv_device, device, _device);
4236 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4237
4238 if (fence->temp_syncobj) {
4239 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4240 return success ? VK_SUCCESS : VK_NOT_READY;
4241 }
4242
4243 if (fence->syncobj) {
4244 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4245 return success ? VK_SUCCESS : VK_NOT_READY;
4246 }
4247
4248 if (fence->fence) {
4249 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4250 return VK_NOT_READY;
4251 }
4252 if (fence->fence_wsi) {
4253 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4254
4255 if (result != VK_SUCCESS) {
4256 if (result == VK_TIMEOUT)
4257 return VK_NOT_READY;
4258 return result;
4259 }
4260 }
4261 return VK_SUCCESS;
4262 }
4263
4264
4265 // Queue semaphore functions
4266
4267 VkResult radv_CreateSemaphore(
4268 VkDevice _device,
4269 const VkSemaphoreCreateInfo* pCreateInfo,
4270 const VkAllocationCallbacks* pAllocator,
4271 VkSemaphore* pSemaphore)
4272 {
4273 RADV_FROM_HANDLE(radv_device, device, _device);
4274 const VkExportSemaphoreCreateInfo *export =
4275 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4276 VkExternalSemaphoreHandleTypeFlags handleTypes =
4277 export ? export->handleTypes : 0;
4278
4279 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4280 sizeof(*sem), 8,
4281 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4282 if (!sem)
4283 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4284
4285 sem->temp_syncobj = 0;
4286 /* create a syncobject if we are going to export this semaphore */
4287 if (device->always_use_syncobj || handleTypes) {
4288 assert (device->physical_device->rad_info.has_syncobj);
4289 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4290 if (ret) {
4291 vk_free2(&device->alloc, pAllocator, sem);
4292 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4293 }
4294 sem->sem = NULL;
4295 } else {
4296 sem->sem = device->ws->create_sem(device->ws);
4297 if (!sem->sem) {
4298 vk_free2(&device->alloc, pAllocator, sem);
4299 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4300 }
4301 sem->syncobj = 0;
4302 }
4303
4304 *pSemaphore = radv_semaphore_to_handle(sem);
4305 return VK_SUCCESS;
4306 }
4307
4308 void radv_DestroySemaphore(
4309 VkDevice _device,
4310 VkSemaphore _semaphore,
4311 const VkAllocationCallbacks* pAllocator)
4312 {
4313 RADV_FROM_HANDLE(radv_device, device, _device);
4314 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4315 if (!_semaphore)
4316 return;
4317
4318 if (sem->syncobj)
4319 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4320 else
4321 device->ws->destroy_sem(sem->sem);
4322 vk_free2(&device->alloc, pAllocator, sem);
4323 }
4324
4325 VkResult radv_CreateEvent(
4326 VkDevice _device,
4327 const VkEventCreateInfo* pCreateInfo,
4328 const VkAllocationCallbacks* pAllocator,
4329 VkEvent* pEvent)
4330 {
4331 RADV_FROM_HANDLE(radv_device, device, _device);
4332 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4333 sizeof(*event), 8,
4334 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4335
4336 if (!event)
4337 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4338
4339 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4340 RADEON_DOMAIN_GTT,
4341 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4342 RADV_BO_PRIORITY_FENCE);
4343 if (!event->bo) {
4344 vk_free2(&device->alloc, pAllocator, event);
4345 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4346 }
4347
4348 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4349
4350 *pEvent = radv_event_to_handle(event);
4351
4352 return VK_SUCCESS;
4353 }
4354
4355 void radv_DestroyEvent(
4356 VkDevice _device,
4357 VkEvent _event,
4358 const VkAllocationCallbacks* pAllocator)
4359 {
4360 RADV_FROM_HANDLE(radv_device, device, _device);
4361 RADV_FROM_HANDLE(radv_event, event, _event);
4362
4363 if (!event)
4364 return;
4365 device->ws->buffer_destroy(event->bo);
4366 vk_free2(&device->alloc, pAllocator, event);
4367 }
4368
4369 VkResult radv_GetEventStatus(
4370 VkDevice _device,
4371 VkEvent _event)
4372 {
4373 RADV_FROM_HANDLE(radv_event, event, _event);
4374
4375 if (*event->map == 1)
4376 return VK_EVENT_SET;
4377 return VK_EVENT_RESET;
4378 }
4379
4380 VkResult radv_SetEvent(
4381 VkDevice _device,
4382 VkEvent _event)
4383 {
4384 RADV_FROM_HANDLE(radv_event, event, _event);
4385 *event->map = 1;
4386
4387 return VK_SUCCESS;
4388 }
4389
4390 VkResult radv_ResetEvent(
4391 VkDevice _device,
4392 VkEvent _event)
4393 {
4394 RADV_FROM_HANDLE(radv_event, event, _event);
4395 *event->map = 0;
4396
4397 return VK_SUCCESS;
4398 }
4399
4400 VkResult radv_CreateBuffer(
4401 VkDevice _device,
4402 const VkBufferCreateInfo* pCreateInfo,
4403 const VkAllocationCallbacks* pAllocator,
4404 VkBuffer* pBuffer)
4405 {
4406 RADV_FROM_HANDLE(radv_device, device, _device);
4407 struct radv_buffer *buffer;
4408
4409 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4410
4411 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4412 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4413 if (buffer == NULL)
4414 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4415
4416 buffer->size = pCreateInfo->size;
4417 buffer->usage = pCreateInfo->usage;
4418 buffer->bo = NULL;
4419 buffer->offset = 0;
4420 buffer->flags = pCreateInfo->flags;
4421
4422 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4423 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4424
4425 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4426 buffer->bo = device->ws->buffer_create(device->ws,
4427 align64(buffer->size, 4096),
4428 4096, 0, RADEON_FLAG_VIRTUAL,
4429 RADV_BO_PRIORITY_VIRTUAL);
4430 if (!buffer->bo) {
4431 vk_free2(&device->alloc, pAllocator, buffer);
4432 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4433 }
4434 }
4435
4436 *pBuffer = radv_buffer_to_handle(buffer);
4437
4438 return VK_SUCCESS;
4439 }
4440
4441 void radv_DestroyBuffer(
4442 VkDevice _device,
4443 VkBuffer _buffer,
4444 const VkAllocationCallbacks* pAllocator)
4445 {
4446 RADV_FROM_HANDLE(radv_device, device, _device);
4447 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4448
4449 if (!buffer)
4450 return;
4451
4452 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4453 device->ws->buffer_destroy(buffer->bo);
4454
4455 vk_free2(&device->alloc, pAllocator, buffer);
4456 }
4457
4458 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4459 VkDevice device,
4460 const VkBufferDeviceAddressInfoEXT* pInfo)
4461 {
4462 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4463 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4464 }
4465
4466
4467 static inline unsigned
4468 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4469 {
4470 if (stencil)
4471 return plane->surface.u.legacy.stencil_tiling_index[level];
4472 else
4473 return plane->surface.u.legacy.tiling_index[level];
4474 }
4475
4476 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4477 {
4478 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4479 }
4480
4481 static uint32_t
4482 radv_init_dcc_control_reg(struct radv_device *device,
4483 struct radv_image_view *iview)
4484 {
4485 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4486 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4487 unsigned max_compressed_block_size;
4488 unsigned independent_128b_blocks;
4489 unsigned independent_64b_blocks;
4490
4491 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4492 return 0;
4493
4494 if (!device->physical_device->rad_info.has_dedicated_vram) {
4495 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4496 * dGPU and 64 for APU because all of our APUs to date use
4497 * DIMMs which have a request granularity size of 64B while all
4498 * other chips have a 32B request size.
4499 */
4500 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4501 }
4502
4503 if (device->physical_device->rad_info.chip_class >= GFX10) {
4504 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4505 independent_64b_blocks = 0;
4506 independent_128b_blocks = 1;
4507 } else {
4508 independent_128b_blocks = 0;
4509
4510 if (iview->image->info.samples > 1) {
4511 if (iview->image->planes[0].surface.bpe == 1)
4512 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4513 else if (iview->image->planes[0].surface.bpe == 2)
4514 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4515 }
4516
4517 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4518 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4519 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4520 /* If this DCC image is potentially going to be used in texture
4521 * fetches, we need some special settings.
4522 */
4523 independent_64b_blocks = 1;
4524 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4525 } else {
4526 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4527 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4528 * big as possible for better compression state.
4529 */
4530 independent_64b_blocks = 0;
4531 max_compressed_block_size = max_uncompressed_block_size;
4532 }
4533 }
4534
4535 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4536 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4537 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4538 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4539 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4540 }
4541
4542 void
4543 radv_initialise_color_surface(struct radv_device *device,
4544 struct radv_color_buffer_info *cb,
4545 struct radv_image_view *iview)
4546 {
4547 const struct vk_format_description *desc;
4548 unsigned ntype, format, swap, endian;
4549 unsigned blend_clamp = 0, blend_bypass = 0;
4550 uint64_t va;
4551 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4552 const struct radeon_surf *surf = &plane->surface;
4553
4554 desc = vk_format_description(iview->vk_format);
4555
4556 memset(cb, 0, sizeof(*cb));
4557
4558 /* Intensity is implemented as Red, so treat it that way. */
4559 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4560
4561 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4562
4563 cb->cb_color_base = va >> 8;
4564
4565 if (device->physical_device->rad_info.chip_class >= GFX9) {
4566 struct gfx9_surf_meta_flags meta;
4567 if (iview->image->dcc_offset)
4568 meta = surf->u.gfx9.dcc;
4569 else
4570 meta = surf->u.gfx9.cmask;
4571
4572 if (device->physical_device->rad_info.chip_class >= GFX10) {
4573 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4574 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4575 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4576 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4577 } else {
4578 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4579 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4580 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4581 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4582 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4583 }
4584
4585 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4586 cb->cb_color_base |= surf->tile_swizzle;
4587 } else {
4588 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4589 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4590
4591 cb->cb_color_base += level_info->offset >> 8;
4592 if (level_info->mode == RADEON_SURF_MODE_2D)
4593 cb->cb_color_base |= surf->tile_swizzle;
4594
4595 pitch_tile_max = level_info->nblk_x / 8 - 1;
4596 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4597 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4598
4599 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4600 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4601 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4602
4603 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4604
4605 if (radv_image_has_fmask(iview->image)) {
4606 if (device->physical_device->rad_info.chip_class >= GFX7)
4607 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4608 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4609 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4610 } else {
4611 /* This must be set for fast clear to work without FMASK. */
4612 if (device->physical_device->rad_info.chip_class >= GFX7)
4613 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4614 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4615 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4616 }
4617 }
4618
4619 /* CMASK variables */
4620 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4621 va += iview->image->cmask_offset;
4622 cb->cb_color_cmask = va >> 8;
4623
4624 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4625 va += iview->image->dcc_offset;
4626
4627 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4628 device->physical_device->rad_info.chip_class <= GFX8)
4629 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4630
4631 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4632 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4633
4634 cb->cb_dcc_base = va >> 8;
4635 cb->cb_dcc_base |= dcc_tile_swizzle;
4636
4637 /* GFX10 field has the same base shift as the GFX6 field. */
4638 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4639 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4640 S_028C6C_SLICE_MAX_GFX10(max_slice);
4641
4642 if (iview->image->info.samples > 1) {
4643 unsigned log_samples = util_logbase2(iview->image->info.samples);
4644
4645 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4646 S_028C74_NUM_FRAGMENTS(log_samples);
4647 }
4648
4649 if (radv_image_has_fmask(iview->image)) {
4650 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4651 cb->cb_color_fmask = va >> 8;
4652 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4653 } else {
4654 cb->cb_color_fmask = cb->cb_color_base;
4655 }
4656
4657 ntype = radv_translate_color_numformat(iview->vk_format,
4658 desc,
4659 vk_format_get_first_non_void_channel(iview->vk_format));
4660 format = radv_translate_colorformat(iview->vk_format);
4661 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4662 radv_finishme("Illegal color\n");
4663 swap = radv_translate_colorswap(iview->vk_format, false);
4664 endian = radv_colorformat_endian_swap(format);
4665
4666 /* blend clamp should be set for all NORM/SRGB types */
4667 if (ntype == V_028C70_NUMBER_UNORM ||
4668 ntype == V_028C70_NUMBER_SNORM ||
4669 ntype == V_028C70_NUMBER_SRGB)
4670 blend_clamp = 1;
4671
4672 /* set blend bypass according to docs if SINT/UINT or
4673 8/24 COLOR variants */
4674 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4675 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4676 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4677 blend_clamp = 0;
4678 blend_bypass = 1;
4679 }
4680 #if 0
4681 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4682 (format == V_028C70_COLOR_8 ||
4683 format == V_028C70_COLOR_8_8 ||
4684 format == V_028C70_COLOR_8_8_8_8))
4685 ->color_is_int8 = true;
4686 #endif
4687 cb->cb_color_info = S_028C70_FORMAT(format) |
4688 S_028C70_COMP_SWAP(swap) |
4689 S_028C70_BLEND_CLAMP(blend_clamp) |
4690 S_028C70_BLEND_BYPASS(blend_bypass) |
4691 S_028C70_SIMPLE_FLOAT(1) |
4692 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4693 ntype != V_028C70_NUMBER_SNORM &&
4694 ntype != V_028C70_NUMBER_SRGB &&
4695 format != V_028C70_COLOR_8_24 &&
4696 format != V_028C70_COLOR_24_8) |
4697 S_028C70_NUMBER_TYPE(ntype) |
4698 S_028C70_ENDIAN(endian);
4699 if (radv_image_has_fmask(iview->image)) {
4700 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4701 if (device->physical_device->rad_info.chip_class == GFX6) {
4702 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4703 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4704 }
4705
4706 if (radv_image_is_tc_compat_cmask(iview->image)) {
4707 /* Allow the texture block to read FMASK directly
4708 * without decompressing it. This bit must be cleared
4709 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4710 * otherwise the operation doesn't happen.
4711 */
4712 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4713
4714 /* Set CMASK into a tiling format that allows the
4715 * texture block to read it.
4716 */
4717 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4718 }
4719 }
4720
4721 if (radv_image_has_cmask(iview->image) &&
4722 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4723 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4724
4725 if (radv_dcc_enabled(iview->image, iview->base_mip))
4726 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4727
4728 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4729
4730 /* This must be set for fast clear to work without FMASK. */
4731 if (!radv_image_has_fmask(iview->image) &&
4732 device->physical_device->rad_info.chip_class == GFX6) {
4733 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4734 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4735 }
4736
4737 if (device->physical_device->rad_info.chip_class >= GFX9) {
4738 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4739
4740 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4741 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4742 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4743 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4744
4745 if (device->physical_device->rad_info.chip_class >= GFX10) {
4746 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4747
4748 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4749 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4750 S_028EE0_RESOURCE_LEVEL(1);
4751 } else {
4752 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4753 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4754 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4755 }
4756
4757 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4758 S_028C68_MIP0_HEIGHT(height - 1) |
4759 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4760 }
4761 }
4762
4763 static unsigned
4764 radv_calc_decompress_on_z_planes(struct radv_device *device,
4765 struct radv_image_view *iview)
4766 {
4767 unsigned max_zplanes = 0;
4768
4769 assert(radv_image_is_tc_compat_htile(iview->image));
4770
4771 if (device->physical_device->rad_info.chip_class >= GFX9) {
4772 /* Default value for 32-bit depth surfaces. */
4773 max_zplanes = 4;
4774
4775 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4776 iview->image->info.samples > 1)
4777 max_zplanes = 2;
4778
4779 max_zplanes = max_zplanes + 1;
4780 } else {
4781 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4782 /* Do not enable Z plane compression for 16-bit depth
4783 * surfaces because isn't supported on GFX8. Only
4784 * 32-bit depth surfaces are supported by the hardware.
4785 * This allows to maintain shader compatibility and to
4786 * reduce the number of depth decompressions.
4787 */
4788 max_zplanes = 1;
4789 } else {
4790 if (iview->image->info.samples <= 1)
4791 max_zplanes = 5;
4792 else if (iview->image->info.samples <= 4)
4793 max_zplanes = 3;
4794 else
4795 max_zplanes = 2;
4796 }
4797 }
4798
4799 return max_zplanes;
4800 }
4801
4802 void
4803 radv_initialise_ds_surface(struct radv_device *device,
4804 struct radv_ds_buffer_info *ds,
4805 struct radv_image_view *iview)
4806 {
4807 unsigned level = iview->base_mip;
4808 unsigned format, stencil_format;
4809 uint64_t va, s_offs, z_offs;
4810 bool stencil_only = false;
4811 const struct radv_image_plane *plane = &iview->image->planes[0];
4812 const struct radeon_surf *surf = &plane->surface;
4813
4814 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4815
4816 memset(ds, 0, sizeof(*ds));
4817 switch (iview->image->vk_format) {
4818 case VK_FORMAT_D24_UNORM_S8_UINT:
4819 case VK_FORMAT_X8_D24_UNORM_PACK32:
4820 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4821 ds->offset_scale = 2.0f;
4822 break;
4823 case VK_FORMAT_D16_UNORM:
4824 case VK_FORMAT_D16_UNORM_S8_UINT:
4825 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4826 ds->offset_scale = 4.0f;
4827 break;
4828 case VK_FORMAT_D32_SFLOAT:
4829 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4830 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4831 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4832 ds->offset_scale = 1.0f;
4833 break;
4834 case VK_FORMAT_S8_UINT:
4835 stencil_only = true;
4836 break;
4837 default:
4838 break;
4839 }
4840
4841 format = radv_translate_dbformat(iview->image->vk_format);
4842 stencil_format = surf->has_stencil ?
4843 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4844
4845 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4846 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4847 S_028008_SLICE_MAX(max_slice);
4848 if (device->physical_device->rad_info.chip_class >= GFX10) {
4849 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4850 S_028008_SLICE_MAX_HI(max_slice >> 11);
4851 }
4852
4853 ds->db_htile_data_base = 0;
4854 ds->db_htile_surface = 0;
4855
4856 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4857 s_offs = z_offs = va;
4858
4859 if (device->physical_device->rad_info.chip_class >= GFX9) {
4860 assert(surf->u.gfx9.surf_offset == 0);
4861 s_offs += surf->u.gfx9.stencil_offset;
4862
4863 ds->db_z_info = S_028038_FORMAT(format) |
4864 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4865 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4866 S_028038_MAXMIP(iview->image->info.levels - 1) |
4867 S_028038_ZRANGE_PRECISION(1);
4868 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4869 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4870
4871 if (device->physical_device->rad_info.chip_class == GFX9) {
4872 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4873 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4874 }
4875
4876 ds->db_depth_view |= S_028008_MIPID(level);
4877 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4878 S_02801C_Y_MAX(iview->image->info.height - 1);
4879
4880 if (radv_htile_enabled(iview->image, level)) {
4881 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4882
4883 if (radv_image_is_tc_compat_htile(iview->image)) {
4884 unsigned max_zplanes =
4885 radv_calc_decompress_on_z_planes(device, iview);
4886
4887 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4888
4889 if (device->physical_device->rad_info.chip_class >= GFX10) {
4890 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4891 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4892 } else {
4893 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4894 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4895 }
4896 }
4897
4898 if (!surf->has_stencil)
4899 /* Use all of the htile_buffer for depth if there's no stencil. */
4900 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4901 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4902 iview->image->htile_offset;
4903 ds->db_htile_data_base = va >> 8;
4904 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4905 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4906
4907 if (device->physical_device->rad_info.chip_class == GFX9) {
4908 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4909 }
4910 }
4911 } else {
4912 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4913
4914 if (stencil_only)
4915 level_info = &surf->u.legacy.stencil_level[level];
4916
4917 z_offs += surf->u.legacy.level[level].offset;
4918 s_offs += surf->u.legacy.stencil_level[level].offset;
4919
4920 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4921 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4922 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4923
4924 if (iview->image->info.samples > 1)
4925 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4926
4927 if (device->physical_device->rad_info.chip_class >= GFX7) {
4928 struct radeon_info *info = &device->physical_device->rad_info;
4929 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4930 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4931 unsigned macro_index = surf->u.legacy.macro_tile_index;
4932 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4933 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4934 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4935
4936 if (stencil_only)
4937 tile_mode = stencil_tile_mode;
4938
4939 ds->db_depth_info |=
4940 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4941 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4942 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4943 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4944 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4945 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4946 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4947 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4948 } else {
4949 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4950 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4951 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4952 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4953 if (stencil_only)
4954 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4955 }
4956
4957 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4958 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4959 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4960
4961 if (radv_htile_enabled(iview->image, level)) {
4962 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4963
4964 if (!surf->has_stencil &&
4965 !radv_image_is_tc_compat_htile(iview->image))
4966 /* Use all of the htile_buffer for depth if there's no stencil. */
4967 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4968
4969 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4970 iview->image->htile_offset;
4971 ds->db_htile_data_base = va >> 8;
4972 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4973
4974 if (radv_image_is_tc_compat_htile(iview->image)) {
4975 unsigned max_zplanes =
4976 radv_calc_decompress_on_z_planes(device, iview);
4977
4978 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4979 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4980 }
4981 }
4982 }
4983
4984 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4985 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4986 }
4987
4988 VkResult radv_CreateFramebuffer(
4989 VkDevice _device,
4990 const VkFramebufferCreateInfo* pCreateInfo,
4991 const VkAllocationCallbacks* pAllocator,
4992 VkFramebuffer* pFramebuffer)
4993 {
4994 RADV_FROM_HANDLE(radv_device, device, _device);
4995 struct radv_framebuffer *framebuffer;
4996 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4997 vk_find_struct_const(pCreateInfo->pNext,
4998 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4999
5000 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
5001
5002 size_t size = sizeof(*framebuffer);
5003 if (!imageless_create_info)
5004 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
5005 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
5006 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5007 if (framebuffer == NULL)
5008 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5009
5010 framebuffer->attachment_count = pCreateInfo->attachmentCount;
5011 framebuffer->width = pCreateInfo->width;
5012 framebuffer->height = pCreateInfo->height;
5013 framebuffer->layers = pCreateInfo->layers;
5014 if (imageless_create_info) {
5015 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
5016 const VkFramebufferAttachmentImageInfoKHR *attachment =
5017 imageless_create_info->pAttachmentImageInfos + i;
5018 framebuffer->width = MIN2(framebuffer->width, attachment->width);
5019 framebuffer->height = MIN2(framebuffer->height, attachment->height);
5020 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
5021 }
5022 } else {
5023 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
5024 VkImageView _iview = pCreateInfo->pAttachments[i];
5025 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
5026 framebuffer->attachments[i] = iview;
5027 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
5028 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
5029 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
5030 }
5031 }
5032
5033 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
5034 return VK_SUCCESS;
5035 }
5036
5037 void radv_DestroyFramebuffer(
5038 VkDevice _device,
5039 VkFramebuffer _fb,
5040 const VkAllocationCallbacks* pAllocator)
5041 {
5042 RADV_FROM_HANDLE(radv_device, device, _device);
5043 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
5044
5045 if (!fb)
5046 return;
5047 vk_free2(&device->alloc, pAllocator, fb);
5048 }
5049
5050 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
5051 {
5052 switch (address_mode) {
5053 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
5054 return V_008F30_SQ_TEX_WRAP;
5055 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
5056 return V_008F30_SQ_TEX_MIRROR;
5057 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
5058 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
5059 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
5060 return V_008F30_SQ_TEX_CLAMP_BORDER;
5061 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
5062 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
5063 default:
5064 unreachable("illegal tex wrap mode");
5065 break;
5066 }
5067 }
5068
5069 static unsigned
5070 radv_tex_compare(VkCompareOp op)
5071 {
5072 switch (op) {
5073 case VK_COMPARE_OP_NEVER:
5074 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
5075 case VK_COMPARE_OP_LESS:
5076 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
5077 case VK_COMPARE_OP_EQUAL:
5078 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
5079 case VK_COMPARE_OP_LESS_OR_EQUAL:
5080 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
5081 case VK_COMPARE_OP_GREATER:
5082 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
5083 case VK_COMPARE_OP_NOT_EQUAL:
5084 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
5085 case VK_COMPARE_OP_GREATER_OR_EQUAL:
5086 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
5087 case VK_COMPARE_OP_ALWAYS:
5088 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
5089 default:
5090 unreachable("illegal compare mode");
5091 break;
5092 }
5093 }
5094
5095 static unsigned
5096 radv_tex_filter(VkFilter filter, unsigned max_ansio)
5097 {
5098 switch (filter) {
5099 case VK_FILTER_NEAREST:
5100 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
5101 V_008F38_SQ_TEX_XY_FILTER_POINT);
5102 case VK_FILTER_LINEAR:
5103 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
5104 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
5105 case VK_FILTER_CUBIC_IMG:
5106 default:
5107 fprintf(stderr, "illegal texture filter");
5108 return 0;
5109 }
5110 }
5111
5112 static unsigned
5113 radv_tex_mipfilter(VkSamplerMipmapMode mode)
5114 {
5115 switch (mode) {
5116 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
5117 return V_008F38_SQ_TEX_Z_FILTER_POINT;
5118 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
5119 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
5120 default:
5121 return V_008F38_SQ_TEX_Z_FILTER_NONE;
5122 }
5123 }
5124
5125 static unsigned
5126 radv_tex_bordercolor(VkBorderColor bcolor)
5127 {
5128 switch (bcolor) {
5129 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
5130 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
5131 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
5132 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
5133 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
5134 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
5135 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
5136 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
5137 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
5138 default:
5139 break;
5140 }
5141 return 0;
5142 }
5143
5144 static unsigned
5145 radv_tex_aniso_filter(unsigned filter)
5146 {
5147 if (filter < 2)
5148 return 0;
5149 if (filter < 4)
5150 return 1;
5151 if (filter < 8)
5152 return 2;
5153 if (filter < 16)
5154 return 3;
5155 return 4;
5156 }
5157
5158 static unsigned
5159 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5160 {
5161 switch (mode) {
5162 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5163 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5164 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5165 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5166 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5167 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5168 default:
5169 break;
5170 }
5171 return 0;
5172 }
5173
5174 static uint32_t
5175 radv_get_max_anisotropy(struct radv_device *device,
5176 const VkSamplerCreateInfo *pCreateInfo)
5177 {
5178 if (device->force_aniso >= 0)
5179 return device->force_aniso;
5180
5181 if (pCreateInfo->anisotropyEnable &&
5182 pCreateInfo->maxAnisotropy > 1.0f)
5183 return (uint32_t)pCreateInfo->maxAnisotropy;
5184
5185 return 0;
5186 }
5187
5188 static void
5189 radv_init_sampler(struct radv_device *device,
5190 struct radv_sampler *sampler,
5191 const VkSamplerCreateInfo *pCreateInfo)
5192 {
5193 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5194 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5195 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5196 device->physical_device->rad_info.chip_class == GFX9;
5197 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5198
5199 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5200 vk_find_struct_const(pCreateInfo->pNext,
5201 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5202 if (sampler_reduction)
5203 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5204
5205 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5206 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5207 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5208 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5209 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5210 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5211 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5212 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5213 S_008F30_DISABLE_CUBE_WRAP(0) |
5214 S_008F30_COMPAT_MODE(compat_mode) |
5215 S_008F30_FILTER_MODE(filter_mode));
5216 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5217 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5218 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5219 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5220 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5221 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5222 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5223 S_008F38_MIP_POINT_PRECLAMP(0));
5224 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5225 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5226
5227 if (device->physical_device->rad_info.chip_class >= GFX10) {
5228 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5229 } else {
5230 sampler->state[2] |=
5231 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5232 S_008F38_FILTER_PREC_FIX(1) |
5233 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5234 }
5235 }
5236
5237 VkResult radv_CreateSampler(
5238 VkDevice _device,
5239 const VkSamplerCreateInfo* pCreateInfo,
5240 const VkAllocationCallbacks* pAllocator,
5241 VkSampler* pSampler)
5242 {
5243 RADV_FROM_HANDLE(radv_device, device, _device);
5244 struct radv_sampler *sampler;
5245
5246 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5247 vk_find_struct_const(pCreateInfo->pNext,
5248 SAMPLER_YCBCR_CONVERSION_INFO);
5249
5250 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5251
5252 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5253 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5254 if (!sampler)
5255 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5256
5257 radv_init_sampler(device, sampler, pCreateInfo);
5258
5259 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5260 *pSampler = radv_sampler_to_handle(sampler);
5261
5262 return VK_SUCCESS;
5263 }
5264
5265 void radv_DestroySampler(
5266 VkDevice _device,
5267 VkSampler _sampler,
5268 const VkAllocationCallbacks* pAllocator)
5269 {
5270 RADV_FROM_HANDLE(radv_device, device, _device);
5271 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5272
5273 if (!sampler)
5274 return;
5275 vk_free2(&device->alloc, pAllocator, sampler);
5276 }
5277
5278 /* vk_icd.h does not declare this function, so we declare it here to
5279 * suppress Wmissing-prototypes.
5280 */
5281 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5282 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5283
5284 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5285 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5286 {
5287 /* For the full details on loader interface versioning, see
5288 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5289 * What follows is a condensed summary, to help you navigate the large and
5290 * confusing official doc.
5291 *
5292 * - Loader interface v0 is incompatible with later versions. We don't
5293 * support it.
5294 *
5295 * - In loader interface v1:
5296 * - The first ICD entrypoint called by the loader is
5297 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5298 * entrypoint.
5299 * - The ICD must statically expose no other Vulkan symbol unless it is
5300 * linked with -Bsymbolic.
5301 * - Each dispatchable Vulkan handle created by the ICD must be
5302 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5303 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5304 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5305 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5306 * such loader-managed surfaces.
5307 *
5308 * - Loader interface v2 differs from v1 in:
5309 * - The first ICD entrypoint called by the loader is
5310 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5311 * statically expose this entrypoint.
5312 *
5313 * - Loader interface v3 differs from v2 in:
5314 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5315 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5316 * because the loader no longer does so.
5317 */
5318 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5319 return VK_SUCCESS;
5320 }
5321
5322 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5323 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5324 int *pFD)
5325 {
5326 RADV_FROM_HANDLE(radv_device, device, _device);
5327 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5328
5329 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5330
5331 /* At the moment, we support only the below handle types. */
5332 assert(pGetFdInfo->handleType ==
5333 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5334 pGetFdInfo->handleType ==
5335 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5336
5337 bool ret = radv_get_memory_fd(device, memory, pFD);
5338 if (ret == false)
5339 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5340 return VK_SUCCESS;
5341 }
5342
5343 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5344 VkExternalMemoryHandleTypeFlagBits handleType,
5345 int fd,
5346 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5347 {
5348 RADV_FROM_HANDLE(radv_device, device, _device);
5349
5350 switch (handleType) {
5351 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5352 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5353 return VK_SUCCESS;
5354
5355 default:
5356 /* The valid usage section for this function says:
5357 *
5358 * "handleType must not be one of the handle types defined as
5359 * opaque."
5360 *
5361 * So opaque handle types fall into the default "unsupported" case.
5362 */
5363 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5364 }
5365 }
5366
5367 static VkResult radv_import_opaque_fd(struct radv_device *device,
5368 int fd,
5369 uint32_t *syncobj)
5370 {
5371 uint32_t syncobj_handle = 0;
5372 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5373 if (ret != 0)
5374 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5375
5376 if (*syncobj)
5377 device->ws->destroy_syncobj(device->ws, *syncobj);
5378
5379 *syncobj = syncobj_handle;
5380 close(fd);
5381
5382 return VK_SUCCESS;
5383 }
5384
5385 static VkResult radv_import_sync_fd(struct radv_device *device,
5386 int fd,
5387 uint32_t *syncobj)
5388 {
5389 /* If we create a syncobj we do it locally so that if we have an error, we don't
5390 * leave a syncobj in an undetermined state in the fence. */
5391 uint32_t syncobj_handle = *syncobj;
5392 if (!syncobj_handle) {
5393 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5394 if (ret) {
5395 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5396 }
5397 }
5398
5399 if (fd == -1) {
5400 device->ws->signal_syncobj(device->ws, syncobj_handle);
5401 } else {
5402 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5403 if (ret != 0)
5404 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5405 }
5406
5407 *syncobj = syncobj_handle;
5408 if (fd != -1)
5409 close(fd);
5410
5411 return VK_SUCCESS;
5412 }
5413
5414 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5415 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5416 {
5417 RADV_FROM_HANDLE(radv_device, device, _device);
5418 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5419 uint32_t *syncobj_dst = NULL;
5420
5421 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5422 syncobj_dst = &sem->temp_syncobj;
5423 } else {
5424 syncobj_dst = &sem->syncobj;
5425 }
5426
5427 switch(pImportSemaphoreFdInfo->handleType) {
5428 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5429 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5430 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5431 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5432 default:
5433 unreachable("Unhandled semaphore handle type");
5434 }
5435 }
5436
5437 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5438 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5439 int *pFd)
5440 {
5441 RADV_FROM_HANDLE(radv_device, device, _device);
5442 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5443 int ret;
5444 uint32_t syncobj_handle;
5445
5446 if (sem->temp_syncobj)
5447 syncobj_handle = sem->temp_syncobj;
5448 else
5449 syncobj_handle = sem->syncobj;
5450
5451 switch(pGetFdInfo->handleType) {
5452 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5453 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5454 break;
5455 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5456 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5457 if (!ret) {
5458 if (sem->temp_syncobj) {
5459 close (sem->temp_syncobj);
5460 sem->temp_syncobj = 0;
5461 } else {
5462 device->ws->reset_syncobj(device->ws, syncobj_handle);
5463 }
5464 }
5465 break;
5466 default:
5467 unreachable("Unhandled semaphore handle type");
5468 }
5469
5470 if (ret)
5471 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5472 return VK_SUCCESS;
5473 }
5474
5475 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5476 VkPhysicalDevice physicalDevice,
5477 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5478 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5479 {
5480 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5481
5482 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5483 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5484 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5485 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5486 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5487 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5488 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5489 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5490 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5491 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5492 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5493 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5494 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5495 } else {
5496 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5497 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5498 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5499 }
5500 }
5501
5502 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5503 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5504 {
5505 RADV_FROM_HANDLE(radv_device, device, _device);
5506 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5507 uint32_t *syncobj_dst = NULL;
5508
5509
5510 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5511 syncobj_dst = &fence->temp_syncobj;
5512 } else {
5513 syncobj_dst = &fence->syncobj;
5514 }
5515
5516 switch(pImportFenceFdInfo->handleType) {
5517 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5518 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5519 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5520 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5521 default:
5522 unreachable("Unhandled fence handle type");
5523 }
5524 }
5525
5526 VkResult radv_GetFenceFdKHR(VkDevice _device,
5527 const VkFenceGetFdInfoKHR *pGetFdInfo,
5528 int *pFd)
5529 {
5530 RADV_FROM_HANDLE(radv_device, device, _device);
5531 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5532 int ret;
5533 uint32_t syncobj_handle;
5534
5535 if (fence->temp_syncobj)
5536 syncobj_handle = fence->temp_syncobj;
5537 else
5538 syncobj_handle = fence->syncobj;
5539
5540 switch(pGetFdInfo->handleType) {
5541 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5542 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5543 break;
5544 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5545 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5546 if (!ret) {
5547 if (fence->temp_syncobj) {
5548 close (fence->temp_syncobj);
5549 fence->temp_syncobj = 0;
5550 } else {
5551 device->ws->reset_syncobj(device->ws, syncobj_handle);
5552 }
5553 }
5554 break;
5555 default:
5556 unreachable("Unhandled fence handle type");
5557 }
5558
5559 if (ret)
5560 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5561 return VK_SUCCESS;
5562 }
5563
5564 void radv_GetPhysicalDeviceExternalFenceProperties(
5565 VkPhysicalDevice physicalDevice,
5566 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5567 VkExternalFenceProperties *pExternalFenceProperties)
5568 {
5569 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5570
5571 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5572 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5573 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5574 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5575 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5576 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5577 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5578 } else {
5579 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5580 pExternalFenceProperties->compatibleHandleTypes = 0;
5581 pExternalFenceProperties->externalFenceFeatures = 0;
5582 }
5583 }
5584
5585 VkResult
5586 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5587 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5588 const VkAllocationCallbacks* pAllocator,
5589 VkDebugReportCallbackEXT* pCallback)
5590 {
5591 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5592 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5593 pCreateInfo, pAllocator, &instance->alloc,
5594 pCallback);
5595 }
5596
5597 void
5598 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5599 VkDebugReportCallbackEXT _callback,
5600 const VkAllocationCallbacks* pAllocator)
5601 {
5602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5603 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5604 _callback, pAllocator, &instance->alloc);
5605 }
5606
5607 void
5608 radv_DebugReportMessageEXT(VkInstance _instance,
5609 VkDebugReportFlagsEXT flags,
5610 VkDebugReportObjectTypeEXT objectType,
5611 uint64_t object,
5612 size_t location,
5613 int32_t messageCode,
5614 const char* pLayerPrefix,
5615 const char* pMessage)
5616 {
5617 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5618 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5619 object, location, messageCode, pLayerPrefix, pMessage);
5620 }
5621
5622 void
5623 radv_GetDeviceGroupPeerMemoryFeatures(
5624 VkDevice device,
5625 uint32_t heapIndex,
5626 uint32_t localDeviceIndex,
5627 uint32_t remoteDeviceIndex,
5628 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5629 {
5630 assert(localDeviceIndex == remoteDeviceIndex);
5631
5632 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5633 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5634 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5635 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5636 }
5637
5638 static const VkTimeDomainEXT radv_time_domains[] = {
5639 VK_TIME_DOMAIN_DEVICE_EXT,
5640 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5641 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5642 };
5643
5644 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5645 VkPhysicalDevice physicalDevice,
5646 uint32_t *pTimeDomainCount,
5647 VkTimeDomainEXT *pTimeDomains)
5648 {
5649 int d;
5650 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5651
5652 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5653 vk_outarray_append(&out, i) {
5654 *i = radv_time_domains[d];
5655 }
5656 }
5657
5658 return vk_outarray_status(&out);
5659 }
5660
5661 static uint64_t
5662 radv_clock_gettime(clockid_t clock_id)
5663 {
5664 struct timespec current;
5665 int ret;
5666
5667 ret = clock_gettime(clock_id, &current);
5668 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5669 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5670 if (ret < 0)
5671 return 0;
5672
5673 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5674 }
5675
5676 VkResult radv_GetCalibratedTimestampsEXT(
5677 VkDevice _device,
5678 uint32_t timestampCount,
5679 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5680 uint64_t *pTimestamps,
5681 uint64_t *pMaxDeviation)
5682 {
5683 RADV_FROM_HANDLE(radv_device, device, _device);
5684 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5685 int d;
5686 uint64_t begin, end;
5687 uint64_t max_clock_period = 0;
5688
5689 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5690
5691 for (d = 0; d < timestampCount; d++) {
5692 switch (pTimestampInfos[d].timeDomain) {
5693 case VK_TIME_DOMAIN_DEVICE_EXT:
5694 pTimestamps[d] = device->ws->query_value(device->ws,
5695 RADEON_TIMESTAMP);
5696 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5697 max_clock_period = MAX2(max_clock_period, device_period);
5698 break;
5699 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5700 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5701 max_clock_period = MAX2(max_clock_period, 1);
5702 break;
5703
5704 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5705 pTimestamps[d] = begin;
5706 break;
5707 default:
5708 pTimestamps[d] = 0;
5709 break;
5710 }
5711 }
5712
5713 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5714
5715 /*
5716 * The maximum deviation is the sum of the interval over which we
5717 * perform the sampling and the maximum period of any sampled
5718 * clock. That's because the maximum skew between any two sampled
5719 * clock edges is when the sampled clock with the largest period is
5720 * sampled at the end of that period but right at the beginning of the
5721 * sampling interval and some other clock is sampled right at the
5722 * begining of its sampling period and right at the end of the
5723 * sampling interval. Let's assume the GPU has the longest clock
5724 * period and that the application is sampling GPU and monotonic:
5725 *
5726 * s e
5727 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5728 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5729 *
5730 * g
5731 * 0 1 2 3
5732 * GPU -----_____-----_____-----_____-----_____
5733 *
5734 * m
5735 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5736 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5737 *
5738 * Interval <----------------->
5739 * Deviation <-------------------------->
5740 *
5741 * s = read(raw) 2
5742 * g = read(GPU) 1
5743 * m = read(monotonic) 2
5744 * e = read(raw) b
5745 *
5746 * We round the sample interval up by one tick to cover sampling error
5747 * in the interval clock
5748 */
5749
5750 uint64_t sample_interval = end - begin + 1;
5751
5752 *pMaxDeviation = sample_interval + max_clock_period;
5753
5754 return VK_SUCCESS;
5755 }
5756
5757 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5758 VkPhysicalDevice physicalDevice,
5759 VkSampleCountFlagBits samples,
5760 VkMultisamplePropertiesEXT* pMultisampleProperties)
5761 {
5762 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5763 VK_SAMPLE_COUNT_4_BIT |
5764 VK_SAMPLE_COUNT_8_BIT)) {
5765 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5766 } else {
5767 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5768 }
5769 }