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radv: Add support for driconf.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
121 }
122
123 static uint64_t
124 radv_get_visible_vram_size(struct radv_physical_device *device)
125 {
126 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
127 }
128
129 static uint64_t
130 radv_get_vram_size(struct radv_physical_device *device)
131 {
132 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
133 }
134
135 static void
136 radv_physical_device_init_mem_types(struct radv_physical_device *device)
137 {
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
139 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
140 uint64_t vram_size = radv_get_vram_size(device);
141 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
142 device->memory_properties.memoryHeapCount = 0;
143 if (vram_size > 0) {
144 vram_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
146 .size = vram_size,
147 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150 if (visible_vram_size) {
151 visible_vram_index = device->memory_properties.memoryHeapCount++;
152 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
153 .size = visible_vram_size,
154 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
155 };
156 }
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
162 };
163 }
164
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
166 unsigned type_count = 0;
167 if (vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
185 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
186 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
189 .heapIndex = visible_vram_index,
190 };
191 }
192 if (gart_index >= 0) {
193 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
194 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
195 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
198 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 .heapIndex = gart_index,
200 };
201 }
202 device->memory_properties.memoryTypeCount = type_count;
203 }
204
205 static void
206 radv_handle_env_var_force_family(struct radv_physical_device *device)
207 {
208 const char *family = getenv("RADV_FORCE_FAMILY");
209 unsigned i;
210
211 if (!family)
212 return;
213
214 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
215 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
216 /* Override family and chip_class. */
217 device->rad_info.family = i;
218
219 if (i >= CHIP_VEGA10)
220 device->rad_info.chip_class = GFX9;
221 else if (i >= CHIP_TONGA)
222 device->rad_info.chip_class = VI;
223 else if (i >= CHIP_BONAIRE)
224 device->rad_info.chip_class = CIK;
225 else
226 device->rad_info.chip_class = SI;
227
228 return;
229 }
230 }
231
232 fprintf(stderr, "radv: Unknown family: %s\n", family);
233 exit(1);
234 }
235
236 static VkResult
237 radv_physical_device_init(struct radv_physical_device *device,
238 struct radv_instance *instance,
239 drmDevicePtr drm_device)
240 {
241 const char *path = drm_device->nodes[DRM_NODE_RENDER];
242 VkResult result;
243 drmVersionPtr version;
244 int fd;
245 int master_fd = -1;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0) {
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Could not open device '%s'", path);
251
252 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
253 }
254
255 version = drmGetVersion(fd);
256 if (!version) {
257 close(fd);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not get the kernel driver version for device '%s'", path);
261
262 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
263 "failed to get version %s: %m", path);
264 }
265
266 if (strcmp(version->name, "amdgpu")) {
267 drmFreeVersion(version);
268 close(fd);
269
270 if (instance->debug_flags & RADV_DEBUG_STARTUP)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
272
273 return VK_ERROR_INCOMPATIBLE_DRIVER;
274 }
275 drmFreeVersion(version);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Found compatible device '%s'.", path);
279
280 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 device->instance = instance;
282
283 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
284 instance->perftest_flags);
285 if (!device->ws) {
286 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
287 goto fail;
288 }
289
290 if (instance->enabled_extensions.KHR_display) {
291 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
292 if (master_fd >= 0) {
293 uint32_t accel_working = 0;
294 struct drm_amdgpu_info request = {
295 .return_pointer = (uintptr_t)&accel_working,
296 .return_size = sizeof(accel_working),
297 .query = AMDGPU_INFO_ACCEL_WORKING
298 };
299
300 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
301 close(master_fd);
302 master_fd = -1;
303 }
304 }
305 }
306
307 device->master_fd = master_fd;
308 device->local_fd = fd;
309 device->ws->query_info(device->ws, &device->rad_info);
310
311 radv_handle_env_var_force_family(device);
312
313 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
314
315 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
316 device->ws->destroy(device->ws);
317 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags =
324 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
325 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
326
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
329 */
330 char buf[VK_UUID_SIZE * 2 + 1];
331 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
332 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
333
334 if (device->rad_info.chip_class < VI ||
335 device->rad_info.chip_class > GFX9)
336 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337
338 radv_get_driver_uuid(&device->driver_uuid);
339 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
340
341 if (device->rad_info.family == CHIP_STONEY ||
342 device->rad_info.chip_class >= GFX9) {
343 device->has_rbplus = true;
344 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
345 device->rad_info.family == CHIP_VEGA12 ||
346 device->rad_info.family == CHIP_RAVEN ||
347 device->rad_info.family == CHIP_RAVEN2;
348 }
349
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
351 * on SI.
352 */
353 device->has_clear_state = device->rad_info.chip_class >= CIK;
354
355 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
356
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
359 device->rad_info.family == CHIP_RAVEN;
360
361 /* Out-of-order primitive rasterization. */
362 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
363 device->rad_info.max_se >= 2;
364 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
365 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
366
367 device->dcc_msaa_allowed =
368 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
369
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
371 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
372 (device->rad_info.chip_class >= VI &&
373 device->rad_info.me_fw_feature >= 41);
374
375 radv_physical_device_init_mem_types(device);
376 radv_fill_device_extension_table(device, &device->supported_extensions);
377
378 device->bus_info = *drm_device->businfo.pci;
379
380 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
381 ac_print_gpu_info(&device->rad_info);
382
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
385 * semi-layers).
386 */
387 result = radv_init_wsi(device);
388 if (result != VK_SUCCESS) {
389 device->ws->destroy(device->ws);
390 vk_error(instance, result);
391 goto fail;
392 }
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {"nobinning", RADV_DEBUG_NOBINNING},
466 {NULL, 0}
467 };
468
469 const char *
470 radv_get_debug_option_name(int id)
471 {
472 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
473 return radv_debug_options[id].string;
474 }
475
476 static const struct debug_control radv_perftest_options[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
478 {"sisched", RADV_PERFTEST_SISCHED},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
481 {"bolist", RADV_PERFTEST_BO_LIST},
482 {NULL, 0}
483 };
484
485 const char *
486 radv_get_perftest_option_name(int id)
487 {
488 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
489 return radv_perftest_options[id].string;
490 }
491
492 static void
493 radv_handle_per_app_options(struct radv_instance *instance,
494 const VkApplicationInfo *info)
495 {
496 const char *name = info ? info->pApplicationName : NULL;
497
498 if (!name)
499 return;
500
501 if (!strcmp(name, "Talos - Linux - 32bit") ||
502 !strcmp(name, "Talos - Linux - 64bit")) {
503 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
506 */
507 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
508 }
509 } else if (!strcmp(name, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
512 }
513 }
514
515 static int radv_get_instance_extension_index(const char *name)
516 {
517 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
518 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
519 return i;
520 }
521 return -1;
522 }
523
524 static const char radv_dri_options_xml[] =
525 DRI_CONF_BEGIN
526 DRI_CONF_END;
527
528 static void radv_init_dri_options(struct radv_instance *instance)
529 {
530 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
531 driParseConfigFiles(&instance->dri_options,
532 &instance->available_dri_options,
533 0, "radv", NULL);
534 }
535
536 VkResult radv_CreateInstance(
537 const VkInstanceCreateInfo* pCreateInfo,
538 const VkAllocationCallbacks* pAllocator,
539 VkInstance* pInstance)
540 {
541 struct radv_instance *instance;
542 VkResult result;
543
544 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
545
546 uint32_t client_version;
547 if (pCreateInfo->pApplicationInfo &&
548 pCreateInfo->pApplicationInfo->apiVersion != 0) {
549 client_version = pCreateInfo->pApplicationInfo->apiVersion;
550 } else {
551 client_version = VK_API_VERSION_1_0;
552 }
553
554 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
555 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
556 if (!instance)
557 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
558
559 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
560
561 if (pAllocator)
562 instance->alloc = *pAllocator;
563 else
564 instance->alloc = default_alloc;
565
566 instance->apiVersion = client_version;
567 instance->physicalDeviceCount = -1;
568
569 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
570 radv_debug_options);
571
572 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
573 radv_perftest_options);
574
575
576 if (instance->debug_flags & RADV_DEBUG_STARTUP)
577 radv_logi("Created an instance");
578
579 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
580 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
581 int index = radv_get_instance_extension_index(ext_name);
582
583 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
584 vk_free2(&default_alloc, pAllocator, instance);
585 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
586 }
587
588 instance->enabled_extensions.extensions[index] = true;
589 }
590
591 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
592 if (result != VK_SUCCESS) {
593 vk_free2(&default_alloc, pAllocator, instance);
594 return vk_error(instance, result);
595 }
596
597 _mesa_locale_init();
598 glsl_type_singleton_init_or_ref();
599
600 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
601
602 radv_init_dri_options(instance);
603 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
604
605 *pInstance = radv_instance_to_handle(instance);
606
607 return VK_SUCCESS;
608 }
609
610 void radv_DestroyInstance(
611 VkInstance _instance,
612 const VkAllocationCallbacks* pAllocator)
613 {
614 RADV_FROM_HANDLE(radv_instance, instance, _instance);
615
616 if (!instance)
617 return;
618
619 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
620 radv_physical_device_finish(instance->physicalDevices + i);
621 }
622
623 VG(VALGRIND_DESTROY_MEMPOOL(instance));
624
625 glsl_type_singleton_decref();
626 _mesa_locale_fini();
627
628 driDestroyOptionCache(&instance->dri_options);
629 driDestroyOptionInfo(&instance->available_dri_options);
630
631 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
632
633 vk_free(&instance->alloc, instance);
634 }
635
636 static VkResult
637 radv_enumerate_devices(struct radv_instance *instance)
638 {
639 /* TODO: Check for more devices ? */
640 drmDevicePtr devices[8];
641 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
642 int max_devices;
643
644 instance->physicalDeviceCount = 0;
645
646 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
647
648 if (instance->debug_flags & RADV_DEBUG_STARTUP)
649 radv_logi("Found %d drm nodes", max_devices);
650
651 if (max_devices < 1)
652 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
653
654 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
655 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
656 devices[i]->bustype == DRM_BUS_PCI &&
657 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
658
659 result = radv_physical_device_init(instance->physicalDevices +
660 instance->physicalDeviceCount,
661 instance,
662 devices[i]);
663 if (result == VK_SUCCESS)
664 ++instance->physicalDeviceCount;
665 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
666 break;
667 }
668 }
669 drmFreeDevices(devices, max_devices);
670
671 return result;
672 }
673
674 VkResult radv_EnumeratePhysicalDevices(
675 VkInstance _instance,
676 uint32_t* pPhysicalDeviceCount,
677 VkPhysicalDevice* pPhysicalDevices)
678 {
679 RADV_FROM_HANDLE(radv_instance, instance, _instance);
680 VkResult result;
681
682 if (instance->physicalDeviceCount < 0) {
683 result = radv_enumerate_devices(instance);
684 if (result != VK_SUCCESS &&
685 result != VK_ERROR_INCOMPATIBLE_DRIVER)
686 return result;
687 }
688
689 if (!pPhysicalDevices) {
690 *pPhysicalDeviceCount = instance->physicalDeviceCount;
691 } else {
692 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
693 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
694 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
695 }
696
697 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
698 : VK_SUCCESS;
699 }
700
701 VkResult radv_EnumeratePhysicalDeviceGroups(
702 VkInstance _instance,
703 uint32_t* pPhysicalDeviceGroupCount,
704 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
705 {
706 RADV_FROM_HANDLE(radv_instance, instance, _instance);
707 VkResult result;
708
709 if (instance->physicalDeviceCount < 0) {
710 result = radv_enumerate_devices(instance);
711 if (result != VK_SUCCESS &&
712 result != VK_ERROR_INCOMPATIBLE_DRIVER)
713 return result;
714 }
715
716 if (!pPhysicalDeviceGroupProperties) {
717 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
718 } else {
719 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
720 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
721 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
722 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
723 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
724 }
725 }
726 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
727 : VK_SUCCESS;
728 }
729
730 void radv_GetPhysicalDeviceFeatures(
731 VkPhysicalDevice physicalDevice,
732 VkPhysicalDeviceFeatures* pFeatures)
733 {
734 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
735 memset(pFeatures, 0, sizeof(*pFeatures));
736
737 *pFeatures = (VkPhysicalDeviceFeatures) {
738 .robustBufferAccess = true,
739 .fullDrawIndexUint32 = true,
740 .imageCubeArray = true,
741 .independentBlend = true,
742 .geometryShader = true,
743 .tessellationShader = true,
744 .sampleRateShading = true,
745 .dualSrcBlend = true,
746 .logicOp = true,
747 .multiDrawIndirect = true,
748 .drawIndirectFirstInstance = true,
749 .depthClamp = true,
750 .depthBiasClamp = true,
751 .fillModeNonSolid = true,
752 .depthBounds = true,
753 .wideLines = true,
754 .largePoints = true,
755 .alphaToOne = true,
756 .multiViewport = true,
757 .samplerAnisotropy = true,
758 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
759 .textureCompressionASTC_LDR = false,
760 .textureCompressionBC = true,
761 .occlusionQueryPrecise = true,
762 .pipelineStatisticsQuery = true,
763 .vertexPipelineStoresAndAtomics = true,
764 .fragmentStoresAndAtomics = true,
765 .shaderTessellationAndGeometryPointSize = true,
766 .shaderImageGatherExtended = true,
767 .shaderStorageImageExtendedFormats = true,
768 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
769 .shaderUniformBufferArrayDynamicIndexing = true,
770 .shaderSampledImageArrayDynamicIndexing = true,
771 .shaderStorageBufferArrayDynamicIndexing = true,
772 .shaderStorageImageArrayDynamicIndexing = true,
773 .shaderStorageImageReadWithoutFormat = true,
774 .shaderStorageImageWriteWithoutFormat = true,
775 .shaderClipDistance = true,
776 .shaderCullDistance = true,
777 .shaderFloat64 = true,
778 .shaderInt64 = true,
779 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
780 .sparseBinding = true,
781 .variableMultisampleRate = true,
782 .inheritedQueries = true,
783 };
784 }
785
786 void radv_GetPhysicalDeviceFeatures2(
787 VkPhysicalDevice physicalDevice,
788 VkPhysicalDeviceFeatures2 *pFeatures)
789 {
790 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
791 vk_foreach_struct(ext, pFeatures->pNext) {
792 switch (ext->sType) {
793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
794 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
795 features->variablePointersStorageBuffer = true;
796 features->variablePointers = true;
797 break;
798 }
799 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
800 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
801 features->multiview = true;
802 features->multiviewGeometryShader = true;
803 features->multiviewTessellationShader = true;
804 break;
805 }
806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
807 VkPhysicalDeviceShaderDrawParameterFeatures *features =
808 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
809 features->shaderDrawParameters = true;
810 break;
811 }
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
813 VkPhysicalDeviceProtectedMemoryFeatures *features =
814 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
815 features->protectedMemory = false;
816 break;
817 }
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
819 VkPhysicalDevice16BitStorageFeatures *features =
820 (VkPhysicalDevice16BitStorageFeatures*)ext;
821 bool enabled = pdevice->rad_info.chip_class >= VI;
822 features->storageBuffer16BitAccess = enabled;
823 features->uniformAndStorageBuffer16BitAccess = enabled;
824 features->storagePushConstant16 = enabled;
825 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
826 break;
827 }
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
829 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
830 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
831 features->samplerYcbcrConversion = false;
832 break;
833 }
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
835 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
836 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
837 features->shaderInputAttachmentArrayDynamicIndexing = true;
838 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
839 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
840 features->shaderUniformBufferArrayNonUniformIndexing = true;
841 features->shaderSampledImageArrayNonUniformIndexing = true;
842 features->shaderStorageBufferArrayNonUniformIndexing = true;
843 features->shaderStorageImageArrayNonUniformIndexing = true;
844 features->shaderInputAttachmentArrayNonUniformIndexing = true;
845 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
846 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
847 features->descriptorBindingUniformBufferUpdateAfterBind = true;
848 features->descriptorBindingSampledImageUpdateAfterBind = true;
849 features->descriptorBindingStorageImageUpdateAfterBind = true;
850 features->descriptorBindingStorageBufferUpdateAfterBind = true;
851 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
852 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
853 features->descriptorBindingUpdateUnusedWhilePending = true;
854 features->descriptorBindingPartiallyBound = true;
855 features->descriptorBindingVariableDescriptorCount = true;
856 features->runtimeDescriptorArray = true;
857 break;
858 }
859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
860 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
861 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
862 features->conditionalRendering = true;
863 features->inheritedConditionalRendering = false;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
867 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
868 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
869 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
870 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
874 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
875 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
876 features->transformFeedback = true;
877 features->geometryStreams = true;
878 break;
879 }
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
881 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
882 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
883 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
884 break;
885 }
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
887 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
888 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
889 features->memoryPriority = VK_TRUE;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
893 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
894 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
895 features->bufferDeviceAddress = true;
896 features->bufferDeviceAddressCaptureReplay = false;
897 features->bufferDeviceAddressMultiDevice = false;
898 break;
899 }
900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
901 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
902 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
903 features->depthClipEnable = true;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
907 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
908 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
909 features->hostQueryReset = true;
910 break;
911 }
912 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
913 VkPhysicalDevice8BitStorageFeaturesKHR *features =
914 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
915 bool enabled = pdevice->rad_info.chip_class >= VI;
916 features->storageBuffer8BitAccess = enabled;
917 features->uniformAndStorageBuffer8BitAccess = enabled;
918 features->storagePushConstant8 = enabled;
919 break;
920 }
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
922 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
923 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
924 features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800;
925 features->shaderInt8 = true;
926 break;
927 }
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
929 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
930 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
931 /* TODO: Enable this once the driver supports 64-bit
932 * compare&swap atomic operations.
933 */
934 features->shaderBufferInt64Atomics = false;
935 features->shaderSharedInt64Atomics = false;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
939 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
940 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
941
942 features->inlineUniformBlock = true;
943 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
947 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
948 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
949 features->computeDerivativeGroupQuads = false;
950 features->computeDerivativeGroupLinear = true;
951 break;
952 }
953 default:
954 break;
955 }
956 }
957 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
958 }
959
960 void radv_GetPhysicalDeviceProperties(
961 VkPhysicalDevice physicalDevice,
962 VkPhysicalDeviceProperties* pProperties)
963 {
964 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
965 VkSampleCountFlags sample_counts = 0xf;
966
967 /* make sure that the entire descriptor set is addressable with a signed
968 * 32-bit int. So the sum of all limits scaled by descriptor size has to
969 * be at most 2 GiB. the combined image & samples object count as one of
970 * both. This limit is for the pipeline layout, not for the set layout, but
971 * there is no set limit, so we just set a pipeline limit. I don't think
972 * any app is going to hit this soon. */
973 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
974 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
975 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
976 32 /* sampler, largest when combined with image */ +
977 64 /* sampled image */ +
978 64 /* storage image */);
979
980 VkPhysicalDeviceLimits limits = {
981 .maxImageDimension1D = (1 << 14),
982 .maxImageDimension2D = (1 << 14),
983 .maxImageDimension3D = (1 << 11),
984 .maxImageDimensionCube = (1 << 14),
985 .maxImageArrayLayers = (1 << 11),
986 .maxTexelBufferElements = 128 * 1024 * 1024,
987 .maxUniformBufferRange = UINT32_MAX,
988 .maxStorageBufferRange = UINT32_MAX,
989 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
990 .maxMemoryAllocationCount = UINT32_MAX,
991 .maxSamplerAllocationCount = 64 * 1024,
992 .bufferImageGranularity = 64, /* A cache line */
993 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
994 .maxBoundDescriptorSets = MAX_SETS,
995 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
996 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
997 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
998 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
999 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1000 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1001 .maxPerStageResources = max_descriptor_set_size,
1002 .maxDescriptorSetSamplers = max_descriptor_set_size,
1003 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1004 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1005 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1006 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1007 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1008 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1009 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1010 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1011 .maxVertexInputBindings = MAX_VBS,
1012 .maxVertexInputAttributeOffset = 2047,
1013 .maxVertexInputBindingStride = 2048,
1014 .maxVertexOutputComponents = 128,
1015 .maxTessellationGenerationLevel = 64,
1016 .maxTessellationPatchSize = 32,
1017 .maxTessellationControlPerVertexInputComponents = 128,
1018 .maxTessellationControlPerVertexOutputComponents = 128,
1019 .maxTessellationControlPerPatchOutputComponents = 120,
1020 .maxTessellationControlTotalOutputComponents = 4096,
1021 .maxTessellationEvaluationInputComponents = 128,
1022 .maxTessellationEvaluationOutputComponents = 128,
1023 .maxGeometryShaderInvocations = 127,
1024 .maxGeometryInputComponents = 64,
1025 .maxGeometryOutputComponents = 128,
1026 .maxGeometryOutputVertices = 256,
1027 .maxGeometryTotalOutputComponents = 1024,
1028 .maxFragmentInputComponents = 128,
1029 .maxFragmentOutputAttachments = 8,
1030 .maxFragmentDualSrcAttachments = 1,
1031 .maxFragmentCombinedOutputResources = 8,
1032 .maxComputeSharedMemorySize = 32768,
1033 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1034 .maxComputeWorkGroupInvocations = 2048,
1035 .maxComputeWorkGroupSize = {
1036 2048,
1037 2048,
1038 2048
1039 },
1040 .subPixelPrecisionBits = 8,
1041 .subTexelPrecisionBits = 8,
1042 .mipmapPrecisionBits = 8,
1043 .maxDrawIndexedIndexValue = UINT32_MAX,
1044 .maxDrawIndirectCount = UINT32_MAX,
1045 .maxSamplerLodBias = 16,
1046 .maxSamplerAnisotropy = 16,
1047 .maxViewports = MAX_VIEWPORTS,
1048 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1049 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1050 .viewportSubPixelBits = 8,
1051 .minMemoryMapAlignment = 4096, /* A page */
1052 .minTexelBufferOffsetAlignment = 1,
1053 .minUniformBufferOffsetAlignment = 4,
1054 .minStorageBufferOffsetAlignment = 4,
1055 .minTexelOffset = -32,
1056 .maxTexelOffset = 31,
1057 .minTexelGatherOffset = -32,
1058 .maxTexelGatherOffset = 31,
1059 .minInterpolationOffset = -2,
1060 .maxInterpolationOffset = 2,
1061 .subPixelInterpolationOffsetBits = 8,
1062 .maxFramebufferWidth = (1 << 14),
1063 .maxFramebufferHeight = (1 << 14),
1064 .maxFramebufferLayers = (1 << 10),
1065 .framebufferColorSampleCounts = sample_counts,
1066 .framebufferDepthSampleCounts = sample_counts,
1067 .framebufferStencilSampleCounts = sample_counts,
1068 .framebufferNoAttachmentsSampleCounts = sample_counts,
1069 .maxColorAttachments = MAX_RTS,
1070 .sampledImageColorSampleCounts = sample_counts,
1071 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1072 .sampledImageDepthSampleCounts = sample_counts,
1073 .sampledImageStencilSampleCounts = sample_counts,
1074 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1075 .maxSampleMaskWords = 1,
1076 .timestampComputeAndGraphics = true,
1077 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1078 .maxClipDistances = 8,
1079 .maxCullDistances = 8,
1080 .maxCombinedClipAndCullDistances = 8,
1081 .discreteQueuePriorities = 2,
1082 .pointSizeRange = { 0.0, 8192.0 },
1083 .lineWidthRange = { 0.0, 7.9921875 },
1084 .pointSizeGranularity = (1.0 / 8.0),
1085 .lineWidthGranularity = (1.0 / 128.0),
1086 .strictLines = false, /* FINISHME */
1087 .standardSampleLocations = true,
1088 .optimalBufferCopyOffsetAlignment = 128,
1089 .optimalBufferCopyRowPitchAlignment = 128,
1090 .nonCoherentAtomSize = 64,
1091 };
1092
1093 *pProperties = (VkPhysicalDeviceProperties) {
1094 .apiVersion = radv_physical_device_api_version(pdevice),
1095 .driverVersion = vk_get_driver_version(),
1096 .vendorID = ATI_VENDOR_ID,
1097 .deviceID = pdevice->rad_info.pci_id,
1098 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1099 .limits = limits,
1100 .sparseProperties = {0},
1101 };
1102
1103 strcpy(pProperties->deviceName, pdevice->name);
1104 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1105 }
1106
1107 void radv_GetPhysicalDeviceProperties2(
1108 VkPhysicalDevice physicalDevice,
1109 VkPhysicalDeviceProperties2 *pProperties)
1110 {
1111 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1112 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1113
1114 vk_foreach_struct(ext, pProperties->pNext) {
1115 switch (ext->sType) {
1116 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1117 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1118 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1119 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1120 break;
1121 }
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1123 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1124 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1125 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1126 properties->deviceLUIDValid = false;
1127 break;
1128 }
1129 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1130 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1131 properties->maxMultiviewViewCount = MAX_VIEWS;
1132 properties->maxMultiviewInstanceIndex = INT_MAX;
1133 break;
1134 }
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1136 VkPhysicalDevicePointClippingProperties *properties =
1137 (VkPhysicalDevicePointClippingProperties*)ext;
1138 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1139 break;
1140 }
1141 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1142 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1143 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1144 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1145 break;
1146 }
1147 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1148 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1149 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1150 properties->minImportedHostPointerAlignment = 4096;
1151 break;
1152 }
1153 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1154 VkPhysicalDeviceSubgroupProperties *properties =
1155 (VkPhysicalDeviceSubgroupProperties*)ext;
1156 properties->subgroupSize = 64;
1157 properties->supportedStages = VK_SHADER_STAGE_ALL;
1158 properties->supportedOperations =
1159 VK_SUBGROUP_FEATURE_BASIC_BIT |
1160 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1161 VK_SUBGROUP_FEATURE_QUAD_BIT |
1162 VK_SUBGROUP_FEATURE_VOTE_BIT;
1163 if (pdevice->rad_info.chip_class >= VI) {
1164 properties->supportedOperations |=
1165 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1166 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1167 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1168 }
1169 properties->quadOperationsInAllStages = true;
1170 break;
1171 }
1172 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1173 VkPhysicalDeviceMaintenance3Properties *properties =
1174 (VkPhysicalDeviceMaintenance3Properties*)ext;
1175 /* Make sure everything is addressable by a signed 32-bit int, and
1176 * our largest descriptors are 96 bytes. */
1177 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1178 /* Our buffer size fields allow only this much */
1179 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1183 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1184 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1185 /* GFX6-8 only support single channel min/max filter. */
1186 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1187 properties->filterMinmaxSingleComponentFormats = true;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1191 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1192 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1193
1194 /* Shader engines. */
1195 properties->shaderEngineCount =
1196 pdevice->rad_info.max_se;
1197 properties->shaderArraysPerEngineCount =
1198 pdevice->rad_info.max_sh_per_se;
1199 properties->computeUnitsPerShaderArray =
1200 pdevice->rad_info.num_good_cu_per_sh;
1201 properties->simdPerComputeUnit = 4;
1202 properties->wavefrontsPerSimd =
1203 pdevice->rad_info.family == CHIP_TONGA ||
1204 pdevice->rad_info.family == CHIP_ICELAND ||
1205 pdevice->rad_info.family == CHIP_POLARIS10 ||
1206 pdevice->rad_info.family == CHIP_POLARIS11 ||
1207 pdevice->rad_info.family == CHIP_POLARIS12 ||
1208 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1209 properties->wavefrontSize = 64;
1210
1211 /* SGPR. */
1212 properties->sgprsPerSimd =
1213 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1214 properties->minSgprAllocation =
1215 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1216 properties->maxSgprAllocation =
1217 pdevice->rad_info.family == CHIP_TONGA ||
1218 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1219 properties->sgprAllocationGranularity =
1220 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1221
1222 /* VGPR. */
1223 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1224 properties->minVgprAllocation = 4;
1225 properties->maxVgprAllocation = 256;
1226 properties->vgprAllocationGranularity = 4;
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1230 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1231 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1232 properties->maxVertexAttribDivisor = UINT32_MAX;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1236 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1237 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1238 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1239 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1240 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1241 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1242 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1243 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1244 properties->robustBufferAccessUpdateAfterBind = false;
1245 properties->quadDivergentImplicitLod = false;
1246
1247 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1248 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1249 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1250 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1251 32 /* sampler, largest when combined with image */ +
1252 64 /* sampled image */ +
1253 64 /* storage image */);
1254 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1255 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1256 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1257 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1258 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1259 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1260 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1261 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1262 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1263 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1264 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1265 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1266 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1267 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1268 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1269 break;
1270 }
1271 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1272 VkPhysicalDeviceProtectedMemoryProperties *properties =
1273 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1274 properties->protectedNoFault = false;
1275 break;
1276 }
1277 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1278 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1279 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1280 properties->primitiveOverestimationSize = 0;
1281 properties->maxExtraPrimitiveOverestimationSize = 0;
1282 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1283 properties->primitiveUnderestimation = VK_FALSE;
1284 properties->conservativePointAndLineRasterization = VK_FALSE;
1285 properties->degenerateTrianglesRasterized = VK_FALSE;
1286 properties->degenerateLinesRasterized = VK_FALSE;
1287 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1288 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1289 break;
1290 }
1291 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1292 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1293 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1294 properties->pciDomain = pdevice->bus_info.domain;
1295 properties->pciBus = pdevice->bus_info.bus;
1296 properties->pciDevice = pdevice->bus_info.dev;
1297 properties->pciFunction = pdevice->bus_info.func;
1298 break;
1299 }
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1301 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1302 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1303
1304 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1305 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1306 strcpy(driver_props->driverName, "radv");
1307
1308 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1309 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1310 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1311 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1312
1313 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1314 .major = 1,
1315 .minor = 1,
1316 .subminor = 2,
1317 .patch = 0,
1318 };
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1322 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1323 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1324 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1325 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1326 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1327 properties->maxTransformFeedbackStreamDataSize = 512;
1328 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1329 properties->maxTransformFeedbackBufferDataStride = 512;
1330 properties->transformFeedbackQueries = true;
1331 properties->transformFeedbackStreamsLinesTriangles = false;
1332 properties->transformFeedbackRasterizationStreamSelect = false;
1333 properties->transformFeedbackDraw = true;
1334 break;
1335 }
1336 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1337 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1338 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1339
1340 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1341 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1342 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1343 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1344 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1345 break;
1346 }
1347 default:
1348 break;
1349 }
1350 }
1351 }
1352
1353 static void radv_get_physical_device_queue_family_properties(
1354 struct radv_physical_device* pdevice,
1355 uint32_t* pCount,
1356 VkQueueFamilyProperties** pQueueFamilyProperties)
1357 {
1358 int num_queue_families = 1;
1359 int idx;
1360 if (pdevice->rad_info.num_compute_rings > 0 &&
1361 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1362 num_queue_families++;
1363
1364 if (pQueueFamilyProperties == NULL) {
1365 *pCount = num_queue_families;
1366 return;
1367 }
1368
1369 if (!*pCount)
1370 return;
1371
1372 idx = 0;
1373 if (*pCount >= 1) {
1374 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1375 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1376 VK_QUEUE_COMPUTE_BIT |
1377 VK_QUEUE_TRANSFER_BIT |
1378 VK_QUEUE_SPARSE_BINDING_BIT,
1379 .queueCount = 1,
1380 .timestampValidBits = 64,
1381 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1382 };
1383 idx++;
1384 }
1385
1386 if (pdevice->rad_info.num_compute_rings > 0 &&
1387 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1388 if (*pCount > idx) {
1389 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1390 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1391 VK_QUEUE_TRANSFER_BIT |
1392 VK_QUEUE_SPARSE_BINDING_BIT,
1393 .queueCount = pdevice->rad_info.num_compute_rings,
1394 .timestampValidBits = 64,
1395 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1396 };
1397 idx++;
1398 }
1399 }
1400 *pCount = idx;
1401 }
1402
1403 void radv_GetPhysicalDeviceQueueFamilyProperties(
1404 VkPhysicalDevice physicalDevice,
1405 uint32_t* pCount,
1406 VkQueueFamilyProperties* pQueueFamilyProperties)
1407 {
1408 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1409 if (!pQueueFamilyProperties) {
1410 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1411 return;
1412 }
1413 VkQueueFamilyProperties *properties[] = {
1414 pQueueFamilyProperties + 0,
1415 pQueueFamilyProperties + 1,
1416 pQueueFamilyProperties + 2,
1417 };
1418 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1419 assert(*pCount <= 3);
1420 }
1421
1422 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1423 VkPhysicalDevice physicalDevice,
1424 uint32_t* pCount,
1425 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1426 {
1427 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1428 if (!pQueueFamilyProperties) {
1429 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1430 return;
1431 }
1432 VkQueueFamilyProperties *properties[] = {
1433 &pQueueFamilyProperties[0].queueFamilyProperties,
1434 &pQueueFamilyProperties[1].queueFamilyProperties,
1435 &pQueueFamilyProperties[2].queueFamilyProperties,
1436 };
1437 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1438 assert(*pCount <= 3);
1439 }
1440
1441 void radv_GetPhysicalDeviceMemoryProperties(
1442 VkPhysicalDevice physicalDevice,
1443 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1444 {
1445 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1446
1447 *pMemoryProperties = physical_device->memory_properties;
1448 }
1449
1450 static void
1451 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1452 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1453 {
1454 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1455 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1456 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1457 uint64_t vram_size = radv_get_vram_size(device);
1458 uint64_t gtt_size = device->rad_info.gart_size;
1459 uint64_t heap_budget, heap_usage;
1460
1461 /* For all memory heaps, the computation of budget is as follow:
1462 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1463 *
1464 * The Vulkan spec 1.1.97 says that the budget should include any
1465 * currently allocated device memory.
1466 *
1467 * Note that the application heap usages are not really accurate (eg.
1468 * in presence of shared buffers).
1469 */
1470 if (vram_size) {
1471 heap_usage = device->ws->query_value(device->ws,
1472 RADEON_ALLOCATED_VRAM);
1473
1474 heap_budget = vram_size -
1475 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1476 heap_usage;
1477
1478 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1479 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1480 }
1481
1482 if (visible_vram_size) {
1483 heap_usage = device->ws->query_value(device->ws,
1484 RADEON_ALLOCATED_VRAM_VIS);
1485
1486 heap_budget = visible_vram_size -
1487 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1488 heap_usage;
1489
1490 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1491 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1492 }
1493
1494 if (gtt_size) {
1495 heap_usage = device->ws->query_value(device->ws,
1496 RADEON_ALLOCATED_GTT);
1497
1498 heap_budget = gtt_size -
1499 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1500 heap_usage;
1501
1502 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1503 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1504 }
1505
1506 /* The heapBudget and heapUsage values must be zero for array elements
1507 * greater than or equal to
1508 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1509 */
1510 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1511 memoryBudget->heapBudget[i] = 0;
1512 memoryBudget->heapUsage[i] = 0;
1513 }
1514 }
1515
1516 void radv_GetPhysicalDeviceMemoryProperties2(
1517 VkPhysicalDevice physicalDevice,
1518 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1519 {
1520 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1521 &pMemoryProperties->memoryProperties);
1522
1523 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1524 vk_find_struct(pMemoryProperties->pNext,
1525 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1526 if (memory_budget)
1527 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1528 }
1529
1530 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1531 VkDevice _device,
1532 VkExternalMemoryHandleTypeFlagBits handleType,
1533 const void *pHostPointer,
1534 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1535 {
1536 RADV_FROM_HANDLE(radv_device, device, _device);
1537
1538 switch (handleType)
1539 {
1540 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1541 const struct radv_physical_device *physical_device = device->physical_device;
1542 uint32_t memoryTypeBits = 0;
1543 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1544 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1545 memoryTypeBits = (1 << i);
1546 break;
1547 }
1548 }
1549 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1550 return VK_SUCCESS;
1551 }
1552 default:
1553 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1554 }
1555 }
1556
1557 static enum radeon_ctx_priority
1558 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1559 {
1560 /* Default to MEDIUM when a specific global priority isn't requested */
1561 if (!pObj)
1562 return RADEON_CTX_PRIORITY_MEDIUM;
1563
1564 switch(pObj->globalPriority) {
1565 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1566 return RADEON_CTX_PRIORITY_REALTIME;
1567 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1568 return RADEON_CTX_PRIORITY_HIGH;
1569 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1570 return RADEON_CTX_PRIORITY_MEDIUM;
1571 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1572 return RADEON_CTX_PRIORITY_LOW;
1573 default:
1574 unreachable("Illegal global priority value");
1575 return RADEON_CTX_PRIORITY_INVALID;
1576 }
1577 }
1578
1579 static int
1580 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1581 uint32_t queue_family_index, int idx,
1582 VkDeviceQueueCreateFlags flags,
1583 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1584 {
1585 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1586 queue->device = device;
1587 queue->queue_family_index = queue_family_index;
1588 queue->queue_idx = idx;
1589 queue->priority = radv_get_queue_global_priority(global_priority);
1590 queue->flags = flags;
1591
1592 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1593 if (!queue->hw_ctx)
1594 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1595
1596 return VK_SUCCESS;
1597 }
1598
1599 static void
1600 radv_queue_finish(struct radv_queue *queue)
1601 {
1602 if (queue->hw_ctx)
1603 queue->device->ws->ctx_destroy(queue->hw_ctx);
1604
1605 if (queue->initial_full_flush_preamble_cs)
1606 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1607 if (queue->initial_preamble_cs)
1608 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1609 if (queue->continue_preamble_cs)
1610 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1611 if (queue->descriptor_bo)
1612 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1613 if (queue->scratch_bo)
1614 queue->device->ws->buffer_destroy(queue->scratch_bo);
1615 if (queue->esgs_ring_bo)
1616 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1617 if (queue->gsvs_ring_bo)
1618 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1619 if (queue->tess_rings_bo)
1620 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1621 if (queue->compute_scratch_bo)
1622 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1623 }
1624
1625 static void
1626 radv_bo_list_init(struct radv_bo_list *bo_list)
1627 {
1628 pthread_mutex_init(&bo_list->mutex, NULL);
1629 bo_list->list.count = bo_list->capacity = 0;
1630 bo_list->list.bos = NULL;
1631 }
1632
1633 static void
1634 radv_bo_list_finish(struct radv_bo_list *bo_list)
1635 {
1636 free(bo_list->list.bos);
1637 pthread_mutex_destroy(&bo_list->mutex);
1638 }
1639
1640 static VkResult radv_bo_list_add(struct radv_device *device,
1641 struct radeon_winsys_bo *bo)
1642 {
1643 struct radv_bo_list *bo_list = &device->bo_list;
1644
1645 if (bo->is_local)
1646 return VK_SUCCESS;
1647
1648 if (unlikely(!device->use_global_bo_list))
1649 return VK_SUCCESS;
1650
1651 pthread_mutex_lock(&bo_list->mutex);
1652 if (bo_list->list.count == bo_list->capacity) {
1653 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1654 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1655
1656 if (!data) {
1657 pthread_mutex_unlock(&bo_list->mutex);
1658 return VK_ERROR_OUT_OF_HOST_MEMORY;
1659 }
1660
1661 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1662 bo_list->capacity = capacity;
1663 }
1664
1665 bo_list->list.bos[bo_list->list.count++] = bo;
1666 pthread_mutex_unlock(&bo_list->mutex);
1667 return VK_SUCCESS;
1668 }
1669
1670 static void radv_bo_list_remove(struct radv_device *device,
1671 struct radeon_winsys_bo *bo)
1672 {
1673 struct radv_bo_list *bo_list = &device->bo_list;
1674
1675 if (bo->is_local)
1676 return;
1677
1678 if (unlikely(!device->use_global_bo_list))
1679 return;
1680
1681 pthread_mutex_lock(&bo_list->mutex);
1682 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1683 if (bo_list->list.bos[i] == bo) {
1684 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1685 --bo_list->list.count;
1686 break;
1687 }
1688 }
1689 pthread_mutex_unlock(&bo_list->mutex);
1690 }
1691
1692 static void
1693 radv_device_init_gs_info(struct radv_device *device)
1694 {
1695 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1696 device->physical_device->rad_info.family);
1697 }
1698
1699 static int radv_get_device_extension_index(const char *name)
1700 {
1701 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1702 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1703 return i;
1704 }
1705 return -1;
1706 }
1707
1708 static int
1709 radv_get_int_debug_option(const char *name, int default_value)
1710 {
1711 const char *str;
1712 int result;
1713
1714 str = getenv(name);
1715 if (!str) {
1716 result = default_value;
1717 } else {
1718 char *endptr;
1719
1720 result = strtol(str, &endptr, 0);
1721 if (str == endptr) {
1722 /* No digits founs. */
1723 result = default_value;
1724 }
1725 }
1726
1727 return result;
1728 }
1729
1730 VkResult radv_CreateDevice(
1731 VkPhysicalDevice physicalDevice,
1732 const VkDeviceCreateInfo* pCreateInfo,
1733 const VkAllocationCallbacks* pAllocator,
1734 VkDevice* pDevice)
1735 {
1736 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1737 VkResult result;
1738 struct radv_device *device;
1739
1740 bool keep_shader_info = false;
1741
1742 /* Check enabled features */
1743 if (pCreateInfo->pEnabledFeatures) {
1744 VkPhysicalDeviceFeatures supported_features;
1745 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1746 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1747 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1748 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1749 for (uint32_t i = 0; i < num_features; i++) {
1750 if (enabled_feature[i] && !supported_feature[i])
1751 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1752 }
1753 }
1754
1755 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1756 sizeof(*device), 8,
1757 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1758 if (!device)
1759 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1760
1761 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1762 device->instance = physical_device->instance;
1763 device->physical_device = physical_device;
1764
1765 device->ws = physical_device->ws;
1766 if (pAllocator)
1767 device->alloc = *pAllocator;
1768 else
1769 device->alloc = physical_device->instance->alloc;
1770
1771 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1772 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1773 int index = radv_get_device_extension_index(ext_name);
1774 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1775 vk_free(&device->alloc, device);
1776 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1777 }
1778
1779 device->enabled_extensions.extensions[index] = true;
1780 }
1781
1782 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1783
1784 /* With update after bind we can't attach bo's to the command buffer
1785 * from the descriptor set anymore, so we have to use a global BO list.
1786 */
1787 device->use_global_bo_list =
1788 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1789 device->enabled_extensions.EXT_descriptor_indexing ||
1790 device->enabled_extensions.EXT_buffer_device_address;
1791
1792 mtx_init(&device->shader_slab_mutex, mtx_plain);
1793 list_inithead(&device->shader_slabs);
1794
1795 radv_bo_list_init(&device->bo_list);
1796
1797 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1798 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1799 uint32_t qfi = queue_create->queueFamilyIndex;
1800 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1801 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1802
1803 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1804
1805 device->queues[qfi] = vk_alloc(&device->alloc,
1806 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1807 if (!device->queues[qfi]) {
1808 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1809 goto fail;
1810 }
1811
1812 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1813
1814 device->queue_count[qfi] = queue_create->queueCount;
1815
1816 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1817 result = radv_queue_init(device, &device->queues[qfi][q],
1818 qfi, q, queue_create->flags,
1819 global_priority);
1820 if (result != VK_SUCCESS)
1821 goto fail;
1822 }
1823 }
1824
1825 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1826 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1827
1828 /* Disabled and not implemented for now. */
1829 device->dfsm_allowed = device->pbb_allowed &&
1830 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1831 device->physical_device->rad_info.family == CHIP_RAVEN2);
1832
1833 #ifdef ANDROID
1834 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1835 #endif
1836
1837 /* The maximum number of scratch waves. Scratch space isn't divided
1838 * evenly between CUs. The number is only a function of the number of CUs.
1839 * We can decrease the constant to decrease the scratch buffer size.
1840 *
1841 * sctx->scratch_waves must be >= the maximum possible size of
1842 * 1 threadgroup, so that the hw doesn't hang from being unable
1843 * to start any.
1844 *
1845 * The recommended value is 4 per CU at most. Higher numbers don't
1846 * bring much benefit, but they still occupy chip resources (think
1847 * async compute). I've seen ~2% performance difference between 4 and 32.
1848 */
1849 uint32_t max_threads_per_block = 2048;
1850 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1851 max_threads_per_block / 64);
1852
1853 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1854
1855 if (device->physical_device->rad_info.chip_class >= CIK) {
1856 /* If the KMD allows it (there is a KMD hw register for it),
1857 * allow launching waves out-of-order.
1858 */
1859 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1860 }
1861
1862 radv_device_init_gs_info(device);
1863
1864 device->tess_offchip_block_dw_size =
1865 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1866 device->has_distributed_tess =
1867 device->physical_device->rad_info.chip_class >= VI &&
1868 device->physical_device->rad_info.max_se >= 2;
1869
1870 if (getenv("RADV_TRACE_FILE")) {
1871 const char *filename = getenv("RADV_TRACE_FILE");
1872
1873 keep_shader_info = true;
1874
1875 if (!radv_init_trace(device))
1876 goto fail;
1877
1878 fprintf(stderr, "*****************************************************************************\n");
1879 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1880 fprintf(stderr, "*****************************************************************************\n");
1881
1882 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1883 radv_dump_enabled_options(device, stderr);
1884 }
1885
1886 device->keep_shader_info = keep_shader_info;
1887
1888 result = radv_device_init_meta(device);
1889 if (result != VK_SUCCESS)
1890 goto fail;
1891
1892 radv_device_init_msaa(device);
1893
1894 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1895 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1896 switch (family) {
1897 case RADV_QUEUE_GENERAL:
1898 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1899 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1900 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1901 break;
1902 case RADV_QUEUE_COMPUTE:
1903 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1904 radeon_emit(device->empty_cs[family], 0);
1905 break;
1906 }
1907 device->ws->cs_finalize(device->empty_cs[family]);
1908 }
1909
1910 if (device->physical_device->rad_info.chip_class >= CIK)
1911 cik_create_gfx_config(device);
1912
1913 VkPipelineCacheCreateInfo ci;
1914 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1915 ci.pNext = NULL;
1916 ci.flags = 0;
1917 ci.pInitialData = NULL;
1918 ci.initialDataSize = 0;
1919 VkPipelineCache pc;
1920 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1921 &ci, NULL, &pc);
1922 if (result != VK_SUCCESS)
1923 goto fail_meta;
1924
1925 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1926
1927 device->force_aniso =
1928 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1929 if (device->force_aniso >= 0) {
1930 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1931 1 << util_logbase2(device->force_aniso));
1932 }
1933
1934 *pDevice = radv_device_to_handle(device);
1935 return VK_SUCCESS;
1936
1937 fail_meta:
1938 radv_device_finish_meta(device);
1939 fail:
1940 radv_bo_list_finish(&device->bo_list);
1941
1942 if (device->trace_bo)
1943 device->ws->buffer_destroy(device->trace_bo);
1944
1945 if (device->gfx_init)
1946 device->ws->buffer_destroy(device->gfx_init);
1947
1948 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1949 for (unsigned q = 0; q < device->queue_count[i]; q++)
1950 radv_queue_finish(&device->queues[i][q]);
1951 if (device->queue_count[i])
1952 vk_free(&device->alloc, device->queues[i]);
1953 }
1954
1955 vk_free(&device->alloc, device);
1956 return result;
1957 }
1958
1959 void radv_DestroyDevice(
1960 VkDevice _device,
1961 const VkAllocationCallbacks* pAllocator)
1962 {
1963 RADV_FROM_HANDLE(radv_device, device, _device);
1964
1965 if (!device)
1966 return;
1967
1968 if (device->trace_bo)
1969 device->ws->buffer_destroy(device->trace_bo);
1970
1971 if (device->gfx_init)
1972 device->ws->buffer_destroy(device->gfx_init);
1973
1974 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1975 for (unsigned q = 0; q < device->queue_count[i]; q++)
1976 radv_queue_finish(&device->queues[i][q]);
1977 if (device->queue_count[i])
1978 vk_free(&device->alloc, device->queues[i]);
1979 if (device->empty_cs[i])
1980 device->ws->cs_destroy(device->empty_cs[i]);
1981 }
1982 radv_device_finish_meta(device);
1983
1984 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1985 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1986
1987 radv_destroy_shader_slabs(device);
1988
1989 radv_bo_list_finish(&device->bo_list);
1990 vk_free(&device->alloc, device);
1991 }
1992
1993 VkResult radv_EnumerateInstanceLayerProperties(
1994 uint32_t* pPropertyCount,
1995 VkLayerProperties* pProperties)
1996 {
1997 if (pProperties == NULL) {
1998 *pPropertyCount = 0;
1999 return VK_SUCCESS;
2000 }
2001
2002 /* None supported at this time */
2003 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2004 }
2005
2006 VkResult radv_EnumerateDeviceLayerProperties(
2007 VkPhysicalDevice physicalDevice,
2008 uint32_t* pPropertyCount,
2009 VkLayerProperties* pProperties)
2010 {
2011 if (pProperties == NULL) {
2012 *pPropertyCount = 0;
2013 return VK_SUCCESS;
2014 }
2015
2016 /* None supported at this time */
2017 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2018 }
2019
2020 void radv_GetDeviceQueue2(
2021 VkDevice _device,
2022 const VkDeviceQueueInfo2* pQueueInfo,
2023 VkQueue* pQueue)
2024 {
2025 RADV_FROM_HANDLE(radv_device, device, _device);
2026 struct radv_queue *queue;
2027
2028 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2029 if (pQueueInfo->flags != queue->flags) {
2030 /* From the Vulkan 1.1.70 spec:
2031 *
2032 * "The queue returned by vkGetDeviceQueue2 must have the same
2033 * flags value from this structure as that used at device
2034 * creation time in a VkDeviceQueueCreateInfo instance. If no
2035 * matching flags were specified at device creation time then
2036 * pQueue will return VK_NULL_HANDLE."
2037 */
2038 *pQueue = VK_NULL_HANDLE;
2039 return;
2040 }
2041
2042 *pQueue = radv_queue_to_handle(queue);
2043 }
2044
2045 void radv_GetDeviceQueue(
2046 VkDevice _device,
2047 uint32_t queueFamilyIndex,
2048 uint32_t queueIndex,
2049 VkQueue* pQueue)
2050 {
2051 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2052 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2053 .queueFamilyIndex = queueFamilyIndex,
2054 .queueIndex = queueIndex
2055 };
2056
2057 radv_GetDeviceQueue2(_device, &info, pQueue);
2058 }
2059
2060 static void
2061 fill_geom_tess_rings(struct radv_queue *queue,
2062 uint32_t *map,
2063 bool add_sample_positions,
2064 uint32_t esgs_ring_size,
2065 struct radeon_winsys_bo *esgs_ring_bo,
2066 uint32_t gsvs_ring_size,
2067 struct radeon_winsys_bo *gsvs_ring_bo,
2068 uint32_t tess_factor_ring_size,
2069 uint32_t tess_offchip_ring_offset,
2070 uint32_t tess_offchip_ring_size,
2071 struct radeon_winsys_bo *tess_rings_bo)
2072 {
2073 uint32_t *desc = &map[4];
2074
2075 if (esgs_ring_bo) {
2076 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2077
2078 /* stride 0, num records - size, add tid, swizzle, elsize4,
2079 index stride 64 */
2080 desc[0] = esgs_va;
2081 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2082 S_008F04_STRIDE(0) |
2083 S_008F04_SWIZZLE_ENABLE(true);
2084 desc[2] = esgs_ring_size;
2085 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2086 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2087 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2088 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2089 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2090 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2091 S_008F0C_ELEMENT_SIZE(1) |
2092 S_008F0C_INDEX_STRIDE(3) |
2093 S_008F0C_ADD_TID_ENABLE(true);
2094
2095 /* GS entry for ES->GS ring */
2096 /* stride 0, num records - size, elsize0,
2097 index stride 0 */
2098 desc[4] = esgs_va;
2099 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2100 S_008F04_STRIDE(0) |
2101 S_008F04_SWIZZLE_ENABLE(false);
2102 desc[6] = esgs_ring_size;
2103 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2104 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2105 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2106 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2107 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2108 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2109 S_008F0C_ELEMENT_SIZE(0) |
2110 S_008F0C_INDEX_STRIDE(0) |
2111 S_008F0C_ADD_TID_ENABLE(false);
2112 }
2113
2114 desc += 8;
2115
2116 if (gsvs_ring_bo) {
2117 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2118
2119 /* VS entry for GS->VS ring */
2120 /* stride 0, num records - size, elsize0,
2121 index stride 0 */
2122 desc[0] = gsvs_va;
2123 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2124 S_008F04_STRIDE(0) |
2125 S_008F04_SWIZZLE_ENABLE(false);
2126 desc[2] = gsvs_ring_size;
2127 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2128 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2129 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2130 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2131 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2132 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2133 S_008F0C_ELEMENT_SIZE(0) |
2134 S_008F0C_INDEX_STRIDE(0) |
2135 S_008F0C_ADD_TID_ENABLE(false);
2136
2137 /* stride gsvs_itemsize, num records 64
2138 elsize 4, index stride 16 */
2139 /* shader will patch stride and desc[2] */
2140 desc[4] = gsvs_va;
2141 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2142 S_008F04_STRIDE(0) |
2143 S_008F04_SWIZZLE_ENABLE(true);
2144 desc[6] = 0;
2145 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2146 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2147 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2148 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2149 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2150 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2151 S_008F0C_ELEMENT_SIZE(1) |
2152 S_008F0C_INDEX_STRIDE(1) |
2153 S_008F0C_ADD_TID_ENABLE(true);
2154 }
2155
2156 desc += 8;
2157
2158 if (tess_rings_bo) {
2159 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2160 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2161
2162 desc[0] = tess_va;
2163 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2164 S_008F04_STRIDE(0) |
2165 S_008F04_SWIZZLE_ENABLE(false);
2166 desc[2] = tess_factor_ring_size;
2167 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2168 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2169 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2170 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2171 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2173 S_008F0C_ELEMENT_SIZE(0) |
2174 S_008F0C_INDEX_STRIDE(0) |
2175 S_008F0C_ADD_TID_ENABLE(false);
2176
2177 desc[4] = tess_offchip_va;
2178 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2179 S_008F04_STRIDE(0) |
2180 S_008F04_SWIZZLE_ENABLE(false);
2181 desc[6] = tess_offchip_ring_size;
2182 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2183 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2184 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2185 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2186 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2187 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2188 S_008F0C_ELEMENT_SIZE(0) |
2189 S_008F0C_INDEX_STRIDE(0) |
2190 S_008F0C_ADD_TID_ENABLE(false);
2191 }
2192
2193 desc += 8;
2194
2195 if (add_sample_positions) {
2196 /* add sample positions after all rings */
2197 memcpy(desc, queue->device->sample_locations_1x, 8);
2198 desc += 2;
2199 memcpy(desc, queue->device->sample_locations_2x, 16);
2200 desc += 4;
2201 memcpy(desc, queue->device->sample_locations_4x, 32);
2202 desc += 8;
2203 memcpy(desc, queue->device->sample_locations_8x, 64);
2204 }
2205 }
2206
2207 static unsigned
2208 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2209 {
2210 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2211 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2212 device->physical_device->rad_info.family != CHIP_STONEY;
2213 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2214 unsigned max_offchip_buffers;
2215 unsigned offchip_granularity;
2216 unsigned hs_offchip_param;
2217
2218 /*
2219 * Per RadeonSI:
2220 * This must be one less than the maximum number due to a hw limitation.
2221 * Various hardware bugs in SI, CIK, and GFX9 need this.
2222 *
2223 * Per AMDVLK:
2224 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2225 * Gfx7 should limit max_offchip_buffers to 508
2226 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2227 *
2228 * Follow AMDVLK here.
2229 */
2230 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2231 device->physical_device->rad_info.chip_class == CIK ||
2232 device->physical_device->rad_info.chip_class == SI)
2233 --max_offchip_buffers_per_se;
2234
2235 max_offchip_buffers = max_offchip_buffers_per_se *
2236 device->physical_device->rad_info.max_se;
2237
2238 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2239 * around by setting 4K granularity.
2240 */
2241 if (device->tess_offchip_block_dw_size == 4096) {
2242 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2243 offchip_granularity = V_03093C_X_4K_DWORDS;
2244 } else {
2245 assert(device->tess_offchip_block_dw_size == 8192);
2246 offchip_granularity = V_03093C_X_8K_DWORDS;
2247 }
2248
2249 switch (device->physical_device->rad_info.chip_class) {
2250 case SI:
2251 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2252 break;
2253 case CIK:
2254 case VI:
2255 case GFX9:
2256 default:
2257 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2258 break;
2259 }
2260
2261 *max_offchip_buffers_p = max_offchip_buffers;
2262 if (device->physical_device->rad_info.chip_class >= CIK) {
2263 if (device->physical_device->rad_info.chip_class >= VI)
2264 --max_offchip_buffers;
2265 hs_offchip_param =
2266 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2267 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2268 } else {
2269 hs_offchip_param =
2270 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2271 }
2272 return hs_offchip_param;
2273 }
2274
2275 static void
2276 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2277 struct radeon_winsys_bo *esgs_ring_bo,
2278 uint32_t esgs_ring_size,
2279 struct radeon_winsys_bo *gsvs_ring_bo,
2280 uint32_t gsvs_ring_size)
2281 {
2282 if (!esgs_ring_bo && !gsvs_ring_bo)
2283 return;
2284
2285 if (esgs_ring_bo)
2286 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2287
2288 if (gsvs_ring_bo)
2289 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2290
2291 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2292 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2293 radeon_emit(cs, esgs_ring_size >> 8);
2294 radeon_emit(cs, gsvs_ring_size >> 8);
2295 } else {
2296 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2297 radeon_emit(cs, esgs_ring_size >> 8);
2298 radeon_emit(cs, gsvs_ring_size >> 8);
2299 }
2300 }
2301
2302 static void
2303 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2304 unsigned hs_offchip_param, unsigned tf_ring_size,
2305 struct radeon_winsys_bo *tess_rings_bo)
2306 {
2307 uint64_t tf_va;
2308
2309 if (!tess_rings_bo)
2310 return;
2311
2312 tf_va = radv_buffer_get_va(tess_rings_bo);
2313
2314 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2315
2316 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2317 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2318 S_030938_SIZE(tf_ring_size / 4));
2319 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2320 tf_va >> 8);
2321 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2322 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2323 S_030944_BASE_HI(tf_va >> 40));
2324 }
2325 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2326 hs_offchip_param);
2327 } else {
2328 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2329 S_008988_SIZE(tf_ring_size / 4));
2330 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2331 tf_va >> 8);
2332 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2333 hs_offchip_param);
2334 }
2335 }
2336
2337 static void
2338 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2339 struct radeon_winsys_bo *compute_scratch_bo)
2340 {
2341 uint64_t scratch_va;
2342
2343 if (!compute_scratch_bo)
2344 return;
2345
2346 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2347
2348 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2349
2350 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2351 radeon_emit(cs, scratch_va);
2352 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2353 S_008F04_SWIZZLE_ENABLE(1));
2354 }
2355
2356 static void
2357 radv_emit_global_shader_pointers(struct radv_queue *queue,
2358 struct radeon_cmdbuf *cs,
2359 struct radeon_winsys_bo *descriptor_bo)
2360 {
2361 uint64_t va;
2362
2363 if (!descriptor_bo)
2364 return;
2365
2366 va = radv_buffer_get_va(descriptor_bo);
2367
2368 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2369
2370 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2371 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2372 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2373 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2374 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2375
2376 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2377 radv_emit_shader_pointer(queue->device, cs, regs[i],
2378 va, true);
2379 }
2380 } else {
2381 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2382 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2383 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2384 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2385 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2386 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2387
2388 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2389 radv_emit_shader_pointer(queue->device, cs, regs[i],
2390 va, true);
2391 }
2392 }
2393 }
2394
2395 static void
2396 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2397 {
2398 struct radv_device *device = queue->device;
2399
2400 if (device->gfx_init) {
2401 uint64_t va = radv_buffer_get_va(device->gfx_init);
2402
2403 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2404 radeon_emit(cs, va);
2405 radeon_emit(cs, va >> 32);
2406 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2407
2408 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2409 } else {
2410 struct radv_physical_device *physical_device = device->physical_device;
2411 si_emit_graphics(physical_device, cs);
2412 }
2413 }
2414
2415 static void
2416 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2417 {
2418 struct radv_physical_device *physical_device = queue->device->physical_device;
2419 si_emit_compute(physical_device, cs);
2420 }
2421
2422 static VkResult
2423 radv_get_preamble_cs(struct radv_queue *queue,
2424 uint32_t scratch_size,
2425 uint32_t compute_scratch_size,
2426 uint32_t esgs_ring_size,
2427 uint32_t gsvs_ring_size,
2428 bool needs_tess_rings,
2429 bool needs_sample_positions,
2430 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2431 struct radeon_cmdbuf **initial_preamble_cs,
2432 struct radeon_cmdbuf **continue_preamble_cs)
2433 {
2434 struct radeon_winsys_bo *scratch_bo = NULL;
2435 struct radeon_winsys_bo *descriptor_bo = NULL;
2436 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2437 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2438 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2439 struct radeon_winsys_bo *tess_rings_bo = NULL;
2440 struct radeon_cmdbuf *dest_cs[3] = {0};
2441 bool add_tess_rings = false, add_sample_positions = false;
2442 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2443 unsigned max_offchip_buffers;
2444 unsigned hs_offchip_param = 0;
2445 unsigned tess_offchip_ring_offset;
2446 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2447 if (!queue->has_tess_rings) {
2448 if (needs_tess_rings)
2449 add_tess_rings = true;
2450 }
2451 if (!queue->has_sample_positions) {
2452 if (needs_sample_positions)
2453 add_sample_positions = true;
2454 }
2455 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2456 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2457 &max_offchip_buffers);
2458 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2459 tess_offchip_ring_size = max_offchip_buffers *
2460 queue->device->tess_offchip_block_dw_size * 4;
2461
2462 if (scratch_size <= queue->scratch_size &&
2463 compute_scratch_size <= queue->compute_scratch_size &&
2464 esgs_ring_size <= queue->esgs_ring_size &&
2465 gsvs_ring_size <= queue->gsvs_ring_size &&
2466 !add_tess_rings && !add_sample_positions &&
2467 queue->initial_preamble_cs) {
2468 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2469 *initial_preamble_cs = queue->initial_preamble_cs;
2470 *continue_preamble_cs = queue->continue_preamble_cs;
2471 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2472 *continue_preamble_cs = NULL;
2473 return VK_SUCCESS;
2474 }
2475
2476 if (scratch_size > queue->scratch_size) {
2477 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2478 scratch_size,
2479 4096,
2480 RADEON_DOMAIN_VRAM,
2481 ring_bo_flags,
2482 RADV_BO_PRIORITY_SCRATCH);
2483 if (!scratch_bo)
2484 goto fail;
2485 } else
2486 scratch_bo = queue->scratch_bo;
2487
2488 if (compute_scratch_size > queue->compute_scratch_size) {
2489 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2490 compute_scratch_size,
2491 4096,
2492 RADEON_DOMAIN_VRAM,
2493 ring_bo_flags,
2494 RADV_BO_PRIORITY_SCRATCH);
2495 if (!compute_scratch_bo)
2496 goto fail;
2497
2498 } else
2499 compute_scratch_bo = queue->compute_scratch_bo;
2500
2501 if (esgs_ring_size > queue->esgs_ring_size) {
2502 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2503 esgs_ring_size,
2504 4096,
2505 RADEON_DOMAIN_VRAM,
2506 ring_bo_flags,
2507 RADV_BO_PRIORITY_SCRATCH);
2508 if (!esgs_ring_bo)
2509 goto fail;
2510 } else {
2511 esgs_ring_bo = queue->esgs_ring_bo;
2512 esgs_ring_size = queue->esgs_ring_size;
2513 }
2514
2515 if (gsvs_ring_size > queue->gsvs_ring_size) {
2516 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2517 gsvs_ring_size,
2518 4096,
2519 RADEON_DOMAIN_VRAM,
2520 ring_bo_flags,
2521 RADV_BO_PRIORITY_SCRATCH);
2522 if (!gsvs_ring_bo)
2523 goto fail;
2524 } else {
2525 gsvs_ring_bo = queue->gsvs_ring_bo;
2526 gsvs_ring_size = queue->gsvs_ring_size;
2527 }
2528
2529 if (add_tess_rings) {
2530 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2531 tess_offchip_ring_offset + tess_offchip_ring_size,
2532 256,
2533 RADEON_DOMAIN_VRAM,
2534 ring_bo_flags,
2535 RADV_BO_PRIORITY_SCRATCH);
2536 if (!tess_rings_bo)
2537 goto fail;
2538 } else {
2539 tess_rings_bo = queue->tess_rings_bo;
2540 }
2541
2542 if (scratch_bo != queue->scratch_bo ||
2543 esgs_ring_bo != queue->esgs_ring_bo ||
2544 gsvs_ring_bo != queue->gsvs_ring_bo ||
2545 tess_rings_bo != queue->tess_rings_bo ||
2546 add_sample_positions) {
2547 uint32_t size = 0;
2548 if (gsvs_ring_bo || esgs_ring_bo ||
2549 tess_rings_bo || add_sample_positions) {
2550 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2551 if (add_sample_positions)
2552 size += 128; /* 64+32+16+8 = 120 bytes */
2553 }
2554 else if (scratch_bo)
2555 size = 8; /* 2 dword */
2556
2557 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2558 size,
2559 4096,
2560 RADEON_DOMAIN_VRAM,
2561 RADEON_FLAG_CPU_ACCESS |
2562 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2563 RADEON_FLAG_READ_ONLY,
2564 RADV_BO_PRIORITY_DESCRIPTOR);
2565 if (!descriptor_bo)
2566 goto fail;
2567 } else
2568 descriptor_bo = queue->descriptor_bo;
2569
2570 if (descriptor_bo != queue->descriptor_bo) {
2571 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2572
2573 if (scratch_bo) {
2574 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2575 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2576 S_008F04_SWIZZLE_ENABLE(1);
2577 map[0] = scratch_va;
2578 map[1] = rsrc1;
2579 }
2580
2581 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2582 fill_geom_tess_rings(queue, map, add_sample_positions,
2583 esgs_ring_size, esgs_ring_bo,
2584 gsvs_ring_size, gsvs_ring_bo,
2585 tess_factor_ring_size,
2586 tess_offchip_ring_offset,
2587 tess_offchip_ring_size,
2588 tess_rings_bo);
2589
2590 queue->device->ws->buffer_unmap(descriptor_bo);
2591 }
2592
2593 for(int i = 0; i < 3; ++i) {
2594 struct radeon_cmdbuf *cs = NULL;
2595 cs = queue->device->ws->cs_create(queue->device->ws,
2596 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2597 if (!cs)
2598 goto fail;
2599
2600 dest_cs[i] = cs;
2601
2602 if (scratch_bo)
2603 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2604
2605 /* Emit initial configuration. */
2606 switch (queue->queue_family_index) {
2607 case RADV_QUEUE_GENERAL:
2608 radv_init_graphics_state(cs, queue);
2609 break;
2610 case RADV_QUEUE_COMPUTE:
2611 radv_init_compute_state(cs, queue);
2612 break;
2613 case RADV_QUEUE_TRANSFER:
2614 break;
2615 }
2616
2617 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2618 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2619 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2620 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2621 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2622 }
2623
2624 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2625 gsvs_ring_bo, gsvs_ring_size);
2626 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2627 tess_factor_ring_size, tess_rings_bo);
2628 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2629 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2630
2631 if (i == 0) {
2632 si_cs_emit_cache_flush(cs,
2633 queue->device->physical_device->rad_info.chip_class,
2634 NULL, 0,
2635 queue->queue_family_index == RING_COMPUTE &&
2636 queue->device->physical_device->rad_info.chip_class >= CIK,
2637 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2638 RADV_CMD_FLAG_INV_ICACHE |
2639 RADV_CMD_FLAG_INV_SMEM_L1 |
2640 RADV_CMD_FLAG_INV_VMEM_L1 |
2641 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2642 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2643 } else if (i == 1) {
2644 si_cs_emit_cache_flush(cs,
2645 queue->device->physical_device->rad_info.chip_class,
2646 NULL, 0,
2647 queue->queue_family_index == RING_COMPUTE &&
2648 queue->device->physical_device->rad_info.chip_class >= CIK,
2649 RADV_CMD_FLAG_INV_ICACHE |
2650 RADV_CMD_FLAG_INV_SMEM_L1 |
2651 RADV_CMD_FLAG_INV_VMEM_L1 |
2652 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2653 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2654 }
2655
2656 if (!queue->device->ws->cs_finalize(cs))
2657 goto fail;
2658 }
2659
2660 if (queue->initial_full_flush_preamble_cs)
2661 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2662
2663 if (queue->initial_preamble_cs)
2664 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2665
2666 if (queue->continue_preamble_cs)
2667 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2668
2669 queue->initial_full_flush_preamble_cs = dest_cs[0];
2670 queue->initial_preamble_cs = dest_cs[1];
2671 queue->continue_preamble_cs = dest_cs[2];
2672
2673 if (scratch_bo != queue->scratch_bo) {
2674 if (queue->scratch_bo)
2675 queue->device->ws->buffer_destroy(queue->scratch_bo);
2676 queue->scratch_bo = scratch_bo;
2677 queue->scratch_size = scratch_size;
2678 }
2679
2680 if (compute_scratch_bo != queue->compute_scratch_bo) {
2681 if (queue->compute_scratch_bo)
2682 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2683 queue->compute_scratch_bo = compute_scratch_bo;
2684 queue->compute_scratch_size = compute_scratch_size;
2685 }
2686
2687 if (esgs_ring_bo != queue->esgs_ring_bo) {
2688 if (queue->esgs_ring_bo)
2689 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2690 queue->esgs_ring_bo = esgs_ring_bo;
2691 queue->esgs_ring_size = esgs_ring_size;
2692 }
2693
2694 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2695 if (queue->gsvs_ring_bo)
2696 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2697 queue->gsvs_ring_bo = gsvs_ring_bo;
2698 queue->gsvs_ring_size = gsvs_ring_size;
2699 }
2700
2701 if (tess_rings_bo != queue->tess_rings_bo) {
2702 queue->tess_rings_bo = tess_rings_bo;
2703 queue->has_tess_rings = true;
2704 }
2705
2706 if (descriptor_bo != queue->descriptor_bo) {
2707 if (queue->descriptor_bo)
2708 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2709
2710 queue->descriptor_bo = descriptor_bo;
2711 }
2712
2713 if (add_sample_positions)
2714 queue->has_sample_positions = true;
2715
2716 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2717 *initial_preamble_cs = queue->initial_preamble_cs;
2718 *continue_preamble_cs = queue->continue_preamble_cs;
2719 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2720 *continue_preamble_cs = NULL;
2721 return VK_SUCCESS;
2722 fail:
2723 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2724 if (dest_cs[i])
2725 queue->device->ws->cs_destroy(dest_cs[i]);
2726 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2727 queue->device->ws->buffer_destroy(descriptor_bo);
2728 if (scratch_bo && scratch_bo != queue->scratch_bo)
2729 queue->device->ws->buffer_destroy(scratch_bo);
2730 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2731 queue->device->ws->buffer_destroy(compute_scratch_bo);
2732 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2733 queue->device->ws->buffer_destroy(esgs_ring_bo);
2734 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2735 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2736 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2737 queue->device->ws->buffer_destroy(tess_rings_bo);
2738 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2739 }
2740
2741 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2742 struct radv_winsys_sem_counts *counts,
2743 int num_sems,
2744 const VkSemaphore *sems,
2745 VkFence _fence,
2746 bool reset_temp)
2747 {
2748 int syncobj_idx = 0, sem_idx = 0;
2749
2750 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2751 return VK_SUCCESS;
2752
2753 for (uint32_t i = 0; i < num_sems; i++) {
2754 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2755
2756 if (sem->temp_syncobj || sem->syncobj)
2757 counts->syncobj_count++;
2758 else
2759 counts->sem_count++;
2760 }
2761
2762 if (_fence != VK_NULL_HANDLE) {
2763 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2764 if (fence->temp_syncobj || fence->syncobj)
2765 counts->syncobj_count++;
2766 }
2767
2768 if (counts->syncobj_count) {
2769 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2770 if (!counts->syncobj)
2771 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2772 }
2773
2774 if (counts->sem_count) {
2775 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2776 if (!counts->sem) {
2777 free(counts->syncobj);
2778 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2779 }
2780 }
2781
2782 for (uint32_t i = 0; i < num_sems; i++) {
2783 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2784
2785 if (sem->temp_syncobj) {
2786 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2787 }
2788 else if (sem->syncobj)
2789 counts->syncobj[syncobj_idx++] = sem->syncobj;
2790 else {
2791 assert(sem->sem);
2792 counts->sem[sem_idx++] = sem->sem;
2793 }
2794 }
2795
2796 if (_fence != VK_NULL_HANDLE) {
2797 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2798 if (fence->temp_syncobj)
2799 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2800 else if (fence->syncobj)
2801 counts->syncobj[syncobj_idx++] = fence->syncobj;
2802 }
2803
2804 return VK_SUCCESS;
2805 }
2806
2807 static void
2808 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2809 {
2810 free(sem_info->wait.syncobj);
2811 free(sem_info->wait.sem);
2812 free(sem_info->signal.syncobj);
2813 free(sem_info->signal.sem);
2814 }
2815
2816
2817 static void radv_free_temp_syncobjs(struct radv_device *device,
2818 int num_sems,
2819 const VkSemaphore *sems)
2820 {
2821 for (uint32_t i = 0; i < num_sems; i++) {
2822 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2823
2824 if (sem->temp_syncobj) {
2825 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2826 sem->temp_syncobj = 0;
2827 }
2828 }
2829 }
2830
2831 static VkResult
2832 radv_alloc_sem_info(struct radv_instance *instance,
2833 struct radv_winsys_sem_info *sem_info,
2834 int num_wait_sems,
2835 const VkSemaphore *wait_sems,
2836 int num_signal_sems,
2837 const VkSemaphore *signal_sems,
2838 VkFence fence)
2839 {
2840 VkResult ret;
2841 memset(sem_info, 0, sizeof(*sem_info));
2842
2843 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2844 if (ret)
2845 return ret;
2846 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2847 if (ret)
2848 radv_free_sem_info(sem_info);
2849
2850 /* caller can override these */
2851 sem_info->cs_emit_wait = true;
2852 sem_info->cs_emit_signal = true;
2853 return ret;
2854 }
2855
2856 /* Signals fence as soon as all the work currently put on queue is done. */
2857 static VkResult radv_signal_fence(struct radv_queue *queue,
2858 struct radv_fence *fence)
2859 {
2860 int ret;
2861 VkResult result;
2862 struct radv_winsys_sem_info sem_info;
2863
2864 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2865 radv_fence_to_handle(fence));
2866 if (result != VK_SUCCESS)
2867 return result;
2868
2869 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2870 &queue->device->empty_cs[queue->queue_family_index],
2871 1, NULL, NULL, &sem_info, NULL,
2872 false, fence->fence);
2873 radv_free_sem_info(&sem_info);
2874
2875 if (ret)
2876 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2877
2878 return VK_SUCCESS;
2879 }
2880
2881 VkResult radv_QueueSubmit(
2882 VkQueue _queue,
2883 uint32_t submitCount,
2884 const VkSubmitInfo* pSubmits,
2885 VkFence _fence)
2886 {
2887 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2888 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2889 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2890 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2891 int ret;
2892 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2893 uint32_t scratch_size = 0;
2894 uint32_t compute_scratch_size = 0;
2895 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2896 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2897 VkResult result;
2898 bool fence_emitted = false;
2899 bool tess_rings_needed = false;
2900 bool sample_positions_needed = false;
2901
2902 /* Do this first so failing to allocate scratch buffers can't result in
2903 * partially executed submissions. */
2904 for (uint32_t i = 0; i < submitCount; i++) {
2905 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2906 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2907 pSubmits[i].pCommandBuffers[j]);
2908
2909 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2910 compute_scratch_size = MAX2(compute_scratch_size,
2911 cmd_buffer->compute_scratch_size_needed);
2912 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2913 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2914 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2915 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2916 }
2917 }
2918
2919 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2920 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2921 sample_positions_needed, &initial_flush_preamble_cs,
2922 &initial_preamble_cs, &continue_preamble_cs);
2923 if (result != VK_SUCCESS)
2924 return result;
2925
2926 for (uint32_t i = 0; i < submitCount; i++) {
2927 struct radeon_cmdbuf **cs_array;
2928 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2929 bool can_patch = true;
2930 uint32_t advance;
2931 struct radv_winsys_sem_info sem_info;
2932
2933 result = radv_alloc_sem_info(queue->device->instance,
2934 &sem_info,
2935 pSubmits[i].waitSemaphoreCount,
2936 pSubmits[i].pWaitSemaphores,
2937 pSubmits[i].signalSemaphoreCount,
2938 pSubmits[i].pSignalSemaphores,
2939 _fence);
2940 if (result != VK_SUCCESS)
2941 return result;
2942
2943 if (!pSubmits[i].commandBufferCount) {
2944 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2945 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2946 &queue->device->empty_cs[queue->queue_family_index],
2947 1, NULL, NULL,
2948 &sem_info, NULL,
2949 false, base_fence);
2950 if (ret) {
2951 radv_loge("failed to submit CS %d\n", i);
2952 abort();
2953 }
2954 fence_emitted = true;
2955 }
2956 radv_free_sem_info(&sem_info);
2957 continue;
2958 }
2959
2960 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2961 (pSubmits[i].commandBufferCount));
2962
2963 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2964 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2965 pSubmits[i].pCommandBuffers[j]);
2966 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2967
2968 cs_array[j] = cmd_buffer->cs;
2969 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2970 can_patch = false;
2971
2972 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2973 }
2974
2975 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2976 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2977 const struct radv_winsys_bo_list *bo_list = NULL;
2978
2979 advance = MIN2(max_cs_submission,
2980 pSubmits[i].commandBufferCount - j);
2981
2982 if (queue->device->trace_bo)
2983 *queue->device->trace_id_ptr = 0;
2984
2985 sem_info.cs_emit_wait = j == 0;
2986 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2987
2988 if (unlikely(queue->device->use_global_bo_list)) {
2989 pthread_mutex_lock(&queue->device->bo_list.mutex);
2990 bo_list = &queue->device->bo_list.list;
2991 }
2992
2993 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2994 advance, initial_preamble, continue_preamble_cs,
2995 &sem_info, bo_list,
2996 can_patch, base_fence);
2997
2998 if (unlikely(queue->device->use_global_bo_list))
2999 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3000
3001 if (ret) {
3002 radv_loge("failed to submit CS %d\n", i);
3003 abort();
3004 }
3005 fence_emitted = true;
3006 if (queue->device->trace_bo) {
3007 radv_check_gpu_hangs(queue, cs_array[j]);
3008 }
3009 }
3010
3011 radv_free_temp_syncobjs(queue->device,
3012 pSubmits[i].waitSemaphoreCount,
3013 pSubmits[i].pWaitSemaphores);
3014 radv_free_sem_info(&sem_info);
3015 free(cs_array);
3016 }
3017
3018 if (fence) {
3019 if (!fence_emitted) {
3020 result = radv_signal_fence(queue, fence);
3021 if (result != VK_SUCCESS)
3022 return result;
3023 }
3024 fence->submitted = true;
3025 }
3026
3027 return VK_SUCCESS;
3028 }
3029
3030 VkResult radv_QueueWaitIdle(
3031 VkQueue _queue)
3032 {
3033 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3034
3035 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3036 radv_queue_family_to_ring(queue->queue_family_index),
3037 queue->queue_idx);
3038 return VK_SUCCESS;
3039 }
3040
3041 VkResult radv_DeviceWaitIdle(
3042 VkDevice _device)
3043 {
3044 RADV_FROM_HANDLE(radv_device, device, _device);
3045
3046 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3047 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3048 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3049 }
3050 }
3051 return VK_SUCCESS;
3052 }
3053
3054 VkResult radv_EnumerateInstanceExtensionProperties(
3055 const char* pLayerName,
3056 uint32_t* pPropertyCount,
3057 VkExtensionProperties* pProperties)
3058 {
3059 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3060
3061 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3062 if (radv_supported_instance_extensions.extensions[i]) {
3063 vk_outarray_append(&out, prop) {
3064 *prop = radv_instance_extensions[i];
3065 }
3066 }
3067 }
3068
3069 return vk_outarray_status(&out);
3070 }
3071
3072 VkResult radv_EnumerateDeviceExtensionProperties(
3073 VkPhysicalDevice physicalDevice,
3074 const char* pLayerName,
3075 uint32_t* pPropertyCount,
3076 VkExtensionProperties* pProperties)
3077 {
3078 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3079 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3080
3081 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3082 if (device->supported_extensions.extensions[i]) {
3083 vk_outarray_append(&out, prop) {
3084 *prop = radv_device_extensions[i];
3085 }
3086 }
3087 }
3088
3089 return vk_outarray_status(&out);
3090 }
3091
3092 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3093 VkInstance _instance,
3094 const char* pName)
3095 {
3096 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3097
3098 return radv_lookup_entrypoint_checked(pName,
3099 instance ? instance->apiVersion : 0,
3100 instance ? &instance->enabled_extensions : NULL,
3101 NULL);
3102 }
3103
3104 /* The loader wants us to expose a second GetInstanceProcAddr function
3105 * to work around certain LD_PRELOAD issues seen in apps.
3106 */
3107 PUBLIC
3108 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3109 VkInstance instance,
3110 const char* pName);
3111
3112 PUBLIC
3113 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3114 VkInstance instance,
3115 const char* pName)
3116 {
3117 return radv_GetInstanceProcAddr(instance, pName);
3118 }
3119
3120 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3121 VkDevice _device,
3122 const char* pName)
3123 {
3124 RADV_FROM_HANDLE(radv_device, device, _device);
3125
3126 return radv_lookup_entrypoint_checked(pName,
3127 device->instance->apiVersion,
3128 &device->instance->enabled_extensions,
3129 &device->enabled_extensions);
3130 }
3131
3132 bool radv_get_memory_fd(struct radv_device *device,
3133 struct radv_device_memory *memory,
3134 int *pFD)
3135 {
3136 struct radeon_bo_metadata metadata;
3137
3138 if (memory->image) {
3139 radv_init_metadata(device, memory->image, &metadata);
3140 device->ws->buffer_set_metadata(memory->bo, &metadata);
3141 }
3142
3143 return device->ws->buffer_get_fd(device->ws, memory->bo,
3144 pFD);
3145 }
3146
3147 static VkResult radv_alloc_memory(struct radv_device *device,
3148 const VkMemoryAllocateInfo* pAllocateInfo,
3149 const VkAllocationCallbacks* pAllocator,
3150 VkDeviceMemory* pMem)
3151 {
3152 struct radv_device_memory *mem;
3153 VkResult result;
3154 enum radeon_bo_domain domain;
3155 uint32_t flags = 0;
3156 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3157
3158 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3159
3160 if (pAllocateInfo->allocationSize == 0) {
3161 /* Apparently, this is allowed */
3162 *pMem = VK_NULL_HANDLE;
3163 return VK_SUCCESS;
3164 }
3165
3166 const VkImportMemoryFdInfoKHR *import_info =
3167 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3168 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3169 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3170 const VkExportMemoryAllocateInfo *export_info =
3171 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3172 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3173 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3174
3175 const struct wsi_memory_allocate_info *wsi_info =
3176 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3177
3178 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3179 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3180 if (mem == NULL)
3181 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3182
3183 if (wsi_info && wsi_info->implicit_sync)
3184 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3185
3186 if (dedicate_info) {
3187 mem->image = radv_image_from_handle(dedicate_info->image);
3188 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3189 } else {
3190 mem->image = NULL;
3191 mem->buffer = NULL;
3192 }
3193
3194 float priority_float = 0.5;
3195 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3196 vk_find_struct_const(pAllocateInfo->pNext,
3197 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3198 if (priority_ext)
3199 priority_float = priority_ext->priority;
3200
3201 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3202 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3203
3204 mem->user_ptr = NULL;
3205
3206 if (import_info) {
3207 assert(import_info->handleType ==
3208 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3209 import_info->handleType ==
3210 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3211 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3212 priority, NULL, NULL);
3213 if (!mem->bo) {
3214 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3215 goto fail;
3216 } else {
3217 close(import_info->fd);
3218 }
3219 } else if (host_ptr_info) {
3220 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3221 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3222 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3223 pAllocateInfo->allocationSize,
3224 priority);
3225 if (!mem->bo) {
3226 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3227 goto fail;
3228 } else {
3229 mem->user_ptr = host_ptr_info->pHostPointer;
3230 }
3231 } else {
3232 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3233 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3234 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3235 domain = RADEON_DOMAIN_GTT;
3236 else
3237 domain = RADEON_DOMAIN_VRAM;
3238
3239 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3240 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3241 else
3242 flags |= RADEON_FLAG_CPU_ACCESS;
3243
3244 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3245 flags |= RADEON_FLAG_GTT_WC;
3246
3247 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3248 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3249 if (device->use_global_bo_list) {
3250 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3251 }
3252 }
3253
3254 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3255 domain, flags, priority);
3256
3257 if (!mem->bo) {
3258 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3259 goto fail;
3260 }
3261 mem->type_index = mem_type_index;
3262 }
3263
3264 result = radv_bo_list_add(device, mem->bo);
3265 if (result != VK_SUCCESS)
3266 goto fail_bo;
3267
3268 *pMem = radv_device_memory_to_handle(mem);
3269
3270 return VK_SUCCESS;
3271
3272 fail_bo:
3273 device->ws->buffer_destroy(mem->bo);
3274 fail:
3275 vk_free2(&device->alloc, pAllocator, mem);
3276
3277 return result;
3278 }
3279
3280 VkResult radv_AllocateMemory(
3281 VkDevice _device,
3282 const VkMemoryAllocateInfo* pAllocateInfo,
3283 const VkAllocationCallbacks* pAllocator,
3284 VkDeviceMemory* pMem)
3285 {
3286 RADV_FROM_HANDLE(radv_device, device, _device);
3287 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3288 }
3289
3290 void radv_FreeMemory(
3291 VkDevice _device,
3292 VkDeviceMemory _mem,
3293 const VkAllocationCallbacks* pAllocator)
3294 {
3295 RADV_FROM_HANDLE(radv_device, device, _device);
3296 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3297
3298 if (mem == NULL)
3299 return;
3300
3301 radv_bo_list_remove(device, mem->bo);
3302 device->ws->buffer_destroy(mem->bo);
3303 mem->bo = NULL;
3304
3305 vk_free2(&device->alloc, pAllocator, mem);
3306 }
3307
3308 VkResult radv_MapMemory(
3309 VkDevice _device,
3310 VkDeviceMemory _memory,
3311 VkDeviceSize offset,
3312 VkDeviceSize size,
3313 VkMemoryMapFlags flags,
3314 void** ppData)
3315 {
3316 RADV_FROM_HANDLE(radv_device, device, _device);
3317 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3318
3319 if (mem == NULL) {
3320 *ppData = NULL;
3321 return VK_SUCCESS;
3322 }
3323
3324 if (mem->user_ptr)
3325 *ppData = mem->user_ptr;
3326 else
3327 *ppData = device->ws->buffer_map(mem->bo);
3328
3329 if (*ppData) {
3330 *ppData += offset;
3331 return VK_SUCCESS;
3332 }
3333
3334 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3335 }
3336
3337 void radv_UnmapMemory(
3338 VkDevice _device,
3339 VkDeviceMemory _memory)
3340 {
3341 RADV_FROM_HANDLE(radv_device, device, _device);
3342 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3343
3344 if (mem == NULL)
3345 return;
3346
3347 if (mem->user_ptr == NULL)
3348 device->ws->buffer_unmap(mem->bo);
3349 }
3350
3351 VkResult radv_FlushMappedMemoryRanges(
3352 VkDevice _device,
3353 uint32_t memoryRangeCount,
3354 const VkMappedMemoryRange* pMemoryRanges)
3355 {
3356 return VK_SUCCESS;
3357 }
3358
3359 VkResult radv_InvalidateMappedMemoryRanges(
3360 VkDevice _device,
3361 uint32_t memoryRangeCount,
3362 const VkMappedMemoryRange* pMemoryRanges)
3363 {
3364 return VK_SUCCESS;
3365 }
3366
3367 void radv_GetBufferMemoryRequirements(
3368 VkDevice _device,
3369 VkBuffer _buffer,
3370 VkMemoryRequirements* pMemoryRequirements)
3371 {
3372 RADV_FROM_HANDLE(radv_device, device, _device);
3373 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3374
3375 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3376
3377 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3378 pMemoryRequirements->alignment = 4096;
3379 else
3380 pMemoryRequirements->alignment = 16;
3381
3382 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3383 }
3384
3385 void radv_GetBufferMemoryRequirements2(
3386 VkDevice device,
3387 const VkBufferMemoryRequirementsInfo2 *pInfo,
3388 VkMemoryRequirements2 *pMemoryRequirements)
3389 {
3390 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3391 &pMemoryRequirements->memoryRequirements);
3392 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3393 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3394 switch (ext->sType) {
3395 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3396 VkMemoryDedicatedRequirements *req =
3397 (VkMemoryDedicatedRequirements *) ext;
3398 req->requiresDedicatedAllocation = buffer->shareable;
3399 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3400 break;
3401 }
3402 default:
3403 break;
3404 }
3405 }
3406 }
3407
3408 void radv_GetImageMemoryRequirements(
3409 VkDevice _device,
3410 VkImage _image,
3411 VkMemoryRequirements* pMemoryRequirements)
3412 {
3413 RADV_FROM_HANDLE(radv_device, device, _device);
3414 RADV_FROM_HANDLE(radv_image, image, _image);
3415
3416 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3417
3418 pMemoryRequirements->size = image->size;
3419 pMemoryRequirements->alignment = image->alignment;
3420 }
3421
3422 void radv_GetImageMemoryRequirements2(
3423 VkDevice device,
3424 const VkImageMemoryRequirementsInfo2 *pInfo,
3425 VkMemoryRequirements2 *pMemoryRequirements)
3426 {
3427 radv_GetImageMemoryRequirements(device, pInfo->image,
3428 &pMemoryRequirements->memoryRequirements);
3429
3430 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3431
3432 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3433 switch (ext->sType) {
3434 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3435 VkMemoryDedicatedRequirements *req =
3436 (VkMemoryDedicatedRequirements *) ext;
3437 req->requiresDedicatedAllocation = image->shareable;
3438 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3439 break;
3440 }
3441 default:
3442 break;
3443 }
3444 }
3445 }
3446
3447 void radv_GetImageSparseMemoryRequirements(
3448 VkDevice device,
3449 VkImage image,
3450 uint32_t* pSparseMemoryRequirementCount,
3451 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3452 {
3453 stub();
3454 }
3455
3456 void radv_GetImageSparseMemoryRequirements2(
3457 VkDevice device,
3458 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3459 uint32_t* pSparseMemoryRequirementCount,
3460 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3461 {
3462 stub();
3463 }
3464
3465 void radv_GetDeviceMemoryCommitment(
3466 VkDevice device,
3467 VkDeviceMemory memory,
3468 VkDeviceSize* pCommittedMemoryInBytes)
3469 {
3470 *pCommittedMemoryInBytes = 0;
3471 }
3472
3473 VkResult radv_BindBufferMemory2(VkDevice device,
3474 uint32_t bindInfoCount,
3475 const VkBindBufferMemoryInfo *pBindInfos)
3476 {
3477 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3478 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3479 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3480
3481 if (mem) {
3482 buffer->bo = mem->bo;
3483 buffer->offset = pBindInfos[i].memoryOffset;
3484 } else {
3485 buffer->bo = NULL;
3486 }
3487 }
3488 return VK_SUCCESS;
3489 }
3490
3491 VkResult radv_BindBufferMemory(
3492 VkDevice device,
3493 VkBuffer buffer,
3494 VkDeviceMemory memory,
3495 VkDeviceSize memoryOffset)
3496 {
3497 const VkBindBufferMemoryInfo info = {
3498 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3499 .buffer = buffer,
3500 .memory = memory,
3501 .memoryOffset = memoryOffset
3502 };
3503
3504 return radv_BindBufferMemory2(device, 1, &info);
3505 }
3506
3507 VkResult radv_BindImageMemory2(VkDevice device,
3508 uint32_t bindInfoCount,
3509 const VkBindImageMemoryInfo *pBindInfos)
3510 {
3511 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3512 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3513 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3514
3515 if (mem) {
3516 image->bo = mem->bo;
3517 image->offset = pBindInfos[i].memoryOffset;
3518 } else {
3519 image->bo = NULL;
3520 image->offset = 0;
3521 }
3522 }
3523 return VK_SUCCESS;
3524 }
3525
3526
3527 VkResult radv_BindImageMemory(
3528 VkDevice device,
3529 VkImage image,
3530 VkDeviceMemory memory,
3531 VkDeviceSize memoryOffset)
3532 {
3533 const VkBindImageMemoryInfo info = {
3534 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3535 .image = image,
3536 .memory = memory,
3537 .memoryOffset = memoryOffset
3538 };
3539
3540 return radv_BindImageMemory2(device, 1, &info);
3541 }
3542
3543
3544 static void
3545 radv_sparse_buffer_bind_memory(struct radv_device *device,
3546 const VkSparseBufferMemoryBindInfo *bind)
3547 {
3548 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3549
3550 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3551 struct radv_device_memory *mem = NULL;
3552
3553 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3554 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3555
3556 device->ws->buffer_virtual_bind(buffer->bo,
3557 bind->pBinds[i].resourceOffset,
3558 bind->pBinds[i].size,
3559 mem ? mem->bo : NULL,
3560 bind->pBinds[i].memoryOffset);
3561 }
3562 }
3563
3564 static void
3565 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3566 const VkSparseImageOpaqueMemoryBindInfo *bind)
3567 {
3568 RADV_FROM_HANDLE(radv_image, image, bind->image);
3569
3570 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3571 struct radv_device_memory *mem = NULL;
3572
3573 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3574 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3575
3576 device->ws->buffer_virtual_bind(image->bo,
3577 bind->pBinds[i].resourceOffset,
3578 bind->pBinds[i].size,
3579 mem ? mem->bo : NULL,
3580 bind->pBinds[i].memoryOffset);
3581 }
3582 }
3583
3584 VkResult radv_QueueBindSparse(
3585 VkQueue _queue,
3586 uint32_t bindInfoCount,
3587 const VkBindSparseInfo* pBindInfo,
3588 VkFence _fence)
3589 {
3590 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3591 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3592 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3593 bool fence_emitted = false;
3594 VkResult result;
3595 int ret;
3596
3597 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3598 struct radv_winsys_sem_info sem_info;
3599 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3600 radv_sparse_buffer_bind_memory(queue->device,
3601 pBindInfo[i].pBufferBinds + j);
3602 }
3603
3604 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3605 radv_sparse_image_opaque_bind_memory(queue->device,
3606 pBindInfo[i].pImageOpaqueBinds + j);
3607 }
3608
3609 VkResult result;
3610 result = radv_alloc_sem_info(queue->device->instance,
3611 &sem_info,
3612 pBindInfo[i].waitSemaphoreCount,
3613 pBindInfo[i].pWaitSemaphores,
3614 pBindInfo[i].signalSemaphoreCount,
3615 pBindInfo[i].pSignalSemaphores,
3616 _fence);
3617 if (result != VK_SUCCESS)
3618 return result;
3619
3620 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3621 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3622 &queue->device->empty_cs[queue->queue_family_index],
3623 1, NULL, NULL,
3624 &sem_info, NULL,
3625 false, base_fence);
3626 if (ret) {
3627 radv_loge("failed to submit CS %d\n", i);
3628 abort();
3629 }
3630
3631 fence_emitted = true;
3632 if (fence)
3633 fence->submitted = true;
3634 }
3635
3636 radv_free_sem_info(&sem_info);
3637
3638 }
3639
3640 if (fence) {
3641 if (!fence_emitted) {
3642 result = radv_signal_fence(queue, fence);
3643 if (result != VK_SUCCESS)
3644 return result;
3645 }
3646 fence->submitted = true;
3647 }
3648
3649 return VK_SUCCESS;
3650 }
3651
3652 VkResult radv_CreateFence(
3653 VkDevice _device,
3654 const VkFenceCreateInfo* pCreateInfo,
3655 const VkAllocationCallbacks* pAllocator,
3656 VkFence* pFence)
3657 {
3658 RADV_FROM_HANDLE(radv_device, device, _device);
3659 const VkExportFenceCreateInfo *export =
3660 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3661 VkExternalFenceHandleTypeFlags handleTypes =
3662 export ? export->handleTypes : 0;
3663
3664 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3665 sizeof(*fence), 8,
3666 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3667
3668 if (!fence)
3669 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3670
3671 fence->fence_wsi = NULL;
3672 fence->submitted = false;
3673 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3674 fence->temp_syncobj = 0;
3675 if (device->always_use_syncobj || handleTypes) {
3676 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3677 if (ret) {
3678 vk_free2(&device->alloc, pAllocator, fence);
3679 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3680 }
3681 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3682 device->ws->signal_syncobj(device->ws, fence->syncobj);
3683 }
3684 fence->fence = NULL;
3685 } else {
3686 fence->fence = device->ws->create_fence();
3687 if (!fence->fence) {
3688 vk_free2(&device->alloc, pAllocator, fence);
3689 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3690 }
3691 fence->syncobj = 0;
3692 }
3693
3694 *pFence = radv_fence_to_handle(fence);
3695
3696 return VK_SUCCESS;
3697 }
3698
3699 void radv_DestroyFence(
3700 VkDevice _device,
3701 VkFence _fence,
3702 const VkAllocationCallbacks* pAllocator)
3703 {
3704 RADV_FROM_HANDLE(radv_device, device, _device);
3705 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3706
3707 if (!fence)
3708 return;
3709
3710 if (fence->temp_syncobj)
3711 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3712 if (fence->syncobj)
3713 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3714 if (fence->fence)
3715 device->ws->destroy_fence(fence->fence);
3716 if (fence->fence_wsi)
3717 fence->fence_wsi->destroy(fence->fence_wsi);
3718 vk_free2(&device->alloc, pAllocator, fence);
3719 }
3720
3721
3722 uint64_t radv_get_current_time(void)
3723 {
3724 struct timespec tv;
3725 clock_gettime(CLOCK_MONOTONIC, &tv);
3726 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3727 }
3728
3729 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3730 {
3731 uint64_t current_time = radv_get_current_time();
3732
3733 timeout = MIN2(UINT64_MAX - current_time, timeout);
3734
3735 return current_time + timeout;
3736 }
3737
3738
3739 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3740 {
3741 for (uint32_t i = 0; i < fenceCount; ++i) {
3742 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3743 if (fence->fence == NULL || fence->syncobj ||
3744 fence->temp_syncobj ||
3745 (!fence->signalled && !fence->submitted))
3746 return false;
3747 }
3748 return true;
3749 }
3750
3751 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3752 {
3753 for (uint32_t i = 0; i < fenceCount; ++i) {
3754 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3755 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3756 return false;
3757 }
3758 return true;
3759 }
3760
3761 VkResult radv_WaitForFences(
3762 VkDevice _device,
3763 uint32_t fenceCount,
3764 const VkFence* pFences,
3765 VkBool32 waitAll,
3766 uint64_t timeout)
3767 {
3768 RADV_FROM_HANDLE(radv_device, device, _device);
3769 timeout = radv_get_absolute_timeout(timeout);
3770
3771 if (device->always_use_syncobj &&
3772 radv_all_fences_syncobj(fenceCount, pFences))
3773 {
3774 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3775 if (!handles)
3776 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3777
3778 for (uint32_t i = 0; i < fenceCount; ++i) {
3779 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3780 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3781 }
3782
3783 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3784
3785 free(handles);
3786 return success ? VK_SUCCESS : VK_TIMEOUT;
3787 }
3788
3789 if (!waitAll && fenceCount > 1) {
3790 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3791 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3792 uint32_t wait_count = 0;
3793 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3794 if (!fences)
3795 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3796
3797 for (uint32_t i = 0; i < fenceCount; ++i) {
3798 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3799
3800 if (fence->signalled) {
3801 free(fences);
3802 return VK_SUCCESS;
3803 }
3804
3805 fences[wait_count++] = fence->fence;
3806 }
3807
3808 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3809 waitAll, timeout - radv_get_current_time());
3810
3811 free(fences);
3812 return success ? VK_SUCCESS : VK_TIMEOUT;
3813 }
3814
3815 while(radv_get_current_time() <= timeout) {
3816 for (uint32_t i = 0; i < fenceCount; ++i) {
3817 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3818 return VK_SUCCESS;
3819 }
3820 }
3821 return VK_TIMEOUT;
3822 }
3823
3824 for (uint32_t i = 0; i < fenceCount; ++i) {
3825 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3826 bool expired = false;
3827
3828 if (fence->temp_syncobj) {
3829 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3830 return VK_TIMEOUT;
3831 continue;
3832 }
3833
3834 if (fence->syncobj) {
3835 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3836 return VK_TIMEOUT;
3837 continue;
3838 }
3839
3840 if (fence->signalled)
3841 continue;
3842
3843 if (fence->fence) {
3844 if (!fence->submitted) {
3845 while(radv_get_current_time() <= timeout &&
3846 !fence->submitted)
3847 /* Do nothing */;
3848
3849 if (!fence->submitted)
3850 return VK_TIMEOUT;
3851
3852 /* Recheck as it may have been set by
3853 * submitting operations. */
3854
3855 if (fence->signalled)
3856 continue;
3857 }
3858
3859 expired = device->ws->fence_wait(device->ws,
3860 fence->fence,
3861 true, timeout);
3862 if (!expired)
3863 return VK_TIMEOUT;
3864 }
3865
3866 if (fence->fence_wsi) {
3867 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3868 if (result != VK_SUCCESS)
3869 return result;
3870 }
3871
3872 fence->signalled = true;
3873 }
3874
3875 return VK_SUCCESS;
3876 }
3877
3878 VkResult radv_ResetFences(VkDevice _device,
3879 uint32_t fenceCount,
3880 const VkFence *pFences)
3881 {
3882 RADV_FROM_HANDLE(radv_device, device, _device);
3883
3884 for (unsigned i = 0; i < fenceCount; ++i) {
3885 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3886 fence->submitted = fence->signalled = false;
3887
3888 /* Per spec, we first restore the permanent payload, and then reset, so
3889 * having a temp syncobj should not skip resetting the permanent syncobj. */
3890 if (fence->temp_syncobj) {
3891 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3892 fence->temp_syncobj = 0;
3893 }
3894
3895 if (fence->syncobj) {
3896 device->ws->reset_syncobj(device->ws, fence->syncobj);
3897 }
3898 }
3899
3900 return VK_SUCCESS;
3901 }
3902
3903 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3904 {
3905 RADV_FROM_HANDLE(radv_device, device, _device);
3906 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3907
3908 if (fence->temp_syncobj) {
3909 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3910 return success ? VK_SUCCESS : VK_NOT_READY;
3911 }
3912
3913 if (fence->syncobj) {
3914 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3915 return success ? VK_SUCCESS : VK_NOT_READY;
3916 }
3917
3918 if (fence->signalled)
3919 return VK_SUCCESS;
3920 if (!fence->submitted)
3921 return VK_NOT_READY;
3922 if (fence->fence) {
3923 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3924 return VK_NOT_READY;
3925 }
3926 if (fence->fence_wsi) {
3927 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3928
3929 if (result != VK_SUCCESS) {
3930 if (result == VK_TIMEOUT)
3931 return VK_NOT_READY;
3932 return result;
3933 }
3934 }
3935 return VK_SUCCESS;
3936 }
3937
3938
3939 // Queue semaphore functions
3940
3941 VkResult radv_CreateSemaphore(
3942 VkDevice _device,
3943 const VkSemaphoreCreateInfo* pCreateInfo,
3944 const VkAllocationCallbacks* pAllocator,
3945 VkSemaphore* pSemaphore)
3946 {
3947 RADV_FROM_HANDLE(radv_device, device, _device);
3948 const VkExportSemaphoreCreateInfo *export =
3949 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3950 VkExternalSemaphoreHandleTypeFlags handleTypes =
3951 export ? export->handleTypes : 0;
3952
3953 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3954 sizeof(*sem), 8,
3955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3956 if (!sem)
3957 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3958
3959 sem->temp_syncobj = 0;
3960 /* create a syncobject if we are going to export this semaphore */
3961 if (device->always_use_syncobj || handleTypes) {
3962 assert (device->physical_device->rad_info.has_syncobj);
3963 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3964 if (ret) {
3965 vk_free2(&device->alloc, pAllocator, sem);
3966 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3967 }
3968 sem->sem = NULL;
3969 } else {
3970 sem->sem = device->ws->create_sem(device->ws);
3971 if (!sem->sem) {
3972 vk_free2(&device->alloc, pAllocator, sem);
3973 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3974 }
3975 sem->syncobj = 0;
3976 }
3977
3978 *pSemaphore = radv_semaphore_to_handle(sem);
3979 return VK_SUCCESS;
3980 }
3981
3982 void radv_DestroySemaphore(
3983 VkDevice _device,
3984 VkSemaphore _semaphore,
3985 const VkAllocationCallbacks* pAllocator)
3986 {
3987 RADV_FROM_HANDLE(radv_device, device, _device);
3988 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3989 if (!_semaphore)
3990 return;
3991
3992 if (sem->syncobj)
3993 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3994 else
3995 device->ws->destroy_sem(sem->sem);
3996 vk_free2(&device->alloc, pAllocator, sem);
3997 }
3998
3999 VkResult radv_CreateEvent(
4000 VkDevice _device,
4001 const VkEventCreateInfo* pCreateInfo,
4002 const VkAllocationCallbacks* pAllocator,
4003 VkEvent* pEvent)
4004 {
4005 RADV_FROM_HANDLE(radv_device, device, _device);
4006 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4007 sizeof(*event), 8,
4008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4009
4010 if (!event)
4011 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4012
4013 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4014 RADEON_DOMAIN_GTT,
4015 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4016 RADV_BO_PRIORITY_FENCE);
4017 if (!event->bo) {
4018 vk_free2(&device->alloc, pAllocator, event);
4019 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4020 }
4021
4022 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4023
4024 *pEvent = radv_event_to_handle(event);
4025
4026 return VK_SUCCESS;
4027 }
4028
4029 void radv_DestroyEvent(
4030 VkDevice _device,
4031 VkEvent _event,
4032 const VkAllocationCallbacks* pAllocator)
4033 {
4034 RADV_FROM_HANDLE(radv_device, device, _device);
4035 RADV_FROM_HANDLE(radv_event, event, _event);
4036
4037 if (!event)
4038 return;
4039 device->ws->buffer_destroy(event->bo);
4040 vk_free2(&device->alloc, pAllocator, event);
4041 }
4042
4043 VkResult radv_GetEventStatus(
4044 VkDevice _device,
4045 VkEvent _event)
4046 {
4047 RADV_FROM_HANDLE(radv_event, event, _event);
4048
4049 if (*event->map == 1)
4050 return VK_EVENT_SET;
4051 return VK_EVENT_RESET;
4052 }
4053
4054 VkResult radv_SetEvent(
4055 VkDevice _device,
4056 VkEvent _event)
4057 {
4058 RADV_FROM_HANDLE(radv_event, event, _event);
4059 *event->map = 1;
4060
4061 return VK_SUCCESS;
4062 }
4063
4064 VkResult radv_ResetEvent(
4065 VkDevice _device,
4066 VkEvent _event)
4067 {
4068 RADV_FROM_HANDLE(radv_event, event, _event);
4069 *event->map = 0;
4070
4071 return VK_SUCCESS;
4072 }
4073
4074 VkResult radv_CreateBuffer(
4075 VkDevice _device,
4076 const VkBufferCreateInfo* pCreateInfo,
4077 const VkAllocationCallbacks* pAllocator,
4078 VkBuffer* pBuffer)
4079 {
4080 RADV_FROM_HANDLE(radv_device, device, _device);
4081 struct radv_buffer *buffer;
4082
4083 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4084
4085 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4086 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4087 if (buffer == NULL)
4088 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4089
4090 buffer->size = pCreateInfo->size;
4091 buffer->usage = pCreateInfo->usage;
4092 buffer->bo = NULL;
4093 buffer->offset = 0;
4094 buffer->flags = pCreateInfo->flags;
4095
4096 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4097 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4098
4099 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4100 buffer->bo = device->ws->buffer_create(device->ws,
4101 align64(buffer->size, 4096),
4102 4096, 0, RADEON_FLAG_VIRTUAL,
4103 RADV_BO_PRIORITY_VIRTUAL);
4104 if (!buffer->bo) {
4105 vk_free2(&device->alloc, pAllocator, buffer);
4106 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4107 }
4108 }
4109
4110 *pBuffer = radv_buffer_to_handle(buffer);
4111
4112 return VK_SUCCESS;
4113 }
4114
4115 void radv_DestroyBuffer(
4116 VkDevice _device,
4117 VkBuffer _buffer,
4118 const VkAllocationCallbacks* pAllocator)
4119 {
4120 RADV_FROM_HANDLE(radv_device, device, _device);
4121 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4122
4123 if (!buffer)
4124 return;
4125
4126 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4127 device->ws->buffer_destroy(buffer->bo);
4128
4129 vk_free2(&device->alloc, pAllocator, buffer);
4130 }
4131
4132 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4133 VkDevice device,
4134 const VkBufferDeviceAddressInfoEXT* pInfo)
4135 {
4136 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4137 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4138 }
4139
4140
4141 static inline unsigned
4142 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4143 {
4144 if (stencil)
4145 return image->surface.u.legacy.stencil_tiling_index[level];
4146 else
4147 return image->surface.u.legacy.tiling_index[level];
4148 }
4149
4150 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4151 {
4152 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4153 }
4154
4155 static uint32_t
4156 radv_init_dcc_control_reg(struct radv_device *device,
4157 struct radv_image_view *iview)
4158 {
4159 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4160 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4161 unsigned max_compressed_block_size;
4162 unsigned independent_64b_blocks;
4163
4164 if (!radv_image_has_dcc(iview->image))
4165 return 0;
4166
4167 if (iview->image->info.samples > 1) {
4168 if (iview->image->surface.bpe == 1)
4169 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4170 else if (iview->image->surface.bpe == 2)
4171 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4172 }
4173
4174 if (!device->physical_device->rad_info.has_dedicated_vram) {
4175 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4176 * dGPU and 64 for APU because all of our APUs to date use
4177 * DIMMs which have a request granularity size of 64B while all
4178 * other chips have a 32B request size.
4179 */
4180 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4181 }
4182
4183 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4184 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4185 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4186 /* If this DCC image is potentially going to be used in texture
4187 * fetches, we need some special settings.
4188 */
4189 independent_64b_blocks = 1;
4190 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4191 } else {
4192 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4193 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4194 * big as possible for better compression state.
4195 */
4196 independent_64b_blocks = 0;
4197 max_compressed_block_size = max_uncompressed_block_size;
4198 }
4199
4200 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4201 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4202 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4203 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4204 }
4205
4206 static void
4207 radv_initialise_color_surface(struct radv_device *device,
4208 struct radv_color_buffer_info *cb,
4209 struct radv_image_view *iview)
4210 {
4211 const struct vk_format_description *desc;
4212 unsigned ntype, format, swap, endian;
4213 unsigned blend_clamp = 0, blend_bypass = 0;
4214 uint64_t va;
4215 const struct radeon_surf *surf = &iview->image->surface;
4216
4217 desc = vk_format_description(iview->vk_format);
4218
4219 memset(cb, 0, sizeof(*cb));
4220
4221 /* Intensity is implemented as Red, so treat it that way. */
4222 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4223
4224 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4225
4226 cb->cb_color_base = va >> 8;
4227
4228 if (device->physical_device->rad_info.chip_class >= GFX9) {
4229 struct gfx9_surf_meta_flags meta;
4230 if (iview->image->dcc_offset)
4231 meta = iview->image->surface.u.gfx9.dcc;
4232 else
4233 meta = iview->image->surface.u.gfx9.cmask;
4234
4235 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4236 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4237 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4238 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4239
4240 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4241 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4242 } else {
4243 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4244 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4245
4246 cb->cb_color_base += level_info->offset >> 8;
4247 if (level_info->mode == RADEON_SURF_MODE_2D)
4248 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4249
4250 pitch_tile_max = level_info->nblk_x / 8 - 1;
4251 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4252 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4253
4254 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4255 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4256 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4257
4258 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4259
4260 if (radv_image_has_fmask(iview->image)) {
4261 if (device->physical_device->rad_info.chip_class >= CIK)
4262 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4263 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4264 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4265 } else {
4266 /* This must be set for fast clear to work without FMASK. */
4267 if (device->physical_device->rad_info.chip_class >= CIK)
4268 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4269 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4270 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4271 }
4272 }
4273
4274 /* CMASK variables */
4275 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4276 va += iview->image->cmask.offset;
4277 cb->cb_color_cmask = va >> 8;
4278
4279 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4280 va += iview->image->dcc_offset;
4281 cb->cb_dcc_base = va >> 8;
4282 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4283
4284 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4285 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4286 S_028C6C_SLICE_MAX(max_slice);
4287
4288 if (iview->image->info.samples > 1) {
4289 unsigned log_samples = util_logbase2(iview->image->info.samples);
4290
4291 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4292 S_028C74_NUM_FRAGMENTS(log_samples);
4293 }
4294
4295 if (radv_image_has_fmask(iview->image)) {
4296 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4297 cb->cb_color_fmask = va >> 8;
4298 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4299 } else {
4300 cb->cb_color_fmask = cb->cb_color_base;
4301 }
4302
4303 ntype = radv_translate_color_numformat(iview->vk_format,
4304 desc,
4305 vk_format_get_first_non_void_channel(iview->vk_format));
4306 format = radv_translate_colorformat(iview->vk_format);
4307 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4308 radv_finishme("Illegal color\n");
4309 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4310 endian = radv_colorformat_endian_swap(format);
4311
4312 /* blend clamp should be set for all NORM/SRGB types */
4313 if (ntype == V_028C70_NUMBER_UNORM ||
4314 ntype == V_028C70_NUMBER_SNORM ||
4315 ntype == V_028C70_NUMBER_SRGB)
4316 blend_clamp = 1;
4317
4318 /* set blend bypass according to docs if SINT/UINT or
4319 8/24 COLOR variants */
4320 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4321 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4322 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4323 blend_clamp = 0;
4324 blend_bypass = 1;
4325 }
4326 #if 0
4327 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4328 (format == V_028C70_COLOR_8 ||
4329 format == V_028C70_COLOR_8_8 ||
4330 format == V_028C70_COLOR_8_8_8_8))
4331 ->color_is_int8 = true;
4332 #endif
4333 cb->cb_color_info = S_028C70_FORMAT(format) |
4334 S_028C70_COMP_SWAP(swap) |
4335 S_028C70_BLEND_CLAMP(blend_clamp) |
4336 S_028C70_BLEND_BYPASS(blend_bypass) |
4337 S_028C70_SIMPLE_FLOAT(1) |
4338 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4339 ntype != V_028C70_NUMBER_SNORM &&
4340 ntype != V_028C70_NUMBER_SRGB &&
4341 format != V_028C70_COLOR_8_24 &&
4342 format != V_028C70_COLOR_24_8) |
4343 S_028C70_NUMBER_TYPE(ntype) |
4344 S_028C70_ENDIAN(endian);
4345 if (radv_image_has_fmask(iview->image)) {
4346 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4347 if (device->physical_device->rad_info.chip_class == SI) {
4348 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4349 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4350 }
4351 }
4352
4353 if (radv_image_has_cmask(iview->image) &&
4354 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4355 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4356
4357 if (radv_dcc_enabled(iview->image, iview->base_mip))
4358 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4359
4360 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4361
4362 /* This must be set for fast clear to work without FMASK. */
4363 if (!radv_image_has_fmask(iview->image) &&
4364 device->physical_device->rad_info.chip_class == SI) {
4365 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4366 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4367 }
4368
4369 if (device->physical_device->rad_info.chip_class >= GFX9) {
4370 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4371 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4372
4373 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4374 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4375 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4376 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4377 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4378 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4379 }
4380 }
4381
4382 static unsigned
4383 radv_calc_decompress_on_z_planes(struct radv_device *device,
4384 struct radv_image_view *iview)
4385 {
4386 unsigned max_zplanes = 0;
4387
4388 assert(radv_image_is_tc_compat_htile(iview->image));
4389
4390 if (device->physical_device->rad_info.chip_class >= GFX9) {
4391 /* Default value for 32-bit depth surfaces. */
4392 max_zplanes = 4;
4393
4394 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4395 iview->image->info.samples > 1)
4396 max_zplanes = 2;
4397
4398 max_zplanes = max_zplanes + 1;
4399 } else {
4400 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4401 /* Do not enable Z plane compression for 16-bit depth
4402 * surfaces because isn't supported on GFX8. Only
4403 * 32-bit depth surfaces are supported by the hardware.
4404 * This allows to maintain shader compatibility and to
4405 * reduce the number of depth decompressions.
4406 */
4407 max_zplanes = 1;
4408 } else {
4409 if (iview->image->info.samples <= 1)
4410 max_zplanes = 5;
4411 else if (iview->image->info.samples <= 4)
4412 max_zplanes = 3;
4413 else
4414 max_zplanes = 2;
4415 }
4416 }
4417
4418 return max_zplanes;
4419 }
4420
4421 static void
4422 radv_initialise_ds_surface(struct radv_device *device,
4423 struct radv_ds_buffer_info *ds,
4424 struct radv_image_view *iview)
4425 {
4426 unsigned level = iview->base_mip;
4427 unsigned format, stencil_format;
4428 uint64_t va, s_offs, z_offs;
4429 bool stencil_only = false;
4430 memset(ds, 0, sizeof(*ds));
4431 switch (iview->image->vk_format) {
4432 case VK_FORMAT_D24_UNORM_S8_UINT:
4433 case VK_FORMAT_X8_D24_UNORM_PACK32:
4434 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4435 ds->offset_scale = 2.0f;
4436 break;
4437 case VK_FORMAT_D16_UNORM:
4438 case VK_FORMAT_D16_UNORM_S8_UINT:
4439 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4440 ds->offset_scale = 4.0f;
4441 break;
4442 case VK_FORMAT_D32_SFLOAT:
4443 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4444 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4445 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4446 ds->offset_scale = 1.0f;
4447 break;
4448 case VK_FORMAT_S8_UINT:
4449 stencil_only = true;
4450 break;
4451 default:
4452 break;
4453 }
4454
4455 format = radv_translate_dbformat(iview->image->vk_format);
4456 stencil_format = iview->image->surface.has_stencil ?
4457 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4458
4459 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4460 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4461 S_028008_SLICE_MAX(max_slice);
4462
4463 ds->db_htile_data_base = 0;
4464 ds->db_htile_surface = 0;
4465
4466 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4467 s_offs = z_offs = va;
4468
4469 if (device->physical_device->rad_info.chip_class >= GFX9) {
4470 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4471 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4472
4473 ds->db_z_info = S_028038_FORMAT(format) |
4474 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4475 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4476 S_028038_MAXMIP(iview->image->info.levels - 1) |
4477 S_028038_ZRANGE_PRECISION(1);
4478 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4479 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4480
4481 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4482 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4483 ds->db_depth_view |= S_028008_MIPID(level);
4484
4485 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4486 S_02801C_Y_MAX(iview->image->info.height - 1);
4487
4488 if (radv_htile_enabled(iview->image, level)) {
4489 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4490
4491 if (radv_image_is_tc_compat_htile(iview->image)) {
4492 unsigned max_zplanes =
4493 radv_calc_decompress_on_z_planes(device, iview);
4494
4495 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4496 S_028038_ITERATE_FLUSH(1);
4497 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4498 }
4499
4500 if (!iview->image->surface.has_stencil)
4501 /* Use all of the htile_buffer for depth if there's no stencil. */
4502 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4503 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4504 iview->image->htile_offset;
4505 ds->db_htile_data_base = va >> 8;
4506 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4507 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4508 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4509 }
4510 } else {
4511 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4512
4513 if (stencil_only)
4514 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4515
4516 z_offs += iview->image->surface.u.legacy.level[level].offset;
4517 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4518
4519 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4520 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4521 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4522
4523 if (iview->image->info.samples > 1)
4524 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4525
4526 if (device->physical_device->rad_info.chip_class >= CIK) {
4527 struct radeon_info *info = &device->physical_device->rad_info;
4528 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4529 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4530 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4531 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4532 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4533 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4534
4535 if (stencil_only)
4536 tile_mode = stencil_tile_mode;
4537
4538 ds->db_depth_info |=
4539 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4540 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4541 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4542 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4543 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4544 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4545 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4546 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4547 } else {
4548 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4549 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4550 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4551 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4552 if (stencil_only)
4553 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4554 }
4555
4556 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4557 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4558 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4559
4560 if (radv_htile_enabled(iview->image, level)) {
4561 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4562
4563 if (!iview->image->surface.has_stencil &&
4564 !radv_image_is_tc_compat_htile(iview->image))
4565 /* Use all of the htile_buffer for depth if there's no stencil. */
4566 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4567
4568 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4569 iview->image->htile_offset;
4570 ds->db_htile_data_base = va >> 8;
4571 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4572
4573 if (radv_image_is_tc_compat_htile(iview->image)) {
4574 unsigned max_zplanes =
4575 radv_calc_decompress_on_z_planes(device, iview);
4576
4577 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4578 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4579 }
4580 }
4581 }
4582
4583 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4584 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4585 }
4586
4587 VkResult radv_CreateFramebuffer(
4588 VkDevice _device,
4589 const VkFramebufferCreateInfo* pCreateInfo,
4590 const VkAllocationCallbacks* pAllocator,
4591 VkFramebuffer* pFramebuffer)
4592 {
4593 RADV_FROM_HANDLE(radv_device, device, _device);
4594 struct radv_framebuffer *framebuffer;
4595
4596 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4597
4598 size_t size = sizeof(*framebuffer) +
4599 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4600 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4601 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4602 if (framebuffer == NULL)
4603 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4604
4605 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4606 framebuffer->width = pCreateInfo->width;
4607 framebuffer->height = pCreateInfo->height;
4608 framebuffer->layers = pCreateInfo->layers;
4609 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4610 VkImageView _iview = pCreateInfo->pAttachments[i];
4611 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4612 framebuffer->attachments[i].attachment = iview;
4613 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4614 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4615 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4616 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4617 }
4618 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4619 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4620 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4621 }
4622
4623 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4624 return VK_SUCCESS;
4625 }
4626
4627 void radv_DestroyFramebuffer(
4628 VkDevice _device,
4629 VkFramebuffer _fb,
4630 const VkAllocationCallbacks* pAllocator)
4631 {
4632 RADV_FROM_HANDLE(radv_device, device, _device);
4633 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4634
4635 if (!fb)
4636 return;
4637 vk_free2(&device->alloc, pAllocator, fb);
4638 }
4639
4640 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4641 {
4642 switch (address_mode) {
4643 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4644 return V_008F30_SQ_TEX_WRAP;
4645 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4646 return V_008F30_SQ_TEX_MIRROR;
4647 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4648 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4649 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4650 return V_008F30_SQ_TEX_CLAMP_BORDER;
4651 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4652 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4653 default:
4654 unreachable("illegal tex wrap mode");
4655 break;
4656 }
4657 }
4658
4659 static unsigned
4660 radv_tex_compare(VkCompareOp op)
4661 {
4662 switch (op) {
4663 case VK_COMPARE_OP_NEVER:
4664 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4665 case VK_COMPARE_OP_LESS:
4666 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4667 case VK_COMPARE_OP_EQUAL:
4668 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4669 case VK_COMPARE_OP_LESS_OR_EQUAL:
4670 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4671 case VK_COMPARE_OP_GREATER:
4672 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4673 case VK_COMPARE_OP_NOT_EQUAL:
4674 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4675 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4676 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4677 case VK_COMPARE_OP_ALWAYS:
4678 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4679 default:
4680 unreachable("illegal compare mode");
4681 break;
4682 }
4683 }
4684
4685 static unsigned
4686 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4687 {
4688 switch (filter) {
4689 case VK_FILTER_NEAREST:
4690 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4691 V_008F38_SQ_TEX_XY_FILTER_POINT);
4692 case VK_FILTER_LINEAR:
4693 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4694 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4695 case VK_FILTER_CUBIC_IMG:
4696 default:
4697 fprintf(stderr, "illegal texture filter");
4698 return 0;
4699 }
4700 }
4701
4702 static unsigned
4703 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4704 {
4705 switch (mode) {
4706 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4707 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4708 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4709 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4710 default:
4711 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4712 }
4713 }
4714
4715 static unsigned
4716 radv_tex_bordercolor(VkBorderColor bcolor)
4717 {
4718 switch (bcolor) {
4719 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4720 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4721 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4722 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4723 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4724 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4725 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4726 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4727 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4728 default:
4729 break;
4730 }
4731 return 0;
4732 }
4733
4734 static unsigned
4735 radv_tex_aniso_filter(unsigned filter)
4736 {
4737 if (filter < 2)
4738 return 0;
4739 if (filter < 4)
4740 return 1;
4741 if (filter < 8)
4742 return 2;
4743 if (filter < 16)
4744 return 3;
4745 return 4;
4746 }
4747
4748 static unsigned
4749 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4750 {
4751 switch (mode) {
4752 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4753 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4754 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4755 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4756 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4757 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4758 default:
4759 break;
4760 }
4761 return 0;
4762 }
4763
4764 static uint32_t
4765 radv_get_max_anisotropy(struct radv_device *device,
4766 const VkSamplerCreateInfo *pCreateInfo)
4767 {
4768 if (device->force_aniso >= 0)
4769 return device->force_aniso;
4770
4771 if (pCreateInfo->anisotropyEnable &&
4772 pCreateInfo->maxAnisotropy > 1.0f)
4773 return (uint32_t)pCreateInfo->maxAnisotropy;
4774
4775 return 0;
4776 }
4777
4778 static void
4779 radv_init_sampler(struct radv_device *device,
4780 struct radv_sampler *sampler,
4781 const VkSamplerCreateInfo *pCreateInfo)
4782 {
4783 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4784 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4785 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4786 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4787
4788 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4789 vk_find_struct_const(pCreateInfo->pNext,
4790 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4791 if (sampler_reduction)
4792 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4793
4794 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4795 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4796 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4797 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4798 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4799 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4800 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4801 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4802 S_008F30_DISABLE_CUBE_WRAP(0) |
4803 S_008F30_COMPAT_MODE(is_vi) |
4804 S_008F30_FILTER_MODE(filter_mode));
4805 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4806 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4807 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4808 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4809 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4810 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4811 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4812 S_008F38_MIP_POINT_PRECLAMP(0) |
4813 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4814 S_008F38_FILTER_PREC_FIX(1) |
4815 S_008F38_ANISO_OVERRIDE(is_vi));
4816 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4817 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4818 }
4819
4820 VkResult radv_CreateSampler(
4821 VkDevice _device,
4822 const VkSamplerCreateInfo* pCreateInfo,
4823 const VkAllocationCallbacks* pAllocator,
4824 VkSampler* pSampler)
4825 {
4826 RADV_FROM_HANDLE(radv_device, device, _device);
4827 struct radv_sampler *sampler;
4828
4829 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4830
4831 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4832 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4833 if (!sampler)
4834 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4835
4836 radv_init_sampler(device, sampler, pCreateInfo);
4837 *pSampler = radv_sampler_to_handle(sampler);
4838
4839 return VK_SUCCESS;
4840 }
4841
4842 void radv_DestroySampler(
4843 VkDevice _device,
4844 VkSampler _sampler,
4845 const VkAllocationCallbacks* pAllocator)
4846 {
4847 RADV_FROM_HANDLE(radv_device, device, _device);
4848 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4849
4850 if (!sampler)
4851 return;
4852 vk_free2(&device->alloc, pAllocator, sampler);
4853 }
4854
4855 /* vk_icd.h does not declare this function, so we declare it here to
4856 * suppress Wmissing-prototypes.
4857 */
4858 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4859 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4860
4861 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4862 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4863 {
4864 /* For the full details on loader interface versioning, see
4865 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4866 * What follows is a condensed summary, to help you navigate the large and
4867 * confusing official doc.
4868 *
4869 * - Loader interface v0 is incompatible with later versions. We don't
4870 * support it.
4871 *
4872 * - In loader interface v1:
4873 * - The first ICD entrypoint called by the loader is
4874 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4875 * entrypoint.
4876 * - The ICD must statically expose no other Vulkan symbol unless it is
4877 * linked with -Bsymbolic.
4878 * - Each dispatchable Vulkan handle created by the ICD must be
4879 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4880 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4881 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4882 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4883 * such loader-managed surfaces.
4884 *
4885 * - Loader interface v2 differs from v1 in:
4886 * - The first ICD entrypoint called by the loader is
4887 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4888 * statically expose this entrypoint.
4889 *
4890 * - Loader interface v3 differs from v2 in:
4891 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4892 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4893 * because the loader no longer does so.
4894 */
4895 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4896 return VK_SUCCESS;
4897 }
4898
4899 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4900 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4901 int *pFD)
4902 {
4903 RADV_FROM_HANDLE(radv_device, device, _device);
4904 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4905
4906 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4907
4908 /* At the moment, we support only the below handle types. */
4909 assert(pGetFdInfo->handleType ==
4910 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4911 pGetFdInfo->handleType ==
4912 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4913
4914 bool ret = radv_get_memory_fd(device, memory, pFD);
4915 if (ret == false)
4916 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4917 return VK_SUCCESS;
4918 }
4919
4920 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4921 VkExternalMemoryHandleTypeFlagBits handleType,
4922 int fd,
4923 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4924 {
4925 RADV_FROM_HANDLE(radv_device, device, _device);
4926
4927 switch (handleType) {
4928 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4929 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4930 return VK_SUCCESS;
4931
4932 default:
4933 /* The valid usage section for this function says:
4934 *
4935 * "handleType must not be one of the handle types defined as
4936 * opaque."
4937 *
4938 * So opaque handle types fall into the default "unsupported" case.
4939 */
4940 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4941 }
4942 }
4943
4944 static VkResult radv_import_opaque_fd(struct radv_device *device,
4945 int fd,
4946 uint32_t *syncobj)
4947 {
4948 uint32_t syncobj_handle = 0;
4949 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4950 if (ret != 0)
4951 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4952
4953 if (*syncobj)
4954 device->ws->destroy_syncobj(device->ws, *syncobj);
4955
4956 *syncobj = syncobj_handle;
4957 close(fd);
4958
4959 return VK_SUCCESS;
4960 }
4961
4962 static VkResult radv_import_sync_fd(struct radv_device *device,
4963 int fd,
4964 uint32_t *syncobj)
4965 {
4966 /* If we create a syncobj we do it locally so that if we have an error, we don't
4967 * leave a syncobj in an undetermined state in the fence. */
4968 uint32_t syncobj_handle = *syncobj;
4969 if (!syncobj_handle) {
4970 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4971 if (ret) {
4972 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4973 }
4974 }
4975
4976 if (fd == -1) {
4977 device->ws->signal_syncobj(device->ws, syncobj_handle);
4978 } else {
4979 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4980 if (ret != 0)
4981 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4982 }
4983
4984 *syncobj = syncobj_handle;
4985 if (fd != -1)
4986 close(fd);
4987
4988 return VK_SUCCESS;
4989 }
4990
4991 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4992 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4993 {
4994 RADV_FROM_HANDLE(radv_device, device, _device);
4995 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4996 uint32_t *syncobj_dst = NULL;
4997
4998 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4999 syncobj_dst = &sem->temp_syncobj;
5000 } else {
5001 syncobj_dst = &sem->syncobj;
5002 }
5003
5004 switch(pImportSemaphoreFdInfo->handleType) {
5005 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5006 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5007 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5008 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5009 default:
5010 unreachable("Unhandled semaphore handle type");
5011 }
5012 }
5013
5014 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5015 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5016 int *pFd)
5017 {
5018 RADV_FROM_HANDLE(radv_device, device, _device);
5019 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5020 int ret;
5021 uint32_t syncobj_handle;
5022
5023 if (sem->temp_syncobj)
5024 syncobj_handle = sem->temp_syncobj;
5025 else
5026 syncobj_handle = sem->syncobj;
5027
5028 switch(pGetFdInfo->handleType) {
5029 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5030 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5031 break;
5032 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5033 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5034 if (!ret) {
5035 if (sem->temp_syncobj) {
5036 close (sem->temp_syncobj);
5037 sem->temp_syncobj = 0;
5038 } else {
5039 device->ws->reset_syncobj(device->ws, syncobj_handle);
5040 }
5041 }
5042 break;
5043 default:
5044 unreachable("Unhandled semaphore handle type");
5045 }
5046
5047 if (ret)
5048 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5049 return VK_SUCCESS;
5050 }
5051
5052 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5053 VkPhysicalDevice physicalDevice,
5054 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5055 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5056 {
5057 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5058
5059 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5060 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5061 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5062 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5063 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5064 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5065 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5066 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5067 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5068 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5069 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5070 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5071 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5072 } else {
5073 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5074 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5075 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5076 }
5077 }
5078
5079 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5080 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5081 {
5082 RADV_FROM_HANDLE(radv_device, device, _device);
5083 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5084 uint32_t *syncobj_dst = NULL;
5085
5086
5087 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5088 syncobj_dst = &fence->temp_syncobj;
5089 } else {
5090 syncobj_dst = &fence->syncobj;
5091 }
5092
5093 switch(pImportFenceFdInfo->handleType) {
5094 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5095 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5096 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5097 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5098 default:
5099 unreachable("Unhandled fence handle type");
5100 }
5101 }
5102
5103 VkResult radv_GetFenceFdKHR(VkDevice _device,
5104 const VkFenceGetFdInfoKHR *pGetFdInfo,
5105 int *pFd)
5106 {
5107 RADV_FROM_HANDLE(radv_device, device, _device);
5108 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5109 int ret;
5110 uint32_t syncobj_handle;
5111
5112 if (fence->temp_syncobj)
5113 syncobj_handle = fence->temp_syncobj;
5114 else
5115 syncobj_handle = fence->syncobj;
5116
5117 switch(pGetFdInfo->handleType) {
5118 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5119 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5120 break;
5121 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5122 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5123 if (!ret) {
5124 if (fence->temp_syncobj) {
5125 close (fence->temp_syncobj);
5126 fence->temp_syncobj = 0;
5127 } else {
5128 device->ws->reset_syncobj(device->ws, syncobj_handle);
5129 }
5130 }
5131 break;
5132 default:
5133 unreachable("Unhandled fence handle type");
5134 }
5135
5136 if (ret)
5137 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5138 return VK_SUCCESS;
5139 }
5140
5141 void radv_GetPhysicalDeviceExternalFenceProperties(
5142 VkPhysicalDevice physicalDevice,
5143 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5144 VkExternalFenceProperties *pExternalFenceProperties)
5145 {
5146 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5147
5148 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5149 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5150 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5151 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5152 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5153 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5154 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5155 } else {
5156 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5157 pExternalFenceProperties->compatibleHandleTypes = 0;
5158 pExternalFenceProperties->externalFenceFeatures = 0;
5159 }
5160 }
5161
5162 VkResult
5163 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5164 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5165 const VkAllocationCallbacks* pAllocator,
5166 VkDebugReportCallbackEXT* pCallback)
5167 {
5168 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5169 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5170 pCreateInfo, pAllocator, &instance->alloc,
5171 pCallback);
5172 }
5173
5174 void
5175 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5176 VkDebugReportCallbackEXT _callback,
5177 const VkAllocationCallbacks* pAllocator)
5178 {
5179 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5180 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5181 _callback, pAllocator, &instance->alloc);
5182 }
5183
5184 void
5185 radv_DebugReportMessageEXT(VkInstance _instance,
5186 VkDebugReportFlagsEXT flags,
5187 VkDebugReportObjectTypeEXT objectType,
5188 uint64_t object,
5189 size_t location,
5190 int32_t messageCode,
5191 const char* pLayerPrefix,
5192 const char* pMessage)
5193 {
5194 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5195 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5196 object, location, messageCode, pLayerPrefix, pMessage);
5197 }
5198
5199 void
5200 radv_GetDeviceGroupPeerMemoryFeatures(
5201 VkDevice device,
5202 uint32_t heapIndex,
5203 uint32_t localDeviceIndex,
5204 uint32_t remoteDeviceIndex,
5205 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5206 {
5207 assert(localDeviceIndex == remoteDeviceIndex);
5208
5209 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5210 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5211 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5212 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5213 }
5214
5215 static const VkTimeDomainEXT radv_time_domains[] = {
5216 VK_TIME_DOMAIN_DEVICE_EXT,
5217 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5218 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5219 };
5220
5221 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5222 VkPhysicalDevice physicalDevice,
5223 uint32_t *pTimeDomainCount,
5224 VkTimeDomainEXT *pTimeDomains)
5225 {
5226 int d;
5227 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5228
5229 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5230 vk_outarray_append(&out, i) {
5231 *i = radv_time_domains[d];
5232 }
5233 }
5234
5235 return vk_outarray_status(&out);
5236 }
5237
5238 static uint64_t
5239 radv_clock_gettime(clockid_t clock_id)
5240 {
5241 struct timespec current;
5242 int ret;
5243
5244 ret = clock_gettime(clock_id, &current);
5245 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5246 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5247 if (ret < 0)
5248 return 0;
5249
5250 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5251 }
5252
5253 VkResult radv_GetCalibratedTimestampsEXT(
5254 VkDevice _device,
5255 uint32_t timestampCount,
5256 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5257 uint64_t *pTimestamps,
5258 uint64_t *pMaxDeviation)
5259 {
5260 RADV_FROM_HANDLE(radv_device, device, _device);
5261 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5262 int d;
5263 uint64_t begin, end;
5264 uint64_t max_clock_period = 0;
5265
5266 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5267
5268 for (d = 0; d < timestampCount; d++) {
5269 switch (pTimestampInfos[d].timeDomain) {
5270 case VK_TIME_DOMAIN_DEVICE_EXT:
5271 pTimestamps[d] = device->ws->query_value(device->ws,
5272 RADEON_TIMESTAMP);
5273 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5274 max_clock_period = MAX2(max_clock_period, device_period);
5275 break;
5276 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5277 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5278 max_clock_period = MAX2(max_clock_period, 1);
5279 break;
5280
5281 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5282 pTimestamps[d] = begin;
5283 break;
5284 default:
5285 pTimestamps[d] = 0;
5286 break;
5287 }
5288 }
5289
5290 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5291
5292 /*
5293 * The maximum deviation is the sum of the interval over which we
5294 * perform the sampling and the maximum period of any sampled
5295 * clock. That's because the maximum skew between any two sampled
5296 * clock edges is when the sampled clock with the largest period is
5297 * sampled at the end of that period but right at the beginning of the
5298 * sampling interval and some other clock is sampled right at the
5299 * begining of its sampling period and right at the end of the
5300 * sampling interval. Let's assume the GPU has the longest clock
5301 * period and that the application is sampling GPU and monotonic:
5302 *
5303 * s e
5304 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5305 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5306 *
5307 * g
5308 * 0 1 2 3
5309 * GPU -----_____-----_____-----_____-----_____
5310 *
5311 * m
5312 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5313 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5314 *
5315 * Interval <----------------->
5316 * Deviation <-------------------------->
5317 *
5318 * s = read(raw) 2
5319 * g = read(GPU) 1
5320 * m = read(monotonic) 2
5321 * e = read(raw) b
5322 *
5323 * We round the sample interval up by one tick to cover sampling error
5324 * in the interval clock
5325 */
5326
5327 uint64_t sample_interval = end - begin + 1;
5328
5329 *pMaxDeviation = sample_interval + max_clock_period;
5330
5331 return VK_SUCCESS;
5332 }