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ac: rename SI-CIK-VI to GFX6-GFX7-GFX8
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
116 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
117 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
118 default: chip_string = "AMD RADV unknown"; break;
119 }
120
121 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
122 }
123
124 static uint64_t
125 radv_get_visible_vram_size(struct radv_physical_device *device)
126 {
127 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
128 }
129
130 static uint64_t
131 radv_get_vram_size(struct radv_physical_device *device)
132 {
133 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
134 }
135
136 static void
137 radv_physical_device_init_mem_types(struct radv_physical_device *device)
138 {
139 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
140 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
141 uint64_t vram_size = radv_get_vram_size(device);
142 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
143 device->memory_properties.memoryHeapCount = 0;
144 if (vram_size > 0) {
145 vram_index = device->memory_properties.memoryHeapCount++;
146 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
147 .size = vram_size,
148 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
149 };
150 }
151 if (visible_vram_size) {
152 visible_vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
154 .size = visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (device->rad_info.gart_size > 0) {
159 gart_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
161 .size = device->rad_info.gart_size,
162 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165
166 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
167 unsigned type_count = 0;
168 if (vram_index >= 0) {
169 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
170 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
171 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
172 .heapIndex = vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
197 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
198 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
199 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
200 .heapIndex = gart_index,
201 };
202 }
203 device->memory_properties.memoryTypeCount = type_count;
204 }
205
206 static void
207 radv_handle_env_var_force_family(struct radv_physical_device *device)
208 {
209 const char *family = getenv("RADV_FORCE_FAMILY");
210 unsigned i;
211
212 if (!family)
213 return;
214
215 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
216 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
217 /* Override family and chip_class. */
218 device->rad_info.family = i;
219
220 if (i >= CHIP_VEGA10)
221 device->rad_info.chip_class = GFX9;
222 else if (i >= CHIP_TONGA)
223 device->rad_info.chip_class = GFX8;
224 else if (i >= CHIP_BONAIRE)
225 device->rad_info.chip_class = GFX7;
226 else
227 device->rad_info.chip_class = GFX6;
228
229 return;
230 }
231 }
232
233 fprintf(stderr, "radv: Unknown family: %s\n", family);
234 exit(1);
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246 int master_fd = -1;
247
248 fd = open(path, O_RDWR | O_CLOEXEC);
249 if (fd < 0) {
250 if (instance->debug_flags & RADV_DEBUG_STARTUP)
251 radv_logi("Could not open device '%s'", path);
252
253 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
254 }
255
256 version = drmGetVersion(fd);
257 if (!version) {
258 close(fd);
259
260 if (instance->debug_flags & RADV_DEBUG_STARTUP)
261 radv_logi("Could not get the kernel driver version for device '%s'", path);
262
263 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
264 "failed to get version %s: %m", path);
265 }
266
267 if (strcmp(version->name, "amdgpu")) {
268 drmFreeVersion(version);
269 close(fd);
270
271 if (instance->debug_flags & RADV_DEBUG_STARTUP)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
273
274 return VK_ERROR_INCOMPATIBLE_DRIVER;
275 }
276 drmFreeVersion(version);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Found compatible device '%s'.", path);
280
281 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
282 device->instance = instance;
283
284 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
285 instance->perftest_flags);
286 if (!device->ws) {
287 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 goto fail;
289 }
290
291 if (instance->enabled_extensions.KHR_display) {
292 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
293 if (master_fd >= 0) {
294 uint32_t accel_working = 0;
295 struct drm_amdgpu_info request = {
296 .return_pointer = (uintptr_t)&accel_working,
297 .return_size = sizeof(accel_working),
298 .query = AMDGPU_INFO_ACCEL_WORKING
299 };
300
301 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
302 close(master_fd);
303 master_fd = -1;
304 }
305 }
306 }
307
308 device->master_fd = master_fd;
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311
312 radv_handle_env_var_force_family(device);
313
314 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
315
316 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
317 device->ws->destroy(device->ws);
318 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
319 "cannot generate UUID");
320 goto fail;
321 }
322
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags =
325 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
326 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
327
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
330 */
331 char buf[VK_UUID_SIZE * 2 + 1];
332 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
333 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
334
335 if (device->rad_info.chip_class < GFX8 ||
336 device->rad_info.chip_class > GFX9)
337 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338
339 radv_get_driver_uuid(&device->driver_uuid);
340 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
341
342 if (device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.chip_class >= GFX9) {
344 device->has_rbplus = true;
345 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.family == CHIP_VEGA12 ||
347 device->rad_info.family == CHIP_RAVEN ||
348 device->rad_info.family == CHIP_RAVEN2;
349 }
350
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 * on GFX6.
353 */
354 device->has_clear_state = device->rad_info.chip_class >= GFX7;
355
356 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
357
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
360 device->rad_info.family == CHIP_RAVEN;
361
362 /* Out-of-order primitive rasterization. */
363 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
364 device->rad_info.max_se >= 2;
365 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
366 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
367
368 device->dcc_msaa_allowed =
369 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
370
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
372 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
373 (device->rad_info.chip_class >= GFX8 &&
374 device->rad_info.me_fw_feature >= 41);
375
376 radv_physical_device_init_mem_types(device);
377 radv_fill_device_extension_table(device, &device->supported_extensions);
378
379 device->bus_info = *drm_device->businfo.pci;
380
381 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
382 ac_print_gpu_info(&device->rad_info);
383
384 /* The WSI is structured as a layer on top of the driver, so this has
385 * to be the last part of initialization (at least until we get other
386 * semi-layers).
387 */
388 result = radv_init_wsi(device);
389 if (result != VK_SUCCESS) {
390 device->ws->destroy(device->ws);
391 vk_error(instance, result);
392 goto fail;
393 }
394
395 return VK_SUCCESS;
396
397 fail:
398 close(fd);
399 if (master_fd != -1)
400 close(master_fd);
401 return result;
402 }
403
404 static void
405 radv_physical_device_finish(struct radv_physical_device *device)
406 {
407 radv_finish_wsi(device);
408 device->ws->destroy(device->ws);
409 disk_cache_destroy(device->disk_cache);
410 close(device->local_fd);
411 if (device->master_fd != -1)
412 close(device->master_fd);
413 }
414
415 static void *
416 default_alloc_func(void *pUserData, size_t size, size_t align,
417 VkSystemAllocationScope allocationScope)
418 {
419 return malloc(size);
420 }
421
422 static void *
423 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
424 size_t align, VkSystemAllocationScope allocationScope)
425 {
426 return realloc(pOriginal, size);
427 }
428
429 static void
430 default_free_func(void *pUserData, void *pMemory)
431 {
432 free(pMemory);
433 }
434
435 static const VkAllocationCallbacks default_alloc = {
436 .pUserData = NULL,
437 .pfnAllocation = default_alloc_func,
438 .pfnReallocation = default_realloc_func,
439 .pfnFree = default_free_func,
440 };
441
442 static const struct debug_control radv_debug_options[] = {
443 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
444 {"nodcc", RADV_DEBUG_NO_DCC},
445 {"shaders", RADV_DEBUG_DUMP_SHADERS},
446 {"nocache", RADV_DEBUG_NO_CACHE},
447 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
448 {"nohiz", RADV_DEBUG_NO_HIZ},
449 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
450 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
451 {"allbos", RADV_DEBUG_ALL_BOS},
452 {"noibs", RADV_DEBUG_NO_IBS},
453 {"spirv", RADV_DEBUG_DUMP_SPIRV},
454 {"vmfaults", RADV_DEBUG_VM_FAULTS},
455 {"zerovram", RADV_DEBUG_ZERO_VRAM},
456 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
457 {"nosisched", RADV_DEBUG_NO_SISCHED},
458 {"preoptir", RADV_DEBUG_PREOPTIR},
459 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
460 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
461 {"info", RADV_DEBUG_INFO},
462 {"errors", RADV_DEBUG_ERRORS},
463 {"startup", RADV_DEBUG_STARTUP},
464 {"checkir", RADV_DEBUG_CHECKIR},
465 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
466 {"nobinning", RADV_DEBUG_NOBINNING},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
482 {"bolist", RADV_PERFTEST_BO_LIST},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525 static const char radv_dri_options_xml[] =
526 DRI_CONF_BEGIN
527 DRI_CONF_SECTION_QUALITY
528 DRI_CONF_ADAPTIVE_SYNC("true")
529 DRI_CONF_SECTION_END
530 DRI_CONF_END;
531
532 static void radv_init_dri_options(struct radv_instance *instance)
533 {
534 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
535 driParseConfigFiles(&instance->dri_options,
536 &instance->available_dri_options,
537 0, "radv", NULL);
538 }
539
540 VkResult radv_CreateInstance(
541 const VkInstanceCreateInfo* pCreateInfo,
542 const VkAllocationCallbacks* pAllocator,
543 VkInstance* pInstance)
544 {
545 struct radv_instance *instance;
546 VkResult result;
547
548 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
549
550 uint32_t client_version;
551 if (pCreateInfo->pApplicationInfo &&
552 pCreateInfo->pApplicationInfo->apiVersion != 0) {
553 client_version = pCreateInfo->pApplicationInfo->apiVersion;
554 } else {
555 client_version = VK_API_VERSION_1_0;
556 }
557
558 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
559 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
560 if (!instance)
561 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
562
563 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
564
565 if (pAllocator)
566 instance->alloc = *pAllocator;
567 else
568 instance->alloc = default_alloc;
569
570 instance->apiVersion = client_version;
571 instance->physicalDeviceCount = -1;
572
573 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
574 radv_debug_options);
575
576 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
577 radv_perftest_options);
578
579
580 if (instance->debug_flags & RADV_DEBUG_STARTUP)
581 radv_logi("Created an instance");
582
583 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
584 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
585 int index = radv_get_instance_extension_index(ext_name);
586
587 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
588 vk_free2(&default_alloc, pAllocator, instance);
589 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
590 }
591
592 instance->enabled_extensions.extensions[index] = true;
593 }
594
595 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
596 if (result != VK_SUCCESS) {
597 vk_free2(&default_alloc, pAllocator, instance);
598 return vk_error(instance, result);
599 }
600
601 _mesa_locale_init();
602 glsl_type_singleton_init_or_ref();
603
604 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
605
606 radv_init_dri_options(instance);
607 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
608
609 *pInstance = radv_instance_to_handle(instance);
610
611 return VK_SUCCESS;
612 }
613
614 void radv_DestroyInstance(
615 VkInstance _instance,
616 const VkAllocationCallbacks* pAllocator)
617 {
618 RADV_FROM_HANDLE(radv_instance, instance, _instance);
619
620 if (!instance)
621 return;
622
623 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
624 radv_physical_device_finish(instance->physicalDevices + i);
625 }
626
627 VG(VALGRIND_DESTROY_MEMPOOL(instance));
628
629 glsl_type_singleton_decref();
630 _mesa_locale_fini();
631
632 driDestroyOptionCache(&instance->dri_options);
633 driDestroyOptionInfo(&instance->available_dri_options);
634
635 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
636
637 vk_free(&instance->alloc, instance);
638 }
639
640 static VkResult
641 radv_enumerate_devices(struct radv_instance *instance)
642 {
643 /* TODO: Check for more devices ? */
644 drmDevicePtr devices[8];
645 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
646 int max_devices;
647
648 instance->physicalDeviceCount = 0;
649
650 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
651
652 if (instance->debug_flags & RADV_DEBUG_STARTUP)
653 radv_logi("Found %d drm nodes", max_devices);
654
655 if (max_devices < 1)
656 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
657
658 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
659 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
660 devices[i]->bustype == DRM_BUS_PCI &&
661 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
662
663 result = radv_physical_device_init(instance->physicalDevices +
664 instance->physicalDeviceCount,
665 instance,
666 devices[i]);
667 if (result == VK_SUCCESS)
668 ++instance->physicalDeviceCount;
669 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 break;
671 }
672 }
673 drmFreeDevices(devices, max_devices);
674
675 return result;
676 }
677
678 VkResult radv_EnumeratePhysicalDevices(
679 VkInstance _instance,
680 uint32_t* pPhysicalDeviceCount,
681 VkPhysicalDevice* pPhysicalDevices)
682 {
683 RADV_FROM_HANDLE(radv_instance, instance, _instance);
684 VkResult result;
685
686 if (instance->physicalDeviceCount < 0) {
687 result = radv_enumerate_devices(instance);
688 if (result != VK_SUCCESS &&
689 result != VK_ERROR_INCOMPATIBLE_DRIVER)
690 return result;
691 }
692
693 if (!pPhysicalDevices) {
694 *pPhysicalDeviceCount = instance->physicalDeviceCount;
695 } else {
696 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
697 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
698 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
699 }
700
701 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
702 : VK_SUCCESS;
703 }
704
705 VkResult radv_EnumeratePhysicalDeviceGroups(
706 VkInstance _instance,
707 uint32_t* pPhysicalDeviceGroupCount,
708 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
709 {
710 RADV_FROM_HANDLE(radv_instance, instance, _instance);
711 VkResult result;
712
713 if (instance->physicalDeviceCount < 0) {
714 result = radv_enumerate_devices(instance);
715 if (result != VK_SUCCESS &&
716 result != VK_ERROR_INCOMPATIBLE_DRIVER)
717 return result;
718 }
719
720 if (!pPhysicalDeviceGroupProperties) {
721 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
722 } else {
723 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
724 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
725 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
726 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
727 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
728 }
729 }
730 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
731 : VK_SUCCESS;
732 }
733
734 void radv_GetPhysicalDeviceFeatures(
735 VkPhysicalDevice physicalDevice,
736 VkPhysicalDeviceFeatures* pFeatures)
737 {
738 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
739 memset(pFeatures, 0, sizeof(*pFeatures));
740
741 *pFeatures = (VkPhysicalDeviceFeatures) {
742 .robustBufferAccess = true,
743 .fullDrawIndexUint32 = true,
744 .imageCubeArray = true,
745 .independentBlend = true,
746 .geometryShader = true,
747 .tessellationShader = true,
748 .sampleRateShading = true,
749 .dualSrcBlend = true,
750 .logicOp = true,
751 .multiDrawIndirect = true,
752 .drawIndirectFirstInstance = true,
753 .depthClamp = true,
754 .depthBiasClamp = true,
755 .fillModeNonSolid = true,
756 .depthBounds = true,
757 .wideLines = true,
758 .largePoints = true,
759 .alphaToOne = true,
760 .multiViewport = true,
761 .samplerAnisotropy = true,
762 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
763 .textureCompressionASTC_LDR = false,
764 .textureCompressionBC = true,
765 .occlusionQueryPrecise = true,
766 .pipelineStatisticsQuery = true,
767 .vertexPipelineStoresAndAtomics = true,
768 .fragmentStoresAndAtomics = true,
769 .shaderTessellationAndGeometryPointSize = true,
770 .shaderImageGatherExtended = true,
771 .shaderStorageImageExtendedFormats = true,
772 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
773 .shaderUniformBufferArrayDynamicIndexing = true,
774 .shaderSampledImageArrayDynamicIndexing = true,
775 .shaderStorageBufferArrayDynamicIndexing = true,
776 .shaderStorageImageArrayDynamicIndexing = true,
777 .shaderStorageImageReadWithoutFormat = true,
778 .shaderStorageImageWriteWithoutFormat = true,
779 .shaderClipDistance = true,
780 .shaderCullDistance = true,
781 .shaderFloat64 = true,
782 .shaderInt64 = true,
783 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
784 .sparseBinding = true,
785 .variableMultisampleRate = true,
786 .inheritedQueries = true,
787 };
788 }
789
790 void radv_GetPhysicalDeviceFeatures2(
791 VkPhysicalDevice physicalDevice,
792 VkPhysicalDeviceFeatures2 *pFeatures)
793 {
794 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
795 vk_foreach_struct(ext, pFeatures->pNext) {
796 switch (ext->sType) {
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
798 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
799 features->variablePointersStorageBuffer = true;
800 features->variablePointers = true;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
804 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
805 features->multiview = true;
806 features->multiviewGeometryShader = true;
807 features->multiviewTessellationShader = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
811 VkPhysicalDeviceShaderDrawParametersFeatures *features =
812 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
813 features->shaderDrawParameters = true;
814 break;
815 }
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
817 VkPhysicalDeviceProtectedMemoryFeatures *features =
818 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
819 features->protectedMemory = false;
820 break;
821 }
822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
823 VkPhysicalDevice16BitStorageFeatures *features =
824 (VkPhysicalDevice16BitStorageFeatures*)ext;
825 bool enabled = pdevice->rad_info.chip_class >= GFX8;
826 features->storageBuffer16BitAccess = enabled;
827 features->uniformAndStorageBuffer16BitAccess = enabled;
828 features->storagePushConstant16 = enabled;
829 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
830 break;
831 }
832 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
833 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
834 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
835 features->samplerYcbcrConversion = true;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
839 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
840 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
841 features->shaderInputAttachmentArrayDynamicIndexing = true;
842 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
843 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
844 features->shaderUniformBufferArrayNonUniformIndexing = true;
845 features->shaderSampledImageArrayNonUniformIndexing = true;
846 features->shaderStorageBufferArrayNonUniformIndexing = true;
847 features->shaderStorageImageArrayNonUniformIndexing = true;
848 features->shaderInputAttachmentArrayNonUniformIndexing = true;
849 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
850 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
851 features->descriptorBindingUniformBufferUpdateAfterBind = true;
852 features->descriptorBindingSampledImageUpdateAfterBind = true;
853 features->descriptorBindingStorageImageUpdateAfterBind = true;
854 features->descriptorBindingStorageBufferUpdateAfterBind = true;
855 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
856 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
857 features->descriptorBindingUpdateUnusedWhilePending = true;
858 features->descriptorBindingPartiallyBound = true;
859 features->descriptorBindingVariableDescriptorCount = true;
860 features->runtimeDescriptorArray = true;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
864 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
865 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
866 features->conditionalRendering = true;
867 features->inheritedConditionalRendering = false;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
871 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
872 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
873 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
874 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
878 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
879 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
880 features->transformFeedback = true;
881 features->geometryStreams = true;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
885 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
886 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
887 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
891 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
892 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
893 features->memoryPriority = VK_TRUE;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
897 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
898 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
899 features->bufferDeviceAddress = true;
900 features->bufferDeviceAddressCaptureReplay = false;
901 features->bufferDeviceAddressMultiDevice = false;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
905 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
906 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
907 features->depthClipEnable = true;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
911 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
912 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
913 features->hostQueryReset = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
917 VkPhysicalDevice8BitStorageFeaturesKHR *features =
918 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
919 bool enabled = pdevice->rad_info.chip_class >= GFX8;
920 features->storageBuffer8BitAccess = enabled;
921 features->uniformAndStorageBuffer8BitAccess = enabled;
922 features->storagePushConstant8 = enabled;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
926 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
927 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
928 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
929 features->shaderInt8 = true;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
933 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
934 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
935 /* TODO: Enable this once the driver supports 64-bit
936 * compare&swap atomic operations.
937 */
938 features->shaderBufferInt64Atomics = false;
939 features->shaderSharedInt64Atomics = false;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
943 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
944 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
945
946 features->inlineUniformBlock = true;
947 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
948 break;
949 }
950 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
951 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
952 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
953 features->computeDerivativeGroupQuads = false;
954 features->computeDerivativeGroupLinear = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
958 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
959 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
960 features->ycbcrImageArrays = true;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
964 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
965 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
966 features->uniformBufferStandardLayout = true;
967 break;
968 }
969 default:
970 break;
971 }
972 }
973 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
974 }
975
976 void radv_GetPhysicalDeviceProperties(
977 VkPhysicalDevice physicalDevice,
978 VkPhysicalDeviceProperties* pProperties)
979 {
980 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
981 VkSampleCountFlags sample_counts = 0xf;
982
983 /* make sure that the entire descriptor set is addressable with a signed
984 * 32-bit int. So the sum of all limits scaled by descriptor size has to
985 * be at most 2 GiB. the combined image & samples object count as one of
986 * both. This limit is for the pipeline layout, not for the set layout, but
987 * there is no set limit, so we just set a pipeline limit. I don't think
988 * any app is going to hit this soon. */
989 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
990 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
991 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
992 32 /* sampler, largest when combined with image */ +
993 64 /* sampled image */ +
994 64 /* storage image */);
995
996 VkPhysicalDeviceLimits limits = {
997 .maxImageDimension1D = (1 << 14),
998 .maxImageDimension2D = (1 << 14),
999 .maxImageDimension3D = (1 << 11),
1000 .maxImageDimensionCube = (1 << 14),
1001 .maxImageArrayLayers = (1 << 11),
1002 .maxTexelBufferElements = 128 * 1024 * 1024,
1003 .maxUniformBufferRange = UINT32_MAX,
1004 .maxStorageBufferRange = UINT32_MAX,
1005 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1006 .maxMemoryAllocationCount = UINT32_MAX,
1007 .maxSamplerAllocationCount = 64 * 1024,
1008 .bufferImageGranularity = 64, /* A cache line */
1009 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1010 .maxBoundDescriptorSets = MAX_SETS,
1011 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1012 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1013 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1014 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1015 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1016 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1017 .maxPerStageResources = max_descriptor_set_size,
1018 .maxDescriptorSetSamplers = max_descriptor_set_size,
1019 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1020 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1021 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1022 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1023 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1024 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1025 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1026 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1027 .maxVertexInputBindings = MAX_VBS,
1028 .maxVertexInputAttributeOffset = 2047,
1029 .maxVertexInputBindingStride = 2048,
1030 .maxVertexOutputComponents = 128,
1031 .maxTessellationGenerationLevel = 64,
1032 .maxTessellationPatchSize = 32,
1033 .maxTessellationControlPerVertexInputComponents = 128,
1034 .maxTessellationControlPerVertexOutputComponents = 128,
1035 .maxTessellationControlPerPatchOutputComponents = 120,
1036 .maxTessellationControlTotalOutputComponents = 4096,
1037 .maxTessellationEvaluationInputComponents = 128,
1038 .maxTessellationEvaluationOutputComponents = 128,
1039 .maxGeometryShaderInvocations = 127,
1040 .maxGeometryInputComponents = 64,
1041 .maxGeometryOutputComponents = 128,
1042 .maxGeometryOutputVertices = 256,
1043 .maxGeometryTotalOutputComponents = 1024,
1044 .maxFragmentInputComponents = 128,
1045 .maxFragmentOutputAttachments = 8,
1046 .maxFragmentDualSrcAttachments = 1,
1047 .maxFragmentCombinedOutputResources = 8,
1048 .maxComputeSharedMemorySize = 32768,
1049 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1050 .maxComputeWorkGroupInvocations = 2048,
1051 .maxComputeWorkGroupSize = {
1052 2048,
1053 2048,
1054 2048
1055 },
1056 .subPixelPrecisionBits = 8,
1057 .subTexelPrecisionBits = 8,
1058 .mipmapPrecisionBits = 8,
1059 .maxDrawIndexedIndexValue = UINT32_MAX,
1060 .maxDrawIndirectCount = UINT32_MAX,
1061 .maxSamplerLodBias = 16,
1062 .maxSamplerAnisotropy = 16,
1063 .maxViewports = MAX_VIEWPORTS,
1064 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1065 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1066 .viewportSubPixelBits = 8,
1067 .minMemoryMapAlignment = 4096, /* A page */
1068 .minTexelBufferOffsetAlignment = 1,
1069 .minUniformBufferOffsetAlignment = 4,
1070 .minStorageBufferOffsetAlignment = 4,
1071 .minTexelOffset = -32,
1072 .maxTexelOffset = 31,
1073 .minTexelGatherOffset = -32,
1074 .maxTexelGatherOffset = 31,
1075 .minInterpolationOffset = -2,
1076 .maxInterpolationOffset = 2,
1077 .subPixelInterpolationOffsetBits = 8,
1078 .maxFramebufferWidth = (1 << 14),
1079 .maxFramebufferHeight = (1 << 14),
1080 .maxFramebufferLayers = (1 << 10),
1081 .framebufferColorSampleCounts = sample_counts,
1082 .framebufferDepthSampleCounts = sample_counts,
1083 .framebufferStencilSampleCounts = sample_counts,
1084 .framebufferNoAttachmentsSampleCounts = sample_counts,
1085 .maxColorAttachments = MAX_RTS,
1086 .sampledImageColorSampleCounts = sample_counts,
1087 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1088 .sampledImageDepthSampleCounts = sample_counts,
1089 .sampledImageStencilSampleCounts = sample_counts,
1090 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1091 .maxSampleMaskWords = 1,
1092 .timestampComputeAndGraphics = true,
1093 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1094 .maxClipDistances = 8,
1095 .maxCullDistances = 8,
1096 .maxCombinedClipAndCullDistances = 8,
1097 .discreteQueuePriorities = 2,
1098 .pointSizeRange = { 0.0, 8192.0 },
1099 .lineWidthRange = { 0.0, 7.9921875 },
1100 .pointSizeGranularity = (1.0 / 8.0),
1101 .lineWidthGranularity = (1.0 / 128.0),
1102 .strictLines = false, /* FINISHME */
1103 .standardSampleLocations = true,
1104 .optimalBufferCopyOffsetAlignment = 128,
1105 .optimalBufferCopyRowPitchAlignment = 128,
1106 .nonCoherentAtomSize = 64,
1107 };
1108
1109 *pProperties = (VkPhysicalDeviceProperties) {
1110 .apiVersion = radv_physical_device_api_version(pdevice),
1111 .driverVersion = vk_get_driver_version(),
1112 .vendorID = ATI_VENDOR_ID,
1113 .deviceID = pdevice->rad_info.pci_id,
1114 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1115 .limits = limits,
1116 .sparseProperties = {0},
1117 };
1118
1119 strcpy(pProperties->deviceName, pdevice->name);
1120 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1121 }
1122
1123 void radv_GetPhysicalDeviceProperties2(
1124 VkPhysicalDevice physicalDevice,
1125 VkPhysicalDeviceProperties2 *pProperties)
1126 {
1127 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1128 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1129
1130 vk_foreach_struct(ext, pProperties->pNext) {
1131 switch (ext->sType) {
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1133 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1134 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1135 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1139 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1140 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1141 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1142 properties->deviceLUIDValid = false;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1146 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1147 properties->maxMultiviewViewCount = MAX_VIEWS;
1148 properties->maxMultiviewInstanceIndex = INT_MAX;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1152 VkPhysicalDevicePointClippingProperties *properties =
1153 (VkPhysicalDevicePointClippingProperties*)ext;
1154 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1158 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1159 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1160 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1164 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1165 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1166 properties->minImportedHostPointerAlignment = 4096;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1170 VkPhysicalDeviceSubgroupProperties *properties =
1171 (VkPhysicalDeviceSubgroupProperties*)ext;
1172 properties->subgroupSize = 64;
1173 properties->supportedStages = VK_SHADER_STAGE_ALL;
1174 properties->supportedOperations =
1175 VK_SUBGROUP_FEATURE_BASIC_BIT |
1176 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1177 VK_SUBGROUP_FEATURE_QUAD_BIT |
1178 VK_SUBGROUP_FEATURE_VOTE_BIT;
1179 if (pdevice->rad_info.chip_class >= GFX8) {
1180 properties->supportedOperations |=
1181 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1182 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1183 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1184 }
1185 properties->quadOperationsInAllStages = true;
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1189 VkPhysicalDeviceMaintenance3Properties *properties =
1190 (VkPhysicalDeviceMaintenance3Properties*)ext;
1191 /* Make sure everything is addressable by a signed 32-bit int, and
1192 * our largest descriptors are 96 bytes. */
1193 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1194 /* Our buffer size fields allow only this much */
1195 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1199 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1200 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1201 /* GFX6-8 only support single channel min/max filter. */
1202 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1203 properties->filterMinmaxSingleComponentFormats = true;
1204 break;
1205 }
1206 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1207 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1208 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1209
1210 /* Shader engines. */
1211 properties->shaderEngineCount =
1212 pdevice->rad_info.max_se;
1213 properties->shaderArraysPerEngineCount =
1214 pdevice->rad_info.max_sh_per_se;
1215 properties->computeUnitsPerShaderArray =
1216 pdevice->rad_info.num_good_cu_per_sh;
1217 properties->simdPerComputeUnit = 4;
1218 properties->wavefrontsPerSimd =
1219 pdevice->rad_info.family == CHIP_TONGA ||
1220 pdevice->rad_info.family == CHIP_ICELAND ||
1221 pdevice->rad_info.family == CHIP_POLARIS10 ||
1222 pdevice->rad_info.family == CHIP_POLARIS11 ||
1223 pdevice->rad_info.family == CHIP_POLARIS12 ||
1224 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1225 properties->wavefrontSize = 64;
1226
1227 /* SGPR. */
1228 properties->sgprsPerSimd =
1229 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1230 properties->minSgprAllocation =
1231 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1232 properties->maxSgprAllocation =
1233 pdevice->rad_info.family == CHIP_TONGA ||
1234 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1235 properties->sgprAllocationGranularity =
1236 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1237
1238 /* VGPR. */
1239 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1240 properties->minVgprAllocation = 4;
1241 properties->maxVgprAllocation = 256;
1242 properties->vgprAllocationGranularity = 4;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1246 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1247 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1248 properties->maxVertexAttribDivisor = UINT32_MAX;
1249 break;
1250 }
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1252 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1253 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1254 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1255 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1256 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1257 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1258 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1259 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1260 properties->robustBufferAccessUpdateAfterBind = false;
1261 properties->quadDivergentImplicitLod = false;
1262
1263 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1264 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1265 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1266 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1267 32 /* sampler, largest when combined with image */ +
1268 64 /* sampled image */ +
1269 64 /* storage image */);
1270 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1271 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1272 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1273 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1274 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1275 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1276 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1277 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1278 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1279 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1280 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1281 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1282 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1283 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1284 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1288 VkPhysicalDeviceProtectedMemoryProperties *properties =
1289 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1290 properties->protectedNoFault = false;
1291 break;
1292 }
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1294 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1295 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1296 properties->primitiveOverestimationSize = 0;
1297 properties->maxExtraPrimitiveOverestimationSize = 0;
1298 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1299 properties->primitiveUnderestimation = VK_FALSE;
1300 properties->conservativePointAndLineRasterization = VK_FALSE;
1301 properties->degenerateTrianglesRasterized = VK_FALSE;
1302 properties->degenerateLinesRasterized = VK_FALSE;
1303 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1304 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1308 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1309 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1310 properties->pciDomain = pdevice->bus_info.domain;
1311 properties->pciBus = pdevice->bus_info.bus;
1312 properties->pciDevice = pdevice->bus_info.dev;
1313 properties->pciFunction = pdevice->bus_info.func;
1314 break;
1315 }
1316 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1317 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1318 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1319
1320 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1321 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1322 strcpy(driver_props->driverName, "radv");
1323
1324 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1325 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1326 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1327 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1328
1329 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1330 .major = 1,
1331 .minor = 1,
1332 .subminor = 2,
1333 .patch = 0,
1334 };
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1338 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1339 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1340 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1341 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1342 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1343 properties->maxTransformFeedbackStreamDataSize = 512;
1344 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1345 properties->maxTransformFeedbackBufferDataStride = 512;
1346 properties->transformFeedbackQueries = true;
1347 properties->transformFeedbackStreamsLinesTriangles = false;
1348 properties->transformFeedbackRasterizationStreamSelect = false;
1349 properties->transformFeedbackDraw = true;
1350 break;
1351 }
1352 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1353 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1354 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1355
1356 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1357 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1358 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1359 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1360 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1361 break;
1362 }
1363 default:
1364 break;
1365 }
1366 }
1367 }
1368
1369 static void radv_get_physical_device_queue_family_properties(
1370 struct radv_physical_device* pdevice,
1371 uint32_t* pCount,
1372 VkQueueFamilyProperties** pQueueFamilyProperties)
1373 {
1374 int num_queue_families = 1;
1375 int idx;
1376 if (pdevice->rad_info.num_compute_rings > 0 &&
1377 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1378 num_queue_families++;
1379
1380 if (pQueueFamilyProperties == NULL) {
1381 *pCount = num_queue_families;
1382 return;
1383 }
1384
1385 if (!*pCount)
1386 return;
1387
1388 idx = 0;
1389 if (*pCount >= 1) {
1390 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1391 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1392 VK_QUEUE_COMPUTE_BIT |
1393 VK_QUEUE_TRANSFER_BIT |
1394 VK_QUEUE_SPARSE_BINDING_BIT,
1395 .queueCount = 1,
1396 .timestampValidBits = 64,
1397 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1398 };
1399 idx++;
1400 }
1401
1402 if (pdevice->rad_info.num_compute_rings > 0 &&
1403 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1404 if (*pCount > idx) {
1405 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1406 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1407 VK_QUEUE_TRANSFER_BIT |
1408 VK_QUEUE_SPARSE_BINDING_BIT,
1409 .queueCount = pdevice->rad_info.num_compute_rings,
1410 .timestampValidBits = 64,
1411 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1412 };
1413 idx++;
1414 }
1415 }
1416 *pCount = idx;
1417 }
1418
1419 void radv_GetPhysicalDeviceQueueFamilyProperties(
1420 VkPhysicalDevice physicalDevice,
1421 uint32_t* pCount,
1422 VkQueueFamilyProperties* pQueueFamilyProperties)
1423 {
1424 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1425 if (!pQueueFamilyProperties) {
1426 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1427 return;
1428 }
1429 VkQueueFamilyProperties *properties[] = {
1430 pQueueFamilyProperties + 0,
1431 pQueueFamilyProperties + 1,
1432 pQueueFamilyProperties + 2,
1433 };
1434 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1435 assert(*pCount <= 3);
1436 }
1437
1438 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1439 VkPhysicalDevice physicalDevice,
1440 uint32_t* pCount,
1441 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1442 {
1443 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1444 if (!pQueueFamilyProperties) {
1445 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1446 return;
1447 }
1448 VkQueueFamilyProperties *properties[] = {
1449 &pQueueFamilyProperties[0].queueFamilyProperties,
1450 &pQueueFamilyProperties[1].queueFamilyProperties,
1451 &pQueueFamilyProperties[2].queueFamilyProperties,
1452 };
1453 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1454 assert(*pCount <= 3);
1455 }
1456
1457 void radv_GetPhysicalDeviceMemoryProperties(
1458 VkPhysicalDevice physicalDevice,
1459 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1460 {
1461 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1462
1463 *pMemoryProperties = physical_device->memory_properties;
1464 }
1465
1466 static void
1467 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1468 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1469 {
1470 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1471 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1472 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1473 uint64_t vram_size = radv_get_vram_size(device);
1474 uint64_t gtt_size = device->rad_info.gart_size;
1475 uint64_t heap_budget, heap_usage;
1476
1477 /* For all memory heaps, the computation of budget is as follow:
1478 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1479 *
1480 * The Vulkan spec 1.1.97 says that the budget should include any
1481 * currently allocated device memory.
1482 *
1483 * Note that the application heap usages are not really accurate (eg.
1484 * in presence of shared buffers).
1485 */
1486 if (vram_size) {
1487 heap_usage = device->ws->query_value(device->ws,
1488 RADEON_ALLOCATED_VRAM);
1489
1490 heap_budget = vram_size -
1491 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1492 heap_usage;
1493
1494 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1495 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1496 }
1497
1498 if (visible_vram_size) {
1499 heap_usage = device->ws->query_value(device->ws,
1500 RADEON_ALLOCATED_VRAM_VIS);
1501
1502 heap_budget = visible_vram_size -
1503 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1504 heap_usage;
1505
1506 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1507 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1508 }
1509
1510 if (gtt_size) {
1511 heap_usage = device->ws->query_value(device->ws,
1512 RADEON_ALLOCATED_GTT);
1513
1514 heap_budget = gtt_size -
1515 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1516 heap_usage;
1517
1518 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1519 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1520 }
1521
1522 /* The heapBudget and heapUsage values must be zero for array elements
1523 * greater than or equal to
1524 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1525 */
1526 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1527 memoryBudget->heapBudget[i] = 0;
1528 memoryBudget->heapUsage[i] = 0;
1529 }
1530 }
1531
1532 void radv_GetPhysicalDeviceMemoryProperties2(
1533 VkPhysicalDevice physicalDevice,
1534 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1535 {
1536 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1537 &pMemoryProperties->memoryProperties);
1538
1539 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1540 vk_find_struct(pMemoryProperties->pNext,
1541 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1542 if (memory_budget)
1543 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1544 }
1545
1546 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1547 VkDevice _device,
1548 VkExternalMemoryHandleTypeFlagBits handleType,
1549 const void *pHostPointer,
1550 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1551 {
1552 RADV_FROM_HANDLE(radv_device, device, _device);
1553
1554 switch (handleType)
1555 {
1556 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1557 const struct radv_physical_device *physical_device = device->physical_device;
1558 uint32_t memoryTypeBits = 0;
1559 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1560 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1561 memoryTypeBits = (1 << i);
1562 break;
1563 }
1564 }
1565 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1566 return VK_SUCCESS;
1567 }
1568 default:
1569 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1570 }
1571 }
1572
1573 static enum radeon_ctx_priority
1574 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1575 {
1576 /* Default to MEDIUM when a specific global priority isn't requested */
1577 if (!pObj)
1578 return RADEON_CTX_PRIORITY_MEDIUM;
1579
1580 switch(pObj->globalPriority) {
1581 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1582 return RADEON_CTX_PRIORITY_REALTIME;
1583 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1584 return RADEON_CTX_PRIORITY_HIGH;
1585 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1586 return RADEON_CTX_PRIORITY_MEDIUM;
1587 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1588 return RADEON_CTX_PRIORITY_LOW;
1589 default:
1590 unreachable("Illegal global priority value");
1591 return RADEON_CTX_PRIORITY_INVALID;
1592 }
1593 }
1594
1595 static int
1596 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1597 uint32_t queue_family_index, int idx,
1598 VkDeviceQueueCreateFlags flags,
1599 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1600 {
1601 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1602 queue->device = device;
1603 queue->queue_family_index = queue_family_index;
1604 queue->queue_idx = idx;
1605 queue->priority = radv_get_queue_global_priority(global_priority);
1606 queue->flags = flags;
1607
1608 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1609 if (!queue->hw_ctx)
1610 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1611
1612 return VK_SUCCESS;
1613 }
1614
1615 static void
1616 radv_queue_finish(struct radv_queue *queue)
1617 {
1618 if (queue->hw_ctx)
1619 queue->device->ws->ctx_destroy(queue->hw_ctx);
1620
1621 if (queue->initial_full_flush_preamble_cs)
1622 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1623 if (queue->initial_preamble_cs)
1624 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1625 if (queue->continue_preamble_cs)
1626 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1627 if (queue->descriptor_bo)
1628 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1629 if (queue->scratch_bo)
1630 queue->device->ws->buffer_destroy(queue->scratch_bo);
1631 if (queue->esgs_ring_bo)
1632 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1633 if (queue->gsvs_ring_bo)
1634 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1635 if (queue->tess_rings_bo)
1636 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1637 if (queue->compute_scratch_bo)
1638 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1639 }
1640
1641 static void
1642 radv_bo_list_init(struct radv_bo_list *bo_list)
1643 {
1644 pthread_mutex_init(&bo_list->mutex, NULL);
1645 bo_list->list.count = bo_list->capacity = 0;
1646 bo_list->list.bos = NULL;
1647 }
1648
1649 static void
1650 radv_bo_list_finish(struct radv_bo_list *bo_list)
1651 {
1652 free(bo_list->list.bos);
1653 pthread_mutex_destroy(&bo_list->mutex);
1654 }
1655
1656 static VkResult radv_bo_list_add(struct radv_device *device,
1657 struct radeon_winsys_bo *bo)
1658 {
1659 struct radv_bo_list *bo_list = &device->bo_list;
1660
1661 if (bo->is_local)
1662 return VK_SUCCESS;
1663
1664 if (unlikely(!device->use_global_bo_list))
1665 return VK_SUCCESS;
1666
1667 pthread_mutex_lock(&bo_list->mutex);
1668 if (bo_list->list.count == bo_list->capacity) {
1669 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1670 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1671
1672 if (!data) {
1673 pthread_mutex_unlock(&bo_list->mutex);
1674 return VK_ERROR_OUT_OF_HOST_MEMORY;
1675 }
1676
1677 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1678 bo_list->capacity = capacity;
1679 }
1680
1681 bo_list->list.bos[bo_list->list.count++] = bo;
1682 pthread_mutex_unlock(&bo_list->mutex);
1683 return VK_SUCCESS;
1684 }
1685
1686 static void radv_bo_list_remove(struct radv_device *device,
1687 struct radeon_winsys_bo *bo)
1688 {
1689 struct radv_bo_list *bo_list = &device->bo_list;
1690
1691 if (bo->is_local)
1692 return;
1693
1694 if (unlikely(!device->use_global_bo_list))
1695 return;
1696
1697 pthread_mutex_lock(&bo_list->mutex);
1698 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1699 if (bo_list->list.bos[i] == bo) {
1700 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1701 --bo_list->list.count;
1702 break;
1703 }
1704 }
1705 pthread_mutex_unlock(&bo_list->mutex);
1706 }
1707
1708 static void
1709 radv_device_init_gs_info(struct radv_device *device)
1710 {
1711 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1712 device->physical_device->rad_info.family);
1713 }
1714
1715 static int radv_get_device_extension_index(const char *name)
1716 {
1717 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1718 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1719 return i;
1720 }
1721 return -1;
1722 }
1723
1724 static int
1725 radv_get_int_debug_option(const char *name, int default_value)
1726 {
1727 const char *str;
1728 int result;
1729
1730 str = getenv(name);
1731 if (!str) {
1732 result = default_value;
1733 } else {
1734 char *endptr;
1735
1736 result = strtol(str, &endptr, 0);
1737 if (str == endptr) {
1738 /* No digits founs. */
1739 result = default_value;
1740 }
1741 }
1742
1743 return result;
1744 }
1745
1746 VkResult radv_CreateDevice(
1747 VkPhysicalDevice physicalDevice,
1748 const VkDeviceCreateInfo* pCreateInfo,
1749 const VkAllocationCallbacks* pAllocator,
1750 VkDevice* pDevice)
1751 {
1752 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1753 VkResult result;
1754 struct radv_device *device;
1755
1756 bool keep_shader_info = false;
1757
1758 /* Check enabled features */
1759 if (pCreateInfo->pEnabledFeatures) {
1760 VkPhysicalDeviceFeatures supported_features;
1761 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1762 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1763 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1764 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1765 for (uint32_t i = 0; i < num_features; i++) {
1766 if (enabled_feature[i] && !supported_feature[i])
1767 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1768 }
1769 }
1770
1771 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1772 sizeof(*device), 8,
1773 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1774 if (!device)
1775 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1776
1777 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1778 device->instance = physical_device->instance;
1779 device->physical_device = physical_device;
1780
1781 device->ws = physical_device->ws;
1782 if (pAllocator)
1783 device->alloc = *pAllocator;
1784 else
1785 device->alloc = physical_device->instance->alloc;
1786
1787 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1788 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1789 int index = radv_get_device_extension_index(ext_name);
1790 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1791 vk_free(&device->alloc, device);
1792 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1793 }
1794
1795 device->enabled_extensions.extensions[index] = true;
1796 }
1797
1798 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1799
1800 /* With update after bind we can't attach bo's to the command buffer
1801 * from the descriptor set anymore, so we have to use a global BO list.
1802 */
1803 device->use_global_bo_list =
1804 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1805 device->enabled_extensions.EXT_descriptor_indexing ||
1806 device->enabled_extensions.EXT_buffer_device_address;
1807
1808 mtx_init(&device->shader_slab_mutex, mtx_plain);
1809 list_inithead(&device->shader_slabs);
1810
1811 radv_bo_list_init(&device->bo_list);
1812
1813 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1814 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1815 uint32_t qfi = queue_create->queueFamilyIndex;
1816 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1817 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1818
1819 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1820
1821 device->queues[qfi] = vk_alloc(&device->alloc,
1822 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1823 if (!device->queues[qfi]) {
1824 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1825 goto fail;
1826 }
1827
1828 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1829
1830 device->queue_count[qfi] = queue_create->queueCount;
1831
1832 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1833 result = radv_queue_init(device, &device->queues[qfi][q],
1834 qfi, q, queue_create->flags,
1835 global_priority);
1836 if (result != VK_SUCCESS)
1837 goto fail;
1838 }
1839 }
1840
1841 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1842 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1843
1844 /* Disabled and not implemented for now. */
1845 device->dfsm_allowed = device->pbb_allowed &&
1846 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1847 device->physical_device->rad_info.family == CHIP_RAVEN2);
1848
1849 #ifdef ANDROID
1850 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1851 #endif
1852
1853 /* The maximum number of scratch waves. Scratch space isn't divided
1854 * evenly between CUs. The number is only a function of the number of CUs.
1855 * We can decrease the constant to decrease the scratch buffer size.
1856 *
1857 * sctx->scratch_waves must be >= the maximum possible size of
1858 * 1 threadgroup, so that the hw doesn't hang from being unable
1859 * to start any.
1860 *
1861 * The recommended value is 4 per CU at most. Higher numbers don't
1862 * bring much benefit, but they still occupy chip resources (think
1863 * async compute). I've seen ~2% performance difference between 4 and 32.
1864 */
1865 uint32_t max_threads_per_block = 2048;
1866 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1867 max_threads_per_block / 64);
1868
1869 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1870
1871 if (device->physical_device->rad_info.chip_class >= GFX7) {
1872 /* If the KMD allows it (there is a KMD hw register for it),
1873 * allow launching waves out-of-order.
1874 */
1875 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1876 }
1877
1878 radv_device_init_gs_info(device);
1879
1880 device->tess_offchip_block_dw_size =
1881 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1882 device->has_distributed_tess =
1883 device->physical_device->rad_info.chip_class >= GFX8 &&
1884 device->physical_device->rad_info.max_se >= 2;
1885
1886 if (getenv("RADV_TRACE_FILE")) {
1887 const char *filename = getenv("RADV_TRACE_FILE");
1888
1889 keep_shader_info = true;
1890
1891 if (!radv_init_trace(device))
1892 goto fail;
1893
1894 fprintf(stderr, "*****************************************************************************\n");
1895 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1896 fprintf(stderr, "*****************************************************************************\n");
1897
1898 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1899 radv_dump_enabled_options(device, stderr);
1900 }
1901
1902 device->keep_shader_info = keep_shader_info;
1903
1904 result = radv_device_init_meta(device);
1905 if (result != VK_SUCCESS)
1906 goto fail;
1907
1908 radv_device_init_msaa(device);
1909
1910 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1911 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1912 switch (family) {
1913 case RADV_QUEUE_GENERAL:
1914 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1915 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1916 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1917 break;
1918 case RADV_QUEUE_COMPUTE:
1919 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1920 radeon_emit(device->empty_cs[family], 0);
1921 break;
1922 }
1923 device->ws->cs_finalize(device->empty_cs[family]);
1924 }
1925
1926 if (device->physical_device->rad_info.chip_class >= GFX7)
1927 cik_create_gfx_config(device);
1928
1929 VkPipelineCacheCreateInfo ci;
1930 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1931 ci.pNext = NULL;
1932 ci.flags = 0;
1933 ci.pInitialData = NULL;
1934 ci.initialDataSize = 0;
1935 VkPipelineCache pc;
1936 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1937 &ci, NULL, &pc);
1938 if (result != VK_SUCCESS)
1939 goto fail_meta;
1940
1941 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1942
1943 device->force_aniso =
1944 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1945 if (device->force_aniso >= 0) {
1946 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1947 1 << util_logbase2(device->force_aniso));
1948 }
1949
1950 *pDevice = radv_device_to_handle(device);
1951 return VK_SUCCESS;
1952
1953 fail_meta:
1954 radv_device_finish_meta(device);
1955 fail:
1956 radv_bo_list_finish(&device->bo_list);
1957
1958 if (device->trace_bo)
1959 device->ws->buffer_destroy(device->trace_bo);
1960
1961 if (device->gfx_init)
1962 device->ws->buffer_destroy(device->gfx_init);
1963
1964 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1965 for (unsigned q = 0; q < device->queue_count[i]; q++)
1966 radv_queue_finish(&device->queues[i][q]);
1967 if (device->queue_count[i])
1968 vk_free(&device->alloc, device->queues[i]);
1969 }
1970
1971 vk_free(&device->alloc, device);
1972 return result;
1973 }
1974
1975 void radv_DestroyDevice(
1976 VkDevice _device,
1977 const VkAllocationCallbacks* pAllocator)
1978 {
1979 RADV_FROM_HANDLE(radv_device, device, _device);
1980
1981 if (!device)
1982 return;
1983
1984 if (device->trace_bo)
1985 device->ws->buffer_destroy(device->trace_bo);
1986
1987 if (device->gfx_init)
1988 device->ws->buffer_destroy(device->gfx_init);
1989
1990 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1991 for (unsigned q = 0; q < device->queue_count[i]; q++)
1992 radv_queue_finish(&device->queues[i][q]);
1993 if (device->queue_count[i])
1994 vk_free(&device->alloc, device->queues[i]);
1995 if (device->empty_cs[i])
1996 device->ws->cs_destroy(device->empty_cs[i]);
1997 }
1998 radv_device_finish_meta(device);
1999
2000 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2001 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2002
2003 radv_destroy_shader_slabs(device);
2004
2005 radv_bo_list_finish(&device->bo_list);
2006 vk_free(&device->alloc, device);
2007 }
2008
2009 VkResult radv_EnumerateInstanceLayerProperties(
2010 uint32_t* pPropertyCount,
2011 VkLayerProperties* pProperties)
2012 {
2013 if (pProperties == NULL) {
2014 *pPropertyCount = 0;
2015 return VK_SUCCESS;
2016 }
2017
2018 /* None supported at this time */
2019 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2020 }
2021
2022 VkResult radv_EnumerateDeviceLayerProperties(
2023 VkPhysicalDevice physicalDevice,
2024 uint32_t* pPropertyCount,
2025 VkLayerProperties* pProperties)
2026 {
2027 if (pProperties == NULL) {
2028 *pPropertyCount = 0;
2029 return VK_SUCCESS;
2030 }
2031
2032 /* None supported at this time */
2033 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2034 }
2035
2036 void radv_GetDeviceQueue2(
2037 VkDevice _device,
2038 const VkDeviceQueueInfo2* pQueueInfo,
2039 VkQueue* pQueue)
2040 {
2041 RADV_FROM_HANDLE(radv_device, device, _device);
2042 struct radv_queue *queue;
2043
2044 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2045 if (pQueueInfo->flags != queue->flags) {
2046 /* From the Vulkan 1.1.70 spec:
2047 *
2048 * "The queue returned by vkGetDeviceQueue2 must have the same
2049 * flags value from this structure as that used at device
2050 * creation time in a VkDeviceQueueCreateInfo instance. If no
2051 * matching flags were specified at device creation time then
2052 * pQueue will return VK_NULL_HANDLE."
2053 */
2054 *pQueue = VK_NULL_HANDLE;
2055 return;
2056 }
2057
2058 *pQueue = radv_queue_to_handle(queue);
2059 }
2060
2061 void radv_GetDeviceQueue(
2062 VkDevice _device,
2063 uint32_t queueFamilyIndex,
2064 uint32_t queueIndex,
2065 VkQueue* pQueue)
2066 {
2067 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2068 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2069 .queueFamilyIndex = queueFamilyIndex,
2070 .queueIndex = queueIndex
2071 };
2072
2073 radv_GetDeviceQueue2(_device, &info, pQueue);
2074 }
2075
2076 static void
2077 fill_geom_tess_rings(struct radv_queue *queue,
2078 uint32_t *map,
2079 bool add_sample_positions,
2080 uint32_t esgs_ring_size,
2081 struct radeon_winsys_bo *esgs_ring_bo,
2082 uint32_t gsvs_ring_size,
2083 struct radeon_winsys_bo *gsvs_ring_bo,
2084 uint32_t tess_factor_ring_size,
2085 uint32_t tess_offchip_ring_offset,
2086 uint32_t tess_offchip_ring_size,
2087 struct radeon_winsys_bo *tess_rings_bo)
2088 {
2089 uint32_t *desc = &map[4];
2090
2091 if (esgs_ring_bo) {
2092 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2093
2094 /* stride 0, num records - size, add tid, swizzle, elsize4,
2095 index stride 64 */
2096 desc[0] = esgs_va;
2097 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2098 S_008F04_STRIDE(0) |
2099 S_008F04_SWIZZLE_ENABLE(true);
2100 desc[2] = esgs_ring_size;
2101 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2102 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2103 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2104 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2105 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2106 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2107 S_008F0C_ELEMENT_SIZE(1) |
2108 S_008F0C_INDEX_STRIDE(3) |
2109 S_008F0C_ADD_TID_ENABLE(true);
2110
2111 /* GS entry for ES->GS ring */
2112 /* stride 0, num records - size, elsize0,
2113 index stride 0 */
2114 desc[4] = esgs_va;
2115 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2116 S_008F04_STRIDE(0) |
2117 S_008F04_SWIZZLE_ENABLE(false);
2118 desc[6] = esgs_ring_size;
2119 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2120 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2121 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2122 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2123 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2124 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2125 S_008F0C_ELEMENT_SIZE(0) |
2126 S_008F0C_INDEX_STRIDE(0) |
2127 S_008F0C_ADD_TID_ENABLE(false);
2128 }
2129
2130 desc += 8;
2131
2132 if (gsvs_ring_bo) {
2133 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2134
2135 /* VS entry for GS->VS ring */
2136 /* stride 0, num records - size, elsize0,
2137 index stride 0 */
2138 desc[0] = gsvs_va;
2139 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2140 S_008F04_STRIDE(0) |
2141 S_008F04_SWIZZLE_ENABLE(false);
2142 desc[2] = gsvs_ring_size;
2143 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2144 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2145 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2146 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2147 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2148 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2149 S_008F0C_ELEMENT_SIZE(0) |
2150 S_008F0C_INDEX_STRIDE(0) |
2151 S_008F0C_ADD_TID_ENABLE(false);
2152
2153 /* stride gsvs_itemsize, num records 64
2154 elsize 4, index stride 16 */
2155 /* shader will patch stride and desc[2] */
2156 desc[4] = gsvs_va;
2157 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2158 S_008F04_STRIDE(0) |
2159 S_008F04_SWIZZLE_ENABLE(true);
2160 desc[6] = 0;
2161 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2165 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2166 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2167 S_008F0C_ELEMENT_SIZE(1) |
2168 S_008F0C_INDEX_STRIDE(1) |
2169 S_008F0C_ADD_TID_ENABLE(true);
2170 }
2171
2172 desc += 8;
2173
2174 if (tess_rings_bo) {
2175 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2176 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2177
2178 desc[0] = tess_va;
2179 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2180 S_008F04_STRIDE(0) |
2181 S_008F04_SWIZZLE_ENABLE(false);
2182 desc[2] = tess_factor_ring_size;
2183 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2187 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2188 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2189 S_008F0C_ELEMENT_SIZE(0) |
2190 S_008F0C_INDEX_STRIDE(0) |
2191 S_008F0C_ADD_TID_ENABLE(false);
2192
2193 desc[4] = tess_offchip_va;
2194 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2195 S_008F04_STRIDE(0) |
2196 S_008F04_SWIZZLE_ENABLE(false);
2197 desc[6] = tess_offchip_ring_size;
2198 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2199 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2200 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2201 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2202 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2203 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2204 S_008F0C_ELEMENT_SIZE(0) |
2205 S_008F0C_INDEX_STRIDE(0) |
2206 S_008F0C_ADD_TID_ENABLE(false);
2207 }
2208
2209 desc += 8;
2210
2211 if (add_sample_positions) {
2212 /* add sample positions after all rings */
2213 memcpy(desc, queue->device->sample_locations_1x, 8);
2214 desc += 2;
2215 memcpy(desc, queue->device->sample_locations_2x, 16);
2216 desc += 4;
2217 memcpy(desc, queue->device->sample_locations_4x, 32);
2218 desc += 8;
2219 memcpy(desc, queue->device->sample_locations_8x, 64);
2220 }
2221 }
2222
2223 static unsigned
2224 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2225 {
2226 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2227 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2228 device->physical_device->rad_info.family != CHIP_STONEY;
2229 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2230 unsigned max_offchip_buffers;
2231 unsigned offchip_granularity;
2232 unsigned hs_offchip_param;
2233
2234 /*
2235 * Per RadeonSI:
2236 * This must be one less than the maximum number due to a hw limitation.
2237 * Various hardware bugs need thGFX7
2238 *
2239 * Per AMDVLK:
2240 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2241 * Gfx7 should limit max_offchip_buffers to 508
2242 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2243 *
2244 * Follow AMDVLK here.
2245 */
2246 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2247 device->physical_device->rad_info.chip_class == GFX7 ||
2248 device->physical_device->rad_info.chip_class == GFX6)
2249 --max_offchip_buffers_per_se;
2250
2251 max_offchip_buffers = max_offchip_buffers_per_se *
2252 device->physical_device->rad_info.max_se;
2253
2254 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2255 * around by setting 4K granularity.
2256 */
2257 if (device->tess_offchip_block_dw_size == 4096) {
2258 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2259 offchip_granularity = V_03093C_X_4K_DWORDS;
2260 } else {
2261 assert(device->tess_offchip_block_dw_size == 8192);
2262 offchip_granularity = V_03093C_X_8K_DWORDS;
2263 }
2264
2265 switch (device->physical_device->rad_info.chip_class) {
2266 case GFX6:
2267 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2268 break;
2269 case GFX7:
2270 case GFX8:
2271 case GFX9:
2272 default:
2273 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2274 break;
2275 }
2276
2277 *max_offchip_buffers_p = max_offchip_buffers;
2278 if (device->physical_device->rad_info.chip_class >= GFX7) {
2279 if (device->physical_device->rad_info.chip_class >= GFX8)
2280 --max_offchip_buffers;
2281 hs_offchip_param =
2282 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2283 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2284 } else {
2285 hs_offchip_param =
2286 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2287 }
2288 return hs_offchip_param;
2289 }
2290
2291 static void
2292 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2293 struct radeon_winsys_bo *esgs_ring_bo,
2294 uint32_t esgs_ring_size,
2295 struct radeon_winsys_bo *gsvs_ring_bo,
2296 uint32_t gsvs_ring_size)
2297 {
2298 if (!esgs_ring_bo && !gsvs_ring_bo)
2299 return;
2300
2301 if (esgs_ring_bo)
2302 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2303
2304 if (gsvs_ring_bo)
2305 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2306
2307 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2308 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2309 radeon_emit(cs, esgs_ring_size >> 8);
2310 radeon_emit(cs, gsvs_ring_size >> 8);
2311 } else {
2312 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2313 radeon_emit(cs, esgs_ring_size >> 8);
2314 radeon_emit(cs, gsvs_ring_size >> 8);
2315 }
2316 }
2317
2318 static void
2319 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2320 unsigned hs_offchip_param, unsigned tf_ring_size,
2321 struct radeon_winsys_bo *tess_rings_bo)
2322 {
2323 uint64_t tf_va;
2324
2325 if (!tess_rings_bo)
2326 return;
2327
2328 tf_va = radv_buffer_get_va(tess_rings_bo);
2329
2330 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2331
2332 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2333 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2334 S_030938_SIZE(tf_ring_size / 4));
2335 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2336 tf_va >> 8);
2337 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2338 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2339 S_030944_BASE_HI(tf_va >> 40));
2340 }
2341 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2342 hs_offchip_param);
2343 } else {
2344 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2345 S_008988_SIZE(tf_ring_size / 4));
2346 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2347 tf_va >> 8);
2348 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2349 hs_offchip_param);
2350 }
2351 }
2352
2353 static void
2354 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2355 struct radeon_winsys_bo *compute_scratch_bo)
2356 {
2357 uint64_t scratch_va;
2358
2359 if (!compute_scratch_bo)
2360 return;
2361
2362 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2363
2364 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2365
2366 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2367 radeon_emit(cs, scratch_va);
2368 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2369 S_008F04_SWIZZLE_ENABLE(1));
2370 }
2371
2372 static void
2373 radv_emit_global_shader_pointers(struct radv_queue *queue,
2374 struct radeon_cmdbuf *cs,
2375 struct radeon_winsys_bo *descriptor_bo)
2376 {
2377 uint64_t va;
2378
2379 if (!descriptor_bo)
2380 return;
2381
2382 va = radv_buffer_get_va(descriptor_bo);
2383
2384 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2385
2386 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2387 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2388 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2389 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2390 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2391
2392 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2393 radv_emit_shader_pointer(queue->device, cs, regs[i],
2394 va, true);
2395 }
2396 } else {
2397 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2398 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2399 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2400 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2401 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2402 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2403
2404 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2405 radv_emit_shader_pointer(queue->device, cs, regs[i],
2406 va, true);
2407 }
2408 }
2409 }
2410
2411 static void
2412 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2413 {
2414 struct radv_device *device = queue->device;
2415
2416 if (device->gfx_init) {
2417 uint64_t va = radv_buffer_get_va(device->gfx_init);
2418
2419 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2420 radeon_emit(cs, va);
2421 radeon_emit(cs, va >> 32);
2422 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2423
2424 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2425 } else {
2426 struct radv_physical_device *physical_device = device->physical_device;
2427 si_emit_graphics(physical_device, cs);
2428 }
2429 }
2430
2431 static void
2432 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2433 {
2434 struct radv_physical_device *physical_device = queue->device->physical_device;
2435 si_emit_compute(physical_device, cs);
2436 }
2437
2438 static VkResult
2439 radv_get_preamble_cs(struct radv_queue *queue,
2440 uint32_t scratch_size,
2441 uint32_t compute_scratch_size,
2442 uint32_t esgs_ring_size,
2443 uint32_t gsvs_ring_size,
2444 bool needs_tess_rings,
2445 bool needs_sample_positions,
2446 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2447 struct radeon_cmdbuf **initial_preamble_cs,
2448 struct radeon_cmdbuf **continue_preamble_cs)
2449 {
2450 struct radeon_winsys_bo *scratch_bo = NULL;
2451 struct radeon_winsys_bo *descriptor_bo = NULL;
2452 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2453 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2454 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2455 struct radeon_winsys_bo *tess_rings_bo = NULL;
2456 struct radeon_cmdbuf *dest_cs[3] = {0};
2457 bool add_tess_rings = false, add_sample_positions = false;
2458 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2459 unsigned max_offchip_buffers;
2460 unsigned hs_offchip_param = 0;
2461 unsigned tess_offchip_ring_offset;
2462 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2463 if (!queue->has_tess_rings) {
2464 if (needs_tess_rings)
2465 add_tess_rings = true;
2466 }
2467 if (!queue->has_sample_positions) {
2468 if (needs_sample_positions)
2469 add_sample_positions = true;
2470 }
2471 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2472 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2473 &max_offchip_buffers);
2474 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2475 tess_offchip_ring_size = max_offchip_buffers *
2476 queue->device->tess_offchip_block_dw_size * 4;
2477
2478 if (scratch_size <= queue->scratch_size &&
2479 compute_scratch_size <= queue->compute_scratch_size &&
2480 esgs_ring_size <= queue->esgs_ring_size &&
2481 gsvs_ring_size <= queue->gsvs_ring_size &&
2482 !add_tess_rings && !add_sample_positions &&
2483 queue->initial_preamble_cs) {
2484 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2485 *initial_preamble_cs = queue->initial_preamble_cs;
2486 *continue_preamble_cs = queue->continue_preamble_cs;
2487 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2488 *continue_preamble_cs = NULL;
2489 return VK_SUCCESS;
2490 }
2491
2492 if (scratch_size > queue->scratch_size) {
2493 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2494 scratch_size,
2495 4096,
2496 RADEON_DOMAIN_VRAM,
2497 ring_bo_flags,
2498 RADV_BO_PRIORITY_SCRATCH);
2499 if (!scratch_bo)
2500 goto fail;
2501 } else
2502 scratch_bo = queue->scratch_bo;
2503
2504 if (compute_scratch_size > queue->compute_scratch_size) {
2505 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2506 compute_scratch_size,
2507 4096,
2508 RADEON_DOMAIN_VRAM,
2509 ring_bo_flags,
2510 RADV_BO_PRIORITY_SCRATCH);
2511 if (!compute_scratch_bo)
2512 goto fail;
2513
2514 } else
2515 compute_scratch_bo = queue->compute_scratch_bo;
2516
2517 if (esgs_ring_size > queue->esgs_ring_size) {
2518 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2519 esgs_ring_size,
2520 4096,
2521 RADEON_DOMAIN_VRAM,
2522 ring_bo_flags,
2523 RADV_BO_PRIORITY_SCRATCH);
2524 if (!esgs_ring_bo)
2525 goto fail;
2526 } else {
2527 esgs_ring_bo = queue->esgs_ring_bo;
2528 esgs_ring_size = queue->esgs_ring_size;
2529 }
2530
2531 if (gsvs_ring_size > queue->gsvs_ring_size) {
2532 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2533 gsvs_ring_size,
2534 4096,
2535 RADEON_DOMAIN_VRAM,
2536 ring_bo_flags,
2537 RADV_BO_PRIORITY_SCRATCH);
2538 if (!gsvs_ring_bo)
2539 goto fail;
2540 } else {
2541 gsvs_ring_bo = queue->gsvs_ring_bo;
2542 gsvs_ring_size = queue->gsvs_ring_size;
2543 }
2544
2545 if (add_tess_rings) {
2546 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2547 tess_offchip_ring_offset + tess_offchip_ring_size,
2548 256,
2549 RADEON_DOMAIN_VRAM,
2550 ring_bo_flags,
2551 RADV_BO_PRIORITY_SCRATCH);
2552 if (!tess_rings_bo)
2553 goto fail;
2554 } else {
2555 tess_rings_bo = queue->tess_rings_bo;
2556 }
2557
2558 if (scratch_bo != queue->scratch_bo ||
2559 esgs_ring_bo != queue->esgs_ring_bo ||
2560 gsvs_ring_bo != queue->gsvs_ring_bo ||
2561 tess_rings_bo != queue->tess_rings_bo ||
2562 add_sample_positions) {
2563 uint32_t size = 0;
2564 if (gsvs_ring_bo || esgs_ring_bo ||
2565 tess_rings_bo || add_sample_positions) {
2566 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2567 if (add_sample_positions)
2568 size += 128; /* 64+32+16+8 = 120 bytes */
2569 }
2570 else if (scratch_bo)
2571 size = 8; /* 2 dword */
2572
2573 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2574 size,
2575 4096,
2576 RADEON_DOMAIN_VRAM,
2577 RADEON_FLAG_CPU_ACCESS |
2578 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2579 RADEON_FLAG_READ_ONLY,
2580 RADV_BO_PRIORITY_DESCRIPTOR);
2581 if (!descriptor_bo)
2582 goto fail;
2583 } else
2584 descriptor_bo = queue->descriptor_bo;
2585
2586 if (descriptor_bo != queue->descriptor_bo) {
2587 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2588
2589 if (scratch_bo) {
2590 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2591 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2592 S_008F04_SWIZZLE_ENABLE(1);
2593 map[0] = scratch_va;
2594 map[1] = rsrc1;
2595 }
2596
2597 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2598 fill_geom_tess_rings(queue, map, add_sample_positions,
2599 esgs_ring_size, esgs_ring_bo,
2600 gsvs_ring_size, gsvs_ring_bo,
2601 tess_factor_ring_size,
2602 tess_offchip_ring_offset,
2603 tess_offchip_ring_size,
2604 tess_rings_bo);
2605
2606 queue->device->ws->buffer_unmap(descriptor_bo);
2607 }
2608
2609 for(int i = 0; i < 3; ++i) {
2610 struct radeon_cmdbuf *cs = NULL;
2611 cs = queue->device->ws->cs_create(queue->device->ws,
2612 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2613 if (!cs)
2614 goto fail;
2615
2616 dest_cs[i] = cs;
2617
2618 if (scratch_bo)
2619 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2620
2621 /* Emit initial configuration. */
2622 switch (queue->queue_family_index) {
2623 case RADV_QUEUE_GENERAL:
2624 radv_init_graphics_state(cs, queue);
2625 break;
2626 case RADV_QUEUE_COMPUTE:
2627 radv_init_compute_state(cs, queue);
2628 break;
2629 case RADV_QUEUE_TRANSFER:
2630 break;
2631 }
2632
2633 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2634 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2635 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2636 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2637 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2638 }
2639
2640 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2641 gsvs_ring_bo, gsvs_ring_size);
2642 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2643 tess_factor_ring_size, tess_rings_bo);
2644 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2645 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2646
2647 if (i == 0) {
2648 si_cs_emit_cache_flush(cs,
2649 queue->device->physical_device->rad_info.chip_class,
2650 NULL, 0,
2651 queue->queue_family_index == RING_COMPUTE &&
2652 queue->device->physical_device->rad_info.chip_class >= GFX7,
2653 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2654 RADV_CMD_FLAG_INV_ICACHE |
2655 RADV_CMD_FLAG_INV_SMEM_L1 |
2656 RADV_CMD_FLAG_INV_VMEM_L1 |
2657 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2658 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2659 } else if (i == 1) {
2660 si_cs_emit_cache_flush(cs,
2661 queue->device->physical_device->rad_info.chip_class,
2662 NULL, 0,
2663 queue->queue_family_index == RING_COMPUTE &&
2664 queue->device->physical_device->rad_info.chip_class >= GFX7,
2665 RADV_CMD_FLAG_INV_ICACHE |
2666 RADV_CMD_FLAG_INV_SMEM_L1 |
2667 RADV_CMD_FLAG_INV_VMEM_L1 |
2668 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2669 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2670 }
2671
2672 if (!queue->device->ws->cs_finalize(cs))
2673 goto fail;
2674 }
2675
2676 if (queue->initial_full_flush_preamble_cs)
2677 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2678
2679 if (queue->initial_preamble_cs)
2680 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2681
2682 if (queue->continue_preamble_cs)
2683 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2684
2685 queue->initial_full_flush_preamble_cs = dest_cs[0];
2686 queue->initial_preamble_cs = dest_cs[1];
2687 queue->continue_preamble_cs = dest_cs[2];
2688
2689 if (scratch_bo != queue->scratch_bo) {
2690 if (queue->scratch_bo)
2691 queue->device->ws->buffer_destroy(queue->scratch_bo);
2692 queue->scratch_bo = scratch_bo;
2693 queue->scratch_size = scratch_size;
2694 }
2695
2696 if (compute_scratch_bo != queue->compute_scratch_bo) {
2697 if (queue->compute_scratch_bo)
2698 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2699 queue->compute_scratch_bo = compute_scratch_bo;
2700 queue->compute_scratch_size = compute_scratch_size;
2701 }
2702
2703 if (esgs_ring_bo != queue->esgs_ring_bo) {
2704 if (queue->esgs_ring_bo)
2705 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2706 queue->esgs_ring_bo = esgs_ring_bo;
2707 queue->esgs_ring_size = esgs_ring_size;
2708 }
2709
2710 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2711 if (queue->gsvs_ring_bo)
2712 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2713 queue->gsvs_ring_bo = gsvs_ring_bo;
2714 queue->gsvs_ring_size = gsvs_ring_size;
2715 }
2716
2717 if (tess_rings_bo != queue->tess_rings_bo) {
2718 queue->tess_rings_bo = tess_rings_bo;
2719 queue->has_tess_rings = true;
2720 }
2721
2722 if (descriptor_bo != queue->descriptor_bo) {
2723 if (queue->descriptor_bo)
2724 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2725
2726 queue->descriptor_bo = descriptor_bo;
2727 }
2728
2729 if (add_sample_positions)
2730 queue->has_sample_positions = true;
2731
2732 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2733 *initial_preamble_cs = queue->initial_preamble_cs;
2734 *continue_preamble_cs = queue->continue_preamble_cs;
2735 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2736 *continue_preamble_cs = NULL;
2737 return VK_SUCCESS;
2738 fail:
2739 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2740 if (dest_cs[i])
2741 queue->device->ws->cs_destroy(dest_cs[i]);
2742 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2743 queue->device->ws->buffer_destroy(descriptor_bo);
2744 if (scratch_bo && scratch_bo != queue->scratch_bo)
2745 queue->device->ws->buffer_destroy(scratch_bo);
2746 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2747 queue->device->ws->buffer_destroy(compute_scratch_bo);
2748 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2749 queue->device->ws->buffer_destroy(esgs_ring_bo);
2750 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2751 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2752 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2753 queue->device->ws->buffer_destroy(tess_rings_bo);
2754 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2755 }
2756
2757 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2758 struct radv_winsys_sem_counts *counts,
2759 int num_sems,
2760 const VkSemaphore *sems,
2761 VkFence _fence,
2762 bool reset_temp)
2763 {
2764 int syncobj_idx = 0, sem_idx = 0;
2765
2766 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2767 return VK_SUCCESS;
2768
2769 for (uint32_t i = 0; i < num_sems; i++) {
2770 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2771
2772 if (sem->temp_syncobj || sem->syncobj)
2773 counts->syncobj_count++;
2774 else
2775 counts->sem_count++;
2776 }
2777
2778 if (_fence != VK_NULL_HANDLE) {
2779 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2780 if (fence->temp_syncobj || fence->syncobj)
2781 counts->syncobj_count++;
2782 }
2783
2784 if (counts->syncobj_count) {
2785 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2786 if (!counts->syncobj)
2787 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2788 }
2789
2790 if (counts->sem_count) {
2791 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2792 if (!counts->sem) {
2793 free(counts->syncobj);
2794 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2795 }
2796 }
2797
2798 for (uint32_t i = 0; i < num_sems; i++) {
2799 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2800
2801 if (sem->temp_syncobj) {
2802 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2803 }
2804 else if (sem->syncobj)
2805 counts->syncobj[syncobj_idx++] = sem->syncobj;
2806 else {
2807 assert(sem->sem);
2808 counts->sem[sem_idx++] = sem->sem;
2809 }
2810 }
2811
2812 if (_fence != VK_NULL_HANDLE) {
2813 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2814 if (fence->temp_syncobj)
2815 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2816 else if (fence->syncobj)
2817 counts->syncobj[syncobj_idx++] = fence->syncobj;
2818 }
2819
2820 return VK_SUCCESS;
2821 }
2822
2823 static void
2824 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2825 {
2826 free(sem_info->wait.syncobj);
2827 free(sem_info->wait.sem);
2828 free(sem_info->signal.syncobj);
2829 free(sem_info->signal.sem);
2830 }
2831
2832
2833 static void radv_free_temp_syncobjs(struct radv_device *device,
2834 int num_sems,
2835 const VkSemaphore *sems)
2836 {
2837 for (uint32_t i = 0; i < num_sems; i++) {
2838 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2839
2840 if (sem->temp_syncobj) {
2841 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2842 sem->temp_syncobj = 0;
2843 }
2844 }
2845 }
2846
2847 static VkResult
2848 radv_alloc_sem_info(struct radv_instance *instance,
2849 struct radv_winsys_sem_info *sem_info,
2850 int num_wait_sems,
2851 const VkSemaphore *wait_sems,
2852 int num_signal_sems,
2853 const VkSemaphore *signal_sems,
2854 VkFence fence)
2855 {
2856 VkResult ret;
2857 memset(sem_info, 0, sizeof(*sem_info));
2858
2859 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2860 if (ret)
2861 return ret;
2862 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2863 if (ret)
2864 radv_free_sem_info(sem_info);
2865
2866 /* caller can override these */
2867 sem_info->cs_emit_wait = true;
2868 sem_info->cs_emit_signal = true;
2869 return ret;
2870 }
2871
2872 /* Signals fence as soon as all the work currently put on queue is done. */
2873 static VkResult radv_signal_fence(struct radv_queue *queue,
2874 struct radv_fence *fence)
2875 {
2876 int ret;
2877 VkResult result;
2878 struct radv_winsys_sem_info sem_info;
2879
2880 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2881 radv_fence_to_handle(fence));
2882 if (result != VK_SUCCESS)
2883 return result;
2884
2885 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2886 &queue->device->empty_cs[queue->queue_family_index],
2887 1, NULL, NULL, &sem_info, NULL,
2888 false, fence->fence);
2889 radv_free_sem_info(&sem_info);
2890
2891 if (ret)
2892 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2893
2894 return VK_SUCCESS;
2895 }
2896
2897 VkResult radv_QueueSubmit(
2898 VkQueue _queue,
2899 uint32_t submitCount,
2900 const VkSubmitInfo* pSubmits,
2901 VkFence _fence)
2902 {
2903 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2904 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2905 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2906 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2907 int ret;
2908 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2909 uint32_t scratch_size = 0;
2910 uint32_t compute_scratch_size = 0;
2911 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2912 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2913 VkResult result;
2914 bool fence_emitted = false;
2915 bool tess_rings_needed = false;
2916 bool sample_positions_needed = false;
2917
2918 /* Do this first so failing to allocate scratch buffers can't result in
2919 * partially executed submissions. */
2920 for (uint32_t i = 0; i < submitCount; i++) {
2921 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2922 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2923 pSubmits[i].pCommandBuffers[j]);
2924
2925 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2926 compute_scratch_size = MAX2(compute_scratch_size,
2927 cmd_buffer->compute_scratch_size_needed);
2928 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2929 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2930 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2931 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2932 }
2933 }
2934
2935 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2936 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2937 sample_positions_needed, &initial_flush_preamble_cs,
2938 &initial_preamble_cs, &continue_preamble_cs);
2939 if (result != VK_SUCCESS)
2940 return result;
2941
2942 for (uint32_t i = 0; i < submitCount; i++) {
2943 struct radeon_cmdbuf **cs_array;
2944 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2945 bool can_patch = true;
2946 uint32_t advance;
2947 struct radv_winsys_sem_info sem_info;
2948
2949 result = radv_alloc_sem_info(queue->device->instance,
2950 &sem_info,
2951 pSubmits[i].waitSemaphoreCount,
2952 pSubmits[i].pWaitSemaphores,
2953 pSubmits[i].signalSemaphoreCount,
2954 pSubmits[i].pSignalSemaphores,
2955 _fence);
2956 if (result != VK_SUCCESS)
2957 return result;
2958
2959 if (!pSubmits[i].commandBufferCount) {
2960 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2961 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2962 &queue->device->empty_cs[queue->queue_family_index],
2963 1, NULL, NULL,
2964 &sem_info, NULL,
2965 false, base_fence);
2966 if (ret) {
2967 radv_loge("failed to submit CS %d\n", i);
2968 abort();
2969 }
2970 fence_emitted = true;
2971 }
2972 radv_free_sem_info(&sem_info);
2973 continue;
2974 }
2975
2976 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2977 (pSubmits[i].commandBufferCount));
2978
2979 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2980 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2981 pSubmits[i].pCommandBuffers[j]);
2982 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2983
2984 cs_array[j] = cmd_buffer->cs;
2985 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2986 can_patch = false;
2987
2988 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2989 }
2990
2991 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2992 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2993 const struct radv_winsys_bo_list *bo_list = NULL;
2994
2995 advance = MIN2(max_cs_submission,
2996 pSubmits[i].commandBufferCount - j);
2997
2998 if (queue->device->trace_bo)
2999 *queue->device->trace_id_ptr = 0;
3000
3001 sem_info.cs_emit_wait = j == 0;
3002 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3003
3004 if (unlikely(queue->device->use_global_bo_list)) {
3005 pthread_mutex_lock(&queue->device->bo_list.mutex);
3006 bo_list = &queue->device->bo_list.list;
3007 }
3008
3009 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3010 advance, initial_preamble, continue_preamble_cs,
3011 &sem_info, bo_list,
3012 can_patch, base_fence);
3013
3014 if (unlikely(queue->device->use_global_bo_list))
3015 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3016
3017 if (ret) {
3018 radv_loge("failed to submit CS %d\n", i);
3019 abort();
3020 }
3021 fence_emitted = true;
3022 if (queue->device->trace_bo) {
3023 radv_check_gpu_hangs(queue, cs_array[j]);
3024 }
3025 }
3026
3027 radv_free_temp_syncobjs(queue->device,
3028 pSubmits[i].waitSemaphoreCount,
3029 pSubmits[i].pWaitSemaphores);
3030 radv_free_sem_info(&sem_info);
3031 free(cs_array);
3032 }
3033
3034 if (fence) {
3035 if (!fence_emitted) {
3036 result = radv_signal_fence(queue, fence);
3037 if (result != VK_SUCCESS)
3038 return result;
3039 }
3040 }
3041
3042 return VK_SUCCESS;
3043 }
3044
3045 VkResult radv_QueueWaitIdle(
3046 VkQueue _queue)
3047 {
3048 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3049
3050 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3051 radv_queue_family_to_ring(queue->queue_family_index),
3052 queue->queue_idx);
3053 return VK_SUCCESS;
3054 }
3055
3056 VkResult radv_DeviceWaitIdle(
3057 VkDevice _device)
3058 {
3059 RADV_FROM_HANDLE(radv_device, device, _device);
3060
3061 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3062 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3063 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3064 }
3065 }
3066 return VK_SUCCESS;
3067 }
3068
3069 VkResult radv_EnumerateInstanceExtensionProperties(
3070 const char* pLayerName,
3071 uint32_t* pPropertyCount,
3072 VkExtensionProperties* pProperties)
3073 {
3074 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3075
3076 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3077 if (radv_supported_instance_extensions.extensions[i]) {
3078 vk_outarray_append(&out, prop) {
3079 *prop = radv_instance_extensions[i];
3080 }
3081 }
3082 }
3083
3084 return vk_outarray_status(&out);
3085 }
3086
3087 VkResult radv_EnumerateDeviceExtensionProperties(
3088 VkPhysicalDevice physicalDevice,
3089 const char* pLayerName,
3090 uint32_t* pPropertyCount,
3091 VkExtensionProperties* pProperties)
3092 {
3093 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3094 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3095
3096 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3097 if (device->supported_extensions.extensions[i]) {
3098 vk_outarray_append(&out, prop) {
3099 *prop = radv_device_extensions[i];
3100 }
3101 }
3102 }
3103
3104 return vk_outarray_status(&out);
3105 }
3106
3107 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3108 VkInstance _instance,
3109 const char* pName)
3110 {
3111 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3112
3113 return radv_lookup_entrypoint_checked(pName,
3114 instance ? instance->apiVersion : 0,
3115 instance ? &instance->enabled_extensions : NULL,
3116 NULL);
3117 }
3118
3119 /* The loader wants us to expose a second GetInstanceProcAddr function
3120 * to work around certain LD_PRELOAD issues seen in apps.
3121 */
3122 PUBLIC
3123 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3124 VkInstance instance,
3125 const char* pName);
3126
3127 PUBLIC
3128 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3129 VkInstance instance,
3130 const char* pName)
3131 {
3132 return radv_GetInstanceProcAddr(instance, pName);
3133 }
3134
3135 PUBLIC
3136 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3137 VkInstance _instance,
3138 const char* pName);
3139
3140 PUBLIC
3141 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3142 VkInstance _instance,
3143 const char* pName)
3144 {
3145 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3146
3147 return radv_lookup_physical_device_entrypoint_checked(pName,
3148 instance ? instance->apiVersion : 0,
3149 instance ? &instance->enabled_extensions : NULL);
3150 }
3151
3152 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3153 VkDevice _device,
3154 const char* pName)
3155 {
3156 RADV_FROM_HANDLE(radv_device, device, _device);
3157
3158 return radv_lookup_entrypoint_checked(pName,
3159 device->instance->apiVersion,
3160 &device->instance->enabled_extensions,
3161 &device->enabled_extensions);
3162 }
3163
3164 bool radv_get_memory_fd(struct radv_device *device,
3165 struct radv_device_memory *memory,
3166 int *pFD)
3167 {
3168 struct radeon_bo_metadata metadata;
3169
3170 if (memory->image) {
3171 radv_init_metadata(device, memory->image, &metadata);
3172 device->ws->buffer_set_metadata(memory->bo, &metadata);
3173 }
3174
3175 return device->ws->buffer_get_fd(device->ws, memory->bo,
3176 pFD);
3177 }
3178
3179 static VkResult radv_alloc_memory(struct radv_device *device,
3180 const VkMemoryAllocateInfo* pAllocateInfo,
3181 const VkAllocationCallbacks* pAllocator,
3182 VkDeviceMemory* pMem)
3183 {
3184 struct radv_device_memory *mem;
3185 VkResult result;
3186 enum radeon_bo_domain domain;
3187 uint32_t flags = 0;
3188 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3189
3190 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3191
3192 if (pAllocateInfo->allocationSize == 0) {
3193 /* Apparently, this is allowed */
3194 *pMem = VK_NULL_HANDLE;
3195 return VK_SUCCESS;
3196 }
3197
3198 const VkImportMemoryFdInfoKHR *import_info =
3199 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3200 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3201 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3202 const VkExportMemoryAllocateInfo *export_info =
3203 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3204 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3205 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3206
3207 const struct wsi_memory_allocate_info *wsi_info =
3208 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3209
3210 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3211 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3212 if (mem == NULL)
3213 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3214
3215 if (wsi_info && wsi_info->implicit_sync)
3216 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3217
3218 if (dedicate_info) {
3219 mem->image = radv_image_from_handle(dedicate_info->image);
3220 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3221 } else {
3222 mem->image = NULL;
3223 mem->buffer = NULL;
3224 }
3225
3226 float priority_float = 0.5;
3227 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3228 vk_find_struct_const(pAllocateInfo->pNext,
3229 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3230 if (priority_ext)
3231 priority_float = priority_ext->priority;
3232
3233 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3234 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3235
3236 mem->user_ptr = NULL;
3237
3238 if (import_info) {
3239 assert(import_info->handleType ==
3240 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3241 import_info->handleType ==
3242 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3243 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3244 priority, NULL, NULL);
3245 if (!mem->bo) {
3246 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3247 goto fail;
3248 } else {
3249 close(import_info->fd);
3250 }
3251 } else if (host_ptr_info) {
3252 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3253 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3254 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3255 pAllocateInfo->allocationSize,
3256 priority);
3257 if (!mem->bo) {
3258 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3259 goto fail;
3260 } else {
3261 mem->user_ptr = host_ptr_info->pHostPointer;
3262 }
3263 } else {
3264 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3265 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3266 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3267 domain = RADEON_DOMAIN_GTT;
3268 else
3269 domain = RADEON_DOMAIN_VRAM;
3270
3271 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3272 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3273 else
3274 flags |= RADEON_FLAG_CPU_ACCESS;
3275
3276 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3277 flags |= RADEON_FLAG_GTT_WC;
3278
3279 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3280 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3281 if (device->use_global_bo_list) {
3282 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3283 }
3284 }
3285
3286 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3287 domain, flags, priority);
3288
3289 if (!mem->bo) {
3290 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3291 goto fail;
3292 }
3293 mem->type_index = mem_type_index;
3294 }
3295
3296 result = radv_bo_list_add(device, mem->bo);
3297 if (result != VK_SUCCESS)
3298 goto fail_bo;
3299
3300 *pMem = radv_device_memory_to_handle(mem);
3301
3302 return VK_SUCCESS;
3303
3304 fail_bo:
3305 device->ws->buffer_destroy(mem->bo);
3306 fail:
3307 vk_free2(&device->alloc, pAllocator, mem);
3308
3309 return result;
3310 }
3311
3312 VkResult radv_AllocateMemory(
3313 VkDevice _device,
3314 const VkMemoryAllocateInfo* pAllocateInfo,
3315 const VkAllocationCallbacks* pAllocator,
3316 VkDeviceMemory* pMem)
3317 {
3318 RADV_FROM_HANDLE(radv_device, device, _device);
3319 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3320 }
3321
3322 void radv_FreeMemory(
3323 VkDevice _device,
3324 VkDeviceMemory _mem,
3325 const VkAllocationCallbacks* pAllocator)
3326 {
3327 RADV_FROM_HANDLE(radv_device, device, _device);
3328 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3329
3330 if (mem == NULL)
3331 return;
3332
3333 radv_bo_list_remove(device, mem->bo);
3334 device->ws->buffer_destroy(mem->bo);
3335 mem->bo = NULL;
3336
3337 vk_free2(&device->alloc, pAllocator, mem);
3338 }
3339
3340 VkResult radv_MapMemory(
3341 VkDevice _device,
3342 VkDeviceMemory _memory,
3343 VkDeviceSize offset,
3344 VkDeviceSize size,
3345 VkMemoryMapFlags flags,
3346 void** ppData)
3347 {
3348 RADV_FROM_HANDLE(radv_device, device, _device);
3349 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3350
3351 if (mem == NULL) {
3352 *ppData = NULL;
3353 return VK_SUCCESS;
3354 }
3355
3356 if (mem->user_ptr)
3357 *ppData = mem->user_ptr;
3358 else
3359 *ppData = device->ws->buffer_map(mem->bo);
3360
3361 if (*ppData) {
3362 *ppData += offset;
3363 return VK_SUCCESS;
3364 }
3365
3366 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3367 }
3368
3369 void radv_UnmapMemory(
3370 VkDevice _device,
3371 VkDeviceMemory _memory)
3372 {
3373 RADV_FROM_HANDLE(radv_device, device, _device);
3374 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3375
3376 if (mem == NULL)
3377 return;
3378
3379 if (mem->user_ptr == NULL)
3380 device->ws->buffer_unmap(mem->bo);
3381 }
3382
3383 VkResult radv_FlushMappedMemoryRanges(
3384 VkDevice _device,
3385 uint32_t memoryRangeCount,
3386 const VkMappedMemoryRange* pMemoryRanges)
3387 {
3388 return VK_SUCCESS;
3389 }
3390
3391 VkResult radv_InvalidateMappedMemoryRanges(
3392 VkDevice _device,
3393 uint32_t memoryRangeCount,
3394 const VkMappedMemoryRange* pMemoryRanges)
3395 {
3396 return VK_SUCCESS;
3397 }
3398
3399 void radv_GetBufferMemoryRequirements(
3400 VkDevice _device,
3401 VkBuffer _buffer,
3402 VkMemoryRequirements* pMemoryRequirements)
3403 {
3404 RADV_FROM_HANDLE(radv_device, device, _device);
3405 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3406
3407 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3408
3409 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3410 pMemoryRequirements->alignment = 4096;
3411 else
3412 pMemoryRequirements->alignment = 16;
3413
3414 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3415 }
3416
3417 void radv_GetBufferMemoryRequirements2(
3418 VkDevice device,
3419 const VkBufferMemoryRequirementsInfo2 *pInfo,
3420 VkMemoryRequirements2 *pMemoryRequirements)
3421 {
3422 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3423 &pMemoryRequirements->memoryRequirements);
3424 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3425 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3426 switch (ext->sType) {
3427 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3428 VkMemoryDedicatedRequirements *req =
3429 (VkMemoryDedicatedRequirements *) ext;
3430 req->requiresDedicatedAllocation = buffer->shareable;
3431 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3432 break;
3433 }
3434 default:
3435 break;
3436 }
3437 }
3438 }
3439
3440 void radv_GetImageMemoryRequirements(
3441 VkDevice _device,
3442 VkImage _image,
3443 VkMemoryRequirements* pMemoryRequirements)
3444 {
3445 RADV_FROM_HANDLE(radv_device, device, _device);
3446 RADV_FROM_HANDLE(radv_image, image, _image);
3447
3448 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3449
3450 pMemoryRequirements->size = image->size;
3451 pMemoryRequirements->alignment = image->alignment;
3452 }
3453
3454 void radv_GetImageMemoryRequirements2(
3455 VkDevice device,
3456 const VkImageMemoryRequirementsInfo2 *pInfo,
3457 VkMemoryRequirements2 *pMemoryRequirements)
3458 {
3459 radv_GetImageMemoryRequirements(device, pInfo->image,
3460 &pMemoryRequirements->memoryRequirements);
3461
3462 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3463
3464 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3465 switch (ext->sType) {
3466 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3467 VkMemoryDedicatedRequirements *req =
3468 (VkMemoryDedicatedRequirements *) ext;
3469 req->requiresDedicatedAllocation = image->shareable;
3470 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3471 break;
3472 }
3473 default:
3474 break;
3475 }
3476 }
3477 }
3478
3479 void radv_GetImageSparseMemoryRequirements(
3480 VkDevice device,
3481 VkImage image,
3482 uint32_t* pSparseMemoryRequirementCount,
3483 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3484 {
3485 stub();
3486 }
3487
3488 void radv_GetImageSparseMemoryRequirements2(
3489 VkDevice device,
3490 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3491 uint32_t* pSparseMemoryRequirementCount,
3492 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3493 {
3494 stub();
3495 }
3496
3497 void radv_GetDeviceMemoryCommitment(
3498 VkDevice device,
3499 VkDeviceMemory memory,
3500 VkDeviceSize* pCommittedMemoryInBytes)
3501 {
3502 *pCommittedMemoryInBytes = 0;
3503 }
3504
3505 VkResult radv_BindBufferMemory2(VkDevice device,
3506 uint32_t bindInfoCount,
3507 const VkBindBufferMemoryInfo *pBindInfos)
3508 {
3509 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3510 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3511 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3512
3513 if (mem) {
3514 buffer->bo = mem->bo;
3515 buffer->offset = pBindInfos[i].memoryOffset;
3516 } else {
3517 buffer->bo = NULL;
3518 }
3519 }
3520 return VK_SUCCESS;
3521 }
3522
3523 VkResult radv_BindBufferMemory(
3524 VkDevice device,
3525 VkBuffer buffer,
3526 VkDeviceMemory memory,
3527 VkDeviceSize memoryOffset)
3528 {
3529 const VkBindBufferMemoryInfo info = {
3530 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3531 .buffer = buffer,
3532 .memory = memory,
3533 .memoryOffset = memoryOffset
3534 };
3535
3536 return radv_BindBufferMemory2(device, 1, &info);
3537 }
3538
3539 VkResult radv_BindImageMemory2(VkDevice device,
3540 uint32_t bindInfoCount,
3541 const VkBindImageMemoryInfo *pBindInfos)
3542 {
3543 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3544 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3545 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3546
3547 if (mem) {
3548 image->bo = mem->bo;
3549 image->offset = pBindInfos[i].memoryOffset;
3550 } else {
3551 image->bo = NULL;
3552 image->offset = 0;
3553 }
3554 }
3555 return VK_SUCCESS;
3556 }
3557
3558
3559 VkResult radv_BindImageMemory(
3560 VkDevice device,
3561 VkImage image,
3562 VkDeviceMemory memory,
3563 VkDeviceSize memoryOffset)
3564 {
3565 const VkBindImageMemoryInfo info = {
3566 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3567 .image = image,
3568 .memory = memory,
3569 .memoryOffset = memoryOffset
3570 };
3571
3572 return radv_BindImageMemory2(device, 1, &info);
3573 }
3574
3575
3576 static void
3577 radv_sparse_buffer_bind_memory(struct radv_device *device,
3578 const VkSparseBufferMemoryBindInfo *bind)
3579 {
3580 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3581
3582 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3583 struct radv_device_memory *mem = NULL;
3584
3585 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3586 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3587
3588 device->ws->buffer_virtual_bind(buffer->bo,
3589 bind->pBinds[i].resourceOffset,
3590 bind->pBinds[i].size,
3591 mem ? mem->bo : NULL,
3592 bind->pBinds[i].memoryOffset);
3593 }
3594 }
3595
3596 static void
3597 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3598 const VkSparseImageOpaqueMemoryBindInfo *bind)
3599 {
3600 RADV_FROM_HANDLE(radv_image, image, bind->image);
3601
3602 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3603 struct radv_device_memory *mem = NULL;
3604
3605 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3606 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3607
3608 device->ws->buffer_virtual_bind(image->bo,
3609 bind->pBinds[i].resourceOffset,
3610 bind->pBinds[i].size,
3611 mem ? mem->bo : NULL,
3612 bind->pBinds[i].memoryOffset);
3613 }
3614 }
3615
3616 VkResult radv_QueueBindSparse(
3617 VkQueue _queue,
3618 uint32_t bindInfoCount,
3619 const VkBindSparseInfo* pBindInfo,
3620 VkFence _fence)
3621 {
3622 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3623 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3624 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3625 bool fence_emitted = false;
3626 VkResult result;
3627 int ret;
3628
3629 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3630 struct radv_winsys_sem_info sem_info;
3631 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3632 radv_sparse_buffer_bind_memory(queue->device,
3633 pBindInfo[i].pBufferBinds + j);
3634 }
3635
3636 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3637 radv_sparse_image_opaque_bind_memory(queue->device,
3638 pBindInfo[i].pImageOpaqueBinds + j);
3639 }
3640
3641 VkResult result;
3642 result = radv_alloc_sem_info(queue->device->instance,
3643 &sem_info,
3644 pBindInfo[i].waitSemaphoreCount,
3645 pBindInfo[i].pWaitSemaphores,
3646 pBindInfo[i].signalSemaphoreCount,
3647 pBindInfo[i].pSignalSemaphores,
3648 _fence);
3649 if (result != VK_SUCCESS)
3650 return result;
3651
3652 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3653 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3654 &queue->device->empty_cs[queue->queue_family_index],
3655 1, NULL, NULL,
3656 &sem_info, NULL,
3657 false, base_fence);
3658 if (ret) {
3659 radv_loge("failed to submit CS %d\n", i);
3660 abort();
3661 }
3662
3663 fence_emitted = true;
3664 }
3665
3666 radv_free_sem_info(&sem_info);
3667
3668 }
3669
3670 if (fence) {
3671 if (!fence_emitted) {
3672 result = radv_signal_fence(queue, fence);
3673 if (result != VK_SUCCESS)
3674 return result;
3675 }
3676 }
3677
3678 return VK_SUCCESS;
3679 }
3680
3681 VkResult radv_CreateFence(
3682 VkDevice _device,
3683 const VkFenceCreateInfo* pCreateInfo,
3684 const VkAllocationCallbacks* pAllocator,
3685 VkFence* pFence)
3686 {
3687 RADV_FROM_HANDLE(radv_device, device, _device);
3688 const VkExportFenceCreateInfo *export =
3689 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3690 VkExternalFenceHandleTypeFlags handleTypes =
3691 export ? export->handleTypes : 0;
3692
3693 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3694 sizeof(*fence), 8,
3695 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3696
3697 if (!fence)
3698 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3699
3700 fence->fence_wsi = NULL;
3701 fence->temp_syncobj = 0;
3702 if (device->always_use_syncobj || handleTypes) {
3703 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3704 if (ret) {
3705 vk_free2(&device->alloc, pAllocator, fence);
3706 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3707 }
3708 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3709 device->ws->signal_syncobj(device->ws, fence->syncobj);
3710 }
3711 fence->fence = NULL;
3712 } else {
3713 fence->fence = device->ws->create_fence();
3714 if (!fence->fence) {
3715 vk_free2(&device->alloc, pAllocator, fence);
3716 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3717 }
3718 fence->syncobj = 0;
3719 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3720 device->ws->signal_fence(fence->fence);
3721 }
3722
3723 *pFence = radv_fence_to_handle(fence);
3724
3725 return VK_SUCCESS;
3726 }
3727
3728 void radv_DestroyFence(
3729 VkDevice _device,
3730 VkFence _fence,
3731 const VkAllocationCallbacks* pAllocator)
3732 {
3733 RADV_FROM_HANDLE(radv_device, device, _device);
3734 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3735
3736 if (!fence)
3737 return;
3738
3739 if (fence->temp_syncobj)
3740 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3741 if (fence->syncobj)
3742 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3743 if (fence->fence)
3744 device->ws->destroy_fence(fence->fence);
3745 if (fence->fence_wsi)
3746 fence->fence_wsi->destroy(fence->fence_wsi);
3747 vk_free2(&device->alloc, pAllocator, fence);
3748 }
3749
3750
3751 uint64_t radv_get_current_time(void)
3752 {
3753 struct timespec tv;
3754 clock_gettime(CLOCK_MONOTONIC, &tv);
3755 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3756 }
3757
3758 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3759 {
3760 uint64_t current_time = radv_get_current_time();
3761
3762 timeout = MIN2(UINT64_MAX - current_time, timeout);
3763
3764 return current_time + timeout;
3765 }
3766
3767
3768 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3769 uint32_t fenceCount, const VkFence *pFences)
3770 {
3771 for (uint32_t i = 0; i < fenceCount; ++i) {
3772 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3773 if (fence->fence == NULL || fence->syncobj ||
3774 fence->temp_syncobj || fence->fence_wsi ||
3775 (!device->ws->is_fence_waitable(fence->fence)))
3776 return false;
3777 }
3778 return true;
3779 }
3780
3781 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3782 {
3783 for (uint32_t i = 0; i < fenceCount; ++i) {
3784 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3785 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3786 return false;
3787 }
3788 return true;
3789 }
3790
3791 VkResult radv_WaitForFences(
3792 VkDevice _device,
3793 uint32_t fenceCount,
3794 const VkFence* pFences,
3795 VkBool32 waitAll,
3796 uint64_t timeout)
3797 {
3798 RADV_FROM_HANDLE(radv_device, device, _device);
3799 timeout = radv_get_absolute_timeout(timeout);
3800
3801 if (device->always_use_syncobj &&
3802 radv_all_fences_syncobj(fenceCount, pFences))
3803 {
3804 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3805 if (!handles)
3806 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3807
3808 for (uint32_t i = 0; i < fenceCount; ++i) {
3809 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3810 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3811 }
3812
3813 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3814
3815 free(handles);
3816 return success ? VK_SUCCESS : VK_TIMEOUT;
3817 }
3818
3819 if (!waitAll && fenceCount > 1) {
3820 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3821 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3822 uint32_t wait_count = 0;
3823 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3824 if (!fences)
3825 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3826
3827 for (uint32_t i = 0; i < fenceCount; ++i) {
3828 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3829
3830 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3831 free(fences);
3832 return VK_SUCCESS;
3833 }
3834
3835 fences[wait_count++] = fence->fence;
3836 }
3837
3838 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3839 waitAll, timeout - radv_get_current_time());
3840
3841 free(fences);
3842 return success ? VK_SUCCESS : VK_TIMEOUT;
3843 }
3844
3845 while(radv_get_current_time() <= timeout) {
3846 for (uint32_t i = 0; i < fenceCount; ++i) {
3847 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3848 return VK_SUCCESS;
3849 }
3850 }
3851 return VK_TIMEOUT;
3852 }
3853
3854 for (uint32_t i = 0; i < fenceCount; ++i) {
3855 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3856 bool expired = false;
3857
3858 if (fence->temp_syncobj) {
3859 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3860 return VK_TIMEOUT;
3861 continue;
3862 }
3863
3864 if (fence->syncobj) {
3865 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3866 return VK_TIMEOUT;
3867 continue;
3868 }
3869
3870 if (fence->fence) {
3871 if (!device->ws->is_fence_waitable(fence->fence)) {
3872 while(!device->ws->is_fence_waitable(fence->fence) &&
3873 radv_get_current_time() <= timeout)
3874 /* Do nothing */;
3875 }
3876
3877 expired = device->ws->fence_wait(device->ws,
3878 fence->fence,
3879 true, timeout);
3880 if (!expired)
3881 return VK_TIMEOUT;
3882 }
3883
3884 if (fence->fence_wsi) {
3885 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3886 if (result != VK_SUCCESS)
3887 return result;
3888 }
3889 }
3890
3891 return VK_SUCCESS;
3892 }
3893
3894 VkResult radv_ResetFences(VkDevice _device,
3895 uint32_t fenceCount,
3896 const VkFence *pFences)
3897 {
3898 RADV_FROM_HANDLE(radv_device, device, _device);
3899
3900 for (unsigned i = 0; i < fenceCount; ++i) {
3901 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3902 if (fence->fence)
3903 device->ws->reset_fence(fence->fence);
3904
3905 /* Per spec, we first restore the permanent payload, and then reset, so
3906 * having a temp syncobj should not skip resetting the permanent syncobj. */
3907 if (fence->temp_syncobj) {
3908 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3909 fence->temp_syncobj = 0;
3910 }
3911
3912 if (fence->syncobj) {
3913 device->ws->reset_syncobj(device->ws, fence->syncobj);
3914 }
3915 }
3916
3917 return VK_SUCCESS;
3918 }
3919
3920 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3921 {
3922 RADV_FROM_HANDLE(radv_device, device, _device);
3923 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3924
3925 if (fence->temp_syncobj) {
3926 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3927 return success ? VK_SUCCESS : VK_NOT_READY;
3928 }
3929
3930 if (fence->syncobj) {
3931 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3932 return success ? VK_SUCCESS : VK_NOT_READY;
3933 }
3934
3935 if (fence->fence) {
3936 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3937 return VK_NOT_READY;
3938 }
3939 if (fence->fence_wsi) {
3940 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3941
3942 if (result != VK_SUCCESS) {
3943 if (result == VK_TIMEOUT)
3944 return VK_NOT_READY;
3945 return result;
3946 }
3947 }
3948 return VK_SUCCESS;
3949 }
3950
3951
3952 // Queue semaphore functions
3953
3954 VkResult radv_CreateSemaphore(
3955 VkDevice _device,
3956 const VkSemaphoreCreateInfo* pCreateInfo,
3957 const VkAllocationCallbacks* pAllocator,
3958 VkSemaphore* pSemaphore)
3959 {
3960 RADV_FROM_HANDLE(radv_device, device, _device);
3961 const VkExportSemaphoreCreateInfo *export =
3962 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3963 VkExternalSemaphoreHandleTypeFlags handleTypes =
3964 export ? export->handleTypes : 0;
3965
3966 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3967 sizeof(*sem), 8,
3968 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3969 if (!sem)
3970 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3971
3972 sem->temp_syncobj = 0;
3973 /* create a syncobject if we are going to export this semaphore */
3974 if (device->always_use_syncobj || handleTypes) {
3975 assert (device->physical_device->rad_info.has_syncobj);
3976 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3977 if (ret) {
3978 vk_free2(&device->alloc, pAllocator, sem);
3979 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3980 }
3981 sem->sem = NULL;
3982 } else {
3983 sem->sem = device->ws->create_sem(device->ws);
3984 if (!sem->sem) {
3985 vk_free2(&device->alloc, pAllocator, sem);
3986 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3987 }
3988 sem->syncobj = 0;
3989 }
3990
3991 *pSemaphore = radv_semaphore_to_handle(sem);
3992 return VK_SUCCESS;
3993 }
3994
3995 void radv_DestroySemaphore(
3996 VkDevice _device,
3997 VkSemaphore _semaphore,
3998 const VkAllocationCallbacks* pAllocator)
3999 {
4000 RADV_FROM_HANDLE(radv_device, device, _device);
4001 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4002 if (!_semaphore)
4003 return;
4004
4005 if (sem->syncobj)
4006 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4007 else
4008 device->ws->destroy_sem(sem->sem);
4009 vk_free2(&device->alloc, pAllocator, sem);
4010 }
4011
4012 VkResult radv_CreateEvent(
4013 VkDevice _device,
4014 const VkEventCreateInfo* pCreateInfo,
4015 const VkAllocationCallbacks* pAllocator,
4016 VkEvent* pEvent)
4017 {
4018 RADV_FROM_HANDLE(radv_device, device, _device);
4019 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4020 sizeof(*event), 8,
4021 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4022
4023 if (!event)
4024 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4025
4026 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4027 RADEON_DOMAIN_GTT,
4028 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4029 RADV_BO_PRIORITY_FENCE);
4030 if (!event->bo) {
4031 vk_free2(&device->alloc, pAllocator, event);
4032 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4033 }
4034
4035 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4036
4037 *pEvent = radv_event_to_handle(event);
4038
4039 return VK_SUCCESS;
4040 }
4041
4042 void radv_DestroyEvent(
4043 VkDevice _device,
4044 VkEvent _event,
4045 const VkAllocationCallbacks* pAllocator)
4046 {
4047 RADV_FROM_HANDLE(radv_device, device, _device);
4048 RADV_FROM_HANDLE(radv_event, event, _event);
4049
4050 if (!event)
4051 return;
4052 device->ws->buffer_destroy(event->bo);
4053 vk_free2(&device->alloc, pAllocator, event);
4054 }
4055
4056 VkResult radv_GetEventStatus(
4057 VkDevice _device,
4058 VkEvent _event)
4059 {
4060 RADV_FROM_HANDLE(radv_event, event, _event);
4061
4062 if (*event->map == 1)
4063 return VK_EVENT_SET;
4064 return VK_EVENT_RESET;
4065 }
4066
4067 VkResult radv_SetEvent(
4068 VkDevice _device,
4069 VkEvent _event)
4070 {
4071 RADV_FROM_HANDLE(radv_event, event, _event);
4072 *event->map = 1;
4073
4074 return VK_SUCCESS;
4075 }
4076
4077 VkResult radv_ResetEvent(
4078 VkDevice _device,
4079 VkEvent _event)
4080 {
4081 RADV_FROM_HANDLE(radv_event, event, _event);
4082 *event->map = 0;
4083
4084 return VK_SUCCESS;
4085 }
4086
4087 VkResult radv_CreateBuffer(
4088 VkDevice _device,
4089 const VkBufferCreateInfo* pCreateInfo,
4090 const VkAllocationCallbacks* pAllocator,
4091 VkBuffer* pBuffer)
4092 {
4093 RADV_FROM_HANDLE(radv_device, device, _device);
4094 struct radv_buffer *buffer;
4095
4096 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4097
4098 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4099 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4100 if (buffer == NULL)
4101 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4102
4103 buffer->size = pCreateInfo->size;
4104 buffer->usage = pCreateInfo->usage;
4105 buffer->bo = NULL;
4106 buffer->offset = 0;
4107 buffer->flags = pCreateInfo->flags;
4108
4109 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4110 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4111
4112 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4113 buffer->bo = device->ws->buffer_create(device->ws,
4114 align64(buffer->size, 4096),
4115 4096, 0, RADEON_FLAG_VIRTUAL,
4116 RADV_BO_PRIORITY_VIRTUAL);
4117 if (!buffer->bo) {
4118 vk_free2(&device->alloc, pAllocator, buffer);
4119 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4120 }
4121 }
4122
4123 *pBuffer = radv_buffer_to_handle(buffer);
4124
4125 return VK_SUCCESS;
4126 }
4127
4128 void radv_DestroyBuffer(
4129 VkDevice _device,
4130 VkBuffer _buffer,
4131 const VkAllocationCallbacks* pAllocator)
4132 {
4133 RADV_FROM_HANDLE(radv_device, device, _device);
4134 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4135
4136 if (!buffer)
4137 return;
4138
4139 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4140 device->ws->buffer_destroy(buffer->bo);
4141
4142 vk_free2(&device->alloc, pAllocator, buffer);
4143 }
4144
4145 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4146 VkDevice device,
4147 const VkBufferDeviceAddressInfoEXT* pInfo)
4148 {
4149 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4150 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4151 }
4152
4153
4154 static inline unsigned
4155 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4156 {
4157 if (stencil)
4158 return plane->surface.u.legacy.stencil_tiling_index[level];
4159 else
4160 return plane->surface.u.legacy.tiling_index[level];
4161 }
4162
4163 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4164 {
4165 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4166 }
4167
4168 static uint32_t
4169 radv_init_dcc_control_reg(struct radv_device *device,
4170 struct radv_image_view *iview)
4171 {
4172 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4173 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4174 unsigned max_compressed_block_size;
4175 unsigned independent_64b_blocks;
4176
4177 if (!radv_image_has_dcc(iview->image))
4178 return 0;
4179
4180 if (iview->image->info.samples > 1) {
4181 if (iview->image->planes[0].surface.bpe == 1)
4182 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4183 else if (iview->image->planes[0].surface.bpe == 2)
4184 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4185 }
4186
4187 if (!device->physical_device->rad_info.has_dedicated_vram) {
4188 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4189 * dGPU and 64 for APU because all of our APUs to date use
4190 * DIMMs which have a request granularity size of 64B while all
4191 * other chips have a 32B request size.
4192 */
4193 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4194 }
4195
4196 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4197 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4198 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4199 /* If this DCC image is potentially going to be used in texture
4200 * fetches, we need some special settings.
4201 */
4202 independent_64b_blocks = 1;
4203 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4204 } else {
4205 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4206 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4207 * big as possible for better compression state.
4208 */
4209 independent_64b_blocks = 0;
4210 max_compressed_block_size = max_uncompressed_block_size;
4211 }
4212
4213 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4214 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4215 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4216 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4217 }
4218
4219 static void
4220 radv_initialise_color_surface(struct radv_device *device,
4221 struct radv_color_buffer_info *cb,
4222 struct radv_image_view *iview)
4223 {
4224 const struct vk_format_description *desc;
4225 unsigned ntype, format, swap, endian;
4226 unsigned blend_clamp = 0, blend_bypass = 0;
4227 uint64_t va;
4228 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4229 const struct radeon_surf *surf = &plane->surface;
4230
4231 desc = vk_format_description(iview->vk_format);
4232
4233 memset(cb, 0, sizeof(*cb));
4234
4235 /* Intensity is implemented as Red, so treat it that way. */
4236 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4237
4238 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4239
4240 cb->cb_color_base = va >> 8;
4241
4242 if (device->physical_device->rad_info.chip_class >= GFX9) {
4243 struct gfx9_surf_meta_flags meta;
4244 if (iview->image->dcc_offset)
4245 meta = surf->u.gfx9.dcc;
4246 else
4247 meta = surf->u.gfx9.cmask;
4248
4249 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4250 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4251 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4252 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4253
4254 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4255 cb->cb_color_base |= surf->tile_swizzle;
4256
4257 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4258 } else {
4259 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4260 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4261
4262 cb->cb_color_base += level_info->offset >> 8;
4263 if (level_info->mode == RADEON_SURF_MODE_2D)
4264 cb->cb_color_base |= surf->tile_swizzle;
4265
4266 pitch_tile_max = level_info->nblk_x / 8 - 1;
4267 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4268 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4269
4270 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4271 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4272 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4273
4274 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4275
4276 if (radv_image_has_fmask(iview->image)) {
4277 if (device->physical_device->rad_info.chip_class >= GFX7)
4278 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4279 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4280 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4281 } else {
4282 /* This must be set for fast clear to work without FMASK. */
4283 if (device->physical_device->rad_info.chip_class >= GFX7)
4284 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4285 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4286 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4287 }
4288 }
4289
4290 /* CMASK variables */
4291 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4292 va += iview->image->cmask.offset;
4293 cb->cb_color_cmask = va >> 8;
4294
4295 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4296 va += iview->image->dcc_offset;
4297 cb->cb_dcc_base = va >> 8;
4298 cb->cb_dcc_base |= surf->tile_swizzle;
4299
4300 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4301 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4302 S_028C6C_SLICE_MAX(max_slice);
4303
4304 if (iview->image->info.samples > 1) {
4305 unsigned log_samples = util_logbase2(iview->image->info.samples);
4306
4307 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4308 S_028C74_NUM_FRAGMENTS(log_samples);
4309 }
4310
4311 if (radv_image_has_fmask(iview->image)) {
4312 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4313 cb->cb_color_fmask = va >> 8;
4314 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4315 } else {
4316 cb->cb_color_fmask = cb->cb_color_base;
4317 }
4318
4319 ntype = radv_translate_color_numformat(iview->vk_format,
4320 desc,
4321 vk_format_get_first_non_void_channel(iview->vk_format));
4322 format = radv_translate_colorformat(iview->vk_format);
4323 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4324 radv_finishme("Illegal color\n");
4325 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4326 endian = radv_colorformat_endian_swap(format);
4327
4328 /* blend clamp should be set for all NORM/SRGB types */
4329 if (ntype == V_028C70_NUMBER_UNORM ||
4330 ntype == V_028C70_NUMBER_SNORM ||
4331 ntype == V_028C70_NUMBER_SRGB)
4332 blend_clamp = 1;
4333
4334 /* set blend bypass according to docs if SINT/UINT or
4335 8/24 COLOR variants */
4336 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4337 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4338 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4339 blend_clamp = 0;
4340 blend_bypass = 1;
4341 }
4342 #if 0
4343 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4344 (format == V_028C70_COLOR_8 ||
4345 format == V_028C70_COLOR_8_8 ||
4346 format == V_028C70_COLOR_8_8_8_8))
4347 ->color_is_int8 = true;
4348 #endif
4349 cb->cb_color_info = S_028C70_FORMAT(format) |
4350 S_028C70_COMP_SWAP(swap) |
4351 S_028C70_BLEND_CLAMP(blend_clamp) |
4352 S_028C70_BLEND_BYPASS(blend_bypass) |
4353 S_028C70_SIMPLE_FLOAT(1) |
4354 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4355 ntype != V_028C70_NUMBER_SNORM &&
4356 ntype != V_028C70_NUMBER_SRGB &&
4357 format != V_028C70_COLOR_8_24 &&
4358 format != V_028C70_COLOR_24_8) |
4359 S_028C70_NUMBER_TYPE(ntype) |
4360 S_028C70_ENDIAN(endian);
4361 if (radv_image_has_fmask(iview->image)) {
4362 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4363 if (device->physical_device->rad_info.chip_class == GFX6) {
4364 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4365 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4366 }
4367 }
4368
4369 if (radv_image_has_cmask(iview->image) &&
4370 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4371 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4372
4373 if (radv_dcc_enabled(iview->image, iview->base_mip))
4374 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4375
4376 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4377
4378 /* This must be set for fast clear to work without FMASK. */
4379 if (!radv_image_has_fmask(iview->image) &&
4380 device->physical_device->rad_info.chip_class == GFX6) {
4381 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4382 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4383 }
4384
4385 if (device->physical_device->rad_info.chip_class >= GFX9) {
4386 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4387
4388 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4389 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4390 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4391 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4392
4393 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4394 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4395 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4396 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4397 S_028C68_MIP0_HEIGHT(height - 1) |
4398 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4399 }
4400 }
4401
4402 static unsigned
4403 radv_calc_decompress_on_z_planes(struct radv_device *device,
4404 struct radv_image_view *iview)
4405 {
4406 unsigned max_zplanes = 0;
4407
4408 assert(radv_image_is_tc_compat_htile(iview->image));
4409
4410 if (device->physical_device->rad_info.chip_class >= GFX9) {
4411 /* Default value for 32-bit depth surfaces. */
4412 max_zplanes = 4;
4413
4414 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4415 iview->image->info.samples > 1)
4416 max_zplanes = 2;
4417
4418 max_zplanes = max_zplanes + 1;
4419 } else {
4420 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4421 /* Do not enable Z plane compression for 16-bit depth
4422 * surfaces because isn't supported on GFX8. Only
4423 * 32-bit depth surfaces are supported by the hardware.
4424 * This allows to maintain shader compatibility and to
4425 * reduce the number of depth decompressions.
4426 */
4427 max_zplanes = 1;
4428 } else {
4429 if (iview->image->info.samples <= 1)
4430 max_zplanes = 5;
4431 else if (iview->image->info.samples <= 4)
4432 max_zplanes = 3;
4433 else
4434 max_zplanes = 2;
4435 }
4436 }
4437
4438 return max_zplanes;
4439 }
4440
4441 static void
4442 radv_initialise_ds_surface(struct radv_device *device,
4443 struct radv_ds_buffer_info *ds,
4444 struct radv_image_view *iview)
4445 {
4446 unsigned level = iview->base_mip;
4447 unsigned format, stencil_format;
4448 uint64_t va, s_offs, z_offs;
4449 bool stencil_only = false;
4450 const struct radv_image_plane *plane = &iview->image->planes[0];
4451 const struct radeon_surf *surf = &plane->surface;
4452
4453 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4454
4455 memset(ds, 0, sizeof(*ds));
4456 switch (iview->image->vk_format) {
4457 case VK_FORMAT_D24_UNORM_S8_UINT:
4458 case VK_FORMAT_X8_D24_UNORM_PACK32:
4459 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4460 ds->offset_scale = 2.0f;
4461 break;
4462 case VK_FORMAT_D16_UNORM:
4463 case VK_FORMAT_D16_UNORM_S8_UINT:
4464 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4465 ds->offset_scale = 4.0f;
4466 break;
4467 case VK_FORMAT_D32_SFLOAT:
4468 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4469 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4470 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4471 ds->offset_scale = 1.0f;
4472 break;
4473 case VK_FORMAT_S8_UINT:
4474 stencil_only = true;
4475 break;
4476 default:
4477 break;
4478 }
4479
4480 format = radv_translate_dbformat(iview->image->vk_format);
4481 stencil_format = surf->has_stencil ?
4482 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4483
4484 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4485 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4486 S_028008_SLICE_MAX(max_slice);
4487
4488 ds->db_htile_data_base = 0;
4489 ds->db_htile_surface = 0;
4490
4491 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4492 s_offs = z_offs = va;
4493
4494 if (device->physical_device->rad_info.chip_class >= GFX9) {
4495 assert(surf->u.gfx9.surf_offset == 0);
4496 s_offs += surf->u.gfx9.stencil_offset;
4497
4498 ds->db_z_info = S_028038_FORMAT(format) |
4499 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4500 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4501 S_028038_MAXMIP(iview->image->info.levels - 1) |
4502 S_028038_ZRANGE_PRECISION(1);
4503 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4504 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4505
4506 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4507 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4508 ds->db_depth_view |= S_028008_MIPID(level);
4509
4510 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4511 S_02801C_Y_MAX(iview->image->info.height - 1);
4512
4513 if (radv_htile_enabled(iview->image, level)) {
4514 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4515
4516 if (radv_image_is_tc_compat_htile(iview->image)) {
4517 unsigned max_zplanes =
4518 radv_calc_decompress_on_z_planes(device, iview);
4519
4520 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4521 S_028038_ITERATE_FLUSH(1);
4522 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4523 }
4524
4525 if (!surf->has_stencil)
4526 /* Use all of the htile_buffer for depth if there's no stencil. */
4527 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4528 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4529 iview->image->htile_offset;
4530 ds->db_htile_data_base = va >> 8;
4531 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4532 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4533 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4534 }
4535 } else {
4536 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4537
4538 if (stencil_only)
4539 level_info = &surf->u.legacy.stencil_level[level];
4540
4541 z_offs += surf->u.legacy.level[level].offset;
4542 s_offs += surf->u.legacy.stencil_level[level].offset;
4543
4544 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4545 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4546 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4547
4548 if (iview->image->info.samples > 1)
4549 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4550
4551 if (device->physical_device->rad_info.chip_class >= GFX7) {
4552 struct radeon_info *info = &device->physical_device->rad_info;
4553 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4554 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4555 unsigned macro_index = surf->u.legacy.macro_tile_index;
4556 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4557 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4558 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4559
4560 if (stencil_only)
4561 tile_mode = stencil_tile_mode;
4562
4563 ds->db_depth_info |=
4564 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4565 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4566 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4567 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4568 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4569 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4570 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4571 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4572 } else {
4573 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4574 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4575 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4576 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4577 if (stencil_only)
4578 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4579 }
4580
4581 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4582 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4583 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4584
4585 if (radv_htile_enabled(iview->image, level)) {
4586 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4587
4588 if (!surf->has_stencil &&
4589 !radv_image_is_tc_compat_htile(iview->image))
4590 /* Use all of the htile_buffer for depth if there's no stencil. */
4591 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4592
4593 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4594 iview->image->htile_offset;
4595 ds->db_htile_data_base = va >> 8;
4596 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4597
4598 if (radv_image_is_tc_compat_htile(iview->image)) {
4599 unsigned max_zplanes =
4600 radv_calc_decompress_on_z_planes(device, iview);
4601
4602 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4603 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4604 }
4605 }
4606 }
4607
4608 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4609 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4610 }
4611
4612 VkResult radv_CreateFramebuffer(
4613 VkDevice _device,
4614 const VkFramebufferCreateInfo* pCreateInfo,
4615 const VkAllocationCallbacks* pAllocator,
4616 VkFramebuffer* pFramebuffer)
4617 {
4618 RADV_FROM_HANDLE(radv_device, device, _device);
4619 struct radv_framebuffer *framebuffer;
4620
4621 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4622
4623 size_t size = sizeof(*framebuffer) +
4624 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4625 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4626 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4627 if (framebuffer == NULL)
4628 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4629
4630 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4631 framebuffer->width = pCreateInfo->width;
4632 framebuffer->height = pCreateInfo->height;
4633 framebuffer->layers = pCreateInfo->layers;
4634 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4635 VkImageView _iview = pCreateInfo->pAttachments[i];
4636 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4637 framebuffer->attachments[i].attachment = iview;
4638 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4639 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4640 } else {
4641 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4642 }
4643 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4644 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4645 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4646 }
4647
4648 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4649 return VK_SUCCESS;
4650 }
4651
4652 void radv_DestroyFramebuffer(
4653 VkDevice _device,
4654 VkFramebuffer _fb,
4655 const VkAllocationCallbacks* pAllocator)
4656 {
4657 RADV_FROM_HANDLE(radv_device, device, _device);
4658 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4659
4660 if (!fb)
4661 return;
4662 vk_free2(&device->alloc, pAllocator, fb);
4663 }
4664
4665 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4666 {
4667 switch (address_mode) {
4668 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4669 return V_008F30_SQ_TEX_WRAP;
4670 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4671 return V_008F30_SQ_TEX_MIRROR;
4672 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4673 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4674 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4675 return V_008F30_SQ_TEX_CLAMP_BORDER;
4676 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4677 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4678 default:
4679 unreachable("illegal tex wrap mode");
4680 break;
4681 }
4682 }
4683
4684 static unsigned
4685 radv_tex_compare(VkCompareOp op)
4686 {
4687 switch (op) {
4688 case VK_COMPARE_OP_NEVER:
4689 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4690 case VK_COMPARE_OP_LESS:
4691 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4692 case VK_COMPARE_OP_EQUAL:
4693 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4694 case VK_COMPARE_OP_LESS_OR_EQUAL:
4695 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4696 case VK_COMPARE_OP_GREATER:
4697 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4698 case VK_COMPARE_OP_NOT_EQUAL:
4699 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4700 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4701 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4702 case VK_COMPARE_OP_ALWAYS:
4703 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4704 default:
4705 unreachable("illegal compare mode");
4706 break;
4707 }
4708 }
4709
4710 static unsigned
4711 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4712 {
4713 switch (filter) {
4714 case VK_FILTER_NEAREST:
4715 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4716 V_008F38_SQ_TEX_XY_FILTER_POINT);
4717 case VK_FILTER_LINEAR:
4718 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4719 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4720 case VK_FILTER_CUBIC_IMG:
4721 default:
4722 fprintf(stderr, "illegal texture filter");
4723 return 0;
4724 }
4725 }
4726
4727 static unsigned
4728 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4729 {
4730 switch (mode) {
4731 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4732 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4733 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4734 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4735 default:
4736 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4737 }
4738 }
4739
4740 static unsigned
4741 radv_tex_bordercolor(VkBorderColor bcolor)
4742 {
4743 switch (bcolor) {
4744 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4745 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4746 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4747 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4748 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4749 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4750 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4751 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4752 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4753 default:
4754 break;
4755 }
4756 return 0;
4757 }
4758
4759 static unsigned
4760 radv_tex_aniso_filter(unsigned filter)
4761 {
4762 if (filter < 2)
4763 return 0;
4764 if (filter < 4)
4765 return 1;
4766 if (filter < 8)
4767 return 2;
4768 if (filter < 16)
4769 return 3;
4770 return 4;
4771 }
4772
4773 static unsigned
4774 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4775 {
4776 switch (mode) {
4777 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4778 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4779 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4780 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4781 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4782 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4783 default:
4784 break;
4785 }
4786 return 0;
4787 }
4788
4789 static uint32_t
4790 radv_get_max_anisotropy(struct radv_device *device,
4791 const VkSamplerCreateInfo *pCreateInfo)
4792 {
4793 if (device->force_aniso >= 0)
4794 return device->force_aniso;
4795
4796 if (pCreateInfo->anisotropyEnable &&
4797 pCreateInfo->maxAnisotropy > 1.0f)
4798 return (uint32_t)pCreateInfo->maxAnisotropy;
4799
4800 return 0;
4801 }
4802
4803 static void
4804 radv_init_sampler(struct radv_device *device,
4805 struct radv_sampler *sampler,
4806 const VkSamplerCreateInfo *pCreateInfo)
4807 {
4808 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4809 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4810 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4811 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4812
4813 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4814 vk_find_struct_const(pCreateInfo->pNext,
4815 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4816 if (sampler_reduction)
4817 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4818
4819 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4820 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4821 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4822 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4823 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4824 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4825 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4826 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4827 S_008F30_DISABLE_CUBE_WRAP(0) |
4828 S_008F30_COMPAT_MODE(is_vi) |
4829 S_008F30_FILTER_MODE(filter_mode));
4830 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4831 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4832 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4833 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4834 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4835 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4836 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4837 S_008F38_MIP_POINT_PRECLAMP(0) |
4838 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4839 S_008F38_FILTER_PREC_FIX(1) |
4840 S_008F38_ANISO_OVERRIDE(is_vi));
4841 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4842 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4843 }
4844
4845 VkResult radv_CreateSampler(
4846 VkDevice _device,
4847 const VkSamplerCreateInfo* pCreateInfo,
4848 const VkAllocationCallbacks* pAllocator,
4849 VkSampler* pSampler)
4850 {
4851 RADV_FROM_HANDLE(radv_device, device, _device);
4852 struct radv_sampler *sampler;
4853
4854 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4855 vk_find_struct_const(pCreateInfo->pNext,
4856 SAMPLER_YCBCR_CONVERSION_INFO);
4857
4858 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4859
4860 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4861 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4862 if (!sampler)
4863 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4864
4865 radv_init_sampler(device, sampler, pCreateInfo);
4866
4867 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4868 *pSampler = radv_sampler_to_handle(sampler);
4869
4870 return VK_SUCCESS;
4871 }
4872
4873 void radv_DestroySampler(
4874 VkDevice _device,
4875 VkSampler _sampler,
4876 const VkAllocationCallbacks* pAllocator)
4877 {
4878 RADV_FROM_HANDLE(radv_device, device, _device);
4879 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4880
4881 if (!sampler)
4882 return;
4883 vk_free2(&device->alloc, pAllocator, sampler);
4884 }
4885
4886 /* vk_icd.h does not declare this function, so we declare it here to
4887 * suppress Wmissing-prototypes.
4888 */
4889 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4890 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4891
4892 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4893 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4894 {
4895 /* For the full details on loader interface versioning, see
4896 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4897 * What follows is a condensed summary, to help you navigate the large and
4898 * confusing official doc.
4899 *
4900 * - Loader interface v0 is incompatible with later versions. We don't
4901 * support it.
4902 *
4903 * - In loader interface v1:
4904 * - The first ICD entrypoint called by the loader is
4905 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4906 * entrypoint.
4907 * - The ICD must statically expose no other Vulkan symbol unless it is
4908 * linked with -Bsymbolic.
4909 * - Each dispatchable Vulkan handle created by the ICD must be
4910 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4911 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4912 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4913 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4914 * such loader-managed surfaces.
4915 *
4916 * - Loader interface v2 differs from v1 in:
4917 * - The first ICD entrypoint called by the loader is
4918 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4919 * statically expose this entrypoint.
4920 *
4921 * - Loader interface v3 differs from v2 in:
4922 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4923 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4924 * because the loader no longer does so.
4925 */
4926 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
4927 return VK_SUCCESS;
4928 }
4929
4930 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4931 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4932 int *pFD)
4933 {
4934 RADV_FROM_HANDLE(radv_device, device, _device);
4935 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4936
4937 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4938
4939 /* At the moment, we support only the below handle types. */
4940 assert(pGetFdInfo->handleType ==
4941 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4942 pGetFdInfo->handleType ==
4943 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4944
4945 bool ret = radv_get_memory_fd(device, memory, pFD);
4946 if (ret == false)
4947 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4948 return VK_SUCCESS;
4949 }
4950
4951 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4952 VkExternalMemoryHandleTypeFlagBits handleType,
4953 int fd,
4954 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4955 {
4956 RADV_FROM_HANDLE(radv_device, device, _device);
4957
4958 switch (handleType) {
4959 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4960 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4961 return VK_SUCCESS;
4962
4963 default:
4964 /* The valid usage section for this function says:
4965 *
4966 * "handleType must not be one of the handle types defined as
4967 * opaque."
4968 *
4969 * So opaque handle types fall into the default "unsupported" case.
4970 */
4971 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4972 }
4973 }
4974
4975 static VkResult radv_import_opaque_fd(struct radv_device *device,
4976 int fd,
4977 uint32_t *syncobj)
4978 {
4979 uint32_t syncobj_handle = 0;
4980 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4981 if (ret != 0)
4982 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4983
4984 if (*syncobj)
4985 device->ws->destroy_syncobj(device->ws, *syncobj);
4986
4987 *syncobj = syncobj_handle;
4988 close(fd);
4989
4990 return VK_SUCCESS;
4991 }
4992
4993 static VkResult radv_import_sync_fd(struct radv_device *device,
4994 int fd,
4995 uint32_t *syncobj)
4996 {
4997 /* If we create a syncobj we do it locally so that if we have an error, we don't
4998 * leave a syncobj in an undetermined state in the fence. */
4999 uint32_t syncobj_handle = *syncobj;
5000 if (!syncobj_handle) {
5001 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5002 if (ret) {
5003 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5004 }
5005 }
5006
5007 if (fd == -1) {
5008 device->ws->signal_syncobj(device->ws, syncobj_handle);
5009 } else {
5010 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5011 if (ret != 0)
5012 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5013 }
5014
5015 *syncobj = syncobj_handle;
5016 if (fd != -1)
5017 close(fd);
5018
5019 return VK_SUCCESS;
5020 }
5021
5022 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5023 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5024 {
5025 RADV_FROM_HANDLE(radv_device, device, _device);
5026 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5027 uint32_t *syncobj_dst = NULL;
5028
5029 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5030 syncobj_dst = &sem->temp_syncobj;
5031 } else {
5032 syncobj_dst = &sem->syncobj;
5033 }
5034
5035 switch(pImportSemaphoreFdInfo->handleType) {
5036 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5037 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5038 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5039 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5040 default:
5041 unreachable("Unhandled semaphore handle type");
5042 }
5043 }
5044
5045 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5046 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5047 int *pFd)
5048 {
5049 RADV_FROM_HANDLE(radv_device, device, _device);
5050 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5051 int ret;
5052 uint32_t syncobj_handle;
5053
5054 if (sem->temp_syncobj)
5055 syncobj_handle = sem->temp_syncobj;
5056 else
5057 syncobj_handle = sem->syncobj;
5058
5059 switch(pGetFdInfo->handleType) {
5060 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5061 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5062 break;
5063 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5064 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5065 if (!ret) {
5066 if (sem->temp_syncobj) {
5067 close (sem->temp_syncobj);
5068 sem->temp_syncobj = 0;
5069 } else {
5070 device->ws->reset_syncobj(device->ws, syncobj_handle);
5071 }
5072 }
5073 break;
5074 default:
5075 unreachable("Unhandled semaphore handle type");
5076 }
5077
5078 if (ret)
5079 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5080 return VK_SUCCESS;
5081 }
5082
5083 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5084 VkPhysicalDevice physicalDevice,
5085 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5086 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5087 {
5088 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5089
5090 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5091 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5092 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5093 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5094 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5095 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5096 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5097 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5098 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5099 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5100 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5101 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5102 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5103 } else {
5104 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5105 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5106 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5107 }
5108 }
5109
5110 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5111 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5112 {
5113 RADV_FROM_HANDLE(radv_device, device, _device);
5114 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5115 uint32_t *syncobj_dst = NULL;
5116
5117
5118 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5119 syncobj_dst = &fence->temp_syncobj;
5120 } else {
5121 syncobj_dst = &fence->syncobj;
5122 }
5123
5124 switch(pImportFenceFdInfo->handleType) {
5125 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5126 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5127 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5128 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5129 default:
5130 unreachable("Unhandled fence handle type");
5131 }
5132 }
5133
5134 VkResult radv_GetFenceFdKHR(VkDevice _device,
5135 const VkFenceGetFdInfoKHR *pGetFdInfo,
5136 int *pFd)
5137 {
5138 RADV_FROM_HANDLE(radv_device, device, _device);
5139 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5140 int ret;
5141 uint32_t syncobj_handle;
5142
5143 if (fence->temp_syncobj)
5144 syncobj_handle = fence->temp_syncobj;
5145 else
5146 syncobj_handle = fence->syncobj;
5147
5148 switch(pGetFdInfo->handleType) {
5149 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5150 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5151 break;
5152 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5153 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5154 if (!ret) {
5155 if (fence->temp_syncobj) {
5156 close (fence->temp_syncobj);
5157 fence->temp_syncobj = 0;
5158 } else {
5159 device->ws->reset_syncobj(device->ws, syncobj_handle);
5160 }
5161 }
5162 break;
5163 default:
5164 unreachable("Unhandled fence handle type");
5165 }
5166
5167 if (ret)
5168 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5169 return VK_SUCCESS;
5170 }
5171
5172 void radv_GetPhysicalDeviceExternalFenceProperties(
5173 VkPhysicalDevice physicalDevice,
5174 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5175 VkExternalFenceProperties *pExternalFenceProperties)
5176 {
5177 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5178
5179 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5180 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5181 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5182 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5183 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5184 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5185 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5186 } else {
5187 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5188 pExternalFenceProperties->compatibleHandleTypes = 0;
5189 pExternalFenceProperties->externalFenceFeatures = 0;
5190 }
5191 }
5192
5193 VkResult
5194 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5195 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5196 const VkAllocationCallbacks* pAllocator,
5197 VkDebugReportCallbackEXT* pCallback)
5198 {
5199 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5200 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5201 pCreateInfo, pAllocator, &instance->alloc,
5202 pCallback);
5203 }
5204
5205 void
5206 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5207 VkDebugReportCallbackEXT _callback,
5208 const VkAllocationCallbacks* pAllocator)
5209 {
5210 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5211 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5212 _callback, pAllocator, &instance->alloc);
5213 }
5214
5215 void
5216 radv_DebugReportMessageEXT(VkInstance _instance,
5217 VkDebugReportFlagsEXT flags,
5218 VkDebugReportObjectTypeEXT objectType,
5219 uint64_t object,
5220 size_t location,
5221 int32_t messageCode,
5222 const char* pLayerPrefix,
5223 const char* pMessage)
5224 {
5225 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5226 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5227 object, location, messageCode, pLayerPrefix, pMessage);
5228 }
5229
5230 void
5231 radv_GetDeviceGroupPeerMemoryFeatures(
5232 VkDevice device,
5233 uint32_t heapIndex,
5234 uint32_t localDeviceIndex,
5235 uint32_t remoteDeviceIndex,
5236 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5237 {
5238 assert(localDeviceIndex == remoteDeviceIndex);
5239
5240 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5241 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5242 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5243 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5244 }
5245
5246 static const VkTimeDomainEXT radv_time_domains[] = {
5247 VK_TIME_DOMAIN_DEVICE_EXT,
5248 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5249 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5250 };
5251
5252 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5253 VkPhysicalDevice physicalDevice,
5254 uint32_t *pTimeDomainCount,
5255 VkTimeDomainEXT *pTimeDomains)
5256 {
5257 int d;
5258 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5259
5260 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5261 vk_outarray_append(&out, i) {
5262 *i = radv_time_domains[d];
5263 }
5264 }
5265
5266 return vk_outarray_status(&out);
5267 }
5268
5269 static uint64_t
5270 radv_clock_gettime(clockid_t clock_id)
5271 {
5272 struct timespec current;
5273 int ret;
5274
5275 ret = clock_gettime(clock_id, &current);
5276 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5277 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5278 if (ret < 0)
5279 return 0;
5280
5281 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5282 }
5283
5284 VkResult radv_GetCalibratedTimestampsEXT(
5285 VkDevice _device,
5286 uint32_t timestampCount,
5287 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5288 uint64_t *pTimestamps,
5289 uint64_t *pMaxDeviation)
5290 {
5291 RADV_FROM_HANDLE(radv_device, device, _device);
5292 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5293 int d;
5294 uint64_t begin, end;
5295 uint64_t max_clock_period = 0;
5296
5297 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5298
5299 for (d = 0; d < timestampCount; d++) {
5300 switch (pTimestampInfos[d].timeDomain) {
5301 case VK_TIME_DOMAIN_DEVICE_EXT:
5302 pTimestamps[d] = device->ws->query_value(device->ws,
5303 RADEON_TIMESTAMP);
5304 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5305 max_clock_period = MAX2(max_clock_period, device_period);
5306 break;
5307 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5308 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5309 max_clock_period = MAX2(max_clock_period, 1);
5310 break;
5311
5312 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5313 pTimestamps[d] = begin;
5314 break;
5315 default:
5316 pTimestamps[d] = 0;
5317 break;
5318 }
5319 }
5320
5321 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5322
5323 /*
5324 * The maximum deviation is the sum of the interval over which we
5325 * perform the sampling and the maximum period of any sampled
5326 * clock. That's because the maximum skew between any two sampled
5327 * clock edges is when the sampled clock with the largest period is
5328 * sampled at the end of that period but right at the beginning of the
5329 * sampling interval and some other clock is sampled right at the
5330 * begining of its sampling period and right at the end of the
5331 * sampling interval. Let's assume the GPU has the longest clock
5332 * period and that the application is sampling GPU and monotonic:
5333 *
5334 * s e
5335 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5336 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5337 *
5338 * g
5339 * 0 1 2 3
5340 * GPU -----_____-----_____-----_____-----_____
5341 *
5342 * m
5343 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5344 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5345 *
5346 * Interval <----------------->
5347 * Deviation <-------------------------->
5348 *
5349 * s = read(raw) 2
5350 * g = read(GPU) 1
5351 * m = read(monotonic) 2
5352 * e = read(raw) b
5353 *
5354 * We round the sample interval up by one tick to cover sampling error
5355 * in the interval clock
5356 */
5357
5358 uint64_t sample_interval = end - begin + 1;
5359
5360 *pMaxDeviation = sample_interval + max_clock_period;
5361
5362 return VK_SUCCESS;
5363 }