2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 /* TODO: Implement layout transitions with variable sample locations
80 * before enabling HTILE for depth/stencil images created with this
81 * flags because the depth decompress pass needs to know them.
83 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT
)
86 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
89 if (pCreateInfo
->mipLevels
> 1)
92 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
93 * tests - disable for now */
94 if (pCreateInfo
->samples
>= 2 &&
95 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
98 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
99 * supports 32-bit. Though, it's possible to enable TC-compat for
100 * 16-bit depth surfaces if no Z planes are compressed.
102 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
103 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
104 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
107 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
108 const struct VkImageFormatListCreateInfoKHR
*format_list
=
109 (const struct VkImageFormatListCreateInfoKHR
*)
110 vk_find_struct_const(pCreateInfo
->pNext
,
111 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
113 /* We have to ignore the existence of the list if viewFormatCount = 0 */
114 if (format_list
&& format_list
->viewFormatCount
) {
115 /* compatibility is transitive, so we only need to check
116 * one format with everything else.
118 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
119 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
131 radv_use_dcc_for_image(struct radv_device
*device
,
132 const struct radv_image
*image
,
133 const struct radv_image_create_info
*create_info
,
134 const VkImageCreateInfo
*pCreateInfo
)
136 bool dcc_compatible_formats
;
139 /* DCC (Delta Color Compression) is only available for GFX8+. */
140 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
143 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
146 /* FIXME: DCC is broken for shareable images starting with GFX9 */
147 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
151 /* TODO: Enable DCC for storage images. */
152 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
153 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
156 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
159 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
160 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
163 /* TODO: Enable DCC for mipmaps and array layers. */
164 if (pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1)
167 if (create_info
->scanout
)
170 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
171 * 2x can be enabled with an option.
173 if (pCreateInfo
->samples
> 2 ||
174 (pCreateInfo
->samples
== 2 &&
175 !device
->physical_device
->dcc_msaa_allowed
))
178 /* Determine if the formats are DCC compatible. */
179 dcc_compatible_formats
=
180 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
183 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
184 const struct VkImageFormatListCreateInfoKHR
*format_list
=
185 (const struct VkImageFormatListCreateInfoKHR
*)
186 vk_find_struct_const(pCreateInfo
->pNext
,
187 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
189 /* We have to ignore the existence of the list if viewFormatCount = 0 */
190 if (format_list
&& format_list
->viewFormatCount
) {
191 /* compatibility is transitive, so we only need to check
192 * one format with everything else. */
193 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
194 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
195 format_list
->pViewFormats
[i
]))
196 dcc_compatible_formats
= false;
199 dcc_compatible_formats
= false;
203 if (!dcc_compatible_formats
)
210 radv_init_surface(struct radv_device
*device
,
211 const struct radv_image
*image
,
212 struct radeon_surf
*surface
,
214 const struct radv_image_create_info
*create_info
)
216 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
217 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
218 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
219 const struct vk_format_description
*desc
= vk_format_description(format
);
220 bool is_depth
, is_stencil
;
222 is_depth
= vk_format_has_depth(desc
);
223 is_stencil
= vk_format_has_stencil(desc
);
225 surface
->blk_w
= vk_format_get_blockwidth(format
);
226 surface
->blk_h
= vk_format_get_blockheight(format
);
228 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
229 /* align byte per element on dword */
230 if (surface
->bpe
== 3) {
233 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
235 switch (pCreateInfo
->imageType
){
236 case VK_IMAGE_TYPE_1D
:
237 if (pCreateInfo
->arrayLayers
> 1)
238 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
240 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
242 case VK_IMAGE_TYPE_2D
:
243 if (pCreateInfo
->arrayLayers
> 1)
244 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
246 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
248 case VK_IMAGE_TYPE_3D
:
249 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
252 unreachable("unhandled image type");
256 surface
->flags
|= RADEON_SURF_ZBUFFER
;
257 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
258 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
262 surface
->flags
|= RADEON_SURF_SBUFFER
;
264 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
265 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
266 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
267 vk_format_is_compressed(pCreateInfo
->format
))
268 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
270 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
272 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
273 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
275 if (create_info
->scanout
)
276 surface
->flags
|= RADEON_SURF_SCANOUT
;
280 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
282 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
285 static inline unsigned
286 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
289 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
291 return plane
->surface
.u
.legacy
.tiling_index
[level
];
294 static unsigned radv_map_swizzle(unsigned swizzle
)
298 return V_008F0C_SQ_SEL_Y
;
300 return V_008F0C_SQ_SEL_Z
;
302 return V_008F0C_SQ_SEL_W
;
304 return V_008F0C_SQ_SEL_0
;
306 return V_008F0C_SQ_SEL_1
;
307 default: /* VK_SWIZZLE_X */
308 return V_008F0C_SQ_SEL_X
;
313 radv_make_buffer_descriptor(struct radv_device
*device
,
314 struct radv_buffer
*buffer
,
320 const struct vk_format_description
*desc
;
322 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
323 uint64_t va
= gpu_address
+ buffer
->offset
;
324 unsigned num_format
, data_format
;
326 desc
= vk_format_description(vk_format
);
327 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
328 stride
= desc
->block
.bits
/ 8;
330 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
331 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
335 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
336 S_008F04_STRIDE(stride
);
338 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
343 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
344 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
345 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
346 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
347 S_008F0C_NUM_FORMAT(num_format
) |
348 S_008F0C_DATA_FORMAT(data_format
);
352 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
353 struct radv_image
*image
,
354 const struct legacy_surf_level
*base_level_info
,
356 unsigned base_level
, unsigned first_level
,
357 unsigned block_width
, bool is_stencil
,
358 bool is_storage_image
, uint32_t *state
)
360 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
361 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
362 uint64_t va
= gpu_address
+ plane
->offset
;
363 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
364 uint64_t meta_va
= 0;
365 if (chip_class
>= GFX9
) {
367 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
369 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
371 va
+= base_level_info
->offset
;
374 if (chip_class
>= GFX9
||
375 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
376 state
[0] |= plane
->surface
.tile_swizzle
;
377 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
378 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
380 if (chip_class
>= GFX8
) {
381 state
[6] &= C_008F28_COMPRESSION_EN
;
383 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
384 meta_va
= gpu_address
+ image
->dcc_offset
;
385 if (chip_class
<= GFX8
)
386 meta_va
+= base_level_info
->dcc_offset
;
387 } else if (!is_storage_image
&&
388 radv_image_is_tc_compat_htile(image
)) {
389 meta_va
= gpu_address
+ image
->htile_offset
;
393 state
[6] |= S_008F28_COMPRESSION_EN(1);
394 state
[7] = meta_va
>> 8;
395 state
[7] |= plane
->surface
.tile_swizzle
;
399 if (chip_class
>= GFX9
) {
400 state
[3] &= C_008F1C_SW_MODE
;
401 state
[4] &= C_008F20_PITCH
;
404 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
405 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
407 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
408 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
411 state
[5] &= C_008F24_META_DATA_ADDRESS
&
412 C_008F24_META_PIPE_ALIGNED
&
413 C_008F24_META_RB_ALIGNED
;
415 struct gfx9_surf_meta_flags meta
;
417 if (image
->dcc_offset
)
418 meta
= plane
->surface
.u
.gfx9
.dcc
;
420 meta
= plane
->surface
.u
.gfx9
.htile
;
422 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
423 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
424 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
428 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
429 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
431 state
[3] &= C_008F1C_TILING_INDEX
;
432 state
[3] |= S_008F1C_TILING_INDEX(index
);
433 state
[4] &= C_008F20_PITCH
;
434 state
[4] |= S_008F20_PITCH(pitch
- 1);
438 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
439 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
441 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
442 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
444 /* GFX9 allocates 1D textures as 2D. */
445 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
446 image_type
= VK_IMAGE_TYPE_2D
;
447 switch (image_type
) {
448 case VK_IMAGE_TYPE_1D
:
449 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
450 case VK_IMAGE_TYPE_2D
:
452 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
454 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
455 case VK_IMAGE_TYPE_3D
:
456 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
457 return V_008F1C_SQ_RSRC_IMG_3D
;
459 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
461 unreachable("illegal image type");
465 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
467 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
469 if (swizzle
[3] == VK_SWIZZLE_X
) {
470 /* For the pre-defined border color values (white, opaque
471 * black, transparent black), the only thing that matters is
472 * that the alpha channel winds up in the correct place
473 * (because the RGB channels are all the same) so either of
474 * these enumerations will work.
476 if (swizzle
[2] == VK_SWIZZLE_Y
)
477 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
479 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
480 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
481 if (swizzle
[1] == VK_SWIZZLE_Y
)
482 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
484 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
485 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
486 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
487 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
488 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
495 * Build the sampler view descriptor for a texture.
498 si_make_texture_descriptor(struct radv_device
*device
,
499 struct radv_image
*image
,
500 bool is_storage_image
,
501 VkImageViewType view_type
,
503 const VkComponentMapping
*mapping
,
504 unsigned first_level
, unsigned last_level
,
505 unsigned first_layer
, unsigned last_layer
,
506 unsigned width
, unsigned height
, unsigned depth
,
508 uint32_t *fmask_state
)
510 const struct vk_format_description
*desc
;
511 enum vk_swizzle swizzle
[4];
513 unsigned num_format
, data_format
, type
;
515 desc
= vk_format_description(vk_format
);
517 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
518 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
519 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
521 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
524 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
526 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
527 if (num_format
== ~0) {
531 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
532 if (data_format
== ~0) {
536 /* S8 with either Z16 or Z32 HTILE need a special format. */
537 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
538 vk_format
== VK_FORMAT_S8_UINT
&&
539 radv_image_is_tc_compat_htile(image
)) {
540 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
541 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
542 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
543 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
545 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
546 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
547 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
549 depth
= image
->info
.array_size
;
550 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
551 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
552 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
553 depth
= image
->info
.array_size
;
554 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
555 depth
= image
->info
.array_size
/ 6;
558 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
559 S_008F14_NUM_FORMAT(num_format
));
560 state
[2] = (S_008F18_WIDTH(width
- 1) |
561 S_008F18_HEIGHT(height
- 1) |
562 S_008F18_PERF_MOD(4));
563 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
564 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
565 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
566 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
567 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
569 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
570 util_logbase2(image
->info
.samples
) :
572 S_008F1C_TYPE(type
));
574 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
578 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
579 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
581 /* Depth is the last accessible layer on Gfx9.
582 * The hw doesn't need to know the total number of layers.
584 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
585 state
[4] |= S_008F20_DEPTH(depth
- 1);
587 state
[4] |= S_008F20_DEPTH(last_layer
);
589 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
590 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
591 util_logbase2(image
->info
.samples
) :
592 image
->info
.levels
- 1);
594 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
595 state
[4] |= S_008F20_DEPTH(depth
- 1);
596 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
598 if (image
->dcc_offset
) {
599 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
601 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
603 /* The last dword is unused by hw. The shader uses it to clear
604 * bits in the first dword of sampler state.
606 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
607 if (first_level
== last_level
)
608 state
[7] = C_008F30_MAX_ANISO_RATIO
;
610 state
[7] = 0xffffffff;
614 /* Initialize the sampler view for FMASK. */
615 if (radv_image_has_fmask(image
)) {
616 uint32_t fmask_format
, num_format
;
617 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
620 assert(image
->plane_count
== 1);
622 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
624 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
625 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
626 switch (image
->info
.samples
) {
628 num_format
= V_008F14_IMG_FMASK_8_2_2
;
631 num_format
= V_008F14_IMG_FMASK_8_4_4
;
634 num_format
= V_008F14_IMG_FMASK_32_8_8
;
637 unreachable("invalid nr_samples");
640 switch (image
->info
.samples
) {
642 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
645 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
648 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
652 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
654 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
657 fmask_state
[0] = va
>> 8;
658 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
659 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
660 S_008F14_DATA_FORMAT(fmask_format
) |
661 S_008F14_NUM_FORMAT(num_format
);
662 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
663 S_008F18_HEIGHT(height
- 1);
664 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
665 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
666 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
667 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
668 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
670 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
674 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
675 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
676 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
677 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
678 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
679 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
681 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
682 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
683 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
684 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
686 } else if (fmask_state
)
687 memset(fmask_state
, 0, 8 * 4);
691 radv_query_opaque_metadata(struct radv_device
*device
,
692 struct radv_image
*image
,
693 struct radeon_bo_metadata
*md
)
695 static const VkComponentMapping fixedmapping
;
698 assert(image
->plane_count
== 1);
700 /* Metadata image format format version 1:
701 * [0] = 1 (metadata format identifier)
702 * [1] = (VENDOR_ID << 16) | PCI_ID
703 * [2:9] = image descriptor for the whole resource
704 * [2] is always 0, because the base address is cleared
705 * [9] is the DCC offset bits [39:8] from the beginning of
707 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
709 md
->metadata
[0] = 1; /* metadata image format version 1 */
711 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
712 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
715 si_make_texture_descriptor(device
, image
, false,
716 (VkImageViewType
)image
->type
, image
->vk_format
,
717 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
718 image
->info
.array_size
- 1,
719 image
->info
.width
, image
->info
.height
,
723 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
724 image
->planes
[0].surface
.blk_w
, false, false, desc
);
726 /* Clear the base address and set the relative DCC offset. */
728 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
729 desc
[7] = image
->dcc_offset
>> 8;
731 /* Dwords [2:9] contain the image descriptor. */
732 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
734 /* Dwords [10:..] contain the mipmap level offsets. */
735 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
736 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
737 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
738 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
743 radv_init_metadata(struct radv_device
*device
,
744 struct radv_image
*image
,
745 struct radeon_bo_metadata
*metadata
)
747 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
749 memset(metadata
, 0, sizeof(*metadata
));
751 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
752 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
754 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
755 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
756 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
757 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
758 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
759 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
760 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
761 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
762 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
763 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
764 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
765 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
767 radv_query_opaque_metadata(device
, image
, metadata
);
771 radv_image_override_offset_stride(struct radv_device
*device
,
772 struct radv_image
*image
,
773 uint64_t offset
, uint32_t stride
)
775 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
776 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
778 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
780 surface
->u
.gfx9
.surf_pitch
= stride
;
781 surface
->u
.gfx9
.surf_slice_size
=
782 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
784 surface
->u
.gfx9
.surf_offset
= offset
;
786 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
787 surface
->u
.legacy
.level
[0].slice_size_dw
=
788 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
791 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
792 surface
->u
.legacy
.level
[i
].offset
+= offset
;
798 /* The number of samples can be specified independently of the texture. */
800 radv_image_get_fmask_info(struct radv_device
*device
,
801 struct radv_image
*image
,
803 struct radv_fmask_info
*out
)
805 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
806 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
807 out
->size
= image
->planes
[0].surface
.fmask_size
;
808 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
812 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
813 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
814 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
815 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
816 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
817 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
818 out
->size
= image
->planes
[0].surface
.fmask_size
;
820 assert(!out
->tile_swizzle
|| !image
->shareable
);
824 radv_image_alloc_fmask(struct radv_device
*device
,
825 struct radv_image
*image
)
827 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
829 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
830 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
831 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
835 radv_image_get_cmask_info(struct radv_device
*device
,
836 struct radv_image
*image
,
837 struct radv_cmask_info
*out
)
839 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
840 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
841 unsigned cl_width
, cl_height
;
843 assert(image
->plane_count
== 1);
845 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
846 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
847 out
->size
= image
->planes
[0].surface
.cmask_size
;
864 case 16: /* Hawaii */
873 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
875 unsigned width
= align(image
->planes
[0].surface
.u
.legacy
.level
[0].nblk_x
, cl_width
*8);
876 unsigned height
= align(image
->planes
[0].surface
.u
.legacy
.level
[0].nblk_y
, cl_height
*8);
877 unsigned slice_elements
= (width
* height
) / (8*8);
879 /* Each element of CMASK is a nibble. */
880 unsigned slice_bytes
= slice_elements
/ 2;
882 out
->slice_tile_max
= (width
* height
) / (128*128);
883 if (out
->slice_tile_max
)
884 out
->slice_tile_max
-= 1;
886 out
->alignment
= MAX2(256, base_align
);
887 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
888 align(slice_bytes
, base_align
);
892 radv_image_alloc_cmask(struct radv_device
*device
,
893 struct radv_image
*image
)
895 uint32_t clear_value_size
= 0;
896 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
898 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
899 /* + 8 for storing the clear values */
900 if (!image
->clear_value_offset
) {
901 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
902 clear_value_size
= 8;
904 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
905 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
909 radv_image_alloc_dcc(struct radv_image
*image
)
911 assert(image
->plane_count
== 1);
913 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
914 /* + 16 for storing the clear values + dcc pred */
915 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
916 image
->fce_pred_offset
= image
->clear_value_offset
+ 8;
917 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16;
918 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24;
919 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
923 radv_image_alloc_htile(struct radv_image
*image
)
925 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
927 /* + 8 for storing the clear values */
928 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
929 image
->size
= image
->clear_value_offset
+ 8;
930 if (radv_image_is_tc_compat_htile(image
)) {
931 /* Metadata for the TC-compatible HTILE hardware bug which
932 * have to be fixed by updating ZRANGE_PRECISION when doing
933 * fast depth clears to 0.0f.
935 image
->tc_compat_zrange_offset
= image
->clear_value_offset
+ 8;
936 image
->size
= image
->clear_value_offset
+ 16;
938 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
942 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
944 if (image
->info
.samples
<= 1 &&
945 image
->info
.width
* image
->info
.height
<= 512 * 512) {
946 /* Do not enable CMASK or DCC for small surfaces where the cost
947 * of the eliminate pass can be higher than the benefit of fast
948 * clear. RadeonSI does this, but the image threshold is
954 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
955 (image
->exclusive
|| image
->queue_family_mask
== 1);
959 radv_image_can_enable_dcc(struct radv_image
*image
)
961 return radv_image_can_enable_dcc_or_cmask(image
) &&
962 radv_image_has_dcc(image
);
966 radv_image_can_enable_cmask(struct radv_image
*image
)
968 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
969 /* Do not enable CMASK for non-MSAA images (fast color clear)
970 * because 128 bit formats are not supported, but FMASK might
976 return radv_image_can_enable_dcc_or_cmask(image
) &&
977 image
->info
.levels
== 1 &&
978 image
->info
.depth
== 1 &&
979 !image
->planes
[0].surface
.is_linear
;
983 radv_image_can_enable_fmask(struct radv_image
*image
)
985 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
989 radv_image_can_enable_htile(struct radv_image
*image
)
991 return radv_image_has_htile(image
) &&
992 image
->info
.levels
== 1 &&
993 image
->info
.width
* image
->info
.height
>= 8 * 8;
996 static void radv_image_disable_dcc(struct radv_image
*image
)
998 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
999 image
->planes
[i
].surface
.dcc_size
= 0;
1002 static void radv_image_disable_htile(struct radv_image
*image
)
1004 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1005 image
->planes
[i
].surface
.htile_size
= 0;
1009 radv_image_create(VkDevice _device
,
1010 const struct radv_image_create_info
*create_info
,
1011 const VkAllocationCallbacks
* alloc
,
1014 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1015 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1016 struct radv_image
*image
= NULL
;
1017 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1019 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1020 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1022 radv_assert(pCreateInfo
->mipLevels
> 0);
1023 radv_assert(pCreateInfo
->arrayLayers
> 0);
1024 radv_assert(pCreateInfo
->samples
> 0);
1025 radv_assert(pCreateInfo
->extent
.width
> 0);
1026 radv_assert(pCreateInfo
->extent
.height
> 0);
1027 radv_assert(pCreateInfo
->extent
.depth
> 0);
1029 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1030 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1032 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1034 image
->type
= pCreateInfo
->imageType
;
1035 image
->info
.width
= pCreateInfo
->extent
.width
;
1036 image
->info
.height
= pCreateInfo
->extent
.height
;
1037 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1038 image
->info
.samples
= pCreateInfo
->samples
;
1039 image
->info
.storage_samples
= pCreateInfo
->samples
;
1040 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1041 image
->info
.levels
= pCreateInfo
->mipLevels
;
1042 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1044 image
->vk_format
= pCreateInfo
->format
;
1045 image
->tiling
= pCreateInfo
->tiling
;
1046 image
->usage
= pCreateInfo
->usage
;
1047 image
->flags
= pCreateInfo
->flags
;
1049 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1050 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1051 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1052 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
)
1053 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1055 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1058 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1059 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1060 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
1061 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1064 image
->plane_count
= plane_count
;
1066 image
->alignment
= 1;
1067 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1068 struct ac_surf_info info
= image
->info
;
1069 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1072 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1073 assert(info
.width
% desc
->width_divisor
== 0);
1074 assert(info
.height
% desc
->height_divisor
== 0);
1076 info
.width
/= desc
->width_divisor
;
1077 info
.height
/= desc
->height_divisor
;
1080 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1082 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1083 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1084 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1086 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1089 if (!create_info
->no_metadata_planes
) {
1090 /* Try to enable DCC first. */
1091 if (radv_image_can_enable_dcc(image
)) {
1092 radv_image_alloc_dcc(image
);
1093 if (image
->info
.samples
> 1) {
1094 /* CMASK should be enabled because DCC fast
1095 * clear with MSAA needs it.
1097 assert(radv_image_can_enable_cmask(image
));
1098 radv_image_alloc_cmask(device
, image
);
1101 /* When DCC cannot be enabled, try CMASK. */
1102 radv_image_disable_dcc(image
);
1103 if (radv_image_can_enable_cmask(image
)) {
1104 radv_image_alloc_cmask(device
, image
);
1108 /* Try to enable FMASK for multisampled images. */
1109 if (radv_image_can_enable_fmask(image
)) {
1110 radv_image_alloc_fmask(device
, image
);
1112 /* Otherwise, try to enable HTILE for depth surfaces. */
1113 if (radv_image_can_enable_htile(image
) &&
1114 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1115 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1116 radv_image_alloc_htile(image
);
1118 radv_image_disable_htile(image
);
1122 radv_image_disable_dcc(image
);
1123 radv_image_disable_htile(image
);
1126 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1127 image
->alignment
= MAX2(image
->alignment
, 4096);
1128 image
->size
= align64(image
->size
, image
->alignment
);
1131 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1132 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1134 vk_free2(&device
->alloc
, alloc
, image
);
1135 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1139 *pImage
= radv_image_to_handle(image
);
1145 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1146 struct radv_device
*device
,
1148 const VkComponentMapping
*components
,
1149 bool is_storage_image
, unsigned plane_id
,
1150 unsigned descriptor_plane_id
)
1152 struct radv_image
*image
= iview
->image
;
1153 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1154 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1155 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1157 union radv_descriptor
*descriptor
;
1158 uint32_t hw_level
= 0;
1160 if (is_storage_image
) {
1161 descriptor
= &iview
->storage_descriptor
;
1163 descriptor
= &iview
->descriptor
;
1166 assert(vk_format_get_plane_count(vk_format
) == 1);
1167 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1168 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1170 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1171 hw_level
= iview
->base_mip
;
1172 si_make_texture_descriptor(device
, image
, is_storage_image
,
1176 hw_level
, hw_level
+ iview
->level_count
- 1,
1178 iview
->base_layer
+ iview
->layer_count
- 1,
1179 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1180 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1181 iview
->extent
.depth
,
1182 descriptor
->plane_descriptors
[descriptor_plane_id
],
1183 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1185 const struct legacy_surf_level
*base_level_info
= NULL
;
1186 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1188 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1190 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1192 si_set_mutable_tex_desc_fields(device
, image
,
1197 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1201 radv_plane_from_aspect(VkImageAspectFlags mask
)
1204 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1206 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1214 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1217 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1218 return image
->planes
[0].format
;
1219 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1220 return image
->planes
[1].format
;
1221 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1222 return image
->planes
[2].format
;
1223 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1224 return vk_format_stencil_only(image
->vk_format
);
1225 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1226 return vk_format_depth_only(image
->vk_format
);
1227 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1228 return vk_format_depth_only(image
->vk_format
);
1230 return image
->vk_format
;
1235 radv_image_view_init(struct radv_image_view
*iview
,
1236 struct radv_device
*device
,
1237 const VkImageViewCreateInfo
* pCreateInfo
)
1239 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1240 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1242 switch (image
->type
) {
1243 case VK_IMAGE_TYPE_1D
:
1244 case VK_IMAGE_TYPE_2D
:
1245 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1247 case VK_IMAGE_TYPE_3D
:
1248 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1249 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1252 unreachable("bad VkImageType");
1254 iview
->image
= image
;
1255 iview
->bo
= image
->bo
;
1256 iview
->type
= pCreateInfo
->viewType
;
1257 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1258 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1259 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1260 iview
->vk_format
= pCreateInfo
->format
;
1262 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1263 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1264 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1265 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1268 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1269 iview
->extent
= (VkExtent3D
) {
1270 .width
= image
->info
.width
,
1271 .height
= image
->info
.height
,
1272 .depth
= image
->info
.depth
,
1275 iview
->extent
= (VkExtent3D
) {
1276 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1277 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1278 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1282 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1283 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1284 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1285 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1286 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1288 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1289 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1291 /* Comment ported from amdvlk -
1292 * If we have the following image:
1293 * Uncompressed pixels Compressed block sizes (4x4)
1294 * mip0: 22 x 22 6 x 6
1295 * mip1: 11 x 11 3 x 3
1300 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1301 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1302 * divide-by-two integer math):
1308 * This means that mip2 will be missing texels.
1310 * Fix this by calculating the base mip's width and height, then convert that, and round it
1311 * back up to get the level 0 size.
1312 * Clamp the converted size between the original values, and next power of two, which
1313 * means we don't oversize the image.
1315 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1316 vk_format_is_compressed(image
->vk_format
) &&
1317 !vk_format_is_compressed(iview
->vk_format
)) {
1318 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1319 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1321 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1322 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1324 lvl_width
<<= range
->baseMipLevel
;
1325 lvl_height
<<= range
->baseMipLevel
;
1327 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1328 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1332 iview
->base_layer
= range
->baseArrayLayer
;
1333 iview
->layer_count
= radv_get_layerCount(image
, range
);
1334 iview
->base_mip
= range
->baseMipLevel
;
1335 iview
->level_count
= radv_get_levelCount(image
, range
);
1337 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1338 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1339 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1340 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1344 bool radv_layout_has_htile(const struct radv_image
*image
,
1345 VkImageLayout layout
,
1346 unsigned queue_mask
)
1348 if (radv_image_is_tc_compat_htile(image
))
1349 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1351 return radv_image_has_htile(image
) &&
1352 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1353 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1354 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1357 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1358 VkImageLayout layout
,
1359 unsigned queue_mask
)
1361 if (radv_image_is_tc_compat_htile(image
))
1362 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1364 return radv_image_has_htile(image
) &&
1365 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1366 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1367 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1370 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1371 VkImageLayout layout
,
1372 unsigned queue_mask
)
1374 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1377 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1378 VkImageLayout layout
,
1379 unsigned queue_mask
)
1381 /* Don't compress compute transfer dst, as image stores are not supported. */
1382 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1383 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1386 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1390 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1392 if (!image
->exclusive
)
1393 return image
->queue_family_mask
;
1394 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
1395 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1396 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1397 return 1u << queue_family
;
1398 return 1u << family
;
1402 radv_CreateImage(VkDevice device
,
1403 const VkImageCreateInfo
*pCreateInfo
,
1404 const VkAllocationCallbacks
*pAllocator
,
1408 const VkNativeBufferANDROID
*gralloc_info
=
1409 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1412 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1413 pAllocator
, pImage
);
1416 const struct wsi_image_create_info
*wsi_info
=
1417 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1418 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1420 return radv_image_create(device
,
1421 &(struct radv_image_create_info
) {
1422 .vk_info
= pCreateInfo
,
1430 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1431 const VkAllocationCallbacks
*pAllocator
)
1433 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1434 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1439 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1440 device
->ws
->buffer_destroy(image
->bo
);
1442 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1443 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1445 vk_free2(&device
->alloc
, pAllocator
, image
);
1448 void radv_GetImageSubresourceLayout(
1451 const VkImageSubresource
* pSubresource
,
1452 VkSubresourceLayout
* pLayout
)
1454 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1455 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1456 int level
= pSubresource
->mipLevel
;
1457 int layer
= pSubresource
->arrayLayer
;
1459 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1461 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1462 struct radeon_surf
*surface
= &plane
->surface
;
1464 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1465 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1466 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1467 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1468 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1469 /* Adjust the number of bytes between each row because
1470 * the pitch is actually the number of components per
1473 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1475 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1476 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1479 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1480 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1481 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1482 if (image
->type
== VK_IMAGE_TYPE_3D
)
1483 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1485 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1486 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1487 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1488 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1489 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1490 if (image
->type
== VK_IMAGE_TYPE_3D
)
1491 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1497 radv_CreateImageView(VkDevice _device
,
1498 const VkImageViewCreateInfo
*pCreateInfo
,
1499 const VkAllocationCallbacks
*pAllocator
,
1502 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1503 struct radv_image_view
*view
;
1505 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1506 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1508 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1510 radv_image_view_init(view
, device
, pCreateInfo
);
1512 *pView
= radv_image_view_to_handle(view
);
1518 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1519 const VkAllocationCallbacks
*pAllocator
)
1521 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1522 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1526 vk_free2(&device
->alloc
, pAllocator
, iview
);
1529 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1530 struct radv_device
*device
,
1531 const VkBufferViewCreateInfo
* pCreateInfo
)
1533 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1535 view
->bo
= buffer
->bo
;
1536 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1537 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1538 view
->vk_format
= pCreateInfo
->format
;
1540 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1541 pCreateInfo
->offset
, view
->range
, view
->state
);
1545 radv_CreateBufferView(VkDevice _device
,
1546 const VkBufferViewCreateInfo
*pCreateInfo
,
1547 const VkAllocationCallbacks
*pAllocator
,
1548 VkBufferView
*pView
)
1550 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1551 struct radv_buffer_view
*view
;
1553 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1554 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1556 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1558 radv_buffer_view_init(view
, device
, pCreateInfo
);
1560 *pView
= radv_buffer_view_to_handle(view
);
1566 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1567 const VkAllocationCallbacks
*pAllocator
)
1569 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1570 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1575 vk_free2(&device
->alloc
, pAllocator
, view
);