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radv: split metadata struct into legacy/gfx9 parts.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "radv_radeon_winsys.h"
31 #include "sid.h"
32 #include "util/debug.h"
33 static unsigned
34 radv_choose_tiling(struct radv_device *Device,
35 const struct radv_image_create_info *create_info)
36 {
37 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
38
39 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
40 assert(pCreateInfo->samples <= 1);
41 return RADEON_SURF_MODE_LINEAR_ALIGNED;
42 }
43
44 /* Textures with a very small height are recommended to be linear. */
45 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
46 /* Only very thin and long 2D textures should benefit from
47 * linear_aligned. */
48 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
49 return RADEON_SURF_MODE_LINEAR_ALIGNED;
50
51 /* MSAA resources must be 2D tiled. */
52 if (pCreateInfo->samples > 1)
53 return RADEON_SURF_MODE_2D;
54
55 return RADEON_SURF_MODE_2D;
56 }
57 static int
58 radv_init_surface(struct radv_device *device,
59 struct radeon_surf *surface,
60 const struct radv_image_create_info *create_info)
61 {
62 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
63 unsigned array_mode = radv_choose_tiling(device, create_info);
64 const struct vk_format_description *desc =
65 vk_format_description(pCreateInfo->format);
66 bool is_depth, is_stencil, blendable;
67
68 is_depth = vk_format_has_depth(desc);
69 is_stencil = vk_format_has_stencil(desc);
70
71 surface->blk_w = vk_format_get_blockwidth(pCreateInfo->format);
72 surface->blk_h = vk_format_get_blockheight(pCreateInfo->format);
73
74 surface->bpe = vk_format_get_blocksize(pCreateInfo->format);
75 /* align byte per element on dword */
76 if (surface->bpe == 3) {
77 surface->bpe = 4;
78 }
79 surface->flags = RADEON_SURF_SET(array_mode, MODE);
80
81 switch (pCreateInfo->imageType){
82 case VK_IMAGE_TYPE_1D:
83 if (pCreateInfo->arrayLayers > 1)
84 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
85 else
86 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
87 break;
88 case VK_IMAGE_TYPE_2D:
89 if (pCreateInfo->arrayLayers > 1)
90 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
91 else
92 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
93 break;
94 case VK_IMAGE_TYPE_3D:
95 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
96 break;
97 default:
98 unreachable("unhandled image type");
99 }
100
101 if (is_depth) {
102 surface->flags |= RADEON_SURF_ZBUFFER;
103 }
104
105 if (is_stencil)
106 surface->flags |= RADEON_SURF_SBUFFER;
107
108 surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
109
110 if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
111 VK_IMAGE_USAGE_STORAGE_BIT)) ||
112 (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) ||
113 (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
114 device->physical_device->rad_info.chip_class < VI ||
115 create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) ||
116 !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable))
117 surface->flags |= RADEON_SURF_DISABLE_DCC;
118 if (create_info->scanout)
119 surface->flags |= RADEON_SURF_SCANOUT;
120 return 0;
121 }
122 #define ATI_VENDOR_ID 0x1002
123 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
124 {
125 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
126 }
127
128 static inline unsigned
129 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
130 {
131 if (stencil)
132 return image->surface.u.legacy.stencil_tiling_index[level];
133 else
134 return image->surface.u.legacy.tiling_index[level];
135 }
136
137 static unsigned radv_map_swizzle(unsigned swizzle)
138 {
139 switch (swizzle) {
140 case VK_SWIZZLE_Y:
141 return V_008F0C_SQ_SEL_Y;
142 case VK_SWIZZLE_Z:
143 return V_008F0C_SQ_SEL_Z;
144 case VK_SWIZZLE_W:
145 return V_008F0C_SQ_SEL_W;
146 case VK_SWIZZLE_0:
147 return V_008F0C_SQ_SEL_0;
148 case VK_SWIZZLE_1:
149 return V_008F0C_SQ_SEL_1;
150 default: /* VK_SWIZZLE_X */
151 return V_008F0C_SQ_SEL_X;
152 }
153 }
154
155 static void
156 radv_make_buffer_descriptor(struct radv_device *device,
157 struct radv_buffer *buffer,
158 VkFormat vk_format,
159 unsigned offset,
160 unsigned range,
161 uint32_t *state)
162 {
163 const struct vk_format_description *desc;
164 unsigned stride;
165 uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo);
166 uint64_t va = gpu_address + buffer->offset;
167 unsigned num_format, data_format;
168 int first_non_void;
169 desc = vk_format_description(vk_format);
170 first_non_void = vk_format_get_first_non_void_channel(vk_format);
171 stride = desc->block.bits / 8;
172
173 num_format = radv_translate_buffer_numformat(desc, first_non_void);
174 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
175
176 va += offset;
177 state[0] = va;
178 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
179 S_008F04_STRIDE(stride);
180 state[2] = range;
181 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
182 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
183 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
184 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
185 S_008F0C_NUM_FORMAT(num_format) |
186 S_008F0C_DATA_FORMAT(data_format);
187 }
188
189 static void
190 si_set_mutable_tex_desc_fields(struct radv_device *device,
191 struct radv_image *image,
192 const struct legacy_surf_level *base_level_info,
193 unsigned base_level, unsigned first_level,
194 unsigned block_width, bool is_stencil,
195 uint32_t *state)
196 {
197 uint64_t gpu_address = device->ws->buffer_get_va(image->bo) + image->offset;
198 uint64_t va = gpu_address + base_level_info->offset;
199 unsigned pitch = base_level_info->nblk_x * block_width;
200
201 state[1] &= C_008F14_BASE_ADDRESS_HI;
202 state[3] &= C_008F1C_TILING_INDEX;
203 state[4] &= C_008F20_PITCH_GFX6;
204 state[6] &= C_008F28_COMPRESSION_EN;
205
206 assert(!(va & 255));
207
208 state[0] = va >> 8;
209 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
210 state[3] |= S_008F1C_TILING_INDEX(si_tile_mode_index(image, base_level,
211 is_stencil));
212 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
213
214 if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) {
215 state[6] |= S_008F28_COMPRESSION_EN(1);
216 state[7] = (gpu_address +
217 image->dcc_offset +
218 base_level_info->dcc_offset) >> 8;
219 }
220 }
221
222 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
223 unsigned nr_layers, unsigned nr_samples, bool is_storage_image)
224 {
225 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
226 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
227 switch (image_type) {
228 case VK_IMAGE_TYPE_1D:
229 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
230 case VK_IMAGE_TYPE_2D:
231 if (nr_samples > 1)
232 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
233 else
234 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
235 case VK_IMAGE_TYPE_3D:
236 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
237 return V_008F1C_SQ_RSRC_IMG_3D;
238 else
239 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
240 default:
241 unreachable("illegale image type");
242 }
243 }
244 /**
245 * Build the sampler view descriptor for a texture.
246 */
247 static void
248 si_make_texture_descriptor(struct radv_device *device,
249 struct radv_image *image,
250 bool sampler,
251 VkImageViewType view_type,
252 VkFormat vk_format,
253 const VkComponentMapping *mapping,
254 unsigned first_level, unsigned last_level,
255 unsigned first_layer, unsigned last_layer,
256 unsigned width, unsigned height, unsigned depth,
257 uint32_t *state,
258 uint32_t *fmask_state)
259 {
260 const struct vk_format_description *desc;
261 enum vk_swizzle swizzle[4];
262 int first_non_void;
263 unsigned num_format, data_format, type;
264
265 desc = vk_format_description(vk_format);
266
267 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
268 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
269 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
270 } else {
271 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
272 }
273
274 first_non_void = vk_format_get_first_non_void_channel(vk_format);
275
276 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
277 if (num_format == ~0) {
278 num_format = 0;
279 }
280
281 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
282 if (data_format == ~0) {
283 data_format = 0;
284 }
285
286 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
287 (image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
288 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
289 height = 1;
290 depth = image->info.array_size;
291 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
292 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
293 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
294 depth = image->info.array_size;
295 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
296 depth = image->info.array_size / 6;
297
298 state[0] = 0;
299 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
300 S_008F14_NUM_FORMAT_GFX6(num_format));
301 state[2] = (S_008F18_WIDTH(width - 1) |
302 S_008F18_HEIGHT(height - 1) |
303 S_008F18_PERF_MOD(4));
304 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
305 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
306 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
307 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
308 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
309 0 : first_level) |
310 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
311 util_logbase2(image->info.samples) :
312 last_level) |
313 S_008F1C_TYPE(type));
314 state[4] = 0;
315 state[5] = S_008F24_BASE_ARRAY(first_layer);
316
317 state[6] = 0;
318 state[7] = 0;
319
320 {
321 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
322 state[4] |= S_008F20_DEPTH(depth - 1);
323 state[5] |= S_008F24_LAST_ARRAY(last_layer);
324 }
325 if (image->dcc_offset) {
326 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
327
328 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
329 } else {
330 /* The last dword is unused by hw. The shader uses it to clear
331 * bits in the first dword of sampler state.
332 */
333 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
334 if (first_level == last_level)
335 state[7] = C_008F30_MAX_ANISO_RATIO;
336 else
337 state[7] = 0xffffffff;
338 }
339 }
340
341 /* Initialize the sampler view for FMASK. */
342 if (image->fmask.size) {
343 uint32_t fmask_format;
344 uint64_t gpu_address = device->ws->buffer_get_va(image->bo);
345 uint64_t va;
346
347 va = gpu_address + image->offset + image->fmask.offset;
348
349 switch (image->info.samples) {
350 case 2:
351 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
352 break;
353 case 4:
354 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
355 break;
356 case 8:
357 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
358 break;
359 default:
360 assert(0);
361 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
362 }
363
364 fmask_state[0] = va >> 8;
365 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
366 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
367 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_UINT);
368 fmask_state[2] = S_008F18_WIDTH(width - 1) |
369 S_008F18_HEIGHT(height - 1);
370 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
371 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
372 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
373 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
374 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
375 fmask_state[4] = 0;
376 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
377 fmask_state[6] = 0;
378 fmask_state[7] = 0;
379
380 {
381 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
382 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
383 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
384 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
385 }
386 }
387 }
388
389 static void
390 radv_query_opaque_metadata(struct radv_device *device,
391 struct radv_image *image,
392 struct radeon_bo_metadata *md)
393 {
394 static const VkComponentMapping fixedmapping;
395 uint32_t desc[8], i;
396
397 /* Metadata image format format version 1:
398 * [0] = 1 (metadata format identifier)
399 * [1] = (VENDOR_ID << 16) | PCI_ID
400 * [2:9] = image descriptor for the whole resource
401 * [2] is always 0, because the base address is cleared
402 * [9] is the DCC offset bits [39:8] from the beginning of
403 * the buffer
404 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
405 */
406 md->metadata[0] = 1; /* metadata image format version 1 */
407
408 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
409 md->metadata[1] = si_get_bo_metadata_word1(device);
410
411
412 si_make_texture_descriptor(device, image, true,
413 (VkImageViewType)image->type, image->vk_format,
414 &fixedmapping, 0, image->info.levels - 1, 0,
415 image->info.array_size,
416 image->info.width, image->info.height,
417 image->info.depth,
418 desc, NULL);
419
420 si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
421 image->surface.blk_w, false, desc);
422
423 /* Clear the base address and set the relative DCC offset. */
424 desc[0] = 0;
425 desc[1] &= C_008F14_BASE_ADDRESS_HI;
426 desc[7] = image->dcc_offset >> 8;
427
428 /* Dwords [2:9] contain the image descriptor. */
429 memcpy(&md->metadata[2], desc, sizeof(desc));
430
431 /* Dwords [10:..] contain the mipmap level offsets. */
432 for (i = 0; i <= image->info.levels - 1; i++)
433 md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
434
435 md->size_metadata = (11 + image->info.levels - 1) * 4;
436 }
437
438 void
439 radv_init_metadata(struct radv_device *device,
440 struct radv_image *image,
441 struct radeon_bo_metadata *metadata)
442 {
443 struct radeon_surf *surface = &image->surface;
444
445 memset(metadata, 0, sizeof(*metadata));
446
447 if (device->physical_device->rad_info.chip_class >= GFX9) {
448 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
449 } else {
450 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
451 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
452 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
453 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
454 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
455 metadata->u.legacy.bankw = surface->u.legacy.bankw;
456 metadata->u.legacy.bankh = surface->u.legacy.bankh;
457 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
458 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
459 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
460 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
461 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
462 }
463 radv_query_opaque_metadata(device, image, metadata);
464 }
465
466 /* The number of samples can be specified independently of the texture. */
467 static void
468 radv_image_get_fmask_info(struct radv_device *device,
469 struct radv_image *image,
470 unsigned nr_samples,
471 struct radv_fmask_info *out)
472 {
473 /* FMASK is allocated like an ordinary texture. */
474 struct radeon_surf fmask = {};
475 struct ac_surf_info info = image->info;
476 memset(out, 0, sizeof(*out));
477
478 fmask.blk_w = image->surface.blk_w;
479 fmask.blk_h = image->surface.blk_h;
480 info.samples = 1;
481 fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
482
483 /* Force 2D tiling if it wasn't set. This may occur when creating
484 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
485 * destination buffer must have an FMASK too. */
486 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
487 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
488
489 switch (nr_samples) {
490 case 2:
491 case 4:
492 fmask.bpe = 1;
493 break;
494 case 8:
495 fmask.bpe = 4;
496 break;
497 default:
498 return;
499 }
500
501 device->ws->surface_init(device->ws, &info, &fmask);
502 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
503
504 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
505 if (out->slice_tile_max)
506 out->slice_tile_max -= 1;
507
508 out->tile_mode_index = fmask.u.legacy.tiling_index[0];
509 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
510 out->bank_height = fmask.u.legacy.bankh;
511 out->alignment = MAX2(256, fmask.surf_alignment);
512 out->size = fmask.surf_size;
513 }
514
515 static void
516 radv_image_alloc_fmask(struct radv_device *device,
517 struct radv_image *image)
518 {
519 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
520
521 image->fmask.offset = align64(image->size, image->fmask.alignment);
522 image->size = image->fmask.offset + image->fmask.size;
523 image->alignment = MAX2(image->alignment, image->fmask.alignment);
524 }
525
526 static void
527 radv_image_get_cmask_info(struct radv_device *device,
528 struct radv_image *image,
529 struct radv_cmask_info *out)
530 {
531 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
532 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
533 unsigned cl_width, cl_height;
534
535 switch (num_pipes) {
536 case 2:
537 cl_width = 32;
538 cl_height = 16;
539 break;
540 case 4:
541 cl_width = 32;
542 cl_height = 32;
543 break;
544 case 8:
545 cl_width = 64;
546 cl_height = 32;
547 break;
548 case 16: /* Hawaii */
549 cl_width = 64;
550 cl_height = 64;
551 break;
552 default:
553 assert(0);
554 return;
555 }
556
557 unsigned base_align = num_pipes * pipe_interleave_bytes;
558
559 unsigned width = align(image->info.width, cl_width*8);
560 unsigned height = align(image->info.height, cl_height*8);
561 unsigned slice_elements = (width * height) / (8*8);
562
563 /* Each element of CMASK is a nibble. */
564 unsigned slice_bytes = slice_elements / 2;
565
566 out->slice_tile_max = (width * height) / (128*128);
567 if (out->slice_tile_max)
568 out->slice_tile_max -= 1;
569
570 out->alignment = MAX2(256, base_align);
571 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
572 align(slice_bytes, base_align);
573 }
574
575 static void
576 radv_image_alloc_cmask(struct radv_device *device,
577 struct radv_image *image)
578 {
579 radv_image_get_cmask_info(device, image, &image->cmask);
580
581 image->cmask.offset = align64(image->size, image->cmask.alignment);
582 /* + 8 for storing the clear values */
583 image->clear_value_offset = image->cmask.offset + image->cmask.size;
584 image->size = image->cmask.offset + image->cmask.size + 8;
585 image->alignment = MAX2(image->alignment, image->cmask.alignment);
586 }
587
588 static void
589 radv_image_alloc_dcc(struct radv_device *device,
590 struct radv_image *image)
591 {
592 image->dcc_offset = align64(image->size, image->surface.dcc_alignment);
593 /* + 8 for storing the clear values */
594 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size;
595 image->size = image->dcc_offset + image->surface.dcc_size + 8;
596 image->alignment = MAX2(image->alignment, image->surface.dcc_alignment);
597 }
598
599 static void
600 radv_image_alloc_htile(struct radv_device *device,
601 struct radv_image *image)
602 {
603 if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) {
604 image->surface.htile_size = 0;
605 return;
606 }
607
608 image->htile_offset = align64(image->size, image->surface.htile_alignment);
609
610 /* + 8 for storing the clear values */
611 image->clear_value_offset = image->htile_offset + image->surface.htile_size;
612 image->size = image->clear_value_offset + 8;
613 image->alignment = align64(image->alignment, image->surface.htile_alignment);
614 }
615
616 VkResult
617 radv_image_create(VkDevice _device,
618 const struct radv_image_create_info *create_info,
619 const VkAllocationCallbacks* alloc,
620 VkImage *pImage)
621 {
622 RADV_FROM_HANDLE(radv_device, device, _device);
623 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
624 struct radv_image *image = NULL;
625 bool can_cmask_dcc = false;
626 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
627
628 radv_assert(pCreateInfo->mipLevels > 0);
629 radv_assert(pCreateInfo->arrayLayers > 0);
630 radv_assert(pCreateInfo->samples > 0);
631 radv_assert(pCreateInfo->extent.width > 0);
632 radv_assert(pCreateInfo->extent.height > 0);
633 radv_assert(pCreateInfo->extent.depth > 0);
634
635 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
636 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
637 if (!image)
638 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
639
640 memset(image, 0, sizeof(*image));
641 image->type = pCreateInfo->imageType;
642 image->info.width = pCreateInfo->extent.width;
643 image->info.height = pCreateInfo->extent.height;
644 image->info.depth = pCreateInfo->extent.depth;
645 image->info.samples = pCreateInfo->samples;
646 image->info.array_size = pCreateInfo->arrayLayers;
647 image->info.levels = pCreateInfo->mipLevels;
648
649 image->vk_format = pCreateInfo->format;
650 image->tiling = pCreateInfo->tiling;
651 image->usage = pCreateInfo->usage;
652 image->flags = pCreateInfo->flags;
653
654 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
655 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
656 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
657 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL_KHX)
658 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
659 else
660 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
661 }
662
663 radv_init_surface(device, &image->surface, create_info);
664
665 device->ws->surface_init(device->ws, &image->info, &image->surface);
666
667 image->size = image->surface.surf_size;
668 image->alignment = image->surface.surf_alignment;
669
670 if (image->exclusive || image->queue_family_mask == 1)
671 can_cmask_dcc = true;
672
673 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
674 image->surface.dcc_size && can_cmask_dcc)
675 radv_image_alloc_dcc(device, image);
676 else
677 image->surface.dcc_size = 0;
678
679 if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) &&
680 pCreateInfo->mipLevels == 1 &&
681 !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc)
682 radv_image_alloc_cmask(device, image);
683 if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) {
684 radv_image_alloc_fmask(device, image);
685 } else if (vk_format_is_depth(pCreateInfo->format)) {
686
687 radv_image_alloc_htile(device, image);
688 }
689
690 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
691 image->alignment = MAX2(image->alignment, 4096);
692 image->size = align64(image->size, image->alignment);
693 image->offset = 0;
694
695 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
696 0, RADEON_FLAG_VIRTUAL);
697 if (!image->bo) {
698 vk_free2(&device->alloc, alloc, image);
699 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
700 }
701 }
702
703 *pImage = radv_image_to_handle(image);
704
705 return VK_SUCCESS;
706 }
707
708 void
709 radv_image_view_init(struct radv_image_view *iview,
710 struct radv_device *device,
711 const VkImageViewCreateInfo* pCreateInfo,
712 struct radv_cmd_buffer *cmd_buffer,
713 VkImageUsageFlags usage_mask)
714 {
715 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
716 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
717 uint32_t blk_w;
718 bool is_stencil = false;
719 switch (image->type) {
720 case VK_IMAGE_TYPE_1D:
721 case VK_IMAGE_TYPE_2D:
722 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
723 break;
724 case VK_IMAGE_TYPE_3D:
725 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
726 <= radv_minify(image->info.depth, range->baseMipLevel));
727 break;
728 default:
729 unreachable("bad VkImageType");
730 }
731 iview->image = image;
732 iview->bo = image->bo;
733 iview->type = pCreateInfo->viewType;
734 iview->vk_format = pCreateInfo->format;
735 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
736
737 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
738 is_stencil = true;
739 iview->vk_format = vk_format_stencil_only(iview->vk_format);
740 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
741 iview->vk_format = vk_format_depth_only(iview->vk_format);
742 }
743
744 iview->extent = (VkExtent3D) {
745 .width = radv_minify(image->info.width , range->baseMipLevel),
746 .height = radv_minify(image->info.height, range->baseMipLevel),
747 .depth = radv_minify(image->info.depth , range->baseMipLevel),
748 };
749
750 iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format),
751 vk_format_get_blockwidth(image->vk_format));
752 iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
753 vk_format_get_blockheight(image->vk_format));
754
755 assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0);
756 blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format);
757 iview->base_layer = range->baseArrayLayer;
758 iview->layer_count = radv_get_layerCount(image, range);
759 iview->base_mip = range->baseMipLevel;
760
761 si_make_texture_descriptor(device, image, false,
762 iview->type,
763 iview->vk_format,
764 &pCreateInfo->components,
765 0, radv_get_levelCount(image, range) - 1,
766 range->baseArrayLayer,
767 range->baseArrayLayer + radv_get_layerCount(image, range) - 1,
768 iview->extent.width,
769 iview->extent.height,
770 iview->extent.depth,
771 iview->descriptor,
772 iview->fmask_descriptor);
773 si_set_mutable_tex_desc_fields(device, image,
774 is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
775 : &image->surface.u.legacy.level[range->baseMipLevel],
776 range->baseMipLevel,
777 range->baseMipLevel,
778 blk_w, is_stencil, iview->descriptor);
779 }
780
781 bool radv_layout_has_htile(const struct radv_image *image,
782 VkImageLayout layout,
783 unsigned queue_mask)
784 {
785 return image->surface.htile_size &&
786 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
787 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
788 queue_mask == (1u << RADV_QUEUE_GENERAL);
789 }
790
791 bool radv_layout_is_htile_compressed(const struct radv_image *image,
792 VkImageLayout layout,
793 unsigned queue_mask)
794 {
795 return image->surface.htile_size &&
796 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
797 layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
798 queue_mask == (1u << RADV_QUEUE_GENERAL);
799 }
800
801 bool radv_layout_can_fast_clear(const struct radv_image *image,
802 VkImageLayout layout,
803 unsigned queue_mask)
804 {
805 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
806 queue_mask == (1u << RADV_QUEUE_GENERAL);
807 }
808
809
810 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
811 {
812 if (!image->exclusive)
813 return image->queue_family_mask;
814 if (family == VK_QUEUE_FAMILY_EXTERNAL_KHX)
815 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
816 if (family == VK_QUEUE_FAMILY_IGNORED)
817 return 1u << queue_family;
818 return 1u << family;
819 }
820
821 VkResult
822 radv_CreateImage(VkDevice device,
823 const VkImageCreateInfo *pCreateInfo,
824 const VkAllocationCallbacks *pAllocator,
825 VkImage *pImage)
826 {
827 return radv_image_create(device,
828 &(struct radv_image_create_info) {
829 .vk_info = pCreateInfo,
830 .scanout = false,
831 },
832 pAllocator,
833 pImage);
834 }
835
836 void
837 radv_DestroyImage(VkDevice _device, VkImage _image,
838 const VkAllocationCallbacks *pAllocator)
839 {
840 RADV_FROM_HANDLE(radv_device, device, _device);
841 RADV_FROM_HANDLE(radv_image, image, _image);
842
843 if (!image)
844 return;
845
846 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
847 device->ws->buffer_destroy(image->bo);
848
849 vk_free2(&device->alloc, pAllocator, image);
850 }
851
852 void radv_GetImageSubresourceLayout(
853 VkDevice device,
854 VkImage _image,
855 const VkImageSubresource* pSubresource,
856 VkSubresourceLayout* pLayout)
857 {
858 RADV_FROM_HANDLE(radv_image, image, _image);
859 int level = pSubresource->mipLevel;
860 int layer = pSubresource->arrayLayer;
861 struct radeon_surf *surface = &image->surface;
862
863 pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
864 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
865 pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
866 pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
867 pLayout->size = surface->u.legacy.level[level].slice_size;
868 if (image->type == VK_IMAGE_TYPE_3D)
869 pLayout->size *= u_minify(image->info.depth, level);
870 }
871
872
873 VkResult
874 radv_CreateImageView(VkDevice _device,
875 const VkImageViewCreateInfo *pCreateInfo,
876 const VkAllocationCallbacks *pAllocator,
877 VkImageView *pView)
878 {
879 RADV_FROM_HANDLE(radv_device, device, _device);
880 struct radv_image_view *view;
881
882 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
883 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
884 if (view == NULL)
885 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
886
887 radv_image_view_init(view, device, pCreateInfo, NULL, ~0);
888
889 *pView = radv_image_view_to_handle(view);
890
891 return VK_SUCCESS;
892 }
893
894 void
895 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
896 const VkAllocationCallbacks *pAllocator)
897 {
898 RADV_FROM_HANDLE(radv_device, device, _device);
899 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
900
901 if (!iview)
902 return;
903 vk_free2(&device->alloc, pAllocator, iview);
904 }
905
906 void radv_buffer_view_init(struct radv_buffer_view *view,
907 struct radv_device *device,
908 const VkBufferViewCreateInfo* pCreateInfo,
909 struct radv_cmd_buffer *cmd_buffer)
910 {
911 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
912
913 view->bo = buffer->bo;
914 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
915 buffer->size - pCreateInfo->offset : pCreateInfo->range;
916 view->vk_format = pCreateInfo->format;
917
918 radv_make_buffer_descriptor(device, buffer, view->vk_format,
919 pCreateInfo->offset, view->range, view->state);
920 }
921
922 VkResult
923 radv_CreateBufferView(VkDevice _device,
924 const VkBufferViewCreateInfo *pCreateInfo,
925 const VkAllocationCallbacks *pAllocator,
926 VkBufferView *pView)
927 {
928 RADV_FROM_HANDLE(radv_device, device, _device);
929 struct radv_buffer_view *view;
930
931 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
932 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
933 if (!view)
934 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
935
936 radv_buffer_view_init(view, device, pCreateInfo, NULL);
937
938 *pView = radv_buffer_view_to_handle(view);
939
940 return VK_SUCCESS;
941 }
942
943 void
944 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
945 const VkAllocationCallbacks *pAllocator)
946 {
947 RADV_FROM_HANDLE(radv_device, device, _device);
948 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
949
950 if (!view)
951 return;
952
953 vk_free2(&device->alloc, pAllocator, view);
954 }