radv: split metadata struct into legacy/gfx9 parts.

This is just ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 6f2f89c6e3891a0f66f221351e6747295a7fab33..376de71d755f0cf5fa404bd3ef5fd2979703fc1d 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -443,19 +443,23 @@ radv_init_metadata(struct radv_device *device,
        struct radeon_surf *surface = &image->surface;
 
        memset(metadata, 0, sizeof(*metadata));
-       metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
-               RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-       metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
-               RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
-       metadata->pipe_config = surface->u.legacy.pipe_config;
-       metadata->bankw = surface->u.legacy.bankw;
-       metadata->bankh = surface->u.legacy.bankh;
-       metadata->tile_split = surface->u.legacy.tile_split;
-       metadata->mtilea = surface->u.legacy.mtilea;
-       metadata->num_banks = surface->u.legacy.num_banks;
-       metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
-       metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
 
+       if (device->physical_device->rad_info.chip_class >= GFX9) {
+               metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+       } else {
+               metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
+                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+               metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
+                       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
+               metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
+               metadata->u.legacy.bankw = surface->u.legacy.bankw;
+               metadata->u.legacy.bankh = surface->u.legacy.bankh;
+               metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
+               metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
+               metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
+               metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
+               metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
+       }
        radv_query_opaque_metadata(device, image, metadata);
 }
 

diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h
index 397f28e3c46d4ce08999e24c7d8bd5ab3d377c7d..cdcaeca46eca6ac922e4af3918641d77cae2e971 100644 (file)
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -103,16 +103,25 @@ struct radeon_bo_metadata {
        /* Tiling flags describing the texture layout for display code
         * and DRI sharing.
         */
-       enum radeon_bo_layout   microtile;
-       enum radeon_bo_layout   macrotile;
-       unsigned                pipe_config;
-       unsigned                bankw;
-       unsigned                bankh;
-       unsigned                tile_split;
-       unsigned                mtilea;
-       unsigned                num_banks;
-       unsigned                stride;
-       bool                    scanout;
+       union {
+               struct {
+                       enum radeon_bo_layout   microtile;
+                       enum radeon_bo_layout   macrotile;
+                       unsigned                pipe_config;
+                       unsigned                bankw;
+                       unsigned                bankh;
+                       unsigned                tile_split;
+                       unsigned                mtilea;
+                       unsigned                num_banks;
+                       unsigned                stride;
+                       bool                    scanout;
+               } legacy;
+
+               struct {
+                       /* surface flags */
+                       unsigned swizzle_mode:5;
+               } gfx9;
+       } u;
 
        /* Additional metadata associated with the buffer, in bytes.
         * The maximum size is 64 * 4. This is opaque for the winsys & kernel.

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 7b679450cbc609c6cc192e59d205937721ca7606..5c374a238d67a8eee3b5d86cbc639d73f9f31f14 100644 (file)
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -467,25 +467,29 @@ radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys_bo *_bo,
        struct amdgpu_bo_metadata metadata = {0};
        uint32_t tiling_flags = 0;
 
-       if (md->macrotile == RADEON_LAYOUT_TILED)
-               tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
-       else if (md->microtile == RADEON_LAYOUT_TILED)
-               tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
-       else
-               tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
-
-       tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->pipe_config);
-       tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->bankw));
-       tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->bankh));
-       if (md->tile_split)
-               tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->tile_split));
-       tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->mtilea));
-       tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->num_banks)-1);
-
-       if (md->scanout)
-               tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
-       else
-               tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
+       if (bo->ws->info.chip_class >= GFX9) {
+               tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
+       } else {
+               if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
+                       tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
+               else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
+                       tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
+               else
+                       tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
+
+               tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
+               tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
+               tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
+               if (md->u.legacy.tile_split)
+                       tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split));
+               tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea));
+               tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(md->u.legacy.num_banks)-1);
+
+               if (md->u.legacy.scanout)
+                       tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 0); /* DISPLAY_MICRO_TILING */
+               else
+                       tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */
+       }
 
        metadata.tiling_info = tiling_flags;
        metadata.size_metadata = md->size_metadata;