android: aco: add support for libmesa_aco
[mesa.git] / src / amd / vulkan / radv_meta_resolve.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "radv_meta.h"
28 #include "radv_private.h"
29 #include "vk_format.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32
33 /* emit 0, 0, 0, 1 */
34 static nir_shader *
35 build_nir_fs(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39 nir_variable *f_color; /* vec4, fragment output color */
40
41 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
42 b.shader->info.name = ralloc_asprintf(b.shader,
43 "meta_resolve_fs");
44
45 f_color = nir_variable_create(b.shader, nir_var_shader_out, vec4,
46 "f_color");
47 f_color->data.location = FRAG_RESULT_DATA0;
48 nir_store_var(&b, f_color, nir_imm_vec4(&b, 0.0, 0.0, 0.0, 1.0), 0xf);
49
50 return b.shader;
51 }
52
53 static VkResult
54 create_pass(struct radv_device *device, VkFormat vk_format, VkRenderPass *pass)
55 {
56 VkResult result;
57 VkDevice device_h = radv_device_to_handle(device);
58 const VkAllocationCallbacks *alloc = &device->meta_state.alloc;
59 VkAttachmentDescription attachments[2];
60 int i;
61
62 for (i = 0; i < 2; i++) {
63 attachments[i].format = vk_format;
64 attachments[i].samples = 1;
65 attachments[i].loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
66 attachments[i].storeOp = VK_ATTACHMENT_STORE_OP_STORE;
67 }
68 attachments[0].initialLayout = VK_IMAGE_LAYOUT_GENERAL;
69 attachments[0].finalLayout = VK_IMAGE_LAYOUT_GENERAL;
70 attachments[1].initialLayout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
71 attachments[1].finalLayout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
72
73 result = radv_CreateRenderPass(device_h,
74 &(VkRenderPassCreateInfo) {
75 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
76 .attachmentCount = 2,
77 .pAttachments = attachments,
78 .subpassCount = 1,
79 .pSubpasses = &(VkSubpassDescription) {
80 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
81 .inputAttachmentCount = 0,
82 .colorAttachmentCount = 2,
83 .pColorAttachments = (VkAttachmentReference[]) {
84 {
85 .attachment = 0,
86 .layout = VK_IMAGE_LAYOUT_GENERAL,
87 },
88 {
89 .attachment = 1,
90 .layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL,
91 },
92 },
93 .pResolveAttachments = NULL,
94 .pDepthStencilAttachment = &(VkAttachmentReference) {
95 .attachment = VK_ATTACHMENT_UNUSED,
96 },
97 .preserveAttachmentCount = 0,
98 .pPreserveAttachments = NULL,
99 },
100 .dependencyCount = 0,
101 },
102 alloc,
103 pass);
104
105 return result;
106 }
107
108 static VkResult
109 create_pipeline(struct radv_device *device,
110 VkShaderModule vs_module_h,
111 VkPipeline *pipeline,
112 VkRenderPass pass)
113 {
114 VkResult result;
115 VkDevice device_h = radv_device_to_handle(device);
116
117 struct radv_shader_module fs_module = {
118 .nir = build_nir_fs(),
119 };
120
121 if (!fs_module.nir) {
122 /* XXX: Need more accurate error */
123 result = VK_ERROR_OUT_OF_HOST_MEMORY;
124 goto cleanup;
125 }
126
127 VkPipelineLayoutCreateInfo pl_create_info = {
128 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
129 .setLayoutCount = 0,
130 .pSetLayouts = NULL,
131 .pushConstantRangeCount = 0,
132 .pPushConstantRanges = NULL,
133 };
134
135 if (!device->meta_state.resolve.p_layout) {
136 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
137 &pl_create_info,
138 &device->meta_state.alloc,
139 &device->meta_state.resolve.p_layout);
140 if (result != VK_SUCCESS)
141 goto cleanup;
142 }
143
144 result = radv_graphics_pipeline_create(device_h,
145 radv_pipeline_cache_to_handle(&device->meta_state.cache),
146 &(VkGraphicsPipelineCreateInfo) {
147 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
148 .stageCount = 2,
149 .pStages = (VkPipelineShaderStageCreateInfo[]) {
150 {
151 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
152 .stage = VK_SHADER_STAGE_VERTEX_BIT,
153 .module = vs_module_h,
154 .pName = "main",
155 },
156 {
157 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
158 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
159 .module = radv_shader_module_to_handle(&fs_module),
160 .pName = "main",
161 },
162 },
163 .pVertexInputState = &(VkPipelineVertexInputStateCreateInfo) {
164 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
165 .vertexBindingDescriptionCount = 0,
166 .vertexAttributeDescriptionCount = 0,
167 },
168 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
169 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
170 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
171 .primitiveRestartEnable = false,
172 },
173 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
174 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
175 .viewportCount = 1,
176 .scissorCount = 1,
177 },
178 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
179 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
180 .depthClampEnable = false,
181 .rasterizerDiscardEnable = false,
182 .polygonMode = VK_POLYGON_MODE_FILL,
183 .cullMode = VK_CULL_MODE_NONE,
184 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE,
185 },
186 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
187 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
188 .rasterizationSamples = 1,
189 .sampleShadingEnable = false,
190 .pSampleMask = NULL,
191 .alphaToCoverageEnable = false,
192 .alphaToOneEnable = false,
193 },
194 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
195 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
196 .logicOpEnable = false,
197 .attachmentCount = 2,
198 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
199 {
200 .colorWriteMask = VK_COLOR_COMPONENT_R_BIT |
201 VK_COLOR_COMPONENT_G_BIT |
202 VK_COLOR_COMPONENT_B_BIT |
203 VK_COLOR_COMPONENT_A_BIT,
204 },
205 {
206 .colorWriteMask = 0,
207
208 }
209 },
210 },
211 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
212 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
213 .dynamicStateCount = 2,
214 .pDynamicStates = (VkDynamicState[]) {
215 VK_DYNAMIC_STATE_VIEWPORT,
216 VK_DYNAMIC_STATE_SCISSOR,
217 },
218 },
219 .layout = device->meta_state.resolve.p_layout,
220 .renderPass = pass,
221 .subpass = 0,
222 },
223 &(struct radv_graphics_pipeline_create_info) {
224 .use_rectlist = true,
225 .custom_blend_mode = V_028808_CB_RESOLVE,
226 },
227 &device->meta_state.alloc, pipeline);
228 if (result != VK_SUCCESS)
229 goto cleanup;
230
231 goto cleanup;
232
233 cleanup:
234 ralloc_free(fs_module.nir);
235 return result;
236 }
237
238 void
239 radv_device_finish_meta_resolve_state(struct radv_device *device)
240 {
241 struct radv_meta_state *state = &device->meta_state;
242
243 for (uint32_t j = 0; j < NUM_META_FS_KEYS; j++) {
244 radv_DestroyRenderPass(radv_device_to_handle(device),
245 state->resolve.pass[j], &state->alloc);
246 radv_DestroyPipeline(radv_device_to_handle(device),
247 state->resolve.pipeline[j], &state->alloc);
248 }
249 radv_DestroyPipelineLayout(radv_device_to_handle(device),
250 state->resolve.p_layout, &state->alloc);
251
252 }
253
254 VkResult
255 radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand)
256 {
257 if (on_demand)
258 return VK_SUCCESS;
259
260 VkResult res = VK_SUCCESS;
261 struct radv_meta_state *state = &device->meta_state;
262 struct radv_shader_module vs_module = { .nir = radv_meta_build_nir_vs_generate_vertices() };
263 if (!vs_module.nir) {
264 /* XXX: Need more accurate error */
265 res = VK_ERROR_OUT_OF_HOST_MEMORY;
266 goto fail;
267 }
268
269 for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) {
270 VkFormat format = radv_fs_key_format_exemplars[i];
271 unsigned fs_key = radv_format_meta_fs_key(format);
272 res = create_pass(device, format, &state->resolve.pass[fs_key]);
273 if (res != VK_SUCCESS)
274 goto fail;
275
276 VkShaderModule vs_module_h = radv_shader_module_to_handle(&vs_module);
277 res = create_pipeline(device, vs_module_h,
278 &state->resolve.pipeline[fs_key], state->resolve.pass[fs_key]);
279 if (res != VK_SUCCESS)
280 goto fail;
281 }
282
283 goto cleanup;
284
285 fail:
286 radv_device_finish_meta_resolve_state(device);
287
288 cleanup:
289 ralloc_free(vs_module.nir);
290
291 return res;
292 }
293
294 static void
295 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
296 VkFormat vk_format,
297 const VkOffset2D *dest_offset,
298 const VkExtent2D *resolve_extent)
299 {
300 struct radv_device *device = cmd_buffer->device;
301 VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
302 unsigned fs_key = radv_format_meta_fs_key(vk_format);
303
304 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
305
306 radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
307 device->meta_state.resolve.pipeline[fs_key]);
308
309 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
310 .x = dest_offset->x,
311 .y = dest_offset->y,
312 .width = resolve_extent->width,
313 .height = resolve_extent->height,
314 .minDepth = 0.0f,
315 .maxDepth = 1.0f
316 });
317
318 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
319 .offset = *dest_offset,
320 .extent = *resolve_extent,
321 });
322
323 radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
324 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
325 }
326
327 enum radv_resolve_method {
328 RESOLVE_HW,
329 RESOLVE_COMPUTE,
330 RESOLVE_FRAGMENT,
331 };
332
333 static void radv_pick_resolve_method_images(struct radv_device *device,
334 struct radv_image *src_image,
335 VkFormat src_format,
336 struct radv_image *dest_image,
337 VkImageLayout dest_image_layout,
338 bool dest_render_loop,
339 struct radv_cmd_buffer *cmd_buffer,
340 enum radv_resolve_method *method)
341
342 {
343 uint32_t queue_mask = radv_image_queue_family_mask(dest_image,
344 cmd_buffer->queue_family_index,
345 cmd_buffer->queue_family_index);
346
347 if (vk_format_is_color(src_format)) {
348 if (src_format == VK_FORMAT_R16G16_UNORM ||
349 src_format == VK_FORMAT_R16G16_SNORM)
350 *method = RESOLVE_COMPUTE;
351 else if (vk_format_is_int(src_format))
352 *method = RESOLVE_COMPUTE;
353 else if (src_image->info.array_size > 1 ||
354 dest_image->info.array_size > 1)
355 *method = RESOLVE_COMPUTE;
356
357 if (radv_layout_dcc_compressed(device, dest_image, dest_image_layout,
358 dest_render_loop, queue_mask)) {
359 *method = RESOLVE_FRAGMENT;
360 } else if (dest_image->planes[0].surface.micro_tile_mode !=
361 src_image->planes[0].surface.micro_tile_mode) {
362 *method = RESOLVE_COMPUTE;
363 }
364 } else {
365 if (src_image->info.array_size > 1 ||
366 dest_image->info.array_size > 1)
367 *method = RESOLVE_COMPUTE;
368 else
369 *method = RESOLVE_FRAGMENT;
370 }
371 }
372
373 static VkResult
374 build_resolve_pipeline(struct radv_device *device,
375 unsigned fs_key)
376 {
377 VkResult result = VK_SUCCESS;
378
379 if (device->meta_state.resolve.pipeline[fs_key])
380 return result;
381
382 mtx_lock(&device->meta_state.mtx);
383 if (device->meta_state.resolve.pipeline[fs_key]) {
384 mtx_unlock(&device->meta_state.mtx);
385 return result;
386 }
387
388 struct radv_shader_module vs_module = { .nir = radv_meta_build_nir_vs_generate_vertices() };
389
390 result = create_pass(device, radv_fs_key_format_exemplars[fs_key], &device->meta_state.resolve.pass[fs_key]);
391 if (result != VK_SUCCESS)
392 goto fail;
393
394 VkShaderModule vs_module_h = radv_shader_module_to_handle(&vs_module);
395 result = create_pipeline(device, vs_module_h, &device->meta_state.resolve.pipeline[fs_key], device->meta_state.resolve.pass[fs_key]);
396
397 fail:
398 ralloc_free(vs_module.nir);
399 mtx_unlock(&device->meta_state.mtx);
400 return result;
401 }
402
403 void radv_CmdResolveImage(
404 VkCommandBuffer cmd_buffer_h,
405 VkImage src_image_h,
406 VkImageLayout src_image_layout,
407 VkImage dest_image_h,
408 VkImageLayout dest_image_layout,
409 uint32_t region_count,
410 const VkImageResolve* regions)
411 {
412 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, cmd_buffer_h);
413 RADV_FROM_HANDLE(radv_image, src_image, src_image_h);
414 RADV_FROM_HANDLE(radv_image, dest_image, dest_image_h);
415 struct radv_device *device = cmd_buffer->device;
416 struct radv_meta_saved_state saved_state;
417 VkDevice device_h = radv_device_to_handle(device);
418 enum radv_resolve_method resolve_method = RESOLVE_HW;
419 /* we can use the hw resolve only for single full resolves */
420 if (region_count == 1) {
421 if (regions[0].srcOffset.x ||
422 regions[0].srcOffset.y ||
423 regions[0].srcOffset.z)
424 resolve_method = RESOLVE_COMPUTE;
425 if (regions[0].dstOffset.x ||
426 regions[0].dstOffset.y ||
427 regions[0].dstOffset.z)
428 resolve_method = RESOLVE_COMPUTE;
429
430 if (regions[0].extent.width != src_image->info.width ||
431 regions[0].extent.height != src_image->info.height ||
432 regions[0].extent.depth != src_image->info.depth)
433 resolve_method = RESOLVE_COMPUTE;
434 } else
435 resolve_method = RESOLVE_COMPUTE;
436
437 radv_pick_resolve_method_images(cmd_buffer->device, src_image,
438 src_image->vk_format, dest_image,
439 dest_image_layout, false, cmd_buffer,
440 &resolve_method);
441
442 if (resolve_method == RESOLVE_FRAGMENT) {
443 radv_meta_resolve_fragment_image(cmd_buffer,
444 src_image,
445 src_image_layout,
446 dest_image,
447 dest_image_layout,
448 region_count, regions);
449 return;
450 }
451
452 if (resolve_method == RESOLVE_COMPUTE) {
453 radv_meta_resolve_compute_image(cmd_buffer,
454 src_image,
455 src_image->vk_format,
456 src_image_layout,
457 dest_image,
458 dest_image->vk_format,
459 dest_image_layout,
460 region_count, regions);
461 return;
462 }
463
464 radv_meta_save(&saved_state, cmd_buffer,
465 RADV_META_SAVE_GRAPHICS_PIPELINE);
466
467 assert(src_image->info.samples > 1);
468 if (src_image->info.samples <= 1) {
469 /* this causes GPU hangs if we get past here */
470 fprintf(stderr, "radv: Illegal resolve operation (src not multisampled), will hang GPU.");
471 return;
472 }
473 assert(dest_image->info.samples == 1);
474
475 if (src_image->info.array_size > 1)
476 radv_finishme("vkCmdResolveImage: multisample array images");
477
478 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
479 for (uint32_t r = 0; r < region_count; ++r) {
480 const VkImageResolve *region = &regions[r];
481
482 /* From the Vulkan 1.0 spec:
483 *
484 * - The aspectMask member of srcSubresource and dstSubresource must
485 * only contain VK_IMAGE_ASPECT_COLOR_BIT
486 *
487 * - The layerCount member of srcSubresource and dstSubresource must
488 * match
489 */
490 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
491 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
492 assert(region->srcSubresource.layerCount ==
493 region->dstSubresource.layerCount);
494
495 const uint32_t src_base_layer =
496 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
497 &region->srcOffset);
498
499 const uint32_t dest_base_layer =
500 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
501 &region->dstOffset);
502
503 /**
504 * From Vulkan 1.0.6 spec: 18.6 Resolving Multisample Images
505 *
506 * extent is the size in texels of the source image to resolve in width,
507 * height and depth. 1D images use only x and width. 2D images use x, y,
508 * width and height. 3D images use x, y, z, width, height and depth.
509 *
510 * srcOffset and dstOffset select the initial x, y, and z offsets in
511 * texels of the sub-regions of the source and destination image data.
512 * extent is the size in texels of the source image to resolve in width,
513 * height and depth. 1D images use only x and width. 2D images use x, y,
514 * width and height. 3D images use x, y, z, width, height and depth.
515 */
516 const struct VkExtent3D extent =
517 radv_sanitize_image_extent(src_image->type, region->extent);
518 const struct VkOffset3D dstOffset =
519 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
520
521 if (radv_dcc_enabled(dest_image, region->dstSubresource.mipLevel)) {
522 VkImageSubresourceRange range = {
523 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
524 .baseMipLevel = region->dstSubresource.mipLevel,
525 .levelCount = 1,
526 .baseArrayLayer = dest_base_layer,
527 .layerCount = region->dstSubresource.layerCount,
528 };
529
530 radv_initialize_dcc(cmd_buffer, dest_image, &range, 0xffffffff);
531 }
532
533 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
534 ++layer) {
535
536 VkResult ret = build_resolve_pipeline(device, fs_key);
537 if (ret != VK_SUCCESS) {
538 cmd_buffer->record_result = ret;
539 break;
540 }
541
542 struct radv_image_view src_iview;
543 radv_image_view_init(&src_iview, cmd_buffer->device,
544 &(VkImageViewCreateInfo) {
545 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
546 .image = src_image_h,
547 .viewType = radv_meta_get_view_type(src_image),
548 .format = src_image->vk_format,
549 .subresourceRange = {
550 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
551 .baseMipLevel = region->srcSubresource.mipLevel,
552 .levelCount = 1,
553 .baseArrayLayer = src_base_layer + layer,
554 .layerCount = 1,
555 },
556 }, NULL);
557
558 struct radv_image_view dest_iview;
559 radv_image_view_init(&dest_iview, cmd_buffer->device,
560 &(VkImageViewCreateInfo) {
561 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
562 .image = dest_image_h,
563 .viewType = radv_meta_get_view_type(dest_image),
564 .format = dest_image->vk_format,
565 .subresourceRange = {
566 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
567 .baseMipLevel = region->dstSubresource.mipLevel,
568 .levelCount = 1,
569 .baseArrayLayer = dest_base_layer + layer,
570 .layerCount = 1,
571 },
572 }, NULL);
573
574 VkFramebuffer fb_h;
575 radv_CreateFramebuffer(device_h,
576 &(VkFramebufferCreateInfo) {
577 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
578 .attachmentCount = 2,
579 .pAttachments = (VkImageView[]) {
580 radv_image_view_to_handle(&src_iview),
581 radv_image_view_to_handle(&dest_iview),
582 },
583 .width = radv_minify(dest_image->info.width,
584 region->dstSubresource.mipLevel),
585 .height = radv_minify(dest_image->info.height,
586 region->dstSubresource.mipLevel),
587 .layers = 1
588 },
589 &cmd_buffer->pool->alloc,
590 &fb_h);
591
592 radv_CmdBeginRenderPass(cmd_buffer_h,
593 &(VkRenderPassBeginInfo) {
594 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
595 .renderPass = device->meta_state.resolve.pass[fs_key],
596 .framebuffer = fb_h,
597 .renderArea = {
598 .offset = {
599 dstOffset.x,
600 dstOffset.y,
601 },
602 .extent = {
603 extent.width,
604 extent.height,
605 }
606 },
607 .clearValueCount = 0,
608 .pClearValues = NULL,
609 },
610 VK_SUBPASS_CONTENTS_INLINE);
611
612 emit_resolve(cmd_buffer,
613 dest_iview.vk_format,
614 &(VkOffset2D) {
615 .x = dstOffset.x,
616 .y = dstOffset.y,
617 },
618 &(VkExtent2D) {
619 .width = extent.width,
620 .height = extent.height,
621 });
622
623 radv_CmdEndRenderPass(cmd_buffer_h);
624
625 radv_DestroyFramebuffer(device_h, fb_h,
626 &cmd_buffer->pool->alloc);
627 }
628 }
629
630 radv_meta_restore(&saved_state, cmd_buffer);
631 }
632
633 /**
634 * Emit any needed resolves for the current subpass.
635 */
636 void
637 radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
638 {
639 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
640 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
641 struct radv_meta_saved_state saved_state;
642 enum radv_resolve_method resolve_method = RESOLVE_HW;
643
644 if (subpass->ds_resolve_attachment) {
645 struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
646 struct radv_subpass_attachment dst_att = *subpass->ds_resolve_attachment;
647 struct radv_image_view *src_iview =
648 cmd_buffer->state.attachments[src_att.attachment].iview;
649 struct radv_image_view *dst_iview =
650 cmd_buffer->state.attachments[dst_att.attachment].iview;
651
652 radv_pick_resolve_method_images(cmd_buffer->device,
653 src_iview->image,
654 src_iview->vk_format,
655 dst_iview->image,
656 dst_att.layout,
657 dst_att.in_render_loop,
658 cmd_buffer,
659 &resolve_method);
660
661 if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
662 subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
663 if (resolve_method == RESOLVE_FRAGMENT) {
664 radv_depth_stencil_resolve_subpass_fs(cmd_buffer,
665 VK_IMAGE_ASPECT_DEPTH_BIT,
666 subpass->depth_resolve_mode);
667 } else {
668 assert(resolve_method == RESOLVE_COMPUTE);
669 radv_depth_stencil_resolve_subpass_cs(cmd_buffer,
670 VK_IMAGE_ASPECT_DEPTH_BIT,
671 subpass->depth_resolve_mode);
672 }
673 }
674
675 if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) &&
676 subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
677 if (resolve_method == RESOLVE_FRAGMENT) {
678 radv_depth_stencil_resolve_subpass_fs(cmd_buffer,
679 VK_IMAGE_ASPECT_STENCIL_BIT,
680 subpass->stencil_resolve_mode);
681 } else {
682 assert(resolve_method == RESOLVE_COMPUTE);
683 radv_depth_stencil_resolve_subpass_cs(cmd_buffer,
684 VK_IMAGE_ASPECT_STENCIL_BIT,
685 subpass->stencil_resolve_mode);
686 }
687 }
688 }
689
690 if (!subpass->has_color_resolve)
691 return;
692
693 for (uint32_t i = 0; i < subpass->color_count; ++i) {
694 struct radv_subpass_attachment src_att = subpass->color_attachments[i];
695 struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
696
697 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
698 continue;
699
700 /* Make sure to not clear color attachments after resolves. */
701 cmd_buffer->state.attachments[dest_att.attachment].pending_clear_aspects = 0;
702
703 struct radv_image *dst_img = cmd_buffer->state.attachments[dest_att.attachment].iview->image;
704 struct radv_image_view *src_iview= cmd_buffer->state.attachments[src_att.attachment].iview;
705 struct radv_image *src_img = src_iview->image;
706
707 radv_pick_resolve_method_images(cmd_buffer->device, src_img,
708 src_iview->vk_format, dst_img,
709 dest_att.layout,
710 dest_att.in_render_loop,
711 cmd_buffer, &resolve_method);
712
713 if (resolve_method == RESOLVE_FRAGMENT) {
714 break;
715 }
716 }
717
718 if (resolve_method == RESOLVE_COMPUTE) {
719 radv_cmd_buffer_resolve_subpass_cs(cmd_buffer);
720 return;
721 } else if (resolve_method == RESOLVE_FRAGMENT) {
722 radv_cmd_buffer_resolve_subpass_fs(cmd_buffer);
723 return;
724 }
725
726 radv_meta_save(&saved_state, cmd_buffer,
727 RADV_META_SAVE_GRAPHICS_PIPELINE);
728
729 for (uint32_t i = 0; i < subpass->color_count; ++i) {
730 struct radv_subpass_attachment src_att = subpass->color_attachments[i];
731 struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
732
733 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
734 continue;
735
736 struct radv_image_view *dest_iview = cmd_buffer->state.attachments[dest_att.attachment].iview;
737 struct radv_image *dst_img = dest_iview->image;
738
739 if (radv_dcc_enabled(dst_img, dest_iview->base_mip)) {
740 VkImageSubresourceRange range = {
741 .aspectMask = dest_iview->aspect_mask,
742 .baseMipLevel = dest_iview->base_mip,
743 .levelCount = dest_iview->level_count,
744 .baseArrayLayer = dest_iview->base_layer,
745 .layerCount = dest_iview->layer_count,
746 };
747
748 radv_initialize_dcc(cmd_buffer, dst_img, &range, 0xffffffff);
749 cmd_buffer->state.attachments[dest_att.attachment].current_layout = VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
750 }
751
752 struct radv_subpass resolve_subpass = {
753 .color_count = 2,
754 .color_attachments = (struct radv_subpass_attachment[]) { src_att, dest_att },
755 .depth_stencil_attachment = NULL,
756 };
757
758 radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
759
760 VkResult ret = build_resolve_pipeline(cmd_buffer->device, radv_format_meta_fs_key(dest_iview->vk_format));
761 if (ret != VK_SUCCESS) {
762 cmd_buffer->record_result = ret;
763 continue;
764 }
765
766 emit_resolve(cmd_buffer,
767 dest_iview->vk_format,
768 &(VkOffset2D) { 0, 0 },
769 &(VkExtent2D) { fb->width, fb->height });
770 }
771
772 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
773
774 radv_meta_restore(&saved_state, cmd_buffer);
775 }
776
777 /**
778 * Decompress CMask/FMask before resolving a multisampled source image inside a
779 * subpass.
780 */
781 void
782 radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
783 {
784 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
785 struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
786 uint32_t layer_count = fb->layers;
787
788 if (subpass->view_mask)
789 layer_count = util_last_bit(subpass->view_mask);
790
791 for (uint32_t i = 0; i < subpass->color_count; ++i) {
792 struct radv_subpass_attachment src_att = subpass->color_attachments[i];
793 struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
794
795 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
796 continue;
797
798 struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
799 struct radv_image *src_image = src_iview->image;
800
801 VkImageResolve region = {};
802 region.srcSubresource.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
803 region.srcSubresource.mipLevel = 0;
804 region.srcSubresource.baseArrayLayer = src_iview->base_layer;
805 region.srcSubresource.layerCount = layer_count;
806
807 radv_decompress_resolve_src(cmd_buffer, src_image,
808 src_att.layout, 1, &region);
809 }
810
811 if (subpass->ds_resolve_attachment) {
812 struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
813 struct radv_image_view *src_iview = fb->attachments[src_att.attachment];
814 struct radv_image *src_image = src_iview->image;
815
816 VkImageResolve region = {};
817 region.srcSubresource.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
818 region.srcSubresource.mipLevel = 0;
819 region.srcSubresource.baseArrayLayer = src_iview->base_layer;
820 region.srcSubresource.layerCount = layer_count;
821
822 radv_decompress_resolve_src(cmd_buffer, src_image,
823 src_att.layout, 1, &region);
824 }
825 }
826
827 static struct radv_sample_locations_state *
828 radv_get_resolve_sample_locations(struct radv_cmd_buffer *cmd_buffer)
829 {
830 struct radv_cmd_state *state = &cmd_buffer->state;
831 uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
832
833 for (uint32_t i = 0; i < state->num_subpass_sample_locs; i++) {
834 if (state->subpass_sample_locs[i].subpass_idx == subpass_id)
835 return &state->subpass_sample_locs[i].sample_location;
836 }
837
838 return NULL;
839 }
840
841 /**
842 * Decompress CMask/FMask before resolving a multisampled source image.
843 */
844 void
845 radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer,
846 struct radv_image *src_image,
847 VkImageLayout src_image_layout,
848 uint32_t region_count,
849 const VkImageResolve *regions)
850 {
851 for (uint32_t r = 0; r < region_count; ++r) {
852 const VkImageResolve *region = &regions[r];
853 const uint32_t src_base_layer =
854 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
855 &region->srcOffset);
856
857 VkImageMemoryBarrier barrier = {};
858 barrier.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT;
859 barrier.dstAccessMask = VK_ACCESS_TRANSFER_READ_BIT;
860 barrier.oldLayout = src_image_layout;
861 barrier.newLayout = VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL;
862 barrier.image = radv_image_to_handle(src_image);
863 barrier.subresourceRange = (VkImageSubresourceRange) {
864 .aspectMask = region->srcSubresource.aspectMask,
865 .baseMipLevel = region->srcSubresource.mipLevel,
866 .levelCount = 1,
867 .baseArrayLayer = src_base_layer,
868 .layerCount = region->srcSubresource.layerCount,
869 };
870
871 if (src_image->flags & VK_IMAGE_CREATE_SAMPLE_LOCATIONS_COMPATIBLE_DEPTH_BIT_EXT) {
872 /* If the depth/stencil image uses different sample
873 * locations, we need them during HTILE decompressions.
874 */
875 struct radv_sample_locations_state *sample_locs =
876 radv_get_resolve_sample_locations(cmd_buffer);
877
878 barrier.pNext = &(VkSampleLocationsInfoEXT) {
879 .sType = VK_STRUCTURE_TYPE_SAMPLE_LOCATIONS_INFO_EXT,
880 .sampleLocationsPerPixel = sample_locs->per_pixel,
881 .sampleLocationGridSize = sample_locs->grid_size,
882 .sampleLocationsCount = sample_locs->count,
883 .pSampleLocations = sample_locs->locations,
884 };
885 }
886
887 radv_CmdPipelineBarrier(radv_cmd_buffer_to_handle(cmd_buffer),
888 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT,
889 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT,
890 false, 0, NULL, 0, NULL, 1, &barrier);
891 }
892 }