radv/meta: split out core part of resolve shader
[mesa.git] / src / amd / vulkan / radv_meta_resolve_cs.c
1 /*
2 * Copyright © 2016 Dave Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24
25 #include <assert.h>
26 #include <stdbool.h>
27
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
31 #include "sid.h"
32 #include "vk_format.h"
33
34 static nir_shader *
35 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
36 {
37 nir_builder b;
38 char name[64];
39 const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
40 false,
41 false,
42 GLSL_TYPE_FLOAT);
43 const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
44 false,
45 false,
46 GLSL_TYPE_FLOAT);
47 snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
48 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
49 b.shader->info->name = ralloc_strdup(b.shader, name);
50 b.shader->info->cs.local_size[0] = 16;
51 b.shader->info->cs.local_size[1] = 16;
52 b.shader->info->cs.local_size[2] = 1;
53
54 nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
55 sampler_type, "s_tex");
56 input_img->data.descriptor_set = 0;
57 input_img->data.binding = 0;
58
59 nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
60 img_type, "out_img");
61 output_img->data.descriptor_set = 0;
62 output_img->data.binding = 1;
63 nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
64 nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
65 nir_ssa_def *block_size = nir_imm_ivec4(&b,
66 b.shader->info->cs.local_size[0],
67 b.shader->info->cs.local_size[1],
68 b.shader->info->cs.local_size[2], 0);
69
70 nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
71
72 nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
73 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
74 src_offset->num_components = 2;
75 nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
76 nir_builder_instr_insert(&b, &src_offset->instr);
77
78 nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
79 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
80 dst_offset->num_components = 2;
81 nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
82 nir_builder_instr_insert(&b, &dst_offset->instr);
83
84 nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
85 nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
86
87 radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb, samples,
88 input_img, color, img_coord);
89
90 nir_ssa_def *outval = nir_load_var(&b, color);
91 nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
92 nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
93 store->src[0] = nir_src_for_ssa(coord);
94 store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
95 store->src[2] = nir_src_for_ssa(outval);
96 store->variables[0] = nir_deref_var_create(store, output_img);
97 nir_builder_instr_insert(&b, &store->instr);
98 return b.shader;
99 }
100
101
102 static VkResult
103 create_layout(struct radv_device *device)
104 {
105 VkResult result;
106 /*
107 * two descriptors one for the image being sampled
108 * one for the buffer being written.
109 */
110 VkDescriptorSetLayoutCreateInfo ds_create_info = {
111 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
112 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
113 .bindingCount = 2,
114 .pBindings = (VkDescriptorSetLayoutBinding[]) {
115 {
116 .binding = 0,
117 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
118 .descriptorCount = 1,
119 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
120 .pImmutableSamplers = NULL
121 },
122 {
123 .binding = 1,
124 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
125 .descriptorCount = 1,
126 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
127 .pImmutableSamplers = NULL
128 },
129 }
130 };
131
132 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
133 &ds_create_info,
134 &device->meta_state.alloc,
135 &device->meta_state.resolve_compute.ds_layout);
136 if (result != VK_SUCCESS)
137 goto fail;
138
139
140 VkPipelineLayoutCreateInfo pl_create_info = {
141 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
142 .setLayoutCount = 1,
143 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
144 .pushConstantRangeCount = 1,
145 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
146 };
147
148 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
149 &pl_create_info,
150 &device->meta_state.alloc,
151 &device->meta_state.resolve_compute.p_layout);
152 if (result != VK_SUCCESS)
153 goto fail;
154 return VK_SUCCESS;
155 fail:
156 return result;
157 }
158
159 static VkResult
160 create_resolve_pipeline(struct radv_device *device,
161 int samples,
162 bool is_integer,
163 bool is_srgb,
164 VkPipeline *pipeline)
165 {
166 VkResult result;
167 struct radv_shader_module cs = { .nir = NULL };
168
169 cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
170
171 /* compute shader */
172
173 VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
174 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
175 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
176 .module = radv_shader_module_to_handle(&cs),
177 .pName = "main",
178 .pSpecializationInfo = NULL,
179 };
180
181 VkComputePipelineCreateInfo vk_pipeline_info = {
182 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
183 .stage = pipeline_shader_stage,
184 .flags = 0,
185 .layout = device->meta_state.resolve_compute.p_layout,
186 };
187
188 result = radv_CreateComputePipelines(radv_device_to_handle(device),
189 radv_pipeline_cache_to_handle(&device->meta_state.cache),
190 1, &vk_pipeline_info, NULL,
191 pipeline);
192 if (result != VK_SUCCESS)
193 goto fail;
194
195 ralloc_free(cs.nir);
196 return VK_SUCCESS;
197 fail:
198 ralloc_free(cs.nir);
199 return result;
200 }
201
202 VkResult
203 radv_device_init_meta_resolve_compute_state(struct radv_device *device)
204 {
205 struct radv_meta_state *state = &device->meta_state;
206 VkResult res;
207 memset(&device->meta_state.resolve_compute, 0, sizeof(device->meta_state.resolve_compute));
208
209 res = create_layout(device);
210 if (res != VK_SUCCESS)
211 return res;
212
213 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
214 uint32_t samples = 1 << i;
215
216 res = create_resolve_pipeline(device, samples, false, false,
217 &state->resolve_compute.rc[i].pipeline);
218
219 res = create_resolve_pipeline(device, samples, true, false,
220 &state->resolve_compute.rc[i].i_pipeline);
221
222 res = create_resolve_pipeline(device, samples, false, true,
223 &state->resolve_compute.rc[i].srgb_pipeline);
224
225 }
226
227 return res;
228 }
229
230 void
231 radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
232 {
233 struct radv_meta_state *state = &device->meta_state;
234 for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
235 radv_DestroyPipeline(radv_device_to_handle(device),
236 state->resolve_compute.rc[i].pipeline,
237 &state->alloc);
238
239 radv_DestroyPipeline(radv_device_to_handle(device),
240 state->resolve_compute.rc[i].i_pipeline,
241 &state->alloc);
242
243 radv_DestroyPipeline(radv_device_to_handle(device),
244 state->resolve_compute.rc[i].srgb_pipeline,
245 &state->alloc);
246 }
247
248 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
249 state->resolve_compute.ds_layout,
250 &state->alloc);
251 radv_DestroyPipelineLayout(radv_device_to_handle(device),
252 state->resolve_compute.p_layout,
253 &state->alloc);
254 }
255
256 void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
257 struct radv_image *src_image,
258 VkImageLayout src_image_layout,
259 struct radv_image *dest_image,
260 VkImageLayout dest_image_layout,
261 uint32_t region_count,
262 const VkImageResolve *regions)
263 {
264 struct radv_device *device = cmd_buffer->device;
265 struct radv_meta_saved_compute_state saved_state;
266 const uint32_t samples = src_image->info.samples;
267 const uint32_t samples_log2 = ffs(samples) - 1;
268
269 for (uint32_t r = 0; r < region_count; ++r) {
270 const VkImageResolve *region = &regions[r];
271 const uint32_t src_base_layer =
272 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
273 &region->srcOffset);
274 VkImageSubresourceRange range;
275 range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
276 range.baseMipLevel = region->srcSubresource.mipLevel;
277 range.levelCount = 1;
278 range.baseArrayLayer = src_base_layer;
279 range.layerCount = region->srcSubresource.layerCount;
280 radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
281 }
282
283 radv_meta_save_compute(&saved_state, cmd_buffer, 16);
284
285 for (uint32_t r = 0; r < region_count; ++r) {
286 const VkImageResolve *region = &regions[r];
287
288 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
289 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
290 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
291
292 const uint32_t src_base_layer =
293 radv_meta_get_iview_layer(src_image, &region->srcSubresource,
294 &region->srcOffset);
295
296 const uint32_t dest_base_layer =
297 radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
298 &region->dstOffset);
299
300 const struct VkExtent3D extent =
301 radv_sanitize_image_extent(src_image->type, region->extent);
302 const struct VkOffset3D srcOffset =
303 radv_sanitize_image_offset(src_image->type, region->srcOffset);
304 const struct VkOffset3D dstOffset =
305 radv_sanitize_image_offset(dest_image->type, region->dstOffset);
306
307 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
308 ++layer) {
309
310 struct radv_image_view src_iview;
311 radv_image_view_init(&src_iview, cmd_buffer->device,
312 &(VkImageViewCreateInfo) {
313 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
314 .image = radv_image_to_handle(src_image),
315 .viewType = radv_meta_get_view_type(src_image),
316 .format = src_image->vk_format,
317 .subresourceRange = {
318 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
319 .baseMipLevel = region->srcSubresource.mipLevel,
320 .levelCount = 1,
321 .baseArrayLayer = src_base_layer + layer,
322 .layerCount = 1,
323 },
324 },
325 cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
326
327 struct radv_image_view dest_iview;
328 radv_image_view_init(&dest_iview, cmd_buffer->device,
329 &(VkImageViewCreateInfo) {
330 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
331 .image = radv_image_to_handle(dest_image),
332 .viewType = radv_meta_get_view_type(dest_image),
333 .format = dest_image->vk_format,
334 .subresourceRange = {
335 .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
336 .baseMipLevel = region->dstSubresource.mipLevel,
337 .levelCount = 1,
338 .baseArrayLayer = dest_base_layer + layer,
339 .layerCount = 1,
340 },
341 },
342 cmd_buffer, VK_IMAGE_USAGE_STORAGE_BIT);
343
344
345 radv_meta_push_descriptor_set(cmd_buffer,
346 VK_PIPELINE_BIND_POINT_COMPUTE,
347 device->meta_state.resolve_compute.p_layout,
348 0, /* set */
349 2, /* descriptorWriteCount */
350 (VkWriteDescriptorSet[]) {
351 {
352 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
353 .dstBinding = 0,
354 .dstArrayElement = 0,
355 .descriptorCount = 1,
356 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
357 .pImageInfo = (VkDescriptorImageInfo[]) {
358 {
359 .sampler = VK_NULL_HANDLE,
360 .imageView = radv_image_view_to_handle(&src_iview),
361 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
362 },
363 }
364 },
365 {
366 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
367 .dstBinding = 1,
368 .dstArrayElement = 0,
369 .descriptorCount = 1,
370 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
371 .pImageInfo = (VkDescriptorImageInfo[]) {
372 {
373 .sampler = VK_NULL_HANDLE,
374 .imageView = radv_image_view_to_handle(&dest_iview),
375 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
376 },
377 }
378 }
379 });
380
381 VkPipeline pipeline;
382 if (vk_format_is_int(src_image->vk_format))
383 pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
384 else if (vk_format_is_srgb(src_image->vk_format))
385 pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
386 else
387 pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
388 if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
389 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
390 VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
391 }
392
393 unsigned push_constants[4] = {
394 srcOffset.x,
395 srcOffset.y,
396 dstOffset.x,
397 dstOffset.y,
398 };
399 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
400 device->meta_state.resolve_compute.p_layout,
401 VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
402 push_constants);
403 radv_unaligned_dispatch(cmd_buffer, extent.width, extent.height, 1);
404 }
405 }
406 radv_meta_restore_compute(&saved_state, cmd_buffer, 16);
407 }