2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "util/xmlconfig.h"
52 #include "main/macros.h"
54 #include "vk_debug_report.h"
56 #include "radv_radeon_winsys.h"
57 #include "ac_binary.h"
58 #include "ac_nir_to_llvm.h"
59 #include "ac_gpu_info.h"
60 #include "ac_surface.h"
61 #include "ac_llvm_build.h"
62 #include "ac_llvm_util.h"
63 #include "radv_descriptor_set.h"
64 #include "radv_extensions.h"
67 #include <llvm-c/TargetMachine.h>
69 /* Pre-declarations needed for WSI entrypoints */
72 typedef struct xcb_connection_t xcb_connection_t
;
73 typedef uint32_t xcb_visualid_t
;
74 typedef uint32_t xcb_window_t
;
76 #include <vulkan/vulkan.h>
77 #include <vulkan/vulkan_intel.h>
78 #include <vulkan/vk_icd.h>
79 #include <vulkan/vk_android_native_buffer.h>
81 #include "radv_entrypoints.h"
83 #include "wsi_common.h"
84 #include "wsi_common_display.h"
87 unsigned img_format
:9;
89 /* Various formats are only supported with workarounds for vertex fetch,
90 * and some 32_32_32 formats are supported natively, but only for buffers
91 * (possibly with some image support, actually, but no filtering). */
95 #include "gfx10_format_table.h"
97 #define ATI_VENDOR_ID 0x1002
100 #define MAX_VERTEX_ATTRIBS 32
102 #define MAX_VIEWPORTS 16
103 #define MAX_SCISSORS 16
104 #define MAX_DISCARD_RECTANGLES 4
105 #define MAX_SAMPLE_LOCATIONS 32
106 #define MAX_PUSH_CONSTANTS_SIZE 128
107 #define MAX_PUSH_DESCRIPTORS 32
108 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
109 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
110 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
111 #define MAX_SAMPLES_LOG2 4
112 #define NUM_META_FS_KEYS 12
113 #define RADV_MAX_DRM_DEVICES 8
115 #define MAX_SO_STREAMS 4
116 #define MAX_SO_BUFFERS 4
117 #define MAX_SO_OUTPUTS 64
118 #define MAX_INLINE_UNIFORM_BLOCK_SIZE (4ull * 1024 * 1024)
119 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
121 #define NUM_DEPTH_CLEAR_PIPELINES 3
124 * This is the point we switch from using CP to compute shader
125 * for certain buffer operations.
127 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
129 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
133 RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
140 RADV_MEM_TYPE_GTT_WRITE_COMBINE
,
141 RADV_MEM_TYPE_VRAM_CPU_ACCESS
,
142 RADV_MEM_TYPE_GTT_CACHED
,
146 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
148 static inline uint32_t
149 align_u32(uint32_t v
, uint32_t a
)
151 assert(a
!= 0 && a
== (a
& -a
));
152 return (v
+ a
- 1) & ~(a
- 1);
155 static inline uint32_t
156 align_u32_npot(uint32_t v
, uint32_t a
)
158 return (v
+ a
- 1) / a
* a
;
161 static inline uint64_t
162 align_u64(uint64_t v
, uint64_t a
)
164 assert(a
!= 0 && a
== (a
& -a
));
165 return (v
+ a
- 1) & ~(a
- 1);
168 static inline int32_t
169 align_i32(int32_t v
, int32_t a
)
171 assert(a
!= 0 && a
== (a
& -a
));
172 return (v
+ a
- 1) & ~(a
- 1);
175 /** Alignment must be a power of 2. */
177 radv_is_aligned(uintmax_t n
, uintmax_t a
)
179 assert(a
== (a
& -a
));
180 return (n
& (a
- 1)) == 0;
183 static inline uint32_t
184 round_up_u32(uint32_t v
, uint32_t a
)
186 return (v
+ a
- 1) / a
;
189 static inline uint64_t
190 round_up_u64(uint64_t v
, uint64_t a
)
192 return (v
+ a
- 1) / a
;
195 static inline uint32_t
196 radv_minify(uint32_t n
, uint32_t levels
)
198 if (unlikely(n
== 0))
201 return MAX2(n
>> levels
, 1);
204 radv_clamp_f(float f
, float min
, float max
)
217 radv_clear_mask(uint32_t *inout_mask
, uint32_t clear_mask
)
219 if (*inout_mask
& clear_mask
) {
220 *inout_mask
&= ~clear_mask
;
227 #define for_each_bit(b, dword) \
228 for (uint32_t __dword = (dword); \
229 (b) = __builtin_ffs(__dword) - 1, __dword; \
230 __dword &= ~(1 << (b)))
232 #define typed_memcpy(dest, src, count) ({ \
233 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
234 memcpy((dest), (src), (count) * sizeof(*(src))); \
237 /* Whenever we generate an error, pass it through this function. Useful for
238 * debugging, where we can break on it. Only call at error site, not when
239 * propagating errors. Might be useful to plug in a stack trace here.
242 struct radv_instance
;
244 VkResult
__vk_errorf(struct radv_instance
*instance
, VkResult error
, const char *file
, int line
, const char *format
, ...);
246 #define vk_error(instance, error) __vk_errorf(instance, error, __FILE__, __LINE__, NULL);
247 #define vk_errorf(instance, error, format, ...) __vk_errorf(instance, error, __FILE__, __LINE__, format, ## __VA_ARGS__);
249 void __radv_finishme(const char *file
, int line
, const char *format
, ...)
250 radv_printflike(3, 4);
251 void radv_loge(const char *format
, ...) radv_printflike(1, 2);
252 void radv_loge_v(const char *format
, va_list va
);
253 void radv_logi(const char *format
, ...) radv_printflike(1, 2);
254 void radv_logi_v(const char *format
, va_list va
);
257 * Print a FINISHME message, including its source location.
259 #define radv_finishme(format, ...) \
261 static bool reported = false; \
263 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
268 /* A non-fatal assert. Useful for debugging. */
270 #define radv_assert(x) ({ \
271 if (unlikely(!(x))) \
272 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
275 #define radv_assert(x)
278 #define stub_return(v) \
280 radv_finishme("stub %s", __func__); \
286 radv_finishme("stub %s", __func__); \
290 void *radv_lookup_entrypoint_unchecked(const char *name
);
291 void *radv_lookup_entrypoint_checked(const char *name
,
292 uint32_t core_version
,
293 const struct radv_instance_extension_table
*instance
,
294 const struct radv_device_extension_table
*device
);
295 void *radv_lookup_physical_device_entrypoint_checked(const char *name
,
296 uint32_t core_version
,
297 const struct radv_instance_extension_table
*instance
);
299 struct radv_physical_device
{
300 VK_LOADER_DATA _loader_data
;
302 struct radv_instance
* instance
;
304 struct radeon_winsys
*ws
;
305 struct radeon_info rad_info
;
306 char name
[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE
];
307 uint8_t driver_uuid
[VK_UUID_SIZE
];
308 uint8_t device_uuid
[VK_UUID_SIZE
];
309 uint8_t cache_uuid
[VK_UUID_SIZE
];
313 struct wsi_device wsi_device
;
315 bool has_rbplus
; /* if RB+ register exist */
316 bool rbplus_allowed
; /* if RB+ is allowed */
317 bool has_clear_state
;
318 bool cpdma_prefetch_writes_memory
;
319 bool has_scissor_bug
;
320 bool has_tc_compat_zrange_bug
;
322 bool has_out_of_order_rast
;
323 bool out_of_order_rast_allowed
;
325 /* Whether DCC should be enabled for MSAA textures. */
326 bool dcc_msaa_allowed
;
328 /* Whether LOAD_CONTEXT_REG packets are supported. */
329 bool has_load_ctx_reg_pkt
;
331 /* Whether to enable the AMD_shader_ballot extension */
332 bool use_shader_ballot
;
334 /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
335 bool has_dcc_constant_encode
;
337 /* This is the drivers on-disk cache used as a fallback as opposed to
338 * the pipeline cache defined by apps.
340 struct disk_cache
* disk_cache
;
342 VkPhysicalDeviceMemoryProperties memory_properties
;
343 enum radv_mem_type mem_type_indices
[RADV_MEM_TYPE_COUNT
];
345 drmPciBusInfo bus_info
;
347 struct radv_device_extension_table supported_extensions
;
350 struct radv_instance
{
351 VK_LOADER_DATA _loader_data
;
353 VkAllocationCallbacks alloc
;
356 int physicalDeviceCount
;
357 struct radv_physical_device physicalDevices
[RADV_MAX_DRM_DEVICES
];
359 uint64_t debug_flags
;
360 uint64_t perftest_flags
;
362 struct vk_debug_report_instance debug_report_callbacks
;
364 struct radv_instance_extension_table enabled_extensions
;
366 struct driOptionCache dri_options
;
367 struct driOptionCache available_dri_options
;
370 VkResult
radv_init_wsi(struct radv_physical_device
*physical_device
);
371 void radv_finish_wsi(struct radv_physical_device
*physical_device
);
373 bool radv_instance_extension_supported(const char *name
);
374 uint32_t radv_physical_device_api_version(struct radv_physical_device
*dev
);
375 bool radv_physical_device_extension_supported(struct radv_physical_device
*dev
,
380 struct radv_pipeline_cache
{
381 struct radv_device
* device
;
382 pthread_mutex_t mutex
;
386 uint32_t kernel_count
;
387 struct cache_entry
** hash_table
;
390 VkAllocationCallbacks alloc
;
393 struct radv_pipeline_key
{
394 uint32_t instance_rate_inputs
;
395 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
396 uint8_t vertex_attribute_formats
[MAX_VERTEX_ATTRIBS
];
397 uint32_t vertex_attribute_bindings
[MAX_VERTEX_ATTRIBS
];
398 uint32_t vertex_attribute_offsets
[MAX_VERTEX_ATTRIBS
];
399 uint32_t vertex_attribute_strides
[MAX_VERTEX_ATTRIBS
];
400 uint64_t vertex_alpha_adjust
;
401 uint32_t vertex_post_shuffle
;
402 unsigned tess_input_vertices
;
406 uint8_t log2_ps_iter_samples
;
408 uint32_t has_multiview_view_index
: 1;
409 uint32_t optimisations_disabled
: 1;
412 struct radv_shader_binary
;
413 struct radv_shader_variant
;
416 radv_pipeline_cache_init(struct radv_pipeline_cache
*cache
,
417 struct radv_device
*device
);
419 radv_pipeline_cache_finish(struct radv_pipeline_cache
*cache
);
421 radv_pipeline_cache_load(struct radv_pipeline_cache
*cache
,
422 const void *data
, size_t size
);
425 radv_create_shader_variants_from_pipeline_cache(struct radv_device
*device
,
426 struct radv_pipeline_cache
*cache
,
427 const unsigned char *sha1
,
428 struct radv_shader_variant
**variants
,
429 bool *found_in_application_cache
);
432 radv_pipeline_cache_insert_shaders(struct radv_device
*device
,
433 struct radv_pipeline_cache
*cache
,
434 const unsigned char *sha1
,
435 struct radv_shader_variant
**variants
,
436 struct radv_shader_binary
*const *binaries
);
438 enum radv_blit_ds_layout
{
439 RADV_BLIT_DS_LAYOUT_TILE_ENABLE
,
440 RADV_BLIT_DS_LAYOUT_TILE_DISABLE
,
441 RADV_BLIT_DS_LAYOUT_COUNT
,
444 static inline enum radv_blit_ds_layout
radv_meta_blit_ds_to_type(VkImageLayout layout
)
446 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE
: RADV_BLIT_DS_LAYOUT_TILE_ENABLE
;
449 static inline VkImageLayout
radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout
)
451 return ds_layout
== RADV_BLIT_DS_LAYOUT_TILE_ENABLE
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
454 enum radv_meta_dst_layout
{
455 RADV_META_DST_LAYOUT_GENERAL
,
456 RADV_META_DST_LAYOUT_OPTIMAL
,
457 RADV_META_DST_LAYOUT_COUNT
,
460 static inline enum radv_meta_dst_layout
radv_meta_dst_layout_from_layout(VkImageLayout layout
)
462 return (layout
== VK_IMAGE_LAYOUT_GENERAL
) ? RADV_META_DST_LAYOUT_GENERAL
: RADV_META_DST_LAYOUT_OPTIMAL
;
465 static inline VkImageLayout
radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout
)
467 return layout
== RADV_META_DST_LAYOUT_OPTIMAL
? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
: VK_IMAGE_LAYOUT_GENERAL
;
470 struct radv_meta_state
{
471 VkAllocationCallbacks alloc
;
473 struct radv_pipeline_cache cache
;
476 * For on-demand pipeline creation, makes sure that
477 * only one thread tries to build a pipeline at the same time.
482 * Use array element `i` for images with `2^i` samples.
485 VkRenderPass render_pass
[NUM_META_FS_KEYS
];
486 VkPipeline color_pipelines
[NUM_META_FS_KEYS
];
488 VkRenderPass depthstencil_rp
;
489 VkPipeline depth_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
490 VkPipeline stencil_only_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
491 VkPipeline depthstencil_pipeline
[NUM_DEPTH_CLEAR_PIPELINES
];
492 } clear
[1 + MAX_SAMPLES_LOG2
];
494 VkPipelineLayout clear_color_p_layout
;
495 VkPipelineLayout clear_depth_p_layout
;
497 /* Optimized compute fast HTILE clear for stencil or depth only. */
498 VkPipeline clear_htile_mask_pipeline
;
499 VkPipelineLayout clear_htile_mask_p_layout
;
500 VkDescriptorSetLayout clear_htile_mask_ds_layout
;
503 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
505 /** Pipeline that blits from a 1D image. */
506 VkPipeline pipeline_1d_src
[NUM_META_FS_KEYS
];
508 /** Pipeline that blits from a 2D image. */
509 VkPipeline pipeline_2d_src
[NUM_META_FS_KEYS
];
511 /** Pipeline that blits from a 3D image. */
512 VkPipeline pipeline_3d_src
[NUM_META_FS_KEYS
];
514 VkRenderPass depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
515 VkPipeline depth_only_1d_pipeline
;
516 VkPipeline depth_only_2d_pipeline
;
517 VkPipeline depth_only_3d_pipeline
;
519 VkRenderPass stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
520 VkPipeline stencil_only_1d_pipeline
;
521 VkPipeline stencil_only_2d_pipeline
;
522 VkPipeline stencil_only_3d_pipeline
;
523 VkPipelineLayout pipeline_layout
;
524 VkDescriptorSetLayout ds_layout
;
528 VkPipelineLayout p_layouts
[5];
529 VkDescriptorSetLayout ds_layouts
[5];
530 VkPipeline pipelines
[5][NUM_META_FS_KEYS
];
532 VkPipeline depth_only_pipeline
[5];
534 VkPipeline stencil_only_pipeline
[5];
535 } blit2d
[1 + MAX_SAMPLES_LOG2
];
537 VkRenderPass blit2d_render_passes
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
538 VkRenderPass blit2d_depth_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
539 VkRenderPass blit2d_stencil_only_rp
[RADV_BLIT_DS_LAYOUT_COUNT
];
542 VkPipelineLayout img_p_layout
;
543 VkDescriptorSetLayout img_ds_layout
;
545 VkPipeline pipeline_3d
;
548 VkPipelineLayout img_p_layout
;
549 VkDescriptorSetLayout img_ds_layout
;
551 VkPipeline pipeline_3d
;
554 VkPipelineLayout img_p_layout
;
555 VkDescriptorSetLayout img_ds_layout
;
559 VkPipelineLayout img_p_layout
;
560 VkDescriptorSetLayout img_ds_layout
;
562 VkPipeline pipeline_3d
;
565 VkPipelineLayout img_p_layout
;
566 VkDescriptorSetLayout img_ds_layout
;
570 VkPipelineLayout img_p_layout
;
571 VkDescriptorSetLayout img_ds_layout
;
573 VkPipeline pipeline_3d
;
576 VkPipelineLayout img_p_layout
;
577 VkDescriptorSetLayout img_ds_layout
;
582 VkPipelineLayout p_layout
;
583 VkPipeline pipeline
[NUM_META_FS_KEYS
];
584 VkRenderPass pass
[NUM_META_FS_KEYS
];
588 VkDescriptorSetLayout ds_layout
;
589 VkPipelineLayout p_layout
;
592 VkPipeline i_pipeline
;
593 VkPipeline srgb_pipeline
;
594 } rc
[MAX_SAMPLES_LOG2
];
596 VkPipeline depth_zero_pipeline
;
598 VkPipeline average_pipeline
;
599 VkPipeline max_pipeline
;
600 VkPipeline min_pipeline
;
601 } depth
[MAX_SAMPLES_LOG2
];
603 VkPipeline stencil_zero_pipeline
;
605 VkPipeline max_pipeline
;
606 VkPipeline min_pipeline
;
607 } stencil
[MAX_SAMPLES_LOG2
];
611 VkDescriptorSetLayout ds_layout
;
612 VkPipelineLayout p_layout
;
615 VkRenderPass render_pass
[NUM_META_FS_KEYS
][RADV_META_DST_LAYOUT_COUNT
];
616 VkPipeline pipeline
[NUM_META_FS_KEYS
];
617 } rc
[MAX_SAMPLES_LOG2
];
619 VkRenderPass depth_render_pass
;
620 VkPipeline depth_zero_pipeline
;
622 VkPipeline average_pipeline
;
623 VkPipeline max_pipeline
;
624 VkPipeline min_pipeline
;
625 } depth
[MAX_SAMPLES_LOG2
];
627 VkRenderPass stencil_render_pass
;
628 VkPipeline stencil_zero_pipeline
;
630 VkPipeline max_pipeline
;
631 VkPipeline min_pipeline
;
632 } stencil
[MAX_SAMPLES_LOG2
];
636 VkPipelineLayout p_layout
;
637 VkPipeline decompress_pipeline
;
638 VkPipeline resummarize_pipeline
;
640 } depth_decomp
[1 + MAX_SAMPLES_LOG2
];
643 VkPipelineLayout p_layout
;
644 VkPipeline cmask_eliminate_pipeline
;
645 VkPipeline fmask_decompress_pipeline
;
646 VkPipeline dcc_decompress_pipeline
;
649 VkDescriptorSetLayout dcc_decompress_compute_ds_layout
;
650 VkPipelineLayout dcc_decompress_compute_p_layout
;
651 VkPipeline dcc_decompress_compute_pipeline
;
655 VkPipelineLayout fill_p_layout
;
656 VkPipelineLayout copy_p_layout
;
657 VkDescriptorSetLayout fill_ds_layout
;
658 VkDescriptorSetLayout copy_ds_layout
;
659 VkPipeline fill_pipeline
;
660 VkPipeline copy_pipeline
;
664 VkDescriptorSetLayout ds_layout
;
665 VkPipelineLayout p_layout
;
666 VkPipeline occlusion_query_pipeline
;
667 VkPipeline pipeline_statistics_query_pipeline
;
668 VkPipeline tfb_query_pipeline
;
672 VkDescriptorSetLayout ds_layout
;
673 VkPipelineLayout p_layout
;
674 VkPipeline pipeline
[MAX_SAMPLES_LOG2
];
679 #define RADV_QUEUE_GENERAL 0
680 #define RADV_QUEUE_COMPUTE 1
681 #define RADV_QUEUE_TRANSFER 2
683 #define RADV_MAX_QUEUE_FAMILIES 3
685 enum ring_type
radv_queue_family_to_ring(int f
);
688 VK_LOADER_DATA _loader_data
;
689 struct radv_device
* device
;
690 struct radeon_winsys_ctx
*hw_ctx
;
691 enum radeon_ctx_priority priority
;
692 uint32_t queue_family_index
;
694 VkDeviceQueueCreateFlags flags
;
696 uint32_t scratch_size
;
697 uint32_t compute_scratch_size
;
698 uint32_t esgs_ring_size
;
699 uint32_t gsvs_ring_size
;
701 bool has_sample_positions
;
703 struct radeon_winsys_bo
*scratch_bo
;
704 struct radeon_winsys_bo
*descriptor_bo
;
705 struct radeon_winsys_bo
*compute_scratch_bo
;
706 struct radeon_winsys_bo
*esgs_ring_bo
;
707 struct radeon_winsys_bo
*gsvs_ring_bo
;
708 struct radeon_winsys_bo
*tess_rings_bo
;
709 struct radeon_cmdbuf
*initial_preamble_cs
;
710 struct radeon_cmdbuf
*initial_full_flush_preamble_cs
;
711 struct radeon_cmdbuf
*continue_preamble_cs
;
714 struct radv_bo_list
{
715 struct radv_winsys_bo_list list
;
717 pthread_mutex_t mutex
;
721 VK_LOADER_DATA _loader_data
;
723 VkAllocationCallbacks alloc
;
725 struct radv_instance
* instance
;
726 struct radeon_winsys
*ws
;
728 struct radv_meta_state meta_state
;
730 struct radv_queue
*queues
[RADV_MAX_QUEUE_FAMILIES
];
731 int queue_count
[RADV_MAX_QUEUE_FAMILIES
];
732 struct radeon_cmdbuf
*empty_cs
[RADV_MAX_QUEUE_FAMILIES
];
734 bool always_use_syncobj
;
735 bool has_distributed_tess
;
738 uint32_t tess_offchip_block_dw_size
;
739 uint32_t scratch_waves
;
740 uint32_t dispatch_initiator
;
742 uint32_t gs_table_depth
;
744 /* MSAA sample locations.
745 * The first index is the sample index.
746 * The second index is the coordinate: X, Y. */
747 float sample_locations_1x
[1][2];
748 float sample_locations_2x
[2][2];
749 float sample_locations_4x
[4][2];
750 float sample_locations_8x
[8][2];
753 uint32_t gfx_init_size_dw
;
754 struct radeon_winsys_bo
*gfx_init
;
756 struct radeon_winsys_bo
*trace_bo
;
757 uint32_t *trace_id_ptr
;
759 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
760 bool keep_shader_info
;
762 struct radv_physical_device
*physical_device
;
764 /* Backup in-memory cache to be used if the app doesn't provide one */
765 struct radv_pipeline_cache
* mem_cache
;
768 * use different counters so MSAA MRTs get consecutive surface indices,
769 * even if MASK is allocated in between.
771 uint32_t image_mrt_offset_counter
;
772 uint32_t fmask_mrt_offset_counter
;
773 struct list_head shader_slabs
;
774 mtx_t shader_slab_mutex
;
776 /* For detecting VM faults reported by dmesg. */
777 uint64_t dmesg_timestamp
;
779 struct radv_device_extension_table enabled_extensions
;
781 /* Whether the driver uses a global BO list. */
782 bool use_global_bo_list
;
784 struct radv_bo_list bo_list
;
786 /* Whether anisotropy is forced with RADV_TEX_ANISO (-1 is disabled). */
790 struct radv_device_memory
{
791 struct radeon_winsys_bo
*bo
;
792 /* for dedicated allocations */
793 struct radv_image
*image
;
794 struct radv_buffer
*buffer
;
796 VkDeviceSize map_size
;
802 struct radv_descriptor_range
{
807 struct radv_descriptor_set
{
808 const struct radv_descriptor_set_layout
*layout
;
811 struct radeon_winsys_bo
*bo
;
813 uint32_t *mapped_ptr
;
814 struct radv_descriptor_range
*dynamic_descriptors
;
816 struct radeon_winsys_bo
*descriptors
[0];
819 struct radv_push_descriptor_set
821 struct radv_descriptor_set set
;
825 struct radv_descriptor_pool_entry
{
828 struct radv_descriptor_set
*set
;
831 struct radv_descriptor_pool
{
832 struct radeon_winsys_bo
*bo
;
834 uint64_t current_offset
;
837 uint8_t *host_memory_base
;
838 uint8_t *host_memory_ptr
;
839 uint8_t *host_memory_end
;
841 uint32_t entry_count
;
842 uint32_t max_entry_count
;
843 struct radv_descriptor_pool_entry entries
[0];
846 struct radv_descriptor_update_template_entry
{
847 VkDescriptorType descriptor_type
;
849 /* The number of descriptors to update */
850 uint32_t descriptor_count
;
852 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
855 /* In dwords. Not valid/used for dynamic descriptors */
858 uint32_t buffer_offset
;
860 /* Only valid for combined image samplers and samplers */
862 uint8_t sampler_offset
;
868 /* For push descriptors */
869 const uint32_t *immutable_samplers
;
872 struct radv_descriptor_update_template
{
873 uint32_t entry_count
;
874 VkPipelineBindPoint bind_point
;
875 struct radv_descriptor_update_template_entry entry
[0];
881 VkBufferUsageFlags usage
;
882 VkBufferCreateFlags flags
;
885 struct radeon_winsys_bo
* bo
;
891 enum radv_dynamic_state_bits
{
892 RADV_DYNAMIC_VIEWPORT
= 1 << 0,
893 RADV_DYNAMIC_SCISSOR
= 1 << 1,
894 RADV_DYNAMIC_LINE_WIDTH
= 1 << 2,
895 RADV_DYNAMIC_DEPTH_BIAS
= 1 << 3,
896 RADV_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
897 RADV_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
898 RADV_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
899 RADV_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
900 RADV_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
901 RADV_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
902 RADV_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
903 RADV_DYNAMIC_ALL
= (1 << 11) - 1,
906 enum radv_cmd_dirty_bits
{
907 /* Keep the dynamic state dirty bits in sync with
908 * enum radv_dynamic_state_bits */
909 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT
= 1 << 0,
910 RADV_CMD_DIRTY_DYNAMIC_SCISSOR
= 1 << 1,
911 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
= 1 << 2,
912 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
= 1 << 3,
913 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
= 1 << 4,
914 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
= 1 << 5,
915 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
= 1 << 6,
916 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
= 1 << 7,
917 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
= 1 << 8,
918 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE
= 1 << 9,
919 RADV_CMD_DIRTY_DYNAMIC_SAMPLE_LOCATIONS
= 1 << 10,
920 RADV_CMD_DIRTY_DYNAMIC_ALL
= (1 << 11) - 1,
921 RADV_CMD_DIRTY_PIPELINE
= 1 << 11,
922 RADV_CMD_DIRTY_INDEX_BUFFER
= 1 << 12,
923 RADV_CMD_DIRTY_FRAMEBUFFER
= 1 << 13,
924 RADV_CMD_DIRTY_VERTEX_BUFFER
= 1 << 14,
925 RADV_CMD_DIRTY_STREAMOUT_BUFFER
= 1 << 15,
928 enum radv_cmd_flush_bits
{
929 /* Instruction cache. */
930 RADV_CMD_FLAG_INV_ICACHE
= 1 << 0,
931 /* Scalar L1 cache. */
932 RADV_CMD_FLAG_INV_SCACHE
= 1 << 1,
933 /* Vector L1 cache. */
934 RADV_CMD_FLAG_INV_VCACHE
= 1 << 2,
935 /* L2 cache + L2 metadata cache writeback & invalidate.
936 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
937 RADV_CMD_FLAG_INV_L2
= 1 << 3,
938 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
939 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
940 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
941 RADV_CMD_FLAG_WB_L2
= 1 << 4,
942 /* Framebuffer caches */
943 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
= 1 << 5,
944 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
= 1 << 6,
945 RADV_CMD_FLAG_FLUSH_AND_INV_DB
= 1 << 7,
946 RADV_CMD_FLAG_FLUSH_AND_INV_CB
= 1 << 8,
947 /* Engine synchronization. */
948 RADV_CMD_FLAG_VS_PARTIAL_FLUSH
= 1 << 9,
949 RADV_CMD_FLAG_PS_PARTIAL_FLUSH
= 1 << 10,
950 RADV_CMD_FLAG_CS_PARTIAL_FLUSH
= 1 << 11,
951 RADV_CMD_FLAG_VGT_FLUSH
= 1 << 12,
952 /* Pipeline query controls. */
953 RADV_CMD_FLAG_START_PIPELINE_STATS
= 1 << 13,
954 RADV_CMD_FLAG_STOP_PIPELINE_STATS
= 1 << 14,
955 RADV_CMD_FLAG_VGT_STREAMOUT_SYNC
= 1 << 15,
957 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER
= (RADV_CMD_FLAG_FLUSH_AND_INV_CB
|
958 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META
|
959 RADV_CMD_FLAG_FLUSH_AND_INV_DB
|
960 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META
)
963 struct radv_vertex_binding
{
964 struct radv_buffer
* buffer
;
968 struct radv_streamout_binding
{
969 struct radv_buffer
*buffer
;
974 struct radv_streamout_state
{
975 /* Mask of bound streamout buffers. */
976 uint8_t enabled_mask
;
978 /* External state that comes from the last vertex stage, it must be
979 * set explicitely when binding a new graphics pipeline.
981 uint16_t stride_in_dw
[MAX_SO_BUFFERS
];
982 uint32_t enabled_stream_buffers_mask
; /* stream0 buffers0-3 in 4 LSB */
984 /* State of VGT_STRMOUT_BUFFER_(CONFIG|END) */
985 uint32_t hw_enabled_mask
;
987 /* State of VGT_STRMOUT_(CONFIG|EN) */
988 bool streamout_enabled
;
991 struct radv_viewport_state
{
993 VkViewport viewports
[MAX_VIEWPORTS
];
996 struct radv_scissor_state
{
998 VkRect2D scissors
[MAX_SCISSORS
];
1001 struct radv_discard_rectangle_state
{
1003 VkRect2D rectangles
[MAX_DISCARD_RECTANGLES
];
1006 struct radv_sample_locations_state
{
1007 VkSampleCountFlagBits per_pixel
;
1008 VkExtent2D grid_size
;
1010 VkSampleLocationEXT locations
[MAX_SAMPLE_LOCATIONS
];
1013 struct radv_dynamic_state
{
1015 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
1016 * Defines the set of saved dynamic state.
1020 struct radv_viewport_state viewport
;
1022 struct radv_scissor_state scissor
;
1032 float blend_constants
[4];
1042 } stencil_compare_mask
;
1047 } stencil_write_mask
;
1052 } stencil_reference
;
1054 struct radv_discard_rectangle_state discard_rectangle
;
1056 struct radv_sample_locations_state sample_location
;
1059 extern const struct radv_dynamic_state default_dynamic_state
;
1062 radv_get_debug_option_name(int id
);
1065 radv_get_perftest_option_name(int id
);
1068 * Attachment state when recording a renderpass instance.
1070 * The clear value is valid only if there exists a pending clear.
1072 struct radv_attachment_state
{
1073 VkImageAspectFlags pending_clear_aspects
;
1074 uint32_t cleared_views
;
1075 VkClearValue clear_value
;
1076 VkImageLayout current_layout
;
1077 struct radv_sample_locations_state sample_location
;
1080 struct radv_descriptor_state
{
1081 struct radv_descriptor_set
*sets
[MAX_SETS
];
1084 struct radv_push_descriptor_set push_set
;
1086 uint32_t dynamic_buffers
[4 * MAX_DYNAMIC_BUFFERS
];
1089 struct radv_subpass_sample_locs_state
{
1090 uint32_t subpass_idx
;
1091 struct radv_sample_locations_state sample_location
;
1094 struct radv_cmd_state
{
1095 /* Vertex descriptors */
1102 uint32_t prefetch_L2_mask
;
1104 struct radv_pipeline
* pipeline
;
1105 struct radv_pipeline
* emitted_pipeline
;
1106 struct radv_pipeline
* compute_pipeline
;
1107 struct radv_pipeline
* emitted_compute_pipeline
;
1108 struct radv_framebuffer
* framebuffer
;
1109 struct radv_render_pass
* pass
;
1110 const struct radv_subpass
* subpass
;
1111 struct radv_dynamic_state dynamic
;
1112 struct radv_attachment_state
* attachments
;
1113 struct radv_streamout_state streamout
;
1114 VkRect2D render_area
;
1116 uint32_t num_subpass_sample_locs
;
1117 struct radv_subpass_sample_locs_state
* subpass_sample_locs
;
1120 struct radv_buffer
*index_buffer
;
1121 uint64_t index_offset
;
1122 uint32_t index_type
;
1123 uint32_t max_index_count
;
1125 int32_t last_index_type
;
1127 int32_t last_primitive_reset_en
;
1128 uint32_t last_primitive_reset_index
;
1129 enum radv_cmd_flush_bits flush_bits
;
1130 unsigned active_occlusion_queries
;
1131 bool perfect_occlusion_queries_enabled
;
1132 unsigned active_pipeline_queries
;
1135 uint32_t last_ia_multi_vgt_param
;
1137 uint32_t last_num_instances
;
1138 uint32_t last_first_instance
;
1139 uint32_t last_vertex_offset
;
1141 /* Whether CP DMA is busy/idle. */
1144 /* Conditional rendering info. */
1145 int predication_type
; /* -1: disabled, 0: normal, 1: inverted */
1146 uint64_t predication_va
;
1148 bool context_roll_without_scissor_emitted
;
1151 struct radv_cmd_pool
{
1152 VkAllocationCallbacks alloc
;
1153 struct list_head cmd_buffers
;
1154 struct list_head free_cmd_buffers
;
1155 uint32_t queue_family_index
;
1158 struct radv_cmd_buffer_upload
{
1162 struct radeon_winsys_bo
*upload_bo
;
1163 struct list_head list
;
1166 enum radv_cmd_buffer_status
{
1167 RADV_CMD_BUFFER_STATUS_INVALID
,
1168 RADV_CMD_BUFFER_STATUS_INITIAL
,
1169 RADV_CMD_BUFFER_STATUS_RECORDING
,
1170 RADV_CMD_BUFFER_STATUS_EXECUTABLE
,
1171 RADV_CMD_BUFFER_STATUS_PENDING
,
1174 struct radv_cmd_buffer
{
1175 VK_LOADER_DATA _loader_data
;
1177 struct radv_device
* device
;
1179 struct radv_cmd_pool
* pool
;
1180 struct list_head pool_link
;
1182 VkCommandBufferUsageFlags usage_flags
;
1183 VkCommandBufferLevel level
;
1184 enum radv_cmd_buffer_status status
;
1185 struct radeon_cmdbuf
*cs
;
1186 struct radv_cmd_state state
;
1187 struct radv_vertex_binding vertex_bindings
[MAX_VBS
];
1188 struct radv_streamout_binding streamout_bindings
[MAX_SO_BUFFERS
];
1189 uint32_t queue_family_index
;
1191 uint8_t push_constants
[MAX_PUSH_CONSTANTS_SIZE
];
1192 VkShaderStageFlags push_constant_stages
;
1193 struct radv_descriptor_set meta_push_descriptors
;
1195 struct radv_descriptor_state descriptors
[VK_PIPELINE_BIND_POINT_RANGE_SIZE
];
1197 struct radv_cmd_buffer_upload upload
;
1199 uint32_t scratch_size_needed
;
1200 uint32_t compute_scratch_size_needed
;
1201 uint32_t esgs_ring_size_needed
;
1202 uint32_t gsvs_ring_size_needed
;
1203 bool tess_rings_needed
;
1204 bool sample_positions_needed
;
1206 VkResult record_result
;
1208 uint64_t gfx9_fence_va
;
1209 uint32_t gfx9_fence_idx
;
1210 uint64_t gfx9_eop_bug_va
;
1213 * Whether a query pool has been resetted and we have to flush caches.
1215 bool pending_reset_query
;
1218 * Bitmask of pending active query flushes.
1220 enum radv_cmd_flush_bits active_query_flush_bits
;
1224 struct radv_image_view
;
1226 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer
*cmd_buffer
);
1228 void si_emit_graphics(struct radv_physical_device
*physical_device
,
1229 struct radeon_cmdbuf
*cs
);
1230 void si_emit_compute(struct radv_physical_device
*physical_device
,
1231 struct radeon_cmdbuf
*cs
);
1233 void cik_create_gfx_config(struct radv_device
*device
);
1235 void si_write_viewport(struct radeon_cmdbuf
*cs
, int first_vp
,
1236 int count
, const VkViewport
*viewports
);
1237 void si_write_scissors(struct radeon_cmdbuf
*cs
, int first
,
1238 int count
, const VkRect2D
*scissors
,
1239 const VkViewport
*viewports
, bool can_use_guardband
);
1240 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer
,
1241 bool instanced_draw
, bool indirect_draw
,
1242 bool count_from_stream_output
,
1243 uint32_t draw_vertex_count
);
1244 void si_cs_emit_write_event_eop(struct radeon_cmdbuf
*cs
,
1245 enum chip_class chip_class
,
1247 unsigned event
, unsigned event_flags
,
1248 unsigned dst_sel
, unsigned data_sel
,
1251 uint64_t gfx9_eop_bug_va
);
1253 void radv_cp_wait_mem(struct radeon_cmdbuf
*cs
, uint32_t op
, uint64_t va
,
1254 uint32_t ref
, uint32_t mask
);
1255 void si_cs_emit_cache_flush(struct radeon_cmdbuf
*cs
,
1256 enum chip_class chip_class
,
1257 uint32_t *fence_ptr
, uint64_t va
,
1259 enum radv_cmd_flush_bits flush_bits
,
1260 uint64_t gfx9_eop_bug_va
);
1261 void si_emit_cache_flush(struct radv_cmd_buffer
*cmd_buffer
);
1262 void si_emit_set_predication_state(struct radv_cmd_buffer
*cmd_buffer
,
1263 bool inverted
, uint64_t va
);
1264 void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer
,
1265 uint64_t src_va
, uint64_t dest_va
,
1267 void si_cp_dma_prefetch(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1269 void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer
, uint64_t va
,
1270 uint64_t size
, unsigned value
);
1271 void si_cp_dma_wait_for_idle(struct radv_cmd_buffer
*cmd_buffer
);
1273 void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer
);
1275 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer
*cmd_buffer
,
1278 unsigned *out_offset
,
1281 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer
*cmd_buffer
,
1282 const struct radv_subpass
*subpass
);
1284 radv_cmd_buffer_upload_data(struct radv_cmd_buffer
*cmd_buffer
,
1285 unsigned size
, unsigned alignmnet
,
1286 const void *data
, unsigned *out_offset
);
1288 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1289 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer
*cmd_buffer
);
1290 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
);
1291 void radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
,
1292 VkImageAspectFlags aspects
,
1293 VkResolveModeFlagBitsKHR resolve_mode
);
1294 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
);
1295 void radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer
*cmd_buffer
,
1296 VkImageAspectFlags aspects
,
1297 VkResolveModeFlagBitsKHR resolve_mode
);
1298 void radv_emit_default_sample_locations(struct radeon_cmdbuf
*cs
, int nr_samples
);
1299 unsigned radv_get_default_max_sample_dist(int log_samples
);
1300 void radv_device_init_msaa(struct radv_device
*device
);
1302 void radv_update_ds_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1303 struct radv_image
*image
,
1304 VkClearDepthStencilValue ds_clear_value
,
1305 VkImageAspectFlags aspects
);
1307 void radv_update_color_clear_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1308 const struct radv_image_view
*iview
,
1310 uint32_t color_values
[2]);
1312 void radv_update_fce_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1313 struct radv_image
*image
,
1314 const VkImageSubresourceRange
*range
, bool value
);
1316 void radv_update_dcc_metadata(struct radv_cmd_buffer
*cmd_buffer
,
1317 struct radv_image
*image
,
1318 const VkImageSubresourceRange
*range
, bool value
);
1320 uint32_t radv_fill_buffer(struct radv_cmd_buffer
*cmd_buffer
,
1321 struct radeon_winsys_bo
*bo
,
1322 uint64_t offset
, uint64_t size
, uint32_t value
);
1323 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer
*cmd_buffer
);
1324 bool radv_get_memory_fd(struct radv_device
*device
,
1325 struct radv_device_memory
*memory
,
1329 radv_emit_shader_pointer_head(struct radeon_cmdbuf
*cs
,
1330 unsigned sh_offset
, unsigned pointer_count
,
1331 bool use_32bit_pointers
)
1333 radeon_emit(cs
, PKT3(PKT3_SET_SH_REG
, pointer_count
* (use_32bit_pointers
? 1 : 2), 0));
1334 radeon_emit(cs
, (sh_offset
- SI_SH_REG_OFFSET
) >> 2);
1338 radv_emit_shader_pointer_body(struct radv_device
*device
,
1339 struct radeon_cmdbuf
*cs
,
1340 uint64_t va
, bool use_32bit_pointers
)
1342 radeon_emit(cs
, va
);
1344 if (use_32bit_pointers
) {
1346 (va
>> 32) == device
->physical_device
->rad_info
.address32_hi
);
1348 radeon_emit(cs
, va
>> 32);
1353 radv_emit_shader_pointer(struct radv_device
*device
,
1354 struct radeon_cmdbuf
*cs
,
1355 uint32_t sh_offset
, uint64_t va
, bool global
)
1357 bool use_32bit_pointers
= !global
;
1359 radv_emit_shader_pointer_head(cs
, sh_offset
, 1, use_32bit_pointers
);
1360 radv_emit_shader_pointer_body(device
, cs
, va
, use_32bit_pointers
);
1363 static inline struct radv_descriptor_state
*
1364 radv_get_descriptors_state(struct radv_cmd_buffer
*cmd_buffer
,
1365 VkPipelineBindPoint bind_point
)
1367 assert(bind_point
== VK_PIPELINE_BIND_POINT_GRAPHICS
||
1368 bind_point
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1369 return &cmd_buffer
->descriptors
[bind_point
];
1373 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1375 * Limitations: Can't call normal dispatch functions without binding or rebinding
1376 * the compute pipeline.
1378 void radv_unaligned_dispatch(
1379 struct radv_cmd_buffer
*cmd_buffer
,
1385 struct radeon_winsys_bo
*bo
;
1389 struct radv_shader_module
;
1391 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1392 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1393 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1394 #define RADV_HASH_SHADER_NO_NGG (1 << 3)
1397 radv_hash_shaders(unsigned char *hash
,
1398 const VkPipelineShaderStageCreateInfo
**stages
,
1399 const struct radv_pipeline_layout
*layout
,
1400 const struct radv_pipeline_key
*key
,
1403 static inline gl_shader_stage
1404 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage
)
1406 assert(__builtin_popcount(vk_stage
) == 1);
1407 return ffs(vk_stage
) - 1;
1410 static inline VkShaderStageFlagBits
1411 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage
)
1413 return (1 << mesa_stage
);
1416 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1418 #define radv_foreach_stage(stage, stage_bits) \
1419 for (gl_shader_stage stage, \
1420 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1421 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1422 __tmp &= ~(1 << (stage)))
1424 extern const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
];
1425 unsigned radv_format_meta_fs_key(VkFormat format
);
1427 struct radv_multisample_state
{
1429 uint32_t pa_sc_line_cntl
;
1430 uint32_t pa_sc_mode_cntl_0
;
1431 uint32_t pa_sc_mode_cntl_1
;
1432 uint32_t pa_sc_aa_config
;
1433 uint32_t pa_sc_aa_mask
[2];
1434 unsigned num_samples
;
1437 struct radv_prim_vertex_count
{
1442 struct radv_vertex_elements_info
{
1443 uint32_t format_size
[MAX_VERTEX_ATTRIBS
];
1446 struct radv_ia_multi_vgt_param_helpers
{
1448 bool partial_es_wave
;
1449 uint8_t primgroup_size
;
1450 bool wd_switch_on_eop
;
1451 bool ia_switch_on_eoi
;
1452 bool partial_vs_wave
;
1455 #define SI_GS_PER_ES 128
1457 struct radv_pipeline
{
1458 struct radv_device
* device
;
1459 struct radv_dynamic_state dynamic_state
;
1461 struct radv_pipeline_layout
* layout
;
1463 bool need_indirect_descriptor_sets
;
1464 struct radv_shader_variant
* shaders
[MESA_SHADER_STAGES
];
1465 struct radv_shader_variant
*gs_copy_shader
;
1466 VkShaderStageFlags active_stages
;
1468 struct radeon_cmdbuf cs
;
1469 uint32_t ctx_cs_hash
;
1470 struct radeon_cmdbuf ctx_cs
;
1472 struct radv_vertex_elements_info vertex_elements
;
1474 uint32_t binding_stride
[MAX_VBS
];
1475 uint8_t num_vertex_bindings
;
1477 uint32_t user_data_0
[MESA_SHADER_STAGES
];
1480 struct radv_multisample_state ms
;
1481 uint32_t spi_baryc_cntl
;
1482 bool prim_restart_enable
;
1483 unsigned esgs_ring_size
;
1484 unsigned gsvs_ring_size
;
1485 uint32_t vtx_base_sgpr
;
1486 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
;
1487 uint8_t vtx_emit_num
;
1488 struct radv_prim_vertex_count prim_vertex_count
;
1489 bool can_use_guardband
;
1490 uint32_t needed_dynamic_state
;
1491 bool disable_out_of_order_rast_for_occlusion
;
1493 /* Used for rbplus */
1494 uint32_t col_format
;
1495 uint32_t cb_target_mask
;
1500 unsigned scratch_bytes_per_wave
;
1502 /* Not NULL if graphics pipeline uses streamout. */
1503 struct radv_shader_variant
*streamout_shader
;
1506 static inline bool radv_pipeline_has_gs(const struct radv_pipeline
*pipeline
)
1508 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
] ? true : false;
1511 static inline bool radv_pipeline_has_tess(const struct radv_pipeline
*pipeline
)
1513 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] ? true : false;
1516 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
);
1518 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
);
1520 struct radv_userdata_info
*radv_lookup_user_sgpr(struct radv_pipeline
*pipeline
,
1521 gl_shader_stage stage
,
1524 struct radv_shader_variant
*radv_get_shader(struct radv_pipeline
*pipeline
,
1525 gl_shader_stage stage
);
1527 struct radv_graphics_pipeline_create_info
{
1529 bool db_depth_clear
;
1530 bool db_stencil_clear
;
1531 bool db_depth_disable_expclear
;
1532 bool db_stencil_disable_expclear
;
1533 bool db_flush_depth_inplace
;
1534 bool db_flush_stencil_inplace
;
1535 bool db_resummarize
;
1536 uint32_t custom_blend_mode
;
1540 radv_graphics_pipeline_create(VkDevice device
,
1541 VkPipelineCache cache
,
1542 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1543 const struct radv_graphics_pipeline_create_info
*extra
,
1544 const VkAllocationCallbacks
*alloc
,
1545 VkPipeline
*pPipeline
);
1547 struct vk_format_description
;
1548 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description
*desc
,
1549 int first_non_void
);
1550 uint32_t radv_translate_buffer_numformat(const struct vk_format_description
*desc
,
1551 int first_non_void
);
1552 bool radv_is_buffer_format_supported(VkFormat format
, bool *scaled
);
1553 uint32_t radv_translate_colorformat(VkFormat format
);
1554 uint32_t radv_translate_color_numformat(VkFormat format
,
1555 const struct vk_format_description
*desc
,
1556 int first_non_void
);
1557 uint32_t radv_colorformat_endian_swap(uint32_t colorformat
);
1558 unsigned radv_translate_colorswap(VkFormat format
, bool do_endian_swap
);
1559 uint32_t radv_translate_dbformat(VkFormat format
);
1560 uint32_t radv_translate_tex_dataformat(VkFormat format
,
1561 const struct vk_format_description
*desc
,
1562 int first_non_void
);
1563 uint32_t radv_translate_tex_numformat(VkFormat format
,
1564 const struct vk_format_description
*desc
,
1565 int first_non_void
);
1566 bool radv_format_pack_clear_color(VkFormat format
,
1567 uint32_t clear_vals
[2],
1568 VkClearColorValue
*value
);
1569 bool radv_is_colorbuffer_format_supported(VkFormat format
, bool *blendable
);
1570 bool radv_dcc_formats_compatible(VkFormat format1
,
1572 bool radv_device_supports_etc(struct radv_physical_device
*physical_device
);
1574 struct radv_fmask_info
{
1578 unsigned pitch_in_pixels
;
1579 unsigned bank_height
;
1580 unsigned slice_tile_max
;
1581 unsigned tile_mode_index
;
1582 unsigned tile_swizzle
;
1583 uint64_t slice_size
;
1586 struct radv_cmask_info
{
1590 unsigned slice_tile_max
;
1591 unsigned slice_size
;
1595 struct radv_image_plane
{
1597 struct radeon_surf surface
;
1603 /* The original VkFormat provided by the client. This may not match any
1604 * of the actual surface formats.
1607 VkImageAspectFlags aspects
;
1608 VkImageUsageFlags usage
; /**< Superset of VkImageCreateInfo::usage. */
1609 struct ac_surf_info info
;
1610 VkImageTiling tiling
; /** VkImageCreateInfo::tiling */
1611 VkImageCreateFlags flags
; /** VkImageCreateInfo::flags */
1616 unsigned queue_family_mask
;
1620 /* Set when bound */
1621 struct radeon_winsys_bo
*bo
;
1622 VkDeviceSize offset
;
1623 uint64_t dcc_offset
;
1624 uint64_t htile_offset
;
1625 bool tc_compatible_htile
;
1626 bool tc_compatible_cmask
;
1628 struct radv_fmask_info fmask
;
1629 struct radv_cmask_info cmask
;
1630 uint64_t clear_value_offset
;
1631 uint64_t fce_pred_offset
;
1632 uint64_t dcc_pred_offset
;
1635 * Metadata for the TC-compat zrange workaround. If the 32-bit value
1636 * stored at this offset is UINT_MAX, the driver will emit
1637 * DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
1638 * SET_CONTEXT_REG packet.
1640 uint64_t tc_compat_zrange_offset
;
1642 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1643 VkDeviceMemory owned_memory
;
1645 unsigned plane_count
;
1646 struct radv_image_plane planes
[0];
1649 /* Whether the image has a htile that is known consistent with the contents of
1651 bool radv_layout_has_htile(const struct radv_image
*image
,
1652 VkImageLayout layout
,
1653 unsigned queue_mask
);
1655 /* Whether the image has a htile that is known consistent with the contents of
1656 * the image and is allowed to be in compressed form.
1658 * If this is false reads that don't use the htile should be able to return
1661 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1662 VkImageLayout layout
,
1663 unsigned queue_mask
);
1665 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1666 VkImageLayout layout
,
1667 unsigned queue_mask
);
1669 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1670 VkImageLayout layout
,
1671 unsigned queue_mask
);
1674 * Return whether the image has CMASK metadata for color surfaces.
1677 radv_image_has_cmask(const struct radv_image
*image
)
1679 return image
->cmask
.size
;
1683 * Return whether the image has FMASK metadata for color surfaces.
1686 radv_image_has_fmask(const struct radv_image
*image
)
1688 return image
->fmask
.size
;
1692 * Return whether the image has DCC metadata for color surfaces.
1695 radv_image_has_dcc(const struct radv_image
*image
)
1697 return image
->planes
[0].surface
.dcc_size
;
1701 * Return whether the image is TC-compatible CMASK.
1704 radv_image_is_tc_compat_cmask(const struct radv_image
*image
)
1706 return radv_image_has_fmask(image
) && image
->tc_compatible_cmask
;
1710 * Return whether DCC metadata is enabled for a level.
1713 radv_dcc_enabled(const struct radv_image
*image
, unsigned level
)
1715 return radv_image_has_dcc(image
) &&
1716 level
< image
->planes
[0].surface
.num_dcc_levels
;
1720 * Return whether the image has CB metadata.
1723 radv_image_has_CB_metadata(const struct radv_image
*image
)
1725 return radv_image_has_cmask(image
) ||
1726 radv_image_has_fmask(image
) ||
1727 radv_image_has_dcc(image
);
1731 * Return whether the image has HTILE metadata for depth surfaces.
1734 radv_image_has_htile(const struct radv_image
*image
)
1736 return image
->planes
[0].surface
.htile_size
;
1740 * Return whether HTILE metadata is enabled for a level.
1743 radv_htile_enabled(const struct radv_image
*image
, unsigned level
)
1745 return radv_image_has_htile(image
) && level
== 0;
1749 * Return whether the image is TC-compatible HTILE.
1752 radv_image_is_tc_compat_htile(const struct radv_image
*image
)
1754 return radv_image_has_htile(image
) && image
->tc_compatible_htile
;
1757 static inline uint64_t
1758 radv_image_get_fast_clear_va(const struct radv_image
*image
,
1759 uint32_t base_level
)
1761 uint64_t va
= radv_buffer_get_va(image
->bo
);
1762 va
+= image
->offset
+ image
->clear_value_offset
+ base_level
* 8;
1766 static inline uint64_t
1767 radv_image_get_fce_pred_va(const struct radv_image
*image
,
1768 uint32_t base_level
)
1770 uint64_t va
= radv_buffer_get_va(image
->bo
);
1771 va
+= image
->offset
+ image
->fce_pred_offset
+ base_level
* 8;
1775 static inline uint64_t
1776 radv_image_get_dcc_pred_va(const struct radv_image
*image
,
1777 uint32_t base_level
)
1779 uint64_t va
= radv_buffer_get_va(image
->bo
);
1780 va
+= image
->offset
+ image
->dcc_pred_offset
+ base_level
* 8;
1784 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
);
1786 static inline uint32_t
1787 radv_get_layerCount(const struct radv_image
*image
,
1788 const VkImageSubresourceRange
*range
)
1790 return range
->layerCount
== VK_REMAINING_ARRAY_LAYERS
?
1791 image
->info
.array_size
- range
->baseArrayLayer
: range
->layerCount
;
1794 static inline uint32_t
1795 radv_get_levelCount(const struct radv_image
*image
,
1796 const VkImageSubresourceRange
*range
)
1798 return range
->levelCount
== VK_REMAINING_MIP_LEVELS
?
1799 image
->info
.levels
- range
->baseMipLevel
: range
->levelCount
;
1802 struct radeon_bo_metadata
;
1804 radv_init_metadata(struct radv_device
*device
,
1805 struct radv_image
*image
,
1806 struct radeon_bo_metadata
*metadata
);
1809 radv_image_override_offset_stride(struct radv_device
*device
,
1810 struct radv_image
*image
,
1811 uint64_t offset
, uint32_t stride
);
1813 union radv_descriptor
{
1815 uint32_t plane0_descriptor
[8];
1816 uint32_t fmask_descriptor
[8];
1819 uint32_t plane_descriptors
[3][8];
1823 struct radv_image_view
{
1824 struct radv_image
*image
; /**< VkImageViewCreateInfo::image */
1825 struct radeon_winsys_bo
*bo
;
1827 VkImageViewType type
;
1828 VkImageAspectFlags aspect_mask
;
1831 bool multiple_planes
;
1832 uint32_t base_layer
;
1833 uint32_t layer_count
;
1835 uint32_t level_count
;
1836 VkExtent3D extent
; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1838 union radv_descriptor descriptor
;
1840 /* Descriptor for use as a storage image as opposed to a sampled image.
1841 * This has a few differences for cube maps (e.g. type).
1843 union radv_descriptor storage_descriptor
;
1846 struct radv_image_create_info
{
1847 const VkImageCreateInfo
*vk_info
;
1849 bool no_metadata_planes
;
1850 const struct radeon_bo_metadata
*bo_metadata
;
1853 VkResult
radv_image_create(VkDevice _device
,
1854 const struct radv_image_create_info
*info
,
1855 const VkAllocationCallbacks
* alloc
,
1859 radv_image_from_gralloc(VkDevice device_h
,
1860 const VkImageCreateInfo
*base_info
,
1861 const VkNativeBufferANDROID
*gralloc_info
,
1862 const VkAllocationCallbacks
*alloc
,
1863 VkImage
*out_image_h
);
1865 void radv_image_view_init(struct radv_image_view
*view
,
1866 struct radv_device
*device
,
1867 const VkImageViewCreateInfo
* pCreateInfo
);
1869 VkFormat
radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
);
1871 struct radv_sampler_ycbcr_conversion
{
1873 VkSamplerYcbcrModelConversion ycbcr_model
;
1874 VkSamplerYcbcrRange ycbcr_range
;
1875 VkComponentMapping components
;
1876 VkChromaLocation chroma_offsets
[2];
1877 VkFilter chroma_filter
;
1880 struct radv_buffer_view
{
1881 struct radeon_winsys_bo
*bo
;
1883 uint64_t range
; /**< VkBufferViewCreateInfo::range */
1886 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1887 struct radv_device
*device
,
1888 const VkBufferViewCreateInfo
* pCreateInfo
);
1890 static inline struct VkExtent3D
1891 radv_sanitize_image_extent(const VkImageType imageType
,
1892 const struct VkExtent3D imageExtent
)
1894 switch (imageType
) {
1895 case VK_IMAGE_TYPE_1D
:
1896 return (VkExtent3D
) { imageExtent
.width
, 1, 1 };
1897 case VK_IMAGE_TYPE_2D
:
1898 return (VkExtent3D
) { imageExtent
.width
, imageExtent
.height
, 1 };
1899 case VK_IMAGE_TYPE_3D
:
1902 unreachable("invalid image type");
1906 static inline struct VkOffset3D
1907 radv_sanitize_image_offset(const VkImageType imageType
,
1908 const struct VkOffset3D imageOffset
)
1910 switch (imageType
) {
1911 case VK_IMAGE_TYPE_1D
:
1912 return (VkOffset3D
) { imageOffset
.x
, 0, 0 };
1913 case VK_IMAGE_TYPE_2D
:
1914 return (VkOffset3D
) { imageOffset
.x
, imageOffset
.y
, 0 };
1915 case VK_IMAGE_TYPE_3D
:
1918 unreachable("invalid image type");
1923 radv_image_extent_compare(const struct radv_image
*image
,
1924 const VkExtent3D
*extent
)
1926 if (extent
->width
!= image
->info
.width
||
1927 extent
->height
!= image
->info
.height
||
1928 extent
->depth
!= image
->info
.depth
)
1933 struct radv_sampler
{
1935 struct radv_sampler_ycbcr_conversion
*ycbcr_sampler
;
1938 struct radv_color_buffer_info
{
1939 uint64_t cb_color_base
;
1940 uint64_t cb_color_cmask
;
1941 uint64_t cb_color_fmask
;
1942 uint64_t cb_dcc_base
;
1943 uint32_t cb_color_slice
;
1944 uint32_t cb_color_view
;
1945 uint32_t cb_color_info
;
1946 uint32_t cb_color_attrib
;
1947 uint32_t cb_color_attrib2
; /* GFX9 and later */
1948 uint32_t cb_color_attrib3
; /* GFX10 and later */
1949 uint32_t cb_dcc_control
;
1950 uint32_t cb_color_cmask_slice
;
1951 uint32_t cb_color_fmask_slice
;
1953 uint32_t cb_color_pitch
; // GFX6-GFX8
1954 uint32_t cb_mrt_epitch
; // GFX9+
1958 struct radv_ds_buffer_info
{
1959 uint64_t db_z_read_base
;
1960 uint64_t db_stencil_read_base
;
1961 uint64_t db_z_write_base
;
1962 uint64_t db_stencil_write_base
;
1963 uint64_t db_htile_data_base
;
1964 uint32_t db_depth_info
;
1966 uint32_t db_stencil_info
;
1967 uint32_t db_depth_view
;
1968 uint32_t db_depth_size
;
1969 uint32_t db_depth_slice
;
1970 uint32_t db_htile_surface
;
1971 uint32_t pa_su_poly_offset_db_fmt_cntl
;
1972 uint32_t db_z_info2
; /* GFX9 only */
1973 uint32_t db_stencil_info2
; /* GFX9 only */
1977 struct radv_attachment_info
{
1979 struct radv_color_buffer_info cb
;
1980 struct radv_ds_buffer_info ds
;
1982 struct radv_image_view
*attachment
;
1985 struct radv_framebuffer
{
1990 uint32_t attachment_count
;
1991 struct radv_attachment_info attachments
[0];
1994 struct radv_subpass_barrier
{
1995 VkPipelineStageFlags src_stage_mask
;
1996 VkAccessFlags src_access_mask
;
1997 VkAccessFlags dst_access_mask
;
2000 void radv_subpass_barrier(struct radv_cmd_buffer
*cmd_buffer
,
2001 const struct radv_subpass_barrier
*barrier
);
2003 struct radv_subpass_attachment
{
2004 uint32_t attachment
;
2005 VkImageLayout layout
;
2008 struct radv_subpass
{
2009 uint32_t attachment_count
;
2010 struct radv_subpass_attachment
* attachments
;
2012 uint32_t input_count
;
2013 uint32_t color_count
;
2014 struct radv_subpass_attachment
* input_attachments
;
2015 struct radv_subpass_attachment
* color_attachments
;
2016 struct radv_subpass_attachment
* resolve_attachments
;
2017 struct radv_subpass_attachment
* depth_stencil_attachment
;
2018 struct radv_subpass_attachment
* ds_resolve_attachment
;
2019 VkResolveModeFlagBitsKHR depth_resolve_mode
;
2020 VkResolveModeFlagBitsKHR stencil_resolve_mode
;
2022 /** Subpass has at least one color resolve attachment */
2023 bool has_color_resolve
;
2025 /** Subpass has at least one color attachment */
2028 struct radv_subpass_barrier start_barrier
;
2031 VkSampleCountFlagBits max_sample_count
;
2035 radv_get_subpass_id(struct radv_cmd_buffer
*cmd_buffer
);
2037 struct radv_render_pass_attachment
{
2040 VkAttachmentLoadOp load_op
;
2041 VkAttachmentLoadOp stencil_load_op
;
2042 VkImageLayout initial_layout
;
2043 VkImageLayout final_layout
;
2045 /* The subpass id in which the attachment will be used first/last. */
2046 uint32_t first_subpass_idx
;
2047 uint32_t last_subpass_idx
;
2050 struct radv_render_pass
{
2051 uint32_t attachment_count
;
2052 uint32_t subpass_count
;
2053 struct radv_subpass_attachment
* subpass_attachments
;
2054 struct radv_render_pass_attachment
* attachments
;
2055 struct radv_subpass_barrier end_barrier
;
2056 struct radv_subpass subpasses
[0];
2059 VkResult
radv_device_init_meta(struct radv_device
*device
);
2060 void radv_device_finish_meta(struct radv_device
*device
);
2062 struct radv_query_pool
{
2063 struct radeon_winsys_bo
*bo
;
2065 uint32_t availability_offset
;
2069 uint32_t pipeline_stats_mask
;
2072 struct radv_semaphore
{
2073 /* use a winsys sem for non-exportable */
2074 struct radeon_winsys_sem
*sem
;
2076 uint32_t temp_syncobj
;
2079 void radv_set_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2080 VkPipelineBindPoint bind_point
,
2081 struct radv_descriptor_set
*set
,
2085 radv_update_descriptor_sets(struct radv_device
*device
,
2086 struct radv_cmd_buffer
*cmd_buffer
,
2087 VkDescriptorSet overrideSet
,
2088 uint32_t descriptorWriteCount
,
2089 const VkWriteDescriptorSet
*pDescriptorWrites
,
2090 uint32_t descriptorCopyCount
,
2091 const VkCopyDescriptorSet
*pDescriptorCopies
);
2094 radv_update_descriptor_set_with_template(struct radv_device
*device
,
2095 struct radv_cmd_buffer
*cmd_buffer
,
2096 struct radv_descriptor_set
*set
,
2097 VkDescriptorUpdateTemplate descriptorUpdateTemplate
,
2100 void radv_meta_push_descriptor_set(struct radv_cmd_buffer
*cmd_buffer
,
2101 VkPipelineBindPoint pipelineBindPoint
,
2102 VkPipelineLayout _layout
,
2104 uint32_t descriptorWriteCount
,
2105 const VkWriteDescriptorSet
*pDescriptorWrites
);
2107 void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer
,
2108 struct radv_image
*image
,
2109 const VkImageSubresourceRange
*range
, uint32_t value
);
2111 void radv_initialize_fmask(struct radv_cmd_buffer
*cmd_buffer
,
2112 struct radv_image
*image
,
2113 const VkImageSubresourceRange
*range
);
2116 struct radeon_winsys_fence
*fence
;
2117 struct wsi_fence
*fence_wsi
;
2120 uint32_t temp_syncobj
;
2123 /* radv_nir_to_llvm.c */
2124 struct radv_shader_variant_info
;
2125 struct radv_nir_compiler_options
;
2127 void radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
2128 struct nir_shader
*geom_shader
,
2129 struct radv_shader_binary
**rbinary
,
2130 struct radv_shader_variant_info
*shader_info
,
2131 const struct radv_nir_compiler_options
*option
);
2133 void radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
2134 struct radv_shader_binary
**rbinary
,
2135 struct radv_shader_variant_info
*shader_info
,
2136 struct nir_shader
*const *nir
,
2138 const struct radv_nir_compiler_options
*options
);
2140 unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
2141 gl_shader_stage stage
,
2142 const struct nir_shader
*nir
);
2144 /* radv_shader_info.h */
2145 struct radv_shader_info
;
2147 void radv_nir_shader_info_pass(const struct nir_shader
*nir
,
2148 const struct radv_nir_compiler_options
*options
,
2149 struct radv_shader_info
*info
);
2151 void radv_nir_shader_info_init(struct radv_shader_info
*info
);
2153 struct radeon_winsys_sem
;
2155 uint64_t radv_get_current_time(void);
2157 static inline uint32_t
2158 si_conv_gl_prim_to_vertices(unsigned gl_prim
)
2161 case 0: /* GL_POINTS */
2163 case 1: /* GL_LINES */
2164 case 3: /* GL_LINE_STRIP */
2166 case 4: /* GL_TRIANGLES */
2167 case 5: /* GL_TRIANGLE_STRIP */
2169 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
2171 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
2173 case 7: /* GL_QUADS */
2174 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
2181 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
2183 static inline struct __radv_type * \
2184 __radv_type ## _from_handle(__VkType _handle) \
2186 return (struct __radv_type *) _handle; \
2189 static inline __VkType \
2190 __radv_type ## _to_handle(struct __radv_type *_obj) \
2192 return (__VkType) _obj; \
2195 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
2197 static inline struct __radv_type * \
2198 __radv_type ## _from_handle(__VkType _handle) \
2200 return (struct __radv_type *)(uintptr_t) _handle; \
2203 static inline __VkType \
2204 __radv_type ## _to_handle(struct __radv_type *_obj) \
2206 return (__VkType)(uintptr_t) _obj; \
2209 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
2210 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
2212 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer
, VkCommandBuffer
)
2213 RADV_DEFINE_HANDLE_CASTS(radv_device
, VkDevice
)
2214 RADV_DEFINE_HANDLE_CASTS(radv_instance
, VkInstance
)
2215 RADV_DEFINE_HANDLE_CASTS(radv_physical_device
, VkPhysicalDevice
)
2216 RADV_DEFINE_HANDLE_CASTS(radv_queue
, VkQueue
)
2218 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool
, VkCommandPool
)
2219 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer
, VkBuffer
)
2220 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view
, VkBufferView
)
2221 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool
, VkDescriptorPool
)
2222 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set
, VkDescriptorSet
)
2223 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout
, VkDescriptorSetLayout
)
2224 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template
, VkDescriptorUpdateTemplate
)
2225 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory
, VkDeviceMemory
)
2226 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence
, VkFence
)
2227 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event
, VkEvent
)
2228 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer
, VkFramebuffer
)
2229 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image
, VkImage
)
2230 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view
, VkImageView
);
2231 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache
, VkPipelineCache
)
2232 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline
, VkPipeline
)
2233 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout
, VkPipelineLayout
)
2234 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool
, VkQueryPool
)
2235 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass
, VkRenderPass
)
2236 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler
, VkSampler
)
2237 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler_ycbcr_conversion
, VkSamplerYcbcrConversion
)
2238 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module
, VkShaderModule
)
2239 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore
, VkSemaphore
)
2241 #endif /* RADV_PRIVATE_H */