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radv: Make FragCoord a sysval
[mesa.git] / src / amd / vulkan / radv_shader.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/mesa-sha1.h"
29 #include "util/u_atomic.h"
30 #include "radv_debug.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "radv_shader_helper.h"
34 #include "nir/nir.h"
35 #include "nir/nir_builder.h"
36 #include "spirv/nir_spirv.h"
37
38 #include <llvm-c/Core.h>
39 #include <llvm-c/TargetMachine.h>
40 #include <llvm-c/Support.h>
41
42 #include "sid.h"
43 #include "ac_binary.h"
44 #include "ac_llvm_util.h"
45 #include "ac_nir_to_llvm.h"
46 #include "ac_rtld.h"
47 #include "vk_format.h"
48 #include "util/debug.h"
49 #include "ac_exp_param.h"
50
51 #include "util/string_buffer.h"
52
53 static const struct nir_shader_compiler_options nir_options = {
54 .vertex_id_zero_based = true,
55 .lower_scmp = true,
56 .lower_flrp16 = true,
57 .lower_flrp32 = true,
58 .lower_flrp64 = true,
59 .lower_device_index_to_zero = true,
60 .lower_fsat = true,
61 .lower_fdiv = true,
62 .lower_bitfield_insert_to_bitfield_select = true,
63 .lower_bitfield_extract = true,
64 .lower_sub = true,
65 .lower_pack_snorm_2x16 = true,
66 .lower_pack_snorm_4x8 = true,
67 .lower_pack_unorm_2x16 = true,
68 .lower_pack_unorm_4x8 = true,
69 .lower_unpack_snorm_2x16 = true,
70 .lower_unpack_snorm_4x8 = true,
71 .lower_unpack_unorm_2x16 = true,
72 .lower_unpack_unorm_4x8 = true,
73 .lower_extract_byte = true,
74 .lower_extract_word = true,
75 .lower_ffma = true,
76 .lower_fpow = true,
77 .lower_mul_2x32_64 = true,
78 .lower_rotate = true,
79 .max_unroll_iterations = 32
80 };
81
82 VkResult radv_CreateShaderModule(
83 VkDevice _device,
84 const VkShaderModuleCreateInfo* pCreateInfo,
85 const VkAllocationCallbacks* pAllocator,
86 VkShaderModule* pShaderModule)
87 {
88 RADV_FROM_HANDLE(radv_device, device, _device);
89 struct radv_shader_module *module;
90
91 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO);
92 assert(pCreateInfo->flags == 0);
93
94 module = vk_alloc2(&device->alloc, pAllocator,
95 sizeof(*module) + pCreateInfo->codeSize, 8,
96 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
97 if (module == NULL)
98 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
99
100 module->nir = NULL;
101 module->size = pCreateInfo->codeSize;
102 memcpy(module->data, pCreateInfo->pCode, module->size);
103
104 _mesa_sha1_compute(module->data, module->size, module->sha1);
105
106 *pShaderModule = radv_shader_module_to_handle(module);
107
108 return VK_SUCCESS;
109 }
110
111 void radv_DestroyShaderModule(
112 VkDevice _device,
113 VkShaderModule _module,
114 const VkAllocationCallbacks* pAllocator)
115 {
116 RADV_FROM_HANDLE(radv_device, device, _device);
117 RADV_FROM_HANDLE(radv_shader_module, module, _module);
118
119 if (!module)
120 return;
121
122 vk_free2(&device->alloc, pAllocator, module);
123 }
124
125 void
126 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
127 bool allow_copies)
128 {
129 bool progress;
130 unsigned lower_flrp =
131 (shader->options->lower_flrp16 ? 16 : 0) |
132 (shader->options->lower_flrp32 ? 32 : 0) |
133 (shader->options->lower_flrp64 ? 64 : 0);
134
135 do {
136 progress = false;
137
138 NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
139 NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
140
141 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
142 NIR_PASS_V(shader, nir_lower_pack);
143
144 if (allow_copies) {
145 /* Only run this pass in the first call to
146 * radv_optimize_nir. Later calls assume that we've
147 * lowered away any copy_deref instructions and we
148 * don't want to introduce any more.
149 */
150 NIR_PASS(progress, shader, nir_opt_find_array_copies);
151 }
152
153 NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
154 NIR_PASS(progress, shader, nir_opt_dead_write_vars);
155
156 NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
157 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
158
159 NIR_PASS(progress, shader, nir_copy_prop);
160 NIR_PASS(progress, shader, nir_opt_remove_phis);
161 NIR_PASS(progress, shader, nir_opt_dce);
162 if (nir_opt_trivial_continues(shader)) {
163 progress = true;
164 NIR_PASS(progress, shader, nir_copy_prop);
165 NIR_PASS(progress, shader, nir_opt_remove_phis);
166 NIR_PASS(progress, shader, nir_opt_dce);
167 }
168 NIR_PASS(progress, shader, nir_opt_if, true);
169 NIR_PASS(progress, shader, nir_opt_dead_cf);
170 NIR_PASS(progress, shader, nir_opt_cse);
171 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
172 NIR_PASS(progress, shader, nir_opt_constant_folding);
173 NIR_PASS(progress, shader, nir_opt_algebraic);
174
175 if (lower_flrp != 0) {
176 bool lower_flrp_progress = false;
177 NIR_PASS(lower_flrp_progress,
178 shader,
179 nir_lower_flrp,
180 lower_flrp,
181 false /* always_precise */,
182 shader->options->lower_ffma);
183 if (lower_flrp_progress) {
184 NIR_PASS(progress, shader,
185 nir_opt_constant_folding);
186 progress = true;
187 }
188
189 /* Nothing should rematerialize any flrps, so we only
190 * need to do this lowering once.
191 */
192 lower_flrp = 0;
193 }
194
195 NIR_PASS(progress, shader, nir_opt_undef);
196 NIR_PASS(progress, shader, nir_opt_conditional_discard);
197 if (shader->options->max_unroll_iterations) {
198 NIR_PASS(progress, shader, nir_opt_loop_unroll, 0);
199 }
200 } while (progress && !optimize_conservatively);
201
202 NIR_PASS(progress, shader, nir_opt_shrink_load);
203 NIR_PASS(progress, shader, nir_opt_move_load_ubo);
204 }
205
206 nir_shader *
207 radv_shader_compile_to_nir(struct radv_device *device,
208 struct radv_shader_module *module,
209 const char *entrypoint_name,
210 gl_shader_stage stage,
211 const VkSpecializationInfo *spec_info,
212 const VkPipelineCreateFlags flags,
213 const struct radv_pipeline_layout *layout)
214 {
215 nir_shader *nir;
216 if (module->nir) {
217 /* Some things such as our meta clear/blit code will give us a NIR
218 * shader directly. In that case, we just ignore the SPIR-V entirely
219 * and just use the NIR shader */
220 nir = module->nir;
221 nir->options = &nir_options;
222 nir_validate_shader(nir, "in internal shader");
223
224 assert(exec_list_length(&nir->functions) == 1);
225 } else {
226 uint32_t *spirv = (uint32_t *) module->data;
227 assert(module->size % 4 == 0);
228
229 if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
230 radv_print_spirv(spirv, module->size, stderr);
231
232 uint32_t num_spec_entries = 0;
233 struct nir_spirv_specialization *spec_entries = NULL;
234 if (spec_info && spec_info->mapEntryCount > 0) {
235 num_spec_entries = spec_info->mapEntryCount;
236 spec_entries = malloc(num_spec_entries * sizeof(*spec_entries));
237 for (uint32_t i = 0; i < num_spec_entries; i++) {
238 VkSpecializationMapEntry entry = spec_info->pMapEntries[i];
239 const void *data = spec_info->pData + entry.offset;
240 assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
241
242 spec_entries[i].id = spec_info->pMapEntries[i].constantID;
243 if (spec_info->dataSize == 8)
244 spec_entries[i].data64 = *(const uint64_t *)data;
245 else
246 spec_entries[i].data32 = *(const uint32_t *)data;
247 }
248 }
249 const struct spirv_to_nir_options spirv_options = {
250 .lower_ubo_ssbo_access_to_offsets = true,
251 .caps = {
252 .amd_gcn_shader = true,
253 .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT,
254 .amd_trinary_minmax = true,
255 .derivative_group = true,
256 .descriptor_array_dynamic_indexing = true,
257 .descriptor_array_non_uniform_indexing = true,
258 .descriptor_indexing = true,
259 .device_group = true,
260 .draw_parameters = true,
261 .float16 = true,
262 .float64 = true,
263 .geometry_streams = true,
264 .image_read_without_format = true,
265 .image_write_without_format = true,
266 .int8 = true,
267 .int16 = true,
268 .int64 = true,
269 .int64_atomics = true,
270 .multiview = true,
271 .physical_storage_buffer_address = true,
272 .runtime_descriptor_array = true,
273 .shader_viewport_index_layer = true,
274 .stencil_export = true,
275 .storage_8bit = true,
276 .storage_16bit = true,
277 .storage_image_ms = true,
278 .subgroup_arithmetic = true,
279 .subgroup_ballot = true,
280 .subgroup_basic = true,
281 .subgroup_quad = true,
282 .subgroup_shuffle = true,
283 .subgroup_vote = true,
284 .tessellation = true,
285 .transform_feedback = true,
286 .variable_pointers = true,
287 },
288 .ubo_addr_format = nir_address_format_32bit_index_offset,
289 .ssbo_addr_format = nir_address_format_32bit_index_offset,
290 .phys_ssbo_addr_format = nir_address_format_64bit_global,
291 .push_const_addr_format = nir_address_format_logical,
292 .shared_addr_format = nir_address_format_32bit_offset,
293 .frag_coord_is_sysval = true,
294 };
295 nir = spirv_to_nir(spirv, module->size / 4,
296 spec_entries, num_spec_entries,
297 stage, entrypoint_name,
298 &spirv_options, &nir_options);
299 assert(nir->info.stage == stage);
300 nir_validate_shader(nir, "after spirv_to_nir");
301
302 free(spec_entries);
303
304 /* We have to lower away local constant initializers right before we
305 * inline functions. That way they get properly initialized at the top
306 * of the function and not at the top of its caller.
307 */
308 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
309 NIR_PASS_V(nir, nir_lower_returns);
310 NIR_PASS_V(nir, nir_inline_functions);
311 NIR_PASS_V(nir, nir_opt_deref);
312
313 /* Pick off the single entrypoint that we want */
314 foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
315 if (func->is_entrypoint)
316 func->name = ralloc_strdup(func, "main");
317 else
318 exec_node_remove(&func->node);
319 }
320 assert(exec_list_length(&nir->functions) == 1);
321
322 /* Make sure we lower constant initializers on output variables so that
323 * nir_remove_dead_variables below sees the corresponding stores
324 */
325 NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out);
326
327 /* Now that we've deleted all but the main function, we can go ahead and
328 * lower the rest of the constant initializers.
329 */
330 NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
331
332 /* Split member structs. We do this before lower_io_to_temporaries so that
333 * it doesn't lower system values to temporaries by accident.
334 */
335 NIR_PASS_V(nir, nir_split_var_copies);
336 NIR_PASS_V(nir, nir_split_per_member_structs);
337
338 if (nir->info.stage == MESA_SHADER_FRAGMENT)
339 NIR_PASS_V(nir, nir_lower_input_attachments, true);
340
341 NIR_PASS_V(nir, nir_remove_dead_variables,
342 nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
343
344 NIR_PASS_V(nir, nir_lower_system_values);
345 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
346 NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
347 }
348
349 /* Vulkan uses the separate-shader linking model */
350 nir->info.separate_shader = true;
351
352 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
353
354 static const nir_lower_tex_options tex_options = {
355 .lower_txp = ~0,
356 .lower_tg4_offsets = true,
357 };
358
359 nir_lower_tex(nir, &tex_options);
360
361 nir_lower_vars_to_ssa(nir);
362
363 if (nir->info.stage == MESA_SHADER_VERTEX ||
364 nir->info.stage == MESA_SHADER_GEOMETRY) {
365 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
366 nir_shader_get_entrypoint(nir), true, true);
367 } else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
368 nir->info.stage == MESA_SHADER_FRAGMENT) {
369 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
370 nir_shader_get_entrypoint(nir), true, false);
371 }
372
373 nir_split_var_copies(nir);
374
375 nir_lower_global_vars_to_local(nir);
376 nir_remove_dead_variables(nir, nir_var_function_temp);
377 nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
378 .subgroup_size = 64,
379 .ballot_bit_size = 64,
380 .lower_to_scalar = 1,
381 .lower_subgroup_masks = 1,
382 .lower_shuffle = 1,
383 .lower_shuffle_to_32bit = 1,
384 .lower_vote_eq_to_ballot = 1,
385 });
386
387 nir_lower_load_const_to_scalar(nir);
388
389 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
390 radv_optimize_nir(nir, false, true);
391
392 /* We call nir_lower_var_copies() after the first radv_optimize_nir()
393 * to remove any copies introduced by nir_opt_find_array_copies().
394 */
395 nir_lower_var_copies(nir);
396
397 /* Indirect lowering must be called after the radv_optimize_nir() loop
398 * has been called at least once. Otherwise indirect lowering can
399 * bloat the instruction count of the loop and cause it to be
400 * considered too large for unrolling.
401 */
402 ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class);
403 radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false);
404
405 return nir;
406 }
407
408 void *
409 radv_alloc_shader_memory(struct radv_device *device,
410 struct radv_shader_variant *shader)
411 {
412 mtx_lock(&device->shader_slab_mutex);
413 list_for_each_entry(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
414 uint64_t offset = 0;
415 list_for_each_entry(struct radv_shader_variant, s, &slab->shaders, slab_list) {
416 if (s->bo_offset - offset >= shader->code_size) {
417 shader->bo = slab->bo;
418 shader->bo_offset = offset;
419 list_addtail(&shader->slab_list, &s->slab_list);
420 mtx_unlock(&device->shader_slab_mutex);
421 return slab->ptr + offset;
422 }
423 offset = align_u64(s->bo_offset + s->code_size, 256);
424 }
425 if (slab->size - offset >= shader->code_size) {
426 shader->bo = slab->bo;
427 shader->bo_offset = offset;
428 list_addtail(&shader->slab_list, &slab->shaders);
429 mtx_unlock(&device->shader_slab_mutex);
430 return slab->ptr + offset;
431 }
432 }
433
434 mtx_unlock(&device->shader_slab_mutex);
435 struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab));
436
437 slab->size = 256 * 1024;
438 slab->bo = device->ws->buffer_create(device->ws, slab->size, 256,
439 RADEON_DOMAIN_VRAM,
440 RADEON_FLAG_NO_INTERPROCESS_SHARING |
441 (device->physical_device->cpdma_prefetch_writes_memory ?
442 0 : RADEON_FLAG_READ_ONLY),
443 RADV_BO_PRIORITY_SHADER);
444 slab->ptr = (char*)device->ws->buffer_map(slab->bo);
445 list_inithead(&slab->shaders);
446
447 mtx_lock(&device->shader_slab_mutex);
448 list_add(&slab->slabs, &device->shader_slabs);
449
450 shader->bo = slab->bo;
451 shader->bo_offset = 0;
452 list_add(&shader->slab_list, &slab->shaders);
453 mtx_unlock(&device->shader_slab_mutex);
454 return slab->ptr;
455 }
456
457 void
458 radv_destroy_shader_slabs(struct radv_device *device)
459 {
460 list_for_each_entry_safe(struct radv_shader_slab, slab, &device->shader_slabs, slabs) {
461 device->ws->buffer_destroy(slab->bo);
462 free(slab);
463 }
464 mtx_destroy(&device->shader_slab_mutex);
465 }
466
467 /* For the UMR disassembler. */
468 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
469 #define DEBUGGER_NUM_MARKERS 5
470
471 static unsigned
472 radv_get_shader_binary_size(size_t code_size)
473 {
474 return code_size + DEBUGGER_NUM_MARKERS * 4;
475 }
476
477 static void radv_postprocess_config(const struct radv_physical_device *pdevice,
478 const struct ac_shader_config *config_in,
479 const struct radv_shader_variant_info *info,
480 gl_shader_stage stage,
481 struct ac_shader_config *config_out)
482 {
483 bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
484 unsigned vgpr_comp_cnt = 0;
485 unsigned num_input_vgprs = info->num_input_vgprs;
486
487 if (stage == MESA_SHADER_FRAGMENT) {
488 num_input_vgprs = 0;
489 if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
490 num_input_vgprs += 2;
491 if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
492 num_input_vgprs += 2;
493 if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
494 num_input_vgprs += 2;
495 if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
496 num_input_vgprs += 3;
497 if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
498 num_input_vgprs += 2;
499 if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
500 num_input_vgprs += 2;
501 if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
502 num_input_vgprs += 2;
503 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
504 num_input_vgprs += 1;
505 if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
506 num_input_vgprs += 1;
507 if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
508 num_input_vgprs += 1;
509 if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
510 num_input_vgprs += 1;
511 if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
512 num_input_vgprs += 1;
513 if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
514 num_input_vgprs += 1;
515 if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
516 num_input_vgprs += 1;
517 if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
518 num_input_vgprs += 1;
519 if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
520 num_input_vgprs += 1;
521 }
522
523 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
524 /* +3 for scratch wave offset and VCC */
525 unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
526
527 *config_out = *config_in;
528 config_out->num_vgprs = num_vgprs;
529 config_out->num_sgprs = num_sgprs;
530
531 /* Enable 64-bit and 16-bit denormals, because there is no performance
532 * cost.
533 *
534 * If denormals are enabled, all floating-point output modifiers are
535 * ignored.
536 *
537 * Don't enable denormals for 32-bit floats, because:
538 * - Floating-point output modifiers would be ignored by the hw.
539 * - Some opcodes don't support denormals, such as v_mad_f32. We would
540 * have to stop using those.
541 * - GFX6 & GFX7 would be very slow.
542 */
543 config_out->float_mode |= V_00B028_FP_64_DENORMS;
544
545 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
546 S_00B12C_SCRATCH_EN(scratch_enabled);
547
548 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / 4) |
549 S_00B848_DX10_CLAMP(1) |
550 S_00B848_FLOAT_MODE(config_out->float_mode);
551
552 if (pdevice->rad_info.chip_class >= GFX10) {
553 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
554 } else {
555 config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
556 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5) |
557 S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
558 S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
559 S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
560 S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
561 S_00B12C_SO_EN(!!info->info.so.num_outputs);
562 }
563
564 switch (stage) {
565 case MESA_SHADER_TESS_EVAL:
566 if (info->tes.as_es) {
567 assert(pdevice->rad_info.chip_class <= GFX8);
568 vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
569 } else {
570 bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
571 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
572
573 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
574 }
575 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
576 break;
577 case MESA_SHADER_TESS_CTRL:
578 if (pdevice->rad_info.chip_class >= GFX9) {
579 /* We need at least 2 components for LS.
580 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
581 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
582 */
583 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
584 } else {
585 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
586 }
587 config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
588 break;
589 case MESA_SHADER_VERTEX:
590 if (info->is_ngg) {
591 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
592 } else if (info->vs.as_ls) {
593 assert(pdevice->rad_info.chip_class <= GFX8);
594 /* We need at least 2 components for LS.
595 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
596 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
597 */
598 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
599 } else if (info->vs.as_es) {
600 assert(pdevice->rad_info.chip_class <= GFX8);
601 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
602 vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
603 } else {
604 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
605 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
606 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
607 */
608 if (info->vs.export_prim_id) {
609 vgpr_comp_cnt = 2;
610 } else if (info->info.vs.needs_instance_id) {
611 vgpr_comp_cnt = 1;
612 } else {
613 vgpr_comp_cnt = 0;
614 }
615
616 config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
617 }
618 break;
619 case MESA_SHADER_FRAGMENT:
620 config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
621 break;
622 case MESA_SHADER_GEOMETRY:
623 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
624 break;
625 case MESA_SHADER_COMPUTE:
626 config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
627 config_out->rsrc2 |=
628 S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) |
629 S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) |
630 S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) |
631 S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 :
632 info->info.cs.uses_thread_id[1] ? 1 : 0) |
633 S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) |
634 S_00B84C_LDS_SIZE(config_in->lds_size);
635 break;
636 default:
637 unreachable("unsupported shader type");
638 break;
639 }
640
641 if (pdevice->rad_info.chip_class >= GFX10 &&
642 stage == MESA_SHADER_VERTEX) {
643 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
644
645 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
646 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0;
647 gs_vgpr_comp_cnt = 3;
648
649 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
650 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
651 S_00B22C_LDS_SIZE(config_in->lds_size);
652 } else if (pdevice->rad_info.chip_class >= GFX9 &&
653 stage == MESA_SHADER_GEOMETRY) {
654 unsigned es_type = info->gs.es_type;
655 unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
656
657 if (es_type == MESA_SHADER_VERTEX) {
658 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
659 es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
660 } else if (es_type == MESA_SHADER_TESS_EVAL) {
661 es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
662 } else {
663 unreachable("invalid shader ES type");
664 }
665
666 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
667 * VGPR[0:4] are always loaded.
668 */
669 if (info->info.uses_invocation_id) {
670 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
671 } else if (info->info.uses_prim_id) {
672 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
673 } else if (info->gs.vertices_in >= 3) {
674 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
675 } else {
676 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
677 }
678
679 config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
680 config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
681 S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
682 } else if (pdevice->rad_info.chip_class >= GFX9 &&
683 stage == MESA_SHADER_TESS_CTRL) {
684 config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
685 } else {
686 config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
687 }
688 }
689
690 static void radv_init_llvm_target()
691 {
692 LLVMInitializeAMDGPUTargetInfo();
693 LLVMInitializeAMDGPUTarget();
694 LLVMInitializeAMDGPUTargetMC();
695 LLVMInitializeAMDGPUAsmPrinter();
696
697 /* For inline assembly. */
698 LLVMInitializeAMDGPUAsmParser();
699
700 /* Workaround for bug in llvm 4.0 that causes image intrinsics
701 * to disappear.
702 * https://reviews.llvm.org/D26348
703 *
704 * Workaround for bug in llvm that causes the GPU to hang in presence
705 * of nested loops because there is an exec mask issue. The proper
706 * solution is to fix LLVM but this might require a bunch of work.
707 * https://bugs.llvm.org/show_bug.cgi?id=37744
708 *
709 * "mesa" is the prefix for error messages.
710 */
711 if (HAVE_LLVM >= 0x0800) {
712 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
713 LLVMParseCommandLineOptions(2, argv, NULL);
714
715 } else {
716 const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false",
717 "-amdgpu-skip-threshold=1" };
718 LLVMParseCommandLineOptions(3, argv, NULL);
719 }
720 }
721
722 static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
723
724 static void radv_init_llvm_once(void)
725 {
726 call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
727 }
728
729 struct radv_shader_variant *
730 radv_shader_variant_create(struct radv_device *device,
731 const struct radv_shader_binary *binary)
732 {
733 struct ac_shader_config config = {0};
734 struct ac_rtld_binary rtld_binary = {0};
735 struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
736 if (!variant)
737 return NULL;
738
739 variant->ref_count = 1;
740
741 if (binary->type == RADV_BINARY_TYPE_RTLD) {
742 struct ac_rtld_symbol lds_symbols[1];
743 unsigned num_lds_symbols = 0;
744 const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
745 size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
746
747 if (device->physical_device->rad_info.chip_class >= GFX9 &&
748 binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) {
749 /* We add this symbol even on LLVM <= 8 to ensure that
750 * shader->config.lds_size is set correctly below.
751 */
752 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
753 sym->name = "esgs_ring";
754 sym->size = 32 * 1024;
755 sym->align = 64 * 1024;
756 }
757 struct ac_rtld_open_info open_info = {
758 .info = &device->physical_device->rad_info,
759 .shader_type = binary->stage,
760 .num_parts = 1,
761 .elf_ptrs = &elf_data,
762 .elf_sizes = &elf_size,
763 .num_shared_lds_symbols = num_lds_symbols,
764 .shared_lds_symbols = lds_symbols,
765 };
766
767 if (!ac_rtld_open(&rtld_binary, open_info)) {
768 free(variant);
769 return NULL;
770 }
771
772 if (!ac_rtld_read_config(&rtld_binary, &config)) {
773 ac_rtld_close(&rtld_binary);
774 free(variant);
775 return NULL;
776 }
777
778 if (rtld_binary.lds_size > 0) {
779 unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
780 config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
781 }
782
783 variant->code_size = rtld_binary.rx_size;
784 } else {
785 assert(binary->type == RADV_BINARY_TYPE_LEGACY);
786 config = ((struct radv_shader_binary_legacy *)binary)->config;
787 variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
788 }
789
790 variant->info = binary->variant_info;
791 radv_postprocess_config(device->physical_device, &config, &binary->variant_info,
792 binary->stage, &variant->config);
793
794 void *dest_ptr = radv_alloc_shader_memory(device, variant);
795
796 if (binary->type == RADV_BINARY_TYPE_RTLD) {
797 struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
798 struct ac_rtld_upload_info info = {
799 .binary = &rtld_binary,
800 .rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
801 .rx_ptr = dest_ptr,
802 };
803
804 if (!ac_rtld_upload(&info)) {
805 radv_shader_variant_destroy(device, variant);
806 ac_rtld_close(&rtld_binary);
807 return NULL;
808 }
809
810 const char *disasm_data;
811 size_t disasm_size;
812 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
813 radv_shader_variant_destroy(device, variant);
814 ac_rtld_close(&rtld_binary);
815 return NULL;
816 }
817
818 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
819 variant->disasm_string = malloc(disasm_size + 1);
820 memcpy(variant->disasm_string, disasm_data, disasm_size);
821 variant->disasm_string[disasm_size] = 0;
822
823 ac_rtld_close(&rtld_binary);
824 } else {
825 struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
826 memcpy(dest_ptr, bin->data, bin->code_size);
827
828 /* Add end-of-code markers for the UMR disassembler. */
829 uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
830 for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
831 ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
832
833 variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
834 variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
835 }
836 return variant;
837 }
838
839 static struct radv_shader_variant *
840 shader_variant_compile(struct radv_device *device,
841 struct radv_shader_module *module,
842 struct nir_shader * const *shaders,
843 int shader_count,
844 gl_shader_stage stage,
845 struct radv_nir_compiler_options *options,
846 bool gs_copy_shader,
847 struct radv_shader_binary **binary_out)
848 {
849 enum radeon_family chip_family = device->physical_device->rad_info.family;
850 enum ac_target_machine_options tm_options = 0;
851 struct ac_llvm_compiler ac_llvm;
852 struct radv_shader_binary *binary = NULL;
853 struct radv_shader_variant_info variant_info = {0};
854 bool thread_compiler;
855
856 options->family = chip_family;
857 options->chip_class = device->physical_device->rad_info.chip_class;
858 options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader);
859 options->dump_preoptir = options->dump_shader &&
860 device->instance->debug_flags & RADV_DEBUG_PREOPTIR;
861 options->record_llvm_ir = device->keep_shader_info;
862 options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR;
863 options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size;
864 options->address32_hi = device->physical_device->rad_info.address32_hi;
865
866 if (options->supports_spill)
867 tm_options |= AC_TM_SUPPORTS_SPILL;
868 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
869 tm_options |= AC_TM_SISCHED;
870 if (options->check_ir)
871 tm_options |= AC_TM_CHECK_IR;
872 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
873 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
874
875 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
876 radv_init_llvm_once();
877 radv_init_llvm_compiler(&ac_llvm,
878 thread_compiler,
879 chip_family, tm_options);
880 if (gs_copy_shader) {
881 assert(shader_count == 1);
882 radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
883 &variant_info, options);
884 } else {
885 radv_compile_nir_shader(&ac_llvm, &binary, &variant_info,
886 shaders, shader_count, options);
887 }
888 binary->variant_info = variant_info;
889
890 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
891
892 struct radv_shader_variant *variant = radv_shader_variant_create(device, binary);
893 if (!variant) {
894 free(binary);
895 return NULL;
896 }
897
898 if (options->dump_shader) {
899 fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
900 }
901
902
903 if (device->keep_shader_info) {
904 if (!gs_copy_shader && !module->nir) {
905 variant->nir = *shaders;
906 variant->spirv = (uint32_t *)module->data;
907 variant->spirv_size = module->size;
908 }
909 }
910
911 if (binary_out)
912 *binary_out = binary;
913 else
914 free(binary);
915
916 return variant;
917 }
918
919 struct radv_shader_variant *
920 radv_shader_variant_compile(struct radv_device *device,
921 struct radv_shader_module *module,
922 struct nir_shader *const *shaders,
923 int shader_count,
924 struct radv_pipeline_layout *layout,
925 const struct radv_shader_variant_key *key,
926 struct radv_shader_binary **binary_out)
927 {
928 struct radv_nir_compiler_options options = {0};
929
930 options.layout = layout;
931 if (key)
932 options.key = *key;
933
934 options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
935 options.supports_spill = true;
936
937 return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
938 &options, false, binary_out);
939 }
940
941 struct radv_shader_variant *
942 radv_create_gs_copy_shader(struct radv_device *device,
943 struct nir_shader *shader,
944 struct radv_shader_binary **binary_out,
945 bool multiview)
946 {
947 struct radv_nir_compiler_options options = {0};
948
949 options.key.has_multiview_view_index = multiview;
950
951 return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
952 &options, true, binary_out);
953 }
954
955 void
956 radv_shader_variant_destroy(struct radv_device *device,
957 struct radv_shader_variant *variant)
958 {
959 if (!p_atomic_dec_zero(&variant->ref_count))
960 return;
961
962 mtx_lock(&device->shader_slab_mutex);
963 list_del(&variant->slab_list);
964 mtx_unlock(&device->shader_slab_mutex);
965
966 ralloc_free(variant->nir);
967 free(variant->disasm_string);
968 free(variant->llvm_ir_string);
969 free(variant);
970 }
971
972 const char *
973 radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
974 {
975 switch (stage) {
976 case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
977 case MESA_SHADER_GEOMETRY: return "Geometry Shader";
978 case MESA_SHADER_FRAGMENT: return "Pixel Shader";
979 case MESA_SHADER_COMPUTE: return "Compute Shader";
980 case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
981 case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
982 default:
983 return "Unknown shader";
984 };
985 }
986
987 static void
988 generate_shader_stats(struct radv_device *device,
989 struct radv_shader_variant *variant,
990 gl_shader_stage stage,
991 struct _mesa_string_buffer *buf)
992 {
993 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
994 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
995 struct ac_shader_config *conf;
996 unsigned max_simd_waves;
997 unsigned lds_per_wave = 0;
998
999 max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
1000
1001 conf = &variant->config;
1002
1003 if (stage == MESA_SHADER_FRAGMENT) {
1004 lds_per_wave = conf->lds_size * lds_increment +
1005 align(variant->info.fs.num_interp * 48,
1006 lds_increment);
1007 } else if (stage == MESA_SHADER_COMPUTE) {
1008 unsigned max_workgroup_size =
1009 radv_nir_get_max_workgroup_size(chip_class, variant->nir);
1010 lds_per_wave = (conf->lds_size * lds_increment) /
1011 DIV_ROUND_UP(max_workgroup_size, 64);
1012 }
1013
1014 if (conf->num_sgprs)
1015 max_simd_waves =
1016 MIN2(max_simd_waves,
1017 ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
1018
1019 if (conf->num_vgprs)
1020 max_simd_waves =
1021 MIN2(max_simd_waves,
1022 RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs);
1023
1024 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
1025 * that PS can use.
1026 */
1027 if (lds_per_wave)
1028 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
1029
1030 if (stage == MESA_SHADER_FRAGMENT) {
1031 _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n"
1032 "SPI_PS_INPUT_ADDR = 0x%04x\n"
1033 "SPI_PS_INPUT_ENA = 0x%04x\n",
1034 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
1035 }
1036
1037 _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n"
1038 "SGPRS: %d\n"
1039 "VGPRS: %d\n"
1040 "Spilled SGPRs: %d\n"
1041 "Spilled VGPRs: %d\n"
1042 "PrivMem VGPRS: %d\n"
1043 "Code Size: %d bytes\n"
1044 "LDS: %d blocks\n"
1045 "Scratch: %d bytes per wave\n"
1046 "Max Waves: %d\n"
1047 "********************\n\n\n",
1048 conf->num_sgprs, conf->num_vgprs,
1049 conf->spilled_sgprs, conf->spilled_vgprs,
1050 variant->info.private_mem_vgprs, variant->code_size,
1051 conf->lds_size, conf->scratch_bytes_per_wave,
1052 max_simd_waves);
1053 }
1054
1055 void
1056 radv_shader_dump_stats(struct radv_device *device,
1057 struct radv_shader_variant *variant,
1058 gl_shader_stage stage,
1059 FILE *file)
1060 {
1061 struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256);
1062
1063 generate_shader_stats(device, variant, stage, buf);
1064
1065 fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
1066 fprintf(file, "%s", buf->buf);
1067
1068 _mesa_string_buffer_destroy(buf);
1069 }
1070
1071 VkResult
1072 radv_GetShaderInfoAMD(VkDevice _device,
1073 VkPipeline _pipeline,
1074 VkShaderStageFlagBits shaderStage,
1075 VkShaderInfoTypeAMD infoType,
1076 size_t* pInfoSize,
1077 void* pInfo)
1078 {
1079 RADV_FROM_HANDLE(radv_device, device, _device);
1080 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
1081 gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage);
1082 struct radv_shader_variant *variant = pipeline->shaders[stage];
1083 struct _mesa_string_buffer *buf;
1084 VkResult result = VK_SUCCESS;
1085
1086 /* Spec doesn't indicate what to do if the stage is invalid, so just
1087 * return no info for this. */
1088 if (!variant)
1089 return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1090
1091 switch (infoType) {
1092 case VK_SHADER_INFO_TYPE_STATISTICS_AMD:
1093 if (!pInfo) {
1094 *pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
1095 } else {
1096 unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
1097 struct ac_shader_config *conf = &variant->config;
1098
1099 VkShaderStatisticsInfoAMD statistics = {};
1100 statistics.shaderStageMask = shaderStage;
1101 statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
1102 statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
1103 statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
1104
1105 if (stage == MESA_SHADER_COMPUTE) {
1106 unsigned *local_size = variant->nir->info.cs.local_size;
1107 unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2];
1108
1109 statistics.numAvailableVgprs = statistics.numPhysicalVgprs /
1110 ceil((double)workgroup_size / statistics.numPhysicalVgprs);
1111
1112 statistics.computeWorkGroupSize[0] = local_size[0];
1113 statistics.computeWorkGroupSize[1] = local_size[1];
1114 statistics.computeWorkGroupSize[2] = local_size[2];
1115 } else {
1116 statistics.numAvailableVgprs = statistics.numPhysicalVgprs;
1117 }
1118
1119 statistics.resourceUsage.numUsedVgprs = conf->num_vgprs;
1120 statistics.resourceUsage.numUsedSgprs = conf->num_sgprs;
1121 statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768;
1122 statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier;
1123 statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave;
1124
1125 size_t size = *pInfoSize;
1126 *pInfoSize = sizeof(statistics);
1127
1128 memcpy(pInfo, &statistics, MIN2(size, *pInfoSize));
1129
1130 if (size < *pInfoSize)
1131 result = VK_INCOMPLETE;
1132 }
1133
1134 break;
1135 case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
1136 buf = _mesa_string_buffer_create(NULL, 1024);
1137
1138 _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
1139 _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
1140 _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
1141 generate_shader_stats(device, variant, stage, buf);
1142
1143 /* Need to include the null terminator. */
1144 size_t length = buf->length + 1;
1145
1146 if (!pInfo) {
1147 *pInfoSize = length;
1148 } else {
1149 size_t size = *pInfoSize;
1150 *pInfoSize = length;
1151
1152 memcpy(pInfo, buf->buf, MIN2(size, length));
1153
1154 if (size < length)
1155 result = VK_INCOMPLETE;
1156 }
1157
1158 _mesa_string_buffer_destroy(buf);
1159 break;
1160 default:
1161 /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */
1162 result = VK_ERROR_FEATURE_NOT_PRESENT;
1163 break;
1164 }
1165
1166 return result;
1167 }