radv: Make FragCoord a sysval

load_fragcoord is already handled in common code for radeonsi, so we
don't need to do anything to handle it. However, there were some passes
creating NIR with the varying, so we switch them over to the sysval. In
the case of nir_lower_input_attachments which is used by both radv and
anv, we add handling for both until intel switches to using a sysval.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c b/src/amd/vulkan/radv_meta_resolve_fs.c
index 8ee3cc07f123995684c12ba4116014b937d7384a..e6edc159372b4cd6c1aab1c19fadc2c7886a218f 100644 (file)
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -55,7 +55,6 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
 {
        nir_builder b;
        char name[64];
-       const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
        const struct glsl_type *vec4 = glsl_vec4_type();
        const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
                                                                 false,
@@ -71,14 +70,11 @@ build_resolve_fragment_shader(struct radv_device *dev, bool is_integer, int samp
        input_img->data.descriptor_set = 0;
        input_img->data.binding = 0;
 
-       nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
-       fs_pos_in->data.location = VARYING_SLOT_POS;
-
        nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
                                                      vec4, "f_color");
        color_out->data.location = FRAG_RESULT_DATA0;
 
-       nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
+       nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
        nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
        nir_intrinsic_set_base(src_offset, 0);
        nir_intrinsic_set_range(src_offset, 8);
@@ -345,7 +341,6 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
 {
        nir_builder b;
        char name[64];
-       const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
        const struct glsl_type *vec4 = glsl_vec4_type();
        const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
                                                                 false,
@@ -364,16 +359,13 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
        input_img->data.descriptor_set = 0;
        input_img->data.binding = 0;
 
-       nir_variable *fs_pos_in = nir_variable_create(b.shader, nir_var_shader_in, vec2, "fs_pos_in");
-       fs_pos_in->data.location = VARYING_SLOT_POS;
-
        nir_variable *fs_out = nir_variable_create(b.shader,
                                                   nir_var_shader_out, vec4,
                                                   "f_out");
        fs_out->data.location =
                index == DEPTH_RESOLVE ? FRAG_RESULT_DEPTH : FRAG_RESULT_STENCIL;
 
-       nir_ssa_def *pos_in = nir_load_var(&b, fs_pos_in);
+       nir_ssa_def *pos_in = nir_channels(&b, nir_load_frag_coord(&b), 0x3);
 
        nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
        nir_intrinsic_set_base(src_offset, 0);

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 323c7c5aecacf7dc836574182e21c635c0c3bbb2..aabb297ca21a36e0d60cbc0c79df567b5cbb6d8e 100644 (file)
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2516,12 +2516,6 @@ handle_fs_inputs(struct radv_shader_context *ctx,
                                                ctx->abi.prim_mask, false, inputs);
                                ++index;
                        }
-               } else if (i == VARYING_SLOT_POS) {
-                       for(int i = 0; i < 3; ++i)
-                               inputs[i] = ctx->abi.frag_pos[i];
-
-                       inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
-                                                 ctx->abi.frag_pos[3]);
                }
        }
        ctx->shader_info->fs.num_interp = index;

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 791ceabb091806fc929257b6e88edb12cd92b1cc..839166992d148213baa38eee79c4257b461deee6 100644 (file)
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -290,6 +290,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                        .phys_ssbo_addr_format = nir_address_format_64bit_global,
                        .push_const_addr_format = nir_address_format_logical,
                        .shared_addr_format = nir_address_format_32bit_offset,
+                       .frag_coord_is_sysval = true,
                };
                nir = spirv_to_nir(spirv, module->size / 4,
                                   spec_entries, num_spec_entries,
@@ -335,7 +336,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                NIR_PASS_V(nir, nir_split_per_member_structs);
 
                if (nir->info.stage == MESA_SHADER_FRAGMENT)
-                       NIR_PASS_V(nir, nir_lower_input_attachments);
+                       NIR_PASS_V(nir, nir_lower_input_attachments, true);
 
                NIR_PASS_V(nir, nir_remove_dead_variables,
                           nir_var_shader_in | nir_var_shader_out | nir_var_system_value);

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index ffb6908073b130bdf9fdad24eb14fe1be709e659..8e5102f53d8ec2e5c95fcfe9b72a1dc417e7eca5 100644 (file)
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -3494,7 +3494,7 @@ bool nir_lower_non_uniform_access(nir_shader *shader,
 
 bool nir_lower_idiv(nir_shader *shader);
 
-bool nir_lower_input_attachments(nir_shader *shader);
+bool nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval);
 
 bool nir_lower_clip_vs(nir_shader *shader, unsigned ucp_enables, bool use_vars);
 bool nir_lower_clip_fs(nir_shader *shader, unsigned ucp_enables);

diff --git a/src/compiler/nir/nir_lower_input_attachments.c b/src/compiler/nir/nir_lower_input_attachments.c
index 25473eab558f85cc73316b9a77f657c0b351bd42..a8e71f7113ac3d404f5f4d390c8f967f092565da 100644 (file)
--- a/src/compiler/nir/nir_lower_input_attachments.c
+++ b/src/compiler/nir/nir_lower_input_attachments.c
@@ -48,7 +48,8 @@ load_frag_coord(nir_builder *b)
 }
 
 static bool
-try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
+try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load,
+                     bool use_fragcoord_sysval)
 {
    nir_deref_instr *deref = nir_src_as_deref(load->src[0]);
    assert(glsl_type_is_image(deref->type));
@@ -64,7 +65,9 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
    nir_builder_init(&b, impl);
    b.cursor = nir_instr_remove(&load->instr);
 
-   nir_ssa_def *frag_coord = nir_f2i32(&b, load_frag_coord(&b));
+   nir_ssa_def *frag_coord = use_fragcoord_sysval ? nir_load_frag_coord(&b)
+                                                  : load_frag_coord(&b);
+   frag_coord = nir_f2i32(&b, frag_coord);
    nir_ssa_def *offset = nir_ssa_for_src(&b, load->src[1], 2);
    nir_ssa_def *pos = nir_iadd(&b, frag_coord, offset);
 
@@ -122,7 +125,7 @@ try_lower_input_load(nir_function_impl *impl, nir_intrinsic_instr *load)
 }
 
 bool
-nir_lower_input_attachments(nir_shader *shader)
+nir_lower_input_attachments(nir_shader *shader, bool use_fragcoord_sysval)
 {
    assert(shader->info.stage == MESA_SHADER_FRAGMENT);
    bool progress = false;
@@ -141,7 +144,8 @@ nir_lower_input_attachments(nir_shader *shader)
             if (load->intrinsic != nir_intrinsic_image_deref_load)
                continue;
 
-            progress |= try_lower_input_load(function->impl, load);
+            progress |= try_lower_input_load(function->impl, load,
+                                             use_fragcoord_sysval);
          }
       }
    }

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 8fa02aedfa13225ce427592d35406b6339eb05ca..051c3334aa88de301245fc5415a2311baecd7ab9 100644 (file)
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -607,7 +607,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
 
    if (nir->info.stage == MESA_SHADER_FRAGMENT) {
       NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
-      NIR_PASS_V(nir, nir_lower_input_attachments);
+      NIR_PASS_V(nir, nir_lower_input_attachments, false);
    }
 
    NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);