src/amd/vulkan/radv_shader_info.c

   1 /*
   2  * Copyright © 2017 Red Hat
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23 #include "radv_private.h"
  24 #include "radv_shader.h"
  25 #include "nir/nir.h"
  26
  27 static void mark_sampler_desc(const nir_variable *var,
  28                               struct radv_shader_info *info)
  29 {
  30         info->desc_set_used_mask |= (1 << var->data.descriptor_set);
  31 }
  32
  33 static void mark_ls_output(struct radv_shader_info *info,
  34                            uint32_t param, int num_slots)
  35 {
  36         uint64_t mask = (1ull << num_slots) - 1ull;
  37         info->vs.ls_outputs_written |= (mask << param);
  38 }
  39
  40 static void mark_tess_output(struct radv_shader_info *info,
  41                              bool is_patch, uint32_t param, int num_slots)
  42 {
  43         uint64_t mask = (1ull << num_slots) - 1ull;
  44         if (is_patch)
  45                 info->tcs.patch_outputs_written |= (mask << param);
  46         else
  47                 info->tcs.outputs_written |= (mask << param);
  48 }
  49
  50 static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
  51 {
  52         nir_deref *tail = &deref->deref;
  53         unsigned const_offset = 0;
  54
  55         if (deref->var->data.compact) {
  56                 assert(tail->child->deref_type == nir_deref_type_array);
  57                 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
  58
  59                 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
  60                 /* We always lower indirect dereferences for "compact" array vars. */
  61                 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
  62
  63                 *const_out = deref_array->base_offset;
  64                 return;
  65         }
  66
  67         while (tail->child != NULL) {
  68                 const struct glsl_type *parent_type = tail->type;
  69                 tail = tail->child;
  70
  71                 if (tail->deref_type == nir_deref_type_array) {
  72                         nir_deref_array *deref_array = nir_deref_as_array(tail);
  73                         unsigned size = glsl_count_attribute_slots(tail->type, false);
  74
  75                         const_offset += size * deref_array->base_offset;
  76                 } else if (tail->deref_type == nir_deref_type_struct) {
  77                         nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
  78
  79                         for (unsigned i = 0; i < deref_struct->index; i++) {
  80                                 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
  81                                 const_offset += glsl_count_attribute_slots(ft, false);
  82                         }
  83                 } else
  84                         unreachable("unsupported deref type");
  85         }
  86
  87         *const_out = const_offset;
  88 }
  89
  90 static void
  91 gather_intrinsic_load_var_info(const nir_shader *nir,
  92                                const nir_intrinsic_instr *instr,
  93                                struct radv_shader_info *info)
  94 {
  95         switch (nir->info.stage) {
  96         case MESA_SHADER_VERTEX: {
  97                 nir_deref_var *dvar = instr->variables[0];
  98                 nir_variable *var = dvar->var;
  99
 100                 if (var->data.mode == nir_var_shader_in) {
 101                         unsigned idx = var->data.location;
 102                         uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
 103
 104                         info->vs.input_usage_mask[idx] |=
 105                                 mask << var->data.location_frac;
 106                 }
 107                 break;
 108         }
 109         default:
 110                 break;
 111         }
 112 }
 113
 114 static void
 115 gather_intrinsic_store_var_info(const nir_shader *nir,
 116                                 const nir_intrinsic_instr *instr,
 117                                 struct radv_shader_info *info)
 118 {
 119         nir_deref_var *dvar = instr->variables[0];
 120         nir_variable *var = dvar->var;
 121
 122         if (var->data.mode == nir_var_shader_out) {
 123                 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
 124                 unsigned idx = var->data.location;
 125                 unsigned comp = var->data.location_frac;
 126                 unsigned const_offset = 0;
 127
 128                 get_deref_offset(dvar, &const_offset);
 129
 130                 switch (nir->info.stage) {
 131                 case MESA_SHADER_VERTEX:
 132                         for (unsigned i = 0; i < attrib_count; i++) {
 133                                 info->vs.output_usage_mask[idx + i + const_offset] |=
 134                                         instr->const_index[0] << comp;
 135                         }
 136                         break;
 137                 case MESA_SHADER_TESS_EVAL:
 138                         for (unsigned i = 0; i < attrib_count; i++) {
 139                                 info->tes.output_usage_mask[idx + i + const_offset] |=
 140                                         instr->const_index[0] << comp;
 141                         }
 142                         break;
 143                 case MESA_SHADER_TESS_CTRL: {
 144                         unsigned param = shader_io_get_unique_index(idx);
 145                         const struct glsl_type *type = var->type;
 146
 147                         if (!var->data.patch)
 148                                 type = glsl_get_array_element(var->type);
 149
 150                         unsigned slots =
 151                                 var->data.compact ? DIV_ROUND_UP(glsl_get_length(type), 4)
 152                                                   : glsl_count_attribute_slots(type, false);
 153
 154                         if (idx == VARYING_SLOT_CLIP_DIST0)
 155                                 slots = (nir->info.clip_distance_array_size +
 156                                          nir->info.cull_distance_array_size > 4) ? 2 : 1;
 157
 158                         mark_tess_output(info, var->data.patch, param, slots);
 159                         break;
 160                 }
 161                 default:
 162                         break;
 163                 }
 164         }
 165 }
 166
 167 static void
 168 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
 169                       struct radv_shader_info *info)
 170 {
 171         switch (instr->intrinsic) {
 172         case nir_intrinsic_interp_var_at_sample:
 173                 info->ps.needs_sample_positions = true;
 174                 break;
 175         case nir_intrinsic_load_draw_id:
 176                 info->vs.needs_draw_id = true;
 177                 break;
 178         case nir_intrinsic_load_instance_id:
 179                 info->vs.needs_instance_id = true;
 180                 break;
 181         case nir_intrinsic_load_num_work_groups:
 182                 info->cs.uses_grid_size = true;
 183                 break;
 184         case nir_intrinsic_load_local_invocation_id:
 185         case nir_intrinsic_load_work_group_id: {
 186                 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
 187                 while (mask) {
 188                         unsigned i = u_bit_scan(&mask);
 189
 190                         if (instr->intrinsic == nir_intrinsic_load_work_group_id)
 191                                 info->cs.uses_block_id[i] = true;
 192                         else
 193                                 info->cs.uses_thread_id[i] = true;
 194                 }
 195                 break;
 196         }
 197         case nir_intrinsic_load_local_invocation_index:
 198         case nir_intrinsic_load_subgroup_id:
 199         case nir_intrinsic_load_num_subgroups:
 200                 info->cs.uses_local_invocation_idx = true;
 201                 break;
 202         case nir_intrinsic_load_sample_id:
 203                 info->ps.force_persample = true;
 204                 break;
 205         case nir_intrinsic_load_sample_pos:
 206                 info->ps.force_persample = true;
 207                 break;
 208         case nir_intrinsic_load_view_index:
 209                 info->needs_multiview_view_index = true;
 210                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 211                         info->ps.layer_input = true;
 212                 break;
 213         case nir_intrinsic_load_invocation_id:
 214                 info->uses_invocation_id = true;
 215                 break;
 216         case nir_intrinsic_load_primitive_id:
 217                 info->uses_prim_id = true;
 218                 break;
 219         case nir_intrinsic_load_push_constant:
 220                 info->loads_push_constants = true;
 221                 break;
 222         case nir_intrinsic_vulkan_resource_index:
 223                 info->desc_set_used_mask |= (1 << nir_intrinsic_desc_set(instr));
 224                 break;
 225         case nir_intrinsic_image_var_load:
 226         case nir_intrinsic_image_var_store:
 227         case nir_intrinsic_image_var_atomic_add:
 228         case nir_intrinsic_image_var_atomic_min:
 229         case nir_intrinsic_image_var_atomic_max:
 230         case nir_intrinsic_image_var_atomic_and:
 231         case nir_intrinsic_image_var_atomic_or:
 232         case nir_intrinsic_image_var_atomic_xor:
 233         case nir_intrinsic_image_var_atomic_exchange:
 234         case nir_intrinsic_image_var_atomic_comp_swap:
 235         case nir_intrinsic_image_var_size: {
 236                 const struct glsl_type *type = instr->variables[0]->var->type;
 237                 if(instr->variables[0]->deref.child)
 238                         type = instr->variables[0]->deref.child->type;
 239
 240                 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
 241                 if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
 242                     dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
 243                         info->ps.layer_input = true;
 244                         info->ps.uses_input_attachments = true;
 245                 }
 246                 mark_sampler_desc(instr->variables[0]->var, info);
 247
 248                 if (nir_intrinsic_image_var_store ||
 249                     nir_intrinsic_image_var_atomic_add ||
 250                     nir_intrinsic_image_var_atomic_min ||
 251                     nir_intrinsic_image_var_atomic_max ||
 252                     nir_intrinsic_image_var_atomic_and ||
 253                     nir_intrinsic_image_var_atomic_or ||
 254                     nir_intrinsic_image_var_atomic_xor ||
 255                     nir_intrinsic_image_var_atomic_exchange ||
 256                     nir_intrinsic_image_var_atomic_comp_swap) {
 257                         if (nir->info.stage == MESA_SHADER_FRAGMENT)
 258                                 info->ps.writes_memory = true;
 259                 }
 260                 break;
 261         }
 262         case nir_intrinsic_store_ssbo:
 263         case nir_intrinsic_ssbo_atomic_add:
 264         case nir_intrinsic_ssbo_atomic_imin:
 265         case nir_intrinsic_ssbo_atomic_umin:
 266         case nir_intrinsic_ssbo_atomic_imax:
 267         case nir_intrinsic_ssbo_atomic_umax:
 268         case nir_intrinsic_ssbo_atomic_and:
 269         case nir_intrinsic_ssbo_atomic_or:
 270         case nir_intrinsic_ssbo_atomic_xor:
 271         case nir_intrinsic_ssbo_atomic_exchange:
 272         case nir_intrinsic_ssbo_atomic_comp_swap:
 273                 if (nir->info.stage == MESA_SHADER_FRAGMENT)
 274                         info->ps.writes_memory = true;
 275                 break;
 276         case nir_intrinsic_load_var:
 277                 gather_intrinsic_load_var_info(nir, instr, info);
 278                 break;
 279         case nir_intrinsic_store_var:
 280                 gather_intrinsic_store_var_info(nir, instr, info);
 281                 break;
 282         default:
 283                 break;
 284         }
 285 }
 286
 287 static void
 288 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr,
 289                 struct radv_shader_info *info)
 290 {
 291         if (instr->sampler)
 292                 mark_sampler_desc(instr->sampler->var, info);
 293         if (instr->texture)
 294                 mark_sampler_desc(instr->texture->var, info);
 295 }
 296
 297 static void
 298 gather_info_block(const nir_shader *nir, const nir_block *block,
 299                   struct radv_shader_info *info)
 300 {
 301         nir_foreach_instr(instr, block) {
 302                 switch (instr->type) {
 303                 case nir_instr_type_intrinsic:
 304                         gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info);
 305                         break;
 306                 case nir_instr_type_tex:
 307                         gather_tex_info(nir, nir_instr_as_tex(instr), info);
 308                         break;
 309                 default:
 310                         break;
 311                 }
 312         }
 313 }
 314
 315 static void
 316 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 317                           struct radv_shader_info *info)
 318 {
 319         int idx = var->data.location;
 320
 321         if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
 322                 info->vs.has_vertex_buffers = true;
 323 }
 324
 325 static void
 326 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
 327                           struct radv_shader_info *info)
 328 {
 329         const struct glsl_type *type = glsl_without_array(var->type);
 330         int idx = var->data.location;
 331
 332         switch (idx) {
 333         case VARYING_SLOT_PNTC:
 334                 info->ps.has_pcoord = true;
 335                 break;
 336         case VARYING_SLOT_PRIMITIVE_ID:
 337                 info->ps.prim_id_input = true;
 338                 break;
 339         case VARYING_SLOT_LAYER:
 340                 info->ps.layer_input = true;
 341                 break;
 342         default:
 343                 break;
 344         }
 345
 346         if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
 347                 if (var->data.sample)
 348                         info->ps.force_persample = true;
 349         }
 350 }
 351
 352 static void
 353 gather_info_input_decl(const nir_shader *nir, const nir_variable *var,
 354                        struct radv_shader_info *info)
 355 {
 356         switch (nir->info.stage) {
 357         case MESA_SHADER_VERTEX:
 358                 gather_info_input_decl_vs(nir, var, info);
 359                 break;
 360         case MESA_SHADER_FRAGMENT:
 361                 gather_info_input_decl_ps(nir, var, info);
 362                 break;
 363         default:
 364                 break;
 365         }
 366 }
 367
 368 static void
 369 gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
 370                            struct radv_shader_info *info)
 371 {
 372         int idx = var->data.location;
 373         unsigned param = shader_io_get_unique_index(idx);
 374         int num_slots = glsl_count_attribute_slots(var->type, false);
 375         if (idx == VARYING_SLOT_CLIP_DIST0)
 376                 num_slots = (nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 2 : 1;
 377         mark_ls_output(info, param, num_slots);
 378 }
 379
 380 static void
 381 gather_info_output_decl_ps(const nir_shader *nir, const nir_variable *var,
 382                            struct radv_shader_info *info)
 383 {
 384         int idx = var->data.location;
 385
 386         switch (idx) {
 387         case FRAG_RESULT_DEPTH:
 388                 info->ps.writes_z = true;
 389                 break;
 390         case FRAG_RESULT_STENCIL:
 391                 info->ps.writes_stencil = true;
 392                 break;
 393         case FRAG_RESULT_SAMPLE_MASK:
 394                 info->ps.writes_sample_mask = true;
 395                 break;
 396         default:
 397                 break;
 398         }
 399 }
 400
 401 static void
 402 gather_info_output_decl(const nir_shader *nir, const nir_variable *var,
 403                         struct radv_shader_info *info,
 404                         const struct radv_nir_compiler_options *options)
 405 {
 406         switch (nir->info.stage) {
 407         case MESA_SHADER_FRAGMENT:
 408                 gather_info_output_decl_ps(nir, var, info);
 409                 break;
 410         case MESA_SHADER_VERTEX:
 411                 if (options->key.vs.as_ls)
 412                         gather_info_output_decl_ls(nir, var, info);
 413                 break;
 414         default:
 415                 break;
 416         }
 417 }
 418
 419 void
 420 radv_nir_shader_info_pass(const struct nir_shader *nir,
 421                           const struct radv_nir_compiler_options *options,
 422                           struct radv_shader_info *info)
 423 {
 424         struct nir_function *func =
 425                 (struct nir_function *)exec_list_get_head_const(&nir->functions);
 426
 427         if (options->layout->dynamic_offset_count)
 428                 info->loads_push_constants = true;
 429
 430         nir_foreach_variable(variable, &nir->inputs)
 431                 gather_info_input_decl(nir, variable, info);
 432
 433         nir_foreach_block(block, func->impl) {
 434                 gather_info_block(nir, block, info);
 435         }
 436
 437         nir_foreach_variable(variable, &nir->outputs)
 438                 gather_info_output_decl(nir, variable, info, options);
 439 }