src/arch/arm/decoder.hh

   1 /*
   2  * Copyright (c) 2013-2014 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2012 Google
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_DECODER_HH__
  42 #define __ARCH_ARM_DECODER_HH__
  43
  44 #include <cassert>
  45
  46 #include "arch/arm/miscregs.hh"
  47 #include "arch/arm/types.hh"
  48 #include "arch/generic/decode_cache.hh"
  49 #include "arch/generic/decoder.hh"
  50 #include "base/types.hh"
  51 #include "cpu/static_inst.hh"
  52 #include "debug/Decode.hh"
  53 #include "enums/DecoderFlavor.hh"
  54
  55 namespace ArmISA
  56 {
  57
  58 class ISA;
  59 class Decoder : public InstDecoder
  60 {
  61   protected:
  62     //The extended machine instruction being generated
  63     ExtMachInst emi;
  64     MachInst data;
  65     bool bigThumb;
  66     bool instDone;
  67     bool outOfBytes;
  68     int offset;
  69     bool foundIt;
  70     ITSTATE itBits;
  71
  72     int fpscrLen;
  73     int fpscrStride;
  74
  75     /**
  76      * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN
  77      * bitfields.
  78      */
  79     int sveLen;
  80
  81     Enums::DecoderFlavor decoderFlavor;
  82
  83     /// A cache of decoded instruction objects.
  84     static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
  85
  86     /**
  87      * Pre-decode an instruction from the current state of the
  88      * decoder.
  89      */
  90     void process();
  91
  92     /**
  93      * Consume bytes by moving the offset into the data word and
  94      * sanity check the results.
  95      */
  96     void consumeBytes(int numBytes);
  97
  98   public: // Decoder API
  99     Decoder(ISA* isa = nullptr);
 100
 101     /** Reset the decoders internal state. */
 102     void reset();
 103
 104     /**
 105      * Can the decoder accept more data?
 106      *
 107      * A CPU model uses this method to determine if the decoder can
 108      * accept more data. Note that an instruction can be ready (see
 109      * instReady() even if this method returns true.
 110      */
 111     bool needMoreBytes() const { return outOfBytes; }
 112
 113     /**
 114      * Is an instruction ready to be decoded?
 115      *
 116      * CPU models call this method to determine if decode() will
 117      * return a new instruction on the next call. It typically only
 118      * returns false if the decoder hasn't received enough data to
 119      * decode a full instruction.
 120      */
 121     bool instReady() const { return instDone; }
 122
 123     /**
 124      * Feed data to the decoder.
 125      *
 126      * A CPU model uses this interface to load instruction data into
 127      * the decoder. Once enough data has been loaded (check with
 128      * instReady()), a decoded instruction can be retrieved using
 129      * decode(ArmISA::PCState).
 130      *
 131      * This method is intended to support both fixed-length and
 132      * variable-length instructions. Instruction data is fetch in
 133      * MachInst blocks (which correspond to the size of a typical
 134      * insturction). The method might need to be called multiple times
 135      * if the instruction spans multiple blocks, in that case
 136      * needMoreBytes() will return true and instReady() will return
 137      * false.
 138      *
 139      * The fetchPC parameter is used to indicate where in memory the
 140      * instruction was fetched from. This is should be the same
 141      * address as the pc. If fetching multiple blocks, it indicates
 142      * where subsequent blocks are fetched from (pc + n *
 143      * sizeof(MachInst)).
 144      *
 145      * @param pc Instruction pointer that we are decoding.
 146      * @param fetchPC The address this chunk was fetched from.
 147      * @param inst Raw instruction data.
 148      */
 149     void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
 150
 151     /**
 152      * Decode an instruction or fetch it from the code cache.
 153      *
 154      * This method decodes the currently pending pre-decoded
 155      * instruction. Data must be fed to the decoder using moreBytes()
 156      * until instReady() is true before calling this method.
 157      *
 158      * @param pc Instruction pointer that we are decoding.
 159      * @return A pointer to a static instruction or NULL if the
 160      * decoder isn't ready (see instReady()).
 161      */
 162     StaticInstPtr decode(ArmISA::PCState &pc);
 163
 164     /**
 165      * Decode a pre-decoded machine instruction.
 166      *
 167      * @warn This method takes a pre-decoded instruction as its
 168      * argument. It should typically not be called directly.
 169      *
 170      * @param mach_inst A pre-decoded instruction
 171      * @retval A pointer to the corresponding StaticInst object.
 172      */
 173     StaticInstPtr
 174     decode(ExtMachInst mach_inst, Addr addr)
 175     {
 176         StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
 177         DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
 178                 si->getName(), mach_inst);
 179         return si;
 180     }
 181
 182     /**
 183      * Decode a machine instruction without calling the cache.
 184      *
 185      * @note The implementation of this method is generated by the ISA
 186      * parser script.
 187      *
 188      * @warn This method takes a pre-decoded instruction as its
 189      * argument. It should typically not be called directly.
 190      *
 191      * @param mach_inst The binary instruction to decode.
 192      * @retval A pointer to the corresponding StaticInst object.
 193      */
 194     StaticInstPtr decodeInst(ExtMachInst mach_inst);
 195
 196     /**
 197      * Take over the state from an old decoder when switching CPUs.
 198      *
 199      * @param old Decoder used in old CPU
 200      */
 201     void takeOverFrom(Decoder *old) {}
 202
 203
 204   public: // ARM-specific decoder state manipulation
 205     void
 206     setContext(FPSCR fpscr)
 207     {
 208         fpscrLen = fpscr.len;
 209         fpscrStride = fpscr.stride;
 210     }
 211
 212     void
 213     setSveLen(uint8_t len)
 214     {
 215         sveLen = len;
 216     }
 217 };
 218
 219 } // namespace ArmISA
 220
 221 #endif // __ARCH_ARM_DECODER_HH__