arch: [Patch 1/5] Added RISC-V base instruction set RV64I
[gem5.git] / src / arch / riscv / RiscvISA.py
1 # Copyright (c) 2012 ARM Limited
2 # Copyright (c) 2014 Sven Karlsson
3 # All rights reserved.
4 #
5 # The license below extends only to copyright in the software and shall
6 # not be construed as granting a license to any other intellectual
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8 # to a hardware implementation of the functionality of the software
9 # licensed hereunder. You may use the software subject to the license
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11 # unmodified and in its entirety in all distributions of the software,
12 # modified or unmodified, in source code or in binary form.
13 #
14 # Copyright (c) 2016 RISC-V Foundation
15 # Copyright (c) 2016 The University of Virginia
16 # All rights reserved.
17 #
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
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22 # redistributions in binary form must reproduce the above copyright
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25 # neither the name of the copyright holders nor the names of its
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27 # this software without specific prior written permission.
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29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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40 #
41 # Authors: Andreas Sandberg
42 # Sven Karlsson
43 # Alec Roelke
44
45 from m5.SimObject import SimObject
46
47 class RiscvISA(SimObject):
48 type = 'RiscvISA'
49 cxx_class = 'RiscvISA::ISA'
50 cxx_header = "arch/riscv/isa.hh"