src/arch/riscv/RiscvInterrupts.py

   1 # Copyright (c) 2008 The Regents of The University of Michigan
   2 # Copyright (c) 2014 Sven Karlsson
   3 # Copyright (c) 2016 RISC-V Foundation
   4 # Copyright (c) 2016 The University of Virginia
   5 # All rights reserved.
   6 #
   7 # Redistribution and use in source and binary forms, with or without
   8 # modification, are permitted provided that the following conditions are
   9 # met: redistributions of source code must retain the above copyright
  10 # notice, this list of conditions and the following disclaimer;
  11 # redistributions in binary form must reproduce the above copyright
  12 # notice, this list of conditions and the following disclaimer in the
  13 # documentation and/or other materials provided with the distribution;
  14 # neither the name of the copyright holders nor the names of its
  15 # contributors may be used to endorse or promote products derived from
  16 # this software without specific prior written permission.
  17 #
  18 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 #
  30 # Authors: Gabe Black
  31 #          Sven Karlsson
  32 #          Alec Roelke
  33
  34 from m5.SimObject import SimObject
  35
  36 class RiscvInterrupts(SimObject):
  37     type = 'RiscvInterrupts'
  38     cxx_class = 'RiscvISA::Interrupts'
  39     cxx_header = 'arch/riscv/interrupts.hh'