arch: [Patch 1/5] Added RISC-V base instruction set RV64I
[gem5.git] / src / arch / riscv / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2013 ARM Limited
4 # Copyright (c) 2014 Sven Karlsson
5 # All rights reserved
6 #
7 # The license below extends only to copyright in the software and shall
8 # not be construed as granting a license to any other intellectual
9 # property including but not limited to intellectual property relating
10 # to a hardware implementation of the functionality of the software
11 # licensed hereunder. You may use the software subject to the license
12 # terms below provided that you ensure that this notice is replicated
13 # unmodified and in its entirety in all distributions of the software,
14 # modified or unmodified, in source code or in binary form.
15 #
16 # Copyright (c) 2016 The University of Virginia
17 # All rights reserved.
18 #
19 # Redistribution and use in source and binary forms, with or without
20 # modification, are permitted provided that the following conditions are
21 # met: redistributions of source code must retain the above copyright
22 # notice, this list of conditions and the following disclaimer;
23 # redistributions in binary form must reproduce the above copyright
24 # notice, this list of conditions and the following disclaimer in the
25 # documentation and/or other materials provided with the distribution;
26 # neither the name of the copyright holders nor the names of its
27 # contributors may be used to endorse or promote products derived from
28 # this software without specific prior written permission.
29 #
30 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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40 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #
42 # Authors: Andreas Hansson
43 # Sven Karlsson
44 # Alec Roelke
45
46 Import('*')
47
48 if env['TARGET_ISA'] == 'riscv':
49 Source('decoder.cc')
50 Source('faults.cc')
51 Source('isa.cc')
52 Source('interrupts.cc')
53 Source('process.cc')
54 Source('pagetable.cc')
55 Source('remote_gdb.cc')
56 Source('stacktrace.cc')
57 Source('tlb.cc')
58 Source('system.cc')
59
60 Source('linux/process.cc')
61 Source('linux/linux.cc')
62
63 SimObject('RiscvInterrupts.py')
64 SimObject('RiscvISA.py')
65 SimObject('RiscvTLB.py')
66 SimObject('RiscvSystem.py')
67
68 DebugFlag('RiscvMisc')
69 DebugFlag('RiscvTLB')
70
71 # Add in files generated by the ISA description.
72 env.ISADesc('isa/main.isa')