src/arch/riscv/isa/base.isa

   1 // -*- mode:c++ -*-
   2
   3 // Copyright (c) 2015 RISC-V Foundation
   4 // Copyright (c) 2016 The University of Virginia
   5 // All rights reserved.
   6 //
   7 // Redistribution and use in source and binary forms, with or without
   8 // modification, are permitted provided that the following conditions are
   9 // met: redistributions of source code must retain the above copyright
  10 // notice, this list of conditions and the following disclaimer;
  11 // redistributions in binary form must reproduce the above copyright
  12 // notice, this list of conditions and the following disclaimer in the
  13 // documentation and/or other materials provided with the distribution;
  14 // neither the name of the copyright holders nor the names of its
  15 // contributors may be used to endorse or promote products derived from
  16 // this software without specific prior written permission.
  17 //
  18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 //
  30 // Authors: Maxwell Walter
  31 //          Alec Roelke
  32
  33 ////////////////////////////////////////////////////////////////////
  34 //
  35 // Base class for Riscv instructions, and some support functions
  36 //
  37
  38 //Outputs to decoder.hh
  39 output header {{
  40     using namespace RiscvISA;
  41
  42     /**
  43      * Base class for all RISC-V static instructions.
  44      */
  45     class RiscvStaticInst : public StaticInst
  46     {
  47       protected:
  48         // Constructor
  49         RiscvStaticInst(const char *mnem, MachInst _machInst,
  50             OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
  51         {}
  52
  53         std::string
  54         regName(RegIndex reg) const;
  55
  56         virtual std::string
  57         generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
  58
  59       public:
  60         void
  61         advancePC(RiscvISA::PCState &pc) const
  62         {
  63             pc.advance();
  64         }
  65     };
  66 }};
  67
  68 //Ouputs to decoder.cc
  69 output decoder {{
  70     std::string
  71     RiscvStaticInst::regName(RegIndex reg) const
  72     {
  73         if (reg < FP_Reg_Base) {
  74             return std::string(RegisterNames[reg]);
  75         } else {
  76             return std::string("f") + std::to_string(reg - FP_Reg_Base);
  77         }
  78     }
  79 }};