3 // Copyright (c) 2015 RISC-V Foundation
4 // Copyright (c) 2016 The University of Virginia
5 // All rights reserved.
7 // Redistribution and use in source and binary forms, with or without
8 // modification, are permitted provided that the following conditions are
9 // met: redistributions of source code must retain the above copyright
10 // notice, this list of conditions and the following disclaimer;
11 // redistributions in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution;
14 // neither the name of the copyright holders nor the names of its
15 // contributors may be used to endorse or promote products derived from
16 // this software without specific prior written permission.
18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 // Authors: Alec Roelke
32 ////////////////////////////////////////////////////////////////////
34 // The RISC-V ISA decoder
37 decode OPCODE default Unknown::unknown() {
67 }}, IsNonSpeculative, IsMemBarrier, No_OpClass);
69 }}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
82 Rd = (Rs1_sd < imm) ? 1 : 0;
85 Rd = (Rs1 < (uint64_t)imm) ? 1 : 0;
88 Rd = Rs1 ^ (uint64_t)imm;
95 Rd_sd = Rs1_sd >> SHAMT6;
99 Rd = Rs1 | (uint64_t)imm;
102 Rd = Rs1 & (uint64_t)imm;
111 0x1b: decode FUNCT3 {
114 Rd_sd = (int32_t)Rs1 + (int32_t)imm;
117 Rd_sd = Rs1_sw << SHAMT5;
121 Rd = Rs1_uw >> SHAMT5;
124 Rd_sd = Rs1_sw >> SHAMT5;
130 0x23: decode FUNCT3 {
147 0x33: decode FUNCT3 {
151 Rd = Rs1_sd + Rs2_sd;
154 Rd = Rs1_sd - Rs2_sd;
159 Rd = Rs1 << Rs2<5:0>;
164 Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
169 Rd = (Rs1 < Rs2) ? 1 : 0;
179 Rd = Rs1 >> Rs2<5:0>;
182 Rd_sd = Rs1_sd >> Rs2<5:0>;
202 0x3b: decode FUNCT3 {
206 Rd_sd = Rs1_sw + Rs2_sw;
209 Rd_sd = Rs1_sw - Rs2_sw;
213 Rd_sd = Rs1_sw << Rs2<4:0>;
217 Rd_uw = Rs1_uw >> Rs2<4:0>;
220 Rd_sd = Rs1_sw >> Rs2<4:0>;
226 0x63: decode FUNCT3 {
234 }}, IsDirectControl, IsCondControl);
241 }}, IsDirectControl, IsCondControl);
243 if (Rs1_sd < Rs2_sd) {
248 }}, IsDirectControl, IsCondControl);
250 if (Rs1_sd >= Rs2_sd) {
255 }}, IsDirectControl, IsCondControl);
262 }}, IsDirectControl, IsCondControl);
269 }}, IsDirectControl, IsCondControl);
273 0x67: decode FUNCT3 {
276 NPC = (imm + Rs1) & (~0x1);
277 }}, IsIndirectControl, IsUncondControl, IsCall);
283 }}, IsDirectControl, IsUncondControl, IsCall);
285 0x73: decode FUNCT3 {
287 0x0: decode FUNCT12 {
289 fault = std::make_shared<SyscallFault>();
290 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall, No_OpClass);
292 fault = std::make_shared<BreakpointFault>();
293 }}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
295 fault = std::make_shared<UnimplementedFault>("eret");
299 Rd = xc->readMiscReg(FUNCT12);
300 xc->setMiscReg(FUNCT12, Rs1);
301 }}, IsNonSpeculative, No_OpClass);
303 Rd = xc->readMiscReg(FUNCT12);
305 xc->setMiscReg(FUNCT12, Rd | Rs1);
307 }}, IsNonSpeculative, No_OpClass);
309 Rd = xc->readMiscReg(FUNCT12);
311 xc->setMiscReg(FUNCT12, Rd & ~Rs1);
313 }}, IsNonSpeculative, No_OpClass);
315 Rd = xc->readMiscReg(FUNCT12);
316 xc->setMiscReg(FUNCT12, ZIMM);
317 }}, IsNonSpeculative, No_OpClass);
319 Rd = xc->readMiscReg(FUNCT12);
321 xc->setMiscReg(FUNCT12, Rd | ZIMM);
323 }}, IsNonSpeculative, No_OpClass);
325 Rd = xc->readMiscReg(FUNCT12);
327 xc->setMiscReg(FUNCT12, Rd & ~ZIMM);
329 }}, IsNonSpeculative, No_OpClass);