3 // Copyright (c) 2015 RISC-V Foundation
4 // Copyright (c) 2016 The University of Virginia
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18 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30 // Authors: Maxwell Walter
45 #General Purpose Integer Reg Operands
46 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
47 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
48 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
51 'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 5),
53 #Program Counter Operands
54 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
55 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),