src/arch/riscv/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * Copyright (c) 2009 The University of Edinburgh
   4  * Copyright (c) 2014 Sven Karlsson
   5  * Copyright (c) 2016 RISC-V Foundation
   6  * Copyright (c) 2016 The University of Virginia
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions are
  11  * met: redistributions of source code must retain the above copyright
  12  * notice, this list of conditions and the following disclaimer;
  13  * redistributions in binary form must reproduce the above copyright
  14  * notice, this list of conditions and the following disclaimer in the
  15  * documentation and/or other materials provided with the distribution;
  16  * neither the name of the copyright holders nor the names of its
  17  * contributors may be used to endorse or promote products derived from
  18  * this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * Authors: Gabe Black
  33  *          Timothy M. Jones
  34  *          Sven Karlsson
  35  *          Alec Roelke
  36  */
  37
  38 #ifndef __ARCH_RISCV_ISA_HH__
  39 #define __ARCH_RISCV_ISA_HH__
  40
  41 #include <map>
  42 #include <string>
  43
  44 #include "arch/riscv/registers.hh"
  45 #include "arch/riscv/types.hh"
  46 #include "base/misc.hh"
  47 #include "sim/sim_object.hh"
  48
  49 struct RiscvISAParams;
  50 class ThreadContext;
  51 class Checkpoint;
  52 class EventManager;
  53
  54 namespace RiscvISA
  55 {
  56
  57 class ISA : public SimObject
  58 {
  59   protected:
  60     std::vector<MiscReg> miscRegFile;
  61
  62   public:
  63     typedef RiscvISAParams Params;
  64     static std::map<int, std::string> miscRegNames;
  65
  66     void
  67     clear();
  68
  69     MiscReg
  70     readMiscRegNoEffect(int misc_reg) const;
  71
  72     MiscReg
  73     readMiscReg(int misc_reg, ThreadContext *tc);
  74
  75     void
  76     setMiscRegNoEffect(int misc_reg, const MiscReg &val);
  77
  78     void
  79     setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
  80
  81     int
  82     flattenIntIndex(int reg) const
  83     {
  84         return reg;
  85     }
  86
  87     int
  88     flattenFloatIndex(int reg) const
  89     {
  90         return reg;
  91     }
  92
  93     // dummy
  94     int
  95     flattenCCIndex(int reg) const
  96     {
  97         return reg;
  98     }
  99
 100     int
 101     flattenMiscIndex(int reg) const
 102     {
 103         return reg;
 104     }
 105
 106     void startup(ThreadContext *tc) {}
 107
 108     /// Explicitly import the otherwise hidden startup
 109     using SimObject::startup;
 110
 111     const Params *
 112     params() const;
 113
 114     ISA(Params *p);
 115 };
 116
 117 } // namespace RiscvISA
 118
 119 #endif // __ARCH_RISCV_ISA_HH__