src/arch/riscv/utility.hh

   1 /*
   2  * Copyright (c) 2013 ARM Limited
   3  * Copyright (c) 2014-2015 Sven Karlsson
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2016 The University of Virginia
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Andreas Hansson
  42  *          Sven Karlsson
  43  *          Alec Roelke
  44  */
  45
  46 #ifndef __ARCH_RISCV_UTILITY_HH__
  47 #define __ARCH_RISCV_UTILITY_HH__
  48
  49 #include <cmath>
  50 #include <cstdint>
  51
  52 #include "base/types.hh"
  53 #include "cpu/static_inst.hh"
  54 #include "cpu/thread_context.hh"
  55
  56 namespace RiscvISA
  57 {
  58
  59 inline PCState
  60 buildRetPC(const PCState &curPC, const PCState &callPC)
  61 {
  62     PCState retPC = callPC;
  63     retPC.advance();
  64     retPC.pc(curPC.npc());
  65     return retPC;
  66 }
  67
  68 inline uint64_t
  69 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
  70 {
  71     return 0;
  72 }
  73
  74 inline void startupCPU(ThreadContext *tc, int cpuId)
  75 {
  76 }
  77
  78 inline void
  79 copyRegs(ThreadContext *src, ThreadContext *dest)
  80 {
  81     // First loop through the integer registers.
  82     for (int i = 0; i < NumIntRegs; ++i)
  83         dest->setIntReg(i, src->readIntReg(i));
  84
  85     // Lastly copy PC/NPC
  86     dest->pcState(src->pcState());
  87 }
  88
  89 inline void
  90 skipFunction(ThreadContext *tc)
  91 {
  92     panic("Not Implemented for Riscv");
  93 }
  94
  95 inline void
  96 advancePC(PCState &pc, const StaticInstPtr &inst)
  97 {
  98     inst->advancePC(pc);
  99 }
 100
 101 static inline bool
 102 inUserMode(ThreadContext *tc)
 103 {
 104     return true;
 105 }
 106
 107 inline uint64_t
 108 getExecutingAsid(ThreadContext *tc)
 109 {
 110     return 0;
 111 }
 112
 113 inline void
 114 initCPU(ThreadContext *, int cpuId)
 115 {
 116     panic("initCPU not implemented for Riscv.\n");
 117 }
 118
 119 } // namespace RiscvISA
 120
 121 #endif // __ARCH_RISCV_UTILITY_HH__