2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "arch/sparc/tlb.hh"
35 #include "arch/sparc/asi.hh"
36 #include "arch/sparc/faults.hh"
37 #include "arch/sparc/registers.hh"
38 #include "base/bitfield.hh"
39 #include "base/compiler.hh"
40 #include "base/trace.hh"
41 #include "cpu/base.hh"
42 #include "cpu/thread_context.hh"
43 #include "debug/IPR.hh"
44 #include "debug/TLB.hh"
45 #include "mem/packet_access.hh"
46 #include "mem/request.hh"
47 #include "sim/full_system.hh"
48 #include "sim/system.hh"
50 /* @todo remove some of the magic constants. -- ali
54 TLB::TLB(const Params
*p
)
55 : BaseTLB(p
), size(p
->size
), usedEntries(0), lastReplaced(0),
56 cacheState(0), cacheValid(false)
58 // To make this work you'll have to change the hypervisor and OS
60 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
62 tlb
= new TlbEntry
[size
];
63 std::memset(tlb
, 0, sizeof(TlbEntry
) * size
);
65 for (int x
= 0; x
< size
; x
++)
66 freeList
.push_back(&tlb
[x
]);
85 for (i
= lookupTable
.begin(); i
!= lookupTable
.end(); i
++) {
86 TlbEntry
*t
= i
->second
;
87 if (!t
->pte
.locked()) {
96 TLB::insert(Addr va
, int partition_id
, int context_id
, bool real
,
97 const PageTableEntry
& PTE
, int entry
)
100 TlbEntry
*new_entry
= NULL
;
105 va
&= ~(PTE
.size()-1);
107 tr.size = PTE.size() - 1;
108 tr.contextId = context_id;
109 tr.partitionId = partition_id;
114 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
115 va
, PTE
.paddr(), partition_id
, context_id
, (int)real
, entry
);
117 // Demap any entry that conflicts
118 for (x
= 0; x
< size
; x
++) {
119 if (tlb
[x
].range
.real
== real
&&
120 tlb
[x
].range
.partitionId
== partition_id
&&
121 tlb
[x
].range
.va
< va
+ PTE
.size() - 1 &&
122 tlb
[x
].range
.va
+ tlb
[x
].range
.size
>= va
&&
123 (real
|| tlb
[x
].range
.contextId
== context_id
))
126 freeList
.push_front(&tlb
[x
]);
127 DPRINTF(TLB
, "TLB: Conflicting entry %#X , deleting it\n", x
);
129 tlb
[x
].valid
= false;
134 lookupTable
.erase(tlb
[x
].range
);
140 assert(entry
< size
&& entry
>= 0);
141 new_entry
= &tlb
[entry
];
143 if (!freeList
.empty()) {
144 new_entry
= freeList
.front();
151 if (x
== lastReplaced
)
152 goto insertAllLocked
;
153 } while (tlb
[x
].pte
.locked());
160 // Update the last ently if their all locked
162 new_entry
= &tlb
[size
-1];
165 freeList
.remove(new_entry
);
166 if (new_entry
->valid
&& new_entry
->used
)
168 if (new_entry
->valid
)
169 lookupTable
.erase(new_entry
->range
);
173 new_entry
->range
.va
= va
;
174 new_entry
->range
.size
= PTE
.size() - 1;
175 new_entry
->range
.partitionId
= partition_id
;
176 new_entry
->range
.contextId
= context_id
;
177 new_entry
->range
.real
= real
;
178 new_entry
->pte
= PTE
;
179 new_entry
->used
= true;;
180 new_entry
->valid
= true;
183 i
= lookupTable
.insert(new_entry
->range
, new_entry
);
184 assert(i
!= lookupTable
.end());
186 // If all entries have their used bit set, clear it on them all,
187 // but the one we just inserted
188 if (usedEntries
== size
) {
190 new_entry
->used
= true;
197 TLB::lookup(Addr va
, int partition_id
, bool real
, int context_id
,
204 DPRINTF(TLB
, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
205 va
, partition_id
, context_id
, real
);
206 // Assemble full address structure
209 tr
.contextId
= context_id
;
210 tr
.partitionId
= partition_id
;
213 // Try to find the entry
214 i
= lookupTable
.find(tr
);
215 if (i
== lookupTable
.end()) {
216 DPRINTF(TLB
, "TLB: No valid entry found\n");
220 // Mark the entries used bit and clear other used bits in needed
222 DPRINTF(TLB
, "TLB: Valid entry found pa: %#x size: %#x\n", t
->pte
.paddr(),
225 // Update the used bits only if this is a real access (not a fake
226 // one from virttophys()
227 if (!t
->used
&& update_used
) {
230 if (usedEntries
== size
) {
244 for (int x
= 0; x
< size
; x
++) {
246 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
247 x
, tlb
[x
].range
.partitionId
, tlb
[x
].range
.contextId
,
248 tlb
[x
].range
.real
? 'R' : ' ', tlb
[x
].range
.size
,
249 tlb
[x
].range
.va
, tlb
[x
].pte
.paddr(), tlb
[x
].pte());
255 TLB::demapPage(Addr va
, int partition_id
, bool real
, int context_id
)
260 DPRINTF(IPR
, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
261 va
, partition_id
, context_id
, real
);
265 // Assemble full address structure
268 tr
.contextId
= context_id
;
269 tr
.partitionId
= partition_id
;
272 // Demap any entry that conflicts
273 i
= lookupTable
.find(tr
);
274 if (i
!= lookupTable
.end()) {
275 DPRINTF(IPR
, "TLB: Demapped page\n");
276 i
->second
->valid
= false;
277 if (i
->second
->used
) {
278 i
->second
->used
= false;
281 freeList
.push_front(i
->second
);
282 lookupTable
.erase(i
);
287 TLB::demapContext(int partition_id
, int context_id
)
289 DPRINTF(IPR
, "TLB: Demapping Context pid=%#d cid=%d\n",
290 partition_id
, context_id
);
292 for (int x
= 0; x
< size
; x
++) {
293 if (tlb
[x
].range
.contextId
== context_id
&&
294 tlb
[x
].range
.partitionId
== partition_id
) {
296 freeList
.push_front(&tlb
[x
]);
298 tlb
[x
].valid
= false;
303 lookupTable
.erase(tlb
[x
].range
);
309 TLB::demapAll(int partition_id
)
311 DPRINTF(TLB
, "TLB: Demapping All pid=%#d\n", partition_id
);
313 for (int x
= 0; x
< size
; x
++) {
314 if (tlb
[x
].valid
&& !tlb
[x
].pte
.locked() &&
315 tlb
[x
].range
.partitionId
== partition_id
) {
316 freeList
.push_front(&tlb
[x
]);
317 tlb
[x
].valid
= false;
322 lookupTable
.erase(tlb
[x
].range
);
333 for (int x
= 0; x
< size
; x
++) {
335 freeList
.push_back(&tlb
[x
]);
336 tlb
[x
].valid
= false;
343 TLB::TteRead(int entry
)
346 panic("entry: %d\n", entry
);
348 assert(entry
< size
);
349 if (tlb
[entry
].valid
)
350 return tlb
[entry
].pte();
352 return (uint64_t)-1ll;
356 TLB::TagRead(int entry
)
358 assert(entry
< size
);
360 if (!tlb
[entry
].valid
)
361 return (uint64_t)-1ll;
363 tag
= tlb
[entry
].range
.contextId
;
364 tag
|= tlb
[entry
].range
.va
;
365 tag
|= (uint64_t)tlb
[entry
].range
.partitionId
<< 61;
366 tag
|= tlb
[entry
].range
.real
? ULL(1) << 60 : 0;
367 tag
|= (uint64_t)~tlb
[entry
].pte
._size() << 56;
372 TLB::validVirtualAddress(Addr va
, bool am
)
376 if (va
>= StartVAddrHole
&& va
<= EndVAddrHole
)
382 TLB::writeSfsr(bool write
, ContextType ct
, bool se
, FaultTypes ft
, int asi
)
399 TLB::writeTagAccess(Addr va
, int context
)
401 DPRINTF(TLB
, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
402 va
, context
, mbits(va
, 63,13) | mbits(context
,12,0));
404 tag_access
= mbits(va
, 63,13) | mbits(context
,12,0);
408 TLB::writeSfsr(Addr a
, bool write
, ContextType ct
,
409 bool se
, FaultTypes ft
, int asi
)
411 DPRINTF(TLB
, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a
, (int)write
, ct
, ft
, asi
);
413 TLB::writeSfsr(write
, ct
, se
, ft
, asi
);
418 TLB::translateInst(const RequestPtr
&req
, ThreadContext
*tc
)
420 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
422 Addr vaddr
= req
->getVaddr();
425 assert(req
->getArchFlags() == ASI_IMPLICIT
);
427 DPRINTF(TLB
, "TLB: ITB Request to translate va=%#x size=%d\n",
428 vaddr
, req
->getSize());
430 // Be fast if we can!
431 if (cacheValid
&& cacheState
== tlbdata
) {
433 if (cacheEntry
[0]->range
.va
< vaddr
+ sizeof(MachInst
) &&
434 cacheEntry
[0]->range
.va
+ cacheEntry
[0]->range
.size
>= vaddr
) {
435 req
->setPaddr(cacheEntry
[0]->pte
.translate(vaddr
));
439 req
->setPaddr(vaddr
& PAddrImplMask
);
444 bool hpriv
= bits(tlbdata
,0,0);
445 bool red
= bits(tlbdata
,1,1);
446 bool priv
= bits(tlbdata
,2,2);
447 bool addr_mask
= bits(tlbdata
,3,3);
448 bool lsu_im
= bits(tlbdata
,4,4);
450 int part_id
= bits(tlbdata
,15,8);
451 int tl
= bits(tlbdata
,18,16);
452 int pri_context
= bits(tlbdata
,47,32);
458 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
459 priv
, hpriv
, red
, lsu_im
, part_id
);
468 context
= pri_context
;
471 if ( hpriv
|| red
) {
473 cacheState
= tlbdata
;
474 cacheEntry
[0] = NULL
;
475 req
->setPaddr(vaddr
& PAddrImplMask
);
479 // If the access is unaligned trap
481 writeSfsr(false, ct
, false, OtherFault
, asi
);
482 return std::make_shared
<MemAddressNotAligned
>();
486 vaddr
= vaddr
& VAddrAMask
;
488 if (!validVirtualAddress(vaddr
, addr_mask
)) {
489 writeSfsr(false, ct
, false, VaOutOfRange
, asi
);
490 return std::make_shared
<InstructionAccessException
>();
494 e
= lookup(vaddr
, part_id
, true);
498 e
= lookup(vaddr
, part_id
, false, context
);
501 if (e
== NULL
|| !e
->valid
) {
502 writeTagAccess(vaddr
, context
);
504 return std::make_shared
<InstructionRealTranslationMiss
>();
507 return std::make_shared
<FastInstructionAccessMMUMiss
>();
509 return std::make_shared
<FastInstructionAccessMMUMiss
>(
514 // were not priviledged accesing priv page
515 if (!priv
&& e
->pte
.priv()) {
516 writeTagAccess(vaddr
, context
);
517 writeSfsr(false, ct
, false, PrivViolation
, asi
);
518 return std::make_shared
<InstructionAccessException
>();
521 // cache translation date for next translation
523 cacheState
= tlbdata
;
526 req
->setPaddr(e
->pte
.translate(vaddr
));
527 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
532 TLB::translateData(const RequestPtr
&req
, ThreadContext
*tc
, bool write
)
535 * @todo this could really use some profiling and fixing to make
538 uint64_t tlbdata
= tc
->readMiscRegNoEffect(MISCREG_TLB_DATA
);
539 Addr vaddr
= req
->getVaddr();
540 Addr size
= req
->getSize();
542 asi
= (ASI
)req
->getArchFlags();
543 bool implicit
= false;
544 bool hpriv
= bits(tlbdata
,0,0);
545 bool unaligned
= vaddr
& (size
- 1);
547 DPRINTF(TLB
, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
550 if (lookupTable
.size() != 64 - freeList
.size())
551 panic("Lookup table size: %d tlb size: %d\n", lookupTable
.size(),
553 if (asi
== ASI_IMPLICIT
)
556 // Only use the fast path here if there doesn't need to be an unaligned
559 if (hpriv
&& implicit
) {
560 req
->setPaddr(vaddr
& PAddrImplMask
);
564 // Be fast if we can!
565 if (cacheValid
&& cacheState
== tlbdata
) {
570 TlbEntry
*ce
= cacheEntry
[0];
571 Addr ce_va
= ce
->range
.va
;
572 if (cacheAsi
[0] == asi
&&
573 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
574 (!write
|| ce
->pte
.writable())) {
575 req
->setPaddr(ce
->pte
.translate(vaddr
));
576 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1) {
578 Request::UNCACHEABLE
| Request::STRICT_ORDER
);
580 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
583 } // if cache entry valid
585 TlbEntry
*ce
= cacheEntry
[1];
586 Addr ce_va
= ce
->range
.va
;
587 if (cacheAsi
[1] == asi
&&
588 ce_va
< vaddr
+ size
&& ce_va
+ ce
->range
.size
> vaddr
&&
589 (!write
|| ce
->pte
.writable())) {
590 req
->setPaddr(ce
->pte
.translate(vaddr
));
591 if (ce
->pte
.sideffect() || (ce
->pte
.paddr() >> 39) & 1) {
593 Request::UNCACHEABLE
| Request::STRICT_ORDER
);
595 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
598 } // if cache entry valid
602 bool red
= bits(tlbdata
,1,1);
603 bool priv
= bits(tlbdata
,2,2);
604 bool addr_mask
= bits(tlbdata
,3,3);
605 bool lsu_dm
= bits(tlbdata
,5,5);
607 int part_id
= bits(tlbdata
,15,8);
608 int tl
= bits(tlbdata
,18,16);
609 int pri_context
= bits(tlbdata
,47,32);
610 int sec_context
= bits(tlbdata
,63,48);
613 ContextType ct
= Primary
;
618 DPRINTF(TLB
, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
619 priv
, hpriv
, red
, lsu_dm
, part_id
);
629 context
= pri_context
;
632 // We need to check for priv level/asi priv
633 if (!priv
&& !hpriv
&& !asiIsUnPriv(asi
)) {
634 // It appears that context should be Nucleus in these cases?
635 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
636 return std::make_shared
<PrivilegedAction
>();
639 if (!hpriv
&& asiIsHPriv(asi
)) {
640 writeSfsr(vaddr
, write
, Nucleus
, false, IllegalAsi
, asi
);
641 return std::make_shared
<DataAccessException
>();
644 if (asiIsPrimary(asi
)) {
645 context
= pri_context
;
647 } else if (asiIsSecondary(asi
)) {
648 context
= sec_context
;
650 } else if (asiIsNucleus(asi
)) {
655 context
= pri_context
;
659 if (!implicit
&& asi
!= ASI_P
&& asi
!= ASI_S
) {
660 if (asiIsLittle(asi
))
661 panic("Little Endian ASIs not supported\n");
663 //XXX It's unclear from looking at the documentation how a no fault
664 // load differs from a regular one, other than what happens concerning
665 // nfo and e bits in the TTE
666 // if (asiIsNoFault(asi))
667 // panic("No Fault ASIs not supported\n");
669 if (asiIsPartialStore(asi
))
670 panic("Partial Store ASIs not supported\n");
673 panic("Cmt ASI registers not implmented\n");
675 if (asiIsInterrupt(asi
))
676 goto handleIntRegAccess
;
678 goto handleMmuRegAccess
;
679 if (asiIsScratchPad(asi
))
680 goto handleScratchRegAccess
;
682 goto handleQueueRegAccess
;
683 if (asiIsSparcError(asi
))
684 goto handleSparcErrorRegAccess
;
686 if (!asiIsReal(asi
) && !asiIsNucleus(asi
) && !asiIsAsIfUser(asi
) &&
687 !asiIsTwin(asi
) && !asiIsBlock(asi
) && !asiIsNoFault(asi
))
688 panic("Accessing ASI %#X. Should we?\n", asi
);
691 // If the asi is unaligned trap
693 writeSfsr(vaddr
, false, ct
, false, OtherFault
, asi
);
694 return std::make_shared
<MemAddressNotAligned
>();
698 vaddr
= vaddr
& VAddrAMask
;
700 if (!validVirtualAddress(vaddr
, addr_mask
)) {
701 writeSfsr(vaddr
, false, ct
, true, VaOutOfRange
, asi
);
702 return std::make_shared
<DataAccessException
>();
705 if ((!lsu_dm
&& !hpriv
&& !red
) || asiIsReal(asi
)) {
710 if (hpriv
&& (implicit
|| (!asiIsAsIfUser(asi
) && !asiIsReal(asi
)))) {
711 req
->setPaddr(vaddr
& PAddrImplMask
);
715 e
= lookup(vaddr
, part_id
, real
, context
);
717 if (e
== NULL
|| !e
->valid
) {
718 writeTagAccess(vaddr
, context
);
719 DPRINTF(TLB
, "TLB: DTB Failed to find matching TLB entry\n");
721 return std::make_shared
<DataRealTranslationMiss
>();
724 return std::make_shared
<FastDataAccessMMUMiss
>();
726 return std::make_shared
<FastDataAccessMMUMiss
>(
732 if (!priv
&& e
->pte
.priv()) {
733 writeTagAccess(vaddr
, context
);
734 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), PrivViolation
, asi
);
735 return std::make_shared
<DataAccessException
>();
738 if (write
&& !e
->pte
.writable()) {
739 writeTagAccess(vaddr
, context
);
740 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), OtherFault
, asi
);
741 return std::make_shared
<FastDataAccessProtection
>();
744 if (e
->pte
.nofault() && !asiIsNoFault(asi
)) {
745 writeTagAccess(vaddr
, context
);
746 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), LoadFromNfo
, asi
);
747 return std::make_shared
<DataAccessException
>();
750 if (e
->pte
.sideffect() && asiIsNoFault(asi
)) {
751 writeTagAccess(vaddr
, context
);
752 writeSfsr(vaddr
, write
, ct
, e
->pte
.sideffect(), SideEffect
, asi
);
753 return std::make_shared
<DataAccessException
>();
756 if (e
->pte
.sideffect() || (e
->pte
.paddr() >> 39) & 1)
757 req
->setFlags(Request::UNCACHEABLE
| Request::STRICT_ORDER
);
759 // cache translation date for next translation
760 cacheState
= tlbdata
;
762 cacheEntry
[1] = NULL
;
763 cacheEntry
[0] = NULL
;
766 if (cacheEntry
[0] != e
&& cacheEntry
[1] != e
) {
767 cacheEntry
[1] = cacheEntry
[0];
769 cacheAsi
[1] = cacheAsi
[0];
772 cacheAsi
[0] = (ASI
)0;
775 req
->setPaddr(e
->pte
.translate(vaddr
));
776 DPRINTF(TLB
, "TLB: %#X -> %#X\n", vaddr
, req
->getPaddr());
779 /** Normal flow ends here. */
782 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
784 return std::make_shared
<DataAccessException
>();
786 return std::make_shared
<PrivilegedAction
>();
789 if ((asi
== ASI_SWVR_UDB_INTR_W
&& !write
) ||
790 (asi
== ASI_SWVR_UDB_INTR_R
&& write
)) {
791 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
792 return std::make_shared
<DataAccessException
>();
798 handleScratchRegAccess
:
799 if (vaddr
> 0x38 || (vaddr
>= 0x20 && vaddr
< 0x30 && !hpriv
)) {
800 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
801 return std::make_shared
<DataAccessException
>();
805 handleQueueRegAccess
:
806 if (!priv
&& !hpriv
) {
807 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
808 return std::make_shared
<PrivilegedAction
>();
810 if ((!hpriv
&& vaddr
& 0xF) || vaddr
> 0x3f8 || vaddr
< 0x3c0) {
811 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
812 return std::make_shared
<DataAccessException
>();
816 handleSparcErrorRegAccess
:
818 writeSfsr(vaddr
, write
, Primary
, true, IllegalAsi
, asi
);
820 return std::make_shared
<DataAccessException
>();
822 return std::make_shared
<PrivilegedAction
>();
829 DPRINTF(TLB
, "TLB: DTB Translating MM IPR access\n");
830 req
->setFlags(Request::MMAPPED_IPR
);
831 req
->setPaddr(req
->getVaddr());
836 TLB::translateAtomic(const RequestPtr
&req
, ThreadContext
*tc
, Mode mode
)
839 return translateInst(req
, tc
);
841 return translateData(req
, tc
, mode
== Write
);
845 TLB::translateTiming(const RequestPtr
&req
, ThreadContext
*tc
,
846 Translation
*translation
, Mode mode
)
849 translation
->finish(translateAtomic(req
, tc
, mode
), req
, tc
, mode
);
853 TLB::finalizePhysical(const RequestPtr
&req
,
854 ThreadContext
*tc
, Mode mode
) const
860 TLB::doMmuRegRead(ThreadContext
*tc
, Packet
*pkt
)
862 Addr va
= pkt
->getAddr();
863 ASI asi
= (ASI
)pkt
->req
->getArchFlags();
866 DPRINTF(IPR
, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867 (uint32_t)pkt
->req
->getArchFlags(), pkt
->getAddr());
869 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
872 case ASI_LSU_CONTROL_REG
:
874 pkt
->set(tc
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
879 pkt
->set(tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
882 pkt
->set(tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
889 pkt
->set(tc
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
894 pkt
->set(c0_tsb_ps0
);
896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
898 pkt
->set(c0_tsb_ps1
);
900 case ASI_DMMU_CTXT_ZERO_CONFIG
:
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
906 pkt
->set(itb
->c0_tsb_ps0
);
908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
910 pkt
->set(itb
->c0_tsb_ps1
);
912 case ASI_IMMU_CTXT_ZERO_CONFIG
:
914 pkt
->set(itb
->c0_config
);
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
918 pkt
->set(cx_tsb_ps0
);
920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
922 pkt
->set(cx_tsb_ps1
);
924 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
930 pkt
->set(itb
->cx_tsb_ps0
);
932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
934 pkt
->set(itb
->cx_tsb_ps1
);
936 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
938 pkt
->set(itb
->cx_config
);
940 case ASI_SPARC_ERROR_STATUS_REG
:
941 pkt
->set((uint64_t)0);
943 case ASI_HYP_SCRATCHPAD
:
945 pkt
->set(tc
->readMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3)));
950 temp
= itb
->tag_access
;
951 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
957 pkt
->set(itb
->tag_access
);
967 pkt
->set(bits(temp
,63,22) | bits(temp
,12,0) << 48);
976 pkt
->set(tag_access
);
979 pkt
->set(tc
->readMiscReg(MISCREG_MMU_PART_ID
));
985 case ASI_DMMU_TSB_PS0_PTR_REG
:
986 pkt
->set(MakeTsbPtr(Ps0
,
993 case ASI_DMMU_TSB_PS1_PTR_REG
:
994 pkt
->set(MakeTsbPtr(Ps1
,
1001 case ASI_IMMU_TSB_PS0_PTR_REG
:
1002 pkt
->set(MakeTsbPtr(Ps0
,
1009 case ASI_IMMU_TSB_PS1_PTR_REG
:
1010 pkt
->set(MakeTsbPtr(Ps1
,
1017 case ASI_SWVR_INTR_RECEIVE
:
1019 SparcISA::Interrupts
* interrupts
=
1020 dynamic_cast<SparcISA::Interrupts
*>(
1021 tc
->getCpuPtr()->getInterruptController(0));
1022 pkt
->set(interrupts
->get_vec(IT_INT_VEC
));
1025 case ASI_SWVR_UDB_INTR_R
:
1027 SparcISA::Interrupts
* interrupts
=
1028 dynamic_cast<SparcISA::Interrupts
*>(
1029 tc
->getCpuPtr()->getInterruptController(0));
1030 temp
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
));
1031 tc
->getCpuPtr()->clearInterrupt(0, IT_INT_VEC
, temp
);
1037 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1040 pkt
->makeAtomicResponse();
1045 TLB::doMmuRegWrite(ThreadContext
*tc
, Packet
*pkt
)
1047 uint64_t data
= pkt
->get
<uint64_t>();
1048 Addr va
= pkt
->getAddr();
1049 ASI asi
= (ASI
)pkt
->req
->getArchFlags();
1055 int entry_insert
= -1;
1062 DPRINTF(IPR
, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1063 (uint32_t)asi
, va
, data
);
1065 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
1068 case ASI_LSU_CONTROL_REG
:
1070 tc
->setMiscReg(MISCREG_MMU_LSU_CTRL
, data
);
1075 tc
->setMiscReg(MISCREG_MMU_P_CONTEXT
, data
);
1078 tc
->setMiscReg(MISCREG_MMU_S_CONTEXT
, data
);
1081 goto doMmuWriteError
;
1085 assert(mbits(data
,13,6) == data
);
1086 tc
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
+
1087 (va
>> 4) - 0x3c, data
);
1089 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0
:
1093 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1
:
1097 case ASI_DMMU_CTXT_ZERO_CONFIG
:
1101 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0
:
1103 itb
->c0_tsb_ps0
= data
;
1105 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1
:
1107 itb
->c0_tsb_ps1
= data
;
1109 case ASI_IMMU_CTXT_ZERO_CONFIG
:
1111 itb
->c0_config
= data
;
1113 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1117 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1121 case ASI_DMMU_CTXT_NONZERO_CONFIG
:
1125 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0
:
1127 itb
->cx_tsb_ps0
= data
;
1129 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1
:
1131 itb
->cx_tsb_ps1
= data
;
1133 case ASI_IMMU_CTXT_NONZERO_CONFIG
:
1135 itb
->cx_config
= data
;
1137 case ASI_SPARC_ERROR_EN_REG
:
1138 case ASI_SPARC_ERROR_STATUS_REG
:
1139 inform("Ignoring write to SPARC ERROR regsiter\n");
1141 case ASI_HYP_SCRATCHPAD
:
1142 case ASI_SCRATCHPAD
:
1143 tc
->setMiscReg(MISCREG_SCRATCHPAD_R0
+ (va
>> 3), data
);
1151 sext
<59>(bits(data
, 59,0));
1152 itb
->tag_access
= data
;
1155 goto doMmuWriteError
;
1158 case ASI_ITLB_DATA_ACCESS_REG
:
1159 entry_insert
= bits(va
, 8,3);
1161 case ASI_ITLB_DATA_IN_REG
:
1162 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1163 ta_insert
= itb
->tag_access
;
1164 va_insert
= mbits(ta_insert
, 63,13);
1165 ct_insert
= mbits(ta_insert
, 12,0);
1166 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1167 real_insert
= bits(va
, 9,9);
1168 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1169 PageTableEntry::sun4u
);
1170 itb
->insert(va_insert
, part_insert
, ct_insert
, real_insert
,
1173 case ASI_DTLB_DATA_ACCESS_REG
:
1174 entry_insert
= bits(va
, 8,3);
1176 case ASI_DTLB_DATA_IN_REG
:
1177 assert(entry_insert
!= -1 || mbits(va
,10,9) == va
);
1178 ta_insert
= tag_access
;
1179 va_insert
= mbits(ta_insert
, 63,13);
1180 ct_insert
= mbits(ta_insert
, 12,0);
1181 part_insert
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1182 real_insert
= bits(va
, 9,9);
1183 pte
.populate(data
, bits(va
,10,10) ? PageTableEntry::sun4v
:
1184 PageTableEntry::sun4u
);
1185 insert(va_insert
, part_insert
, ct_insert
, real_insert
, pte
,
1188 case ASI_IMMU_DEMAP
:
1191 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1192 switch (bits(va
,5,4)) {
1194 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1206 switch (bits(va
,7,6)) {
1207 case 0: // demap page
1209 itb
->demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1211 case 1: // demap context
1213 itb
->demapContext(part_id
, ctx_id
);
1216 itb
->demapAll(part_id
);
1219 panic("Invalid type for IMMU demap\n");
1228 sext
<59>(bits(data
, 59,0));
1232 tc
->setMiscReg(MISCREG_MMU_PART_ID
, data
);
1235 goto doMmuWriteError
;
1238 case ASI_DMMU_DEMAP
:
1241 part_id
= tc
->readMiscReg(MISCREG_MMU_PART_ID
);
1242 switch (bits(va
,5,4)) {
1244 ctx_id
= tc
->readMiscReg(MISCREG_MMU_P_CONTEXT
);
1247 ctx_id
= tc
->readMiscReg(MISCREG_MMU_S_CONTEXT
);
1256 switch (bits(va
,7,6)) {
1257 case 0: // demap page
1259 demapPage(mbits(va
,63,13), part_id
, bits(va
,9,9), ctx_id
);
1261 case 1: // demap context
1263 demapContext(part_id
, ctx_id
);
1269 panic("Invalid type for IMMU demap\n");
1272 case ASI_SWVR_INTR_RECEIVE
:
1275 // clear all the interrupts that aren't set in the write
1276 SparcISA::Interrupts
* interrupts
=
1277 dynamic_cast<SparcISA::Interrupts
*>(
1278 tc
->getCpuPtr()->getInterruptController(0));
1279 while (interrupts
->get_vec(IT_INT_VEC
) & data
) {
1280 msb
= findMsbSet(interrupts
->get_vec(IT_INT_VEC
) & data
);
1281 tc
->getCpuPtr()->clearInterrupt(0, IT_INT_VEC
, msb
);
1285 case ASI_SWVR_UDB_INTR_W
:
1286 tc
->getSystemPtr()->threadContexts
[bits(data
,12,8)]->getCpuPtr()->
1287 postInterrupt(0, bits(data
, 5, 0), 0);
1291 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1292 (uint32_t)pkt
->req
->getArchFlags(), pkt
->getAddr(), data
);
1294 pkt
->makeAtomicResponse();
1299 TLB::GetTsbPtr(ThreadContext
*tc
, Addr addr
, int ctx
, Addr
*ptrs
)
1301 uint64_t tag_access
= mbits(addr
,63,13) | mbits(ctx
,12,0);
1302 TLB
*itb
= dynamic_cast<TLB
*>(tc
->getITBPtr());
1303 ptrs
[0] = MakeTsbPtr(Ps0
, tag_access
,
1308 ptrs
[1] = MakeTsbPtr(Ps1
, tag_access
,
1313 ptrs
[2] = MakeTsbPtr(Ps0
, tag_access
,
1318 ptrs
[3] = MakeTsbPtr(Ps1
, tag_access
,
1326 TLB::MakeTsbPtr(TsbPageSize ps
, uint64_t tag_access
, uint64_t c0_tsb
,
1327 uint64_t c0_config
, uint64_t cX_tsb
, uint64_t cX_config
)
1332 if (bits(tag_access
, 12,0) == 0) {
1340 uint64_t ptr
= mbits(tsb
,63,13);
1341 bool split
= bits(tsb
,12,12);
1342 int tsb_size
= bits(tsb
,3,0);
1343 int page_size
= (ps
== Ps0
) ? bits(config
, 2,0) : bits(config
,10,8);
1345 if (ps
== Ps1
&& split
)
1346 ptr
|= ULL(1) << (13 + tsb_size
);
1347 ptr
|= (tag_access
>> (9 + page_size
* 3)) & mask(12+tsb_size
, 4);
1353 TLB::serialize(CheckpointOut
&cp
) const
1355 SERIALIZE_SCALAR(size
);
1356 SERIALIZE_SCALAR(usedEntries
);
1357 SERIALIZE_SCALAR(lastReplaced
);
1359 // convert the pointer based free list into an index based one
1360 std::vector
<int> free_list
;
1361 for (const TlbEntry
*entry
: freeList
)
1362 free_list
.push_back(entry
- tlb
);
1364 SERIALIZE_CONTAINER(free_list
);
1366 SERIALIZE_SCALAR(c0_tsb_ps0
);
1367 SERIALIZE_SCALAR(c0_tsb_ps1
);
1368 SERIALIZE_SCALAR(c0_config
);
1369 SERIALIZE_SCALAR(cx_tsb_ps0
);
1370 SERIALIZE_SCALAR(cx_tsb_ps1
);
1371 SERIALIZE_SCALAR(cx_config
);
1372 SERIALIZE_SCALAR(sfsr
);
1373 SERIALIZE_SCALAR(tag_access
);
1374 SERIALIZE_SCALAR(sfar
);
1376 for (int x
= 0; x
< size
; x
++) {
1377 ScopedCheckpointSection
sec(cp
, csprintf("PTE%d", x
));
1378 tlb
[x
].serialize(cp
);
1383 TLB::unserialize(CheckpointIn
&cp
)
1387 paramIn(cp
, "size", oldSize
);
1388 if (oldSize
!= size
)
1389 panic("Don't support unserializing different sized TLBs\n");
1390 UNSERIALIZE_SCALAR(usedEntries
);
1391 UNSERIALIZE_SCALAR(lastReplaced
);
1393 std::vector
<int> free_list
;
1394 UNSERIALIZE_CONTAINER(free_list
);
1396 for (int idx
: free_list
)
1397 freeList
.push_back(&tlb
[idx
]);
1399 UNSERIALIZE_SCALAR(c0_tsb_ps0
);
1400 UNSERIALIZE_SCALAR(c0_tsb_ps1
);
1401 UNSERIALIZE_SCALAR(c0_config
);
1402 UNSERIALIZE_SCALAR(cx_tsb_ps0
);
1403 UNSERIALIZE_SCALAR(cx_tsb_ps1
);
1404 UNSERIALIZE_SCALAR(cx_config
);
1405 UNSERIALIZE_SCALAR(sfsr
);
1406 UNSERIALIZE_SCALAR(tag_access
);
1408 lookupTable
.clear();
1409 for (int x
= 0; x
< size
; x
++) {
1410 ScopedCheckpointSection
sec(cp
, csprintf("PTE%d", x
));
1411 tlb
[x
].unserialize(cp
);
1413 lookupTable
.insert(tlb
[x
].range
, &tlb
[x
]);
1416 UNSERIALIZE_SCALAR(sfar
);
1419 } // namespace SparcISA
1422 SparcTLBParams::create()
1424 return new SparcISA::TLB(this);