src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /*====== AXI4 Lite slave declarations =======*/
  14
  15 {3}
  16         /*===========================*/
  17         /*=== package imports ===*/
  18         import Clocks::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Connectable::*;
  22         import Vector::*;
  23         import FIFO::*;
  24         /*=======================*/
  25         /*===== Import the slow peripherals ====*/
  26 {0}
  27     `ifdef CLINT
  28         import clint::*;
  29     `endif
  30     `ifdef PLIC
  31         import plic             ::*;
  32     `endif
  33         `ifdef AXIEXP
  34                 import axiexpansion     ::*;
  35         `endif
  36         /*=====================================*/
  37
  38         /*===== interface declaration =====*/
  39         interface SP_ios;
  40 {1}
  41                 `ifdef AXIEXP
  42                         interface Get#(Bit#(67)) axiexp1_out;
  43                         interface Put#(Bit#(67)) axiexp1_in;
  44                 `endif
  45         endinterface
  46         interface Ifc_slow_peripherals;
  47                 interface AXI4_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
  48                 interface SP_ios slow_ios;
  49     method Action external_int(Bit#(32) in);
  50                 `ifdef CLINT
  51                         method Bit#(1) msip_int;
  52                         method Bit#(1) mtip_int;
  53                         method Bit#(`Reg_width) mtime;
  54                 `endif
  55                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  56     interface IOCellSide iocell_side; // mandatory interface
  57         endinterface
  58         /*================================*/
  59
  60         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  61                      fn_address_mapping (Bit#(`PADDR) addr);
  62                 `ifdef CLINT
  63                         if(addr>=`ClintBase && addr<=`ClintEnd)
  64                                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  65                         else
  66                 `endif
  67                 `ifdef PLIC
  68                         if(addr>=`PLICBase && addr<=`PLICEnd)
  69                                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  70                         else
  71                 `endif
  72                 `ifdef AXIEXP
  73                         if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  74                                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  75                         else
  76                 `endif
  77 {4}
  78                         return tuple2(False,?);
  79         endfunction
  80
  81         (*synthesize*)
  82         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  83                                Clock uart_clock, Reset uart_reset
  84   `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  85                               )(Ifc_slow_peripherals);
  86                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  87                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  88
  89                 /*======= Module declarations for each peripheral =======*/
  90 {5}
  91                 `ifdef CLINT
  92                         Ifc_clint                               clint                           <- mkclint();
  93                 `endif
  94                 `ifdef PLIC
  95                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  96          Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  97                           Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
  98                 `endif
  99                 `ifdef AXIEXP
 100                         Ifc_AxiExpansion                axiexp1                 <- mkAxiExpansion();
 101                 `endif
 102     Ifc_pinmux pinmux <- mkpinmux; // mandatory
 103     Wire#(Bit#(32)) wr_interrupt <- mkWire();
 104                 /*=======================================================*/
 105
 106         AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `Reg_width,`USERSPACE)
 107             slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 108                 Ifc_AXI4Lite_AXI4_Bridge
 109             bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 110
 111                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 112                 /*======= Slave connections to AXI4Lite fabric =========*/
 113 {6}
 114                 `ifdef CLINT
 115                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(CLINT_slave_num))],
 116                     clint.axi4_slave);
 117                 `endif
 118                 `ifdef PLIC
 119                         mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(Plic_slave_num))],
 120                     plic.axi4_slave_plic); //
 121                 `endif
 122                 `ifdef AXIEXP
 123                 mkConnection (slow_fabric.v_to_slaves [fromInteger(valueOf(AxiExp1_slave_num))],
 124                     axiexp1.axi_slave); //
 125                 `endif
 126
 127     // NEEL EDIT
 128     mkConnection (slow_fabric.
 129                   v_to_slaves[fromInteger(valueOf(Muxa_slave_num))],
 130                   muxa.axi_slave);
 131     mkConnection (slow_fabric.
 132                   v_to_slaves[fromInteger(valueOf(Gpioa_slave_num))],
 133                   gpioa.axi_slave);
 134     rule connect_select_lines_pinmux;// mandatory
 135       pinmux.mux_lines.cell0_mux(muxa.mux_config.mux[0]);
 136       pinmux.mux_lines.cell1_mux(muxa.mux_config.mux[1]);
 137       pinmux.mux_lines.cell2_mux(muxa.mux_config.mux[2]);
 138     endrule
 139     rule connect_i2c0_scl;
 140       pinmux.peripheral_side.twi_scl_out(i2c0.out.scl_out);
 141       pinmux.peripheral_side.twi_scl_outen(pack(i2c0.out.scl_out_en));
 142     endrule
 143     rule connect_i2c0_scl_in;
 144       i2c0.out.scl_in(pinmux.peripheral_side.twi_scl_in);
 145     endrule
 146     rule connect_i2c0_sda;
 147       pinmux.peripheral_side.twi_sda_out(i2c0.out.sda_out);
 148       pinmux.peripheral_side.twi_sda_outen(pack(i2c0.out.sda_out_en));
 149     endrule
 150     rule connect_i2c0_sda_in;
 151       i2c0.out.sda_in(pinmux.peripheral_side.twi_sda_in);
 152     endrule
 153     rule connect_uart1tx;
 154       pinmux.peripheral_side.uart_tx(uart1.coe_rs232.sout);
 155     endrule
 156     rule connect_uart1rx;
 157       uart1.coe_rs232.sin(pinmux.peripheral_side.uart_rx);
 158     endrule
 159     rule connect_gpioa;
 160       pinmux.peripheral_side.gpioa_a0_out(gpioa.func.gpio_out[0]);
 161       pinmux.peripheral_side.gpioa_a0_outen(gpioa.func.gpio_out_en[0]);
 162       pinmux.peripheral_side.gpioa_a1_out(gpioa.func.gpio_out[1]);
 163       pinmux.peripheral_side.gpioa_a1_outen(gpioa.func.gpio_out_en[1]);
 164       pinmux.peripheral_side.gpioa_a2_out(gpioa.func.gpio_out[2]);
 165       pinmux.peripheral_side.gpioa_a2_outen(gpioa.func.gpio_out_en[2]);
 166                 Vector#(3,Bit#(1)) temp;
 167                 temp[0]=pinmux.peripheral_side.gpioa_a0_in;
 168                 temp[1]=pinmux.peripheral_side.gpioa_a1_in;
 169                 temp[2]=pinmux.peripheral_side.gpioa_a2_in;
 170       gpioa.func.gpio_in(temp);
 171     endrule
 172     for(Integer i=0;i<32;i=i+ 1)begin
 173       rule connect_int_to_plic(wr_interrupt[i]==1);
 174                                 ff_gateway_queue[i].enq(1);
 175                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 176       endrule
 177     end
 178     rule rl_completion_msg_from_plic;
 179                   let id <- plic.intrpt_completion;
 180       interrupt_id <= id;
 181       `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 182                 endrule
 183
 184     for(Integer i=0; i <32; i=i+1) begin
 185             rule deq_gateway_queue;
 186                     if(interrupt_id==fromInteger(i)) begin
 187                             ff_gateway_queue[i].deq;
 188           `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 189         end
 190       endrule
 191     end
 192     /* for connectin inputs from pinmux as itnerrupts
 193       rule connect_pinmux_eint;
 194         wr_interrupt<= pinmux.peripheral_side.eint_input;
 195       endrule
 196     */
 197     // NEEL EDIT OVER
 198                 /*=======================================================*/
 199                 /*=================== PLIC Connections ==================== */
 200                 `ifdef PLIC_main
 201                         /*TODO DMA interrupt need to be connected to the plic
 202                         for(Integer i=1; i<8; i=i+1) begin
 203          `ifdef DMA
 204              rule rl_connect_dma_interrupts_to_plic;
 205                                         if(dma.interrupt_to_processor[i-1]==1'b1) begin
 206                                                 ff_gateway_queue[i].enq(1);
 207                                                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 208                                         end
 209              endrule
 210           `else
 211              rule rl_connect_dma_interrupts_to_plic;
 212                  ff_gateway_queue[i].enq(0);
 213              endrule
 214           `endif
 215          end
 216                         */
 217          rule rl_connect_i2c0_to_plic;
 218                                 `ifdef I2C0
 219                                         if(i2c0.isint()==1'b1) begin
 220                                                 ff_gateway_queue[8].enq(1);
 221                                                 plic.ifc_external_irq[8].irq_frm_gateway(True);
 222                                         end
 223                                 `else
 224                                         ff_gateway_queue[8].enq(0);
 225             `endif
 226          endrule
 227
 228                         rule rl_connect_i2c1_to_plic;
 229                                 `ifdef I2C1
 230                                         if(i2c1.isint()==1'b1) begin
 231                                                 ff_gateway_queue[9].enq(1);
 232                                                 plic.ifc_external_irq[9].irq_frm_gateway(True);
 233                                         end
 234             `else
 235                                         ff_gateway_queue[9].enq(0);
 236             `endif
 237                         endrule
 238
 239          rule rl_connect_i2c0_timerint_to_plic;
 240                                 `ifdef I2C0
 241                                         if(i2c0.timerint()==1'b1) begin
 242                                                 ff_gateway_queue[10].enq(1);
 243                                                 plic.ifc_external_irq[10].irq_frm_gateway(True);
 244                                         end
 245             `else
 246                                         ff_gateway_queue[10].enq(0);
 247             `endif
 248                         endrule
 249
 250          rule rl_connect_i2c1_timerint_to_plic;
 251                                 `ifdef I2C1
 252                                         if(i2c1.timerint()==1'b1) begin
 253                                                 ff_gateway_queue[11].enq(1);
 254                                                 plic.ifc_external_irq[11].irq_frm_gateway(True);
 255                                         end
 256             `else
 257                                         ff_gateway_queue[11].enq(0);
 258             `endif
 259          endrule
 260
 261          rule rl_connect_i2c0_isber_to_plic;
 262                                 `ifdef I2C0
 263                                         if(i2c0.isber()==1'b1) begin
 264                                                 ff_gateway_queue[12].enq(1);
 265                                                 plic.ifc_external_irq[12].irq_frm_gateway(True);
 266                                         end
 267             `else
 268                                         ff_gateway_queue[12].enq(0);
 269             `endif
 270          endrule
 271
 272          rule rl_connect_i2c1_isber_to_plic;
 273                                 `ifdef I2C1
 274                                         if(i2c1.isber()==1'b1) begin
 275                                                 ff_gateway_queue[13].enq(1);
 276                                                 plic.ifc_external_irq[13].irq_frm_gateway(True);
 277                end
 278             `else
 279                                         ff_gateway_queue[13].enq(0);
 280             `endif
 281          endrule
 282
 283          for(Integer i = 14; i < 20; i=i+1) begin
 284                                 rule rl_connect_qspi0_to_plic;
 285                                         `ifdef QSPI0
 286                                                 if(qspi0.interrupts()[i-14]==1'b1) begin
 287                                                         ff_gateway_queue[i].enq(1);
 288                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 289                                                 end
 290                `else
 291                                                 ff_gateway_queue[i].enq(0);
 292                `endif
 293             endrule
 294          end
 295
 296          for(Integer i = 20; i<26; i=i+1) begin
 297                                 rule rl_connect_qspi1_to_plic;
 298                                         `ifdef QSPI1
 299                                                 if(qspi1.interrupts()[i-20]==1'b1) begin
 300                                                         ff_gateway_queue[i].enq(1);
 301                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 302                                                 end
 303                `else
 304                                                 ff_gateway_queue[i].enq(0);
 305                `endif
 306             endrule
 307                         end
 308
 309                         `ifdef UART0
 310                                 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset);
 311                                 rule synchronize_the_uart0_interrupt;
 312                                         uart0_interrupt.send(uart0.irq);
 313                                 endrule
 314                         `endif
 315                         rule rl_connect_uart_to_plic;
 316                                 `ifdef UART0
 317                                         if(uart0_interrupt.read==1'b1) begin
 318                                                 ff_gateway_queue[27].enq(1);
 319                                                 plic.ifc_external_irq[27].irq_frm_gateway(True);
 320                end
 321
 322             `else
 323                                         ff_gateway_queue[27].enq(0);
 324             `endif
 325          endrule
 326
 327                         for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
 328                                 rule rl_raise_interrupts;
 329                                         if((i-28)<`IONum) begin //Peripheral interrupts
 330                                                 if(gpio.to_plic[i-28]==1'b1) begin
 331                                                         plic.ifc_external_irq[i].irq_frm_gateway(True);
 332                                                                 ff_gateway_queue[i].enq(1);
 333                   end
 334                                         end
 335                                 endrule
 336                         end
 337
 338          rule rl_completion_msg_from_plic;
 339                                 let id <- plic.intrpt_completion;
 340             interrupt_id <= id;
 341             `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
 342                         endrule
 343
 344          for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 345                                 rule deq_gateway_queue;
 346                                         if(interrupt_id==fromInteger(i)) begin
 347                                                 ff_gateway_queue[i].deq;
 348                   `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
 349                end
 350             endrule
 351          end
 352
 353
 354                 `endif
 355                         /*======================================================= */
 356
 357                 /* ===== interface definition =======*/
 358                 interface axi_slave=bridge.axi_slave;
 359                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 360                 `ifdef CLINT
 361                         method msip_int=clint.msip_int;
 362                         method mtip_int=clint.mtip_int;
 363                         method mtime=clint.mtime;
 364                 `endif
 365                 `ifdef I2C0
 366                         method i2c0_isint=i2c0.isint;
 367                 `endif
 368                 `ifdef I2C1
 369                         method i2c1_isint=i2c1.isint;
 370                 `endif
 371                 `ifdef QSPI0 method     qspi0_isint=qspi0.interrupts[5]; `endif
 372                 `ifdef QSPI1 method     qspi1_isint=qspi1.interrupts[5]; `endif
 373                 `ifdef UART0 method uart0_intr=uart0.irq; `endif
 374                 interface SP_ios slow_ios;
 375                         `ifdef UART0
 376                                 interface uart0_coe=uart0.coe_rs232;
 377                         `endif
 378                         `ifdef UART1
 379                                 interface uart1_coe=uart1.coe_rs232;
 380                         `endif
 381                         `ifdef I2C0
 382                                 interface i2c0_out=i2c0.out;
 383                         `endif
 384                         `ifdef I2C1
 385                                 interface i2c1_out=i2c1.out;
 386                         `endif
 387                         `ifdef QSPI0
 388                                 interface qspi0_out = qspi0.out;
 389                         `endif
 390                         `ifdef QSPI1
 391                                 interface qspi1_out = qspi1.out;
 392                         `endif
 393                         `ifdef AXIEXP
 394                                 interface axiexp1_out=axiexp1.slave_out;
 395                                 interface axiexp1_in=axiexp1.slave_in;
 396                         `endif
 397       `ifdef PWM_AXI4Lite
 398         interface pwm_o = pwm_bus.pwm_io;
 399       `endif
 400                 endinterface
 401     // NEEL EDIT
 402     interface iocell_side=pinmux.iocell_side;
 403     interface pad_configa= gpioa.pad_config;
 404     method Action external_int(Bit#(32) in);
 405       wr_interrupt<= in;
 406     endmethod
 407     // NEEL EDIT OVER
 408                 /*===================================*/
 409         endmodule
 410 endpackage