2 Copyright (c) 2013, IIT Madras
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
42 /*=== Project imports === */
46 import AXI4_Fabric::*;
47 import defined_types::*;
48 import MemoryMap :: *;
49 import slow_peripherals::*;
50 import fast_memory_map::*;
51 import slow_memory_map::*;
53 `include "defines.bsv"
55 `include "instance_defines.bsv"
56 `include "core_parameters.bsv"
69 import Memory_AXI4 ::*;
75 import DebugModule::*;
87 import FlexBus_Types::*;
91 /*========================= */
93 interface SP_dedicated_ios slow_ios;
94 (*always_ready,always_enabled*)
95 method Action boot_sequence(Bit#(1) bootseq);
98 (*always_ready*) interface Ifc_sdram_out sdram_out;
101 (*prefix="M_AXI"*) interface
102 AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
105 (*always_ready,always_enabled*)
106 interface Ifc_flash ifc_flash;
108 /*=============================================== */
110 interface Vme_out proc_ifc;
111 interface Data_bus_inf proc_dbus;
116 //============ mkSoc module =================
119 module mkSoc #(Bit#(`VADDR) reset_vector,
120 Clock slow_clock, Reset slow_reset, Clock uart_clock,
121 Reset uart_reset, Clock clk0, Clock tck, Reset trst
122 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
123 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
124 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
127 Ifc_DebugModule core<-mkDebugModule(reset_vector);
129 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
132 BootRom_IFC bootrom <-mkBootRom;
135 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
138 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
139 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
142 Ifc_TCM tcm <- mkTCM;
145 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
148 Ifc_vme_top vme <-mkvme_top();
150 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
151 core_clock, core_reset,
152 uart_clock, uart_reset,
153 clocked_by slow_clock, reset_by slow_reset
154 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
156 // clock sync mkConnections
160 AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
161 `PADDR, `DATA,`USERSPACE)
162 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
164 // Connect traffic generators to fabric
165 mkConnection (core.dmem_master,fabric.v_from_masters
166 [fromInteger(valueOf(Dmem_master_num))]);
167 mkConnection (core.imem_master, fabric.v_from_masters
168 [fromInteger(valueOf(Imem_master_num))]);
170 mkConnection (core.debug_master, fabric.v_from_masters
171 [fromInteger(valueOf(Debug_master_num))]);
174 mkConnection (dma.mmu, fabric.v_from_masters
175 [fromInteger(valueOf(DMA_master_num))]);
179 // Connect fabric to memory slaves
181 mkConnection (fabric.v_to_slaves
182 [fromInteger(valueOf(Debug_slave_num))],
186 mkConnection (fabric.v_to_slaves
187 [fromInteger(valueOf(Sdram_slave_num))],
188 sdram.axi4_slave_sdram); //
189 mkConnection (fabric.v_to_slaves
190 [fromInteger(valueOf(Sdram_cfg_slave_num))],
191 sdram.axi4_slave_cntrl_reg); //
194 mkConnection(fabric.v_to_slaves
195 [fromInteger(valueOf(Sdram_slave_num))],
196 main_memory.axi_slave);
199 mkConnection (fabric.v_to_slaves
200 [fromInteger(valueOf(BootRom_slave_num))],
204 mkConnection (fabric.v_to_slaves
205 [fromInteger(valueOf(Dma_slave_num))],
206 dma.cfg); //DMA slave
209 mkConnection (fabric.v_to_slaves
210 [fromInteger(valueOf(TCM_slave_num))],
213 mkConnection(fabric.v_to_slaves
214 [fromInteger(valueOf(SlowPeripheral_slave_num))],
215 slow_peripherals.axi_slave);
217 mkConnection (fabric.v_to_slaves
218 [fromInteger(valueOf(VME_slave_num))],
225 // fabric connections
229 // rule to connect all interrupt lines to the DMA
230 // All the interrupt lines to DMA are active
231 // HIGH. For peripherals that are not connected,
232 // or those which do not
233 // generate an interrupt (like TCM), drive a constant 1
234 // on the corresponding interrupt line.
239 /*==== Synchornization between the JTAG and the Debug Module ===== */
241 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
242 mkSyncFIFOToCC(1,tck,trst);
243 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
244 mkSyncFIFOFromCC(1,tck);
245 rule connect_tap_request_to_syncfifo;
246 let x<-tap.request_to_dm;
247 sync_request_to_dm.enq(x);
249 rule read_synced_request_to_dm;
250 sync_request_to_dm.deq;
251 core.request_from_dtm(sync_request_to_dm.first);
254 rule connect_debug_response_to_syncfifo;
255 let x<-core.response_to_dtm;
256 sync_response_from_dm.enq(x);
258 rule read_synced_response_from_dm;
259 sync_response_from_dm.deq;
260 tap.response_from_dm(sync_response_from_dm.first);
263 /*============================================================ */
266 //rule drive_flexbus_inputs;
267 //flexbus.flexbus_side.m_TAn(1'b1);
268 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
273 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
274 mkSyncBitToCC(slow_clock,slow_reset);
275 SyncBitIfc#(Bit#(1)) clint_msip_int <-
276 mkSyncBitToCC(slow_clock,slow_reset);
277 Reg#(Bit#(`DATA)) clint_mtime_value <-
278 mkSyncRegToCC(0,slow_clock,slow_reset);
279 rule synchronize_clint_data;
280 clint_mtip_int.send(slow_peripherals.mtip_int);
281 clint_msip_int.send(slow_peripherals.msip_int);
282 clint_mtime_value<=slow_peripherals.mtime;
284 rule connect_msip_mtip_from_clint;
285 core.clint_msip(clint_msip_int.read);
286 core.clint_mtip(clint_mtip_int.read);
287 core.clint_mtime(clint_mtime_value);
291 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
292 mkSyncRegToCC(tuple2(False,False),
293 slow_clock,slow_reset);
294 rule synchronize_interrupts;
295 let note <- slow_peripherals.intrpt_note;
296 plic_interrupt_note<=note;
298 rule rl_send_external_interrupt_to_csr;
299 core.set_external_interrupt(plic_interrupt_note);
304 interface proc_ifc = vme.proc_ifc;
305 interface proc_dbus = vme.proc_dbus;
307 method Action boot_sequence(Bit#(1) bootseq) =
308 core.boot_sequence(bootseq);
310 interface sdram_out=sdram.ifc_sdram_out;
313 interface master=fabric.v_to_slaves
314 [fromInteger(valueOf(Sdram_slave_num))];
316 interface slow_ios = slow_peripherals.slow_ios;
317 interface iocell_side = slow_peripherals.iocell_side;